1 /* Definitions of target machine for GNU compiler, for DEC Alpha.
2 Copyright (C) 1992, 93-99, 2000 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 /* Write out the correct language type definition for the header files.
24 Unless we have assembler language, write out the symbols for C. */
27 %{.S:-D__LANGUAGE_ASSEMBLY__ -D__LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY }}\
28 %{.cc|.cxx|.C:-D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS -D__cplusplus }\
29 %{.m:-D__LANGUAGE_OBJECTIVE_C__ -D__LANGUAGE_OBJECTIVE_C }\
30 %{!.S:%{!.cc:%{!.cxx:%{!.C:%{!.m:-D__LANGUAGE_C__ -D__LANGUAGE_C %{!ansi:-DLANGUAGE_C }}}}}}\
32 %{mieee-with-inexact:-D_IEEE_FP -D_IEEE_FP_INEXACT }}\
33 %(cpp_cpu) %(cpp_subtarget)"
35 #ifndef CPP_SUBTARGET_SPEC
36 #define CPP_SUBTARGET_SPEC ""
39 /* Set the spec to use for signed char. The default tests the above macro
40 but DEC's compiler can't handle the conditional in a "constant"
43 #define SIGNED_CHAR_SPEC "%{funsigned-char:-D__CHAR_UNSIGNED__}"
45 #define WORD_SWITCH_TAKES_ARG(STR) \
46 (!strcmp (STR, "rpath") || !strcmp (STR, "include") \
47 || !strcmp (STR, "imacros") || !strcmp (STR, "aux-info") \
48 || !strcmp (STR, "idirafter") || !strcmp (STR, "iprefix") \
49 || !strcmp (STR, "iwithprefix") || !strcmp (STR, "iwithprefixbefore") \
50 || !strcmp (STR, "isystem"))
52 /* Print subsidiary information on the compiler version in use. */
53 #define TARGET_VERSION
55 /* Run-time compilation parameters selecting different hardware subsets. */
57 /* Which processor to schedule for. The cpu attribute defines a list that
58 mirrors this list, so changes to alpha.md must be made at the same time. */
61 {PROCESSOR_EV4
, /* 2106[46]{a,} */
62 PROCESSOR_EV5
, /* 21164{a,pc,} */
63 PROCESSOR_EV6
}; /* 21264 */
65 extern enum processor_type alpha_cpu
;
67 enum alpha_trap_precision
69 ALPHA_TP_PROG
, /* No precision (default). */
70 ALPHA_TP_FUNC
, /* Trap contained within originating function. */
71 ALPHA_TP_INSN
/* Instruction accuracy and code is resumption safe. */
74 enum alpha_fp_rounding_mode
76 ALPHA_FPRM_NORM
, /* Normal rounding mode. */
77 ALPHA_FPRM_MINF
, /* Round towards minus-infinity. */
78 ALPHA_FPRM_CHOP
, /* Chopped rounding mode (towards 0). */
79 ALPHA_FPRM_DYN
/* Dynamic rounding mode. */
82 enum alpha_fp_trap_mode
84 ALPHA_FPTM_N
, /* Normal trap mode. */
85 ALPHA_FPTM_U
, /* Underflow traps enabled. */
86 ALPHA_FPTM_SU
, /* Software completion, w/underflow traps */
87 ALPHA_FPTM_SUI
/* Software completion, w/underflow & inexact traps */
90 extern int target_flags
;
92 extern enum alpha_trap_precision alpha_tp
;
93 extern enum alpha_fp_rounding_mode alpha_fprm
;
94 extern enum alpha_fp_trap_mode alpha_fptm
;
96 /* This means that floating-point support exists in the target implementation
97 of the Alpha architecture. This is usually the default. */
98 #define MASK_FP (1 << 0)
99 #define TARGET_FP (target_flags & MASK_FP)
101 /* This means that floating-point registers are allowed to be used. Note
102 that Alpha implementations without FP operations are required to
103 provide the FP registers. */
105 #define MASK_FPREGS (1 << 1)
106 #define TARGET_FPREGS (target_flags & MASK_FPREGS)
108 /* This means that gas is used to process the assembler file. */
110 #define MASK_GAS (1 << 2)
111 #define TARGET_GAS (target_flags & MASK_GAS)
113 /* This means that we should mark procedures as IEEE conformant. */
115 #define MASK_IEEE_CONFORMANT (1 << 3)
116 #define TARGET_IEEE_CONFORMANT (target_flags & MASK_IEEE_CONFORMANT)
118 /* This means we should be IEEE-compliant except for inexact. */
120 #define MASK_IEEE (1 << 4)
121 #define TARGET_IEEE (target_flags & MASK_IEEE)
123 /* This means we should be fully IEEE-compliant. */
125 #define MASK_IEEE_WITH_INEXACT (1 << 5)
126 #define TARGET_IEEE_WITH_INEXACT (target_flags & MASK_IEEE_WITH_INEXACT)
128 /* This means we must construct all constants rather than emitting
129 them as literal data. */
131 #define MASK_BUILD_CONSTANTS (1 << 6)
132 #define TARGET_BUILD_CONSTANTS (target_flags & MASK_BUILD_CONSTANTS)
134 /* This means we handle floating points in VAX F- (float)
135 or G- (double) Format. */
137 #define MASK_FLOAT_VAX (1 << 7)
138 #define TARGET_FLOAT_VAX (target_flags & MASK_FLOAT_VAX)
140 /* This means that the processor has byte and half word loads and stores
141 (the BWX extension). */
143 #define MASK_BWX (1 << 8)
144 #define TARGET_BWX (target_flags & MASK_BWX)
146 /* This means that the processor has the MAX extension. */
147 #define MASK_MAX (1 << 9)
148 #define TARGET_MAX (target_flags & MASK_MAX)
150 /* This means that the processor has the FIX extension. */
151 #define MASK_FIX (1 << 10)
152 #define TARGET_FIX (target_flags & MASK_FIX)
154 /* This means that the processor has the CIX extension. */
155 #define MASK_CIX (1 << 11)
156 #define TARGET_CIX (target_flags & MASK_CIX)
158 /* This means that the processor is an EV5, EV56, or PCA56. This is defined
159 only in TARGET_CPU_DEFAULT. */
160 #define MASK_CPU_EV5 (1 << 28)
162 /* Likewise for EV6. */
163 #define MASK_CPU_EV6 (1 << 29)
165 /* This means we support the .arch directive in the assembler. Only
166 defined in TARGET_CPU_DEFAULT. */
167 #define MASK_SUPPORT_ARCH (1 << 30)
168 #define TARGET_SUPPORT_ARCH (target_flags & MASK_SUPPORT_ARCH)
170 /* These are for target os support and cannot be changed at runtime. */
171 #ifndef TARGET_WINDOWS_NT
172 #define TARGET_WINDOWS_NT 0
174 #ifndef TARGET_OPEN_VMS
175 #define TARGET_OPEN_VMS 0
178 #ifndef TARGET_AS_CAN_SUBTRACT_LABELS
179 #define TARGET_AS_CAN_SUBTRACT_LABELS TARGET_GAS
181 #ifndef TARGET_CAN_FAULT_IN_PROLOGUE
182 #define TARGET_CAN_FAULT_IN_PROLOGUE 0
184 #ifndef TARGET_HAS_XFLOATING_LIBS
185 #define TARGET_HAS_XFLOATING_LIBS 0
188 /* Macro to define tables used to set the flags.
189 This is a list in braces of pairs in braces,
190 each pair being { "NAME", VALUE }
191 where VALUE is the bits to set or minus the bits to clear.
192 An empty string NAME is used to identify the default VALUE. */
194 #define TARGET_SWITCHES \
195 { {"no-soft-float", MASK_FP, "Use hardware fp"}, \
196 {"soft-float", - MASK_FP, "Do not use hardware fp"}, \
197 {"fp-regs", MASK_FPREGS, "Use fp registers"}, \
198 {"no-fp-regs", - (MASK_FP|MASK_FPREGS), "Do not use fp registers"}, \
199 {"alpha-as", -MASK_GAS, "Do not assume GAS"}, \
200 {"gas", MASK_GAS, "Assume GAS"}, \
201 {"ieee-conformant", MASK_IEEE_CONFORMANT, \
202 "Request IEEE-conformant math library routines (OSF/1)"}, \
203 {"ieee", MASK_IEEE|MASK_IEEE_CONFORMANT, \
204 "Emit IEEE-conformant code, without inexact exceptions"}, \
205 {"ieee-with-inexact", MASK_IEEE_WITH_INEXACT|MASK_IEEE_CONFORMANT, \
206 "Emit IEEE-conformant code, with inexact exceptions"}, \
207 {"build-constants", MASK_BUILD_CONSTANTS, \
208 "Do not emit complex integer constants to read-only memory"}, \
209 {"float-vax", MASK_FLOAT_VAX, "Use VAX fp"}, \
210 {"float-ieee", -MASK_FLOAT_VAX, "Do not use VAX fp"}, \
211 {"bwx", MASK_BWX, "Emit code for the byte/word ISA extension"}, \
212 {"no-bwx", -MASK_BWX, ""}, \
213 {"max", MASK_MAX, "Emit code for the motion video ISA extension"}, \
214 {"no-max", -MASK_MAX, ""}, \
215 {"fix", MASK_FIX, "Emit code for the fp move and sqrt ISA extension"}, \
216 {"no-fix", -MASK_FIX, ""}, \
217 {"cix", MASK_CIX, "Emit code for the counting ISA extension"}, \
218 {"no-cix", -MASK_CIX, ""}, \
219 {"", TARGET_DEFAULT | TARGET_CPU_DEFAULT, ""} }
221 #define TARGET_DEFAULT MASK_FP|MASK_FPREGS
223 #ifndef TARGET_CPU_DEFAULT
224 #define TARGET_CPU_DEFAULT 0
227 /* This macro is similar to `TARGET_SWITCHES' but defines names of
228 command options that have values. Its definition is an initializer
229 with a subgrouping for each command option.
231 Each subgrouping contains a string constant, that defines the fixed
232 part of the option name, and the address of a variable. The
233 variable, type `char *', is set to the variable part of the given
234 option if the fixed part matches. The actual option name is made
235 by appending `-m' to the specified name.
237 Here is an example which defines `-mshort-data-NUMBER'. If the
238 given option is `-mshort-data-512', the variable `m88k_short_data'
239 will be set to the string `"512"'.
241 extern char *m88k_short_data;
242 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
244 extern const char *alpha_cpu_string
; /* For -mcpu= */
245 extern const char *alpha_fprm_string
; /* For -mfp-rounding-mode=[n|m|c|d] */
246 extern const char *alpha_fptm_string
; /* For -mfp-trap-mode=[n|u|su|sui] */
247 extern const char *alpha_tp_string
; /* For -mtrap-precision=[p|f|i] */
248 extern const char *alpha_mlat_string
; /* For -mmemory-latency= */
250 #define TARGET_OPTIONS \
252 {"cpu=", &alpha_cpu_string, \
253 "Generate code for a given CPU"}, \
254 {"fp-rounding-mode=", &alpha_fprm_string, \
255 "Control the generated fp rounding mode"}, \
256 {"fp-trap-mode=", &alpha_fptm_string, \
257 "Control the IEEE trap mode"}, \
258 {"trap-precision=", &alpha_tp_string, \
259 "Control the precision given to fp exceptions"}, \
260 {"memory-latency=", &alpha_mlat_string, \
261 "Tune expected memory latency"}, \
264 /* Attempt to describe CPU characteristics to the preprocessor. */
266 /* Corresponding to amask... */
267 #define CPP_AM_BWX_SPEC "-D__alpha_bwx__ -Acpu(bwx)"
268 #define CPP_AM_MAX_SPEC "-D__alpha_max__ -Acpu(max)"
269 #define CPP_AM_FIX_SPEC "-D__alpha_fix__ -Acpu(fix)"
270 #define CPP_AM_CIX_SPEC "-D__alpha_cix__ -Acpu(cix)"
272 /* Corresponding to implver... */
273 #define CPP_IM_EV4_SPEC "-D__alpha_ev4__ -Acpu(ev4)"
274 #define CPP_IM_EV5_SPEC "-D__alpha_ev5__ -Acpu(ev5)"
275 #define CPP_IM_EV6_SPEC "-D__alpha_ev6__ -Acpu(ev6)"
277 /* Common combinations. */
278 #define CPP_CPU_EV4_SPEC "%(cpp_im_ev4)"
279 #define CPP_CPU_EV5_SPEC "%(cpp_im_ev5)"
280 #define CPP_CPU_EV56_SPEC "%(cpp_im_ev5) %(cpp_am_bwx)"
281 #define CPP_CPU_PCA56_SPEC "%(cpp_im_ev5) %(cpp_am_bwx) %(cpp_am_max)"
282 #define CPP_CPU_EV6_SPEC \
283 "%(cpp_im_ev6) %(cpp_am_bwx) %(cpp_am_max) %(cpp_am_fix)"
284 #define CPP_CPU_EV67_SPEC \
285 "%(cpp_im_ev6) %(cpp_am_bwx) %(cpp_am_max) %(cpp_am_fix) %(cpp_am_cix)"
287 #ifndef CPP_CPU_DEFAULT_SPEC
288 # if TARGET_CPU_DEFAULT & MASK_CPU_EV6
289 # if TARGET_CPU_DEFAULT & MAX_CIX
290 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV67_SPEC
292 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV6_SPEC
295 # if TARGET_CPU_DEFAULT & MASK_CPU_EV5
296 # if TARGET_CPU_DEFAULT & MASK_MAX
297 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_PCA56_SPEC
299 # if TARGET_CPU_DEFAULT & MASK_BWX
300 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV56_SPEC
302 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV5_SPEC
306 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV4_SPEC
309 #endif /* CPP_CPU_DEFAULT_SPEC */
312 #define CPP_CPU_SPEC "\
313 %{!undef:-Acpu(alpha) -Amachine(alpha) -D__alpha -D__alpha__ \
314 %{mcpu=ev4|mcpu=21064:%(cpp_cpu_ev4) }\
315 %{mcpu=ev5|mcpu=21164:%(cpp_cpu_ev5) }\
316 %{mcpu=ev56|mcpu=21164a:%(cpp_cpu_ev56) }\
317 %{mcpu=pca56|mcpu=21164pc|mcpu=21164PC:%(cpp_cpu_pca56) }\
318 %{mcpu=ev6|mcpu=21264:%(cpp_cpu_ev6) }\
319 %{mcpu=ev67|mcpu=21264a:%(cpp_cpu_ev67) }\
320 %{!mcpu*:%(cpp_cpu_default) }}"
323 /* This macro defines names of additional specifications to put in the
324 specs that can be used in various specifications like CC1_SPEC. Its
325 definition is an initializer with a subgrouping for each command option.
327 Each subgrouping contains a string constant, that defines the
328 specification name, and a string constant that used by the GNU CC driver
331 Do not define this macro if it does not need to do anything. */
333 #ifndef SUBTARGET_EXTRA_SPECS
334 #define SUBTARGET_EXTRA_SPECS
337 #define EXTRA_SPECS \
338 { "cpp_am_bwx", CPP_AM_BWX_SPEC }, \
339 { "cpp_am_max", CPP_AM_MAX_SPEC }, \
340 { "cpp_am_fix", CPP_AM_FIX_SPEC }, \
341 { "cpp_am_cix", CPP_AM_CIX_SPEC }, \
342 { "cpp_im_ev4", CPP_IM_EV4_SPEC }, \
343 { "cpp_im_ev5", CPP_IM_EV5_SPEC }, \
344 { "cpp_im_ev6", CPP_IM_EV6_SPEC }, \
345 { "cpp_cpu_ev4", CPP_CPU_EV4_SPEC }, \
346 { "cpp_cpu_ev5", CPP_CPU_EV5_SPEC }, \
347 { "cpp_cpu_ev56", CPP_CPU_EV56_SPEC }, \
348 { "cpp_cpu_pca56", CPP_CPU_PCA56_SPEC }, \
349 { "cpp_cpu_ev6", CPP_CPU_EV6_SPEC }, \
350 { "cpp_cpu_ev67", CPP_CPU_EV67_SPEC }, \
351 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
352 { "cpp_cpu", CPP_CPU_SPEC }, \
353 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \
354 SUBTARGET_EXTRA_SPECS
357 /* Sometimes certain combinations of command options do not make sense
358 on a particular target machine. You can define a macro
359 `OVERRIDE_OPTIONS' to take account of this. This macro, if
360 defined, is executed once just after all the command options have
363 On the Alpha, it is used to translate target-option strings into
366 #define OVERRIDE_OPTIONS override_options ()
369 /* Define this macro to change register usage conditional on target flags.
371 On the Alpha, we use this to disable the floating-point registers when
374 #define CONDITIONAL_REGISTER_USAGE \
375 if (! TARGET_FPREGS) \
376 for (i = 32; i < 63; i++) \
377 fixed_regs[i] = call_used_regs[i] = 1;
379 /* Show we can debug even without a frame pointer. */
380 #define CAN_DEBUG_WITHOUT_FP
382 /* target machine storage layout */
384 /* Define to enable software floating point emulation. */
385 #define REAL_ARITHMETIC
387 /* The following #defines are used when compiling the routines in
388 libgcc1.c. Since the Alpha calling conventions require single
389 precision floats to be passed in the floating-point registers
390 (rather than in the general registers) we have to build the
391 libgcc1.c routines in such a way that they know the actual types
392 of their formal arguments and the actual types of their return
393 values. Otherwise, gcc will generate calls to the libgcc1.c
394 routines, passing arguments in the floating-point registers,
395 but the libgcc1.c routines will expect their arguments on the
396 stack (where the Alpha calling conventions require structs &
397 unions to be passed). */
399 #define FLOAT_VALUE_TYPE double
400 #define INTIFY(FLOATVAL) (FLOATVAL)
401 #define FLOATIFY(INTVAL) (INTVAL)
402 #define FLOAT_ARG_TYPE double
404 /* Define the size of `int'. The default is the same as the word size. */
405 #define INT_TYPE_SIZE 32
407 /* Define the size of `long long'. The default is the twice the word size. */
408 #define LONG_LONG_TYPE_SIZE 64
410 /* The two floating-point formats we support are S-floating, which is
411 4 bytes, and T-floating, which is 8 bytes. `float' is S and `double'
412 and `long double' are T. */
414 #define FLOAT_TYPE_SIZE 32
415 #define DOUBLE_TYPE_SIZE 64
416 #define LONG_DOUBLE_TYPE_SIZE 64
418 #define WCHAR_TYPE "unsigned int"
419 #define WCHAR_TYPE_SIZE 32
421 /* Define this macro if it is advisable to hold scalars in registers
422 in a wider mode than that declared by the program. In such cases,
423 the value is constrained to be within the bounds of the declared
424 type, but kept valid in the wider mode. The signedness of the
425 extension may differ from that of the type.
427 For Alpha, we always store objects in a full register. 32-bit objects
428 are always sign-extended, but smaller objects retain their signedness. */
430 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
431 if (GET_MODE_CLASS (MODE) == MODE_INT \
432 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
434 if ((MODE) == SImode) \
439 /* Define this if function arguments should also be promoted using the above
442 #define PROMOTE_FUNCTION_ARGS
444 /* Likewise, if the function return value is promoted. */
446 #define PROMOTE_FUNCTION_RETURN
448 /* Define this if most significant bit is lowest numbered
449 in instructions that operate on numbered bit-fields.
451 There are no such instructions on the Alpha, but the documentation
453 #define BITS_BIG_ENDIAN 0
455 /* Define this if most significant byte of a word is the lowest numbered.
456 This is false on the Alpha. */
457 #define BYTES_BIG_ENDIAN 0
459 /* Define this if most significant word of a multiword number is lowest
462 For Alpha we can decide arbitrarily since there are no machine instructions
463 for them. Might as well be consistent with bytes. */
464 #define WORDS_BIG_ENDIAN 0
466 /* number of bits in an addressable storage unit */
467 #define BITS_PER_UNIT 8
469 /* Width in bits of a "word", which is the contents of a machine register.
470 Note that this is not necessarily the width of data type `int';
471 if using 16-bit ints on a 68000, this would still be 32.
472 But on a machine with 16-bit registers, this would be 16. */
473 #define BITS_PER_WORD 64
475 /* Width of a word, in units (bytes). */
476 #define UNITS_PER_WORD 8
478 /* Width in bits of a pointer.
479 See also the macro `Pmode' defined below. */
480 #define POINTER_SIZE 64
482 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
483 #define PARM_BOUNDARY 64
485 /* Boundary (in *bits*) on which stack pointer should be aligned. */
486 #define STACK_BOUNDARY 64
488 /* Allocation boundary (in *bits*) for the code of a function. */
489 #define FUNCTION_BOUNDARY 256
491 /* Alignment of field after `int : 0' in a structure. */
492 #define EMPTY_FIELD_BOUNDARY 64
494 /* Every structure's size must be a multiple of this. */
495 #define STRUCTURE_SIZE_BOUNDARY 8
497 /* A bitfield declared as `int' forces `int' alignment for the struct. */
498 #define PCC_BITFIELD_TYPE_MATTERS 1
500 /* Align loop starts for optimal branching.
502 ??? Kludge this and the next macro for the moment by not doing anything if
503 we don't optimize and also if we are writing ECOFF symbols to work around
504 a bug in DEC's assembler. */
506 #define LOOP_ALIGN(LABEL) \
507 (optimize > 0 && write_symbols != SDB_DEBUG ? 4 : 0)
509 /* This is how to align an instruction for optimal branching. On
510 Alpha we'll get better performance by aligning on an octaword
513 #define LABEL_ALIGN_AFTER_BARRIER(FILE) \
514 (optimize > 0 && write_symbols != SDB_DEBUG ? 4 : 0)
516 /* No data type wants to be aligned rounder than this. */
517 #define BIGGEST_ALIGNMENT 128
519 /* For atomic access to objects, must have at least 32-bit alignment
520 unless the machine has byte operations. */
521 #define MINIMUM_ATOMIC_ALIGNMENT (TARGET_BWX ? 8 : 32)
523 /* Align all constants and variables to at least a word boundary so
524 we can pick up pieces of them faster. */
525 /* ??? Only if block-move stuff knows about different source/destination
528 #define CONSTANT_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD)
529 #define DATA_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD)
532 /* Set this non-zero if move instructions will actually fail to work
533 when given unaligned data.
535 Since we get an error message when we do one, call them invalid. */
537 #define STRICT_ALIGNMENT 1
539 /* Set this non-zero if unaligned move instructions are extremely slow.
541 On the Alpha, they trap. */
543 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
545 /* Standard register usage. */
547 /* Number of actual hardware registers.
548 The hardware registers are assigned numbers for the compiler
549 from 0 to just below FIRST_PSEUDO_REGISTER.
550 All registers that the compiler knows about must be given numbers,
551 even those that are not normally considered general registers.
553 We define all 32 integer registers, even though $31 is always zero,
554 and all 32 floating-point registers, even though $f31 is also
555 always zero. We do not bother defining the FP status register and
556 there are no other registers.
558 Since $31 is always zero, we will use register number 31 as the
559 argument pointer. It will never appear in the generated code
560 because we will always be eliminating it in favor of the stack
561 pointer or hardware frame pointer.
563 Likewise, we use $f31 for the frame pointer, which will always
564 be eliminated in favor of the hardware frame pointer or the
567 #define FIRST_PSEUDO_REGISTER 64
569 /* 1 for registers that have pervasive standard uses
570 and are not available for the register allocator. */
572 #define FIXED_REGISTERS \
573 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
574 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
575 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
576 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 }
578 /* 1 for registers not available across function calls.
579 These must include the FIXED_REGISTERS and also any
580 registers that can be used without being saved.
581 The latter must include the registers where values are returned
582 and the register where structure-value addresses are passed.
583 Aside from that, you can include as many other registers as you like. */
584 #define CALL_USED_REGISTERS \
585 {1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
586 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, \
587 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \
588 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }
590 /* List the order in which to allocate registers. Each register must be
591 listed once, even those in FIXED_REGISTERS.
593 We allocate in the following order:
594 $f10-$f15 (nonsaved floating-point register)
596 $f21-$f16 (likewise, but input args)
597 $f0 (nonsaved, but return value)
598 $f1 (nonsaved, but immediate before saved)
599 $f2-$f9 (saved floating-point registers)
600 $1-$8 (nonsaved integer registers)
603 $0 (likewise, but return value)
604 $21-$16 (likewise, but input args)
605 $27 (procedure value in OSF, nonsaved in NT)
606 $9-$14 (saved integer registers)
610 $30, $31, $f31 (stack pointer and always zero/ap & fp) */
612 #define REG_ALLOC_ORDER \
613 {42, 43, 44, 45, 46, 47, \
614 54, 55, 56, 57, 58, 59, 60, 61, 62, \
615 53, 52, 51, 50, 49, 48, \
617 34, 35, 36, 37, 38, 39, 40, 41, \
618 1, 2, 3, 4, 5, 6, 7, 8, \
622 21, 20, 19, 18, 17, 16, \
624 9, 10, 11, 12, 13, 14, \
630 /* Return number of consecutive hard regs needed starting at reg REGNO
631 to hold something of mode MODE.
632 This is ordinarily the length in words of a value of mode MODE
633 but can be less for certain modes in special long registers. */
635 #define HARD_REGNO_NREGS(REGNO, MODE) \
636 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
638 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
639 On Alpha, the integer registers can hold any mode. The floating-point
640 registers can hold 32-bit and 64-bit integers as well, but not 16-bit
643 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
644 ((REGNO) >= 32 && (REGNO) <= 62 \
645 ? GET_MODE_UNIT_SIZE (MODE) == 8 || GET_MODE_UNIT_SIZE (MODE) == 4 \
648 /* A C expression that is nonzero if a value of mode
649 MODE1 is accessible in mode MODE2 without copying.
651 This asymmetric test is true when MODE1 could be put
652 in an FP register but MODE2 could not. */
654 #define MODES_TIEABLE_P(MODE1, MODE2) \
655 (HARD_REGNO_MODE_OK (32, (MODE1)) \
656 ? HARD_REGNO_MODE_OK (32, (MODE2)) \
659 /* Specify the registers used for certain standard purposes.
660 The values of these macros are register numbers. */
662 /* Alpha pc isn't overloaded on a register that the compiler knows about. */
663 /* #define PC_REGNUM */
665 /* Register to use for pushing function arguments. */
666 #define STACK_POINTER_REGNUM 30
668 /* Base register for access to local variables of the function. */
669 #define HARD_FRAME_POINTER_REGNUM 15
671 /* Value should be nonzero if functions must have frame pointers.
672 Zero means the frame pointer need not be set up (and parms
673 may be accessed via the stack pointer) in functions that seem suitable.
674 This is computed in `reload', in reload1.c. */
675 #define FRAME_POINTER_REQUIRED 0
677 /* Base register for access to arguments of the function. */
678 #define ARG_POINTER_REGNUM 31
680 /* Base register for access to local variables of function. */
681 #define FRAME_POINTER_REGNUM 63
683 /* Register in which static-chain is passed to a function.
685 For the Alpha, this is based on an example; the calling sequence
686 doesn't seem to specify this. */
687 #define STATIC_CHAIN_REGNUM 1
689 /* Register in which address to store a structure value
690 arrives in the function. On the Alpha, the address is passed
691 as a hidden argument. */
692 #define STRUCT_VALUE 0
694 /* Define the classes of registers for register constraints in the
695 machine description. Also define ranges of constants.
697 One of the classes must always be named ALL_REGS and include all hard regs.
698 If there is more than one class, another class must be named NO_REGS
699 and contain no registers.
701 The name GENERAL_REGS must be the name of a class (or an alias for
702 another name such as ALL_REGS). This is the class of registers
703 that is allowed by "g" or "r" in a register constraint.
704 Also, registers outside this class are allocated only when
705 instructions express preferences for them.
707 The classes must be numbered in nondecreasing order; that is,
708 a larger-numbered class must never be contained completely
709 in a smaller-numbered class.
711 For any two classes, it is very desirable that there be another
712 class that represents their union. */
714 enum reg_class
{ NO_REGS
, GENERAL_REGS
, FLOAT_REGS
, ALL_REGS
,
717 #define N_REG_CLASSES (int) LIM_REG_CLASSES
719 /* Give names of register classes as strings for dump file. */
721 #define REG_CLASS_NAMES \
722 {"NO_REGS", "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS" }
724 /* Define which registers fit in which classes.
725 This is an initializer for a vector of HARD_REG_SET
726 of length N_REG_CLASSES. */
728 #define REG_CLASS_CONTENTS \
729 { {0, 0}, {~0, 0x80000000}, {0, 0x7fffffff}, {~0, ~0} }
731 /* The same information, inverted:
732 Return the class number of the smallest class containing
733 reg number REGNO. This could be a conditional expression
734 or could index an array. */
736 #define REGNO_REG_CLASS(REGNO) \
737 ((REGNO) >= 32 && (REGNO) <= 62 ? FLOAT_REGS : GENERAL_REGS)
739 /* The class value for index registers, and the one for base regs. */
740 #define INDEX_REG_CLASS NO_REGS
741 #define BASE_REG_CLASS GENERAL_REGS
743 /* Get reg_class from a letter such as appears in the machine description. */
745 #define REG_CLASS_FROM_LETTER(C) \
746 ((C) == 'f' ? FLOAT_REGS : NO_REGS)
748 /* Define this macro to change register usage conditional on target flags. */
749 /* #define CONDITIONAL_REGISTER_USAGE */
751 /* The letters I, J, K, L, M, N, O, and P in a register constraint string
752 can be used to stand for particular ranges of immediate operands.
753 This macro defines what the ranges are.
754 C is the letter, and VALUE is a constant value.
755 Return 1 if VALUE is in the range specified by C.
758 `I' is used for the range of constants most insns can contain.
759 `J' is the constant zero.
760 `K' is used for the constant in an LDA insn.
761 `L' is used for the constant in a LDAH insn.
762 `M' is used for the constants that can be AND'ed with using a ZAP insn.
763 `N' is used for complemented 8-bit constants.
764 `O' is used for negated 8-bit constants.
765 `P' is used for the constants 1, 2 and 3. */
767 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
768 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VALUE) < 0x100 \
769 : (C) == 'J' ? (VALUE) == 0 \
770 : (C) == 'K' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \
771 : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \
772 && (((VALUE)) >> 31 == -1 || (VALUE) >> 31 == 0)) \
773 : (C) == 'M' ? zap_mask (VALUE) \
774 : (C) == 'N' ? (unsigned HOST_WIDE_INT) (~ (VALUE)) < 0x100 \
775 : (C) == 'O' ? (unsigned HOST_WIDE_INT) (- (VALUE)) < 0x100 \
776 : (C) == 'P' ? (VALUE) == 1 || (VALUE) == 2 || (VALUE) == 3 \
779 /* Similar, but for floating or large integer constants, and defining letters
780 G and H. Here VALUE is the CONST_DOUBLE rtx itself.
782 For Alpha, `G' is the floating-point constant zero. `H' is a CONST_DOUBLE
783 that is the operand of a ZAP insn. */
785 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
786 ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT \
787 && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) \
788 : (C) == 'H' ? (GET_MODE (VALUE) == VOIDmode \
789 && zap_mask (CONST_DOUBLE_LOW (VALUE)) \
790 && zap_mask (CONST_DOUBLE_HIGH (VALUE))) \
793 /* Optional extra constraints for this machine.
795 For the Alpha, `Q' means that this is a memory operand but not a
796 reference to an unaligned location.
798 `R' is a SYMBOL_REF that has SYMBOL_REF_FLAG set or is the current
801 'S' is a 6-bit constant (valid for a shift insn). */
803 #define EXTRA_CONSTRAINT(OP, C) \
804 ((C) == 'Q' ? normal_memory_operand (OP, VOIDmode) \
805 : (C) == 'R' ? current_file_function_operand (OP, Pmode) \
806 : (C) == 'S' ? (GET_CODE (OP) == CONST_INT \
807 && (unsigned HOST_WIDE_INT) INTVAL (OP) < 64) \
810 /* Given an rtx X being reloaded into a reg required to be
811 in class CLASS, return the class of reg to actually use.
812 In general this is just CLASS; but on some machines
813 in some cases it is preferable to use a more restrictive class.
815 On the Alpha, all constants except zero go into a floating-point
816 register via memory. */
818 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
819 (CONSTANT_P (X) && (X) != const0_rtx && (X) != CONST0_RTX (GET_MODE (X)) \
820 ? ((CLASS) == FLOAT_REGS || (CLASS) == NO_REGS ? NO_REGS : GENERAL_REGS)\
823 /* Loading and storing HImode or QImode values to and from memory
824 usually requires a scratch register. The exceptions are loading
825 QImode and HImode from an aligned address to a general register
826 unless byte instructions are permitted.
827 We also cannot load an unaligned address or a paradoxical SUBREG into an
830 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \
831 secondary_reload_class((CLASS), (MODE), (IN), 1)
833 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,OUT) \
834 secondary_reload_class((CLASS), (MODE), (OUT), 0)
836 /* If we are copying between general and FP registers, we need a memory
837 location unless the FIX extension is available. */
839 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
840 (! TARGET_FIX && (CLASS1) != (CLASS2))
842 /* Specify the mode to be used for memory when a secondary memory
843 location is needed. If MODE is floating-point, use it. Otherwise,
844 widen to a word like the default. This is needed because we always
845 store integers in FP registers in quadword format. This whole
846 area is very tricky! */
847 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
848 (GET_MODE_CLASS (MODE) == MODE_FLOAT ? (MODE) \
849 : GET_MODE_SIZE (MODE) >= 4 ? (MODE) \
850 : mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0))
852 /* Return the maximum number of consecutive registers
853 needed to represent mode MODE in a register of class CLASS. */
855 #define CLASS_MAX_NREGS(CLASS, MODE) \
856 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
858 /* If defined, gives a class of registers that cannot be used as the
859 operand of a SUBREG that changes the size of the object. */
861 #define CLASS_CANNOT_CHANGE_SIZE FLOAT_REGS
863 /* Define the cost of moving between registers of various classes. Moving
864 between FLOAT_REGS and anything else except float regs is expensive.
865 In fact, we make it quite expensive because we really don't want to
866 do these moves unless it is clearly worth it. Optimizations may
867 reduce the impact of not being able to allocate a pseudo to a
870 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
871 (((CLASS1) == FLOAT_REGS) == ((CLASS2) == FLOAT_REGS) \
873 : TARGET_FIX ? 3 : 4+2*alpha_memory_latency)
875 /* A C expressions returning the cost of moving data of MODE from a register to
878 On the Alpha, bump this up a bit. */
880 extern int alpha_memory_latency
;
881 #define MEMORY_MOVE_COST(MODE,CLASS,IN) (2*alpha_memory_latency)
883 /* Provide the cost of a branch. Exact meaning under development. */
884 #define BRANCH_COST 5
886 /* Adjust the cost of dependencies. */
888 #define ADJUST_COST(INSN,LINK,DEP,COST) \
889 (COST) = alpha_adjust_cost (INSN, LINK, DEP, COST)
891 /* Stack layout; function entry, exit and calling. */
893 /* Define this if pushing a word on the stack
894 makes the stack pointer a smaller address. */
895 #define STACK_GROWS_DOWNWARD
897 /* Define this if the nominal address of the stack frame
898 is at the high-address end of the local variables;
899 that is, each additional local variable allocated
900 goes at a more negative offset in the frame. */
901 /* #define FRAME_GROWS_DOWNWARD */
903 /* Offset within stack frame to start allocating local variables at.
904 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
905 first local allocated. Otherwise, it is the offset to the BEGINNING
906 of the first local allocated. */
908 #define STARTING_FRAME_OFFSET 0
910 /* If we generate an insn to push BYTES bytes,
911 this says how many the stack pointer really advances by.
912 On Alpha, don't define this because there are no push insns. */
913 /* #define PUSH_ROUNDING(BYTES) */
915 /* Define this to be nonzero if stack checking is built into the ABI. */
916 #define STACK_CHECK_BUILTIN 1
918 /* Define this if the maximum size of all the outgoing args is to be
919 accumulated and pushed during the prologue. The amount can be
920 found in the variable current_function_outgoing_args_size. */
921 #define ACCUMULATE_OUTGOING_ARGS
923 /* Offset of first parameter from the argument pointer register value. */
925 #define FIRST_PARM_OFFSET(FNDECL) 0
927 /* Definitions for register eliminations.
929 We have two registers that can be eliminated on the Alpha. First, the
930 frame pointer register can often be eliminated in favor of the stack
931 pointer register. Secondly, the argument pointer register can always be
932 eliminated; it is replaced with either the stack or frame pointer. */
934 /* This is an array of structures. Each structure initializes one pair
935 of eliminable registers. The "from" register number is given first,
936 followed by "to". Eliminations of the same "from" register are listed
937 in order of preference. */
939 #define ELIMINABLE_REGS \
940 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
941 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
942 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
943 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
945 /* Given FROM and TO register numbers, say whether this elimination is allowed.
946 Frame pointer elimination is automatically handled.
948 All eliminations are valid since the cases where FP can't be
949 eliminated are already handled. */
951 #define CAN_ELIMINATE(FROM, TO) 1
953 /* Round up to a multiple of 16 bytes. */
954 #define ALPHA_ROUND(X) (((X) + 15) & ~ 15)
956 /* Define the offset between two registers, one to be eliminated, and the other
957 its replacement, at the start of a routine. */
958 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
959 { if ((FROM) == FRAME_POINTER_REGNUM) \
960 (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size) \
961 + alpha_sa_size ()); \
962 else if ((FROM) == ARG_POINTER_REGNUM) \
963 (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size) \
965 + (ALPHA_ROUND (get_frame_size () \
966 + current_function_pretend_args_size) \
967 - current_function_pretend_args_size)); \
970 /* Define this if stack space is still allocated for a parameter passed
972 /* #define REG_PARM_STACK_SPACE */
974 /* Value is the number of bytes of arguments automatically
975 popped when returning from a subroutine call.
976 FUNDECL is the declaration node of the function (as a tree),
977 FUNTYPE is the data type of the function (as a tree),
978 or for a library call it is an identifier node for the subroutine name.
979 SIZE is the number of bytes of arguments passed on the stack. */
981 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
983 /* Define how to find the value returned by a function.
984 VALTYPE is the data type of the value (as a tree).
985 If the precise function being called is known, FUNC is its FUNCTION_DECL;
986 otherwise, FUNC is 0.
988 On Alpha the value is found in $0 for integer functions and
989 $f0 for floating-point functions. */
991 #define FUNCTION_VALUE(VALTYPE, FUNC) \
992 gen_rtx_REG (((INTEGRAL_TYPE_P (VALTYPE) \
993 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
994 || POINTER_TYPE_P (VALTYPE)) \
995 ? word_mode : TYPE_MODE (VALTYPE), \
997 && (TREE_CODE (VALTYPE) == REAL_TYPE \
998 || TREE_CODE (VALTYPE) == COMPLEX_TYPE)) \
1001 /* Define how to find the value returned by a library function
1002 assuming the value has mode MODE. */
1004 #define LIBCALL_VALUE(MODE) \
1005 gen_rtx_REG (MODE, \
1007 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1008 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1011 /* The definition of this macro implies that there are cases where
1012 a scalar value cannot be returned in registers.
1014 For the Alpha, any structure or union type is returned in memory, as
1015 are integers whose size is larger than 64 bits. */
1017 #define RETURN_IN_MEMORY(TYPE) \
1018 (TYPE_MODE (TYPE) == BLKmode \
1019 || TYPE_MODE (TYPE) == TFmode \
1020 || TYPE_MODE (TYPE) == TCmode \
1021 || (TREE_CODE (TYPE) == INTEGER_TYPE && TYPE_PRECISION (TYPE) > 64))
1023 /* 1 if N is a possible register number for a function value
1024 as seen by the caller. */
1026 #define FUNCTION_VALUE_REGNO_P(N) \
1027 ((N) == 0 || (N) == 1 || (N) == 32 || (N) == 33)
1029 /* 1 if N is a possible register number for function argument passing.
1030 On Alpha, these are $16-$21 and $f16-$f21. */
1032 #define FUNCTION_ARG_REGNO_P(N) \
1033 (((N) >= 16 && (N) <= 21) || ((N) >= 16 + 32 && (N) <= 21 + 32))
1035 /* Define a data type for recording info about an argument list
1036 during the scan of that argument list. This data type should
1037 hold all necessary information about the function itself
1038 and about the args processed so far, enough to enable macros
1039 such as FUNCTION_ARG to determine where the next arg should go.
1041 On Alpha, this is a single integer, which is a number of words
1042 of arguments scanned so far.
1043 Thus 6 or more means all following args should go on the stack. */
1045 #define CUMULATIVE_ARGS int
1047 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1048 for a call to a function whose data type is FNTYPE.
1049 For a library call, FNTYPE is 0. */
1051 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) (CUM) = 0
1053 /* Define intermediate macro to compute the size (in registers) of an argument
1056 #define ALPHA_ARG_SIZE(MODE, TYPE, NAMED) \
1057 ((MODE) == TFmode || (MODE) == TCmode ? 1 \
1058 : (((MODE) == BLKmode ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) \
1059 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
1061 /* Update the data in CUM to advance over an argument
1062 of mode MODE and data type TYPE.
1063 (TYPE is null for libcalls where that information may not be available.) */
1065 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1066 if (MUST_PASS_IN_STACK (MODE, TYPE)) \
1069 (CUM) += ALPHA_ARG_SIZE (MODE, TYPE, NAMED)
1071 /* Determine where to put an argument to a function.
1072 Value is zero to push the argument on the stack,
1073 or a hard register in which to store the argument.
1075 MODE is the argument's machine mode.
1076 TYPE is the data type of the argument (as a tree).
1077 This is null for libcalls where that information may
1079 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1080 the preceding args and about the function being called.
1081 NAMED is nonzero if this argument is a named parameter
1082 (otherwise it is an extra parameter matching an ellipsis).
1084 On Alpha the first 6 words of args are normally in registers
1085 and the rest are pushed. */
1087 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1088 function_arg((CUM), (MODE), (TYPE), (NAMED))
1090 /* A C expression that indicates when an argument must be passed by
1091 reference. If nonzero for an argument, a copy of that argument is
1092 made in memory and a pointer to the argument is passed instead of
1093 the argument itself. The pointer is passed in whatever way is
1094 appropriate for passing a pointer to that type. */
1096 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1097 ((MODE) == TFmode || (MODE) == TCmode)
1099 /* Specify the padding direction of arguments.
1101 On the Alpha, we must pad upwards in order to be able to pass args in
1104 #define FUNCTION_ARG_PADDING(MODE, TYPE) upward
1106 /* For an arg passed partly in registers and partly in memory,
1107 this is the number of registers used.
1108 For args passed entirely in registers or entirely in memory, zero. */
1110 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1111 ((CUM) < 6 && 6 < (CUM) + ALPHA_ARG_SIZE (MODE, TYPE, NAMED) \
1114 /* Perform any needed actions needed for a function that is receiving a
1115 variable number of arguments.
1119 MODE and TYPE are the mode and type of the current parameter.
1121 PRETEND_SIZE is a variable that should be set to the amount of stack
1122 that must be pushed by the prolog to pretend that our caller pushed
1125 Normally, this macro will push all remaining incoming registers on the
1126 stack and set PRETEND_SIZE to the length of the registers pushed.
1128 On the Alpha, we allocate space for all 12 arg registers, but only
1129 push those that are remaining.
1131 However, if NO registers need to be saved, don't allocate any space.
1132 This is not only because we won't need the space, but because AP includes
1133 the current_pretend_args_size and we don't want to mess up any
1134 ap-relative addresses already made.
1136 If we are not to use the floating-point registers, save the integer
1137 registers where we would put the floating-point registers. This is
1138 not the most efficient way to implement varargs with just one register
1139 class, but it isn't worth doing anything more efficient in this rare
1142 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
1147 rtx tmp; int set = get_varargs_alias_set (); \
1148 tmp = gen_rtx_MEM (BLKmode, \
1149 plus_constant (virtual_incoming_args_rtx, \
1150 ((CUM) + 6)* UNITS_PER_WORD)); \
1151 MEM_ALIAS_SET (tmp) = set; \
1152 move_block_from_reg \
1154 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \
1156 tmp = gen_rtx_MEM (BLKmode, \
1157 plus_constant (virtual_incoming_args_rtx, \
1158 (CUM) * UNITS_PER_WORD)); \
1159 MEM_ALIAS_SET (tmp) = set; \
1160 move_block_from_reg \
1161 (16 + (TARGET_FPREGS ? 32 : 0) + CUM, tmp, \
1162 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \
1164 PRETEND_SIZE = 12 * UNITS_PER_WORD; \
1168 /* Try to output insns to set TARGET equal to the constant C if it can be
1169 done in less than N insns. Do all computations in MODE. Returns the place
1170 where the output has been placed if it can be done and the insns have been
1171 emitted. If it would take more than N insns, zero is returned and no
1172 insns and emitted. */
1174 /* Define the information needed to generate branch and scc insns. This is
1175 stored from the compare operation. Note that we can't use "rtx" here
1176 since it hasn't been defined! */
1178 struct alpha_compare
1180 struct rtx_def
*op0
, *op1
;
1184 extern struct alpha_compare alpha_compare
;
1186 /* Machine specific function data. */
1188 struct machine_function
1190 /* An offset to apply to the stack pointer when unwinding from EH. */
1191 struct rtx_def
*eh_epilogue_sp_ofs
;
1193 /* If non-null, this rtx holds the return address for the function. */
1194 struct rtx_def
*ra_rtx
;
1197 /* Make (or fake) .linkage entry for function call.
1198 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition. */
1200 /* This macro defines the start of an assembly comment. */
1202 #define ASM_COMMENT_START " #"
1204 /* This macro produces the initial definition of a function. */
1206 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
1207 alpha_start_function(FILE,NAME,DECL);
1209 /* This macro closes up a function definition for the assembler. */
1211 #define ASM_DECLARE_FUNCTION_SIZE(FILE,NAME,DECL) \
1212 alpha_end_function(FILE,NAME,DECL)
1214 /* This macro notes the end of the prologue. */
1216 #define FUNCTION_END_PROLOGUE(FILE) output_end_prologue (FILE)
1218 /* Output any profiling code before the prologue. */
1220 #define PROFILE_BEFORE_PROLOGUE 1
1222 /* Output assembler code to FILE to increment profiler label # LABELNO
1223 for profiling a function entry. Under OSF/1, profiling is enabled
1224 by simply passing -pg to the assembler and linker. */
1226 #define FUNCTION_PROFILER(FILE, LABELNO)
1228 /* Output assembler code to FILE to initialize this source file's
1229 basic block profiling info, if that has not already been done.
1230 This assumes that __bb_init_func doesn't garble a1-a5. */
1232 #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
1234 ASM_OUTPUT_REG_PUSH (FILE, 16); \
1235 fputs ("\tlda $16,$PBX32\n", (FILE)); \
1236 fputs ("\tldq $26,0($16)\n", (FILE)); \
1237 fputs ("\tbne $26,1f\n", (FILE)); \
1238 fputs ("\tlda $27,__bb_init_func\n", (FILE)); \
1239 fputs ("\tjsr $26,($27),__bb_init_func\n", (FILE)); \
1240 fputs ("\tldgp $29,0($26)\n", (FILE)); \
1241 fputs ("1:\n", (FILE)); \
1242 ASM_OUTPUT_REG_POP (FILE, 16); \
1245 /* Output assembler code to FILE to increment the entry-count for
1246 the BLOCKNO'th basic block in this source file. */
1248 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1250 int blockn = (BLOCKNO); \
1251 fputs ("\tsubq $30,16,$30\n", (FILE)); \
1252 fputs ("\tstq $26,0($30)\n", (FILE)); \
1253 fputs ("\tstq $27,8($30)\n", (FILE)); \
1254 fputs ("\tlda $26,$PBX34\n", (FILE)); \
1255 fprintf ((FILE), "\tldq $27,%d($26)\n", 8*blockn); \
1256 fputs ("\taddq $27,1,$27\n", (FILE)); \
1257 fprintf ((FILE), "\tstq $27,%d($26)\n", 8*blockn); \
1258 fputs ("\tldq $26,0($30)\n", (FILE)); \
1259 fputs ("\tldq $27,8($30)\n", (FILE)); \
1260 fputs ("\taddq $30,16,$30\n", (FILE)); \
1264 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1265 the stack pointer does not matter. The value is tested only in
1266 functions that have frame pointers.
1267 No definition is equivalent to always zero. */
1269 #define EXIT_IGNORE_STACK 1
1271 /* Output assembler code for a block containing the constant parts
1272 of a trampoline, leaving space for the variable parts.
1274 The trampoline should set the static chain pointer to value placed
1275 into the trampoline and should branch to the specified routine.
1276 Note that $27 has been set to the address of the trampoline, so we can
1277 use it for addressability of the two data items. Trampolines are always
1278 aligned to FUNCTION_BOUNDARY, which is 64 bits. */
1280 #define TRAMPOLINE_TEMPLATE(FILE) \
1282 fprintf (FILE, "\tldq $1,24($27)\n"); \
1283 fprintf (FILE, "\tldq $27,16($27)\n"); \
1284 fprintf (FILE, "\tjmp $31,($27),0\n"); \
1285 fprintf (FILE, "\tnop\n"); \
1286 fprintf (FILE, "\t.quad 0,0\n"); \
1289 /* Section in which to place the trampoline. On Alpha, instructions
1290 may only be placed in a text segment. */
1292 #define TRAMPOLINE_SECTION text_section
1294 /* Length in units of the trampoline for entering a nested function. */
1296 #define TRAMPOLINE_SIZE 32
1298 /* Emit RTL insns to initialize the variable parts of a trampoline.
1299 FNADDR is an RTX for the address of the function's pure code.
1300 CXT is an RTX for the static chain value for the function. */
1302 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1303 alpha_initialize_trampoline (TRAMP, FNADDR, CXT, 16, 24, 8)
1305 /* A C expression whose value is RTL representing the value of the return
1306 address for the frame COUNT steps up from the current frame.
1307 FRAMEADDR is the frame pointer of the COUNT frame, or the frame pointer of
1308 the COUNT-1 frame if RETURN_ADDR_IN_PREVIOUS_FRAME is defined. */
1310 #define RETURN_ADDR_RTX alpha_return_addr
1312 /* Before the prologue, RA lives in $26. */
1313 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 26)
1315 /* Addressing modes, and classification of registers for them. */
1317 /* #define HAVE_POST_INCREMENT 0 */
1318 /* #define HAVE_POST_DECREMENT 0 */
1320 /* #define HAVE_PRE_DECREMENT 0 */
1321 /* #define HAVE_PRE_INCREMENT 0 */
1323 /* Macros to check register numbers against specific register classes. */
1325 /* These assume that REGNO is a hard or pseudo reg number.
1326 They give nonzero only if REGNO is a hard reg of the suitable class
1327 or a pseudo reg currently allocated to a suitable hard reg.
1328 Since they use reg_renumber, they are safe only once reg_renumber
1329 has been allocated, which happens in local-alloc.c. */
1331 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
1332 #define REGNO_OK_FOR_BASE_P(REGNO) \
1333 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32 \
1334 || (REGNO) == 63 || reg_renumber[REGNO] == 63)
1336 /* Maximum number of registers that can appear in a valid memory address. */
1337 #define MAX_REGS_PER_ADDRESS 1
1339 /* Recognize any constant value that is a valid address. For the Alpha,
1340 there are only constants none since we want to use LDA to load any
1341 symbolic addresses into registers. */
1343 #define CONSTANT_ADDRESS_P(X) \
1344 (GET_CODE (X) == CONST_INT \
1345 && (unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1347 /* Include all constant integers and constant doubles, but not
1348 floating-point, except for floating-point zero. */
1350 #define LEGITIMATE_CONSTANT_P(X) \
1351 (GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \
1352 || (X) == CONST0_RTX (GET_MODE (X)))
1354 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1355 and check its validity for a certain class.
1356 We have two alternate definitions for each of them.
1357 The usual definition accepts all pseudo regs; the other rejects
1358 them unless they have been allocated suitable hard regs.
1359 The symbol REG_OK_STRICT causes the latter definition to be used.
1361 Most source files want to accept pseudo regs in the hope that
1362 they will get allocated to the class that the insn wants them to be in.
1363 Source files for reload pass need to be strict.
1364 After reload, it makes no difference, since pseudo regs have
1365 been eliminated by then. */
1367 #ifndef REG_OK_STRICT
1369 /* Nonzero if X is a hard reg that can be used as an index
1370 or if it is a pseudo reg. */
1371 #define REG_OK_FOR_INDEX_P(X) 0
1373 /* Nonzero if X is a hard reg that can be used as a base reg
1374 or if it is a pseudo reg. */
1375 #define REG_OK_FOR_BASE_P(X) \
1376 (REGNO (X) < 32 || REGNO (X) == 63 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1378 /* ??? Nonzero if X is the frame pointer, or some virtual register
1379 that may eliminate to the frame pointer. These will be allowed to
1380 have offsets greater than 32K. This is done because register
1381 elimination offsets will change the hi/lo split, and if we split
1382 before reload, we will require additional instructions. */
1383 #define REG_OK_FP_BASE_P(X) \
1384 (REGNO (X) == 31 || REGNO (X) == 63 \
1385 || (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1386 && REGNO (X) < LAST_VIRTUAL_REGISTER))
1390 /* Nonzero if X is a hard reg that can be used as an index. */
1391 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1393 /* Nonzero if X is a hard reg that can be used as a base reg. */
1394 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1396 #define REG_OK_FP_BASE_P(X) 0
1400 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1401 that is a valid memory address for an instruction.
1402 The MODE argument is the machine mode for the MEM expression
1403 that wants to use this address.
1405 For Alpha, we have either a constant address or the sum of a register
1406 and a constant address, or just a register. For DImode, any of those
1407 forms can be surrounded with an AND that clear the low-order three bits;
1408 this is an "unaligned" access.
1410 First define the basic valid address. */
1412 #define GO_IF_LEGITIMATE_SIMPLE_ADDRESS(MODE, X, ADDR) \
1415 if (GET_CODE (tmp) == SUBREG \
1416 && (GET_MODE_SIZE (GET_MODE (tmp)) \
1417 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (tmp))))) \
1418 tmp = SUBREG_REG (tmp); \
1419 if (REG_P (tmp) && REG_OK_FOR_BASE_P (tmp)) \
1421 if (CONSTANT_ADDRESS_P (X)) \
1423 if (GET_CODE (X) == PLUS) \
1425 tmp = XEXP (X, 0); \
1426 if (GET_CODE (tmp) == SUBREG \
1427 && (GET_MODE_SIZE (GET_MODE (tmp)) \
1428 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (tmp))))) \
1429 tmp = SUBREG_REG (tmp); \
1432 if (REG_OK_FP_BASE_P (tmp) \
1433 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1435 if (REG_OK_FOR_BASE_P (tmp) \
1436 && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1439 else if (GET_CODE (tmp) == ADDRESSOF \
1440 && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1445 /* Now accept the simple address, or, for DImode only, an AND of a simple
1446 address that turns off the low three bits. */
1448 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1449 { GO_IF_LEGITIMATE_SIMPLE_ADDRESS (MODE, X, ADDR); \
1450 if ((MODE) == DImode \
1451 && GET_CODE (X) == AND \
1452 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1453 && INTVAL (XEXP (X, 1)) == -8) \
1454 GO_IF_LEGITIMATE_SIMPLE_ADDRESS (MODE, XEXP (X, 0), ADDR); \
1457 /* Try machine-dependent ways of modifying an illegitimate address
1458 to be legitimate. If we find one, return the new, valid address.
1459 This macro is used in only one place: `memory_address' in explow.c.
1461 OLDX is the address as it was before break_out_memory_refs was called.
1462 In some cases it is useful to look at this to decide what needs to be done.
1464 MODE and WIN are passed so that this macro can use
1465 GO_IF_LEGITIMATE_ADDRESS.
1467 It is always safe for this macro to do nothing. It exists to recognize
1468 opportunities to optimize the output.
1470 For the Alpha, there are three cases we handle:
1472 (1) If the address is (plus reg const_int) and the CONST_INT is not a
1473 valid offset, compute the high part of the constant and add it to the
1474 register. Then our address is (plus temp low-part-const).
1475 (2) If the address is (const (plus FOO const_int)), find the low-order
1476 part of the CONST_INT. Then load FOO plus any high-order part of the
1477 CONST_INT into a register. Our address is (plus reg low-part-const).
1478 This is done to reduce the number of GOT entries.
1479 (3) If we have a (plus reg const), emit the load as in (2), then add
1480 the two registers, and finally generate (plus reg low-part-const) as
1483 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1484 { if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
1485 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1486 && ! CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1488 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1489 HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \
1490 HOST_WIDE_INT highpart = val - lowpart; \
1491 rtx high = GEN_INT (highpart); \
1492 rtx temp = expand_binop (Pmode, add_optab, XEXP (x, 0), \
1493 high, NULL_RTX, 1, OPTAB_LIB_WIDEN); \
1495 (X) = plus_constant (temp, lowpart); \
1498 else if (GET_CODE (X) == CONST \
1499 && GET_CODE (XEXP (X, 0)) == PLUS \
1500 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \
1502 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \
1503 HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \
1504 HOST_WIDE_INT highpart = val - lowpart; \
1505 rtx high = XEXP (XEXP (X, 0), 0); \
1508 high = plus_constant (high, highpart); \
1510 (X) = plus_constant (force_reg (Pmode, high), lowpart); \
1513 else if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
1514 && GET_CODE (XEXP (X, 1)) == CONST \
1515 && GET_CODE (XEXP (XEXP (X, 1), 0)) == PLUS \
1516 && GET_CODE (XEXP (XEXP (XEXP (X, 1), 0), 1)) == CONST_INT) \
1518 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 1), 0), 1)); \
1519 HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \
1520 HOST_WIDE_INT highpart = val - lowpart; \
1521 rtx high = XEXP (XEXP (XEXP (X, 1), 0), 0); \
1524 high = plus_constant (high, highpart); \
1526 high = expand_binop (Pmode, add_optab, XEXP (X, 0), \
1527 force_reg (Pmode, high), \
1528 high, 1, OPTAB_LIB_WIDEN); \
1529 (X) = plus_constant (high, lowpart); \
1534 /* Try a machine-dependent way of reloading an illegitimate address
1535 operand. If we find one, push the reload and jump to WIN. This
1536 macro is used in only one place: `find_reloads_address' in reload.c.
1538 For the Alpha, we wish to handle large displacements off a base
1539 register by splitting the addend across an ldah and the mem insn.
1540 This cuts number of extra insns needed from 3 to 1. */
1542 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1544 /* We must recognize output that we have already generated ourselves. */ \
1545 if (GET_CODE (X) == PLUS \
1546 && GET_CODE (XEXP (X, 0)) == PLUS \
1547 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
1548 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1549 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1551 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \
1552 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1556 if (GET_CODE (X) == PLUS \
1557 && GET_CODE (XEXP (X, 0)) == REG \
1558 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1559 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1560 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1562 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1563 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; \
1564 HOST_WIDE_INT high \
1565 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000; \
1567 /* Check for 32-bit overflow. */ \
1568 if (high + low != val) \
1571 /* Reload the high part into a base reg; leave the low part \
1572 in the mem directly. */ \
1574 X = gen_rtx_PLUS (GET_MODE (X), \
1575 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1579 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \
1580 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1586 /* Go to LABEL if ADDR (a legitimate address expression)
1587 has an effect that depends on the machine mode it is used for.
1588 On the Alpha this is true only for the unaligned modes. We can
1589 simplify this test since we know that the address must be valid. */
1591 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1592 { if (GET_CODE (ADDR) == AND) goto LABEL; }
1594 /* Compute the cost of an address. For the Alpha, all valid addresses are
1597 #define ADDRESS_COST(X) 0
1599 /* Machine-dependent reorg pass. */
1600 #define MACHINE_DEPENDENT_REORG(X) alpha_reorg(X)
1602 /* Specify the machine mode that this machine uses
1603 for the index in the tablejump instruction. */
1604 #define CASE_VECTOR_MODE SImode
1606 /* Define as C expression which evaluates to nonzero if the tablejump
1607 instruction expects the table to contain offsets from the address of the
1610 Do not define this if the table should contain absolute addresses.
1611 On the Alpha, the table is really GP-relative, not relative to the PC
1612 of the table, but we pretend that it is PC-relative; this should be OK,
1613 but we should try to find some better way sometime. */
1614 #define CASE_VECTOR_PC_RELATIVE 1
1616 /* Specify the tree operation to be used to convert reals to integers. */
1617 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1619 /* This is the kind of divide that is easiest to do in the general case. */
1620 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1622 /* Define this as 1 if `char' should by default be signed; else as 0. */
1623 #define DEFAULT_SIGNED_CHAR 1
1625 /* This flag, if defined, says the same insns that convert to a signed fixnum
1626 also convert validly to an unsigned one.
1628 We actually lie a bit here as overflow conditions are different. But
1629 they aren't being checked anyway. */
1631 #define FIXUNS_TRUNC_LIKE_FIX_TRUNC
1633 /* Max number of bytes we can move to or from memory
1634 in one reasonably fast instruction. */
1638 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1639 move-instruction pairs, we will do a movstr or libcall instead.
1641 Without byte/word accesses, we want no more than four instructions;
1642 with, several single byte accesses are better. */
1644 #define MOVE_RATIO (TARGET_BWX ? 7 : 2)
1646 /* Largest number of bytes of an object that can be placed in a register.
1647 On the Alpha we have plenty of registers, so use TImode. */
1648 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
1650 /* Nonzero if access to memory by bytes is no faster than for words.
1651 Also non-zero if doing byte operations (specifically shifts) in registers
1654 On the Alpha, we want to not use the byte operation and instead use
1655 masking operations to access fields; these will save instructions. */
1657 #define SLOW_BYTE_ACCESS 1
1659 /* Define if operations between registers always perform the operation
1660 on the full register even if a narrower mode is specified. */
1661 #define WORD_REGISTER_OPERATIONS
1663 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1664 will either zero-extend or sign-extend. The value of this macro should
1665 be the code that says which one of the two operations is implicitly
1666 done, NIL if none. */
1667 #define LOAD_EXTEND_OP(MODE) ((MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
1669 /* Define if loading short immediate values into registers sign extends. */
1670 #define SHORT_IMMEDIATES_SIGN_EXTEND
1672 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1673 is done just by pretending it is already truncated. */
1674 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1676 /* We assume that the store-condition-codes instructions store 0 for false
1677 and some other value for true. This is the value stored for true. */
1679 #define STORE_FLAG_VALUE 1
1681 /* Define the value returned by a floating-point comparison instruction. */
1683 #define FLOAT_STORE_FLAG_VALUE(MODE) \
1684 REAL_VALUE_ATOF ((TARGET_FLOAT_VAX ? "0.5" : "2.0"), (MODE))
1686 /* Canonicalize a comparison from one we don't have to one we do have. */
1688 #define CANONICALIZE_COMPARISON(CODE,OP0,OP1) \
1690 if (((CODE) == GE || (CODE) == GT || (CODE) == GEU || (CODE) == GTU) \
1691 && (GET_CODE (OP1) == REG || (OP1) == const0_rtx)) \
1696 (CODE) = swap_condition (CODE); \
1698 if (((CODE) == LT || (CODE) == LTU) \
1699 && GET_CODE (OP1) == CONST_INT && INTVAL (OP1) == 256) \
1701 (CODE) = (CODE) == LT ? LE : LEU; \
1702 (OP1) = GEN_INT (255); \
1706 /* Specify the machine mode that pointers have.
1707 After generation of rtl, the compiler makes no further distinction
1708 between pointers and any other objects of this machine mode. */
1709 #define Pmode DImode
1711 /* Mode of a function address in a call instruction (for indexing purposes). */
1713 #define FUNCTION_MODE Pmode
1715 /* Define this if addresses of constant functions
1716 shouldn't be put through pseudo regs where they can be cse'd.
1717 Desirable on machines where ordinary constants are expensive
1718 but a CALL with constant address is cheap.
1720 We define this on the Alpha so that gen_call and gen_call_value
1721 get to see the SYMBOL_REF (for the hint field of the jsr). It will
1722 then copy it into a register, thus actually letting the address be
1725 #define NO_FUNCTION_CSE
1727 /* Define this to be nonzero if shift instructions ignore all but the low-order
1729 #define SHIFT_COUNT_TRUNCATED 1
1731 /* The EV4 is dual issue; EV5/EV6 are quad issue. */
1732 #define ISSUE_RATE (alpha_cpu == PROCESSOR_EV4 ? 2 : 4)
1734 /* Describe the fact that MULTI instructions are multiple instructions
1735 and so to assume they don't pair with anything. */
1736 #define MD_SCHED_VARIABLE_ISSUE(DUMP, SCHED_VERBOSE, INSN, CAN_ISSUE_MORE) \
1737 if (recog_memoized (INSN) < 0 || get_attr_type (INSN) == TYPE_MULTI) \
1738 (CAN_ISSUE_MORE) = 0
1740 /* Compute the cost of computing a constant rtl expression RTX
1741 whose rtx-code is CODE. The body of this macro is a portion
1742 of a switch statement. If the code is computed here,
1743 return it with a return statement. Otherwise, break from the switch.
1745 If this is an 8-bit constant, return zero since it can be used
1746 nearly anywhere with no cost. If it is a valid operand for an
1747 ADD or AND, likewise return 0 if we know it will be used in that
1748 context. Otherwise, return 2 since it might be used there later.
1749 All other constants take at least two insns. */
1751 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1753 if (INTVAL (RTX) >= 0 && INTVAL (RTX) < 256) \
1755 case CONST_DOUBLE: \
1756 if ((RTX) == CONST0_RTX (GET_MODE (RTX))) \
1758 else if (((OUTER_CODE) == PLUS && add_operand (RTX, VOIDmode)) \
1759 || ((OUTER_CODE) == AND && and_operand (RTX, VOIDmode))) \
1761 else if (add_operand (RTX, VOIDmode) || and_operand (RTX, VOIDmode)) \
1764 return COSTS_N_INSNS (2); \
1768 switch (alpha_cpu) \
1770 case PROCESSOR_EV4: \
1771 return COSTS_N_INSNS (3); \
1772 case PROCESSOR_EV5: \
1773 case PROCESSOR_EV6: \
1774 return COSTS_N_INSNS (2); \
1778 /* Provide the costs of a rtl expression. This is in the body of a
1781 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1782 case PLUS: case MINUS: \
1783 if (FLOAT_MODE_P (GET_MODE (X))) \
1784 switch (alpha_cpu) \
1786 case PROCESSOR_EV4: \
1787 return COSTS_N_INSNS (6); \
1788 case PROCESSOR_EV5: \
1789 case PROCESSOR_EV6: \
1790 return COSTS_N_INSNS (4); \
1793 else if (GET_CODE (XEXP (X, 0)) == MULT \
1794 && const48_operand (XEXP (XEXP (X, 0), 1), VOIDmode)) \
1795 return (2 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \
1796 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
1799 switch (alpha_cpu) \
1801 case PROCESSOR_EV4: \
1802 if (FLOAT_MODE_P (GET_MODE (X))) \
1803 return COSTS_N_INSNS (6); \
1804 return COSTS_N_INSNS (23); \
1805 case PROCESSOR_EV5: \
1806 if (FLOAT_MODE_P (GET_MODE (X))) \
1807 return COSTS_N_INSNS (4); \
1808 else if (GET_MODE (X) == DImode) \
1809 return COSTS_N_INSNS (12); \
1811 return COSTS_N_INSNS (8); \
1812 case PROCESSOR_EV6: \
1813 if (FLOAT_MODE_P (GET_MODE (X))) \
1814 return COSTS_N_INSNS (4); \
1816 return COSTS_N_INSNS (7); \
1820 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1821 && INTVAL (XEXP (X, 1)) <= 3) \
1823 /* ... fall through ... */ \
1824 case ASHIFTRT: case LSHIFTRT: \
1825 switch (alpha_cpu) \
1827 case PROCESSOR_EV4: \
1828 return COSTS_N_INSNS (2); \
1829 case PROCESSOR_EV5: \
1830 case PROCESSOR_EV6: \
1831 return COSTS_N_INSNS (1); \
1834 case IF_THEN_ELSE: \
1835 switch (alpha_cpu) \
1837 case PROCESSOR_EV4: \
1838 case PROCESSOR_EV6: \
1839 return COSTS_N_INSNS (2); \
1840 case PROCESSOR_EV5: \
1841 return COSTS_N_INSNS (1); \
1844 case DIV: case UDIV: case MOD: case UMOD: \
1845 switch (alpha_cpu) \
1847 case PROCESSOR_EV4: \
1848 if (GET_MODE (X) == SFmode) \
1849 return COSTS_N_INSNS (34); \
1850 else if (GET_MODE (X) == DFmode) \
1851 return COSTS_N_INSNS (63); \
1853 return COSTS_N_INSNS (70); \
1854 case PROCESSOR_EV5: \
1855 if (GET_MODE (X) == SFmode) \
1856 return COSTS_N_INSNS (15); \
1857 else if (GET_MODE (X) == DFmode) \
1858 return COSTS_N_INSNS (22); \
1860 return COSTS_N_INSNS (70); /* ??? */ \
1861 case PROCESSOR_EV6: \
1862 if (GET_MODE (X) == SFmode) \
1863 return COSTS_N_INSNS (12); \
1864 else if (GET_MODE (X) == DFmode) \
1865 return COSTS_N_INSNS (15); \
1867 return COSTS_N_INSNS (70); /* ??? */ \
1871 switch (alpha_cpu) \
1873 case PROCESSOR_EV4: \
1874 case PROCESSOR_EV6: \
1875 return COSTS_N_INSNS (3); \
1876 case PROCESSOR_EV5: \
1877 return COSTS_N_INSNS (2); \
1880 case NEG: case ABS: \
1881 if (! FLOAT_MODE_P (GET_MODE (X))) \
1883 /* ... fall through ... */ \
1884 case FLOAT: case UNSIGNED_FLOAT: case FIX: case UNSIGNED_FIX: \
1885 case FLOAT_EXTEND: case FLOAT_TRUNCATE: \
1886 switch (alpha_cpu) \
1888 case PROCESSOR_EV4: \
1889 return COSTS_N_INSNS (6); \
1890 case PROCESSOR_EV5: \
1891 case PROCESSOR_EV6: \
1892 return COSTS_N_INSNS (4); \
1896 /* Control the assembler format that we output. */
1898 /* We don't emit these labels, so as to avoid getting linker errors about
1899 missing exception handling info. If we emit a gcc_compiled. label into
1900 text, and the file has no code, then the DEC assembler gives us a zero
1901 sized text section with no associated exception handling info. The
1902 DEC linker sees this text section, and gives a warning saying that
1903 the exception handling info is missing. */
1904 #define ASM_IDENTIFY_GCC(x)
1905 #define ASM_IDENTIFY_LANGUAGE(x)
1907 /* Output to assembler file text saying following lines
1908 may contain character constants, extra white space, comments, etc. */
1910 #define ASM_APP_ON ""
1912 /* Output to assembler file text saying following lines
1913 no longer contain unusual constructs. */
1915 #define ASM_APP_OFF ""
1917 #define TEXT_SECTION_ASM_OP ".text"
1919 /* Output before read-only data. */
1921 #define READONLY_DATA_SECTION_ASM_OP ".rdata"
1923 /* Output before writable data. */
1925 #define DATA_SECTION_ASM_OP ".data"
1927 /* Define an extra section for read-only data, a routine to enter it, and
1928 indicate that it is for read-only data.
1930 The first time we enter the readonly data section for a file, we write
1931 eight bytes of zero. This works around a bug in DEC's assembler in
1932 some versions of OSF/1 V3.x. */
1934 #define EXTRA_SECTIONS readonly_data
1936 #define EXTRA_SECTION_FUNCTIONS \
1938 literal_section () \
1940 if (in_section != readonly_data) \
1942 static int firsttime = 1; \
1944 fprintf (asm_out_file, "%s\n", READONLY_DATA_SECTION_ASM_OP); \
1948 ASM_OUTPUT_DOUBLE_INT (asm_out_file, const0_rtx); \
1951 in_section = readonly_data; \
1955 #define READONLY_DATA_SECTION literal_section
1957 /* If we are referencing a function that is static, make the SYMBOL_REF
1958 special. We use this to see indicate we can branch to this function
1959 without setting PV or restoring GP. */
1961 #define ENCODE_SECTION_INFO(DECL) \
1962 if (TREE_CODE (DECL) == FUNCTION_DECL && ! TREE_PUBLIC (DECL)) \
1963 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1;
1965 /* How to refer to registers in assembler output.
1966 This sequence is indexed by compiler's hard-register-number (see above). */
1968 #define REGISTER_NAMES \
1969 {"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", \
1970 "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
1971 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
1972 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "AP", \
1973 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8", \
1974 "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
1975 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",\
1976 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "FP"}
1978 /* How to renumber registers for dbx and gdb. */
1980 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1982 /* This is how to output the definition of a user-level label named NAME,
1983 such as the label on a static function or variable NAME. */
1985 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1986 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1988 /* This is how to output a command to make the user-level label named NAME
1989 defined for reference from other files. */
1991 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1992 do { fputs ("\t.globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
1994 /* The prefix to add to user-visible assembler symbols. */
1996 #define USER_LABEL_PREFIX ""
1998 /* This is how to output an internal numbered label where
1999 PREFIX is the class of label and NUM is the number within the class. */
2001 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
2002 fprintf (FILE, "$%s%d:\n", PREFIX, NUM)
2004 /* This is how to output a label for a jump table. Arguments are the same as
2005 for ASM_OUTPUT_INTERNAL_LABEL, except the insn for the jump table is
2008 #define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN) \
2009 { ASM_OUTPUT_ALIGN (FILE, 2); ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); }
2011 /* This is how to store into the string LABEL
2012 the symbol_ref name of an internal numbered label where
2013 PREFIX is the class of label and NUM is the number within the class.
2014 This is suitable for output with `assemble_name'. */
2016 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2017 sprintf ((LABEL), "*$%s%ld", (PREFIX), (long)(NUM))
2019 /* Check a floating-point value for validity for a particular machine mode. */
2021 #define CHECK_FLOAT_VALUE(MODE, D, OVERFLOW) \
2022 ((OVERFLOW) = check_float_value (MODE, &D, OVERFLOW))
2024 /* This is how to output an assembler line defining a `long double'
2027 #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \
2030 REAL_VALUE_TO_TARGET_LONG_DOUBLE ((VALUE), t); \
2031 fprintf (FILE, "\t.quad 0x%lx%08lx,0x%lx%08lx\n", \
2032 t[1] & 0xffffffff, t[0] & 0xffffffff, \
2033 t[3] & 0xffffffff, t[2] & 0xffffffff); \
2036 /* This is how to output an assembler line defining a `double' constant. */
2038 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
2041 REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
2042 fprintf (FILE, "\t.quad 0x%lx%08lx\n", \
2043 t[1] & 0xffffffff, t[0] & 0xffffffff); \
2046 /* This is how to output an assembler line defining a `float' constant. */
2048 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
2051 REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
2052 fprintf (FILE, "\t.long 0x%lx\n", t & 0xffffffff); \
2055 /* This is how to output an assembler line defining an `int' constant. */
2057 #define ASM_OUTPUT_INT(FILE,VALUE) \
2058 ( fprintf (FILE, "\t.long "), \
2059 output_addr_const (FILE, (VALUE)), \
2060 fprintf (FILE, "\n"))
2062 /* This is how to output an assembler line defining a `long' constant. */
2064 #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
2065 ( fprintf (FILE, "\t.quad "), \
2066 output_addr_const (FILE, (VALUE)), \
2067 fprintf (FILE, "\n"))
2069 /* Likewise for `char' and `short' constants. */
2071 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
2072 fprintf (FILE, "\t.word %d\n", \
2073 (int)(GET_CODE (VALUE) == CONST_INT \
2074 ? INTVAL (VALUE) & 0xffff : (abort (), 0)))
2076 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
2077 fprintf (FILE, "\t.byte %d\n", \
2078 (int)(GET_CODE (VALUE) == CONST_INT \
2079 ? INTVAL (VALUE) & 0xff : (abort (), 0)))
2081 /* We use the default ASCII-output routine, except that we don't write more
2082 than 50 characters since the assembler doesn't support very long lines. */
2084 #define ASM_OUTPUT_ASCII(MYFILE, MYSTRING, MYLENGTH) \
2086 FILE *_hide_asm_out_file = (MYFILE); \
2087 const unsigned char *_hide_p = (const unsigned char *) (MYSTRING); \
2088 int _hide_thissize = (MYLENGTH); \
2089 int _size_so_far = 0; \
2091 FILE *asm_out_file = _hide_asm_out_file; \
2092 const unsigned char *p = _hide_p; \
2093 int thissize = _hide_thissize; \
2095 fprintf (asm_out_file, "\t.ascii \""); \
2097 for (i = 0; i < thissize; i++) \
2099 register int c = p[i]; \
2101 if (_size_so_far ++ > 50 && i < thissize - 4) \
2102 _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \
2104 if (c == '\"' || c == '\\') \
2105 putc ('\\', asm_out_file); \
2106 if (c >= ' ' && c < 0177) \
2107 putc (c, asm_out_file); \
2110 fprintf (asm_out_file, "\\%o", c); \
2111 /* After an octal-escape, if a digit follows, \
2112 terminate one string constant and start another. \
2113 The Vax assembler fails to stop reading the escape \
2114 after three digits, so this is the only way we \
2115 can get it to parse the data properly. */ \
2116 if (i < thissize - 1 \
2117 && p[i + 1] >= '0' && p[i + 1] <= '9') \
2118 _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \
2121 fprintf (asm_out_file, "\"\n"); \
2126 /* To get unaligned data, we have to turn off auto alignment. */
2127 #define UNALIGNED_SHORT_ASM_OP ".align 0\n\t.word"
2128 #define UNALIGNED_INT_ASM_OP ".align 0\n\t.long"
2129 #define UNALIGNED_DOUBLE_INT_ASM_OP ".align 0\n\t.quad"
2131 /* This is how to output an insn to push a register on the stack.
2132 It need not be very fast code. */
2134 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
2135 fprintf (FILE, "\tsubq $30,8,$30\n\tst%s $%s%d,0($30)\n", \
2136 (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \
2139 /* This is how to output an insn to pop a register from the stack.
2140 It need not be very fast code. */
2142 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
2143 fprintf (FILE, "\tld%s $%s%d,0($30)\n\taddq $30,8,$30\n", \
2144 (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \
2147 /* This is how to output an assembler line for a numeric constant byte. */
2149 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
2150 fprintf (FILE, "\t.byte 0x%x\n", (int) ((VALUE) & 0xff))
2152 /* This is how to output an element of a case-vector that is absolute.
2153 (Alpha does not use such vectors, but we must define this macro anyway.) */
2155 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) abort ()
2157 /* This is how to output an element of a case-vector that is relative. */
2159 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2160 fprintf (FILE, "\t.%s $L%d\n", TARGET_WINDOWS_NT ? "long" : "gprel32", \
2163 /* This is how to output an assembler line
2164 that says to advance the location counter
2165 to a multiple of 2**LOG bytes. */
2167 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2169 fprintf (FILE, "\t.align %d\n", LOG);
2171 /* This is how to advance the location counter by SIZE bytes. */
2173 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2174 fprintf (FILE, "\t.space %d\n", (SIZE))
2176 /* This says how to output an assembler line
2177 to define a global common symbol. */
2179 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2180 ( fputs ("\t.comm ", (FILE)), \
2181 assemble_name ((FILE), (NAME)), \
2182 fprintf ((FILE), ",%d\n", (SIZE)))
2184 /* This says how to output an assembler line
2185 to define a local common symbol. */
2187 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED) \
2188 ( fputs ("\t.lcomm ", (FILE)), \
2189 assemble_name ((FILE), (NAME)), \
2190 fprintf ((FILE), ",%d\n", (SIZE)))
2192 /* Store in OUTPUT a string (made with alloca) containing
2193 an assembler-name for a local static variable named NAME.
2194 LABELNO is an integer which is different for each call. */
2196 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2197 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2198 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2200 /* Define the parentheses used to group arithmetic operations
2201 in assembler code. */
2203 #define ASM_OPEN_PAREN "("
2204 #define ASM_CLOSE_PAREN ")"
2206 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2207 Used for C++ multiple inheritance. */
2209 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2211 const char *fn_name = XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0); \
2214 /* Mark end of prologue. */ \
2215 output_end_prologue (FILE); \
2217 /* Rely on the assembler to macro expand a large delta. */ \
2218 reg = aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) ? 17 : 16; \
2219 fprintf (FILE, "\tlda $%d,%ld($%d)\n", reg, (long)(DELTA), reg); \
2221 if (current_file_function_operand (XEXP (DECL_RTL (FUNCTION), 0), \
2224 fprintf (FILE, "\tbr $31,$"); \
2225 assemble_name (FILE, fn_name); \
2226 fprintf (FILE, "..ng\n"); \
2230 fprintf (FILE, "\tjmp $31,"); \
2231 assemble_name (FILE, fn_name); \
2232 fputc ('\n', FILE); \
2237 /* Define results of standard character escape sequences. */
2238 #define TARGET_BELL 007
2239 #define TARGET_BS 010
2240 #define TARGET_TAB 011
2241 #define TARGET_NEWLINE 012
2242 #define TARGET_VT 013
2243 #define TARGET_FF 014
2244 #define TARGET_CR 015
2246 /* Print operand X (an rtx) in assembler syntax to file FILE.
2247 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2248 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2250 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2252 /* Determine which codes are valid without a following integer. These must
2253 not be alphabetic (the characters are chosen so that
2254 PRINT_OPERAND_PUNCT_VALID_P translates into a simple range change when
2257 & Generates fp-rounding mode suffix: nothing for normal, 'c' for
2258 chopped, 'm' for minus-infinity, and 'd' for dynamic rounding
2259 mode. alpha_fprm controls which suffix is generated.
2261 ' Generates trap-mode suffix for instructions that accept the
2262 su suffix only (cmpt et al).
2264 ` Generates trap-mode suffix for instructions that accept the
2265 v and sv suffix. The only instruction that needs this is cvtql.
2267 ( Generates trap-mode suffix for instructions that accept the
2268 v, sv, and svi suffix. The only instruction that needs this
2271 ) Generates trap-mode suffix for instructions that accept the
2272 u, su, and sui suffix. This is the bulk of the IEEE floating
2273 point instructions (addt et al).
2275 + Generates trap-mode suffix for instructions that accept the
2276 sui suffix (cvtqt and cvtqs).
2278 , Generates single precision suffix for floating point
2279 instructions (s for IEEE, f for VAX)
2281 - Generates double precision suffix for floating point
2282 instructions (t for IEEE, g for VAX)
2285 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2286 ((CODE) == '&' || (CODE) == '`' || (CODE) == '\'' || (CODE) == '(' \
2287 || (CODE) == ')' || (CODE) == '+' || (CODE) == ',' || (CODE) == '-')
2289 /* Print a memory address as an operand to reference that memory location. */
2291 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2292 print_operand_address((FILE), (ADDR))
2294 /* Define the codes that are matched by predicates in alpha.c. */
2296 #define PREDICATE_CODES \
2297 {"reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
2298 {"reg_or_6bit_operand", {SUBREG, REG, CONST_INT}}, \
2299 {"reg_or_8bit_operand", {SUBREG, REG, CONST_INT}}, \
2300 {"cint8_operand", {CONST_INT}}, \
2301 {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \
2302 {"add_operand", {SUBREG, REG, CONST_INT}}, \
2303 {"sext_add_operand", {SUBREG, REG, CONST_INT}}, \
2304 {"const48_operand", {CONST_INT}}, \
2305 {"and_operand", {SUBREG, REG, CONST_INT}}, \
2306 {"or_operand", {SUBREG, REG, CONST_INT}}, \
2307 {"mode_mask_operand", {CONST_INT}}, \
2308 {"mul8_operand", {CONST_INT}}, \
2309 {"mode_width_operand", {CONST_INT}}, \
2310 {"reg_or_fp0_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2311 {"alpha_comparison_operator", {EQ, LE, LT, LEU, LTU}}, \
2312 {"alpha_swapped_comparison_operator", {EQ, GE, GT, GEU, GTU}}, \
2313 {"signed_comparison_operator", {EQ, NE, LE, LT, GE, GT}}, \
2314 {"alpha_fp_comparison_operator", {EQ, LE, LT, UNORDERED}}, \
2315 {"divmod_operator", {DIV, MOD, UDIV, UMOD}}, \
2316 {"fp0_operand", {CONST_DOUBLE}}, \
2317 {"current_file_function_operand", {SYMBOL_REF}}, \
2318 {"call_operand", {REG, SYMBOL_REF}}, \
2319 {"input_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
2320 SYMBOL_REF, CONST, LABEL_REF}}, \
2321 {"some_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
2322 SYMBOL_REF, CONST, LABEL_REF}}, \
2323 {"some_ni_operand", {SUBREG, REG, MEM}}, \
2324 {"aligned_memory_operand", {MEM}}, \
2325 {"unaligned_memory_operand", {MEM}}, \
2326 {"reg_or_unaligned_mem_operand", {SUBREG, REG, MEM}}, \
2327 {"any_memory_operand", {MEM}}, \
2328 {"hard_fp_register_operand", {SUBREG, REG}}, \
2329 {"reg_not_elim_operand", {SUBREG, REG}}, \
2330 {"reg_no_subreg_operand", {REG}}, \
2331 {"addition_operation", {PLUS}},
2333 /* Define the `__builtin_va_list' type for the ABI. */
2334 #define BUILD_VA_LIST_TYPE(VALIST) \
2335 (VALIST) = alpha_build_va_list ()
2337 /* Implement `va_start' for varargs and stdarg. */
2338 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
2339 alpha_va_start (stdarg, valist, nextarg)
2341 /* Implement `va_arg'. */
2342 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2343 alpha_va_arg (valist, type)
2345 /* Tell collect that the object format is ECOFF. */
2346 #define OBJECT_FORMAT_COFF
2347 #define EXTENDED_COFF
2349 /* If we use NM, pass -g to it so it only lists globals. */
2350 #define NM_FLAGS "-pg"
2352 /* Definitions for debugging. */
2354 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
2355 #define DBX_DEBUGGING_INFO /* generate embedded stabs */
2356 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
2358 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
2359 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
2363 /* Correct the offset of automatic variables and arguments. Note that
2364 the Alpha debug format wants all automatic variables and arguments
2365 to be in terms of two different offsets from the virtual frame pointer,
2366 which is the stack pointer before any adjustment in the function.
2367 The offset for the argument pointer is fixed for the native compiler,
2368 it is either zero (for the no arguments case) or large enough to hold
2369 all argument registers.
2370 The offset for the auto pointer is the fourth argument to the .frame
2371 directive (local_offset).
2372 To stay compatible with the native tools we use the same offsets
2373 from the virtual frame pointer and adjust the debugger arg/auto offsets
2374 accordingly. These debugger offsets are set up in output_prolog. */
2376 extern long alpha_arg_offset
;
2377 extern long alpha_auto_offset
;
2378 #define DEBUGGER_AUTO_OFFSET(X) \
2379 ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) + alpha_auto_offset)
2380 #define DEBUGGER_ARG_OFFSET(OFFSET, X) (OFFSET + alpha_arg_offset)
2383 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2384 alpha_output_lineno (STREAM, LINE)
2386 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
2387 alpha_output_filename (STREAM, NAME)
2389 /* mips-tfile.c limits us to strings of one page. We must underestimate this
2390 number, because the real length runs past this up to the next
2391 continuation point. This is really a dbxout.c bug. */
2392 #define DBX_CONTIN_LENGTH 3000
2394 /* By default, turn on GDB extensions. */
2395 #define DEFAULT_GDB_EXTENSIONS 1
2397 /* Stabs-in-ECOFF can't handle dbxout_function_end(). */
2398 #define NO_DBX_FUNCTION_END 1
2400 /* If we are smuggling stabs through the ALPHA ECOFF object
2401 format, put a comment in front of the .stab<x> operation so
2402 that the ALPHA assembler does not choke. The mips-tfile program
2403 will correctly put the stab into the object file. */
2405 #define ASM_STABS_OP ((TARGET_GAS) ? ".stabs" : " #.stabs")
2406 #define ASM_STABN_OP ((TARGET_GAS) ? ".stabn" : " #.stabn")
2407 #define ASM_STABD_OP ((TARGET_GAS) ? ".stabd" : " #.stabd")
2409 /* Forward references to tags are allowed. */
2410 #define SDB_ALLOW_FORWARD_REFERENCES
2412 /* Unknown tags are also allowed. */
2413 #define SDB_ALLOW_UNKNOWN_REFERENCES
2415 #define PUT_SDB_DEF(a) \
2417 fprintf (asm_out_file, "\t%s.def\t", \
2418 (TARGET_GAS) ? "" : "#"); \
2419 ASM_OUTPUT_LABELREF (asm_out_file, a); \
2420 fputc (';', asm_out_file); \
2423 #define PUT_SDB_PLAIN_DEF(a) \
2425 fprintf (asm_out_file, "\t%s.def\t.%s;", \
2426 (TARGET_GAS) ? "" : "#", (a)); \
2429 #define PUT_SDB_TYPE(a) \
2431 fprintf (asm_out_file, "\t.type\t0x%x;", (a)); \
2434 /* For block start and end, we create labels, so that
2435 later we can figure out where the correct offset is.
2436 The normal .ent/.end serve well enough for functions,
2437 so those are just commented out. */
2439 extern int sdb_label_count
; /* block start/end next label # */
2441 #define PUT_SDB_BLOCK_START(LINE) \
2443 fprintf (asm_out_file, \
2444 "$Lb%d:\n\t%s.begin\t$Lb%d\t%d\n", \
2446 (TARGET_GAS) ? "" : "#", \
2449 sdb_label_count++; \
2452 #define PUT_SDB_BLOCK_END(LINE) \
2454 fprintf (asm_out_file, \
2455 "$Le%d:\n\t%s.bend\t$Le%d\t%d\n", \
2457 (TARGET_GAS) ? "" : "#", \
2460 sdb_label_count++; \
2463 #define PUT_SDB_FUNCTION_START(LINE)
2465 #define PUT_SDB_FUNCTION_END(LINE)
2467 #define PUT_SDB_EPILOGUE_END(NAME) ((void)(NAME))
2469 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
2470 mips-tdump.c to print them out.
2472 These must match the corresponding definitions in gdb/mipsread.c.
2473 Unfortunately, gcc and gdb do not currently share any directories. */
2475 #define CODE_MASK 0x8F300
2476 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
2477 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
2478 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
2480 /* Override some mips-tfile definitions. */
2482 #define SHASH_SIZE 511
2483 #define THASH_SIZE 55
2485 /* Align ecoff symbol tables to avoid OSF1/1.3 nm complaints. */
2487 #define ALIGN_SYMTABLE_OFFSET(OFFSET) (((OFFSET) + 7) & ~7)
2489 /* The linker will stick __main into the .init section. */
2490 #define HAS_INIT_SECTION
2491 #define LD_INIT_SWITCH "-init"
2492 #define LD_FINI_SWITCH "-fini"
2494 /* The system headers under Alpha systems are generally C++-aware. */
2495 #define NO_IMPLICIT_EXTERN_C
2497 /* Generate calls to memcpy, etc., not bcopy, etc. */
2498 #define TARGET_MEM_FUNCTIONS 1