1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992-2019 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
23 ;; Uses of UNSPEC in this file:
25 (define_c_enum "unspec" [
65 (define_c_enum "unspecv" [
68 UNSPECV_SETJMPR ; builtin_setjmp_receiver
69 UNSPECV_LONGJMP ; builtin_longjmp
71 UNSPECV_PSPL ; prologue_stack_probe_loop
73 UNSPECV_EHR ; exception_receiver
77 UNSPECV_PLDGP2 ; prologue ldgp
80 UNSPECV_SETJMPR_ER ; builtin_setjmp_receiver fragment
81 UNSPECV_LL ; load-locked
82 UNSPECV_SC ; store-conditional
86 ;; On non-BWX targets, CQImode must be handled the similarly to HImode
87 ;; when generating reloads.
88 (define_mode_iterator RELOAD12 [QI HI CQI])
89 (define_mode_attr reloadmode [(QI "qi") (HI "hi") (CQI "hi")])
91 ;; Other mode iterators
92 (define_mode_iterator IMODE [QI HI SI DI])
93 (define_mode_iterator I12MODE [QI HI])
94 (define_mode_iterator I124MODE [QI HI SI])
95 (define_mode_iterator I24MODE [HI SI])
96 (define_mode_iterator I248MODE [HI SI DI])
97 (define_mode_iterator I48MODE [SI DI])
99 (define_mode_attr DWI [(SI "DI") (DI "TI")])
100 (define_mode_attr modesuffix [(QI "b") (HI "w") (SI "l") (DI "q")
101 (V8QI "b8") (V4HI "w4")
102 (SF "%,") (DF "%-")])
103 (define_mode_attr vecmodesuffix [(QI "b8") (HI "w4")])
105 (define_code_iterator any_maxmin [smax smin umax umin])
107 (define_code_attr maxmin [(smax "maxs") (smin "mins")
108 (umax "maxu") (umin "minu")])
110 ;; Where necessary, the suffixes _le and _be are used to distinguish between
111 ;; little-endian and big-endian patterns.
113 ;; Note that the Unicos/Mk assembler does not support the following
114 ;; opcodes: mov, fmov, nop, fnop, unop.
116 ;; Processor type -- this attribute must exactly match the processor_type
117 ;; enumeration in alpha.h.
119 (define_attr "tune" "ev4,ev5,ev6"
120 (const (symbol_ref "((enum attr_tune) alpha_tune)")))
122 ;; Define an insn type attribute. This is used in function unit delay
123 ;; computations, among other purposes. For the most part, we use the names
124 ;; defined in the EV4 documentation, but add a few that we have to know about
128 "ild,fld,ldsym,ist,fst,ibr,callpal,fbr,jsr,iadd,ilog,shift,icmov,fcmov,
129 icmp,imul,fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,mb,ld_l,st_c,
131 (const_string "iadd"))
133 ;; Describe a user's asm statement.
134 (define_asm_attributes
135 [(set_attr "type" "multi")])
137 ;; Define the operand size an insn operates on. Used primarily by mul
138 ;; and div operations that have size dependent timings.
140 (define_attr "opsize" "si,di,udi"
143 ;; The TRAP attribute marks instructions that may generate traps
144 ;; (which are imprecise and may need a trapb if software completion
147 (define_attr "trap" "no,yes"
150 ;; The ROUND_SUFFIX attribute marks which instructions require a
151 ;; rounding-mode suffix. The value NONE indicates no suffix,
152 ;; the value NORMAL indicates a suffix controlled by alpha_fprm.
154 (define_attr "round_suffix" "none,normal,c"
155 (const_string "none"))
157 ;; The TRAP_SUFFIX attribute marks instructions requiring a trap-mode suffix:
159 ;; SU accepts only /su (cmpt et al)
160 ;; SUI accepts only /sui (cvtqt and cvtqs)
161 ;; V_SV accepts /v and /sv (cvtql only)
162 ;; V_SV_SVI accepts /v, /sv and /svi (cvttq only)
163 ;; U_SU_SUI accepts /u, /su and /sui (most fp instructions)
165 ;; The actual suffix emitted is controlled by alpha_fptm.
167 (define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui"
168 (const_string "none"))
170 ;; The length of an instruction sequence in bytes.
172 (define_attr "length" ""
175 ;; The USEGP attribute marks instructions that have relocations that use
178 (define_attr "usegp" "no,yes"
179 (cond [(eq_attr "type" "ldsym,jsr")
181 (eq_attr "type" "ild,fld,ist,fst")
182 (symbol_ref "((enum attr_usegp) alpha_find_lo_sum_using_gp (insn))")
184 (const_string "no")))
186 ;; The CANNOT_COPY attribute marks instructions with relocations that
187 ;; cannot easily be duplicated. This includes insns with gpdisp relocs
188 ;; since they have to stay in 1-1 correspondence with one another. This
189 ;; also includes jsr insns, since they must stay in correspondence with
190 ;; the immediately following gpdisp instructions.
192 (define_attr "cannot_copy" "false,true"
193 (const_string "false"))
195 ;; Used to control the "enabled" attribute on a per-instruction basis.
196 ;; For convenience, conflate ABI issues re loading of addresses with
198 (define_attr "isa" "base,bwx,max,fix,cix,vms,ner,er"
199 (const_string "base"))
201 (define_attr "enabled" ""
202 (cond [(eq_attr "isa" "bwx") (symbol_ref "TARGET_BWX")
203 (eq_attr "isa" "max") (symbol_ref "TARGET_MAX")
204 (eq_attr "isa" "fix") (symbol_ref "TARGET_FIX")
205 (eq_attr "isa" "cix") (symbol_ref "TARGET_CIX")
206 (eq_attr "isa" "vms") (symbol_ref "TARGET_ABI_OPEN_VMS")
207 (eq_attr "isa" "ner") (symbol_ref "!TARGET_EXPLICIT_RELOCS")
208 (eq_attr "isa" "er") (symbol_ref "TARGET_EXPLICIT_RELOCS")
212 ;; Include scheduling descriptions.
219 ;; Operand and operator predicates and constraints
221 (include "predicates.md")
222 (include "constraints.md")
225 ;; First define the arithmetic insns. Note that the 32-bit forms also
228 ;; Handle 32-64 bit extension from memory to a floating point register
229 ;; specially, since this occurs frequently in int->double conversions.
231 ;; Note that while we must retain the =f case in the insn for reload's
232 ;; benefit, it should be eliminated after reload, so we should never emit
233 ;; code for that case. But we don't reject the possibility.
235 (define_expand "extendsidi2"
236 [(set (match_operand:DI 0 "register_operand")
237 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand")))])
239 (define_insn "*cvtlq"
240 [(set (match_operand:DI 0 "register_operand" "=f")
241 (unspec:DI [(match_operand:SF 1 "reg_or_0_operand" "fG")]
245 [(set_attr "type" "fadd")])
247 (define_insn "*extendsidi2_1"
248 [(set (match_operand:DI 0 "register_operand" "=r,r,!*f")
250 (match_operand:SI 1 "nonimmediate_operand" "r,m,m")))]
255 lds %0,%1\;cvtlq %0,%0"
256 [(set_attr "type" "iadd,ild,fld")
257 (set_attr "length" "*,*,8")])
260 [(set (match_operand:DI 0 "hard_fp_register_operand")
261 (sign_extend:DI (match_operand:SI 1 "memory_operand")))]
263 [(set (match_dup 2) (match_dup 1))
264 (set (match_dup 0) (unspec:DI [(match_dup 2)] UNSPEC_CVTLQ))]
266 operands[1] = adjust_address (operands[1], SFmode, 0);
267 operands[2] = gen_rtx_REG (SFmode, REGNO (operands[0]));
270 ;; Optimize sign-extension of SImode loads. This shows up in the wake of
271 ;; reload when converting fp->int.
274 [(set (match_operand:SI 0 "hard_int_register_operand")
275 (match_operand:SI 1 "memory_operand"))
276 (set (match_operand:DI 2 "hard_int_register_operand")
277 (sign_extend:DI (match_dup 0)))]
278 "true_regnum (operands[0]) == true_regnum (operands[2])
279 || peep2_reg_dead_p (2, operands[0])"
281 (sign_extend:DI (match_dup 1)))])
283 (define_insn "addsi3"
284 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
285 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
286 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
295 [(set (match_operand:SI 0 "register_operand")
296 (plus:SI (match_operand:SI 1 "register_operand")
297 (match_operand:SI 2 "const_int_operand")))]
298 "! add_operand (operands[2], SImode)"
299 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
300 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
302 HOST_WIDE_INT val = INTVAL (operands[2]);
303 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
304 HOST_WIDE_INT rest = val - low;
306 operands[3] = GEN_INT (rest);
307 operands[4] = GEN_INT (low);
310 (define_insn "*addsi_se"
311 [(set (match_operand:DI 0 "register_operand" "=r,r")
313 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
314 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
320 (define_insn "*addsi_se2"
321 [(set (match_operand:DI 0 "register_operand" "=r,r")
323 (subreg:SI (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
324 (match_operand:DI 2 "sext_add_operand" "rI,O"))
332 [(set (match_operand:DI 0 "register_operand")
334 (plus:SI (match_operand:SI 1 "reg_not_elim_operand")
335 (match_operand:SI 2 "const_int_operand"))))
336 (clobber (match_operand:SI 3 "reg_not_elim_operand"))]
337 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
338 && INTVAL (operands[2]) % 4 == 0"
339 [(set (match_dup 3) (match_dup 4))
340 (set (match_dup 0) (sign_extend:DI (plus:SI (ashift:SI (match_dup 3)
344 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
350 operands[4] = GEN_INT (val);
351 operands[5] = GEN_INT (exact_log2 (mult));
355 [(set (match_operand:DI 0 "register_operand")
357 (plus:SI (match_operator:SI 1 "comparison_operator"
360 (match_operand:SI 4 "add_operand"))))
361 (clobber (match_operand:DI 5 "register_operand"))]
363 [(set (match_dup 5) (match_dup 6))
364 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
366 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
367 operands[2], operands[3]);
368 operands[7] = gen_lowpart (SImode, operands[5]);
371 (define_expand "adddi3"
372 [(set (match_operand:DI 0 "register_operand")
373 (plus:DI (match_operand:DI 1 "register_operand")
374 (match_operand:DI 2 "add_operand")))])
376 (define_insn "*adddi_er_lo16_dtp"
377 [(set (match_operand:DI 0 "register_operand" "=r")
378 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
379 (match_operand:DI 2 "dtp16_symbolic_operand")))]
381 "lda %0,%2(%1)\t\t!dtprel")
383 (define_insn "*adddi_er_hi32_dtp"
384 [(set (match_operand:DI 0 "register_operand" "=r")
385 (plus:DI (match_operand:DI 1 "register_operand" "r")
386 (high:DI (match_operand:DI 2 "dtp32_symbolic_operand"))))]
388 "ldah %0,%2(%1)\t\t!dtprelhi")
390 (define_insn "*adddi_er_lo32_dtp"
391 [(set (match_operand:DI 0 "register_operand" "=r")
392 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
393 (match_operand:DI 2 "dtp32_symbolic_operand")))]
395 "lda %0,%2(%1)\t\t!dtprello")
397 (define_insn "*adddi_er_lo16_tp"
398 [(set (match_operand:DI 0 "register_operand" "=r")
399 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
400 (match_operand:DI 2 "tp16_symbolic_operand")))]
402 "lda %0,%2(%1)\t\t!tprel")
404 (define_insn "*adddi_er_hi32_tp"
405 [(set (match_operand:DI 0 "register_operand" "=r")
406 (plus:DI (match_operand:DI 1 "register_operand" "r")
407 (high:DI (match_operand:DI 2 "tp32_symbolic_operand"))))]
409 "ldah %0,%2(%1)\t\t!tprelhi")
411 (define_insn "*adddi_er_lo32_tp"
412 [(set (match_operand:DI 0 "register_operand" "=r")
413 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
414 (match_operand:DI 2 "tp32_symbolic_operand")))]
416 "lda %0,%2(%1)\t\t!tprello")
418 (define_insn "*adddi_er_high_l"
419 [(set (match_operand:DI 0 "register_operand" "=r")
420 (plus:DI (match_operand:DI 1 "register_operand" "r")
421 (high:DI (match_operand:DI 2 "local_symbolic_operand"))))]
422 "TARGET_EXPLICIT_RELOCS && reload_completed"
423 "ldah %0,%2(%1)\t\t!gprelhigh"
424 [(set_attr "usegp" "yes")])
427 [(set (match_operand:DI 0 "register_operand")
428 (high:DI (match_operand:DI 1 "local_symbolic_operand")))]
429 "TARGET_EXPLICIT_RELOCS && reload_completed"
431 (plus:DI (match_dup 2) (high:DI (match_dup 1))))]
432 "operands[2] = pic_offset_table_rtx;")
434 ;; We used to expend quite a lot of effort choosing addq/subq/lda.
435 ;; With complications like
437 ;; The NT stack unwind code can't handle a subq to adjust the stack
438 ;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3,
439 ;; the exception handling code will loop if a subq is used and an
442 ;; The 19980616 change to emit prologues as RTL also confused some
443 ;; versions of GDB, which also interprets prologues. This has been
444 ;; fixed as of GDB 4.18, but it does not harm to unconditionally
447 ;; and the fact that the three insns schedule exactly the same, it's
448 ;; just not worth the effort.
450 (define_insn "*adddi_internal"
451 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
452 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r")
453 (match_operand:DI 2 "add_operand" "r,K,L")))]
460 ;; ??? Allow large constants when basing off the frame pointer or some
461 ;; virtual register that may eliminate to the frame pointer. This is
462 ;; done because register elimination offsets will change the hi/lo split,
463 ;; and if we split before reload, we will require additional instructions.
465 (define_insn "*adddi_fp_hack"
466 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
467 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r,r,r")
468 (match_operand:DI 2 "const_int_operand" "K,L,n")))]
469 "NONSTRICT_REG_OK_FP_BASE_P (operands[1])
470 && INTVAL (operands[2]) >= 0
471 /* This is the largest constant an lda+ldah pair can add, minus
472 an upper bound on the displacement between SP and AP during
473 register elimination. See INITIAL_ELIMINATION_OFFSET. */
474 && INTVAL (operands[2])
476 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD
477 - ALPHA_ROUND(crtl->outgoing_args_size)
478 - (ALPHA_ROUND (get_frame_size ()
479 + max_reg_num () * UNITS_PER_WORD
480 + crtl->args.pretend_args_size)
481 - crtl->args.pretend_args_size))"
487 ;; Don't do this if we are adjusting SP since we don't want to do it
488 ;; in two steps. Don't split FP sources for the reason listed above.
490 [(set (match_operand:DI 0 "register_operand")
491 (plus:DI (match_operand:DI 1 "register_operand")
492 (match_operand:DI 2 "const_int_operand")))]
493 "! add_operand (operands[2], DImode)
494 && operands[0] != stack_pointer_rtx
495 && operands[1] != frame_pointer_rtx
496 && operands[1] != arg_pointer_rtx"
497 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
498 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
500 HOST_WIDE_INT val = INTVAL (operands[2]);
501 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
502 HOST_WIDE_INT rest = val - low;
503 rtx rest_rtx = GEN_INT (rest);
505 operands[4] = GEN_INT (low);
506 if (satisfies_constraint_L (rest_rtx))
507 operands[3] = rest_rtx;
508 else if (can_create_pseudo_p ())
510 operands[3] = gen_reg_rtx (DImode);
511 emit_move_insn (operands[3], operands[2]);
512 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
519 (define_insn "*sadd<modesuffix>"
520 [(set (match_operand:I48MODE 0 "register_operand" "=r,r")
522 (ashift:I48MODE (match_operand:I48MODE 1 "reg_not_elim_operand" "r,r")
523 (match_operand:I48MODE 2 "const23_operand" "I,I"))
524 (match_operand:I48MODE 3 "sext_add_operand" "rI,O")))]
527 s%P2add<modesuffix> %1,%3,%0
528 s%P2sub<modesuffix> %1,%n3,%0")
530 (define_insn "*saddl_se"
531 [(set (match_operand:DI 0 "register_operand" "=r,r")
534 (ashift:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
535 (match_operand:SI 2 "const23_operand" "I,I"))
536 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
543 [(set (match_operand:DI 0 "register_operand")
545 (plus:SI (ashift:SI (match_operator:SI 1 "comparison_operator"
548 (match_operand:SI 4 "const23_operand"))
549 (match_operand:SI 5 "sext_add_operand"))))
550 (clobber (match_operand:DI 6 "reg_not_elim_operand"))]
552 [(set (match_dup 6) (match_dup 7))
554 (sign_extend:DI (plus:SI (ashift:SI (match_dup 8) (match_dup 4))
557 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
558 operands[2], operands[3]);
559 operands[8] = gen_lowpart (SImode, operands[6]);
562 (define_insn "addv<mode>3"
563 [(set (match_operand:I48MODE 0 "register_operand" "=r,r")
564 (plus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "%rJ,rJ")
565 (match_operand:I48MODE 2 "sext_add_operand" "rI,O")))
566 (trap_if (ne (plus:<DWI> (sign_extend:<DWI> (match_dup 1))
567 (sign_extend:<DWI> (match_dup 2)))
568 (sign_extend:<DWI> (plus:I48MODE (match_dup 1)
573 add<modesuffix>v %r1,%2,%0
574 sub<modesuffix>v %r1,%n2,%0")
576 (define_insn "neg<mode>2"
577 [(set (match_operand:I48MODE 0 "register_operand" "=r")
578 (neg:I48MODE (match_operand:I48MODE 1 "reg_or_8bit_operand" "rI")))]
580 "sub<modesuffix> $31,%1,%0")
582 (define_insn "*negsi_se"
583 [(set (match_operand:DI 0 "register_operand" "=r")
584 (sign_extend:DI (neg:SI
585 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
589 (define_insn "negv<mode>2"
590 [(set (match_operand:I48MODE 0 "register_operand" "=r")
591 (neg:I48MODE (match_operand:I48MODE 1 "register_operand" "r")))
592 (trap_if (ne (neg:<DWI> (sign_extend:<DWI> (match_dup 1)))
593 (sign_extend:<DWI> (neg:I48MODE (match_dup 1))))
596 "sub<modesuffix>v $31,%1,%0")
598 (define_insn "sub<mode>3"
599 [(set (match_operand:I48MODE 0 "register_operand" "=r")
600 (minus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "rJ")
601 (match_operand:I48MODE 2 "reg_or_8bit_operand" "rI")))]
603 "sub<modesuffix> %r1,%2,%0")
605 (define_insn "*subsi_se"
606 [(set (match_operand:DI 0 "register_operand" "=r")
608 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
609 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
613 (define_insn "*subsi_se2"
614 [(set (match_operand:DI 0 "register_operand" "=r")
616 (subreg:SI (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
617 (match_operand:DI 2 "reg_or_8bit_operand" "rI"))
622 (define_insn "*ssub<modesuffix>"
623 [(set (match_operand:I48MODE 0 "register_operand" "=r")
625 (ashift:I48MODE (match_operand:I48MODE 1 "reg_not_elim_operand" "r")
626 (match_operand:I48MODE 2 "const23_operand" "I"))
627 (match_operand:I48MODE 3 "reg_or_8bit_operand" "rI")))]
629 "s%P2sub<modesuffix> %1,%3,%0")
631 (define_insn "*ssubl_se"
632 [(set (match_operand:DI 0 "register_operand" "=r")
635 (ashift:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
636 (match_operand:SI 2 "const23_operand" "I"))
637 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
641 (define_insn "subv<mode>3"
642 [(set (match_operand:I48MODE 0 "register_operand" "=r")
643 (minus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "rJ")
644 (match_operand:I48MODE 2 "reg_or_8bit_operand" "rI")))
645 (trap_if (ne (minus:<DWI> (sign_extend:<DWI> (match_dup 1))
646 (sign_extend:<DWI> (match_dup 2)))
647 (sign_extend:<DWI> (minus:I48MODE (match_dup 1)
651 "sub<modesuffix>v %r1,%2,%0")
653 (define_insn "mul<mode>3"
654 [(set (match_operand:I48MODE 0 "register_operand" "=r")
655 (mult:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "%rJ")
656 (match_operand:I48MODE 2 "reg_or_8bit_operand" "rI")))]
658 "mul<modesuffix> %r1,%2,%0"
659 [(set_attr "type" "imul")
660 (set_attr "opsize" "<mode>")])
662 (define_insn "*mulsi_se"
663 [(set (match_operand:DI 0 "register_operand" "=r")
665 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
666 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
669 [(set_attr "type" "imul")
670 (set_attr "opsize" "si")])
672 (define_insn "mulv<mode>3"
673 [(set (match_operand:I48MODE 0 "register_operand" "=r")
674 (mult:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "%rJ")
675 (match_operand:I48MODE 2 "reg_or_8bit_operand" "rI")))
676 (trap_if (ne (mult:<DWI> (sign_extend:<DWI> (match_dup 1))
677 (sign_extend:<DWI> (match_dup 2)))
678 (sign_extend:<DWI> (mult:I48MODE (match_dup 1)
682 "mul<modesuffix>v %r1,%2,%0"
683 [(set_attr "type" "imul")
684 (set_attr "opsize" "<mode>")])
686 (define_expand "umuldi3_highpart"
687 [(set (match_operand:DI 0 "register_operand")
690 (mult:TI (zero_extend:TI
691 (match_operand:DI 1 "register_operand"))
692 (match_operand:DI 2 "reg_or_8bit_operand"))
696 if (REG_P (operands[2]))
697 operands[2] = gen_rtx_ZERO_EXTEND (TImode, operands[2]);
700 (define_insn "*umuldi3_highpart_reg"
701 [(set (match_operand:DI 0 "register_operand" "=r")
704 (mult:TI (zero_extend:TI
705 (match_operand:DI 1 "register_operand" "r"))
707 (match_operand:DI 2 "register_operand" "r")))
711 [(set_attr "type" "imul")
712 (set_attr "opsize" "udi")])
714 (define_insn "*umuldi3_highpart_const"
715 [(set (match_operand:DI 0 "register_operand" "=r")
718 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
719 (match_operand:TI 2 "cint8_operand" "I"))
723 [(set_attr "type" "imul")
724 (set_attr "opsize" "udi")])
726 (define_expand "umulditi3"
727 [(set (match_operand:TI 0 "register_operand")
729 (zero_extend:TI (match_operand:DI 1 "reg_no_subreg_operand"))
730 (zero_extend:TI (match_operand:DI 2 "reg_no_subreg_operand"))))]
733 rtx l = gen_reg_rtx (DImode), h = gen_reg_rtx (DImode);
734 emit_insn (gen_muldi3 (l, operands[1], operands[2]));
735 emit_insn (gen_umuldi3_highpart (h, operands[1], operands[2]));
736 emit_move_insn (gen_lowpart (DImode, operands[0]), l);
737 emit_move_insn (gen_highpart (DImode, operands[0]), h);
741 ;; The divide and remainder operations take their inputs from r24 and
742 ;; r25, put their output in r27, and clobber r23 and r28 on all systems.
744 ;; ??? Force sign-extension here because some versions of OSF/1 and
745 ;; Interix/NT don't do the right thing if the inputs are not properly
746 ;; sign-extended. But Linux, for instance, does not have this
747 ;; problem. Is it worth the complication here to eliminate the sign
750 (define_code_iterator any_divmod [div mod udiv umod])
752 (define_expand "<code>si3"
754 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand")))
756 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand")))
757 (parallel [(set (match_dup 5)
759 (any_divmod:SI (match_dup 3) (match_dup 4))))
760 (clobber (reg:DI 23))
761 (clobber (reg:DI 28))])
762 (set (match_operand:SI 0 "nonimmediate_operand")
763 (subreg:SI (match_dup 5) 0))]
766 operands[3] = gen_reg_rtx (DImode);
767 operands[4] = gen_reg_rtx (DImode);
768 operands[5] = gen_reg_rtx (DImode);
771 (define_expand "<code>di3"
772 [(parallel [(set (match_operand:DI 0 "register_operand")
774 (match_operand:DI 1 "register_operand")
775 (match_operand:DI 2 "register_operand")))
776 (clobber (reg:DI 23))
777 (clobber (reg:DI 28))])]
780 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
781 ;; expanded by the assembler.
783 (define_insn_and_split "*divmodsi_internal_er"
784 [(set (match_operand:DI 0 "register_operand" "=c")
785 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
786 [(match_operand:DI 1 "register_operand" "a")
787 (match_operand:DI 2 "register_operand" "b")])))
788 (clobber (reg:DI 23))
789 (clobber (reg:DI 28))]
790 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
792 "&& reload_completed"
793 [(parallel [(set (match_dup 0)
794 (sign_extend:DI (match_dup 3)))
797 (clobber (reg:DI 23))
798 (clobber (reg:DI 28))])]
801 switch (GET_CODE (operands[3]))
818 operands[4] = GEN_INT (alpha_next_sequence_number++);
819 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
820 gen_rtx_SYMBOL_REF (DImode, str),
823 [(set_attr "type" "jsr")
824 (set_attr "length" "8")])
826 (define_insn "*divmodsi_internal_er_1"
827 [(set (match_operand:DI 0 "register_operand" "=c")
828 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
829 [(match_operand:DI 1 "register_operand" "a")
830 (match_operand:DI 2 "register_operand" "b")])))
831 (use (match_operand:DI 4 "register_operand" "c"))
832 (use (match_operand 5 "const_int_operand"))
833 (clobber (reg:DI 23))
834 (clobber (reg:DI 28))]
835 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
836 "jsr $23,($27),__%E3%j5"
837 [(set_attr "type" "jsr")
838 (set_attr "length" "4")])
840 (define_insn "*divmodsi_internal"
841 [(set (match_operand:DI 0 "register_operand" "=c")
842 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
843 [(match_operand:DI 1 "register_operand" "a")
844 (match_operand:DI 2 "register_operand" "b")])))
845 (clobber (reg:DI 23))
846 (clobber (reg:DI 28))]
849 [(set_attr "type" "jsr")
850 (set_attr "length" "8")])
852 (define_insn_and_split "*divmoddi_internal_er"
853 [(set (match_operand:DI 0 "register_operand" "=c")
854 (match_operator:DI 3 "divmod_operator"
855 [(match_operand:DI 1 "register_operand" "a")
856 (match_operand:DI 2 "register_operand" "b")]))
857 (clobber (reg:DI 23))
858 (clobber (reg:DI 28))]
859 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
861 "&& reload_completed"
862 [(parallel [(set (match_dup 0) (match_dup 3))
865 (clobber (reg:DI 23))
866 (clobber (reg:DI 28))])]
869 switch (GET_CODE (operands[3]))
886 operands[4] = GEN_INT (alpha_next_sequence_number++);
887 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
888 gen_rtx_SYMBOL_REF (DImode, str),
891 [(set_attr "type" "jsr")
892 (set_attr "length" "8")])
894 (define_insn "*divmoddi_internal_er_1"
895 [(set (match_operand:DI 0 "register_operand" "=c")
896 (match_operator:DI 3 "divmod_operator"
897 [(match_operand:DI 1 "register_operand" "a")
898 (match_operand:DI 2 "register_operand" "b")]))
899 (use (match_operand:DI 4 "register_operand" "c"))
900 (use (match_operand 5 "const_int_operand"))
901 (clobber (reg:DI 23))
902 (clobber (reg:DI 28))]
903 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
904 "jsr $23,($27),__%E3%j5"
905 [(set_attr "type" "jsr")
906 (set_attr "length" "4")])
908 (define_insn "*divmoddi_internal"
909 [(set (match_operand:DI 0 "register_operand" "=c")
910 (match_operator:DI 3 "divmod_operator"
911 [(match_operand:DI 1 "register_operand" "a")
912 (match_operand:DI 2 "register_operand" "b")]))
913 (clobber (reg:DI 23))
914 (clobber (reg:DI 28))]
917 [(set_attr "type" "jsr")
918 (set_attr "length" "8")])
920 ;; Next are the basic logical operations. We only expose the DImode operations
921 ;; to the rtl expanders, but SImode versions exist for combine as well as for
922 ;; the atomic operation splitters.
924 (define_insn "*andsi_internal"
925 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
926 (and:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
927 (match_operand:SI 2 "and_operand" "rI,N,M")))]
933 [(set_attr "type" "ilog,ilog,shift")])
935 (define_insn "anddi3"
936 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
937 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
938 (match_operand:DI 2 "and_operand" "rI,N,M")))]
944 [(set_attr "type" "ilog,ilog,shift")])
946 ;; There are times when we can split an AND into two AND insns. This occurs
947 ;; when we can first clear any bytes and then clear anything else. For
948 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
949 ;; Only do this when running on 64-bit host since the computations are
950 ;; too messy otherwise.
953 [(set (match_operand:DI 0 "register_operand")
954 (and:DI (match_operand:DI 1 "register_operand")
955 (match_operand:DI 2 "const_int_operand")))]
956 "! and_operand (operands[2], DImode)"
957 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
958 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
960 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
961 unsigned HOST_WIDE_INT mask2 = mask1;
964 /* For each byte that isn't all zeros, make it all ones. */
965 for (i = 0; i < 64; i += 8)
966 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
967 mask1 |= (HOST_WIDE_INT) 0xff << i;
969 /* Now turn on any bits we've just turned off. */
972 operands[3] = GEN_INT (mask1);
973 operands[4] = GEN_INT (mask2);
976 (define_insn "zero_extendqi<mode>2"
977 [(set (match_operand:I248MODE 0 "register_operand" "=r,r")
978 (zero_extend:I248MODE
979 (match_operand:QI 1 "reg_or_bwx_memory_operand" "r,m")))]
984 [(set_attr "type" "ilog,ild")
985 (set_attr "isa" "*,bwx")])
987 (define_insn "zero_extendhi<mode>2"
988 [(set (match_operand:I48MODE 0 "register_operand" "=r,r")
990 (match_operand:HI 1 "reg_or_bwx_memory_operand" "r,m")))]
995 [(set_attr "type" "shift,ild")
996 (set_attr "isa" "*,bwx")])
998 (define_insn "zero_extendsidi2"
999 [(set (match_operand:DI 0 "register_operand" "=r")
1000 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1003 [(set_attr "type" "shift")])
1005 (define_insn "andnot<mode>3"
1006 [(set (match_operand:I48MODE 0 "register_operand" "=r")
1008 (not:I48MODE (match_operand:I48MODE 1 "reg_or_8bit_operand" "rI"))
1009 (match_operand:I48MODE 2 "reg_or_0_operand" "rJ")))]
1012 [(set_attr "type" "ilog")])
1014 (define_insn "*iorsi_internal"
1015 [(set (match_operand:SI 0 "register_operand" "=r,r")
1016 (ior:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
1017 (match_operand:SI 2 "or_operand" "rI,N")))]
1022 [(set_attr "type" "ilog")])
1024 (define_insn "iordi3"
1025 [(set (match_operand:DI 0 "register_operand" "=r,r")
1026 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1027 (match_operand:DI 2 "or_operand" "rI,N")))]
1032 [(set_attr "type" "ilog")])
1034 (define_insn "*one_cmplsi_internal"
1035 [(set (match_operand:SI 0 "register_operand" "=r")
1036 (not:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
1039 [(set_attr "type" "ilog")])
1041 (define_insn "one_cmpldi2"
1042 [(set (match_operand:DI 0 "register_operand" "=r")
1043 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
1046 [(set_attr "type" "ilog")])
1048 (define_insn "*iornot<mode>3"
1049 [(set (match_operand:I48MODE 0 "register_operand" "=r")
1051 (not:I48MODE (match_operand:I48MODE 1 "reg_or_8bit_operand" "rI"))
1052 (match_operand:I48MODE 2 "reg_or_0_operand" "rJ")))]
1055 [(set_attr "type" "ilog")])
1057 (define_insn "*xorsi_internal"
1058 [(set (match_operand:SI 0 "register_operand" "=r,r")
1059 (xor:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
1060 (match_operand:SI 2 "or_operand" "rI,N")))]
1065 [(set_attr "type" "ilog")])
1067 (define_insn "xordi3"
1068 [(set (match_operand:DI 0 "register_operand" "=r,r")
1069 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1070 (match_operand:DI 2 "or_operand" "rI,N")))]
1075 [(set_attr "type" "ilog")])
1077 (define_insn "*xornot<mode>3"
1078 [(set (match_operand:I48MODE 0 "register_operand" "=r")
1079 (not:I48MODE (xor:I48MODE
1080 (match_operand:I48MODE 1 "register_operand" "%rJ")
1081 (match_operand:I48MODE 2 "register_operand" "rI"))))]
1084 [(set_attr "type" "ilog")])
1086 ;; Handle FFS and related insns iff we support CIX.
1088 (define_expand "ffsdi2"
1090 (ctz:DI (match_operand:DI 1 "register_operand")))
1092 (plus:DI (match_dup 2) (const_int 1)))
1093 (set (match_operand:DI 0 "register_operand")
1094 (if_then_else:DI (eq (match_dup 1) (const_int 0))
1095 (const_int 0) (match_dup 3)))]
1098 operands[2] = gen_reg_rtx (DImode);
1099 operands[3] = gen_reg_rtx (DImode);
1102 (define_insn "clzdi2"
1103 [(set (match_operand:DI 0 "register_operand" "=r")
1104 (clz:DI (match_operand:DI 1 "register_operand" "r")))]
1107 [(set_attr "type" "mvi")])
1109 (define_insn "ctzdi2"
1110 [(set (match_operand:DI 0 "register_operand" "=r")
1111 (ctz:DI (match_operand:DI 1 "register_operand" "r")))]
1114 [(set_attr "type" "mvi")])
1116 (define_insn "popcountdi2"
1117 [(set (match_operand:DI 0 "register_operand" "=r")
1118 (popcount:DI (match_operand:DI 1 "register_operand" "r")))]
1121 [(set_attr "type" "mvi")])
1123 (define_expand "bswapsi2"
1124 [(set (match_operand:SI 0 "register_operand")
1125 (bswap:SI (match_operand:SI 1 "register_operand")))]
1130 t0 = gen_reg_rtx (DImode);
1131 t1 = gen_reg_rtx (DImode);
1133 emit_insn (gen_inslh (t0, gen_lowpart (DImode, operands[1]), GEN_INT (7)));
1134 emit_insn (gen_inswl_const (t1, gen_lowpart (HImode, operands[1]),
1136 emit_insn (gen_iordi3 (t1, t0, t1));
1137 emit_insn (gen_lshrdi3 (t0, t1, GEN_INT (16)));
1138 emit_insn (gen_anddi3 (t1, t1, alpha_expand_zap_mask (0x5)));
1139 emit_insn (gen_anddi3 (t0, t0, alpha_expand_zap_mask (0xa)));
1140 emit_insn (gen_addsi3 (operands[0], gen_lowpart (SImode, t0),
1141 gen_lowpart (SImode, t1)));
1145 (define_expand "bswapdi2"
1146 [(set (match_operand:DI 0 "register_operand")
1147 (bswap:DI (match_operand:DI 1 "register_operand")))]
1152 t0 = gen_reg_rtx (DImode);
1153 t1 = gen_reg_rtx (DImode);
1155 /* This method of shifting and masking is not specific to Alpha, but
1156 is only profitable on Alpha because of our handy byte zap insn. */
1158 emit_insn (gen_lshrdi3 (t0, operands[1], GEN_INT (32)));
1159 emit_insn (gen_ashldi3 (t1, operands[1], GEN_INT (32)));
1160 emit_insn (gen_iordi3 (t1, t0, t1));
1162 emit_insn (gen_lshrdi3 (t0, t1, GEN_INT (16)));
1163 emit_insn (gen_ashldi3 (t1, t1, GEN_INT (16)));
1164 emit_insn (gen_anddi3 (t0, t0, alpha_expand_zap_mask (0xcc)));
1165 emit_insn (gen_anddi3 (t1, t1, alpha_expand_zap_mask (0x33)));
1166 emit_insn (gen_iordi3 (t1, t0, t1));
1168 emit_insn (gen_lshrdi3 (t0, t1, GEN_INT (8)));
1169 emit_insn (gen_ashldi3 (t1, t1, GEN_INT (8)));
1170 emit_insn (gen_anddi3 (t0, t0, alpha_expand_zap_mask (0xaa)));
1171 emit_insn (gen_anddi3 (t1, t1, alpha_expand_zap_mask (0x55)));
1172 emit_insn (gen_iordi3 (operands[0], t0, t1));
1176 ;; Next come the shifts and the various extract and insert operations.
1178 (define_insn "ashldi3"
1179 [(set (match_operand:DI 0 "register_operand" "=r,r")
1180 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
1181 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
1184 switch (which_alternative)
1187 if (operands[2] == const1_rtx)
1188 return "addq %r1,%r1,%0";
1190 return "s%P2addq %r1,0,%0";
1192 return "sll %r1,%2,%0";
1197 [(set_attr "type" "iadd,shift")])
1199 (define_insn "ashlsi3"
1200 [(set (match_operand:SI 0 "register_operand" "=r")
1201 (ashift:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
1202 (match_operand:SI 2 "const123_operand" "P")))]
1205 if (operands[2] == const1_rtx)
1206 return "addl %r1,%r1,%0";
1208 return "s%P2addl %r1,0,%0";
1210 [(set_attr "type" "iadd")])
1212 (define_insn "*ashlsi_se"
1213 [(set (match_operand:DI 0 "register_operand" "=r")
1215 (ashift:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
1216 (match_operand:SI 2 "const123_operand" "P"))))]
1219 if (operands[2] == const1_rtx)
1220 return "addl %r1,%r1,%0";
1222 return "s%P2addl %r1,0,%0";
1224 [(set_attr "type" "iadd")])
1226 (define_insn "lshrdi3"
1227 [(set (match_operand:DI 0 "register_operand" "=r")
1228 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1229 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1232 [(set_attr "type" "shift")])
1234 (define_insn "ashrdi3"
1235 [(set (match_operand:DI 0 "register_operand" "=r")
1236 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1237 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1240 [(set_attr "type" "shift")])
1242 (define_insn "extendqi<mode>2"
1243 [(set (match_operand:I24MODE 0 "register_operand" "=r")
1244 (sign_extend:I24MODE
1245 (match_operand:QI 1 "register_operand" "r")))]
1248 [(set_attr "type" "shift")])
1250 (define_expand "extendqidi2"
1251 [(set (match_operand:DI 0 "register_operand")
1252 (sign_extend:DI (match_operand:QI 1 "general_operand")))]
1256 operands[1] = force_reg (QImode, operands[1]);
1261 if (unaligned_memory_operand (operands[1], QImode))
1263 x = gen_unaligned_extendqidi (operands[0], XEXP (operands[1], 0));
1264 alpha_set_memflags (x, operands[1]);
1269 t1 = gen_reg_rtx (DImode);
1270 t2 = gen_reg_rtx (DImode);
1273 x = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1274 emit_move_insn (t1, x);
1275 emit_insn (gen_ashldi3 (t2, t1, i56));
1276 emit_insn (gen_ashrdi3 (operands[0], t2, i56));
1281 (define_insn "*extendqidi2_bwx"
1282 [(set (match_operand:DI 0 "register_operand" "=r")
1283 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1286 [(set_attr "type" "shift")])
1288 (define_insn "extendhisi2"
1289 [(set (match_operand:SI 0 "register_operand" "=r")
1290 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1293 [(set_attr "type" "shift")])
1295 (define_expand "extendhidi2"
1296 [(set (match_operand:DI 0 "register_operand")
1297 (sign_extend:DI (match_operand:HI 1 "general_operand")))]
1301 operands[1] = force_reg (HImode, operands[1]);
1306 if (unaligned_memory_operand (operands[1], HImode))
1308 x = gen_unaligned_extendhidi (operands[0], XEXP (operands[1], 0));
1309 alpha_set_memflags (x, operands[1]);
1314 t1 = gen_reg_rtx (DImode);
1315 t2 = gen_reg_rtx (DImode);
1318 x = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1319 emit_move_insn (t1, x);
1320 emit_insn (gen_ashldi3 (t2, t1, i48));
1321 emit_insn (gen_ashrdi3 (operands[0], t2, i48));
1326 (define_insn "*extendhidi2_bwx"
1327 [(set (match_operand:DI 0 "register_operand" "=r")
1328 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1331 [(set_attr "type" "shift")])
1333 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1334 ;; as a pattern saves one instruction. The code is similar to that for
1335 ;; the unaligned loads (see below).
1337 ;; Operand 1 is the address, operand 0 is the result.
1339 (define_expand "unaligned_extendqidi"
1341 (mem:DI (and:DI (match_operand:DI 1 "address_operand") (const_int -8))))
1343 (ashift:DI (match_dup 3)
1344 (minus:DI (const_int 64)
1346 (and:DI (match_dup 2) (const_int 7))
1348 (set (match_operand:QI 0 "register_operand")
1349 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1352 operands[0] = gen_lowpart (DImode, operands[0]);
1353 operands[2] = get_unaligned_offset (operands[1], 1);
1354 operands[3] = gen_reg_rtx (DImode);
1355 operands[4] = gen_reg_rtx (DImode);
1358 (define_expand "unaligned_extendhidi"
1360 (mem:DI (and:DI (match_operand:DI 1 "address_operand") (const_int -8))))
1362 (ashift:DI (match_dup 3)
1363 (minus:DI (const_int 64)
1365 (and:DI (match_dup 2) (const_int 7))
1367 (set (match_operand:HI 0 "register_operand")
1368 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1371 operands[0] = gen_lowpart (DImode, operands[0]);
1372 operands[2] = get_unaligned_offset (operands[1], 2);
1373 operands[3] = gen_reg_rtx (DImode);
1374 operands[4] = gen_reg_rtx (DImode);
1377 (define_insn "*extxl_const"
1378 [(set (match_operand:DI 0 "register_operand" "=r")
1379 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1380 (match_operand:DI 2 "mode_width_operand" "n")
1381 (match_operand:DI 3 "mul8_operand" "I")))]
1383 "ext%M2l %r1,%s3,%0"
1384 [(set_attr "type" "shift")])
1386 (define_insn "extxl"
1387 [(set (match_operand:DI 0 "register_operand" "=r")
1389 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1390 (match_operand:DI 2 "mode_width_operand" "n")
1391 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1395 [(set_attr "type" "shift")])
1397 ;; Combine has some strange notion of preserving existing undefined behavior
1398 ;; in shifts larger than a word size. So capture these patterns that it
1399 ;; should have turned into zero_extracts.
1401 (define_insn "*extxl_1"
1402 [(set (match_operand:DI 0 "register_operand" "=r")
1403 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1404 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1406 (match_operand:DI 3 "mode_mask_operand" "n")))]
1409 [(set_attr "type" "shift")])
1411 (define_insn "*extql_2"
1412 [(set (match_operand:DI 0 "register_operand" "=r")
1413 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1414 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1418 [(set_attr "type" "shift")])
1420 (define_insn "extqh"
1421 [(set (match_operand:DI 0 "register_operand" "=r")
1423 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1424 (minus:DI (const_int 64)
1427 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1432 [(set_attr "type" "shift")])
1434 (define_insn "extwh"
1435 [(set (match_operand:DI 0 "register_operand" "=r")
1437 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1439 (minus:DI (const_int 64)
1442 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1447 [(set_attr "type" "shift")])
1449 (define_insn "extlh"
1450 [(set (match_operand:DI 0 "register_operand" "=r")
1452 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1453 (const_int 2147483647))
1454 (minus:DI (const_int 64)
1457 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1462 [(set_attr "type" "shift")])
1464 ;; This converts an extXl into an extXh with an appropriate adjustment
1465 ;; to the address calculation.
1468 ;; [(set (match_operand:DI 0 "register_operand")
1469 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand")
1470 ;; (match_operand:DI 2 "mode_width_operand")
1471 ;; (ashift:DI (match_operand:DI 3)
1473 ;; (match_operand:DI 4 "const_int_operand")))
1474 ;; (clobber (match_operand:DI 5 "register_operand"))]
1475 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
1476 ;; [(set (match_dup 5) (match_dup 6))
1477 ;; (set (match_dup 0)
1478 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
1479 ;; (ashift:DI (plus:DI (match_dup 5)
1485 ;; operands[6] = plus_constant (DImode, operands[3],
1486 ;; INTVAL (operands[2]) / BITS_PER_UNIT);
1487 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
1490 (define_insn "ins<modesuffix>l_const"
1491 [(set (match_operand:DI 0 "register_operand" "=r")
1492 (ashift:DI (zero_extend:DI
1493 (match_operand:I124MODE 1 "register_operand" "r"))
1494 (match_operand:DI 2 "mul8_operand" "I")))]
1496 "ins<modesuffix>l %1,%s2,%0"
1497 [(set_attr "type" "shift")])
1499 (define_insn "ins<modesuffix>l"
1500 [(set (match_operand:DI 0 "register_operand" "=r")
1501 (ashift:DI (zero_extend:DI
1502 (match_operand:I124MODE 1 "register_operand" "r"))
1503 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1506 "ins<modesuffix>l %1,%2,%0"
1507 [(set_attr "type" "shift")])
1509 (define_insn "insql"
1510 [(set (match_operand:DI 0 "register_operand" "=r")
1511 (ashift:DI (match_operand:DI 1 "register_operand" "r")
1512 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1516 [(set_attr "type" "shift")])
1518 ;; Combine has this sometimes habit of moving the and outside of the
1519 ;; shift, making life more interesting.
1521 (define_insn "*insxl"
1522 [(set (match_operand:DI 0 "register_operand" "=r")
1523 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
1524 (match_operand:DI 2 "mul8_operand" "I"))
1525 (match_operand:DI 3 "const_int_operand" "i")))]
1526 "((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
1527 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1528 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
1529 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1530 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
1531 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))"
1533 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
1534 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1535 return "insbl %1,%s2,%0";
1536 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
1537 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1538 return "inswl %1,%s2,%0";
1539 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
1540 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1541 return "insll %1,%s2,%0";
1545 [(set_attr "type" "shift")])
1547 ;; We do not include the insXh insns because they are complex to express
1548 ;; and it does not appear that we would ever want to generate them.
1550 ;; Since we need them for block moves, though, cop out and use unspec.
1552 (define_insn "insxh"
1553 [(set (match_operand:DI 0 "register_operand" "=r")
1554 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
1555 (match_operand:DI 2 "mode_width_operand" "n")
1556 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
1560 [(set_attr "type" "shift")])
1562 (define_insn "mskxl"
1563 [(set (match_operand:DI 0 "register_operand" "=r")
1564 (and:DI (not:DI (ashift:DI
1565 (match_operand:DI 2 "mode_mask_operand" "n")
1567 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1569 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
1572 [(set_attr "type" "shift")])
1574 ;; We do not include the mskXh insns because it does not appear we would
1575 ;; ever generate one.
1577 ;; Again, we do for block moves and we use unspec again.
1579 (define_insn "mskxh"
1580 [(set (match_operand:DI 0 "register_operand" "=r")
1581 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
1582 (match_operand:DI 2 "mode_width_operand" "n")
1583 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
1587 [(set_attr "type" "shift")])
1589 ;; Prefer AND + NE over LSHIFTRT + AND.
1591 (define_insn_and_split "*ze_and_ne"
1592 [(set (match_operand:DI 0 "register_operand" "=r")
1593 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1595 (match_operand 2 "const_int_operand" "I")))]
1596 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
1598 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
1600 (and:DI (match_dup 1) (match_dup 3)))
1602 (ne:DI (match_dup 0) (const_int 0)))]
1603 "operands[3] = GEN_INT (1 << INTVAL (operands[2]));")
1605 ;; Floating-point operations. All the double-precision insns can extend
1606 ;; from single, so indicate that. The exception are the ones that simply
1607 ;; play with the sign bits; it's not clear what to do there.
1609 (define_mode_iterator FMODE [SF DF])
1611 (define_mode_attr opmode [(SF "si") (DF "di")])
1613 (define_insn "abs<mode>2"
1614 [(set (match_operand:FMODE 0 "register_operand" "=f")
1615 (abs:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")))]
1618 [(set_attr "type" "fcpys")])
1620 (define_insn "*nabs<mode>2"
1621 [(set (match_operand:FMODE 0 "register_operand" "=f")
1623 (abs:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG"))))]
1626 [(set_attr "type" "fadd")])
1628 (define_expand "abstf2"
1629 [(parallel [(set (match_operand:TF 0 "register_operand")
1630 (abs:TF (match_operand:TF 1 "reg_or_0_operand")))
1631 (use (match_dup 2))])]
1632 "TARGET_HAS_XFLOATING_LIBS"
1633 "operands[2] = force_reg (DImode, GEN_INT (HOST_WIDE_INT_1U << 63));")
1635 (define_insn_and_split "*abstf_internal"
1636 [(set (match_operand:TF 0 "register_operand" "=r")
1637 (abs:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
1638 (use (match_operand:DI 2 "register_operand" "r"))]
1639 "TARGET_HAS_XFLOATING_LIBS"
1641 "&& reload_completed"
1643 "alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;")
1645 (define_insn "neg<mode>2"
1646 [(set (match_operand:FMODE 0 "register_operand" "=f")
1647 (neg:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")))]
1650 [(set_attr "type" "fadd")])
1652 (define_expand "negtf2"
1653 [(parallel [(set (match_operand:TF 0 "register_operand")
1654 (neg:TF (match_operand:TF 1 "reg_or_0_operand")))
1655 (use (match_dup 2))])]
1656 "TARGET_HAS_XFLOATING_LIBS"
1657 "operands[2] = force_reg (DImode, GEN_INT (HOST_WIDE_INT_1U << 63));")
1659 (define_insn_and_split "*negtf_internal"
1660 [(set (match_operand:TF 0 "register_operand" "=r")
1661 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
1662 (use (match_operand:DI 2 "register_operand" "r"))]
1663 "TARGET_HAS_XFLOATING_LIBS"
1665 "&& reload_completed"
1667 "alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;")
1669 (define_insn "copysign<mode>3"
1670 [(set (match_operand:FMODE 0 "register_operand" "=f")
1671 (unspec:FMODE [(match_operand:FMODE 1 "reg_or_0_operand" "fG")
1672 (match_operand:FMODE 2 "reg_or_0_operand" "fG")]
1676 [(set_attr "type" "fadd")])
1678 (define_insn "*ncopysign<mode>3"
1679 [(set (match_operand:FMODE 0 "register_operand" "=f")
1681 (unspec:FMODE [(match_operand:FMODE 1 "reg_or_0_operand" "fG")
1682 (match_operand:FMODE 2 "reg_or_0_operand" "fG")]
1686 [(set_attr "type" "fadd")])
1688 (define_insn "add<mode>3"
1689 [(set (match_operand:FMODE 0 "register_operand" "=f,&f")
1690 (plus:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "%fG,fG")
1691 (match_operand:FMODE 2 "reg_or_0_operand" "fG,fG")))]
1693 "add<modesuffix>%/ %R1,%R2,%0"
1694 [(set_attr "type" "fadd")
1695 (set_attr "trap" "yes")
1696 (set_attr "round_suffix" "normal")
1697 (set_attr "trap_suffix" "u_su_sui")
1698 (set (attr "enabled")
1699 (cond [(eq_attr "alternative" "0")
1700 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU")
1702 (symbol_ref "true")))])
1704 (define_insn "*adddf_ext1"
1705 [(set (match_operand:DF 0 "register_operand" "=f")
1706 (plus:DF (float_extend:DF
1707 (match_operand:SF 1 "reg_or_0_operand" "fG"))
1708 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
1709 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
1710 "add%-%/ %R1,%R2,%0"
1711 [(set_attr "type" "fadd")
1712 (set_attr "trap" "yes")
1713 (set_attr "round_suffix" "normal")
1714 (set_attr "trap_suffix" "u_su_sui")])
1716 (define_insn "*adddf_ext2"
1717 [(set (match_operand:DF 0 "register_operand" "=f")
1718 (plus:DF (float_extend:DF
1719 (match_operand:SF 1 "reg_or_0_operand" "%fG"))
1721 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
1722 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
1723 "add%-%/ %R1,%R2,%0"
1724 [(set_attr "type" "fadd")
1725 (set_attr "trap" "yes")
1726 (set_attr "round_suffix" "normal")
1727 (set_attr "trap_suffix" "u_su_sui")])
1729 (define_expand "addtf3"
1730 [(use (match_operand:TF 0 "register_operand"))
1731 (use (match_operand:TF 1 "general_operand"))
1732 (use (match_operand:TF 2 "general_operand"))]
1733 "TARGET_HAS_XFLOATING_LIBS"
1734 "alpha_emit_xfloating_arith (PLUS, operands); DONE;")
1736 (define_insn "sub<mode>3"
1737 [(set (match_operand:FMODE 0 "register_operand" "=f,&f")
1738 (minus:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG,fG")
1739 (match_operand:FMODE 2 "reg_or_0_operand" "fG,fG")))]
1741 "sub<modesuffix>%/ %R1,%R2,%0"
1742 [(set_attr "type" "fadd")
1743 (set_attr "trap" "yes")
1744 (set_attr "round_suffix" "normal")
1745 (set_attr "trap_suffix" "u_su_sui")
1746 (set (attr "enabled")
1747 (cond [(eq_attr "alternative" "0")
1748 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU")
1750 (symbol_ref "true")))])
1752 (define_insn "*subdf_ext1"
1753 [(set (match_operand:DF 0 "register_operand" "=f")
1754 (minus:DF (float_extend:DF
1755 (match_operand:SF 1 "reg_or_0_operand" "fG"))
1756 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
1757 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
1758 "sub%-%/ %R1,%R2,%0"
1759 [(set_attr "type" "fadd")
1760 (set_attr "trap" "yes")
1761 (set_attr "round_suffix" "normal")
1762 (set_attr "trap_suffix" "u_su_sui")])
1764 (define_insn "*subdf_ext2"
1765 [(set (match_operand:DF 0 "register_operand" "=f")
1766 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
1768 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
1769 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
1770 "sub%-%/ %R1,%R2,%0"
1771 [(set_attr "type" "fadd")
1772 (set_attr "trap" "yes")
1773 (set_attr "round_suffix" "normal")
1774 (set_attr "trap_suffix" "u_su_sui")])
1776 (define_insn "*subdf_ext3"
1777 [(set (match_operand:DF 0 "register_operand" "=f")
1778 (minus:DF (float_extend:DF
1779 (match_operand:SF 1 "reg_or_0_operand" "fG"))
1781 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
1782 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
1783 "sub%-%/ %R1,%R2,%0"
1784 [(set_attr "type" "fadd")
1785 (set_attr "trap" "yes")
1786 (set_attr "round_suffix" "normal")
1787 (set_attr "trap_suffix" "u_su_sui")])
1789 (define_expand "subtf3"
1790 [(use (match_operand:TF 0 "register_operand"))
1791 (use (match_operand:TF 1 "general_operand"))
1792 (use (match_operand:TF 2 "general_operand"))]
1793 "TARGET_HAS_XFLOATING_LIBS"
1794 "alpha_emit_xfloating_arith (MINUS, operands); DONE;")
1796 (define_insn "mul<mode>3"
1797 [(set (match_operand:FMODE 0 "register_operand" "=f,&f")
1798 (mult:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "%fG,fG")
1799 (match_operand:FMODE 2 "reg_or_0_operand" "fG,fG")))]
1801 "mul<modesuffix>%/ %R1,%R2,%0"
1802 [(set_attr "type" "fmul")
1803 (set_attr "trap" "yes")
1804 (set_attr "round_suffix" "normal")
1805 (set_attr "trap_suffix" "u_su_sui")
1806 (set (attr "enabled")
1807 (cond [(eq_attr "alternative" "0")
1808 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU")
1810 (symbol_ref "true")))])
1812 (define_insn "*muldf_ext1"
1813 [(set (match_operand:DF 0 "register_operand" "=f")
1814 (mult:DF (float_extend:DF
1815 (match_operand:SF 1 "reg_or_0_operand" "fG"))
1816 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
1817 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
1818 "mul%-%/ %R1,%R2,%0"
1819 [(set_attr "type" "fmul")
1820 (set_attr "trap" "yes")
1821 (set_attr "round_suffix" "normal")
1822 (set_attr "trap_suffix" "u_su_sui")])
1824 (define_insn "*muldf_ext2"
1825 [(set (match_operand:DF 0 "register_operand" "=f")
1826 (mult:DF (float_extend:DF
1827 (match_operand:SF 1 "reg_or_0_operand" "%fG"))
1829 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
1830 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
1831 "mul%-%/ %R1,%R2,%0"
1832 [(set_attr "type" "fmul")
1833 (set_attr "trap" "yes")
1834 (set_attr "round_suffix" "normal")
1835 (set_attr "trap_suffix" "u_su_sui")])
1837 (define_expand "multf3"
1838 [(use (match_operand:TF 0 "register_operand"))
1839 (use (match_operand:TF 1 "general_operand"))
1840 (use (match_operand:TF 2 "general_operand"))]
1841 "TARGET_HAS_XFLOATING_LIBS"
1842 "alpha_emit_xfloating_arith (MULT, operands); DONE;")
1844 (define_insn "div<mode>3"
1845 [(set (match_operand:FMODE 0 "register_operand" "=f,&f")
1846 (div:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG,fG")
1847 (match_operand:FMODE 2 "reg_or_0_operand" "fG,fG")))]
1849 "div<modesuffix>%/ %R1,%R2,%0"
1850 [(set_attr "type" "fdiv")
1851 (set_attr "opsize" "<opmode>")
1852 (set_attr "trap" "yes")
1853 (set_attr "round_suffix" "normal")
1854 (set_attr "trap_suffix" "u_su_sui")
1855 (set (attr "enabled")
1856 (cond [(eq_attr "alternative" "0")
1857 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU")
1859 (symbol_ref "true")))])
1861 (define_insn "*divdf_ext1"
1862 [(set (match_operand:DF 0 "register_operand" "=f")
1863 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
1864 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
1865 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
1866 "div%-%/ %R1,%R2,%0"
1867 [(set_attr "type" "fdiv")
1868 (set_attr "trap" "yes")
1869 (set_attr "round_suffix" "normal")
1870 (set_attr "trap_suffix" "u_su_sui")])
1872 (define_insn "*divdf_ext2"
1873 [(set (match_operand:DF 0 "register_operand" "=f")
1874 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
1876 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
1877 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
1878 "div%-%/ %R1,%R2,%0"
1879 [(set_attr "type" "fdiv")
1880 (set_attr "trap" "yes")
1881 (set_attr "round_suffix" "normal")
1882 (set_attr "trap_suffix" "u_su_sui")])
1884 (define_insn "*divdf_ext3"
1885 [(set (match_operand:DF 0 "register_operand" "=f")
1886 (div:DF (float_extend:DF
1887 (match_operand:SF 1 "reg_or_0_operand" "fG"))
1889 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
1890 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
1891 "div%-%/ %R1,%R2,%0"
1892 [(set_attr "type" "fdiv")
1893 (set_attr "trap" "yes")
1894 (set_attr "round_suffix" "normal")
1895 (set_attr "trap_suffix" "u_su_sui")])
1897 (define_expand "divtf3"
1898 [(use (match_operand:TF 0 "register_operand"))
1899 (use (match_operand:TF 1 "general_operand"))
1900 (use (match_operand:TF 2 "general_operand"))]
1901 "TARGET_HAS_XFLOATING_LIBS"
1902 "alpha_emit_xfloating_arith (DIV, operands); DONE;")
1904 (define_insn "sqrt<mode>2"
1905 [(set (match_operand:FMODE 0 "register_operand" "=f,&f")
1906 (sqrt:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG,fG")))]
1907 "TARGET_FP && TARGET_FIX"
1908 "sqrt<modesuffix>%/ %R1,%0"
1909 [(set_attr "type" "fsqrt")
1910 (set_attr "opsize" "<opmode>")
1911 (set_attr "trap" "yes")
1912 (set_attr "round_suffix" "normal")
1913 (set_attr "trap_suffix" "u_su_sui")
1914 (set (attr "enabled")
1915 (cond [(eq_attr "alternative" "0")
1916 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU")
1918 (symbol_ref "true")))])
1920 ;; Define conversion operators between DFmode and SImode, using the cvtql
1921 ;; instruction. To allow combine et al to do useful things, we keep the
1922 ;; operation as a unit until after reload, at which point we split the
1925 ;; Note that we (attempt to) only consider this optimization when the
1926 ;; ultimate destination is memory. If we will be doing further integer
1927 ;; processing, it is cheaper to do the truncation in the int regs.
1929 (define_insn "*cvtql"
1930 [(set (match_operand:SF 0 "register_operand" "=f")
1931 (unspec:SF [(match_operand:DI 1 "reg_or_0_operand" "fG")]
1935 [(set_attr "type" "fadd")
1936 (set_attr "trap" "yes")
1937 (set_attr "trap_suffix" "v_sv")])
1939 (define_insn_and_split "*fix_truncdfsi_ieee"
1940 [(set (match_operand:SI 0 "memory_operand" "=m")
1942 (match_operator:DI 4 "fix_operator"
1943 [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0))
1944 (clobber (match_scratch:DI 2 "=&f"))
1945 (clobber (match_scratch:SF 3 "=&f"))]
1946 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
1948 "&& reload_completed"
1949 [(set (match_dup 2) (match_op_dup 4 [(match_dup 1)]))
1950 (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
1951 (set (match_dup 5) (match_dup 3))]
1953 operands[5] = adjust_address (operands[0], SFmode, 0);
1955 [(set_attr "type" "fadd")
1956 (set_attr "trap" "yes")])
1958 (define_insn_and_split "*fix_truncdfsi_internal"
1959 [(set (match_operand:SI 0 "memory_operand" "=m")
1961 (match_operator:DI 3 "fix_operator"
1962 [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0))
1963 (clobber (match_scratch:DI 2 "=f"))]
1964 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
1966 "&& reload_completed"
1967 [(set (match_dup 2) (match_op_dup 3 [(match_dup 1)]))
1968 (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
1969 (set (match_dup 5) (match_dup 4))]
1971 operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2]));
1972 operands[5] = adjust_address (operands[0], SFmode, 0);
1974 [(set_attr "type" "fadd")
1975 (set_attr "trap" "yes")])
1977 (define_insn "*fix_truncdfdi2"
1978 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f,&f")
1979 (match_operator:DI 2 "fix_operator"
1980 [(match_operand:DF 1 "reg_or_0_operand" "fG,fG")]))]
1983 [(set_attr "type" "fadd")
1984 (set_attr "trap" "yes")
1985 (set_attr "round_suffix" "c")
1986 (set_attr "trap_suffix" "v_sv_svi")
1987 (set (attr "enabled")
1988 (cond [(eq_attr "alternative" "0")
1989 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU")
1991 (symbol_ref "true")))])
1993 (define_expand "fix_truncdfdi2"
1994 [(set (match_operand:DI 0 "reg_no_subreg_operand")
1995 (fix:DI (match_operand:DF 1 "reg_or_0_operand")))]
1998 (define_expand "fixuns_truncdfdi2"
1999 [(set (match_operand:DI 0 "reg_no_subreg_operand")
2000 (unsigned_fix:DI (match_operand:DF 1 "reg_or_0_operand")))]
2003 ;; Likewise between SFmode and SImode.
2005 (define_insn_and_split "*fix_truncsfsi_ieee"
2006 [(set (match_operand:SI 0 "memory_operand" "=m")
2008 (match_operator:DI 4 "fix_operator"
2010 (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0))
2011 (clobber (match_scratch:DI 2 "=&f"))
2012 (clobber (match_scratch:SF 3 "=&f"))]
2013 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2015 "&& reload_completed"
2016 [(set (match_dup 2) (match_op_dup 4 [(float_extend:DF (match_dup 1))]))
2017 (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2018 (set (match_dup 5) (match_dup 3))]
2019 "operands[5] = adjust_address (operands[0], SFmode, 0);"
2020 [(set_attr "type" "fadd")
2021 (set_attr "trap" "yes")])
2023 (define_insn_and_split "*fix_truncsfsi_internal"
2024 [(set (match_operand:SI 0 "memory_operand" "=m")
2026 (match_operator:DI 3 "fix_operator"
2028 (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0))
2029 (clobber (match_scratch:DI 2 "=f"))]
2030 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2032 "&& reload_completed"
2033 [(set (match_dup 2) (match_op_dup 3 [(float_extend:DF (match_dup 1))]))
2034 (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2035 (set (match_dup 5) (match_dup 4))]
2037 operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2]));
2038 operands[5] = adjust_address (operands[0], SFmode, 0);
2040 [(set_attr "type" "fadd")
2041 (set_attr "trap" "yes")])
2043 (define_insn "*fix_truncsfdi2"
2044 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f,&f")
2045 (match_operator:DI 2 "fix_operator"
2046 [(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,fG"))]))]
2049 [(set_attr "type" "fadd")
2050 (set_attr "trap" "yes")
2051 (set_attr "round_suffix" "c")
2052 (set_attr "trap_suffix" "v_sv_svi")
2053 (set (attr "enabled")
2054 (cond [(eq_attr "alternative" "0")
2055 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU")
2057 (symbol_ref "true")))])
2059 (define_expand "fix_truncsfdi2"
2060 [(set (match_operand:DI 0 "reg_no_subreg_operand")
2061 (fix:DI (float_extend:DF (match_operand:SF 1 "reg_or_0_operand"))))]
2064 (define_expand "fixuns_truncsfdi2"
2065 [(set (match_operand:DI 0 "reg_no_subreg_operand")
2067 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand"))))]
2070 (define_expand "fix_trunctfdi2"
2071 [(use (match_operand:DI 0 "register_operand"))
2072 (use (match_operand:TF 1 "general_operand"))]
2073 "TARGET_HAS_XFLOATING_LIBS"
2074 "alpha_emit_xfloating_cvt (FIX, operands); DONE;")
2076 (define_expand "fixuns_trunctfdi2"
2077 [(use (match_operand:DI 0 "register_operand"))
2078 (use (match_operand:TF 1 "general_operand"))]
2079 "TARGET_HAS_XFLOATING_LIBS"
2080 "alpha_emit_xfloating_cvt (UNSIGNED_FIX, operands); DONE;")
2082 (define_insn "floatdisf2"
2083 [(set (match_operand:SF 0 "register_operand" "=f,&f")
2084 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f,f")))]
2087 [(set_attr "type" "fadd")
2088 (set_attr "trap" "yes")
2089 (set_attr "round_suffix" "normal")
2090 (set_attr "trap_suffix" "sui")
2091 (set (attr "enabled")
2092 (cond [(eq_attr "alternative" "0")
2093 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU")
2095 (symbol_ref "true")))])
2097 (define_insn_and_split "*floatsisf2_ieee"
2098 [(set (match_operand:SF 0 "register_operand" "=&f")
2099 (float:SF (match_operand:SI 1 "memory_operand" "m")))
2100 (clobber (match_scratch:DI 2 "=&f"))
2101 (clobber (match_scratch:SF 3 "=&f"))]
2102 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2104 "&& reload_completed"
2105 [(set (match_dup 3) (match_dup 1))
2106 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
2107 (set (match_dup 0) (float:SF (match_dup 2)))]
2108 "operands[1] = adjust_address (operands[1], SFmode, 0);")
2110 (define_insn_and_split "*floatsisf2"
2111 [(set (match_operand:SF 0 "register_operand" "=f")
2112 (float:SF (match_operand:SI 1 "memory_operand" "m")))]
2115 "&& reload_completed"
2116 [(set (match_dup 0) (match_dup 1))
2117 (set (match_dup 2) (unspec:DI [(match_dup 0)] UNSPEC_CVTLQ))
2118 (set (match_dup 0) (float:SF (match_dup 2)))]
2120 operands[1] = adjust_address (operands[1], SFmode, 0);
2121 operands[2] = gen_rtx_REG (DImode, REGNO (operands[0]));
2124 (define_insn "floatdidf2"
2125 [(set (match_operand:DF 0 "register_operand" "=f,&f")
2126 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f,f")))]
2129 [(set_attr "type" "fadd")
2130 (set_attr "trap" "yes")
2131 (set_attr "round_suffix" "normal")
2132 (set_attr "trap_suffix" "sui")
2133 (set (attr "enabled")
2134 (cond [(eq_attr "alternative" "0")
2135 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU")
2137 (symbol_ref "true")))])
2139 (define_insn_and_split "*floatsidf2_ieee"
2140 [(set (match_operand:DF 0 "register_operand" "=&f")
2141 (float:DF (match_operand:SI 1 "memory_operand" "m")))
2142 (clobber (match_scratch:DI 2 "=&f"))
2143 (clobber (match_scratch:SF 3 "=&f"))]
2144 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2146 "&& reload_completed"
2147 [(set (match_dup 3) (match_dup 1))
2148 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
2149 (set (match_dup 0) (float:DF (match_dup 2)))]
2150 "operands[1] = adjust_address (operands[1], SFmode, 0);")
2152 (define_insn_and_split "*floatsidf2"
2153 [(set (match_operand:DF 0 "register_operand" "=f")
2154 (float:DF (match_operand:SI 1 "memory_operand" "m")))]
2157 "&& reload_completed"
2158 [(set (match_dup 3) (match_dup 1))
2159 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
2160 (set (match_dup 0) (float:DF (match_dup 2)))]
2162 operands[1] = adjust_address (operands[1], SFmode, 0);
2163 operands[2] = gen_rtx_REG (DImode, REGNO (operands[0]));
2164 operands[3] = gen_rtx_REG (SFmode, REGNO (operands[0]));
2167 (define_expand "floatditf2"
2168 [(use (match_operand:TF 0 "register_operand"))
2169 (use (match_operand:DI 1 "general_operand"))]
2170 "TARGET_HAS_XFLOATING_LIBS"
2171 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
2173 (define_expand "floatunsdisf2"
2174 [(use (match_operand:SF 0 "register_operand"))
2175 (use (match_operand:DI 1 "register_operand"))]
2177 "alpha_emit_floatuns (operands); DONE;")
2179 (define_expand "floatunsdidf2"
2180 [(use (match_operand:DF 0 "register_operand"))
2181 (use (match_operand:DI 1 "register_operand"))]
2183 "alpha_emit_floatuns (operands); DONE;")
2185 (define_expand "floatunsditf2"
2186 [(use (match_operand:TF 0 "register_operand"))
2187 (use (match_operand:DI 1 "general_operand"))]
2188 "TARGET_HAS_XFLOATING_LIBS"
2189 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
2191 (define_expand "extendsfdf2"
2192 [(set (match_operand:DF 0 "register_operand")
2193 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand")))]
2196 if (alpha_fptm >= ALPHA_FPTM_SU)
2197 operands[1] = force_reg (SFmode, operands[1]);
2200 ;; The Unicos/Mk assembler doesn't support cvtst, but we've already
2201 ;; asserted that alpha_fptm == ALPHA_FPTM_N.
2203 (define_insn "*extendsfdf2_ieee"
2204 [(set (match_operand:DF 0 "register_operand" "=&f")
2205 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2206 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2208 [(set_attr "type" "fadd")
2209 (set_attr "trap" "yes")])
2211 (define_insn "*extendsfdf2_internal"
2212 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
2213 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
2214 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2219 [(set_attr "type" "fcpys,fld,fst")])
2221 ;; Use register_operand for operand 1 to prevent compress_float_constant
2222 ;; from doing something silly. When optimizing we'll put things back
2224 (define_expand "extendsftf2"
2225 [(use (match_operand:TF 0 "register_operand"))
2226 (use (match_operand:SF 1 "register_operand"))]
2227 "TARGET_HAS_XFLOATING_LIBS"
2229 rtx tmp = gen_reg_rtx (DFmode);
2230 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
2231 emit_insn (gen_extenddftf2 (operands[0], tmp));
2235 (define_expand "extenddftf2"
2236 [(use (match_operand:TF 0 "register_operand"))
2237 (use (match_operand:DF 1 "register_operand"))]
2238 "TARGET_HAS_XFLOATING_LIBS"
2239 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
2241 (define_insn "truncdfsf2"
2242 [(set (match_operand:SF 0 "register_operand" "=f,&f")
2243 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG,fG")))]
2246 [(set_attr "type" "fadd")
2247 (set_attr "trap" "yes")
2248 (set_attr "round_suffix" "normal")
2249 (set_attr "trap_suffix" "u_su_sui")
2250 (set (attr "enabled")
2251 (cond [(eq_attr "alternative" "0")
2252 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU")
2254 (symbol_ref "true")))])
2256 (define_expand "trunctfdf2"
2257 [(use (match_operand:DF 0 "register_operand"))
2258 (use (match_operand:TF 1 "general_operand"))]
2259 "TARGET_HAS_XFLOATING_LIBS"
2260 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
2262 (define_expand "trunctfsf2"
2263 [(use (match_operand:SF 0 "register_operand"))
2264 (use (match_operand:TF 1 "general_operand"))]
2265 "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
2267 rtx tmpf, sticky, arg, lo, hi;
2269 tmpf = gen_reg_rtx (DFmode);
2270 sticky = gen_reg_rtx (DImode);
2271 arg = copy_to_mode_reg (TFmode, operands[1]);
2272 lo = gen_lowpart (DImode, arg);
2273 hi = gen_highpart (DImode, arg);
2275 /* Convert the low word of the TFmode value into a sticky rounding bit,
2276 then or it into the low bit of the high word. This leaves the sticky
2277 bit at bit 48 of the fraction, which is representable in DFmode,
2278 which prevents rounding error in the final conversion to SFmode. */
2280 emit_insn (gen_rtx_SET (sticky, gen_rtx_NE (DImode, lo, const0_rtx)));
2281 emit_insn (gen_iordi3 (hi, hi, sticky));
2282 emit_insn (gen_trunctfdf2 (tmpf, arg));
2283 emit_insn (gen_truncdfsf2 (operands[0], tmpf));
2287 ;; Next are all the integer comparisons, and conditional moves and branches
2288 ;; and some of the related define_expand's and define_split's.
2290 (define_insn "*setcc_internal"
2291 [(set (match_operand 0 "register_operand" "=r")
2292 (match_operator 1 "alpha_comparison_operator"
2293 [(match_operand:DI 2 "register_operand" "r")
2294 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
2295 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2296 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2297 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2299 [(set_attr "type" "icmp")])
2301 ;; Yes, we can technically support reg_or_8bit_operand in operand 2,
2302 ;; but that's non-canonical rtl and allowing that causes inefficiencies
2304 (define_insn "*setcc_swapped_internal"
2305 [(set (match_operand 0 "register_operand" "=r")
2306 (match_operator 1 "alpha_swapped_comparison_operator"
2307 [(match_operand:DI 2 "register_operand" "r")
2308 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
2309 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2310 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2311 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2313 [(set_attr "type" "icmp")])
2315 ;; Use match_operator rather than ne directly so that we can match
2316 ;; multiple integer modes.
2317 (define_insn "*setne_internal"
2318 [(set (match_operand 0 "register_operand" "=r")
2319 (match_operator 1 "signed_comparison_operator"
2320 [(match_operand:DI 2 "register_operand" "r")
2322 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2323 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2324 && GET_CODE (operands[1]) == NE
2325 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2327 [(set_attr "type" "icmp")])
2329 ;; The mode folding trick can't be used with const_int operands, since
2330 ;; reload needs to know the proper mode.
2332 ;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand
2333 ;; in order to create more pairs of constants. As long as we're allowing
2334 ;; two constants at the same time, and will have to reload one of them...
2336 (define_insn "*mov<mode>cc_internal"
2337 [(set (match_operand:IMODE 0 "register_operand" "=r,r,r,r")
2339 (match_operator 2 "signed_comparison_operator"
2340 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2341 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2342 (match_operand:IMODE 1 "add_operand" "rI,0,rI,0")
2343 (match_operand:IMODE 5 "add_operand" "0,rI,0,rI")))]
2344 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)"
2350 [(set_attr "type" "icmov")])
2352 (define_insn "*mov<mode>cc_lbc"
2353 [(set (match_operand:IMODE 0 "register_operand" "=r,r")
2355 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2359 (match_operand:IMODE 1 "reg_or_8bit_operand" "rI,0")
2360 (match_operand:IMODE 3 "reg_or_8bit_operand" "0,rI")))]
2365 [(set_attr "type" "icmov")])
2367 (define_insn "*mov<mode>cc_lbs"
2368 [(set (match_operand:IMODE 0 "register_operand" "=r,r")
2370 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2374 (match_operand:IMODE 1 "reg_or_8bit_operand" "rI,0")
2375 (match_operand:IMODE 3 "reg_or_8bit_operand" "0,rI")))]
2380 [(set_attr "type" "icmov")])
2382 ;; For ABS, we have two choices, depending on whether the input and output
2383 ;; registers are the same or not.
2384 (define_expand "absdi2"
2385 [(set (match_operand:DI 0 "register_operand")
2386 (abs:DI (match_operand:DI 1 "register_operand")))]
2389 if (rtx_equal_p (operands[0], operands[1]))
2390 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
2392 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
2396 (define_expand "absdi2_same"
2397 [(set (match_operand:DI 1 "register_operand")
2398 (neg:DI (match_operand:DI 0 "register_operand")))
2400 (if_then_else:DI (ge (match_dup 0) (const_int 0))
2404 (define_expand "absdi2_diff"
2405 [(set (match_operand:DI 0 "register_operand")
2406 (neg:DI (match_operand:DI 1 "register_operand")))
2408 (if_then_else:DI (lt (match_dup 1) (const_int 0))
2413 [(set (match_operand:DI 0 "register_operand")
2414 (abs:DI (match_dup 0)))
2415 (clobber (match_operand:DI 1 "register_operand"))]
2417 [(set (match_dup 1) (neg:DI (match_dup 0)))
2418 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
2419 (match_dup 0) (match_dup 1)))])
2422 [(set (match_operand:DI 0 "register_operand")
2423 (abs:DI (match_operand:DI 1 "register_operand")))]
2424 "! rtx_equal_p (operands[0], operands[1])"
2425 [(set (match_dup 0) (neg:DI (match_dup 1)))
2426 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
2427 (match_dup 0) (match_dup 1)))])
2430 [(set (match_operand:DI 0 "register_operand")
2431 (neg:DI (abs:DI (match_dup 0))))
2432 (clobber (match_operand:DI 1 "register_operand"))]
2434 [(set (match_dup 1) (neg:DI (match_dup 0)))
2435 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
2436 (match_dup 0) (match_dup 1)))])
2439 [(set (match_operand:DI 0 "register_operand")
2440 (neg:DI (abs:DI (match_operand:DI 1 "register_operand"))))]
2441 "! rtx_equal_p (operands[0], operands[1])"
2442 [(set (match_dup 0) (neg:DI (match_dup 1)))
2443 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
2444 (match_dup 0) (match_dup 1)))])
2446 (define_insn "<code><mode>3"
2447 [(set (match_operand:I12MODE 0 "register_operand" "=r")
2449 (match_operand:I12MODE 1 "reg_or_0_operand" "%rJ")
2450 (match_operand:I12MODE 2 "reg_or_8bit_operand" "rI")))]
2452 "<maxmin><vecmodesuffix> %r1,%2,%0"
2453 [(set_attr "type" "mvi")])
2455 (define_expand "smaxdi3"
2457 (le:DI (match_operand:DI 1 "reg_or_0_operand")
2458 (match_operand:DI 2 "reg_or_8bit_operand")))
2459 (set (match_operand:DI 0 "register_operand")
2460 (if_then_else:DI (eq (match_dup 3) (const_int 0))
2461 (match_dup 1) (match_dup 2)))]
2463 "operands[3] = gen_reg_rtx (DImode);")
2466 [(set (match_operand:DI 0 "register_operand")
2467 (smax:DI (match_operand:DI 1 "reg_or_0_operand")
2468 (match_operand:DI 2 "reg_or_8bit_operand")))
2469 (clobber (match_operand:DI 3 "register_operand"))]
2470 "operands[2] != const0_rtx"
2471 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
2472 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
2473 (match_dup 1) (match_dup 2)))])
2475 (define_insn "*smax_const0"
2476 [(set (match_operand:DI 0 "register_operand" "=r")
2477 (smax:DI (match_operand:DI 1 "register_operand" "0")
2481 [(set_attr "type" "icmov")])
2483 (define_expand "smindi3"
2485 (lt:DI (match_operand:DI 1 "reg_or_0_operand")
2486 (match_operand:DI 2 "reg_or_8bit_operand")))
2487 (set (match_operand:DI 0 "register_operand")
2488 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2489 (match_dup 1) (match_dup 2)))]
2491 "operands[3] = gen_reg_rtx (DImode);")
2494 [(set (match_operand:DI 0 "register_operand")
2495 (smin:DI (match_operand:DI 1 "reg_or_0_operand")
2496 (match_operand:DI 2 "reg_or_8bit_operand")))
2497 (clobber (match_operand:DI 3 "register_operand"))]
2498 "operands[2] != const0_rtx"
2499 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
2500 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
2501 (match_dup 1) (match_dup 2)))])
2503 (define_insn "*smin_const0"
2504 [(set (match_operand:DI 0 "register_operand" "=r")
2505 (smin:DI (match_operand:DI 1 "register_operand" "0")
2509 [(set_attr "type" "icmov")])
2511 (define_expand "umaxdi3"
2513 (leu:DI (match_operand:DI 1 "reg_or_0_operand")
2514 (match_operand:DI 2 "reg_or_8bit_operand")))
2515 (set (match_operand:DI 0 "register_operand")
2516 (if_then_else:DI (eq (match_dup 3) (const_int 0))
2517 (match_dup 1) (match_dup 2)))]
2519 "operands[3] = gen_reg_rtx (DImode);")
2522 [(set (match_operand:DI 0 "register_operand")
2523 (umax:DI (match_operand:DI 1 "reg_or_0_operand")
2524 (match_operand:DI 2 "reg_or_8bit_operand")))
2525 (clobber (match_operand:DI 3 "register_operand"))]
2526 "operands[2] != const0_rtx"
2527 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
2528 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
2529 (match_dup 1) (match_dup 2)))])
2531 (define_expand "umindi3"
2533 (ltu:DI (match_operand:DI 1 "reg_or_0_operand")
2534 (match_operand:DI 2 "reg_or_8bit_operand")))
2535 (set (match_operand:DI 0 "register_operand")
2536 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2537 (match_dup 1) (match_dup 2)))]
2539 "operands[3] = gen_reg_rtx (DImode);")
2542 [(set (match_operand:DI 0 "register_operand")
2543 (umin:DI (match_operand:DI 1 "reg_or_0_operand")
2544 (match_operand:DI 2 "reg_or_8bit_operand")))
2545 (clobber (match_operand:DI 3 "register_operand"))]
2546 "operands[2] != const0_rtx"
2547 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
2548 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
2549 (match_dup 1) (match_dup 2)))])
2551 (define_insn "*bcc_normal"
2554 (match_operator 1 "signed_comparison_operator"
2555 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
2557 (label_ref (match_operand 0))
2561 [(set_attr "type" "ibr")])
2563 (define_insn "*bcc_reverse"
2566 (match_operator 1 "signed_comparison_operator"
2567 [(match_operand:DI 2 "register_operand" "r")
2571 (label_ref (match_operand 0))))]
2574 [(set_attr "type" "ibr")])
2576 (define_insn "*blbs_normal"
2579 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2583 (label_ref (match_operand 0))
2587 [(set_attr "type" "ibr")])
2589 (define_insn "*blbc_normal"
2592 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2596 (label_ref (match_operand 0))
2600 [(set_attr "type" "ibr")])
2606 (match_operator 1 "comparison_operator"
2607 [(zero_extract:DI (match_operand:DI 2 "register_operand")
2609 (match_operand:DI 3 "const_int_operand"))
2611 (label_ref (match_operand 0))
2613 (clobber (match_operand:DI 4 "register_operand"))])]
2614 "INTVAL (operands[3]) != 0"
2616 (lshiftrt:DI (match_dup 2) (match_dup 3)))
2618 (if_then_else (match_op_dup 1
2619 [(zero_extract:DI (match_dup 4)
2623 (label_ref (match_dup 0))
2627 ;; The following are the corresponding floating-point insns. Recall
2628 ;; we need to have variants that expand the arguments from SFmode
2631 (define_insn "*cmpdf_internal"
2632 [(set (match_operand:DF 0 "register_operand" "=f,&f")
2633 (match_operator:DF 1 "alpha_fp_comparison_operator"
2634 [(match_operand:DF 2 "reg_or_0_operand" "fG,fG")
2635 (match_operand:DF 3 "reg_or_0_operand" "fG,fG")]))]
2637 "cmp%-%C1%/ %R2,%R3,%0"
2638 [(set_attr "type" "fadd")
2639 (set_attr "trap" "yes")
2640 (set_attr "trap_suffix" "su")
2641 (set (attr "enabled")
2642 (cond [(eq_attr "alternative" "0")
2643 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU")
2645 (symbol_ref "true")))])
2647 (define_insn "*cmpdf_ext1"
2648 [(set (match_operand:DF 0 "register_operand" "=f")
2649 (match_operator:DF 1 "alpha_fp_comparison_operator"
2651 (match_operand:SF 2 "reg_or_0_operand" "fG"))
2652 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
2653 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2654 "cmp%-%C1%/ %R2,%R3,%0"
2655 [(set_attr "type" "fadd")
2656 (set_attr "trap" "yes")
2657 (set_attr "trap_suffix" "su")])
2659 (define_insn "*cmpdf_ext2"
2660 [(set (match_operand:DF 0 "register_operand" "=f")
2661 (match_operator:DF 1 "alpha_fp_comparison_operator"
2662 [(match_operand:DF 2 "reg_or_0_operand" "fG")
2664 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
2665 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2666 "cmp%-%C1%/ %R2,%R3,%0"
2667 [(set_attr "type" "fadd")
2668 (set_attr "trap" "yes")
2669 (set_attr "trap_suffix" "su")])
2671 (define_insn "*cmpdf_ext3"
2672 [(set (match_operand:DF 0 "register_operand" "=f")
2673 (match_operator:DF 1 "alpha_fp_comparison_operator"
2675 (match_operand:SF 2 "reg_or_0_operand" "fG"))
2677 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
2678 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2679 "cmp%-%C1%/ %R2,%R3,%0"
2680 [(set_attr "type" "fadd")
2681 (set_attr "trap" "yes")
2682 (set_attr "trap_suffix" "su")])
2684 (define_insn "*mov<mode>cc_internal"
2685 [(set (match_operand:FMODE 0 "register_operand" "=f,f")
2687 (match_operator 3 "signed_comparison_operator"
2688 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
2689 (match_operand:DF 2 "const0_operand" "G,G")])
2690 (match_operand:FMODE 1 "reg_or_0_operand" "fG,0")
2691 (match_operand:FMODE 5 "reg_or_0_operand" "0,fG")))]
2695 fcmov%D3 %R4,%R5,%0"
2696 [(set_attr "type" "fcmov")])
2698 (define_insn "*movdfcc_ext1"
2699 [(set (match_operand:DF 0 "register_operand" "=f,f")
2701 (match_operator 3 "signed_comparison_operator"
2702 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
2703 (match_operand:DF 2 "const0_operand" "G,G")])
2704 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
2705 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
2706 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2709 fcmov%D3 %R4,%R5,%0"
2710 [(set_attr "type" "fcmov")])
2712 (define_insn "*movdfcc_ext2"
2713 [(set (match_operand:DF 0 "register_operand" "=f,f")
2715 (match_operator 3 "signed_comparison_operator"
2717 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
2718 (match_operand:DF 2 "const0_operand" "G,G")])
2719 (match_operand:DF 1 "reg_or_0_operand" "fG,0")
2720 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
2721 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2724 fcmov%D3 %R4,%R5,%0"
2725 [(set_attr "type" "fcmov")])
2727 (define_insn "*movdfcc_ext3"
2728 [(set (match_operand:SF 0 "register_operand" "=f,f")
2730 (match_operator 3 "signed_comparison_operator"
2732 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
2733 (match_operand:DF 2 "const0_operand" "G,G")])
2734 (match_operand:SF 1 "reg_or_0_operand" "fG,0")
2735 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
2736 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2739 fcmov%D3 %R4,%R5,%0"
2740 [(set_attr "type" "fcmov")])
2742 (define_insn "*movdfcc_ext4"
2743 [(set (match_operand:DF 0 "register_operand" "=f,f")
2745 (match_operator 3 "signed_comparison_operator"
2747 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
2748 (match_operand:DF 2 "const0_operand" "G,G")])
2749 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
2750 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
2751 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2754 fcmov%D3 %R4,%R5,%0"
2755 [(set_attr "type" "fcmov")])
2757 (define_expand "smaxdf3"
2759 (le:DF (match_operand:DF 1 "reg_or_0_operand")
2760 (match_operand:DF 2 "reg_or_0_operand")))
2761 (set (match_operand:DF 0 "register_operand")
2762 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
2763 (match_dup 1) (match_dup 2)))]
2766 operands[3] = gen_reg_rtx (DFmode);
2767 operands[4] = CONST0_RTX (DFmode);
2770 (define_expand "smindf3"
2772 (lt:DF (match_operand:DF 1 "reg_or_0_operand")
2773 (match_operand:DF 2 "reg_or_0_operand")))
2774 (set (match_operand:DF 0 "register_operand")
2775 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
2776 (match_dup 1) (match_dup 2)))]
2779 operands[3] = gen_reg_rtx (DFmode);
2780 operands[4] = CONST0_RTX (DFmode);
2783 (define_expand "smaxsf3"
2785 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand"))
2786 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand"))))
2787 (set (match_operand:SF 0 "register_operand")
2788 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
2789 (match_dup 1) (match_dup 2)))]
2790 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2792 operands[3] = gen_reg_rtx (DFmode);
2793 operands[4] = CONST0_RTX (DFmode);
2796 (define_expand "sminsf3"
2798 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand"))
2799 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand"))))
2800 (set (match_operand:SF 0 "register_operand")
2801 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
2802 (match_dup 1) (match_dup 2)))]
2803 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2805 operands[3] = gen_reg_rtx (DFmode);
2806 operands[4] = CONST0_RTX (DFmode);
2809 (define_insn "*fbcc_normal"
2812 (match_operator 1 "signed_comparison_operator"
2813 [(match_operand:DF 2 "reg_or_0_operand" "fG")
2814 (match_operand:DF 3 "const0_operand" "G")])
2815 (label_ref (match_operand 0))
2819 [(set_attr "type" "fbr")])
2821 (define_insn "*fbcc_ext_normal"
2824 (match_operator 1 "signed_comparison_operator"
2826 (match_operand:SF 2 "reg_or_0_operand" "fG"))
2827 (match_operand:DF 3 "const0_operand" "G")])
2828 (label_ref (match_operand 0))
2832 [(set_attr "type" "fbr")])
2834 ;; These are the main define_expand's used to make conditional branches
2837 (define_expand "cbranchdf4"
2838 [(use (match_operator 0 "alpha_cbranch_operator"
2839 [(match_operand:DF 1 "reg_or_0_operand")
2840 (match_operand:DF 2 "reg_or_0_operand")]))
2841 (use (match_operand 3))]
2843 "alpha_emit_conditional_branch (operands, DFmode); DONE;")
2845 (define_expand "cbranchtf4"
2846 [(use (match_operator 0 "alpha_cbranch_operator"
2847 [(match_operand:TF 1 "general_operand")
2848 (match_operand:TF 2 "general_operand")]))
2849 (use (match_operand 3))]
2850 "TARGET_HAS_XFLOATING_LIBS"
2851 "alpha_emit_conditional_branch (operands, TFmode); DONE;")
2853 (define_expand "cbranchdi4"
2854 [(use (match_operator 0 "alpha_cbranch_operator"
2855 [(match_operand:DI 1 "general_operand")
2856 (match_operand:DI 2 "general_operand")]))
2857 (use (match_operand 3))]
2859 "alpha_emit_conditional_branch (operands, DImode); DONE;")
2861 (define_expand "cstoredf4"
2862 [(use (match_operator:DI 1 "alpha_cbranch_operator"
2863 [(match_operand:DF 2 "reg_or_0_operand")
2864 (match_operand:DF 3 "reg_or_0_operand")]))
2865 (clobber (match_operand:DI 0 "register_operand"))]
2868 if (alpha_emit_setcc (operands, DFmode))
2874 (define_expand "cstoretf4"
2875 [(use (match_operator:DI 1 "alpha_cbranch_operator"
2876 [(match_operand:TF 2 "general_operand")
2877 (match_operand:TF 3 "general_operand")]))
2878 (clobber (match_operand:DI 0 "register_operand"))]
2879 "TARGET_HAS_XFLOATING_LIBS"
2881 if (alpha_emit_setcc (operands, TFmode))
2887 (define_expand "cstoredi4"
2888 [(use (match_operator:DI 1 "alpha_cbranch_operator"
2889 [(match_operand:DI 2 "general_operand")
2890 (match_operand:DI 3 "general_operand")]))
2891 (clobber (match_operand:DI 0 "register_operand"))]
2894 if (alpha_emit_setcc (operands, DImode))
2900 ;; These are the main define_expand's used to make conditional moves.
2902 (define_expand "mov<mode>cc"
2903 [(set (match_operand:I48MODE 0 "register_operand")
2904 (if_then_else:I48MODE
2905 (match_operand 1 "comparison_operator")
2906 (match_operand:I48MODE 2 "reg_or_8bit_operand")
2907 (match_operand:I48MODE 3 "reg_or_8bit_operand")))]
2910 operands[1] = alpha_emit_conditional_move (operands[1], <MODE>mode);
2911 if (operands[1] == 0)
2915 (define_expand "mov<mode>cc"
2916 [(set (match_operand:FMODE 0 "register_operand")
2918 (match_operand 1 "comparison_operator")
2919 (match_operand:FMODE 2 "reg_or_8bit_operand")
2920 (match_operand:FMODE 3 "reg_or_8bit_operand")))]
2923 operands[1] = alpha_emit_conditional_move (operands[1], <MODE>mode);
2924 if (operands[1] == 0)
2928 ;; These define_split definitions are used in cases when comparisons have
2929 ;; not be stated in the correct way and we need to reverse the second
2930 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
2931 ;; comparison that tests the result being reversed. We have one define_split
2932 ;; for each use of a comparison. They do not match valid insns and need
2933 ;; not generate valid insns.
2935 ;; We can also handle equality comparisons (and inequality comparisons in
2936 ;; cases where the resulting add cannot overflow) by doing an add followed by
2937 ;; a comparison with zero. This is faster since the addition takes one
2938 ;; less cycle than a compare when feeding into a conditional move.
2939 ;; For this case, we also have an SImode pattern since we can merge the add
2940 ;; and sign extend and the order doesn't matter.
2942 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
2943 ;; operation could have been generated.
2946 [(set (match_operand:DI 0 "register_operand")
2948 (match_operator 1 "comparison_operator"
2949 [(match_operand:DI 2 "reg_or_0_operand")
2950 (match_operand:DI 3 "reg_or_cint_operand")])
2951 (match_operand:DI 4 "reg_or_cint_operand")
2952 (match_operand:DI 5 "reg_or_cint_operand")))
2953 (clobber (match_operand:DI 6 "register_operand"))]
2954 "operands[3] != const0_rtx"
2955 [(set (match_dup 6) (match_dup 7))
2957 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
2959 enum rtx_code code = GET_CODE (operands[1]);
2960 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
2962 /* If we are comparing for equality with a constant and that constant
2963 appears in the arm when the register equals the constant, use the
2964 register since that is more likely to match (and to produce better code
2967 if (code == EQ && CONST_INT_P (operands[3])
2968 && rtx_equal_p (operands[4], operands[3]))
2969 operands[4] = operands[2];
2971 else if (code == NE && CONST_INT_P (operands[3])
2972 && rtx_equal_p (operands[5], operands[3]))
2973 operands[5] = operands[2];
2975 if (code == NE || code == EQ
2976 || (extended_count (operands[2], DImode, unsignedp) >= 1
2977 && extended_count (operands[3], DImode, unsignedp) >= 1))
2979 if (CONST_INT_P (operands[3]))
2980 operands[7] = gen_rtx_PLUS (DImode, operands[2],
2981 GEN_INT (- INTVAL (operands[3])));
2983 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
2985 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
2988 else if (code == EQ || code == LE || code == LT
2989 || code == LEU || code == LTU)
2991 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
2992 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
2996 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
2997 operands[2], operands[3]);
2998 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
3003 [(set (match_operand:DI 0 "register_operand")
3005 (match_operator 1 "comparison_operator"
3006 [(match_operand:SI 2 "reg_or_0_operand")
3007 (match_operand:SI 3 "reg_or_cint_operand")])
3008 (match_operand:DI 4 "reg_or_8bit_operand")
3009 (match_operand:DI 5 "reg_or_8bit_operand")))
3010 (clobber (match_operand:DI 6 "register_operand"))]
3011 "operands[3] != const0_rtx
3012 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
3013 [(set (match_dup 6) (match_dup 7))
3015 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
3017 enum rtx_code code = GET_CODE (operands[1]);
3018 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3021 if ((code != NE && code != EQ
3022 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
3023 && extended_count (operands[3], DImode, unsignedp) >= 1)))
3026 if (CONST_INT_P (operands[3]))
3027 tem = gen_rtx_PLUS (SImode, operands[2],
3028 GEN_INT (- INTVAL (operands[3])));
3030 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
3032 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
3033 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
3034 operands[6], const0_rtx);
3037 ;; Prefer to use cmp and arithmetic when possible instead of a cmove.
3040 [(set (match_operand 0 "register_operand")
3041 (if_then_else (match_operator 1 "signed_comparison_operator"
3042 [(match_operand:DI 2 "reg_or_0_operand")
3044 (match_operand 3 "const_int_operand")
3045 (match_operand 4 "const_int_operand")))]
3049 if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0],
3050 operands[2], operands[3], operands[4]))
3056 ;; ??? Why combine is allowed to create such non-canonical rtl, I don't know.
3057 ;; Oh well, we match it in movcc, so it must be partially our fault.
3059 [(set (match_operand 0 "register_operand")
3060 (if_then_else (match_operator 1 "signed_comparison_operator"
3062 (match_operand:DI 2 "reg_or_0_operand")])
3063 (match_operand 3 "const_int_operand")
3064 (match_operand 4 "const_int_operand")))]
3068 if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])),
3069 operands[0], operands[2], operands[3],
3076 (define_insn_and_split "*cmp_sadd_di"
3077 [(set (match_operand:DI 0 "register_operand" "=r")
3078 (plus:DI (if_then_else:DI
3079 (match_operator 1 "alpha_zero_comparison_operator"
3080 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3082 (match_operand:DI 3 "const48_operand" "I")
3084 (match_operand:DI 4 "sext_add_operand" "rIO")))
3085 (clobber (match_scratch:DI 5 "=r"))]
3090 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
3092 (plus:DI (ashift:DI (match_dup 5) (match_dup 3))
3095 operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3])));
3096 if (can_create_pseudo_p ())
3097 operands[5] = gen_reg_rtx (DImode);
3098 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
3099 operands[5] = operands[0];
3102 (define_insn_and_split "*cmp_sadd_si"
3103 [(set (match_operand:SI 0 "register_operand" "=r")
3104 (plus:SI (if_then_else:SI
3105 (match_operator 1 "alpha_zero_comparison_operator"
3106 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3108 (match_operand:SI 3 "const48_operand" "I")
3110 (match_operand:SI 4 "sext_add_operand" "rIO")))
3111 (clobber (match_scratch:DI 5 "=r"))]
3116 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
3118 (plus:SI (ashift:SI (match_dup 6) (match_dup 3))
3121 operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3])));
3122 if (can_create_pseudo_p ())
3123 operands[5] = gen_reg_rtx (DImode);
3124 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
3125 operands[5] = gen_lowpart (DImode, operands[0]);
3127 operands[6] = gen_lowpart (SImode, operands[5]);
3130 (define_insn_and_split "*cmp_sadd_sidi"
3131 [(set (match_operand:DI 0 "register_operand" "=r")
3133 (plus:SI (if_then_else:SI
3134 (match_operator 1 "alpha_zero_comparison_operator"
3135 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3137 (match_operand:SI 3 "const48_operand" "I")
3139 (match_operand:SI 4 "sext_add_operand" "rIO"))))
3140 (clobber (match_scratch:DI 5 "=r"))]
3145 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
3147 (sign_extend:DI (plus:SI (ashift:SI (match_dup 6) (match_dup 3))
3150 operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3])));
3151 if (can_create_pseudo_p ())
3152 operands[5] = gen_reg_rtx (DImode);
3153 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
3154 operands[5] = operands[0];
3156 operands[6] = gen_lowpart (SImode, operands[5]);
3159 (define_insn_and_split "*cmp_ssub_di"
3160 [(set (match_operand:DI 0 "register_operand" "=r")
3161 (minus:DI (if_then_else:DI
3162 (match_operator 1 "alpha_zero_comparison_operator"
3163 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3165 (match_operand:DI 3 "const48_operand" "I")
3167 (match_operand:DI 4 "reg_or_8bit_operand" "rI")))
3168 (clobber (match_scratch:DI 5 "=r"))]
3173 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
3175 (minus:DI (ashift:DI (match_dup 5) (match_dup 3))
3178 operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3])));
3179 if (can_create_pseudo_p ())
3180 operands[5] = gen_reg_rtx (DImode);
3181 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
3182 operands[5] = operands[0];
3185 (define_insn_and_split "*cmp_ssub_si"
3186 [(set (match_operand:SI 0 "register_operand" "=r")
3187 (minus:SI (if_then_else:SI
3188 (match_operator 1 "alpha_zero_comparison_operator"
3189 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3191 (match_operand:SI 3 "const48_operand" "I")
3193 (match_operand:SI 4 "reg_or_8bit_operand" "rI")))
3194 (clobber (match_scratch:DI 5 "=r"))]
3199 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
3201 (minus:SI (ashift:SI (match_dup 6) (match_dup 3))
3204 operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3])));
3205 if (can_create_pseudo_p ())
3206 operands[5] = gen_reg_rtx (DImode);
3207 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
3208 operands[5] = gen_lowpart (DImode, operands[0]);
3210 operands[6] = gen_lowpart (SImode, operands[5]);
3213 (define_insn_and_split "*cmp_ssub_sidi"
3214 [(set (match_operand:DI 0 "register_operand" "=r")
3216 (minus:SI (if_then_else:SI
3217 (match_operator 1 "alpha_zero_comparison_operator"
3218 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3220 (match_operand:SI 3 "const48_operand" "I")
3222 (match_operand:SI 4 "reg_or_8bit_operand" "rI"))))
3223 (clobber (match_scratch:DI 5 "=r"))]
3228 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
3230 (sign_extend:DI (minus:SI (ashift:SI (match_dup 6) (match_dup 3))
3233 operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3])));
3234 if (can_create_pseudo_p ())
3235 operands[5] = gen_reg_rtx (DImode);
3236 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
3237 operands[5] = operands[0];
3239 operands[6] = gen_lowpart (SImode, operands[5]);
3242 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
3243 ;; work differently, so we have different patterns for each.
3245 (define_expand "call"
3246 [(use (match_operand:DI 0))
3247 (use (match_operand 1))
3248 (use (match_operand 2))
3249 (use (match_operand 3))]
3252 if (TARGET_ABI_OPEN_VMS)
3253 emit_call_insn (gen_call_vms (operands[0], operands[2]));
3255 emit_call_insn (gen_call_osf (operands[0], operands[1]));
3259 (define_expand "sibcall"
3260 [(parallel [(call (mem:DI (match_operand 0))
3262 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
3265 gcc_assert (MEM_P (operands[0]));
3266 operands[0] = XEXP (operands[0], 0);
3269 (define_expand "call_osf"
3270 [(parallel [(call (mem:DI (match_operand 0))
3273 (clobber (reg:DI 26))])]
3276 gcc_assert (MEM_P (operands[0]));
3278 operands[0] = XEXP (operands[0], 0);
3279 if (! call_operand (operands[0], Pmode))
3280 operands[0] = copy_to_mode_reg (Pmode, operands[0]);
3284 ;; call openvms/alpha
3285 ;; op 0: symbol ref for called function
3286 ;; op 1: next_arg_reg (argument information value for R25)
3288 (define_expand "call_vms"
3289 [(parallel [(call (mem:DI (match_operand 0))
3294 (clobber (reg:DI 27))])]
3297 gcc_assert (MEM_P (operands[0]));
3299 operands[0] = XEXP (operands[0], 0);
3301 /* Always load AI with argument information, then handle symbolic and
3302 indirect call differently. Load RA and set operands[2] to PV in
3305 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
3306 if (GET_CODE (operands[0]) == SYMBOL_REF)
3308 operands[2] = const0_rtx;
3312 emit_move_insn (gen_rtx_REG (Pmode, 26),
3313 gen_rtx_MEM (Pmode, plus_constant (Pmode,
3315 operands[2] = operands[0];
3319 (define_expand "call_value"
3320 [(use (match_operand 0))
3321 (use (match_operand:DI 1))
3322 (use (match_operand 2))
3323 (use (match_operand 3))
3324 (use (match_operand 4))]
3327 if (TARGET_ABI_OPEN_VMS)
3328 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
3331 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
3336 (define_expand "sibcall_value"
3337 [(parallel [(set (match_operand 0)
3338 (call (mem:DI (match_operand 1))
3340 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
3343 gcc_assert (MEM_P (operands[1]));
3344 operands[1] = XEXP (operands[1], 0);
3347 (define_expand "call_value_osf"
3348 [(parallel [(set (match_operand 0)
3349 (call (mem:DI (match_operand 1))
3352 (clobber (reg:DI 26))])]
3355 gcc_assert (MEM_P (operands[1]));
3357 operands[1] = XEXP (operands[1], 0);
3358 if (! call_operand (operands[1], Pmode))
3359 operands[1] = copy_to_mode_reg (Pmode, operands[1]);
3362 (define_expand "call_value_vms"
3363 [(parallel [(set (match_operand 0)
3364 (call (mem:DI (match_operand:DI 1))
3369 (clobber (reg:DI 27))])]
3372 gcc_assert (MEM_P (operands[1]));
3374 operands[1] = XEXP (operands[1], 0);
3376 /* Always load AI with argument information, then handle symbolic and
3377 indirect call differently. Load RA and set operands[3] to PV in
3380 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
3381 if (GET_CODE (operands[1]) == SYMBOL_REF)
3383 operands[3] = const0_rtx;
3387 emit_move_insn (gen_rtx_REG (Pmode, 26),
3388 gen_rtx_MEM (Pmode, plus_constant (Pmode,
3390 operands[3] = operands[1];
3394 (define_insn "*call_osf_1_er_noreturn"
3395 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
3398 (clobber (reg:DI 26))]
3399 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
3400 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
3403 bsr $26,%0\t\t!samegp
3404 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#"
3405 [(set_attr "type" "jsr")
3406 (set_attr "length" "*,*,8")])
3408 (define_insn "*call_osf_1_er"
3409 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
3412 (clobber (reg:DI 26))]
3413 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
3415 jsr $26,(%0),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
3416 bsr $26,%0\t\t!samegp
3417 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
3418 [(set_attr "type" "jsr")
3419 (set_attr "length" "12,*,16")])
3421 ;; We must use peep2 instead of a split because we need accurate life
3422 ;; information for $gp. Consider the case of { bar(); while (1); }.
3424 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand"))
3427 (clobber (reg:DI 26))])]
3428 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
3429 && ! samegp_function_operand (operands[0], Pmode)
3430 && (peep2_regno_dead_p (1, 29)
3431 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
3432 [(parallel [(call (mem:DI (match_dup 2))
3437 (clobber (reg:DI 26))])]
3439 if (CONSTANT_P (operands[0]))
3441 operands[2] = gen_rtx_REG (Pmode, 27);
3442 operands[3] = GEN_INT (alpha_next_sequence_number++);
3443 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
3444 operands[0], operands[3]));
3448 operands[2] = operands[0];
3449 operands[0] = const0_rtx;
3450 operands[3] = const0_rtx;
3455 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand"))
3458 (clobber (reg:DI 26))])]
3459 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
3460 && ! samegp_function_operand (operands[0], Pmode)
3461 && ! (peep2_regno_dead_p (1, 29)
3462 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
3463 [(parallel [(call (mem:DI (match_dup 2))
3466 (unspec:DI [(match_dup 5) (match_dup 3)] UNSPEC_LDGP1))
3469 (clobber (reg:DI 26))])
3471 (unspec:DI [(match_dup 5) (match_dup 3)] UNSPEC_LDGP2))]
3473 if (CONSTANT_P (operands[0]))
3475 operands[2] = gen_rtx_REG (Pmode, 27);
3476 operands[4] = GEN_INT (alpha_next_sequence_number++);
3477 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
3478 operands[0], operands[4]));
3482 operands[2] = operands[0];
3483 operands[0] = const0_rtx;
3484 operands[4] = const0_rtx;
3486 operands[3] = GEN_INT (alpha_next_sequence_number++);
3487 operands[5] = pic_offset_table_rtx;
3490 (define_insn "*call_osf_2_er_nogp"
3491 [(call (mem:DI (match_operand:DI 0 "register_operand" "c"))
3494 (use (match_operand 2))
3495 (use (match_operand 3 "const_int_operand"))
3496 (clobber (reg:DI 26))]
3497 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
3498 "jsr $26,(%0),%2%J3"
3499 [(set_attr "type" "jsr")])
3501 (define_insn "*call_osf_2_er"
3502 [(call (mem:DI (match_operand:DI 0 "register_operand" "c"))
3505 (unspec:DI [(reg:DI 29) (match_operand 4 "const_int_operand")]
3507 (use (match_operand 2))
3508 (use (match_operand 3 "const_int_operand"))
3509 (clobber (reg:DI 26))]
3510 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
3511 "jsr $26,(%0),%2%J3\;ldah $29,0($26)\t\t!gpdisp!%4"
3512 [(set_attr "type" "jsr")
3513 (set_attr "cannot_copy" "true")
3514 (set_attr "length" "8")])
3516 (define_insn "*call_osf_1_noreturn"
3517 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
3520 (clobber (reg:DI 26))]
3521 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
3522 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
3527 [(set_attr "type" "jsr")
3528 (set_attr "length" "*,*,8")])
3530 (define_insn "*call_osf_1"
3531 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
3534 (clobber (reg:DI 26))]
3535 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
3537 jsr $26,($27),0\;ldgp $29,0($26)
3539 jsr $26,%0\;ldgp $29,0($26)"
3540 [(set_attr "type" "jsr")
3541 (set_attr "length" "12,*,16")])
3543 (define_insn "*sibcall_osf_1_er"
3544 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
3546 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
3547 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
3549 br $31,%0\t\t!samegp
3550 ldq $27,%0($29)\t\t!literal!%#\;jmp $31,($27),%0\t\t!lituse_jsr!%#"
3551 [(set_attr "type" "jsr")
3552 (set_attr "length" "*,8")])
3554 ;; Note that the DEC assembler expands "jmp foo" with $at, which
3555 ;; doesn't do what we want.
3556 (define_insn "*sibcall_osf_1"
3557 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
3559 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
3560 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
3563 lda $27,%0\;jmp $31,($27),%0"
3564 [(set_attr "type" "jsr")
3565 (set_attr "length" "*,8")])
3567 ; GAS relies on the order and position of instructions output below in order
3568 ; to generate relocs for VMS link to potentially optimize the call.
3569 ; Please do not molest.
3570 (define_insn "*call_vms_1"
3571 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,s"))
3573 (use (match_operand:DI 2 "nonmemory_operand" "r,n"))
3576 (clobber (reg:DI 27))]
3577 "TARGET_ABI_OPEN_VMS"
3579 switch (which_alternative)
3582 return "mov %2,$27\;jsr $26,0\;ldq $27,0($29)";
3584 operands [2] = alpha_use_linkage (operands [0], true, false);
3585 operands [3] = alpha_use_linkage (operands [0], false, false);
3586 return "ldq $26,%3\;ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)";
3591 [(set_attr "type" "jsr")
3592 (set_attr "length" "12,16")])
3594 ;; Call subroutine returning any type.
3596 (define_expand "untyped_call"
3597 [(parallel [(call (match_operand 0)
3600 (match_operand 2)])]
3605 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
3607 for (i = 0; i < XVECLEN (operands[2], 0); i++)
3609 rtx set = XVECEXP (operands[2], 0, i);
3610 emit_move_insn (SET_DEST (set), SET_SRC (set));
3613 /* The optimizer does not know that the call sets the function value
3614 registers we stored in the result block. We avoid problems by
3615 claiming that all hard registers are used and clobbered at this
3617 emit_insn (gen_blockage ());
3622 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
3623 ;; all of memory. This blocks insns from being moved across this point.
3625 (define_insn "blockage"
3626 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
3629 [(set_attr "length" "0")
3630 (set_attr "type" "none")])
3634 (label_ref (match_operand 0)))]
3637 [(set_attr "type" "ibr")])
3639 (define_expand "return"
3643 (define_insn "*return_internal"
3647 [(set_attr "type" "ibr")])
3649 (define_insn "indirect_jump"
3650 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
3653 [(set_attr "type" "ibr")])
3655 (define_expand "tablejump"
3656 [(parallel [(set (pc)
3657 (match_operand 0 "register_operand"))
3658 (use (label_ref:DI (match_operand 1)))])]
3663 rtx dest = gen_reg_rtx (DImode);
3664 emit_insn (gen_extendsidi2 (dest, operands[0]));
3665 emit_insn (gen_adddi3 (dest, pic_offset_table_rtx, dest));
3670 (define_insn "*tablejump_internal"
3672 (match_operand:DI 0 "register_operand" "r"))
3673 (use (label_ref (match_operand 1)))]
3676 [(set_attr "type" "ibr")])
3678 ;; Cache flush. Used by alpha_trampoline_init. 0x86 is PAL_imb, but we don't
3679 ;; want to have to include pal.h in our .s file.
3681 [(unspec_volatile [(const_int 0)] UNSPECV_IMB)]
3684 [(set_attr "type" "callpal")])
3686 (define_expand "clear_cache"
3687 [(match_operand:DI 0) ; region start
3688 (match_operand:DI 1)] ; region end
3691 emit_insn (gen_imb ());
3695 ;; BUGCHK is documented common to OSF/1 and VMS PALcode.
3697 [(trap_if (const_int 1) (const_int 0))
3701 [(set_attr "type" "callpal")])
3703 ;; For userland, we load the thread pointer from the TCB.
3704 ;; For the kernel, we load the per-cpu private value.
3706 (define_insn "get_thread_pointerdi"
3707 [(set (match_operand:DI 0 "register_operand" "=v")
3708 (unspec:DI [(const_int 0)] UNSPEC_TP))]
3711 if (TARGET_TLS_KERNEL)
3712 return "call_pal 0x32";
3714 return "call_pal 0x9e";
3716 [(set_attr "type" "callpal")])
3718 ;; For completeness, and possibly a __builtin function, here's how to
3719 ;; set the thread pointer. Since we don't describe enough of this
3720 ;; quantity for CSE, we have to use a volatile unspec, and then there's
3721 ;; not much point in creating an R16_REG register class.
3723 (define_expand "set_thread_pointerdi"
3724 [(set (reg:DI 16) (match_operand:DI 0 "input_operand"))
3725 (unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
3728 (define_insn "*set_tp"
3729 [(unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
3732 if (TARGET_TLS_KERNEL)
3733 return "call_pal 0x31";
3735 return "call_pal 0x9f";
3737 [(set_attr "type" "callpal")])
3739 ;; Special builtins for establishing and reverting VMS condition handlers.
3741 (define_expand "builtin_establish_vms_condition_handler"
3742 [(set (reg:DI 0) (match_operand:DI 0 "register_operand"))
3743 (use (match_operand:DI 1 "address_operand"))]
3744 "TARGET_ABI_OPEN_VMS"
3746 alpha_expand_builtin_establish_vms_condition_handler (operands[0],
3750 (define_expand "builtin_revert_vms_condition_handler"
3751 [(set (reg:DI 0) (match_operand:DI 0 "register_operand"))]
3752 "TARGET_ABI_OPEN_VMS"
3753 "alpha_expand_builtin_revert_vms_condition_handler (operands[0]);")
3755 ;; Finally, we have the basic data motion insns. The byte and word insns
3756 ;; are done via define_expand. Start with the floating-point insns, since
3757 ;; they are simpler.
3759 (define_expand "movsf"
3760 [(set (match_operand:SF 0 "nonimmediate_operand")
3761 (match_operand:SF 1 "general_operand"))]
3764 if (MEM_P (operands[0])
3765 && ! reg_or_0_operand (operands[1], SFmode))
3766 operands[1] = force_reg (SFmode, operands[1]);
3769 (define_insn "*movsf"
3770 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
3771 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
3772 "register_operand (operands[0], SFmode)
3773 || reg_or_0_operand (operands[1], SFmode)"
3783 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")
3784 (set_attr "isa" "*,*,*,*,*,*,fix,fix")])
3786 (define_expand "movdf"
3787 [(set (match_operand:DF 0 "nonimmediate_operand")
3788 (match_operand:DF 1 "general_operand"))]
3791 if (MEM_P (operands[0])
3792 && ! reg_or_0_operand (operands[1], DFmode))
3793 operands[1] = force_reg (DFmode, operands[1]);
3796 (define_insn "*movdf"
3797 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
3798 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
3799 "register_operand (operands[0], DFmode)
3800 || reg_or_0_operand (operands[1], DFmode)"
3810 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")
3811 (set_attr "isa" "*,*,*,*,*,*,fix,fix")])
3813 ;; Subregs suck for register allocation. Pretend we can move TFmode
3814 ;; data between general registers until after reload.
3815 ;; ??? Is this still true now that we have the lower-subreg pass?
3817 (define_expand "movtf"
3818 [(set (match_operand:TF 0 "nonimmediate_operand")
3819 (match_operand:TF 1 "general_operand"))]
3822 if (MEM_P (operands[0])
3823 && ! reg_or_0_operand (operands[1], TFmode))
3824 operands[1] = force_reg (TFmode, operands[1]);
3827 (define_insn_and_split "*movtf_internal"
3828 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
3829 (match_operand:TF 1 "input_operand" "roG,rG"))]
3830 "register_operand (operands[0], TFmode)
3831 || reg_or_0_operand (operands[1], TFmode)"
3834 [(set (match_dup 0) (match_dup 2))
3835 (set (match_dup 1) (match_dup 3))]
3836 "alpha_split_tmode_pair (operands, TFmode, true);")
3838 ;; We do two major things here: handle mem->mem and construct long
3841 (define_expand "movsi"
3842 [(set (match_operand:SI 0 "nonimmediate_operand")
3843 (match_operand:SI 1 "general_operand"))]
3846 if (alpha_expand_mov (SImode, operands))
3850 (define_insn "*movsi"
3851 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,r")
3852 (match_operand:SI 1 "input_operand" "rJ,K,L,n,m,rJ,s"))]
3853 "register_operand (operands[0], SImode)
3854 || reg_or_0_operand (operands[1], SImode)"
3863 [(set_attr "type" "ilog,iadd,iadd,multi,ild,ist,ldsym")
3864 (set_attr "isa" "*,*,*,*,*,*,vms")])
3866 ;; Split a load of a large constant into the appropriate two-insn
3870 [(set (match_operand:SI 0 "register_operand")
3871 (match_operand:SI 1 "non_add_const_operand"))]
3875 if (alpha_split_const_mov (SImode, operands))
3881 (define_insn "*movdi_er_low_l"
3882 [(set (match_operand:DI 0 "register_operand" "=r")
3883 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
3884 (match_operand:DI 2 "local_symbolic_operand")))]
3885 "TARGET_EXPLICIT_RELOCS"
3887 if (true_regnum (operands[1]) == 29)
3888 return "lda %0,%2(%1)\t\t!gprel";
3890 return "lda %0,%2(%1)\t\t!gprellow";
3892 [(set_attr "usegp" "yes")])
3895 [(set (match_operand:DI 0 "register_operand")
3896 (match_operand:DI 1 "small_symbolic_operand"))]
3897 "TARGET_EXPLICIT_RELOCS && reload_completed"
3899 (lo_sum:DI (match_dup 2) (match_dup 1)))]
3900 "operands[2] = pic_offset_table_rtx;")
3903 [(set (match_operand:DI 0 "register_operand")
3904 (match_operand:DI 1 "local_symbolic_operand"))]
3905 "TARGET_EXPLICIT_RELOCS && reload_completed"
3907 (plus:DI (match_dup 2) (high:DI (match_dup 1))))
3909 (lo_sum:DI (match_dup 0) (match_dup 1)))]
3910 "operands[2] = pic_offset_table_rtx;")
3913 [(match_operand 0 "some_small_symbolic_operand")]
3916 "operands[0] = split_small_symbolic_operand (operands[0]);")
3918 ;; Accepts any symbolic, not just global, since function calls that
3919 ;; don't go via bsr still use !literal in hopes of linker relaxation.
3920 (define_insn "movdi_er_high_g"
3921 [(set (match_operand:DI 0 "register_operand" "=r")
3922 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
3923 (match_operand:DI 2 "symbolic_operand")
3924 (match_operand 3 "const_int_operand")]
3926 "TARGET_EXPLICIT_RELOCS"
3928 if (INTVAL (operands[3]) == 0)
3929 return "ldq %0,%2(%1)\t\t!literal";
3931 return "ldq %0,%2(%1)\t\t!literal!%3";
3933 [(set_attr "type" "ldsym")])
3936 [(set (match_operand:DI 0 "register_operand")
3937 (match_operand:DI 1 "global_symbolic_operand"))]
3938 "TARGET_EXPLICIT_RELOCS && reload_completed"
3940 (unspec:DI [(match_dup 2)
3942 (const_int 0)] UNSPEC_LITERAL))]
3943 "operands[2] = pic_offset_table_rtx;")
3945 (define_insn "movdi_er_tlsgd"
3946 [(set (match_operand:DI 0 "register_operand" "=r")
3947 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
3948 (match_operand:DI 2 "symbolic_operand")
3949 (match_operand 3 "const_int_operand")]
3953 if (INTVAL (operands[3]) == 0)
3954 return "lda %0,%2(%1)\t\t!tlsgd";
3956 return "lda %0,%2(%1)\t\t!tlsgd!%3";
3959 (define_insn "movdi_er_tlsldm"
3960 [(set (match_operand:DI 0 "register_operand" "=r")
3961 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
3962 (match_operand 2 "const_int_operand")]
3966 if (INTVAL (operands[2]) == 0)
3967 return "lda %0,%&(%1)\t\t!tlsldm";
3969 return "lda %0,%&(%1)\t\t!tlsldm!%2";
3972 (define_insn "*movdi_er_gotdtp"
3973 [(set (match_operand:DI 0 "register_operand" "=r")
3974 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
3975 (match_operand:DI 2 "symbolic_operand")]
3978 "ldq %0,%2(%1)\t\t!gotdtprel"
3979 [(set_attr "type" "ild")
3980 (set_attr "usegp" "yes")])
3983 [(set (match_operand:DI 0 "register_operand")
3984 (match_operand:DI 1 "gotdtp_symbolic_operand"))]
3985 "HAVE_AS_TLS && reload_completed"
3987 (unspec:DI [(match_dup 2)
3988 (match_dup 1)] UNSPEC_DTPREL))]
3990 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
3991 operands[2] = pic_offset_table_rtx;
3994 (define_insn "*movdi_er_gottp"
3995 [(set (match_operand:DI 0 "register_operand" "=r")
3996 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
3997 (match_operand:DI 2 "symbolic_operand")]
4000 "ldq %0,%2(%1)\t\t!gottprel"
4001 [(set_attr "type" "ild")
4002 (set_attr "usegp" "yes")])
4005 [(set (match_operand:DI 0 "register_operand")
4006 (match_operand:DI 1 "gottp_symbolic_operand"))]
4007 "HAVE_AS_TLS && reload_completed"
4009 (unspec:DI [(match_dup 2)
4010 (match_dup 1)] UNSPEC_TPREL))]
4012 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
4013 operands[2] = pic_offset_table_rtx;
4016 (define_insn "*movdi"
4017 [(set (match_operand:DI 0 "nonimmediate_operand"
4018 "=r,r,r,r,r,r,r,r, m, *f,*f, Q, r,*f")
4019 (match_operand:DI 1 "input_operand"
4020 "rJ,K,L,T,s,n,s,m,rJ,*fJ, Q,*f,*f, r"))]
4021 "register_operand (operands[0], DImode)
4022 || reg_or_0_operand (operands[1], DImode)"
4038 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,multi,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")
4039 (set_attr "isa" "*,*,*,er,er,*,ner,*,*,*,*,*,fix,fix")
4040 (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*,*,*,*")])
4042 ;; VMS needs to set up "vms_base_regno" for unwinding. This move
4043 ;; often appears dead to the life analysis code, at which point we
4044 ;; die for emitting dead prologue instructions. Force this live.
4046 (define_insn "force_movdi"
4047 [(set (match_operand:DI 0 "register_operand" "=r")
4048 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")]
4049 UNSPECV_FORCE_MOV))]
4052 [(set_attr "type" "ilog")])
4054 ;; We do three major things here: handle mem->mem, put 64-bit constants in
4055 ;; memory, and construct long 32-bit constants.
4057 (define_expand "movdi"
4058 [(set (match_operand:DI 0 "nonimmediate_operand")
4059 (match_operand:DI 1 "general_operand"))]
4062 if (alpha_expand_mov (DImode, operands))
4066 ;; Split a load of a large constant into the appropriate two-insn
4070 [(set (match_operand:DI 0 "register_operand")
4071 (match_operand:DI 1 "non_add_const_operand"))]
4075 if (alpha_split_const_mov (DImode, operands))
4081 ;; We need to prevent reload from splitting TImode moves, because it
4082 ;; might decide to overwrite a pointer with the value it points to.
4083 ;; In that case we have to do the loads in the appropriate order so
4084 ;; that the pointer is not destroyed too early.
4086 (define_insn_and_split "*movti_internal"
4087 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o")
4088 (match_operand:TI 1 "input_operand" "roJ,rJ"))]
4089 "(register_operand (operands[0], TImode)
4090 /* Prevent rematerialization of constants. */
4091 && ! CONSTANT_P (operands[1]))
4092 || reg_or_0_operand (operands[1], TImode)"
4095 [(set (match_dup 0) (match_dup 2))
4096 (set (match_dup 1) (match_dup 3))]
4097 "alpha_split_tmode_pair (operands, TImode, true);")
4099 (define_expand "movti"
4100 [(set (match_operand:TI 0 "nonimmediate_operand")
4101 (match_operand:TI 1 "general_operand"))]
4104 if (MEM_P (operands[0])
4105 && ! reg_or_0_operand (operands[1], TImode))
4106 operands[1] = force_reg (TImode, operands[1]);
4108 if (operands[1] == const0_rtx)
4110 /* We must put 64-bit constants in memory. We could keep the
4111 32-bit constants in TImode and rely on the splitter, but
4112 this doesn't seem to be worth the pain. */
4113 else if (CONST_SCALAR_INT_P (operands[1]))
4115 rtx in[2], out[2], target;
4117 gcc_assert (can_create_pseudo_p ());
4119 split_double (operands[1], &in[0], &in[1]);
4121 if (in[0] == const0_rtx)
4122 out[0] = const0_rtx;
4125 out[0] = gen_reg_rtx (DImode);
4126 emit_insn (gen_movdi (out[0], in[0]));
4129 if (in[1] == const0_rtx)
4130 out[1] = const0_rtx;
4133 out[1] = gen_reg_rtx (DImode);
4134 emit_insn (gen_movdi (out[1], in[1]));
4137 if (!REG_P (operands[0]))
4138 target = gen_reg_rtx (TImode);
4140 target = operands[0];
4142 emit_insn (gen_movdi (operand_subword (target, 0, 0, TImode), out[0]));
4143 emit_insn (gen_movdi (operand_subword (target, 1, 0, TImode), out[1]));
4145 if (target != operands[0])
4146 emit_insn (gen_rtx_SET (operands[0], target));
4152 ;; These are the partial-word cases.
4154 ;; First we have the code to load an aligned word. Operand 0 is the register
4155 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
4156 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
4157 ;; number of bits within the word that the value is. Operand 3 is an SImode
4158 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
4159 ;; same register. It is allowed to conflict with operand 1 as well.
4161 (define_expand "aligned_loadqi"
4162 [(set (match_operand:SI 3 "register_operand")
4163 (match_operand:SI 1 "memory_operand"))
4164 (set (match_operand:DI 0 "register_operand")
4165 (zero_extract:DI (subreg:DI (match_dup 3) 0)
4167 (match_operand:DI 2 "const_int_operand")))])
4169 (define_expand "aligned_loadhi"
4170 [(set (match_operand:SI 3 "register_operand")
4171 (match_operand:SI 1 "memory_operand"))
4172 (set (match_operand:DI 0 "register_operand")
4173 (zero_extract:DI (subreg:DI (match_dup 3) 0)
4175 (match_operand:DI 2 "const_int_operand")))])
4177 ;; Similar for unaligned loads, where we use the sequence from the
4178 ;; Alpha Architecture manual. We have to distinguish between little-endian
4179 ;; and big-endian systems as the sequences are different.
4181 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
4182 ;; operand 3 can overlap the input and output registers.
4184 (define_expand "unaligned_loadqi"
4185 [(set (match_operand:DI 2 "register_operand")
4186 (mem:DI (and:DI (match_operand:DI 1 "address_operand")
4188 (set (match_operand:DI 3 "register_operand")
4190 (set (match_operand:DI 0 "register_operand")
4191 (zero_extract:DI (match_dup 2)
4193 (ashift:DI (match_dup 3) (const_int 3))))])
4195 (define_expand "unaligned_loadhi"
4196 [(set (match_operand:DI 2 "register_operand")
4197 (mem:DI (and:DI (match_operand:DI 1 "address_operand")
4199 (set (match_operand:DI 3 "register_operand")
4201 (set (match_operand:DI 0 "register_operand")
4202 (zero_extract:DI (match_dup 2)
4204 (ashift:DI (match_dup 3) (const_int 3))))])
4206 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
4207 ;; aligned SImode MEM. Operand 1 is the register containing the
4208 ;; byte or word to store. Operand 2 is the number of bits within the word that
4209 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
4211 (define_expand "aligned_store"
4212 [(set (match_operand:SI 3 "register_operand")
4213 (match_operand:SI 0 "memory_operand"))
4214 (set (subreg:DI (match_dup 3) 0)
4215 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
4216 (set (subreg:DI (match_operand:SI 4 "register_operand") 0)
4217 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand"))
4218 (match_operand:DI 2 "const_int_operand")))
4219 (set (subreg:DI (match_dup 4) 0)
4220 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
4221 (set (match_dup 0) (match_dup 4))]
4224 operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
4225 << INTVAL (operands[2])));
4228 ;; For the unaligned byte and halfword cases, we use code similar to that
4229 ;; in the ;; Architecture book, but reordered to lower the number of registers
4230 ;; required. Operand 0 is the address. Operand 1 is the data to store.
4231 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
4232 ;; be the same temporary, if desired. If the address is in a register,
4233 ;; operand 2 can be that register.
4235 (define_expand "@unaligned_store<mode>"
4236 [(set (match_operand:DI 3 "register_operand")
4237 (mem:DI (and:DI (match_operand:DI 0 "address_operand")
4239 (set (match_operand:DI 2 "register_operand")
4242 (and:DI (not:DI (ashift:DI (match_dup 5)
4243 (ashift:DI (match_dup 2) (const_int 3))))
4245 (set (match_operand:DI 4 "register_operand")
4246 (ashift:DI (zero_extend:DI
4247 (match_operand:I12MODE 1 "register_operand"))
4248 (ashift:DI (match_dup 2) (const_int 3))))
4249 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
4250 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
4253 "operands[5] = GEN_INT (GET_MODE_MASK (<MODE>mode));")
4255 ;; Here are the define_expand's for QI and HI moves that use the above
4256 ;; patterns. We have the normal sets, plus the ones that need scratch
4257 ;; registers for reload.
4259 (define_expand "mov<mode>"
4260 [(set (match_operand:I12MODE 0 "nonimmediate_operand")
4261 (match_operand:I12MODE 1 "general_operand"))]
4265 ? alpha_expand_mov (<MODE>mode, operands)
4266 : alpha_expand_mov_nobwx (<MODE>mode, operands))
4270 (define_insn "*movqi"
4271 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
4272 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
4273 "register_operand (operands[0], QImode)
4274 || reg_or_0_operand (operands[1], QImode)"
4280 [(set_attr "type" "ilog,iadd,ild,ist")
4281 (set_attr "isa" "*,*,bwx,bwx")])
4283 (define_insn "*movhi"
4284 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
4285 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
4286 "register_operand (operands[0], HImode)
4287 || reg_or_0_operand (operands[1], HImode)"
4293 [(set_attr "type" "ilog,iadd,ild,ist")
4294 (set_attr "isa" "*,*,bwx,bwx")])
4296 ;; We need to hook into the extra support that we have for HImode
4297 ;; reloads when BWX insns are not available.
4298 (define_expand "movcqi"
4299 [(set (match_operand:CQI 0 "nonimmediate_operand")
4300 (match_operand:CQI 1 "general_operand"))]
4303 if (GET_CODE (operands[0]) == CONCAT || GET_CODE (operands[1]) == CONCAT)
4305 else if (!any_memory_operand (operands[0], CQImode))
4307 if (!any_memory_operand (operands[1], CQImode))
4309 emit_move_insn (gen_lowpart (HImode, operands[0]),
4310 gen_lowpart (HImode, operands[1]));
4313 if (aligned_memory_operand (operands[1], CQImode))
4317 operands[1] = gen_lowpart (HImode, operands[1]);
4319 operands[0] = gen_lowpart (HImode, operands[0]);
4320 done = alpha_expand_mov_nobwx (HImode, operands);
4325 else if (aligned_memory_operand (operands[0], CQImode))
4327 if (MEM_P (operands[1]))
4329 rtx x = gen_reg_rtx (HImode);
4330 emit_move_insn (gen_lowpart (CQImode, x), operands[1]);
4337 gcc_assert (!reload_in_progress);
4338 emit_move_complex_parts (operands[0], operands[1]);
4342 ;; Here are the versions for reload.
4344 ;; The aligned input case is recognized early in alpha_secondary_reload
4345 ;; in order to avoid allocating an unnecessary scratch register.
4347 ;; Note that in the unaligned cases we know that the operand must not be
4348 ;; a pseudo-register because stack slots are always aligned references.
4350 (define_expand "reload_in<mode>"
4351 [(parallel [(match_operand:RELOAD12 0 "register_operand" "=r")
4352 (match_operand:RELOAD12 1 "any_memory_operand" "m")
4353 (match_operand:TI 2 "register_operand" "=&r")])]
4356 rtx scratch, seq, addr;
4357 unsigned regno = REGNO (operands[2]);
4359 /* It is possible that one of the registers we got for operands[2]
4360 might coincide with that of operands[0] (which is why we made
4361 it TImode). Pick the other one to use as our scratch. */
4362 if (regno == REGNO (operands[0]))
4364 scratch = gen_rtx_REG (DImode, regno);
4366 addr = get_unaligned_address (operands[1]);
4367 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
4368 seq = gen_unaligned_load<reloadmode> (operands[0], addr,
4369 scratch, operands[0]);
4370 alpha_set_memflags (seq, operands[1]);
4376 (define_expand "reload_out<mode>"
4377 [(parallel [(match_operand:RELOAD12 0 "any_memory_operand" "=m")
4378 (match_operand:RELOAD12 1 "register_operand" "r")
4379 (match_operand:TI 2 "register_operand" "=&r")])]
4382 unsigned regno = REGNO (operands[2]);
4384 if (<MODE>mode == CQImode)
4386 operands[0] = gen_lowpart (HImode, operands[0]);
4387 operands[1] = gen_lowpart (HImode, operands[1]);
4390 if (aligned_memory_operand (operands[0], <MODE>mode))
4392 emit_insn (gen_reload_out<reloadmode>_aligned
4393 (operands[0], operands[1],
4394 gen_rtx_REG (SImode, regno),
4395 gen_rtx_REG (SImode, regno + 1)));
4399 rtx addr = get_unaligned_address (operands[0]);
4400 rtx scratch1 = gen_rtx_REG (DImode, regno);
4401 rtx scratch2 = gen_rtx_REG (DImode, regno + 1);
4402 rtx scratch3 = scratch1;
4408 seq = gen_unaligned_store<reloadmode> (addr, operands[1], scratch1,
4409 scratch2, scratch3);
4410 alpha_set_memflags (seq, operands[0]);
4416 ;; Helpers for the above. The way reload is structured, we can't
4417 ;; always get a proper address for a stack slot during reload_foo
4418 ;; expansion, so we must delay our address manipulations until after.
4420 (define_insn_and_split "@reload_in<mode>_aligned"
4421 [(set (match_operand:I12MODE 0 "register_operand" "=r")
4422 (match_operand:I12MODE 1 "memory_operand" "m"))]
4423 "!TARGET_BWX && (reload_in_progress || reload_completed)"
4425 "!TARGET_BWX && reload_completed"
4428 rtx aligned_mem, bitnum;
4429 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
4430 emit_insn (gen_aligned_load<reloadmode>
4431 (gen_lowpart (DImode, operands[0]), aligned_mem, bitnum,
4432 gen_rtx_REG (SImode, REGNO (operands[0]))));
4436 (define_insn_and_split "reload_out<mode>_aligned"
4437 [(set (match_operand:I12MODE 0 "memory_operand" "=m")
4438 (match_operand:I12MODE 1 "register_operand" "r"))
4439 (clobber (match_operand:SI 2 "register_operand" "=&r"))
4440 (clobber (match_operand:SI 3 "register_operand" "=&r"))]
4441 "!TARGET_BWX && (reload_in_progress || reload_completed)"
4443 "!TARGET_BWX && reload_completed"
4446 rtx aligned_mem, bitnum;
4447 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
4448 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
4449 operands[2], operands[3]));
4453 ;; Vector operations
4455 (define_mode_iterator VEC [V8QI V4HI V2SI])
4456 (define_mode_iterator VEC12 [V8QI V4HI])
4458 (define_expand "mov<mode>"
4459 [(set (match_operand:VEC 0 "nonimmediate_operand")
4460 (match_operand:VEC 1 "general_operand"))]
4463 if (alpha_expand_mov (<MODE>mode, operands))
4468 [(set (match_operand:VEC 0 "register_operand")
4469 (match_operand:VEC 1 "non_zero_const_operand"))]
4473 if (alpha_split_const_mov (<MODE>mode, operands))
4480 (define_expand "movmisalign<mode>"
4481 [(set (match_operand:VEC 0 "nonimmediate_operand")
4482 (match_operand:VEC 1 "general_operand"))]
4485 alpha_expand_movmisalign (<MODE>mode, operands);
4489 (define_insn "*mov<mode>_fix"
4490 [(set (match_operand:VEC 0 "nonimmediate_operand" "=r,r,r,m,*f,*f,m,r,*f")
4491 (match_operand:VEC 1 "input_operand" "rW,i,m,rW,*fW,m,*f,*f,r"))]
4492 "register_operand (operands[0], <MODE>mode)
4493 || reg_or_0_operand (operands[1], <MODE>mode)"
4504 [(set_attr "type" "ilog,multi,ild,ist,fcpys,fld,fst,ftoi,itof")
4505 (set_attr "isa" "*,*,*,*,*,*,*,fix,fix")])
4507 (define_insn "<code><mode>3"
4508 [(set (match_operand:VEC12 0 "register_operand" "=r")
4510 (match_operand:VEC12 1 "reg_or_0_operand" "rW")
4511 (match_operand:VEC12 2 "reg_or_0_operand" "rW")))]
4513 "<maxmin><modesuffix> %r1,%r2,%0"
4514 [(set_attr "type" "mvi")])
4516 (define_insn "one_cmpl<mode>2"
4517 [(set (match_operand:VEC 0 "register_operand" "=r")
4518 (not:VEC (match_operand:VEC 1 "register_operand" "r")))]
4521 [(set_attr "type" "ilog")])
4523 (define_insn "and<mode>3"
4524 [(set (match_operand:VEC 0 "register_operand" "=r")
4525 (and:VEC (match_operand:VEC 1 "register_operand" "r")
4526 (match_operand:VEC 2 "register_operand" "r")))]
4529 [(set_attr "type" "ilog")])
4531 (define_insn "*andnot<mode>3"
4532 [(set (match_operand:VEC 0 "register_operand" "=r")
4533 (and:VEC (not:VEC (match_operand:VEC 1 "register_operand" "r"))
4534 (match_operand:VEC 2 "register_operand" "r")))]
4537 [(set_attr "type" "ilog")])
4539 (define_insn "ior<mode>3"
4540 [(set (match_operand:VEC 0 "register_operand" "=r")
4541 (ior:VEC (match_operand:VEC 1 "register_operand" "r")
4542 (match_operand:VEC 2 "register_operand" "r")))]
4545 [(set_attr "type" "ilog")])
4547 (define_insn "*iornot<mode>3"
4548 [(set (match_operand:VEC 0 "register_operand" "=r")
4549 (ior:VEC (not:DI (match_operand:VEC 1 "register_operand" "r"))
4550 (match_operand:VEC 2 "register_operand" "r")))]
4553 [(set_attr "type" "ilog")])
4555 (define_insn "xor<mode>3"
4556 [(set (match_operand:VEC 0 "register_operand" "=r")
4557 (xor:VEC (match_operand:VEC 1 "register_operand" "r")
4558 (match_operand:VEC 2 "register_operand" "r")))]
4561 [(set_attr "type" "ilog")])
4563 (define_insn "*xornot<mode>3"
4564 [(set (match_operand:VEC 0 "register_operand" "=r")
4565 (not:VEC (xor:VEC (match_operand:VEC 1 "register_operand" "r")
4566 (match_operand:VEC 2 "register_operand" "r"))))]
4569 [(set_attr "type" "ilog")])
4571 (define_expand "vec_shl_<mode>"
4572 [(set (match_operand:VEC 0 "register_operand")
4573 (ashift:DI (match_operand:VEC 1 "register_operand")
4574 (match_operand:DI 2 "reg_or_6bit_operand")))]
4577 operands[0] = gen_lowpart (DImode, operands[0]);
4578 operands[1] = gen_lowpart (DImode, operands[1]);
4581 (define_expand "vec_shr_<mode>"
4582 [(set (match_operand:VEC 0 "register_operand")
4583 (lshiftrt:DI (match_operand:VEC 1 "register_operand")
4584 (match_operand:DI 2 "reg_or_6bit_operand")))]
4587 operands[0] = gen_lowpart (DImode, operands[0]);
4588 operands[1] = gen_lowpart (DImode, operands[1]);
4591 ;; Bit field extract patterns which use ext[wlq][lh]
4593 (define_expand "extvmisaligndi"
4594 [(set (match_operand:DI 0 "register_operand")
4595 (sign_extract:DI (match_operand:BLK 1 "memory_operand")
4596 (match_operand:DI 2 "const_int_operand")
4597 (match_operand:DI 3 "const_int_operand")))]
4600 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
4601 if (INTVAL (operands[3]) % 8 != 0
4602 || (INTVAL (operands[2]) != 16
4603 && INTVAL (operands[2]) != 32
4604 && INTVAL (operands[2]) != 64))
4607 alpha_expand_unaligned_load (operands[0], operands[1],
4608 INTVAL (operands[2]) / 8,
4609 INTVAL (operands[3]) / 8, 1);
4613 (define_expand "extzvdi"
4614 [(set (match_operand:DI 0 "register_operand")
4615 (zero_extract:DI (match_operand:DI 1 "register_operand")
4616 (match_operand:DI 2 "const_int_operand")
4617 (match_operand:DI 3 "const_int_operand")))]
4620 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
4621 if (INTVAL (operands[3]) % 8 != 0
4622 || (INTVAL (operands[2]) != 8
4623 && INTVAL (operands[2]) != 16
4624 && INTVAL (operands[2]) != 32
4625 && INTVAL (operands[2]) != 64))
4629 (define_expand "extzvmisaligndi"
4630 [(set (match_operand:DI 0 "register_operand")
4631 (zero_extract:DI (match_operand:BLK 1 "memory_operand")
4632 (match_operand:DI 2 "const_int_operand")
4633 (match_operand:DI 3 "const_int_operand")))]
4636 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries.
4637 We fail 8-bit fields, falling back on a simple byte load. */
4638 if (INTVAL (operands[3]) % 8 != 0
4639 || (INTVAL (operands[2]) != 16
4640 && INTVAL (operands[2]) != 32
4641 && INTVAL (operands[2]) != 64))
4644 alpha_expand_unaligned_load (operands[0], operands[1],
4645 INTVAL (operands[2]) / 8,
4646 INTVAL (operands[3]) / 8, 0);
4650 (define_expand "insvmisaligndi"
4651 [(set (zero_extract:DI (match_operand:BLK 0 "memory_operand")
4652 (match_operand:DI 1 "const_int_operand")
4653 (match_operand:DI 2 "const_int_operand"))
4654 (match_operand:DI 3 "register_operand"))]
4657 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
4658 if (INTVAL (operands[2]) % 8 != 0
4659 || (INTVAL (operands[1]) != 16
4660 && INTVAL (operands[1]) != 32
4661 && INTVAL (operands[1]) != 64))
4664 alpha_expand_unaligned_store (operands[0], operands[3],
4665 INTVAL (operands[1]) / 8,
4666 INTVAL (operands[2]) / 8);
4670 ;; Block move/clear, see alpha.c for more details.
4671 ;; Argument 0 is the destination
4672 ;; Argument 1 is the source
4673 ;; Argument 2 is the length
4674 ;; Argument 3 is the alignment
4676 (define_expand "cpymemqi"
4677 [(parallel [(set (match_operand:BLK 0 "memory_operand")
4678 (match_operand:BLK 1 "memory_operand"))
4679 (use (match_operand:DI 2 "immediate_operand"))
4680 (use (match_operand:DI 3 "immediate_operand"))])]
4683 if (alpha_expand_block_move (operands))
4689 (define_expand "cpymemdi"
4690 [(parallel [(set (match_operand:BLK 0 "memory_operand")
4691 (match_operand:BLK 1 "memory_operand"))
4692 (use (match_operand:DI 2 "immediate_operand"))
4693 (use (match_operand:DI 3 "immediate_operand"))
4695 (clobber (reg:DI 25))
4696 (clobber (reg:DI 16))
4697 (clobber (reg:DI 17))
4698 (clobber (reg:DI 18))
4699 (clobber (reg:DI 19))
4700 (clobber (reg:DI 20))
4701 (clobber (reg:DI 26))
4702 (clobber (reg:DI 27))])]
4703 "TARGET_ABI_OPEN_VMS"
4704 "operands[4] = gen_rtx_SYMBOL_REF (Pmode, \"OTS$MOVE\");")
4706 (define_insn "*cpymemdi_1"
4707 [(set (match_operand:BLK 0 "memory_operand" "=m,m")
4708 (match_operand:BLK 1 "memory_operand" "m,m"))
4709 (use (match_operand:DI 2 "nonmemory_operand" "r,i"))
4710 (use (match_operand:DI 3 "immediate_operand"))
4711 (use (match_operand:DI 4 "call_operand" "i,i"))
4712 (clobber (reg:DI 25))
4713 (clobber (reg:DI 16))
4714 (clobber (reg:DI 17))
4715 (clobber (reg:DI 18))
4716 (clobber (reg:DI 19))
4717 (clobber (reg:DI 20))
4718 (clobber (reg:DI 26))
4719 (clobber (reg:DI 27))]
4720 "TARGET_ABI_OPEN_VMS"
4722 operands [5] = alpha_use_linkage (operands [4], false, true);
4723 switch (which_alternative)
4726 return "lda $16,%0\;bis $31,%2,$17\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)";
4728 return "lda $16,%0\;lda $17,%2($31)\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)";
4733 [(set_attr "type" "multi")
4734 (set_attr "length" "28")])
4736 (define_expand "setmemqi"
4737 [(parallel [(set (match_operand:BLK 0 "memory_operand")
4738 (match_operand 2 "const_int_operand"))
4739 (use (match_operand:DI 1 "immediate_operand"))
4740 (use (match_operand:DI 3 "immediate_operand"))])]
4743 /* If value to set is not zero, use the library routine. */
4744 if (operands[2] != const0_rtx)
4747 if (alpha_expand_block_clear (operands))
4753 (define_expand "setmemdi"
4754 [(parallel [(set (match_operand:BLK 0 "memory_operand")
4755 (match_operand 2 "const_int_operand"))
4756 (use (match_operand:DI 1 "immediate_operand"))
4757 (use (match_operand:DI 3 "immediate_operand"))
4759 (clobber (reg:DI 25))
4760 (clobber (reg:DI 16))
4761 (clobber (reg:DI 17))
4762 (clobber (reg:DI 26))
4763 (clobber (reg:DI 27))])]
4764 "TARGET_ABI_OPEN_VMS"
4766 /* If value to set is not zero, use the library routine. */
4767 if (operands[2] != const0_rtx)
4770 operands[4] = gen_rtx_SYMBOL_REF (Pmode, "OTS$ZERO");
4773 (define_insn "*clrmemdi_1"
4774 [(set (match_operand:BLK 0 "memory_operand" "=m,m")
4776 (use (match_operand:DI 1 "nonmemory_operand" "r,i"))
4777 (use (match_operand:DI 2 "immediate_operand"))
4778 (use (match_operand:DI 3 "call_operand" "i,i"))
4779 (clobber (reg:DI 25))
4780 (clobber (reg:DI 16))
4781 (clobber (reg:DI 17))
4782 (clobber (reg:DI 26))
4783 (clobber (reg:DI 27))]
4784 "TARGET_ABI_OPEN_VMS"
4786 operands [4] = alpha_use_linkage (operands [3], false, true);
4787 switch (which_alternative)
4790 return "lda $16,%0\;bis $31,%1,$17\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)";
4792 return "lda $16,%0\;lda $17,%1($31)\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)";
4797 [(set_attr "type" "multi")
4798 (set_attr "length" "24")])
4801 ;; Subroutine of stack space allocation. Perform a stack probe.
4802 (define_expand "stack_probe_internal"
4803 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand"))]
4806 operands[1] = gen_rtx_MEM (DImode, plus_constant (Pmode, stack_pointer_rtx,
4807 INTVAL (operands[0])));
4808 MEM_VOLATILE_P (operands[1]) = 1;
4810 operands[0] = const0_rtx;
4813 ;; This is how we allocate stack space. If we are allocating a
4814 ;; constant amount of space and we know it is less than 4096
4815 ;; bytes, we need do nothing.
4817 ;; If it is more than 4096 bytes, we need to probe the stack
4819 (define_expand "allocate_stack"
4821 (plus:DI (reg:DI 30)
4822 (match_operand:DI 1 "reg_or_cint_operand")))
4823 (set (match_operand:DI 0 "register_operand" "=r")
4827 if (CONST_INT_P (operands[1])
4828 && INTVAL (operands[1]) < 32768)
4830 if (INTVAL (operands[1]) >= 4096)
4832 /* We do this the same way as in the prologue and generate explicit
4833 probes. Then we update the stack by the constant. */
4837 emit_insn (gen_stack_probe_internal (GEN_INT (- probed)));
4838 while (probed + 8192 < INTVAL (operands[1]))
4839 emit_insn (gen_stack_probe_internal
4840 (GEN_INT (- (probed += 8192))));
4842 if (probed + 4096 < INTVAL (operands[1]))
4843 emit_insn (gen_stack_probe_internal
4844 (GEN_INT (- INTVAL(operands[1]))));
4847 operands[1] = GEN_INT (- INTVAL (operands[1]));
4848 operands[2] = virtual_stack_dynamic_rtx;
4852 rtx_code_label *out_label = 0;
4853 rtx_code_label *loop_label = gen_label_rtx ();
4854 rtx want = gen_reg_rtx (Pmode);
4855 rtx tmp = gen_reg_rtx (Pmode);
4858 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
4859 force_reg (Pmode, operands[1])));
4861 if (!CONST_INT_P (operands[1]))
4863 rtx limit = GEN_INT (4096);
4864 out_label = gen_label_rtx ();
4865 test = gen_rtx_LTU (VOIDmode, operands[1], limit);
4867 (gen_cbranchdi4 (test, operands[1], limit, out_label));
4870 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
4871 emit_label (loop_label);
4872 memref = gen_rtx_MEM (DImode, tmp);
4873 MEM_VOLATILE_P (memref) = 1;
4874 emit_move_insn (memref, const0_rtx);
4875 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
4876 test = gen_rtx_GTU (VOIDmode, tmp, want);
4877 emit_jump_insn (gen_cbranchdi4 (test, tmp, want, loop_label));
4879 memref = gen_rtx_MEM (DImode, want);
4880 MEM_VOLATILE_P (memref) = 1;
4881 emit_move_insn (memref, const0_rtx);
4884 emit_label (out_label);
4886 emit_move_insn (stack_pointer_rtx, want);
4887 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
4892 ;; This is used by alpha_expand_prolog to do the same thing as above,
4893 ;; except we cannot at that time generate new basic blocks, so we hide
4894 ;; the loop in this one insn.
4896 (define_insn "prologue_stack_probe_loop"
4897 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
4898 (match_operand:DI 1 "register_operand" "r")]
4902 operands[2] = gen_label_rtx ();
4903 (*targetm.asm_out.internal_label) (asm_out_file, "L",
4904 CODE_LABEL_NUMBER (operands[2]));
4906 return "stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2";
4908 [(set_attr "length" "16")
4909 (set_attr "type" "multi")])
4911 (define_expand "prologue"
4915 alpha_expand_prologue ();
4919 ;; These take care of emitting the ldgp insn in the prologue. This will be
4920 ;; an lda/ldah pair and we want to align them properly. So we have two
4921 ;; unspec_volatile insns, the first of which emits the ldgp assembler macro
4922 ;; and the second of which emits nothing. However, both are marked as type
4923 ;; IADD (the default) so the alignment code in alpha.c does the right thing
4926 (define_expand "prologue_ldgp"
4928 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
4930 (unspec_volatile:DI [(match_dup 0) (match_dup 2)] UNSPECV_PLDGP2))]
4933 operands[0] = pic_offset_table_rtx;
4934 operands[1] = gen_rtx_REG (Pmode, 27);
4935 operands[2] = (TARGET_EXPLICIT_RELOCS
4936 ? GEN_INT (alpha_next_sequence_number++)
4940 (define_insn "*ldgp_er_1"
4941 [(set (match_operand:DI 0 "register_operand" "=r")
4942 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
4943 (match_operand 2 "const_int_operand")]
4945 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4946 "ldah %0,0(%1)\t\t!gpdisp!%2"
4947 [(set_attr "cannot_copy" "true")])
4949 (define_insn "*ldgp_er_2"
4950 [(set (match_operand:DI 0 "register_operand" "=r")
4951 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
4952 (match_operand 2 "const_int_operand")]
4954 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4955 "lda %0,0(%1)\t\t!gpdisp!%2"
4956 [(set_attr "cannot_copy" "true")])
4958 (define_insn "*prologue_ldgp_er_2"
4959 [(set (match_operand:DI 0 "register_operand" "=r")
4960 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
4961 (match_operand 2 "const_int_operand")]
4963 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4964 "lda %0,0(%1)\t\t!gpdisp!%2\n$%~..ng:"
4965 [(set_attr "cannot_copy" "true")])
4967 (define_insn "*prologue_ldgp_1"
4968 [(set (match_operand:DI 0 "register_operand" "=r")
4969 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
4970 (match_operand 2 "const_int_operand")]
4973 "ldgp %0,0(%1)\n$%~..ng:"
4974 [(set_attr "cannot_copy" "true")])
4976 (define_insn "*prologue_ldgp_2"
4977 [(set (match_operand:DI 0 "register_operand" "=r")
4978 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
4979 (match_operand 2 "const_int_operand")]
4984 ;; The _mcount profiling hook has special calling conventions, and
4985 ;; does not clobber all the registers that a normal call would. So
4986 ;; hide the fact this is a call at all.
4988 (define_insn "prologue_mcount"
4989 [(unspec_volatile [(const_int 0)] UNSPECV_MCOUNT)]
4992 if (TARGET_EXPLICIT_RELOCS)
4993 /* Note that we cannot use a lituse_jsr reloc, since _mcount
4994 cannot be called via the PLT. */
4995 return "ldq $28,_mcount($29)\t\t!literal\;jsr $28,($28),_mcount";
4997 return "lda $28,_mcount\;jsr $28,($28),_mcount";
4999 [(set_attr "type" "multi")
5000 (set_attr "length" "8")])
5002 (define_insn "init_fp"
5003 [(set (match_operand:DI 0 "register_operand" "=r")
5004 (match_operand:DI 1 "register_operand" "r"))
5005 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))]
5009 (define_expand "epilogue"
5012 "alpha_expand_epilogue ();")
5014 (define_expand "sibcall_epilogue"
5018 alpha_expand_epilogue ();
5022 (define_expand "builtin_longjmp"
5023 [(use (match_operand:DI 0 "register_operand" "r"))]
5026 /* The elements of the buffer are, in order: */
5027 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
5028 rtx lab = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 8));
5029 rtx stack = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 16));
5030 rtx pv = gen_rtx_REG (Pmode, 27);
5032 /* This bit is the same as expand_builtin_longjmp. */
5033 emit_move_insn (hard_frame_pointer_rtx, fp);
5034 emit_move_insn (pv, lab);
5035 emit_stack_restore (SAVE_NONLOCAL, stack);
5036 emit_use (hard_frame_pointer_rtx);
5037 emit_use (stack_pointer_rtx);
5039 /* Load the label we are jumping through into $27 so that we know
5040 where to look for it when we get back to setjmp's function for
5041 restoring the gp. */
5042 emit_jump_insn (gen_builtin_longjmp_internal (pv));
5047 ;; This is effectively a copy of indirect_jump, but constrained such
5048 ;; that register renaming cannot foil our cunning plan with $27.
5049 (define_insn "builtin_longjmp_internal"
5051 (unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
5055 [(set_attr "type" "ibr")])
5057 (define_expand "builtin_setjmp_receiver"
5058 [(unspec_volatile [(label_ref (match_operand 0))] UNSPECV_SETJMPR)]
5061 (define_insn_and_split "*builtin_setjmp_receiver_1"
5062 [(unspec_volatile [(match_operand 0)] UNSPECV_SETJMPR)]
5065 if (TARGET_EXPLICIT_RELOCS)
5068 return "br $27,$LSJ%=\n$LSJ%=:\;ldgp $29,0($27)";
5070 "&& TARGET_EXPLICIT_RELOCS && reload_completed"
5072 (unspec_volatile:DI [(match_dup 2) (match_dup 3)] UNSPECV_LDGP1))
5074 (unspec:DI [(match_dup 1) (match_dup 3)] UNSPEC_LDGP2))]
5076 if (prev_nonnote_insn (curr_insn) != XEXP (operands[0], 0))
5077 emit_insn (gen_rtx_UNSPEC_VOLATILE (VOIDmode, gen_rtvec (1, operands[0]),
5078 UNSPECV_SETJMPR_ER));
5079 operands[1] = pic_offset_table_rtx;
5080 operands[2] = gen_rtx_REG (Pmode, 27);
5081 operands[3] = GEN_INT (alpha_next_sequence_number++);
5083 [(set_attr "length" "12")
5084 (set_attr "type" "multi")])
5086 (define_insn "*builtin_setjmp_receiver_er_sl_1"
5087 [(unspec_volatile [(match_operand 0)] UNSPECV_SETJMPR_ER)]
5088 "TARGET_ABI_OSF && TARGET_EXPLICIT_RELOCS"
5089 "lda $27,$LSJ%=-%l0($27)\n$LSJ%=:")
5091 ;; When flag_reorder_blocks_and_partition is in effect, compiler puts
5092 ;; exception landing pads in a cold section. To prevent inter-section offset
5093 ;; calculation, a jump to original landing pad is emitted in the place of the
5094 ;; original landing pad. Since landing pad is moved, RA-relative GP
5095 ;; calculation in the prologue of landing pad breaks. To solve this problem,
5096 ;; we use alternative GP load approach.
5098 (define_expand "exception_receiver"
5099 [(unspec_volatile [(match_dup 0)] UNSPECV_EHR)]
5102 if (flag_reorder_blocks_and_partition)
5103 operands[0] = copy_rtx (alpha_gp_save_rtx ());
5105 operands[0] = const0_rtx;
5108 (define_insn "*exception_receiver_2"
5109 [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_EHR)]
5110 "TARGET_ABI_OSF && flag_reorder_blocks_and_partition"
5112 [(set_attr "type" "ild")])
5114 (define_insn_and_split "*exception_receiver_1"
5115 [(unspec_volatile [(const_int 0)] UNSPECV_EHR)]
5118 if (TARGET_EXPLICIT_RELOCS)
5121 return "ldgp $29,0($26)";
5123 "&& TARGET_EXPLICIT_RELOCS && reload_completed"
5125 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
5127 (unspec:DI [(match_dup 0) (match_dup 2)] UNSPEC_LDGP2))]
5129 operands[0] = pic_offset_table_rtx;
5130 operands[1] = gen_rtx_REG (Pmode, 26);
5131 operands[2] = GEN_INT (alpha_next_sequence_number++);
5133 [(set_attr "length" "8")
5134 (set_attr "type" "multi")])
5136 (define_expand "nonlocal_goto_receiver"
5137 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
5138 (set (reg:DI 27) (mem:DI (reg:DI 29)))
5139 (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
5141 "TARGET_ABI_OPEN_VMS")
5143 (define_insn "arg_home"
5144 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
5159 (clobber (mem:BLK (const_int 0)))
5160 (clobber (reg:DI 24))
5161 (clobber (reg:DI 25))
5162 (clobber (reg:DI 0))]
5163 "TARGET_ABI_OPEN_VMS"
5164 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
5165 [(set_attr "length" "16")
5166 (set_attr "type" "multi")])
5170 ;; On EV4, these instructions are nops -- no load occurs.
5172 ;; On EV5, these instructions act as a normal load, and thus can trap
5173 ;; if the address is invalid. The OS may (or may not) handle this in
5174 ;; the entMM fault handler and suppress the fault. If so, then this
5175 ;; has the effect of a read prefetch instruction.
5177 ;; On EV6, these become official prefetch instructions.
5179 (define_insn "prefetch"
5180 [(prefetch (match_operand:DI 0 "address_operand" "p")
5181 (match_operand:DI 1 "const_int_operand" "n")
5182 (match_operand:DI 2 "const_int_operand" "n"))]
5183 "TARGET_FIXUP_EV5_PREFETCH || alpha_cpu == PROCESSOR_EV6"
5185 /* Interpret "no temporal locality" as this data should be evicted once
5186 it is used. The "evict next" alternatives load the data into the cache
5187 and leave the LRU eviction counter pointing to that block. */
5188 static const char * const alt[2][2] = {
5190 "ldq $31,%a0", /* read, evict next */
5191 "ldl $31,%a0", /* read, evict last */
5194 "ldt $f31,%a0", /* write, evict next */
5195 "lds $f31,%a0", /* write, evict last */
5199 bool write = INTVAL (operands[1]) != 0;
5200 bool lru = INTVAL (operands[2]) != 0;
5202 return alt[write][lru];
5204 [(set_attr "type" "ild")])
5206 ;; Close the trap shadow of preceding instructions. This is generated
5209 (define_insn "trapb"
5210 [(unspec_volatile [(const_int 0)] UNSPECV_TRAPB)]
5213 [(set_attr "type" "misc")])
5215 ;; No-op instructions used by machine-dependent reorg to preserve
5216 ;; alignment for instruction issue.
5217 ;; The Unicos/Mk assembler does not support these opcodes.
5223 [(set_attr "type" "ilog")])
5228 "cpys $f31,$f31,$f31"
5229 [(set_attr "type" "fcpys")])
5236 (define_insn "realign"
5237 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")]
5240 ".align %0 #realign")
5242 ;; Instructions to be emitted from __builtins.
5244 (define_insn "builtin_cmpbge"
5245 [(set (match_operand:DI 0 "register_operand" "=r")
5246 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rJ")
5247 (match_operand:DI 2 "reg_or_8bit_operand" "rI")]
5251 ;; The EV6 data sheets list this as ILOG. OTOH, EV6 doesn't
5252 ;; actually differentiate between ILOG and ICMP in the schedule.
5253 [(set_attr "type" "icmp")])
5255 (define_expand "extbl"
5256 [(match_operand:DI 0 "register_operand")
5257 (match_operand:DI 1 "reg_or_0_operand")
5258 (match_operand:DI 2 "reg_or_8bit_operand")]
5261 emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (8), operands[2]));
5265 (define_expand "extwl"
5266 [(match_operand:DI 0 "register_operand")
5267 (match_operand:DI 1 "reg_or_0_operand")
5268 (match_operand:DI 2 "reg_or_8bit_operand")]
5271 emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (16), operands[2]));
5275 (define_expand "extll"
5276 [(match_operand:DI 0 "register_operand")
5277 (match_operand:DI 1 "reg_or_0_operand")
5278 (match_operand:DI 2 "reg_or_8bit_operand")]
5281 emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (32), operands[2]));
5285 (define_expand "extql"
5286 [(match_operand:DI 0 "register_operand")
5287 (match_operand:DI 1 "reg_or_0_operand")
5288 (match_operand:DI 2 "reg_or_8bit_operand")]
5291 emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (64), operands[2]));
5295 (define_expand "builtin_insbl"
5296 [(match_operand:DI 0 "register_operand")
5297 (match_operand:DI 1 "register_operand")
5298 (match_operand:DI 2 "reg_or_8bit_operand")]
5301 operands[1] = gen_lowpart (QImode, operands[1]);
5302 emit_insn (gen_insbl (operands[0], operands[1], operands[2]));
5306 (define_expand "builtin_inswl"
5307 [(match_operand:DI 0 "register_operand")
5308 (match_operand:DI 1 "register_operand")
5309 (match_operand:DI 2 "reg_or_8bit_operand")]
5312 operands[1] = gen_lowpart (HImode, operands[1]);
5313 emit_insn (gen_inswl (operands[0], operands[1], operands[2]));
5317 (define_expand "builtin_insll"
5318 [(match_operand:DI 0 "register_operand")
5319 (match_operand:DI 1 "register_operand")
5320 (match_operand:DI 2 "reg_or_8bit_operand")]
5323 operands[1] = gen_lowpart (SImode, operands[1]);
5324 emit_insn (gen_insll (operands[0], operands[1], operands[2]));
5328 (define_expand "inswh"
5329 [(match_operand:DI 0 "register_operand")
5330 (match_operand:DI 1 "register_operand")
5331 (match_operand:DI 2 "reg_or_8bit_operand")]
5334 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (16), operands[2]));
5338 (define_expand "inslh"
5339 [(match_operand:DI 0 "register_operand")
5340 (match_operand:DI 1 "register_operand")
5341 (match_operand:DI 2 "reg_or_8bit_operand")]
5344 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (32), operands[2]));
5348 (define_expand "insqh"
5349 [(match_operand:DI 0 "register_operand")
5350 (match_operand:DI 1 "register_operand")
5351 (match_operand:DI 2 "reg_or_8bit_operand")]
5354 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (64), operands[2]));
5358 (define_expand "mskbl"
5359 [(match_operand:DI 0 "register_operand")
5360 (match_operand:DI 1 "reg_or_0_operand")
5361 (match_operand:DI 2 "reg_or_8bit_operand")]
5364 rtx mask = GEN_INT (0xff);
5365 emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2]));
5369 (define_expand "mskwl"
5370 [(match_operand:DI 0 "register_operand")
5371 (match_operand:DI 1 "reg_or_0_operand")
5372 (match_operand:DI 2 "reg_or_8bit_operand")]
5375 rtx mask = GEN_INT (0xffff);
5376 emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2]));
5380 (define_expand "mskll"
5381 [(match_operand:DI 0 "register_operand")
5382 (match_operand:DI 1 "reg_or_0_operand")
5383 (match_operand:DI 2 "reg_or_8bit_operand")]
5386 rtx mask = gen_int_mode (0xffffffff, DImode);
5387 emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2]));
5391 (define_expand "mskql"
5392 [(match_operand:DI 0 "register_operand")
5393 (match_operand:DI 1 "reg_or_0_operand")
5394 (match_operand:DI 2 "reg_or_8bit_operand")]
5397 rtx mask = constm1_rtx;
5398 emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2]));
5402 (define_expand "mskwh"
5403 [(match_operand:DI 0 "register_operand")
5404 (match_operand:DI 1 "register_operand")
5405 (match_operand:DI 2 "reg_or_8bit_operand")]
5408 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (16), operands[2]));
5412 (define_expand "msklh"
5413 [(match_operand:DI 0 "register_operand")
5414 (match_operand:DI 1 "register_operand")
5415 (match_operand:DI 2 "reg_or_8bit_operand")]
5418 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (32), operands[2]));
5422 (define_expand "mskqh"
5423 [(match_operand:DI 0 "register_operand")
5424 (match_operand:DI 1 "register_operand")
5425 (match_operand:DI 2 "reg_or_8bit_operand")]
5428 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (64), operands[2]));
5432 (define_expand "builtin_zap"
5433 [(set (match_operand:DI 0 "register_operand")
5435 [(match_operand:DI 2 "reg_or_cint_operand")]
5437 (match_operand:DI 1 "reg_or_cint_operand")))]
5440 if (CONST_INT_P (operands[2]))
5442 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
5444 if (mask == const0_rtx)
5446 emit_move_insn (operands[0], const0_rtx);
5449 if (mask == constm1_rtx)
5451 emit_move_insn (operands[0], operands[1]);
5455 operands[1] = force_reg (DImode, operands[1]);
5456 emit_insn (gen_anddi3 (operands[0], operands[1], mask));
5460 operands[1] = force_reg (DImode, operands[1]);
5461 operands[2] = gen_lowpart (QImode, operands[2]);
5464 (define_insn "*builtin_zap_1"
5465 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
5467 [(match_operand:QI 2 "reg_or_cint_operand" "n,n,r,r")]
5469 (match_operand:DI 1 "reg_or_cint_operand" "n,r,J,r")))]
5476 [(set_attr "type" "shift,shift,ilog,shift")])
5479 [(set (match_operand:DI 0 "register_operand")
5481 [(match_operand:QI 2 "const_int_operand")]
5483 (match_operand:DI 1 "const_int_operand")))]
5487 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
5489 operands[1] = gen_int_mode (INTVAL (operands[1]) & INTVAL (mask), DImode);
5490 emit_move_insn (operands[0], operands[1]);
5495 [(set (match_operand:DI 0 "register_operand")
5497 [(match_operand:QI 2 "const_int_operand")]
5499 (match_operand:DI 1 "register_operand")))]
5502 (and:DI (match_dup 1) (match_dup 2)))]
5504 operands[2] = alpha_expand_zap_mask (INTVAL (operands[2]));
5505 if (operands[2] == const0_rtx)
5507 emit_move_insn (operands[0], const0_rtx);
5510 if (operands[2] == constm1_rtx)
5512 emit_move_insn (operands[0], operands[1]);
5517 (define_expand "builtin_zapnot"
5518 [(set (match_operand:DI 0 "register_operand")
5520 [(not:QI (match_operand:DI 2 "reg_or_cint_operand"))]
5522 (match_operand:DI 1 "reg_or_cint_operand")))]
5525 if (CONST_INT_P (operands[2]))
5527 rtx mask = alpha_expand_zap_mask (~ INTVAL (operands[2]));
5529 if (mask == const0_rtx)
5531 emit_move_insn (operands[0], const0_rtx);
5534 if (mask == constm1_rtx)
5536 emit_move_insn (operands[0], operands[1]);
5540 operands[1] = force_reg (DImode, operands[1]);
5541 emit_insn (gen_anddi3 (operands[0], operands[1], mask));
5545 operands[1] = force_reg (DImode, operands[1]);
5546 operands[2] = gen_lowpart (QImode, operands[2]);
5549 (define_insn "*builtin_zapnot_1"
5550 [(set (match_operand:DI 0 "register_operand" "=r")
5552 [(not:QI (match_operand:QI 2 "register_operand" "r"))]
5554 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
5557 [(set_attr "type" "shift")])
5559 (define_insn "builtin_amask"
5560 [(set (match_operand:DI 0 "register_operand" "=r")
5561 (unspec:DI [(match_operand:DI 1 "reg_or_8bit_operand" "rI")]
5565 [(set_attr "type" "ilog")])
5567 (define_insn "builtin_implver"
5568 [(set (match_operand:DI 0 "register_operand" "=r")
5569 (unspec:DI [(const_int 0)] UNSPEC_IMPLVER))]
5572 [(set_attr "type" "ilog")])
5574 (define_insn "builtin_rpcc"
5575 [(set (match_operand:DI 0 "register_operand" "=r")
5576 (unspec_volatile:DI [(const_int 0)] UNSPECV_RPCC))]
5579 [(set_attr "type" "ilog")])
5581 (define_expand "builtin_minub8"
5582 [(match_operand:DI 0 "register_operand")
5583 (match_operand:DI 1 "reg_or_0_operand")
5584 (match_operand:DI 2 "reg_or_0_operand")]
5587 alpha_expand_builtin_vector_binop (gen_uminv8qi3, V8QImode, operands[0],
5588 operands[1], operands[2]);
5592 (define_expand "builtin_minsb8"
5593 [(match_operand:DI 0 "register_operand")
5594 (match_operand:DI 1 "reg_or_0_operand")
5595 (match_operand:DI 2 "reg_or_0_operand")]
5598 alpha_expand_builtin_vector_binop (gen_sminv8qi3, V8QImode, operands[0],
5599 operands[1], operands[2]);
5603 (define_expand "builtin_minuw4"
5604 [(match_operand:DI 0 "register_operand")
5605 (match_operand:DI 1 "reg_or_0_operand")
5606 (match_operand:DI 2 "reg_or_0_operand")]
5609 alpha_expand_builtin_vector_binop (gen_uminv4hi3, V4HImode, operands[0],
5610 operands[1], operands[2]);
5614 (define_expand "builtin_minsw4"
5615 [(match_operand:DI 0 "register_operand")
5616 (match_operand:DI 1 "reg_or_0_operand")
5617 (match_operand:DI 2 "reg_or_0_operand")]
5620 alpha_expand_builtin_vector_binop (gen_sminv4hi3, V4HImode, operands[0],
5621 operands[1], operands[2]);
5625 (define_expand "builtin_maxub8"
5626 [(match_operand:DI 0 "register_operand")
5627 (match_operand:DI 1 "reg_or_0_operand")
5628 (match_operand:DI 2 "reg_or_0_operand")]
5631 alpha_expand_builtin_vector_binop (gen_umaxv8qi3, V8QImode, operands[0],
5632 operands[1], operands[2]);
5636 (define_expand "builtin_maxsb8"
5637 [(match_operand:DI 0 "register_operand")
5638 (match_operand:DI 1 "reg_or_0_operand")
5639 (match_operand:DI 2 "reg_or_0_operand")]
5642 alpha_expand_builtin_vector_binop (gen_smaxv8qi3, V8QImode, operands[0],
5643 operands[1], operands[2]);
5647 (define_expand "builtin_maxuw4"
5648 [(match_operand:DI 0 "register_operand")
5649 (match_operand:DI 1 "reg_or_0_operand")
5650 (match_operand:DI 2 "reg_or_0_operand")]
5653 alpha_expand_builtin_vector_binop (gen_umaxv4hi3, V4HImode, operands[0],
5654 operands[1], operands[2]);
5658 (define_expand "builtin_maxsw4"
5659 [(match_operand:DI 0 "register_operand")
5660 (match_operand:DI 1 "reg_or_0_operand")
5661 (match_operand:DI 2 "reg_or_0_operand")]
5664 alpha_expand_builtin_vector_binop (gen_smaxv4hi3, V4HImode, operands[0],
5665 operands[1], operands[2]);
5669 (define_insn "builtin_perr"
5670 [(set (match_operand:DI 0 "register_operand" "=r")
5671 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "%rJ")
5672 (match_operand:DI 2 "reg_or_8bit_operand" "rJ")]
5676 [(set_attr "type" "mvi")])
5678 (define_expand "builtin_pklb"
5679 [(set (match_operand:DI 0 "register_operand")
5682 (truncate:V2QI (match_operand:DI 1 "register_operand"))
5687 operands[0] = gen_lowpart (V8QImode, operands[0]);
5688 operands[1] = gen_lowpart (V2SImode, operands[1]);
5689 operands[2] = CONST0_RTX (V2QImode);
5690 operands[3] = CONST0_RTX (V4QImode);
5693 (define_insn "*pklb"
5694 [(set (match_operand:V8QI 0 "register_operand" "=r")
5697 (truncate:V2QI (match_operand:V2SI 1 "register_operand" "r"))
5698 (match_operand:V2QI 2 "const0_operand"))
5699 (match_operand:V4QI 3 "const0_operand")))]
5702 [(set_attr "type" "mvi")])
5704 (define_expand "builtin_pkwb"
5705 [(set (match_operand:DI 0 "register_operand")
5707 (truncate:V4QI (match_operand:DI 1 "register_operand"))
5711 operands[0] = gen_lowpart (V8QImode, operands[0]);
5712 operands[1] = gen_lowpart (V4HImode, operands[1]);
5713 operands[2] = CONST0_RTX (V4QImode);
5716 (define_insn "*pkwb"
5717 [(set (match_operand:V8QI 0 "register_operand" "=r")
5719 (truncate:V4QI (match_operand:V4HI 1 "register_operand" "r"))
5720 (match_operand:V4QI 2 "const0_operand")))]
5723 [(set_attr "type" "mvi")])
5725 (define_expand "builtin_unpkbl"
5726 [(set (match_operand:DI 0 "register_operand")
5728 (vec_select:V2QI (match_operand:DI 1 "register_operand")
5729 (parallel [(const_int 0) (const_int 1)]))))]
5732 operands[0] = gen_lowpart (V2SImode, operands[0]);
5733 operands[1] = gen_lowpart (V8QImode, operands[1]);
5736 (define_insn "*unpkbl"
5737 [(set (match_operand:V2SI 0 "register_operand" "=r")
5739 (vec_select:V2QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
5740 (parallel [(const_int 0) (const_int 1)]))))]
5743 [(set_attr "type" "mvi")])
5745 (define_expand "builtin_unpkbw"
5746 [(set (match_operand:DI 0 "register_operand")
5748 (vec_select:V4QI (match_operand:DI 1 "register_operand")
5749 (parallel [(const_int 0)
5755 operands[0] = gen_lowpart (V4HImode, operands[0]);
5756 operands[1] = gen_lowpart (V8QImode, operands[1]);
5759 (define_insn "*unpkbw"
5760 [(set (match_operand:V4HI 0 "register_operand" "=r")
5762 (vec_select:V4QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
5763 (parallel [(const_int 0)
5769 [(set_attr "type" "mvi")])
5773 ;; The call patterns are at the end of the file because their
5774 ;; wildcard operand0 interferes with nice recognition.
5776 (define_insn "*call_value_osf_1_er_noreturn"
5777 [(set (match_operand 0)
5778 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
5781 (clobber (reg:DI 26))]
5782 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
5783 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
5786 bsr $26,%1\t\t!samegp
5787 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),%1\t\t!lituse_jsr!%#"
5788 [(set_attr "type" "jsr")
5789 (set_attr "length" "*,*,8")])
5791 (define_insn "*call_value_osf_1_er"
5792 [(set (match_operand 0)
5793 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
5796 (clobber (reg:DI 26))]
5797 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
5799 jsr $26,(%1),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
5800 bsr $26,%1\t\t!samegp
5801 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
5802 [(set_attr "type" "jsr")
5803 (set_attr "length" "12,*,16")])
5805 ;; We must use peep2 instead of a split because we need accurate life
5806 ;; information for $gp. Consider the case of { bar(); while (1); }.
5808 [(parallel [(set (match_operand 0)
5809 (call (mem:DI (match_operand:DI 1 "call_operand"))
5812 (clobber (reg:DI 26))])]
5813 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
5814 && ! samegp_function_operand (operands[1], Pmode)
5815 && (peep2_regno_dead_p (1, 29)
5816 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
5817 [(parallel [(set (match_dup 0)
5818 (call (mem:DI (match_dup 3))
5823 (clobber (reg:DI 26))])]
5825 if (CONSTANT_P (operands[1]))
5827 operands[3] = gen_rtx_REG (Pmode, 27);
5828 operands[4] = GEN_INT (alpha_next_sequence_number++);
5829 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
5830 operands[1], operands[4]));
5834 operands[3] = operands[1];
5835 operands[1] = const0_rtx;
5836 operands[4] = const0_rtx;
5841 [(parallel [(set (match_operand 0)
5842 (call (mem:DI (match_operand:DI 1 "call_operand"))
5845 (clobber (reg:DI 26))])]
5846 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
5847 && ! samegp_function_operand (operands[1], Pmode)
5848 && ! (peep2_regno_dead_p (1, 29)
5849 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
5850 [(parallel [(set (match_dup 0)
5851 (call (mem:DI (match_dup 3))
5854 (unspec:DI [(match_dup 6) (match_dup 4)] UNSPEC_LDGP1))
5857 (clobber (reg:DI 26))])
5859 (unspec:DI [(match_dup 6) (match_dup 4)] UNSPEC_LDGP2))]
5861 if (CONSTANT_P (operands[1]))
5863 operands[3] = gen_rtx_REG (Pmode, 27);
5864 operands[5] = GEN_INT (alpha_next_sequence_number++);
5865 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
5866 operands[1], operands[5]));
5870 operands[3] = operands[1];
5871 operands[1] = const0_rtx;
5872 operands[5] = const0_rtx;
5874 operands[4] = GEN_INT (alpha_next_sequence_number++);
5875 operands[6] = pic_offset_table_rtx;
5878 (define_insn "*call_value_osf_2_er_nogp"
5879 [(set (match_operand 0)
5880 (call (mem:DI (match_operand:DI 1 "register_operand" "c"))
5883 (use (match_operand 3))
5884 (use (match_operand 4))
5885 (clobber (reg:DI 26))]
5886 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
5887 "jsr $26,(%1),%3%J4"
5888 [(set_attr "type" "jsr")])
5890 (define_insn "*call_value_osf_2_er"
5891 [(set (match_operand 0)
5892 (call (mem:DI (match_operand:DI 1 "register_operand" "c"))
5895 (unspec:DI [(reg:DI 29) (match_operand 5 "const_int_operand")]
5897 (use (match_operand 3))
5898 (use (match_operand 4))
5899 (clobber (reg:DI 26))]
5900 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
5901 "jsr $26,(%1),%3%J4\;ldah $29,0($26)\t\t!gpdisp!%5"
5902 [(set_attr "type" "jsr")
5903 (set_attr "cannot_copy" "true")
5904 (set_attr "length" "8")])
5906 (define_insn "*call_value_osf_1_noreturn"
5907 [(set (match_operand 0)
5908 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
5911 (clobber (reg:DI 26))]
5912 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
5913 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
5918 [(set_attr "type" "jsr")
5919 (set_attr "length" "*,*,8")])
5921 (define_int_iterator TLS_CALL
5923 UNSPEC_TLSLDM_CALL])
5925 (define_int_attr tls
5926 [(UNSPEC_TLSGD_CALL "tlsgd")
5927 (UNSPEC_TLSLDM_CALL "tlsldm")])
5929 (define_insn "call_value_osf_<tls>"
5930 [(set (match_operand 0)
5931 (call (mem:DI (match_operand:DI 1 "symbolic_operand"))
5933 (unspec [(match_operand:DI 2 "const_int_operand")] TLS_CALL)
5935 (clobber (reg:DI 26))]
5937 "ldq $27,%1($29)\t\t!literal!%2\;jsr $26,($27),%1\t\t!lituse_<tls>!%2\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
5938 [(set_attr "type" "jsr")
5939 (set_attr "length" "16")])
5941 ;; We must use peep2 instead of a split because we need accurate life
5942 ;; information for $gp.
5945 [(set (match_operand 0)
5946 (call (mem:DI (match_operand:DI 1 "symbolic_operand"))
5948 (unspec [(match_operand:DI 2 "const_int_operand")] TLS_CALL)
5950 (clobber (reg:DI 26))])]
5951 "HAVE_AS_TLS && reload_completed
5952 && peep2_regno_dead_p (1, 29)"
5954 (unspec:DI [(match_dup 5)
5956 (match_dup 2)] UNSPEC_LITERAL))
5957 (parallel [(set (match_dup 0)
5958 (call (mem:DI (match_dup 3))
5962 (use (unspec [(match_dup 2)] TLS_CALL))
5963 (clobber (reg:DI 26))])
5965 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))]
5967 operands[3] = gen_rtx_REG (Pmode, 27);
5968 operands[4] = GEN_INT (alpha_next_sequence_number++);
5969 operands[5] = pic_offset_table_rtx;
5974 [(set (match_operand 0)
5975 (call (mem:DI (match_operand:DI 1 "symbolic_operand"))
5977 (unspec [(match_operand:DI 2 "const_int_operand")] TLS_CALL)
5979 (clobber (reg:DI 26))])]
5980 "HAVE_AS_TLS && reload_completed
5981 && !peep2_regno_dead_p (1, 29)"
5983 (unspec:DI [(match_dup 5)
5985 (match_dup 2)] UNSPEC_LITERAL))
5986 (parallel [(set (match_dup 0)
5987 (call (mem:DI (match_dup 3))
5990 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP1))
5992 (use (unspec [(match_dup 2)] TLS_CALL))
5993 (clobber (reg:DI 26))])
5995 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))]
5997 operands[3] = gen_rtx_REG (Pmode, 27);
5998 operands[4] = GEN_INT (alpha_next_sequence_number++);
5999 operands[5] = pic_offset_table_rtx;
6002 (define_insn "*call_value_osf_1"
6003 [(set (match_operand 0)
6004 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
6007 (clobber (reg:DI 26))]
6008 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6010 jsr $26,($27),0\;ldgp $29,0($26)
6012 jsr $26,%1\;ldgp $29,0($26)"
6013 [(set_attr "type" "jsr")
6014 (set_attr "length" "12,*,16")])
6016 (define_insn "*sibcall_value_osf_1_er"
6017 [(set (match_operand 0)
6018 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
6020 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
6021 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6023 br $31,%1\t\t!samegp
6024 ldq $27,%1($29)\t\t!literal!%#\;jmp $31,($27),%1\t\t!lituse_jsr!%#"
6025 [(set_attr "type" "jsr")
6026 (set_attr "length" "*,8")])
6028 (define_insn "*sibcall_value_osf_1"
6029 [(set (match_operand 0)
6030 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
6032 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
6033 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6036 lda $27,%1\;jmp $31,($27),%1"
6037 [(set_attr "type" "jsr")
6038 (set_attr "length" "*,8")])
6040 ; GAS relies on the order and position of instructions output below in order
6041 ; to generate relocs for VMS link to potentially optimize the call.
6042 ; Please do not molest.
6043 (define_insn "*call_value_vms_1"
6044 [(set (match_operand 0)
6045 (call (mem:DI (match_operand:DI 1 "call_operand" "r,s"))
6047 (use (match_operand:DI 3 "nonmemory_operand" "r,n"))
6050 (clobber (reg:DI 27))]
6051 "TARGET_ABI_OPEN_VMS"
6053 switch (which_alternative)
6056 return "mov %3,$27\;jsr $26,0\;ldq $27,0($29)";
6058 operands [3] = alpha_use_linkage (operands [1], true, false);
6059 operands [4] = alpha_use_linkage (operands [1], false, false);
6060 return "ldq $26,%4\;ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)";
6065 [(set_attr "type" "jsr")
6066 (set_attr "length" "12,16")])