1 /* Subroutines used for code generation on the Synopsys DesignWare ARC cpu.
2 Copyright (C) 1994-2018 Free Software Foundation, Inc.
4 Sources derived from work done by Sankhya Technologies (www.sankhya.com) on
5 behalf of Synopsys Inc.
7 Position Independent Code support added,Code cleaned up,
8 Comments and Support For ARC700 instructions added by
9 Saurabh Verma (saurabh.verma@codito.com)
10 Ramana Radhakrishnan(ramana.radhakrishnan@codito.com)
12 Fixing ABI inconsistencies, optimizations for ARC600 / ARC700 pipelines,
13 profiling support added by Joern Rennecke <joern.rennecke@embecosm.com>
15 This file is part of GCC.
17 GCC is free software; you can redistribute it and/or modify
18 it under the terms of the GNU General Public License as published by
19 the Free Software Foundation; either version 3, or (at your option)
22 GCC is distributed in the hope that it will be useful,
23 but WITHOUT ANY WARRANTY; without even the implied warranty of
24 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 GNU General Public License for more details.
27 You should have received a copy of the GNU General Public License
28 along with GCC; see the file COPYING3. If not see
29 <http://www.gnu.org/licenses/>. */
31 #define IN_TARGET_CODE 1
35 #include "coretypes.h"
44 #include "stringpool.h"
50 #include "diagnostic.h"
51 #include "fold-const.h"
53 #include "stor-layout.h"
56 #include "insn-attr.h"
60 #include "langhooks.h"
61 #include "tm-constrs.h"
62 #include "reload.h" /* For operands_match_p */
64 #include "tree-pass.h"
70 #include "hw-doloop.h"
72 /* Which cpu we're compiling for (ARC600, ARC601, ARC700). */
73 static char arc_cpu_name
[10] = "";
74 static const char *arc_cpu_string
= arc_cpu_name
;
76 typedef struct GTY (()) _arc_jli_section
79 struct _arc_jli_section
*next
;
82 static arc_jli_section
*arc_jli_sections
= NULL
;
84 /* Track which regs are set fixed/call saved/call used from commnad line. */
85 HARD_REG_SET overrideregs
;
87 /* Maximum size of a loop. */
88 #define ARC_MAX_LOOP_LENGTH 4095
90 /* ??? Loads can handle any constant, stores can only handle small ones. */
91 /* OTOH, LIMMs cost extra, so their usefulness is limited. */
92 #define RTX_OK_FOR_OFFSET_P(MODE, X) \
93 (GET_CODE (X) == CONST_INT \
94 && SMALL_INT_RANGE (INTVAL (X), (GET_MODE_SIZE (MODE) - 1) & -4, \
95 (INTVAL (X) & (GET_MODE_SIZE (MODE) - 1) & 3 \
97 : -(-GET_MODE_SIZE (MODE) | -4) >> 1)))
99 /* Array of valid operand punctuation characters. */
100 char arc_punct_chars
[256];
102 /* State used by arc_ccfsm_advance to implement conditional execution. */
103 struct GTY (()) arc_ccfsm
108 rtx_insn
*target_insn
;
112 /* Status of the IRQ_CTRL_AUX register. */
113 typedef struct irq_ctrl_saved_t
115 /* Last register number used by IRQ_CTRL_SAVED aux_reg. */
116 short irq_save_last_reg
;
117 /* True if BLINK is automatically saved. */
119 /* True if LPCOUNT is automatically saved. */
120 bool irq_save_lpcount
;
122 static irq_ctrl_saved_t irq_ctrl_saved
;
124 #define ARC_AUTOBLINK_IRQ_P(FNTYPE) \
125 ((ARC_INTERRUPT_P (FNTYPE) \
126 && irq_ctrl_saved.irq_save_blink) \
127 || (ARC_FAST_INTERRUPT_P (FNTYPE) \
128 && rgf_banked_register_count > 8))
130 #define ARC_AUTOFP_IRQ_P(FNTYPE) \
131 ((ARC_INTERRUPT_P (FNTYPE) \
132 && (irq_ctrl_saved.irq_save_last_reg > 26)) \
133 || (ARC_FAST_INTERRUPT_P (FNTYPE) \
134 && rgf_banked_register_count > 8))
136 #define ARC_AUTO_IRQ_P(FNTYPE) \
137 (ARC_INTERRUPT_P (FNTYPE) && !ARC_FAST_INTERRUPT_P (FNTYPE) \
138 && (irq_ctrl_saved.irq_save_blink \
139 || (irq_ctrl_saved.irq_save_last_reg >= 0)))
141 /* Number of registers in second bank for FIRQ support. */
142 static int rgf_banked_register_count
;
144 #define arc_ccfsm_current cfun->machine->ccfsm_current
146 #define ARC_CCFSM_BRANCH_DELETED_P(STATE) \
147 ((STATE)->state == 1 || (STATE)->state == 2)
149 /* Indicate we're conditionalizing insns now. */
150 #define ARC_CCFSM_RECORD_BRANCH_DELETED(STATE) \
151 ((STATE)->state += 2)
153 #define ARC_CCFSM_COND_EXEC_P(STATE) \
154 ((STATE)->state == 3 || (STATE)->state == 4 || (STATE)->state == 5 \
155 || current_insn_predicate)
157 /* Check if INSN has a 16 bit opcode considering struct arc_ccfsm *STATE. */
158 #define CCFSM_ISCOMPACT(INSN,STATE) \
159 (ARC_CCFSM_COND_EXEC_P (STATE) \
160 ? (get_attr_iscompact (INSN) == ISCOMPACT_TRUE \
161 || get_attr_iscompact (INSN) == ISCOMPACT_TRUE_LIMM) \
162 : get_attr_iscompact (INSN) != ISCOMPACT_FALSE)
164 /* Likewise, but also consider that INSN might be in a delay slot of JUMP. */
165 #define CCFSM_DBR_ISCOMPACT(INSN,JUMP,STATE) \
166 ((ARC_CCFSM_COND_EXEC_P (STATE) \
168 && INSN_ANNULLED_BRANCH_P (JUMP) \
169 && (TARGET_AT_DBR_CONDEXEC || INSN_FROM_TARGET_P (INSN)))) \
170 ? (get_attr_iscompact (INSN) == ISCOMPACT_TRUE \
171 || get_attr_iscompact (INSN) == ISCOMPACT_TRUE_LIMM) \
172 : get_attr_iscompact (INSN) != ISCOMPACT_FALSE)
174 /* The maximum number of insns skipped which will be conditionalised if
176 /* When optimizing for speed:
177 Let p be the probability that the potentially skipped insns need to
178 be executed, pn the cost of a correctly predicted non-taken branch,
179 mt the cost of a mis/non-predicted taken branch,
180 mn mispredicted non-taken, pt correctly predicted taken ;
181 costs expressed in numbers of instructions like the ones considered
183 Unfortunately we don't have a measure of predictability - this
184 is linked to probability only in that in the no-eviction-scenario
185 there is a lower bound 1 - 2 * min (p, 1-p), and a somewhat larger
186 value that can be assumed *if* the distribution is perfectly random.
187 A predictability of 1 is perfectly plausible not matter what p is,
188 because the decision could be dependent on an invocation parameter
190 For large p, we want MAX_INSNS_SKIPPED == pn/(1-p) + mt - pn
191 For small p, we want MAX_INSNS_SKIPPED == pt
193 When optimizing for size:
194 We want to skip insn unless we could use 16 opcodes for the
195 non-conditionalized insn to balance the branch length or more.
196 Performance can be tie-breaker. */
197 /* If the potentially-skipped insns are likely to be executed, we'll
198 generally save one non-taken branch
200 this to be no less than the 1/p */
201 #define MAX_INSNS_SKIPPED 3
203 /* A nop is needed between a 4 byte insn that sets the condition codes and
204 a branch that uses them (the same isn't true for an 8 byte insn that sets
205 the condition codes). Set by arc_ccfsm_advance. Used by
206 arc_print_operand. */
208 static int get_arc_condition_code (rtx
);
210 static tree
arc_handle_interrupt_attribute (tree
*, tree
, tree
, int, bool *);
211 static tree
arc_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
212 static tree
arc_handle_jli_attribute (tree
*, tree
, tree
, int, bool *);
213 static tree
arc_handle_secure_attribute (tree
*, tree
, tree
, int, bool *);
214 static tree
arc_handle_uncached_attribute (tree
*, tree
, tree
, int, bool *);
215 static tree
arc_handle_aux_attribute (tree
*, tree
, tree
, int, bool *);
217 /* Initialized arc_attribute_table to NULL since arc doesnot have any
218 machine specific supported attributes. */
219 const struct attribute_spec arc_attribute_table
[] =
221 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
222 affects_type_identity, handler, exclude } */
223 { "interrupt", 1, 1, true, false, false, true,
224 arc_handle_interrupt_attribute
, NULL
},
225 /* Function calls made to this symbol must be done indirectly, because
226 it may lie outside of the 21/25 bit addressing range of a normal function
228 { "long_call", 0, 0, false, true, true, false, NULL
, NULL
},
229 /* Whereas these functions are always known to reside within the 25 bit
230 addressing range of unconditionalized bl. */
231 { "medium_call", 0, 0, false, true, true, false, NULL
, NULL
},
232 /* And these functions are always known to reside within the 21 bit
233 addressing range of blcc. */
234 { "short_call", 0, 0, false, true, true, false, NULL
, NULL
},
235 /* Function which are not having the prologue and epilogue generated
237 { "naked", 0, 0, true, false, false, false, arc_handle_fndecl_attribute
,
239 /* Functions calls made using jli instruction. The pointer in JLI
240 table is found latter. */
241 { "jli_always", 0, 0, false, true, true, false, NULL
, NULL
},
242 /* Functions calls made using jli instruction. The pointer in JLI
243 table is given as input parameter. */
244 { "jli_fixed", 1, 1, false, true, true, false, arc_handle_jli_attribute
,
246 /* Call a function using secure-mode. */
247 { "secure_call", 1, 1, false, true, true, false, arc_handle_secure_attribute
,
249 /* Bypass caches using .di flag. */
250 { "uncached", 0, 0, false, true, false, false, arc_handle_uncached_attribute
,
252 { "aux", 0, 1, true, false, false, false, arc_handle_aux_attribute
, NULL
},
253 { NULL
, 0, 0, false, false, false, false, NULL
, NULL
}
255 static int arc_comp_type_attributes (const_tree
, const_tree
);
256 static void arc_file_start (void);
257 static void arc_internal_label (FILE *, const char *, unsigned long);
258 static void arc_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
,
260 static int arc_address_cost (rtx
, machine_mode
, addr_space_t
, bool);
261 static void arc_encode_section_info (tree decl
, rtx rtl
, int first
);
263 static void arc_init_builtins (void);
264 static rtx
arc_expand_builtin (tree
, rtx
, rtx
, machine_mode
, int);
266 static int branch_dest (rtx
);
268 static void arc_output_pic_addr_const (FILE *, rtx
, int);
269 static bool arc_function_ok_for_sibcall (tree
, tree
);
270 static rtx
arc_function_value (const_tree
, const_tree
, bool);
271 const char * output_shift (rtx
*);
272 static void arc_reorg (void);
273 static bool arc_in_small_data_p (const_tree
);
275 static void arc_init_reg_tables (void);
276 static bool arc_return_in_memory (const_tree
, const_tree
);
277 static bool arc_vector_mode_supported_p (machine_mode
);
279 static bool arc_can_use_doloop_p (const widest_int
&, const widest_int
&,
281 static const char *arc_invalid_within_doloop (const rtx_insn
*);
283 static void output_short_suffix (FILE *file
);
285 static bool arc_frame_pointer_required (void);
287 static bool arc_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT
,
289 enum by_pieces_operation op
,
292 /* Globally visible information about currently selected cpu. */
293 const arc_cpu_t
*arc_selected_cpu
;
295 /* Given a symbol RTX (const (symb <+ const_int>), returns its
299 get_symbol_alignment (rtx x
)
301 tree decl
= NULL_TREE
;
304 switch (GET_CODE (x
))
307 decl
= SYMBOL_REF_DECL (x
);
310 return get_symbol_alignment (XEXP (x
, 0));
312 gcc_assert (CONST_INT_P (XEXP (x
, 1)));
313 return get_symbol_alignment (XEXP (x
, 0));
319 align
= DECL_ALIGN (decl
);
320 align
= align
/ BITS_PER_UNIT
;
324 /* Return true if x is ok to be used as a small data address. */
327 legitimate_small_data_address_p (rtx x
)
329 switch (GET_CODE (x
))
332 return legitimate_small_data_address_p (XEXP (x
, 0));
334 return SYMBOL_REF_SMALL_P (x
);
337 bool p0
= (GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
338 && SYMBOL_REF_SMALL_P (XEXP (x
, 0));
339 bool p1
= CONST_INT_P (XEXP (x
, 1))
340 && (INTVAL (XEXP (x
, 1)) <= g_switch_value
);
348 /* TRUE if op is an scaled address. */
350 legitimate_scaled_address_p (machine_mode mode
, rtx op
, bool strict
)
352 if (GET_CODE (op
) != PLUS
)
355 if (GET_CODE (XEXP (op
, 0)) != MULT
)
358 /* Check multiplication operands. */
359 if (!RTX_OK_FOR_INDEX_P (XEXP (XEXP (op
, 0), 0), strict
))
362 if (!CONST_INT_P (XEXP (XEXP (op
, 0), 1)))
365 switch (GET_MODE_SIZE (mode
))
368 if (INTVAL (XEXP (XEXP (op
, 0), 1)) != 2)
376 if (INTVAL (XEXP (XEXP (op
, 0), 1)) != 4)
383 /* Check the base. */
384 if (RTX_OK_FOR_BASE_P (XEXP (op
, 1), (strict
)))
389 if (CONST_INT_P (XEXP (op
, 1)))
394 /* Scalled addresses for sdata is done other places. */
395 if (legitimate_small_data_address_p (op
))
398 if (CONSTANT_P (XEXP (op
, 1)))
404 /* Check for constructions like REG + OFFS, where OFFS can be a
405 register, an immediate or an long immediate. */
408 legitimate_offset_address_p (machine_mode mode
, rtx x
, bool index
, bool strict
)
410 if (GET_CODE (x
) != PLUS
)
413 if (!RTX_OK_FOR_BASE_P (XEXP (x
, 0), (strict
)))
416 /* Check for: [Rx + small offset] or [Rx + Ry]. */
417 if (((index
&& RTX_OK_FOR_INDEX_P (XEXP (x
, 1), (strict
))
418 && GET_MODE_SIZE ((mode
)) <= 4)
419 || RTX_OK_FOR_OFFSET_P (mode
, XEXP (x
, 1))))
422 /* Check for [Rx + symbol]. */
424 && (GET_CODE (XEXP (x
, 1)) == SYMBOL_REF
)
425 /* Avoid this type of address for double or larger modes. */
426 && (GET_MODE_SIZE (mode
) <= 4)
427 /* Avoid small data which ends in something like GP +
429 && (!SYMBOL_REF_SMALL_P (XEXP (x
, 1))))
435 /* Implements target hook vector_mode_supported_p. */
438 arc_vector_mode_supported_p (machine_mode mode
)
443 return TARGET_PLUS_DMPY
;
446 return TARGET_PLUS_QMACW
;
449 return TARGET_SIMD_SET
;
456 /* Implements target hook TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
459 arc_preferred_simd_mode (scalar_mode mode
)
464 return TARGET_PLUS_QMACW
? V4HImode
: V2HImode
;
473 /* Implements target hook
474 TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES. */
477 arc_autovectorize_vector_sizes (vector_sizes
*sizes
)
479 if (TARGET_PLUS_QMACW
)
481 sizes
->quick_push (8);
482 sizes
->quick_push (4);
486 /* TARGET_PRESERVE_RELOAD_P is still awaiting patch re-evaluation / review. */
487 static bool arc_preserve_reload_p (rtx in
) ATTRIBUTE_UNUSED
;
488 static rtx
arc_delegitimize_address (rtx
);
489 static bool arc_can_follow_jump (const rtx_insn
*follower
,
490 const rtx_insn
*followee
);
492 static rtx
frame_insn (rtx
);
493 static void arc_function_arg_advance (cumulative_args_t
, machine_mode
,
495 static rtx
arc_legitimize_address_0 (rtx
, rtx
, machine_mode mode
);
497 /* initialize the GCC target structure. */
498 #undef TARGET_COMP_TYPE_ATTRIBUTES
499 #define TARGET_COMP_TYPE_ATTRIBUTES arc_comp_type_attributes
500 #undef TARGET_ASM_FILE_START
501 #define TARGET_ASM_FILE_START arc_file_start
502 #undef TARGET_ATTRIBUTE_TABLE
503 #define TARGET_ATTRIBUTE_TABLE arc_attribute_table
504 #undef TARGET_ASM_INTERNAL_LABEL
505 #define TARGET_ASM_INTERNAL_LABEL arc_internal_label
506 #undef TARGET_RTX_COSTS
507 #define TARGET_RTX_COSTS arc_rtx_costs
508 #undef TARGET_ADDRESS_COST
509 #define TARGET_ADDRESS_COST arc_address_cost
511 #undef TARGET_ENCODE_SECTION_INFO
512 #define TARGET_ENCODE_SECTION_INFO arc_encode_section_info
514 #undef TARGET_CANNOT_FORCE_CONST_MEM
515 #define TARGET_CANNOT_FORCE_CONST_MEM arc_cannot_force_const_mem
517 #undef TARGET_INIT_BUILTINS
518 #define TARGET_INIT_BUILTINS arc_init_builtins
520 #undef TARGET_EXPAND_BUILTIN
521 #define TARGET_EXPAND_BUILTIN arc_expand_builtin
523 #undef TARGET_BUILTIN_DECL
524 #define TARGET_BUILTIN_DECL arc_builtin_decl
526 #undef TARGET_ASM_OUTPUT_MI_THUNK
527 #define TARGET_ASM_OUTPUT_MI_THUNK arc_output_mi_thunk
529 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
530 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
532 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
533 #define TARGET_FUNCTION_OK_FOR_SIBCALL arc_function_ok_for_sibcall
535 #undef TARGET_MACHINE_DEPENDENT_REORG
536 #define TARGET_MACHINE_DEPENDENT_REORG arc_reorg
538 #undef TARGET_IN_SMALL_DATA_P
539 #define TARGET_IN_SMALL_DATA_P arc_in_small_data_p
541 #undef TARGET_PROMOTE_FUNCTION_MODE
542 #define TARGET_PROMOTE_FUNCTION_MODE \
543 default_promote_function_mode_always_promote
545 #undef TARGET_PROMOTE_PROTOTYPES
546 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
548 #undef TARGET_RETURN_IN_MEMORY
549 #define TARGET_RETURN_IN_MEMORY arc_return_in_memory
550 #undef TARGET_PASS_BY_REFERENCE
551 #define TARGET_PASS_BY_REFERENCE arc_pass_by_reference
553 #undef TARGET_SETUP_INCOMING_VARARGS
554 #define TARGET_SETUP_INCOMING_VARARGS arc_setup_incoming_varargs
556 #undef TARGET_ARG_PARTIAL_BYTES
557 #define TARGET_ARG_PARTIAL_BYTES arc_arg_partial_bytes
559 #undef TARGET_MUST_PASS_IN_STACK
560 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
562 #undef TARGET_FUNCTION_VALUE
563 #define TARGET_FUNCTION_VALUE arc_function_value
565 #undef TARGET_SCHED_ADJUST_PRIORITY
566 #define TARGET_SCHED_ADJUST_PRIORITY arc_sched_adjust_priority
568 #undef TARGET_VECTOR_MODE_SUPPORTED_P
569 #define TARGET_VECTOR_MODE_SUPPORTED_P arc_vector_mode_supported_p
571 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
572 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE arc_preferred_simd_mode
574 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
575 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES arc_autovectorize_vector_sizes
577 #undef TARGET_CAN_USE_DOLOOP_P
578 #define TARGET_CAN_USE_DOLOOP_P arc_can_use_doloop_p
580 #undef TARGET_INVALID_WITHIN_DOLOOP
581 #define TARGET_INVALID_WITHIN_DOLOOP arc_invalid_within_doloop
583 #undef TARGET_PRESERVE_RELOAD_P
584 #define TARGET_PRESERVE_RELOAD_P arc_preserve_reload_p
586 #undef TARGET_CAN_FOLLOW_JUMP
587 #define TARGET_CAN_FOLLOW_JUMP arc_can_follow_jump
589 #undef TARGET_DELEGITIMIZE_ADDRESS
590 #define TARGET_DELEGITIMIZE_ADDRESS arc_delegitimize_address
592 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
593 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
594 arc_use_by_pieces_infrastructure_p
596 /* Usually, we will be able to scale anchor offsets.
597 When this fails, we want LEGITIMIZE_ADDRESS to kick in. */
598 #undef TARGET_MIN_ANCHOR_OFFSET
599 #define TARGET_MIN_ANCHOR_OFFSET (-1024)
600 #undef TARGET_MAX_ANCHOR_OFFSET
601 #define TARGET_MAX_ANCHOR_OFFSET (1020)
603 #undef TARGET_SECONDARY_RELOAD
604 #define TARGET_SECONDARY_RELOAD arc_secondary_reload
606 #define TARGET_OPTION_OVERRIDE arc_override_options
608 #define TARGET_CONDITIONAL_REGISTER_USAGE arc_conditional_register_usage
610 #define TARGET_TRAMPOLINE_INIT arc_initialize_trampoline
612 #define TARGET_CAN_ELIMINATE arc_can_eliminate
614 #define TARGET_FRAME_POINTER_REQUIRED arc_frame_pointer_required
616 #define TARGET_FUNCTION_ARG arc_function_arg
618 #define TARGET_FUNCTION_ARG_ADVANCE arc_function_arg_advance
620 #define TARGET_LEGITIMATE_CONSTANT_P arc_legitimate_constant_p
622 #define TARGET_LEGITIMATE_ADDRESS_P arc_legitimate_address_p
624 #define TARGET_MODE_DEPENDENT_ADDRESS_P arc_mode_dependent_address_p
626 #define TARGET_LEGITIMIZE_ADDRESS arc_legitimize_address
628 #undef TARGET_NO_SPECULATION_IN_DELAY_SLOTS_P
629 #define TARGET_NO_SPECULATION_IN_DELAY_SLOTS_P \
630 arc_no_speculation_in_delay_slots_p
633 #define TARGET_LRA_P arc_lra_p
634 #define TARGET_REGISTER_PRIORITY arc_register_priority
635 /* Stores with scaled offsets have different displacement ranges. */
636 #define TARGET_DIFFERENT_ADDR_DISPLACEMENT_P hook_bool_void_true
637 #define TARGET_SPILL_CLASS arc_spill_class
639 #undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS
640 #define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS arc_allocate_stack_slots_for_args
642 #undef TARGET_WARN_FUNC_RETURN
643 #define TARGET_WARN_FUNC_RETURN arc_warn_func_return
645 #include "target-def.h"
647 #undef TARGET_ASM_ALIGNED_HI_OP
648 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
649 #undef TARGET_ASM_ALIGNED_SI_OP
650 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
653 #undef TARGET_HAVE_TLS
654 #define TARGET_HAVE_TLS HAVE_AS_TLS
657 #undef TARGET_DWARF_REGISTER_SPAN
658 #define TARGET_DWARF_REGISTER_SPAN arc_dwarf_register_span
660 #undef TARGET_HARD_REGNO_NREGS
661 #define TARGET_HARD_REGNO_NREGS arc_hard_regno_nregs
662 #undef TARGET_HARD_REGNO_MODE_OK
663 #define TARGET_HARD_REGNO_MODE_OK arc_hard_regno_mode_ok
665 #undef TARGET_MODES_TIEABLE_P
666 #define TARGET_MODES_TIEABLE_P arc_modes_tieable_p
667 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
668 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE arc_builtin_setjmp_frame_value
670 /* Try to keep the (mov:DF _, reg) as early as possible so
671 that the d<add/sub/mul>h-lr insns appear together and can
672 use the peephole2 pattern. */
675 arc_sched_adjust_priority (rtx_insn
*insn
, int priority
)
677 rtx set
= single_set (insn
);
679 && GET_MODE (SET_SRC(set
)) == DFmode
680 && GET_CODE (SET_SRC(set
)) == REG
)
682 /* Incrementing priority by 20 (empirically derived). */
683 return priority
+ 20;
689 /* For ARC base register + offset addressing, the validity of the
690 address is mode-dependent for most of the offset range, as the
691 offset can be scaled by the access size.
692 We don't expose these as mode-dependent addresses in the
693 mode_dependent_address_p target hook, because that would disable
694 lots of optimizations, and most uses of these addresses are for 32
695 or 64 bit accesses anyways, which are fine.
696 However, that leaves some addresses for 8 / 16 bit values not
697 properly reloaded by the generic code, which is why we have to
698 schedule secondary reloads for these. */
701 arc_secondary_reload (bool in_p
,
705 secondary_reload_info
*sri
)
707 enum rtx_code code
= GET_CODE (x
);
709 if (cl
== DOUBLE_REGS
)
712 /* The loop counter register can be stored, but not loaded directly. */
713 if ((cl
== LPCOUNT_REG
|| cl
== WRITABLE_CORE_REGS
)
714 && in_p
&& MEM_P (x
))
717 /* If we have a subreg (reg), where reg is a pseudo (that will end in
718 a memory location), then we may need a scratch register to handle
719 the fp/sp+largeoffset address. */
727 int regno
= REGNO (x
);
728 if (regno
>= FIRST_PSEUDO_REGISTER
)
729 regno
= reg_renumber
[regno
];
734 /* It is a pseudo that ends in a stack location. */
735 if (reg_equiv_mem (REGNO (x
)))
737 /* Get the equivalent address and check the range of the
739 rtx mem
= reg_equiv_mem (REGNO (x
));
740 addr
= find_replacement (&XEXP (mem
, 0));
745 gcc_assert (MEM_P (x
));
747 addr
= simplify_rtx (addr
);
749 if (addr
&& GET_CODE (addr
) == PLUS
750 && CONST_INT_P (XEXP (addr
, 1))
751 && (!RTX_OK_FOR_OFFSET_P (mode
, XEXP (addr
, 1))))
757 in_p
? CODE_FOR_reload_qi_load
: CODE_FOR_reload_qi_store
;
761 in_p
? CODE_FOR_reload_hi_load
: CODE_FOR_reload_hi_store
;
771 /* Convert reloads using offsets that are too large to use indirect
775 arc_secondary_reload_conv (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
779 gcc_assert (GET_CODE (mem
) == MEM
);
780 addr
= XEXP (mem
, 0);
782 /* Large offset: use a move. FIXME: ld ops accepts limms as
783 offsets. Hence, the following move insn is not required. */
784 emit_move_insn (scratch
, addr
);
785 mem
= replace_equiv_address_nv (mem
, scratch
);
787 /* Now create the move. */
789 emit_insn (gen_rtx_SET (mem
, reg
));
791 emit_insn (gen_rtx_SET (reg
, mem
));
796 static unsigned arc_ifcvt (void);
800 const pass_data pass_data_arc_ifcvt
=
803 "arc_ifcvt", /* name */
804 OPTGROUP_NONE
, /* optinfo_flags */
805 TV_IFCVT2
, /* tv_id */
806 0, /* properties_required */
807 0, /* properties_provided */
808 0, /* properties_destroyed */
809 0, /* todo_flags_start */
810 TODO_df_finish
/* todo_flags_finish */
813 class pass_arc_ifcvt
: public rtl_opt_pass
816 pass_arc_ifcvt(gcc::context
*ctxt
)
817 : rtl_opt_pass(pass_data_arc_ifcvt
, ctxt
)
820 /* opt_pass methods: */
821 opt_pass
* clone () { return new pass_arc_ifcvt (m_ctxt
); }
822 virtual unsigned int execute (function
*) { return arc_ifcvt (); }
828 make_pass_arc_ifcvt (gcc::context
*ctxt
)
830 return new pass_arc_ifcvt (ctxt
);
833 static unsigned arc_predicate_delay_insns (void);
837 const pass_data pass_data_arc_predicate_delay_insns
=
840 "arc_predicate_delay_insns", /* name */
841 OPTGROUP_NONE
, /* optinfo_flags */
842 TV_IFCVT2
, /* tv_id */
843 0, /* properties_required */
844 0, /* properties_provided */
845 0, /* properties_destroyed */
846 0, /* todo_flags_start */
847 TODO_df_finish
/* todo_flags_finish */
850 class pass_arc_predicate_delay_insns
: public rtl_opt_pass
853 pass_arc_predicate_delay_insns(gcc::context
*ctxt
)
854 : rtl_opt_pass(pass_data_arc_predicate_delay_insns
, ctxt
)
857 /* opt_pass methods: */
858 virtual unsigned int execute (function
*)
860 return arc_predicate_delay_insns ();
867 make_pass_arc_predicate_delay_insns (gcc::context
*ctxt
)
869 return new pass_arc_predicate_delay_insns (ctxt
);
872 /* Called by OVERRIDE_OPTIONS to initialize various things. */
879 /* I have the multiplier, then use it*/
880 if (TARGET_MPYW
|| TARGET_MULTI
)
881 arc_multcost
= COSTS_N_INSNS (1);
883 /* Note: arc_multcost is only used in rtx_cost if speed is true. */
884 if (arc_multcost
< 0)
887 case ARC_TUNE_ARC700_4_2_STD
:
889 max throughput (1 multiply + 4 other insns) / 5 cycles. */
890 arc_multcost
= COSTS_N_INSNS (4);
891 if (TARGET_NOMPY_SET
)
892 arc_multcost
= COSTS_N_INSNS (30);
894 case ARC_TUNE_ARC700_4_2_XMAC
:
896 max throughput (1 multiply + 2 other insns) / 3 cycles. */
897 arc_multcost
= COSTS_N_INSNS (3);
898 if (TARGET_NOMPY_SET
)
899 arc_multcost
= COSTS_N_INSNS (30);
901 case ARC_TUNE_ARC600
:
902 if (TARGET_MUL64_SET
)
904 arc_multcost
= COSTS_N_INSNS (4);
909 arc_multcost
= COSTS_N_INSNS (30);
913 /* MPY instructions valid only for ARC700 or ARCv2. */
914 if (TARGET_NOMPY_SET
&& TARGET_ARC600_FAMILY
)
915 error ("-mno-mpy supported only for ARC700 or ARCv2");
917 if (!TARGET_DPFP
&& TARGET_DPFP_DISABLE_LRSR
)
918 error ("-mno-dpfp-lrsr supported only with -mdpfp");
920 /* FPX-1. No fast and compact together. */
921 if ((TARGET_DPFP_FAST_SET
&& TARGET_DPFP_COMPACT_SET
)
922 || (TARGET_SPFP_FAST_SET
&& TARGET_SPFP_COMPACT_SET
))
923 error ("FPX fast and compact options cannot be specified together");
925 /* FPX-2. No fast-spfp for arc600 or arc601. */
926 if (TARGET_SPFP_FAST_SET
&& TARGET_ARC600_FAMILY
)
927 error ("-mspfp_fast not available on ARC600 or ARC601");
929 /* FPX-4. No FPX extensions mixed with FPU extensions. */
930 if ((TARGET_DPFP_FAST_SET
|| TARGET_DPFP_COMPACT_SET
|| TARGET_SPFP
)
931 && TARGET_HARD_FLOAT
)
932 error ("No FPX/FPU mixing allowed");
934 /* Warn for unimplemented PIC in pre-ARC700 cores, and disable flag_pic. */
935 if (flag_pic
&& TARGET_ARC600_FAMILY
)
938 "PIC is not supported for %s. Generating non-PIC code only..",
943 arc_init_reg_tables ();
945 /* Initialize array for PRINT_OPERAND_PUNCT_VALID_P. */
946 memset (arc_punct_chars
, 0, sizeof (arc_punct_chars
));
947 arc_punct_chars
['#'] = 1;
948 arc_punct_chars
['*'] = 1;
949 arc_punct_chars
['?'] = 1;
950 arc_punct_chars
['!'] = 1;
951 arc_punct_chars
['^'] = 1;
952 arc_punct_chars
['&'] = 1;
953 arc_punct_chars
['+'] = 1;
954 arc_punct_chars
['_'] = 1;
956 if (optimize
> 1 && !TARGET_NO_COND_EXEC
)
958 /* There are two target-independent ifcvt passes, and arc_reorg may do
959 one or more arc_ifcvt calls. */
960 opt_pass
*pass_arc_ifcvt_4
= make_pass_arc_ifcvt (g
);
961 struct register_pass_info arc_ifcvt4_info
962 = { pass_arc_ifcvt_4
, "dbr", 1, PASS_POS_INSERT_AFTER
};
963 struct register_pass_info arc_ifcvt5_info
964 = { pass_arc_ifcvt_4
->clone (), "shorten", 1, PASS_POS_INSERT_BEFORE
};
966 register_pass (&arc_ifcvt4_info
);
967 register_pass (&arc_ifcvt5_info
);
970 if (flag_delayed_branch
)
972 opt_pass
*pass_arc_predicate_delay_insns
973 = make_pass_arc_predicate_delay_insns (g
);
974 struct register_pass_info arc_predicate_delay_info
975 = { pass_arc_predicate_delay_insns
, "dbr", 1, PASS_POS_INSERT_AFTER
};
977 register_pass (&arc_predicate_delay_info
);
981 /* Parse -mirq-ctrl-saved=RegisterRange, blink, lp_copunt. The
982 register range is specified as two registers separated by a dash.
983 It always starts with r0, and its upper limit is fp register.
984 blink and lp_count registers are optional. */
987 irq_range (const char *cstr
)
989 int i
, first
, last
, blink
, lpcount
, xreg
;
990 char *str
, *dash
, *comma
;
993 str
= (char *) alloca (i
+ 1);
994 memcpy (str
, cstr
, i
+ 1);
998 dash
= strchr (str
, '-');
1001 warning (OPT_mirq_ctrl_saved_
, "missing dash");
1006 comma
= strchr (dash
+ 1, ',');
1010 first
= decode_reg_name (str
);
1013 warning (OPT_mirq_ctrl_saved_
, "first register must be R0");
1017 /* At this moment we do not have the register names initialized
1019 if (!strcmp (dash
+ 1, "ilink"))
1022 last
= decode_reg_name (dash
+ 1);
1026 warning (OPT_mirq_ctrl_saved_
, "unknown register name: %s", dash
+ 1);
1032 warning (OPT_mirq_ctrl_saved_
,
1033 "last register name %s must be an odd register", dash
+ 1);
1041 warning (OPT_mirq_ctrl_saved_
,
1042 "%s-%s is an empty range", str
, dash
+ 1);
1051 comma
= strchr (str
, ',');
1055 xreg
= decode_reg_name (str
);
1067 warning (OPT_mirq_ctrl_saved_
,
1068 "unknown register name: %s", str
);
1073 irq_ctrl_saved
.irq_save_last_reg
= last
;
1074 irq_ctrl_saved
.irq_save_blink
= (blink
== 31) || (last
== 31);
1075 irq_ctrl_saved
.irq_save_lpcount
= (lpcount
== 60);
1078 /* Parse -mrgf-banked-regs=NUM option string. Valid values for NUM are 4,
1082 parse_mrgf_banked_regs_option (const char *arg
)
1088 val
= strtol (arg
, &end_ptr
, 10);
1089 if (errno
!= 0 || *arg
== '\0' || *end_ptr
!= '\0'
1090 || (val
!= 0 && val
!= 4 && val
!= 8 && val
!= 16 && val
!= 32))
1092 error ("invalid number in -mrgf-banked-regs=%s "
1093 "valid values are 0, 4, 8, 16, or 32", arg
);
1096 rgf_banked_register_count
= (int) val
;
1099 /* Check ARC options, generate derived target attributes. */
1102 arc_override_options (void)
1105 cl_deferred_option
*opt
;
1106 vec
<cl_deferred_option
> *vopt
1107 = (vec
<cl_deferred_option
> *) arc_deferred_options
;
1109 if (arc_cpu
== PROCESSOR_NONE
)
1110 arc_cpu
= TARGET_CPU_DEFAULT
;
1112 /* Set the default cpu options. */
1113 arc_selected_cpu
= &arc_cpu_types
[(int) arc_cpu
];
1115 /* Set the architectures. */
1116 switch (arc_selected_cpu
->arch_info
->arch_id
)
1119 arc_cpu_string
= "EM";
1122 arc_cpu_string
= "HS";
1125 if (arc_selected_cpu
->processor
== PROCESSOR_nps400
)
1126 arc_cpu_string
= "NPS400";
1128 arc_cpu_string
= "ARC700";
1131 arc_cpu_string
= "ARC600";
1137 irq_ctrl_saved
.irq_save_last_reg
= -1;
1138 irq_ctrl_saved
.irq_save_blink
= false;
1139 irq_ctrl_saved
.irq_save_lpcount
= false;
1141 rgf_banked_register_count
= 0;
1143 /* Handle the deferred options. */
1145 FOR_EACH_VEC_ELT (*vopt
, i
, opt
)
1147 switch (opt
->opt_index
)
1149 case OPT_mirq_ctrl_saved_
:
1151 irq_range (opt
->arg
);
1153 warning (OPT_mirq_ctrl_saved_
,
1154 "option -mirq-ctrl-saved valid only for ARC v2 processors");
1157 case OPT_mrgf_banked_regs_
:
1159 parse_mrgf_banked_regs_option (opt
->arg
);
1161 warning (OPT_mrgf_banked_regs_
,
1162 "option -mrgf-banked-regs valid only for ARC v2 processors");
1170 CLEAR_HARD_REG_SET (overrideregs
);
1171 if (common_deferred_options
)
1173 vec
<cl_deferred_option
> v
=
1174 *((vec
<cl_deferred_option
> *) common_deferred_options
);
1177 FOR_EACH_VEC_ELT (v
, i
, opt
)
1179 switch (opt
->opt_index
)
1182 case OPT_fcall_used_
:
1183 case OPT_fcall_saved_
:
1184 if ((reg
= decode_reg_name_and_count (opt
->arg
, &nregs
)) >= 0)
1185 for (j
= reg
; j
< reg
+ nregs
; j
++)
1186 SET_HARD_REG_BIT (overrideregs
, j
);
1194 /* Check options against architecture options. Throw an error if
1195 option is not allowed. Extra, check options against default
1196 architecture/cpu flags and throw an warning if we find a
1198 #define ARC_OPTX(NAME, CODE, VAR, VAL, DOC0, DOC1) \
1200 if ((!(arc_selected_cpu->arch_info->flags & CODE)) \
1202 error ("Option %s=%s is not available for %s CPU.", \
1203 DOC0, DOC1, arc_selected_cpu->name); \
1204 if ((arc_selected_cpu->arch_info->dflags & CODE) \
1205 && (VAR != DEFAULT_##VAR) \
1207 warning (0, "Option %s is ignored, the default value %s" \
1208 " is considered for %s CPU.", DOC0, DOC1, \
1209 arc_selected_cpu->name); \
1211 #define ARC_OPT(NAME, CODE, MASK, DOC) \
1213 if ((!(arc_selected_cpu->arch_info->flags & CODE)) \
1214 && (target_flags & MASK)) \
1215 error ("Option %s is not available for %s CPU", \
1216 DOC, arc_selected_cpu->name); \
1217 if ((arc_selected_cpu->arch_info->dflags & CODE) \
1218 && (target_flags_explicit & MASK) \
1219 && (!(target_flags & MASK))) \
1220 warning (0, "Unset option %s is ignored, it is always" \
1221 " enabled for %s CPU.", DOC, \
1222 arc_selected_cpu->name); \
1225 #include "arc-options.def"
1230 /* Set cpu flags accordingly to architecture/selected cpu. The cpu
1231 specific flags are set in arc-common.c. The architecture forces
1232 the default hardware configurations in, regardless what command
1233 line options are saying. The CPU optional hw options can be
1234 turned on or off. */
1235 #define ARC_OPT(NAME, CODE, MASK, DOC) \
1237 if ((arc_selected_cpu->flags & CODE) \
1238 && ((target_flags_explicit & MASK) == 0)) \
1239 target_flags |= MASK; \
1240 if (arc_selected_cpu->arch_info->dflags & CODE) \
1241 target_flags |= MASK; \
1243 #define ARC_OPTX(NAME, CODE, VAR, VAL, DOC0, DOC1) \
1245 if ((arc_selected_cpu->flags & CODE) \
1246 && (VAR == DEFAULT_##VAR)) \
1248 if (arc_selected_cpu->arch_info->dflags & CODE) \
1252 #include "arc-options.def"
1257 /* Set Tune option. */
1258 if (arc_tune
== ARC_TUNE_NONE
)
1259 arc_tune
= (enum arc_tune_attr
) arc_selected_cpu
->tune
;
1261 if (arc_size_opt_level
== 3)
1264 /* Compact casesi is not a valid option for ARCv2 family. */
1267 if (TARGET_COMPACT_CASESI
)
1269 warning (OPT_mcompact_casesi
,
1270 "compact-casesi is not applicable to ARCv2");
1271 TARGET_COMPACT_CASESI
= 0;
1274 else if (optimize_size
== 1
1275 && !global_options_set
.x_TARGET_COMPACT_CASESI
)
1276 TARGET_COMPACT_CASESI
= 1;
1279 target_flags
|= MASK_NO_SDATA_SET
;
1281 if (flag_no_common
== 255)
1282 flag_no_common
= !TARGET_NO_SDATA_SET
;
1284 /* TARGET_COMPACT_CASESI needs the "q" register class. */
1285 if (TARGET_MIXED_CODE
)
1287 if (!TARGET_Q_CLASS
)
1288 TARGET_COMPACT_CASESI
= 0;
1289 if (TARGET_COMPACT_CASESI
)
1290 TARGET_CASE_VECTOR_PC_RELATIVE
= 1;
1292 /* Check for small data option */
1293 if (!global_options_set
.x_g_switch_value
&& !TARGET_NO_SDATA_SET
)
1294 g_switch_value
= TARGET_LL64
? 8 : 4;
1296 /* These need to be done at start up. It's convenient to do them here. */
1300 /* The condition codes of the ARC, and the inverse function. */
1301 /* For short branches, the "c" / "nc" names are not defined in the ARC
1302 Programmers manual, so we have to use "lo" / "hs"" instead. */
1303 static const char *arc_condition_codes
[] =
1305 "al", 0, "eq", "ne", "p", "n", "lo", "hs", "v", "nv",
1306 "gt", "le", "ge", "lt", "hi", "ls", "pnz", 0
1309 enum arc_cc_code_index
1311 ARC_CC_AL
, ARC_CC_EQ
= ARC_CC_AL
+2, ARC_CC_NE
, ARC_CC_P
, ARC_CC_N
,
1312 ARC_CC_C
, ARC_CC_NC
, ARC_CC_V
, ARC_CC_NV
,
1313 ARC_CC_GT
, ARC_CC_LE
, ARC_CC_GE
, ARC_CC_LT
, ARC_CC_HI
, ARC_CC_LS
, ARC_CC_PNZ
,
1314 ARC_CC_LO
= ARC_CC_C
, ARC_CC_HS
= ARC_CC_NC
1317 #define ARC_INVERSE_CONDITION_CODE(X) ((X) ^ 1)
1319 /* Returns the index of the ARC condition code string in
1320 `arc_condition_codes'. COMPARISON should be an rtx like
1321 `(eq (...) (...))'. */
1324 get_arc_condition_code (rtx comparison
)
1326 switch (GET_MODE (XEXP (comparison
, 0)))
1329 case E_SImode
: /* For BRcc. */
1330 switch (GET_CODE (comparison
))
1332 case EQ
: return ARC_CC_EQ
;
1333 case NE
: return ARC_CC_NE
;
1334 case GT
: return ARC_CC_GT
;
1335 case LE
: return ARC_CC_LE
;
1336 case GE
: return ARC_CC_GE
;
1337 case LT
: return ARC_CC_LT
;
1338 case GTU
: return ARC_CC_HI
;
1339 case LEU
: return ARC_CC_LS
;
1340 case LTU
: return ARC_CC_LO
;
1341 case GEU
: return ARC_CC_HS
;
1342 default : gcc_unreachable ();
1345 switch (GET_CODE (comparison
))
1347 case EQ
: return ARC_CC_EQ
;
1348 case NE
: return ARC_CC_NE
;
1349 case GE
: return ARC_CC_P
;
1350 case LT
: return ARC_CC_N
;
1351 case GT
: return ARC_CC_PNZ
;
1352 default : gcc_unreachable ();
1355 switch (GET_CODE (comparison
))
1357 case EQ
: return ARC_CC_EQ
;
1358 case NE
: return ARC_CC_NE
;
1359 default : gcc_unreachable ();
1362 switch (GET_CODE (comparison
))
1364 case LTU
: return ARC_CC_C
;
1365 case GEU
: return ARC_CC_NC
;
1366 default : gcc_unreachable ();
1368 case E_CC_FP_GTmode
:
1369 if (TARGET_ARGONAUT_SET
&& TARGET_SPFP
)
1370 switch (GET_CODE (comparison
))
1372 case GT
: return ARC_CC_N
;
1373 case UNLE
: return ARC_CC_P
;
1374 default : gcc_unreachable ();
1377 switch (GET_CODE (comparison
))
1379 case GT
: return ARC_CC_HI
;
1380 case UNLE
: return ARC_CC_LS
;
1381 default : gcc_unreachable ();
1383 case E_CC_FP_GEmode
:
1384 /* Same for FPX and non-FPX. */
1385 switch (GET_CODE (comparison
))
1387 case GE
: return ARC_CC_HS
;
1388 case UNLT
: return ARC_CC_LO
;
1389 default : gcc_unreachable ();
1391 case E_CC_FP_UNEQmode
:
1392 switch (GET_CODE (comparison
))
1394 case UNEQ
: return ARC_CC_EQ
;
1395 case LTGT
: return ARC_CC_NE
;
1396 default : gcc_unreachable ();
1398 case E_CC_FP_ORDmode
:
1399 switch (GET_CODE (comparison
))
1401 case UNORDERED
: return ARC_CC_C
;
1402 case ORDERED
: return ARC_CC_NC
;
1403 default : gcc_unreachable ();
1406 switch (GET_CODE (comparison
))
1408 case EQ
: return ARC_CC_EQ
;
1409 case NE
: return ARC_CC_NE
;
1410 case UNORDERED
: return ARC_CC_C
;
1411 case ORDERED
: return ARC_CC_NC
;
1412 case LTGT
: return ARC_CC_HI
;
1413 case UNEQ
: return ARC_CC_LS
;
1414 default : gcc_unreachable ();
1417 switch (GET_CODE (comparison
))
1419 case EQ
: return ARC_CC_EQ
;
1420 case NE
: return ARC_CC_NE
;
1421 case GT
: return ARC_CC_GT
;
1422 case GE
: return ARC_CC_GE
;
1423 case LT
: return ARC_CC_C
;
1424 case LE
: return ARC_CC_LS
;
1425 case UNORDERED
: return ARC_CC_V
;
1426 case ORDERED
: return ARC_CC_NV
;
1427 case UNGT
: return ARC_CC_HI
;
1428 case UNGE
: return ARC_CC_HS
;
1429 case UNLT
: return ARC_CC_LT
;
1430 case UNLE
: return ARC_CC_LE
;
1431 /* UNEQ and LTGT do not have representation. */
1432 case LTGT
: /* Fall through. */
1433 case UNEQ
: /* Fall through. */
1434 default : gcc_unreachable ();
1436 case E_CC_FPU_UNEQmode
:
1437 switch (GET_CODE (comparison
))
1439 case LTGT
: return ARC_CC_NE
;
1440 case UNEQ
: return ARC_CC_EQ
;
1441 default : gcc_unreachable ();
1443 default : gcc_unreachable ();
1449 /* Return true if COMPARISON has a short form that can accomodate OFFSET. */
1452 arc_short_comparison_p (rtx comparison
, int offset
)
1454 gcc_assert (ARC_CC_NC
== ARC_CC_HS
);
1455 gcc_assert (ARC_CC_C
== ARC_CC_LO
);
1456 switch (get_arc_condition_code (comparison
))
1458 case ARC_CC_EQ
: case ARC_CC_NE
:
1459 return offset
>= -512 && offset
<= 506;
1460 case ARC_CC_GT
: case ARC_CC_LE
: case ARC_CC_GE
: case ARC_CC_LT
:
1461 case ARC_CC_HI
: case ARC_CC_LS
: case ARC_CC_LO
: case ARC_CC_HS
:
1462 return offset
>= -64 && offset
<= 58;
1468 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1469 return the mode to be used for the comparison. */
1472 arc_select_cc_mode (enum rtx_code op
, rtx x
, rtx y
)
1474 machine_mode mode
= GET_MODE (x
);
1477 /* For an operation that sets the condition codes as a side-effect, the
1478 C and V flags is not set as for cmp, so we can only use comparisons where
1479 this doesn't matter. (For LT and GE we can use "mi" and "pl"
1481 /* ??? We could use "pnz" for greater than zero, however, we could then
1482 get into trouble because the comparison could not be reversed. */
1483 if (GET_MODE_CLASS (mode
) == MODE_INT
1485 && (op
== EQ
|| op
== NE
1486 || ((op
== LT
|| op
== GE
) && GET_MODE_SIZE (GET_MODE (x
)) <= 4)))
1489 /* add.f for if (a+b) */
1491 && GET_CODE (y
) == NEG
1492 && (op
== EQ
|| op
== NE
))
1495 /* Check if this is a test suitable for bxor.f . */
1496 if (mode
== SImode
&& (op
== EQ
|| op
== NE
) && CONST_INT_P (y
)
1497 && ((INTVAL (y
) - 1) & INTVAL (y
)) == 0
1501 /* Check if this is a test suitable for add / bmsk.f . */
1502 if (mode
== SImode
&& (op
== EQ
|| op
== NE
) && CONST_INT_P (y
)
1503 && GET_CODE (x
) == AND
&& CONST_INT_P ((x1
= XEXP (x
, 1)))
1504 && ((INTVAL (x1
) + 1) & INTVAL (x1
)) == 0
1505 && (~INTVAL (x1
) | INTVAL (y
)) < 0
1506 && (~INTVAL (x1
) | INTVAL (y
)) > -0x800)
1509 if (GET_MODE (x
) == SImode
&& (op
== LTU
|| op
== GEU
)
1510 && GET_CODE (x
) == PLUS
1511 && (rtx_equal_p (XEXP (x
, 0), y
) || rtx_equal_p (XEXP (x
, 1), y
)))
1514 if (TARGET_ARGONAUT_SET
1515 && ((mode
== SFmode
&& TARGET_SPFP
) || (mode
== DFmode
&& TARGET_DPFP
)))
1518 case EQ
: case NE
: case UNEQ
: case LTGT
: case ORDERED
: case UNORDERED
:
1520 case LT
: case UNGE
: case GT
: case UNLE
:
1521 return CC_FP_GTmode
;
1522 case LE
: case UNGT
: case GE
: case UNLT
:
1523 return CC_FP_GEmode
;
1524 default: gcc_unreachable ();
1526 else if (TARGET_HARD_FLOAT
1527 && ((mode
== SFmode
&& TARGET_FP_SP_BASE
)
1528 || (mode
== DFmode
&& TARGET_FP_DP_BASE
)))
1547 return CC_FPU_UNEQmode
;
1552 else if (GET_MODE_CLASS (mode
) == MODE_FLOAT
&& TARGET_OPTFPE
)
1556 case EQ
: case NE
: return CC_Zmode
;
1558 case GT
: case UNLE
: return CC_FP_GTmode
;
1560 case GE
: case UNLT
: return CC_FP_GEmode
;
1561 case UNEQ
: case LTGT
: return CC_FP_UNEQmode
;
1562 case ORDERED
: case UNORDERED
: return CC_FP_ORDmode
;
1563 default: gcc_unreachable ();
1569 /* Vectors to keep interesting information about registers where it can easily
1570 be got. We use to use the actual mode value as the bit number, but there
1571 is (or may be) more than 32 modes now. Instead we use two tables: one
1572 indexed by hard register number, and one indexed by mode. */
1574 /* The purpose of arc_mode_class is to shrink the range of modes so that
1575 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
1576 mapped into one arc_mode_class mode. */
1578 enum arc_mode_class
{
1580 S_MODE
, D_MODE
, T_MODE
, O_MODE
,
1581 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
,
1585 /* Modes for condition codes. */
1586 #define C_MODES (1 << (int) C_MODE)
1588 /* Modes for single-word and smaller quantities. */
1589 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
1591 /* Modes for double-word and smaller quantities. */
1592 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
1594 /* Mode for 8-byte DF values only. */
1595 #define DF_MODES (1 << DF_MODE)
1597 /* Modes for quad-word and smaller quantities. */
1598 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
1600 /* Modes for 128-bit vectors. */
1601 #define V_MODES (1 << (int) V_MODE)
1603 /* Value is 1 if register/mode pair is acceptable on arc. */
1605 static unsigned int arc_hard_regno_modes
[] = {
1606 T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
,
1607 T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
,
1608 T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, D_MODES
,
1609 D_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
,
1611 /* ??? Leave these as S_MODES for now. */
1612 S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
,
1613 DF_MODES
, 0, DF_MODES
, 0, S_MODES
, S_MODES
, S_MODES
, S_MODES
,
1614 S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
,
1615 S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, C_MODES
, S_MODES
,
1617 V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
,
1618 V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
,
1619 V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
,
1620 V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
,
1622 V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
,
1623 V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
,
1624 V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
,
1625 V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
,
1627 S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
,
1628 S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
1631 static unsigned int arc_mode_class
[NUM_MACHINE_MODES
];
1633 enum reg_class arc_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
1636 arc_preferred_reload_class (rtx
, enum reg_class cl
)
1638 if ((cl
) == CHEAP_CORE_REGS
|| (cl
) == WRITABLE_CORE_REGS
)
1639 return GENERAL_REGS
;
1643 /* Initialize the arc_mode_class array. */
1646 arc_init_reg_tables (void)
1650 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
1652 machine_mode m
= (machine_mode
) i
;
1654 switch (GET_MODE_CLASS (m
))
1657 case MODE_PARTIAL_INT
:
1658 case MODE_COMPLEX_INT
:
1659 if (GET_MODE_SIZE (m
) <= 4)
1660 arc_mode_class
[i
] = 1 << (int) S_MODE
;
1661 else if (GET_MODE_SIZE (m
) == 8)
1662 arc_mode_class
[i
] = 1 << (int) D_MODE
;
1663 else if (GET_MODE_SIZE (m
) == 16)
1664 arc_mode_class
[i
] = 1 << (int) T_MODE
;
1665 else if (GET_MODE_SIZE (m
) == 32)
1666 arc_mode_class
[i
] = 1 << (int) O_MODE
;
1668 arc_mode_class
[i
] = 0;
1671 case MODE_COMPLEX_FLOAT
:
1672 if (GET_MODE_SIZE (m
) <= 4)
1673 arc_mode_class
[i
] = 1 << (int) SF_MODE
;
1674 else if (GET_MODE_SIZE (m
) == 8)
1675 arc_mode_class
[i
] = 1 << (int) DF_MODE
;
1676 else if (GET_MODE_SIZE (m
) == 16)
1677 arc_mode_class
[i
] = 1 << (int) TF_MODE
;
1678 else if (GET_MODE_SIZE (m
) == 32)
1679 arc_mode_class
[i
] = 1 << (int) OF_MODE
;
1681 arc_mode_class
[i
] = 0;
1683 case MODE_VECTOR_INT
:
1684 if (GET_MODE_SIZE (m
) == 4)
1685 arc_mode_class
[i
] = (1 << (int) S_MODE
);
1686 else if (GET_MODE_SIZE (m
) == 8)
1687 arc_mode_class
[i
] = (1 << (int) D_MODE
);
1689 arc_mode_class
[i
] = (1 << (int) V_MODE
);
1693 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
1694 we must explicitly check for them here. */
1695 if (i
== (int) CCmode
|| i
== (int) CC_ZNmode
|| i
== (int) CC_Zmode
1696 || i
== (int) CC_Cmode
1697 || i
== CC_FP_GTmode
|| i
== CC_FP_GEmode
|| i
== CC_FP_ORDmode
1698 || i
== CC_FPUmode
|| i
== CC_FPU_UNEQmode
)
1699 arc_mode_class
[i
] = 1 << (int) C_MODE
;
1701 arc_mode_class
[i
] = 0;
1707 /* Core registers 56..59 are used for multiply extension options.
1708 The dsp option uses r56 and r57, these are then named acc1 and acc2.
1709 acc1 is the highpart, and acc2 the lowpart, so which register gets which
1710 number depends on endianness.
1711 The mul64 multiplier options use r57 for mlo, r58 for mmid and r59 for mhi.
1712 Because mlo / mhi form a 64 bit value, we use different gcc internal
1713 register numbers to make them form a register pair as the gcc internals
1714 know it. mmid gets number 57, if still available, and mlo / mhi get
1715 number 58 and 59, depending on endianness. We use DBX_REGISTER_NUMBER
1716 to map this back. */
1717 char rname56
[5] = "r56";
1718 char rname57
[5] = "r57";
1719 char rname58
[5] = "r58";
1720 char rname59
[5] = "r59";
1721 char rname29
[7] = "ilink1";
1722 char rname30
[7] = "ilink2";
1725 arc_conditional_register_usage (void)
1729 int fix_start
= 60, fix_end
= 55;
1733 /* For ARCv2 the core register set is changed. */
1734 strcpy (rname29
, "ilink");
1735 strcpy (rname30
, "r30");
1737 if (!TEST_HARD_REG_BIT (overrideregs
, 30))
1739 /* No user interference. Set the r30 to be used by the
1741 call_used_regs
[30] = 1;
1744 arc_regno_reg_class
[30] = WRITABLE_CORE_REGS
;
1745 SET_HARD_REG_BIT (reg_class_contents
[WRITABLE_CORE_REGS
], 30);
1746 SET_HARD_REG_BIT (reg_class_contents
[CHEAP_CORE_REGS
], 30);
1747 SET_HARD_REG_BIT (reg_class_contents
[GENERAL_REGS
], 30);
1748 SET_HARD_REG_BIT (reg_class_contents
[MPY_WRITABLE_CORE_REGS
], 30);
1752 if (TARGET_MUL64_SET
)
1757 /* We don't provide a name for mmed. In rtl / assembly resource lists,
1758 you are supposed to refer to it as mlo & mhi, e.g
1759 (zero_extract:SI (reg:DI 58) (const_int 32) (16)) .
1760 In an actual asm instruction, you are of course use mmed.
1761 The point of avoiding having a separate register for mmed is that
1762 this way, we don't have to carry clobbers of that reg around in every
1763 isntruction that modifies mlo and/or mhi. */
1764 strcpy (rname57
, "");
1765 strcpy (rname58
, TARGET_BIG_ENDIAN
? "mhi" : "mlo");
1766 strcpy (rname59
, TARGET_BIG_ENDIAN
? "mlo" : "mhi");
1769 /* The nature of arc_tp_regno is actually something more like a global
1770 register, however globalize_reg requires a declaration.
1771 We use EPILOGUE_USES to compensate so that sets from
1772 __builtin_set_frame_pointer are not deleted. */
1773 if (arc_tp_regno
!= -1)
1774 fixed_regs
[arc_tp_regno
] = call_used_regs
[arc_tp_regno
] = 1;
1776 if (TARGET_MULMAC_32BY16_SET
)
1779 fix_end
= fix_end
> 57 ? fix_end
: 57;
1780 strcpy (rname56
, TARGET_BIG_ENDIAN
? "acc1" : "acc2");
1781 strcpy (rname57
, TARGET_BIG_ENDIAN
? "acc2" : "acc1");
1783 for (regno
= fix_start
; regno
<= fix_end
; regno
++)
1785 if (!fixed_regs
[regno
])
1786 warning (0, "multiply option implies r%d is fixed", regno
);
1787 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
1793 reg_alloc_order
[0] = 0;
1794 reg_alloc_order
[1] = 1;
1795 reg_alloc_order
[2] = 2;
1796 reg_alloc_order
[3] = 3;
1797 reg_alloc_order
[4] = 12;
1798 reg_alloc_order
[5] = 13;
1799 reg_alloc_order
[6] = 14;
1800 reg_alloc_order
[7] = 15;
1801 reg_alloc_order
[8] = 4;
1802 reg_alloc_order
[9] = 5;
1803 reg_alloc_order
[10] = 6;
1804 reg_alloc_order
[11] = 7;
1805 reg_alloc_order
[12] = 8;
1806 reg_alloc_order
[13] = 9;
1807 reg_alloc_order
[14] = 10;
1808 reg_alloc_order
[15] = 11;
1812 reg_alloc_order
[2] = 12;
1813 reg_alloc_order
[3] = 13;
1814 reg_alloc_order
[4] = 14;
1815 reg_alloc_order
[5] = 15;
1816 reg_alloc_order
[6] = 1;
1817 reg_alloc_order
[7] = 0;
1818 reg_alloc_order
[8] = 4;
1819 reg_alloc_order
[9] = 5;
1820 reg_alloc_order
[10] = 6;
1821 reg_alloc_order
[11] = 7;
1822 reg_alloc_order
[12] = 8;
1823 reg_alloc_order
[13] = 9;
1824 reg_alloc_order
[14] = 10;
1825 reg_alloc_order
[15] = 11;
1828 if (TARGET_SIMD_SET
)
1831 for (i
= ARC_FIRST_SIMD_VR_REG
; i
<= ARC_LAST_SIMD_VR_REG
; i
++)
1832 reg_alloc_order
[i
] = i
;
1833 for (i
= ARC_FIRST_SIMD_DMA_CONFIG_REG
;
1834 i
<= ARC_LAST_SIMD_DMA_CONFIG_REG
; i
++)
1835 reg_alloc_order
[i
] = i
;
1838 /* Reduced configuration: don't use r4-r9, r16-r25. */
1841 for (i
= 4; i
<= 9; i
++)
1843 fixed_regs
[i
] = call_used_regs
[i
] = 1;
1845 for (i
= 16; i
<= 25; i
++)
1847 fixed_regs
[i
] = call_used_regs
[i
] = 1;
1851 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
1852 if (!call_used_regs
[regno
])
1853 CLEAR_HARD_REG_BIT (reg_class_contents
[SIBCALL_REGS
], regno
);
1854 for (regno
= 32; regno
< 60; regno
++)
1855 if (!fixed_regs
[regno
])
1856 SET_HARD_REG_BIT (reg_class_contents
[WRITABLE_CORE_REGS
], regno
);
1857 if (!TARGET_ARC600_FAMILY
)
1859 for (regno
= 32; regno
<= 60; regno
++)
1860 CLEAR_HARD_REG_BIT (reg_class_contents
[CHEAP_CORE_REGS
], regno
);
1862 /* If they have used -ffixed-lp_count, make sure it takes
1864 if (fixed_regs
[LP_COUNT
])
1866 CLEAR_HARD_REG_BIT (reg_class_contents
[LPCOUNT_REG
], LP_COUNT
);
1867 CLEAR_HARD_REG_BIT (reg_class_contents
[SIBCALL_REGS
], LP_COUNT
);
1868 CLEAR_HARD_REG_BIT (reg_class_contents
[WRITABLE_CORE_REGS
], LP_COUNT
);
1870 /* Instead of taking out SF_MODE like below, forbid it outright. */
1871 arc_hard_regno_modes
[60] = 0;
1874 arc_hard_regno_modes
[60] = 1 << (int) S_MODE
;
1877 /* ARCHS has 64-bit data-path which makes use of the even-odd paired
1881 for (regno
= 1; regno
< 32; regno
+=2)
1883 arc_hard_regno_modes
[regno
] = S_MODES
;
1887 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1891 if ((TARGET_Q_CLASS
|| TARGET_RRQ_CLASS
)
1892 && ((i
<= 3) || ((i
>= 12) && (i
<= 15))))
1893 arc_regno_reg_class
[i
] = ARCOMPACT16_REGS
;
1895 arc_regno_reg_class
[i
] = GENERAL_REGS
;
1898 arc_regno_reg_class
[i
]
1900 ? (TEST_HARD_REG_BIT (reg_class_contents
[CHEAP_CORE_REGS
], i
)
1901 ? CHEAP_CORE_REGS
: ALL_CORE_REGS
)
1902 : (((!TARGET_ARC600_FAMILY
)
1903 && TEST_HARD_REG_BIT (reg_class_contents
[CHEAP_CORE_REGS
], i
))
1904 ? CHEAP_CORE_REGS
: WRITABLE_CORE_REGS
));
1906 arc_regno_reg_class
[i
] = NO_REGS
;
1909 /* ARCOMPACT16_REGS is empty, if TARGET_Q_CLASS / TARGET_RRQ_CLASS
1910 has not been activated. */
1911 if (!TARGET_Q_CLASS
&& !TARGET_RRQ_CLASS
)
1912 CLEAR_HARD_REG_SET(reg_class_contents
[ARCOMPACT16_REGS
]);
1913 if (!TARGET_Q_CLASS
)
1914 CLEAR_HARD_REG_SET(reg_class_contents
[AC16_BASE_REGS
]);
1916 gcc_assert (FIRST_PSEUDO_REGISTER
>= 144);
1918 /* Handle Special Registers. */
1919 arc_regno_reg_class
[29] = LINK_REGS
; /* ilink1 register. */
1921 arc_regno_reg_class
[30] = LINK_REGS
; /* ilink2 register. */
1922 arc_regno_reg_class
[31] = LINK_REGS
; /* blink register. */
1923 arc_regno_reg_class
[60] = LPCOUNT_REG
;
1924 arc_regno_reg_class
[61] = NO_REGS
; /* CC_REG: must be NO_REGS. */
1925 arc_regno_reg_class
[62] = GENERAL_REGS
;
1929 for (i
= 40; i
< 44; ++i
)
1931 arc_regno_reg_class
[i
] = DOUBLE_REGS
;
1933 /* Unless they want us to do 'mov d1, 0x00000000' make sure
1934 no attempt is made to use such a register as a destination
1935 operand in *movdf_insn. */
1936 if (!TARGET_ARGONAUT_SET
)
1938 /* Make sure no 'c', 'w', 'W', or 'Rac' constraint is
1939 interpreted to mean they can use D1 or D2 in their insn. */
1940 CLEAR_HARD_REG_BIT(reg_class_contents
[CHEAP_CORE_REGS
], i
);
1941 CLEAR_HARD_REG_BIT(reg_class_contents
[ALL_CORE_REGS
], i
);
1942 CLEAR_HARD_REG_BIT(reg_class_contents
[WRITABLE_CORE_REGS
], i
);
1943 CLEAR_HARD_REG_BIT(reg_class_contents
[MPY_WRITABLE_CORE_REGS
], i
);
1949 /* Disable all DOUBLE_REGISTER settings,
1950 if not generating DPFP code. */
1951 arc_regno_reg_class
[40] = ALL_REGS
;
1952 arc_regno_reg_class
[41] = ALL_REGS
;
1953 arc_regno_reg_class
[42] = ALL_REGS
;
1954 arc_regno_reg_class
[43] = ALL_REGS
;
1961 arc_hard_regno_modes
[40] = 0;
1962 arc_hard_regno_modes
[42] = 0;
1964 CLEAR_HARD_REG_SET(reg_class_contents
[DOUBLE_REGS
]);
1967 if (TARGET_SIMD_SET
)
1969 gcc_assert (ARC_FIRST_SIMD_VR_REG
== 64);
1970 gcc_assert (ARC_LAST_SIMD_VR_REG
== 127);
1972 for (i
= ARC_FIRST_SIMD_VR_REG
; i
<= ARC_LAST_SIMD_VR_REG
; i
++)
1973 arc_regno_reg_class
[i
] = SIMD_VR_REGS
;
1975 gcc_assert (ARC_FIRST_SIMD_DMA_CONFIG_REG
== 128);
1976 gcc_assert (ARC_FIRST_SIMD_DMA_CONFIG_IN_REG
== 128);
1977 gcc_assert (ARC_FIRST_SIMD_DMA_CONFIG_OUT_REG
== 136);
1978 gcc_assert (ARC_LAST_SIMD_DMA_CONFIG_REG
== 143);
1980 for (i
= ARC_FIRST_SIMD_DMA_CONFIG_REG
;
1981 i
<= ARC_LAST_SIMD_DMA_CONFIG_REG
; i
++)
1982 arc_regno_reg_class
[i
] = SIMD_DMA_CONFIG_REGS
;
1986 arc_regno_reg_class
[PROGRAM_COUNTER_REGNO
] = GENERAL_REGS
;
1988 /*ARCV2 Accumulator. */
1990 && (TARGET_FP_DP_FUSED
|| TARGET_FP_SP_FUSED
))
1991 || TARGET_PLUS_DMPY
)
1993 arc_regno_reg_class
[ACCL_REGNO
] = WRITABLE_CORE_REGS
;
1994 arc_regno_reg_class
[ACCH_REGNO
] = WRITABLE_CORE_REGS
;
1995 SET_HARD_REG_BIT (reg_class_contents
[WRITABLE_CORE_REGS
], ACCL_REGNO
);
1996 SET_HARD_REG_BIT (reg_class_contents
[WRITABLE_CORE_REGS
], ACCH_REGNO
);
1997 SET_HARD_REG_BIT (reg_class_contents
[CHEAP_CORE_REGS
], ACCL_REGNO
);
1998 SET_HARD_REG_BIT (reg_class_contents
[CHEAP_CORE_REGS
], ACCH_REGNO
);
1999 SET_HARD_REG_BIT (reg_class_contents
[GENERAL_REGS
], ACCL_REGNO
);
2000 SET_HARD_REG_BIT (reg_class_contents
[GENERAL_REGS
], ACCH_REGNO
);
2001 SET_HARD_REG_BIT (reg_class_contents
[MPY_WRITABLE_CORE_REGS
], ACCL_REGNO
);
2002 SET_HARD_REG_BIT (reg_class_contents
[MPY_WRITABLE_CORE_REGS
], ACCH_REGNO
);
2004 /* Allow the compiler to freely use them. */
2005 if (!TEST_HARD_REG_BIT (overrideregs
, ACCL_REGNO
))
2006 fixed_regs
[ACCL_REGNO
] = 0;
2007 if (!TEST_HARD_REG_BIT (overrideregs
, ACCH_REGNO
))
2008 fixed_regs
[ACCH_REGNO
] = 0;
2010 if (!fixed_regs
[ACCH_REGNO
] && !fixed_regs
[ACCL_REGNO
])
2011 arc_hard_regno_modes
[ACC_REG_FIRST
] = D_MODES
;
2015 /* Implement TARGET_HARD_REGNO_NREGS. */
2018 arc_hard_regno_nregs (unsigned int regno
, machine_mode mode
)
2020 if (GET_MODE_SIZE (mode
) == 16
2021 && regno
>= ARC_FIRST_SIMD_VR_REG
2022 && regno
<= ARC_LAST_SIMD_VR_REG
)
2025 return CEIL (GET_MODE_SIZE (mode
), UNITS_PER_WORD
);
2028 /* Implement TARGET_HARD_REGNO_MODE_OK. */
2031 arc_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
2033 return (arc_hard_regno_modes
[regno
] & arc_mode_class
[mode
]) != 0;
2036 /* Implement TARGET_MODES_TIEABLE_P. Tie QI/HI/SI modes together. */
2039 arc_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
2041 return (GET_MODE_CLASS (mode1
) == MODE_INT
2042 && GET_MODE_CLASS (mode2
) == MODE_INT
2043 && GET_MODE_SIZE (mode1
) <= UNITS_PER_WORD
2044 && GET_MODE_SIZE (mode2
) <= UNITS_PER_WORD
);
2047 /* Handle an "interrupt" attribute; arguments as in
2048 struct attribute_spec.handler. */
2051 arc_handle_interrupt_attribute (tree
*, tree name
, tree args
, int,
2056 tree value
= TREE_VALUE (args
);
2058 if (TREE_CODE (value
) != STRING_CST
)
2060 warning (OPT_Wattributes
,
2061 "argument of %qE attribute is not a string constant",
2063 *no_add_attrs
= true;
2066 && strcmp (TREE_STRING_POINTER (value
), "ilink1")
2067 && strcmp (TREE_STRING_POINTER (value
), "ilink2"))
2069 warning (OPT_Wattributes
,
2070 "argument of %qE attribute is not \"ilink1\" or \"ilink2\"",
2072 *no_add_attrs
= true;
2075 && strcmp (TREE_STRING_POINTER (value
), "ilink")
2076 && strcmp (TREE_STRING_POINTER (value
), "firq"))
2078 warning (OPT_Wattributes
,
2079 "argument of %qE attribute is not \"ilink\" or \"firq\"",
2081 *no_add_attrs
= true;
2088 arc_handle_fndecl_attribute (tree
*node
, tree name
, tree args ATTRIBUTE_UNUSED
,
2089 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
2091 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2093 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
2095 *no_add_attrs
= true;
2101 /* Implement `TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS' */
2104 arc_allocate_stack_slots_for_args (void)
2106 /* Naked functions should not allocate stack slots for arguments. */
2107 unsigned int fn_type
= arc_compute_function_type (cfun
);
2109 return !ARC_NAKED_P(fn_type
);
2112 /* Implement `TARGET_WARN_FUNC_RETURN'. */
2115 arc_warn_func_return (tree decl
)
2117 struct function
*func
= DECL_STRUCT_FUNCTION (decl
);
2118 unsigned int fn_type
= arc_compute_function_type (func
);
2120 return !ARC_NAKED_P (fn_type
);
2123 /* Return zero if TYPE1 and TYPE are incompatible, one if they are compatible,
2124 and two if they are nearly compatible (which causes a warning to be
2128 arc_comp_type_attributes (const_tree type1
,
2131 int l1
, l2
, m1
, m2
, s1
, s2
;
2133 /* Check for mismatch of non-default calling convention. */
2134 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
2137 /* Check for mismatched call attributes. */
2138 l1
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2139 l2
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2140 m1
= lookup_attribute ("medium_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2141 m2
= lookup_attribute ("medium_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2142 s1
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2143 s2
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2145 /* Only bother to check if an attribute is defined. */
2146 if (l1
| l2
| m1
| m2
| s1
| s2
)
2148 /* If one type has an attribute, the other must have the same attribute. */
2149 if ((l1
!= l2
) || (m1
!= m2
) || (s1
!= s2
))
2152 /* Disallow mixed attributes. */
2153 if (l1
+ m1
+ s1
> 1)
2161 /* Misc. utilities. */
2163 /* X and Y are two things to compare using CODE. Emit the compare insn and
2164 return the rtx for the cc reg in the proper mode. */
2167 gen_compare_reg (rtx comparison
, machine_mode omode
)
2169 enum rtx_code code
= GET_CODE (comparison
);
2170 rtx x
= XEXP (comparison
, 0);
2171 rtx y
= XEXP (comparison
, 1);
2173 machine_mode mode
, cmode
;
2176 cmode
= GET_MODE (x
);
2177 if (cmode
== VOIDmode
)
2178 cmode
= GET_MODE (y
);
2179 gcc_assert (cmode
== SImode
|| cmode
== SFmode
|| cmode
== DFmode
);
2180 if (cmode
== SImode
)
2182 if (!register_operand (x
, SImode
))
2184 if (register_operand (y
, SImode
))
2189 code
= swap_condition (code
);
2192 x
= copy_to_mode_reg (SImode
, x
);
2194 if (GET_CODE (y
) == SYMBOL_REF
&& flag_pic
)
2195 y
= copy_to_mode_reg (SImode
, y
);
2199 x
= force_reg (cmode
, x
);
2200 y
= force_reg (cmode
, y
);
2202 mode
= SELECT_CC_MODE (code
, x
, y
);
2204 cc_reg
= gen_rtx_REG (mode
, CC_REG
);
2206 /* ??? FIXME (x-y)==0, as done by both cmpsfpx_raw and
2207 cmpdfpx_raw, is not a correct comparison for floats:
2208 http://www.cygnus-software.com/papers/comparingfloats/comparingfloats.htm
2210 if (TARGET_ARGONAUT_SET
2211 && ((cmode
== SFmode
&& TARGET_SPFP
) || (cmode
== DFmode
&& TARGET_DPFP
)))
2215 case NE
: case EQ
: case LT
: case UNGE
: case LE
: case UNGT
:
2216 case UNEQ
: case LTGT
: case ORDERED
: case UNORDERED
:
2218 case GT
: case UNLE
: case GE
: case UNLT
:
2219 code
= swap_condition (code
);
2227 if (cmode
== SFmode
)
2229 emit_insn (gen_cmpsfpx_raw (x
, y
));
2233 /* Accepts Dx regs directly by insns. */
2234 emit_insn (gen_cmpdfpx_raw (x
, y
));
2237 if (mode
!= CC_FPXmode
)
2238 emit_insn (gen_rtx_SET (cc_reg
,
2239 gen_rtx_COMPARE (mode
,
2240 gen_rtx_REG (CC_FPXmode
, 61),
2243 else if (TARGET_FPX_QUARK
&& (cmode
== SFmode
))
2247 case NE
: case EQ
: case GT
: case UNLE
: case GE
: case UNLT
:
2248 case UNEQ
: case LTGT
: case ORDERED
: case UNORDERED
:
2250 case LT
: case UNGE
: case LE
: case UNGT
:
2251 code
= swap_condition (code
);
2260 emit_insn (gen_cmp_quark (cc_reg
,
2261 gen_rtx_COMPARE (mode
, x
, y
)));
2263 else if (TARGET_HARD_FLOAT
2264 && ((cmode
== SFmode
&& TARGET_FP_SP_BASE
)
2265 || (cmode
== DFmode
&& TARGET_FP_DP_BASE
)))
2266 emit_insn (gen_rtx_SET (cc_reg
, gen_rtx_COMPARE (mode
, x
, y
)));
2267 else if (GET_MODE_CLASS (cmode
) == MODE_FLOAT
&& TARGET_OPTFPE
)
2269 rtx op0
= gen_rtx_REG (cmode
, 0);
2270 rtx op1
= gen_rtx_REG (cmode
, GET_MODE_SIZE (cmode
) / UNITS_PER_WORD
);
2275 case NE
: case EQ
: case GT
: case UNLE
: case GE
: case UNLT
:
2276 case UNEQ
: case LTGT
: case ORDERED
: case UNORDERED
:
2278 case LT
: case UNGE
: case LE
: case UNGT
:
2279 code
= swap_condition (code
);
2285 if (currently_expanding_to_rtl
)
2293 emit_move_insn (op0
, x
);
2294 emit_move_insn (op1
, y
);
2298 gcc_assert (rtx_equal_p (op0
, x
));
2299 gcc_assert (rtx_equal_p (op1
, y
));
2306 emit_insn (gen_cmp_float (cc_reg
, gen_rtx_COMPARE (mode
, op0
, op1
)));
2309 emit_insn (gen_rtx_SET (cc_reg
, gen_rtx_COMPARE (mode
, x
, y
)));
2310 return gen_rtx_fmt_ee (code
, omode
, cc_reg
, const0_rtx
);
2313 /* Return true if VALUE, a const_double, will fit in a limm (4 byte number).
2314 We assume the value can be either signed or unsigned. */
2317 arc_double_limm_p (rtx value
)
2319 HOST_WIDE_INT low
, high
;
2321 gcc_assert (GET_CODE (value
) == CONST_DOUBLE
);
2326 low
= CONST_DOUBLE_LOW (value
);
2327 high
= CONST_DOUBLE_HIGH (value
);
2329 if (low
& 0x80000000)
2331 return (((unsigned HOST_WIDE_INT
) low
<= 0xffffffff && high
== 0)
2332 || (((low
& - (unsigned HOST_WIDE_INT
) 0x80000000)
2333 == - (unsigned HOST_WIDE_INT
) 0x80000000)
2338 return (unsigned HOST_WIDE_INT
) low
<= 0x7fffffff && high
== 0;
2342 /* Do any needed setup for a variadic function. For the ARC, we must
2343 create a register parameter block, and then copy any anonymous arguments
2344 in registers to memory.
2346 CUM has not been updated for the last named argument which has type TYPE
2347 and mode MODE, and we rely on this fact. */
2350 arc_setup_incoming_varargs (cumulative_args_t args_so_far
,
2351 machine_mode mode
, tree type
,
2352 int *pretend_size
, int no_rtl
)
2355 CUMULATIVE_ARGS next_cum
;
2357 /* We must treat `__builtin_va_alist' as an anonymous arg. */
2359 next_cum
= *get_cumulative_args (args_so_far
);
2360 arc_function_arg_advance (pack_cumulative_args (&next_cum
),
2362 first_anon_arg
= next_cum
;
2364 if (FUNCTION_ARG_REGNO_P (first_anon_arg
))
2366 /* First anonymous (unnamed) argument is in a reg. */
2368 /* Note that first_reg_offset < MAX_ARC_PARM_REGS. */
2369 int first_reg_offset
= first_anon_arg
;
2374 = gen_rtx_MEM (BLKmode
, plus_constant (Pmode
, arg_pointer_rtx
,
2375 FIRST_PARM_OFFSET (0)));
2376 move_block_from_reg (first_reg_offset
, regblock
,
2377 MAX_ARC_PARM_REGS
- first_reg_offset
);
2381 = ((MAX_ARC_PARM_REGS
- first_reg_offset
) * UNITS_PER_WORD
);
2385 /* Cost functions. */
2387 /* Provide the costs of an addressing mode that contains ADDR.
2388 If ADDR is not a valid address, its cost is irrelevant. */
2391 arc_address_cost (rtx addr
, machine_mode
, addr_space_t
, bool speed
)
2393 switch (GET_CODE (addr
))
2396 return speed
|| satisfies_constraint_Rcq (addr
) ? 0 : 1;
2397 case PRE_INC
: case PRE_DEC
: case POST_INC
: case POST_DEC
:
2398 case PRE_MODIFY
: case POST_MODIFY
:
2404 if (TARGET_NPS_CMEM
&& cmem_address (addr
, SImode
))
2406 /* Most likely needs a LIMM. */
2407 return COSTS_N_INSNS (1);
2411 register rtx plus0
= XEXP (addr
, 0);
2412 register rtx plus1
= XEXP (addr
, 1);
2414 if (GET_CODE (plus0
) != REG
2415 && (GET_CODE (plus0
) != MULT
2416 || !CONST_INT_P (XEXP (plus0
, 1))
2417 || (INTVAL (XEXP (plus0
, 1)) != 2
2418 && INTVAL (XEXP (plus0
, 1)) != 4)))
2421 switch (GET_CODE (plus1
))
2424 return (!RTX_OK_FOR_OFFSET_P (SImode
, plus1
)
2428 : (satisfies_constraint_Rcq (plus0
)
2429 && satisfies_constraint_O (plus1
))
2433 return (speed
< 1 ? 0
2434 : (satisfies_constraint_Rcq (plus0
)
2435 && satisfies_constraint_Rcq (plus1
))
2440 return COSTS_N_INSNS (1);
2453 /* Emit instruction X with the frame related bit set. */
2459 RTX_FRAME_RELATED_P (x
) = 1;
2463 /* Emit a frame insn to move SRC to DST. */
2466 frame_move (rtx dst
, rtx src
)
2468 rtx tmp
= gen_rtx_SET (dst
, src
);
2469 RTX_FRAME_RELATED_P (tmp
) = 1;
2470 return frame_insn (tmp
);
2473 /* Like frame_move, but add a REG_INC note for REG if ADDR contains an
2474 auto increment address, or is zero. */
2477 frame_move_inc (rtx dst
, rtx src
, rtx reg
, rtx addr
)
2479 rtx insn
= frame_move (dst
, src
);
2482 || GET_CODE (addr
) == PRE_DEC
|| GET_CODE (addr
) == POST_INC
2483 || GET_CODE (addr
) == PRE_MODIFY
|| GET_CODE (addr
) == POST_MODIFY
)
2484 add_reg_note (insn
, REG_INC
, reg
);
2488 /* Emit a frame insn which adjusts a frame address register REG by OFFSET. */
2491 frame_add (rtx reg
, HOST_WIDE_INT offset
)
2493 gcc_assert ((offset
& 0x3) == 0);
2496 return frame_move (reg
, plus_constant (Pmode
, reg
, offset
));
2499 /* Emit a frame insn which adjusts stack pointer by OFFSET. */
2502 frame_stack_add (HOST_WIDE_INT offset
)
2504 return frame_add (stack_pointer_rtx
, offset
);
2507 /* Traditionally, we push saved registers first in the prologue,
2508 then we allocate the rest of the frame - and reverse in the epilogue.
2509 This has still its merits for ease of debugging, or saving code size
2510 or even execution time if the stack frame is so large that some accesses
2511 can't be encoded anymore with offsets in the instruction code when using
2513 Also, it would be a good starting point if we got instructions to help
2514 with register save/restore.
2516 However, often stack frames are small, and the pushing / popping has
2518 - the stack modification prevents a lot of scheduling.
2519 - frame allocation / deallocation needs extra instructions.
2520 - unless we know that we compile ARC700 user code, we need to put
2521 a memory barrier after frame allocation / before deallocation to
2522 prevent interrupts clobbering our data in the frame.
2523 In particular, we don't have any such guarantees for library functions,
2524 which tend to, on the other hand, to have small frames.
2526 Thus, for small frames, we'd like to use a different scheme:
2527 - The frame is allocated in full with the first prologue instruction,
2528 and deallocated in full with the last epilogue instruction.
2529 Thus, the instructions in-betwen can be freely scheduled.
2530 - If the function has no outgoing arguments on the stack, we can allocate
2531 one register save slot at the top of the stack. This register can then
2532 be saved simultanously with frame allocation, and restored with
2534 This register can be picked depending on scheduling considerations,
2535 although same though should go into having some set of registers
2536 to be potentially lingering after a call, and others to be available
2537 immediately - i.e. in the absence of interprocedual optimization, we
2538 can use an ABI-like convention for register allocation to reduce
2539 stalls after function return. */
2540 /* Function prologue/epilogue handlers. */
2542 /* ARCompact stack frames look like:
2544 Before call After call
2545 high +-----------------------+ +-----------------------+
2546 mem | reg parm save area | | reg parm save area |
2547 | only created for | | only created for |
2548 | variable arg fns | | variable arg fns |
2549 AP +-----------------------+ +-----------------------+
2550 | return addr register | | return addr register |
2551 | (if required) | | (if required) |
2552 +-----------------------+ +-----------------------+
2554 | reg save area | | reg save area |
2556 +-----------------------+ +-----------------------+
2557 | frame pointer | | frame pointer |
2558 | (if required) | | (if required) |
2559 FP +-----------------------+ +-----------------------+
2561 | local/temp variables | | local/temp variables |
2563 +-----------------------+ +-----------------------+
2565 | arguments on stack | | arguments on stack |
2567 SP +-----------------------+ +-----------------------+
2568 | reg parm save area |
2569 | only created for |
2570 | variable arg fns |
2571 AP +-----------------------+
2572 | return addr register |
2574 +-----------------------+
2578 +-----------------------+
2581 FP +-----------------------+
2583 | local/temp variables |
2585 +-----------------------+
2587 | arguments on stack |
2589 mem SP +-----------------------+
2592 1) The "reg parm save area" does not exist for non variable argument fns.
2593 The "reg parm save area" can be eliminated completely if we created our
2594 own va-arc.h, but that has tradeoffs as well (so it's not done). */
2596 /* Structure to be filled in by arc_compute_frame_size with register
2597 save masks, and offsets for the current function. */
2598 struct GTY (()) arc_frame_info
2600 unsigned int total_size
; /* # bytes that the entire frame takes up. */
2601 unsigned int extra_size
; /* # bytes of extra stuff. */
2602 unsigned int pretend_size
; /* # bytes we push and pretend caller did. */
2603 unsigned int args_size
; /* # bytes that outgoing arguments take up. */
2604 unsigned int reg_size
; /* # bytes needed to store regs. */
2605 unsigned int var_size
; /* # bytes that variables take up. */
2606 unsigned int reg_offset
; /* Offset from new sp to store regs. */
2607 unsigned int gmask
; /* Mask of saved gp registers. */
2608 int initialized
; /* Nonzero if frame size already calculated. */
2609 short millicode_start_reg
;
2610 short millicode_end_reg
;
2611 bool save_return_addr
;
2614 /* Defining data structures for per-function information. */
2616 typedef struct GTY (()) machine_function
2618 unsigned int fn_type
;
2619 struct arc_frame_info frame_info
;
2620 /* To keep track of unalignment caused by short insns. */
2622 int force_short_suffix
; /* Used when disgorging return delay slot insns. */
2623 const char *size_reason
;
2624 struct arc_ccfsm ccfsm_current
;
2625 /* Map from uid to ccfsm state during branch shortening. */
2626 rtx ccfsm_current_insn
;
2627 char arc_reorg_started
;
2628 char prescan_initialized
;
2631 /* Type of function DECL.
2633 The result is cached. To reset the cache at the end of a function,
2634 call with DECL = NULL_TREE. */
2637 arc_compute_function_type (struct function
*fun
)
2639 tree attr
, decl
= fun
->decl
;
2640 unsigned int fn_type
= fun
->machine
->fn_type
;
2642 if (fn_type
!= ARC_FUNCTION_UNKNOWN
)
2645 /* Check if it is a naked function. */
2646 if (lookup_attribute ("naked", DECL_ATTRIBUTES (decl
)) != NULL_TREE
)
2647 fn_type
|= ARC_FUNCTION_NAKED
;
2649 fn_type
|= ARC_FUNCTION_NORMAL
;
2651 /* Now see if this is an interrupt handler. */
2652 attr
= lookup_attribute ("interrupt", DECL_ATTRIBUTES (decl
));
2653 if (attr
!= NULL_TREE
)
2655 tree value
, args
= TREE_VALUE (attr
);
2657 gcc_assert (list_length (args
) == 1);
2658 value
= TREE_VALUE (args
);
2659 gcc_assert (TREE_CODE (value
) == STRING_CST
);
2661 if (!strcmp (TREE_STRING_POINTER (value
), "ilink1")
2662 || !strcmp (TREE_STRING_POINTER (value
), "ilink"))
2663 fn_type
|= ARC_FUNCTION_ILINK1
;
2664 else if (!strcmp (TREE_STRING_POINTER (value
), "ilink2"))
2665 fn_type
|= ARC_FUNCTION_ILINK2
;
2666 else if (!strcmp (TREE_STRING_POINTER (value
), "firq"))
2667 fn_type
|= ARC_FUNCTION_FIRQ
;
2672 return fun
->machine
->fn_type
= fn_type
;
2675 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
2676 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
2678 /* Tell prologue and epilogue if register REGNO should be saved / restored.
2679 The return address and frame pointer are treated separately.
2680 Don't consider them here.
2681 Addition for pic: The gp register needs to be saved if the current
2682 function changes it to access gotoff variables.
2683 FIXME: This will not be needed if we used some arbitrary register
2687 arc_must_save_register (int regno
, struct function
*func
)
2689 unsigned int fn_type
= arc_compute_function_type (func
);
2690 bool irq_auto_save_p
= ((irq_ctrl_saved
.irq_save_last_reg
>= regno
)
2691 && ARC_AUTO_IRQ_P (fn_type
));
2692 bool firq_auto_save_p
= ARC_FAST_INTERRUPT_P (fn_type
);
2694 switch (rgf_banked_register_count
)
2697 firq_auto_save_p
&= (regno
< 4);
2700 firq_auto_save_p
&= ((regno
< 4) || ((regno
> 11) && (regno
< 16)));
2703 firq_auto_save_p
&= ((regno
< 4) || ((regno
> 9) && (regno
< 16))
2704 || ((regno
> 25) && (regno
< 29))
2705 || ((regno
> 29) && (regno
< 32)));
2708 firq_auto_save_p
&= (regno
!= 29) && (regno
< 32);
2711 firq_auto_save_p
= false;
2715 if ((regno
) != RETURN_ADDR_REGNUM
2716 && (regno
) != FRAME_POINTER_REGNUM
2717 && df_regs_ever_live_p (regno
)
2718 && (!call_used_regs
[regno
]
2719 || ARC_INTERRUPT_P (fn_type
))
2720 /* Do not emit code for auto saved regs. */
2722 && !firq_auto_save_p
)
2728 /* Return true if the return address must be saved in the current function,
2729 otherwise return false. */
2732 arc_must_save_return_addr (struct function
*func
)
2734 if (func
->machine
->frame_info
.save_return_addr
)
2740 /* Helper function to wrap FRAME_POINTER_NEEDED. We do this as
2741 FRAME_POINTER_NEEDED will not be true until the IRA (Integrated
2742 Register Allocator) pass, while we want to get the frame size
2743 correct earlier than the IRA pass.
2745 When a function uses eh_return we must ensure that the fp register
2746 is saved and then restored so that the unwinder can restore the
2747 correct value for the frame we are going to jump to.
2749 To do this we force all frames that call eh_return to require a
2750 frame pointer (see arc_frame_pointer_required), this
2751 will ensure that the previous frame pointer is stored on entry to
2752 the function, and will then be reloaded at function exit.
2754 As the frame pointer is handled as a special case in our prologue
2755 and epilogue code it must not be saved and restored using the
2756 MUST_SAVE_REGISTER mechanism otherwise we run into issues where GCC
2757 believes that the function is not using a frame pointer and that
2758 the value in the fp register is the frame pointer, while the
2759 prologue and epilogue are busy saving and restoring the fp
2762 During compilation of a function the frame size is evaluated
2763 multiple times, it is not until the reload pass is complete the the
2764 frame size is considered fixed (it is at this point that space for
2765 all spills has been allocated). However the frame_pointer_needed
2766 variable is not set true until the register allocation pass, as a
2767 result in the early stages the frame size does not include space
2768 for the frame pointer to be spilled.
2770 The problem that this causes is that the rtl generated for
2771 EH_RETURN_HANDLER_RTX uses the details of the frame size to compute
2772 the offset from the frame pointer at which the return address
2773 lives. However, in early passes GCC has not yet realised we need a
2774 frame pointer, and so has not included space for the frame pointer
2775 in the frame size, and so gets the offset of the return address
2776 wrong. This should not be an issue as in later passes GCC has
2777 realised that the frame pointer needs to be spilled, and has
2778 increased the frame size. However, the rtl for the
2779 EH_RETURN_HANDLER_RTX is not regenerated to use the newer, larger
2780 offset, and the wrong smaller offset is used. */
2783 arc_frame_pointer_needed (void)
2785 return (frame_pointer_needed
|| crtl
->calls_eh_return
);
2788 /* Return non-zero if there are registers to be saved or loaded using
2789 millicode thunks. We can only use consecutive sequences starting
2790 with r13, and not going beyond r25.
2791 GMASK is a bitmask of registers to save. This function sets
2792 FRAME->millicod_start_reg .. FRAME->millicode_end_reg to the range
2793 of registers to be saved / restored with a millicode call. */
2796 arc_compute_millicode_save_restore_regs (unsigned int gmask
,
2797 struct arc_frame_info
*frame
)
2801 int start_reg
= 13, end_reg
= 25;
2803 for (regno
= start_reg
; regno
<= end_reg
&& (gmask
& (1L << regno
));)
2805 end_reg
= regno
- 1;
2806 /* There is no point in using millicode thunks if we don't save/restore
2807 at least three registers. For non-leaf functions we also have the
2809 if (regno
- start_reg
>= 3 - (crtl
->is_leaf
== 0))
2811 frame
->millicode_start_reg
= 13;
2812 frame
->millicode_end_reg
= regno
- 1;
2818 /* Return the bytes needed to compute the frame pointer from the
2819 current stack pointer. */
2822 arc_compute_frame_size (void)
2825 unsigned int total_size
, var_size
, args_size
, pretend_size
, extra_size
;
2826 unsigned int reg_size
, reg_offset
;
2828 struct arc_frame_info
*frame_info
;
2831 /* The answer might already be known. */
2832 if (cfun
->machine
->frame_info
.initialized
)
2833 return cfun
->machine
->frame_info
.total_size
;
2835 frame_info
= &cfun
->machine
->frame_info
;
2836 size
= ARC_STACK_ALIGN (get_frame_size ());
2838 /* 1) Size of locals and temporaries. */
2841 /* 2) Size of outgoing arguments. */
2842 args_size
= crtl
->outgoing_args_size
;
2844 /* 3) Calculate space needed for saved registers.
2845 ??? We ignore the extension registers for now. */
2847 /* See if this is an interrupt handler. Call used registers must be saved
2853 for (regno
= 0; regno
<= 31; regno
++)
2855 if (arc_must_save_register (regno
, cfun
))
2857 reg_size
+= UNITS_PER_WORD
;
2858 gmask
|= 1L << regno
;
2862 /* In a frame that calls __builtin_eh_return two data registers are
2863 used to pass values back to the exception handler.
2865 Ensure that these registers are spilled to the stack so that the
2866 exception throw code can find them, and update the saved values.
2867 The handling code will then consume these reloaded values to
2868 handle the exception. */
2869 if (crtl
->calls_eh_return
)
2870 for (regno
= 0; EH_RETURN_DATA_REGNO (regno
) != INVALID_REGNUM
; regno
++)
2872 reg_size
+= UNITS_PER_WORD
;
2873 gmask
|= 1 << regno
;
2876 /* 4) Space for back trace data structure.
2877 <return addr reg size> (if required) + <fp size> (if required). */
2878 frame_info
->save_return_addr
2879 = (!crtl
->is_leaf
|| df_regs_ever_live_p (RETURN_ADDR_REGNUM
)
2880 || crtl
->calls_eh_return
);
2881 /* Saving blink reg in case of leaf function for millicode thunk calls. */
2883 && !TARGET_NO_MILLICODE_THUNK_SET
2884 && !crtl
->calls_eh_return
)
2886 if (arc_compute_millicode_save_restore_regs (gmask
, frame_info
))
2887 frame_info
->save_return_addr
= true;
2891 if (arc_must_save_return_addr (cfun
))
2893 if (arc_frame_pointer_needed ())
2896 /* 5) Space for variable arguments passed in registers */
2897 pretend_size
= crtl
->args
.pretend_args_size
;
2899 /* Ensure everything before the locals is aligned appropriately. */
2901 unsigned int extra_plus_reg_size
;
2902 unsigned int extra_plus_reg_size_aligned
;
2904 extra_plus_reg_size
= extra_size
+ reg_size
;
2905 extra_plus_reg_size_aligned
= ARC_STACK_ALIGN(extra_plus_reg_size
);
2906 reg_size
= extra_plus_reg_size_aligned
- extra_size
;
2909 /* Compute total frame size. */
2910 total_size
= var_size
+ args_size
+ extra_size
+ pretend_size
+ reg_size
;
2912 /* It used to be the case that the alignment was forced at this
2913 point. However, that is dangerous, calculations based on
2914 total_size would be wrong. Given that this has never cropped up
2915 as an issue I've changed this to an assert for now. */
2916 gcc_assert (total_size
== ARC_STACK_ALIGN (total_size
));
2918 /* Compute offset of register save area from stack pointer:
2919 Frame: pretend_size <blink> reg_size <fp> var_size args_size <--sp
2921 reg_offset
= (total_size
- (pretend_size
+ reg_size
+ extra_size
)
2922 + (arc_frame_pointer_needed () ? 4 : 0));
2924 /* Save computed information. */
2925 frame_info
->total_size
= total_size
;
2926 frame_info
->extra_size
= extra_size
;
2927 frame_info
->pretend_size
= pretend_size
;
2928 frame_info
->var_size
= var_size
;
2929 frame_info
->args_size
= args_size
;
2930 frame_info
->reg_size
= reg_size
;
2931 frame_info
->reg_offset
= reg_offset
;
2932 frame_info
->gmask
= gmask
;
2933 frame_info
->initialized
= reload_completed
;
2935 /* Ok, we're done. */
2939 /* Common code to save/restore registers. */
2940 /* BASE_REG is the base register to use for addressing and to adjust.
2941 GMASK is a bitmask of general purpose registers to save/restore.
2942 epilogue_p 0: prologue 1:epilogue 2:epilogue, sibling thunk
2943 If *FIRST_OFFSET is non-zero, add it first to BASE_REG - preferably
2944 using a pre-modify for the first memory access. *FIRST_OFFSET is then
2948 arc_save_restore (rtx base_reg
,
2949 unsigned int gmask
, int epilogue_p
, int *first_offset
)
2951 unsigned int offset
= 0;
2953 struct arc_frame_info
*frame
= &cfun
->machine
->frame_info
;
2954 rtx sibthunk_insn
= NULL_RTX
;
2958 /* Millicode thunks implementation:
2959 Generates calls to millicodes for registers starting from r13 to r25
2960 Present Limitations:
2961 - Only one range supported. The remaining regs will have the ordinary
2962 st and ld instructions for store and loads. Hence a gmask asking
2963 to store r13-14, r16-r25 will only generate calls to store and
2964 load r13 to r14 while store and load insns will be generated for
2965 r16 to r25 in the prologue and epilogue respectively.
2967 - Presently library only supports register ranges starting from r13.
2969 if (epilogue_p
== 2 || frame
->millicode_end_reg
> 14)
2971 int start_call
= frame
->millicode_start_reg
;
2972 int end_call
= frame
->millicode_end_reg
;
2973 int n_regs
= end_call
- start_call
+ 1;
2974 int i
= 0, r
, off
= 0;
2976 rtx ret_addr
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
2980 /* "reg_size" won't be more than 127 . */
2981 gcc_assert (epilogue_p
|| abs (*first_offset
) <= 127);
2982 frame_add (base_reg
, *first_offset
);
2985 insn
= gen_rtx_PARALLEL
2986 (VOIDmode
, rtvec_alloc ((epilogue_p
== 2) + n_regs
+ 1));
2987 if (epilogue_p
== 2)
2990 XVECEXP (insn
, 0, n_regs
) = gen_rtx_CLOBBER (VOIDmode
, ret_addr
);
2991 for (r
= start_call
; r
<= end_call
; r
++, off
+= UNITS_PER_WORD
, i
++)
2993 rtx reg
= gen_rtx_REG (SImode
, r
);
2995 = gen_frame_mem (SImode
, plus_constant (Pmode
, base_reg
, off
));
2998 XVECEXP (insn
, 0, i
) = gen_rtx_SET (reg
, mem
);
3000 XVECEXP (insn
, 0, i
) = gen_rtx_SET (mem
, reg
);
3001 gmask
= gmask
& ~(1L << r
);
3003 if (epilogue_p
== 2)
3004 sibthunk_insn
= insn
;
3007 insn
= frame_insn (insn
);
3008 for (r
= start_call
, off
= 0;
3010 r
++, off
+= UNITS_PER_WORD
)
3012 rtx reg
= gen_rtx_REG (SImode
, r
);
3014 add_reg_note (insn
, REG_CFA_RESTORE
, reg
);
3017 rtx mem
= gen_rtx_MEM (SImode
, plus_constant (Pmode
,
3021 add_reg_note (insn
, REG_CFA_OFFSET
,
3022 gen_rtx_SET (mem
, reg
));
3029 for (regno
= 0; regno
<= 31; regno
++)
3031 machine_mode mode
= SImode
;
3036 && ((gmask
& (1L << regno
)) != 0)
3037 && ((gmask
& (1L << (regno
+1))) != 0))
3042 else if ((gmask
& (1L << regno
)) != 0)
3050 rtx reg
= gen_rtx_REG (mode
, regno
);
3052 int cfa_adjust
= *first_offset
;
3056 gcc_assert (!offset
);
3057 addr
= plus_constant (Pmode
, base_reg
, *first_offset
);
3058 addr
= gen_rtx_PRE_MODIFY (Pmode
, base_reg
, addr
);
3063 gcc_assert (SMALL_INT (offset
));
3064 addr
= plus_constant (Pmode
, base_reg
, offset
);
3066 mem
= gen_frame_mem (mode
, addr
);
3070 frame_move_inc (reg
, mem
, base_reg
, addr
);
3071 add_reg_note (insn
, REG_CFA_RESTORE
, reg
);
3074 enum reg_note note
= REG_CFA_ADJUST_CFA
;
3075 add_reg_note (insn
, note
,
3076 gen_rtx_SET (stack_pointer_rtx
,
3077 plus_constant (Pmode
,
3083 frame_move_inc (mem
, reg
, base_reg
, addr
);
3084 offset
+= UNITS_PER_WORD
;
3087 offset
+= UNITS_PER_WORD
;
3095 int start_call
= frame
->millicode_start_reg
;
3096 int end_call
= frame
->millicode_end_reg
;
3099 rtx r12
= gen_rtx_REG (Pmode
, 12);
3101 frame_insn (gen_rtx_SET (r12
, GEN_INT (offset
)));
3102 XVECEXP (sibthunk_insn
, 0, 0) = ret_rtx
;
3103 XVECEXP (sibthunk_insn
, 0, 1)
3104 = gen_rtx_SET (stack_pointer_rtx
,
3105 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, r12
));
3106 sibthunk_insn
= emit_jump_insn (sibthunk_insn
);
3107 RTX_FRAME_RELATED_P (sibthunk_insn
) = 1;
3109 /* Would be nice if we could do this earlier, when the PARALLEL
3110 is populated, but these need to be attached after the
3112 for (r
= start_call
; r
<= end_call
; r
++)
3114 rtx reg
= gen_rtx_REG (SImode
, r
);
3115 add_reg_note (sibthunk_insn
, REG_CFA_RESTORE
, reg
);
3118 } /* arc_save_restore */
3120 /* Build dwarf information when the context is saved via AUX_IRQ_CTRL
3124 arc_dwarf_emit_irq_save_regs (void)
3126 rtx tmp
, par
, insn
, reg
;
3129 par
= gen_rtx_SEQUENCE (VOIDmode
,
3130 rtvec_alloc (irq_ctrl_saved
.irq_save_last_reg
+ 1
3131 + irq_ctrl_saved
.irq_save_blink
3132 + irq_ctrl_saved
.irq_save_lpcount
3135 /* Build the stack adjustment note for unwind info. */
3137 offset
= UNITS_PER_WORD
* (irq_ctrl_saved
.irq_save_last_reg
+ 1
3138 + irq_ctrl_saved
.irq_save_blink
3139 + irq_ctrl_saved
.irq_save_lpcount
);
3140 tmp
= plus_constant (Pmode
, stack_pointer_rtx
, -1 * offset
);
3141 tmp
= gen_rtx_SET (stack_pointer_rtx
, tmp
);
3142 RTX_FRAME_RELATED_P (tmp
) = 1;
3143 XVECEXP (par
, 0, j
++) = tmp
;
3145 offset
-= UNITS_PER_WORD
;
3147 /* 1st goes LP_COUNT. */
3148 if (irq_ctrl_saved
.irq_save_lpcount
)
3150 reg
= gen_rtx_REG (SImode
, 60);
3151 tmp
= plus_constant (Pmode
, stack_pointer_rtx
, offset
);
3152 tmp
= gen_frame_mem (SImode
, tmp
);
3153 tmp
= gen_rtx_SET (tmp
, reg
);
3154 RTX_FRAME_RELATED_P (tmp
) = 1;
3155 XVECEXP (par
, 0, j
++) = tmp
;
3156 offset
-= UNITS_PER_WORD
;
3159 /* 2nd goes BLINK. */
3160 if (irq_ctrl_saved
.irq_save_blink
)
3162 reg
= gen_rtx_REG (SImode
, 31);
3163 tmp
= plus_constant (Pmode
, stack_pointer_rtx
, offset
);
3164 tmp
= gen_frame_mem (SImode
, tmp
);
3165 tmp
= gen_rtx_SET (tmp
, reg
);
3166 RTX_FRAME_RELATED_P (tmp
) = 1;
3167 XVECEXP (par
, 0, j
++) = tmp
;
3168 offset
-= UNITS_PER_WORD
;
3171 /* Build the parallel of the remaining registers recorded as saved
3173 for (i
= irq_ctrl_saved
.irq_save_last_reg
; i
>= 0; i
--)
3175 reg
= gen_rtx_REG (SImode
, i
);
3176 tmp
= plus_constant (Pmode
, stack_pointer_rtx
, offset
);
3177 tmp
= gen_frame_mem (SImode
, tmp
);
3178 tmp
= gen_rtx_SET (tmp
, reg
);
3179 RTX_FRAME_RELATED_P (tmp
) = 1;
3180 XVECEXP (par
, 0, j
++) = tmp
;
3181 offset
-= UNITS_PER_WORD
;
3184 /* Dummy insn used to anchor the dwarf info. */
3185 insn
= emit_insn (gen_stack_irq_dwarf());
3186 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, par
);
3187 RTX_FRAME_RELATED_P (insn
) = 1;
3190 /* Set up the stack and frame pointer (if desired) for the function. */
3193 arc_expand_prologue (void)
3196 unsigned int gmask
= cfun
->machine
->frame_info
.gmask
;
3197 /* unsigned int frame_pointer_offset;*/
3198 unsigned int frame_size_to_allocate
;
3199 /* (FIXME: The first store will use a PRE_MODIFY; this will usually be r13.
3200 Change the stack layout so that we rather store a high register with the
3201 PRE_MODIFY, thus enabling more short insn generation.) */
3202 int first_offset
= 0;
3203 unsigned int fn_type
= arc_compute_function_type (cfun
);
3205 /* Naked functions don't have prologue. */
3206 if (ARC_NAKED_P (fn_type
))
3208 if (flag_stack_usage_info
)
3209 current_function_static_stack_size
= 0;
3213 /* Compute total frame size. */
3214 size
= arc_compute_frame_size ();
3216 if (flag_stack_usage_info
)
3217 current_function_static_stack_size
= size
;
3219 /* Keep track of frame size to be allocated. */
3220 frame_size_to_allocate
= size
;
3222 /* These cases shouldn't happen. Catch them now. */
3223 gcc_assert (!(size
== 0 && gmask
));
3225 /* Allocate space for register arguments if this is a variadic function. */
3226 if (cfun
->machine
->frame_info
.pretend_size
!= 0)
3228 /* Ensure pretend_size is maximum of 8 * word_size. */
3229 gcc_assert (cfun
->machine
->frame_info
.pretend_size
<= 32);
3231 frame_stack_add (-(HOST_WIDE_INT
)cfun
->machine
->frame_info
.pretend_size
);
3232 frame_size_to_allocate
-= cfun
->machine
->frame_info
.pretend_size
;
3235 /* IRQ using automatic save mechanism will save the register before
3237 if (ARC_AUTO_IRQ_P (fn_type
)
3238 && !ARC_FAST_INTERRUPT_P (fn_type
))
3240 arc_dwarf_emit_irq_save_regs ();
3243 /* The home-grown ABI says link register is saved first. */
3244 if (arc_must_save_return_addr (cfun
)
3245 && !ARC_AUTOBLINK_IRQ_P (fn_type
))
3247 rtx ra
= gen_rtx_REG (SImode
, RETURN_ADDR_REGNUM
);
3248 rtx mem
= gen_frame_mem (Pmode
,
3249 gen_rtx_PRE_DEC (Pmode
,
3250 stack_pointer_rtx
));
3252 frame_move_inc (mem
, ra
, stack_pointer_rtx
, 0);
3253 frame_size_to_allocate
-= UNITS_PER_WORD
;
3256 /* Save any needed call-saved regs (and call-used if this is an
3257 interrupt handler) for ARCompact ISA. */
3258 if (cfun
->machine
->frame_info
.reg_size
)
3260 first_offset
= -cfun
->machine
->frame_info
.reg_size
;
3261 /* N.B. FRAME_POINTER_MASK and RETURN_ADDR_MASK are cleared in gmask. */
3262 arc_save_restore (stack_pointer_rtx
, gmask
, 0, &first_offset
);
3263 frame_size_to_allocate
-= cfun
->machine
->frame_info
.reg_size
;
3266 /* In the case of millicode thunk, we need to restore the clobbered
3268 if (cfun
->machine
->frame_info
.millicode_end_reg
> 0
3269 && arc_must_save_return_addr (cfun
))
3271 HOST_WIDE_INT tmp
= cfun
->machine
->frame_info
.reg_size
;
3272 emit_insn (gen_rtx_SET (gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
),
3274 plus_constant (Pmode
,
3279 /* Save frame pointer if needed. First save the FP on stack, if not
3281 if (arc_frame_pointer_needed ()
3282 && !ARC_AUTOFP_IRQ_P (fn_type
))
3284 rtx addr
= gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
3285 GEN_INT (-UNITS_PER_WORD
+ first_offset
));
3286 rtx mem
= gen_frame_mem (Pmode
, gen_rtx_PRE_MODIFY (Pmode
,
3289 frame_move_inc (mem
, frame_pointer_rtx
, stack_pointer_rtx
, 0);
3290 frame_size_to_allocate
-= UNITS_PER_WORD
;
3294 /* Emit mov fp,sp. */
3295 if (arc_frame_pointer_needed ())
3297 frame_move (frame_pointer_rtx
, stack_pointer_rtx
);
3300 /* ??? We don't handle the case where the saved regs are more than 252
3301 bytes away from sp. This can be handled by decrementing sp once, saving
3302 the regs, and then decrementing it again. The epilogue doesn't have this
3303 problem as the `ld' insn takes reg+limm values (though it would be more
3304 efficient to avoid reg+limm). */
3306 frame_size_to_allocate
-= first_offset
;
3307 /* Allocate the stack frame. */
3308 if (frame_size_to_allocate
> 0)
3310 frame_stack_add ((HOST_WIDE_INT
) 0 - frame_size_to_allocate
);
3311 /* If the frame pointer is needed, emit a special barrier that
3312 will prevent the scheduler from moving stores to the frame
3313 before the stack adjustment. */
3314 if (arc_frame_pointer_needed ())
3315 emit_insn (gen_stack_tie (stack_pointer_rtx
,
3316 hard_frame_pointer_rtx
));
3320 /* Do any necessary cleanup after a function to restore stack, frame,
3324 arc_expand_epilogue (int sibcall_p
)
3327 unsigned int fn_type
= arc_compute_function_type (cfun
);
3329 size
= arc_compute_frame_size ();
3331 unsigned int pretend_size
= cfun
->machine
->frame_info
.pretend_size
;
3332 unsigned int frame_size
;
3333 unsigned int size_to_deallocate
;
3335 int can_trust_sp_p
= !cfun
->calls_alloca
;
3336 int first_offset
= 0;
3337 int millicode_p
= cfun
->machine
->frame_info
.millicode_end_reg
> 0;
3340 /* Naked functions don't have epilogue. */
3341 if (ARC_NAKED_P (fn_type
))
3344 size_to_deallocate
= size
;
3346 frame_size
= size
- (pretend_size
+
3347 cfun
->machine
->frame_info
.reg_size
+
3348 cfun
->machine
->frame_info
.extra_size
);
3350 /* ??? There are lots of optimizations that can be done here.
3351 EG: Use fp to restore regs if it's closer.
3352 Maybe in time we'll do them all. For now, always restore regs from
3353 sp, but don't restore sp if we don't have to. */
3355 if (!can_trust_sp_p
)
3356 gcc_assert (arc_frame_pointer_needed ());
3358 /* Restore stack pointer to the beginning of saved register area for
3362 if (arc_frame_pointer_needed ())
3363 frame_move (stack_pointer_rtx
, frame_pointer_rtx
);
3365 first_offset
= frame_size
;
3366 size_to_deallocate
-= frame_size
;
3368 else if (!can_trust_sp_p
)
3369 frame_stack_add (-frame_size
);
3372 /* Restore any saved registers. */
3373 if (arc_frame_pointer_needed ()
3374 && !ARC_AUTOFP_IRQ_P (fn_type
))
3376 rtx addr
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
3378 insn
= frame_move_inc (frame_pointer_rtx
, gen_frame_mem (Pmode
, addr
),
3379 stack_pointer_rtx
, 0);
3380 add_reg_note (insn
, REG_CFA_RESTORE
, frame_pointer_rtx
);
3381 add_reg_note (insn
, REG_CFA_DEF_CFA
,
3382 plus_constant (SImode
, stack_pointer_rtx
,
3384 size_to_deallocate
-= UNITS_PER_WORD
;
3387 /* Load blink after the calls to thunk calls in case of optimize size. */
3390 int sibthunk_p
= (!sibcall_p
3391 && fn_type
== ARC_FUNCTION_NORMAL
3392 && !cfun
->machine
->frame_info
.pretend_size
);
3394 gcc_assert (!(cfun
->machine
->frame_info
.gmask
3395 & (FRAME_POINTER_MASK
| RETURN_ADDR_MASK
)));
3396 arc_save_restore (stack_pointer_rtx
,
3397 cfun
->machine
->frame_info
.gmask
,
3398 1 + sibthunk_p
, &first_offset
);
3402 /* If we are to restore registers, and first_offset would require
3403 a limm to be encoded in a PRE_MODIFY, yet we can add it with a
3404 fast add to the stack pointer, do this now. */
3405 if ((!SMALL_INT (first_offset
)
3406 && cfun
->machine
->frame_info
.gmask
3407 && ((TARGET_ARC700
&& !optimize_size
)
3408 ? first_offset
<= 0x800
3409 : satisfies_constraint_C2a (GEN_INT (first_offset
))))
3410 /* Also do this if we have both gprs and return
3411 address to restore, and they both would need a LIMM. */
3412 || (arc_must_save_return_addr (cfun
)
3413 && !SMALL_INT ((cfun
->machine
->frame_info
.reg_size
+ first_offset
) >> 2)
3414 && cfun
->machine
->frame_info
.gmask
))
3416 frame_stack_add (first_offset
);
3419 if (arc_must_save_return_addr (cfun
)
3420 && !ARC_AUTOBLINK_IRQ_P (fn_type
))
3422 rtx ra
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
3423 int ra_offs
= cfun
->machine
->frame_info
.reg_size
+ first_offset
;
3424 rtx addr
= plus_constant (Pmode
, stack_pointer_rtx
, ra_offs
);
3425 HOST_WIDE_INT cfa_adjust
= 0;
3427 /* If the load of blink would need a LIMM, but we can add
3428 the offset quickly to sp, do the latter. */
3429 if (!SMALL_INT (ra_offs
>> 2)
3430 && !cfun
->machine
->frame_info
.gmask
3431 && ((TARGET_ARC700
&& !optimize_size
)
3433 : satisfies_constraint_C2a (GEN_INT (ra_offs
))))
3435 size_to_deallocate
-= ra_offs
- first_offset
;
3437 frame_stack_add (ra_offs
);
3439 addr
= stack_pointer_rtx
;
3441 /* See if we can combine the load of the return address with the
3442 final stack adjustment.
3443 We need a separate load if there are still registers to
3444 restore. We also want a separate load if the combined insn
3445 would need a limm, but a separate load doesn't. */
3447 && !cfun
->machine
->frame_info
.gmask
3448 && (SMALL_INT (ra_offs
) || !SMALL_INT (ra_offs
>> 2)))
3450 addr
= gen_rtx_PRE_MODIFY (Pmode
, stack_pointer_rtx
, addr
);
3451 cfa_adjust
= ra_offs
;
3453 size_to_deallocate
-= cfun
->machine
->frame_info
.reg_size
;
3455 else if (!ra_offs
&& size_to_deallocate
== UNITS_PER_WORD
)
3457 addr
= gen_rtx_POST_INC (Pmode
, addr
);
3458 cfa_adjust
= GET_MODE_SIZE (Pmode
);
3459 size_to_deallocate
= 0;
3462 insn
= frame_move_inc (ra
, gen_frame_mem (Pmode
, addr
),
3463 stack_pointer_rtx
, addr
);
3466 enum reg_note note
= REG_CFA_ADJUST_CFA
;
3468 add_reg_note (insn
, note
,
3469 gen_rtx_SET (stack_pointer_rtx
,
3470 plus_constant (SImode
, stack_pointer_rtx
,
3473 add_reg_note (insn
, REG_CFA_RESTORE
, ra
);
3478 if (cfun
->machine
->frame_info
.reg_size
)
3479 arc_save_restore (stack_pointer_rtx
,
3480 /* The zeroing of these two bits is unnecessary, but leave this in for clarity. */
3481 cfun
->machine
->frame_info
.gmask
3482 & ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
), 1, &first_offset
);
3485 /* The rest of this function does the following:
3486 ARCompact : handle epilogue_delay, restore sp (phase-2), return
3489 /* Keep track of how much of the stack pointer we've restored.
3490 It makes the following a lot more readable. */
3491 size_to_deallocate
+= first_offset
;
3492 restored
= size
- size_to_deallocate
;
3494 if (size
> restored
)
3495 frame_stack_add (size
- restored
);
3497 /* For frames that use __builtin_eh_return, the register defined by
3498 EH_RETURN_STACKADJ_RTX is set to 0 for all standard return paths.
3499 On eh_return paths however, the register is set to the value that
3500 should be added to the stack pointer in order to restore the
3501 correct stack pointer for the exception handling frame.
3503 For ARC we are going to use r2 for EH_RETURN_STACKADJ_RTX, add
3504 this onto the stack for eh_return frames. */
3505 if (crtl
->calls_eh_return
)
3506 emit_insn (gen_add2_insn (stack_pointer_rtx
,
3507 EH_RETURN_STACKADJ_RTX
));
3509 /* Emit the return instruction. */
3510 if (sibcall_p
== FALSE
)
3511 emit_jump_insn (gen_simple_return ());
3514 /* Return rtx for the location of the return address on the stack,
3515 suitable for use in __builtin_eh_return. The new return address
3516 will be written to this location in order to redirect the return to
3517 the exception handler. */
3520 arc_eh_return_address_location (void)
3524 struct arc_frame_info
*afi
;
3526 arc_compute_frame_size ();
3527 afi
= &cfun
->machine
->frame_info
;
3529 gcc_assert (crtl
->calls_eh_return
);
3530 gcc_assert (afi
->save_return_addr
);
3531 gcc_assert (afi
->extra_size
>= 4);
3533 /* The '-4' removes the size of the return address, which is
3534 included in the 'extra_size' field. */
3535 offset
= afi
->reg_size
+ afi
->extra_size
- 4;
3536 mem
= gen_frame_mem (Pmode
,
3537 plus_constant (Pmode
, frame_pointer_rtx
, offset
));
3539 /* The following should not be needed, and is, really a hack. The
3540 issue being worked around here is that the DSE (Dead Store
3541 Elimination) pass will remove this write to the stack as it sees
3542 a single store and no corresponding read. The read however
3543 occurs in the epilogue code, which is not added into the function
3544 rtl until a later pass. So, at the time of DSE, the decision to
3545 remove this store seems perfectly sensible. Marking the memory
3546 address as volatile obviously has the effect of preventing DSE
3547 from removing the store. */
3548 MEM_VOLATILE_P (mem
) = 1;
3554 /* Helper to generate unspec constant. */
3557 arc_unspec_offset (rtx loc
, int unspec
)
3559 return gen_rtx_CONST (Pmode
, gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, loc
),
3563 /* !TARGET_BARREL_SHIFTER support. */
3564 /* Emit a shift insn to set OP0 to OP1 shifted by OP2; CODE specifies what
3568 emit_shift (enum rtx_code code
, rtx op0
, rtx op1
, rtx op2
)
3570 rtx shift
= gen_rtx_fmt_ee (code
, SImode
, op1
, op2
);
3572 = ((shift4_operator (shift
, SImode
) ? gen_shift_si3
: gen_shift_si3_loop
)
3573 (op0
, op1
, op2
, shift
));
3577 /* Output the assembler code for doing a shift.
3578 We go to a bit of trouble to generate efficient code as the ARC601 only has
3579 single bit shifts. This is taken from the h8300 port. We only have one
3580 mode of shifting and can't access individual bytes like the h8300 can, so
3581 this is greatly simplified (at the expense of not generating hyper-
3584 This function is not used if the variable shift insns are present. */
3586 /* FIXME: This probably can be done using a define_split in arc.md.
3587 Alternately, generate rtx rather than output instructions. */
3590 output_shift (rtx
*operands
)
3592 /* static int loopend_lab;*/
3593 rtx shift
= operands
[3];
3594 machine_mode mode
= GET_MODE (shift
);
3595 enum rtx_code code
= GET_CODE (shift
);
3596 const char *shift_one
;
3598 gcc_assert (mode
== SImode
);
3602 case ASHIFT
: shift_one
= "add %0,%1,%1"; break;
3603 case ASHIFTRT
: shift_one
= "asr %0,%1"; break;
3604 case LSHIFTRT
: shift_one
= "lsr %0,%1"; break;
3605 default: gcc_unreachable ();
3608 if (GET_CODE (operands
[2]) != CONST_INT
)
3610 output_asm_insn ("and.f lp_count,%2, 0x1f", operands
);
3617 n
= INTVAL (operands
[2]);
3619 /* Only consider the lower 5 bits of the shift count. */
3622 /* First see if we can do them inline. */
3623 /* ??? We could get better scheduling & shorter code (using short insns)
3624 by using splitters. Alas, that'd be even more verbose. */
3625 if (code
== ASHIFT
&& n
<= 9 && n
> 2
3626 && dest_reg_operand (operands
[4], SImode
))
3628 output_asm_insn ("mov %4,0\n\tadd3 %0,%4,%1", operands
);
3629 for (n
-=3 ; n
>= 3; n
-= 3)
3630 output_asm_insn ("add3 %0,%4,%0", operands
);
3632 output_asm_insn ("add2 %0,%4,%0", operands
);
3634 output_asm_insn ("add %0,%0,%0", operands
);
3640 output_asm_insn (shift_one
, operands
);
3641 operands
[1] = operands
[0];
3644 /* See if we can use a rotate/and. */
3645 else if (n
== BITS_PER_WORD
- 1)
3650 output_asm_insn ("and %0,%1,1\n\tror %0,%0", operands
);
3653 /* The ARC doesn't have a rol insn. Use something else. */
3654 output_asm_insn ("add.f 0,%1,%1\n\tsbc %0,%0,%0", operands
);
3657 /* The ARC doesn't have a rol insn. Use something else. */
3658 output_asm_insn ("add.f 0,%1,%1\n\trlc %0,0", operands
);
3664 else if (n
== BITS_PER_WORD
- 2 && dest_reg_operand (operands
[4], SImode
))
3669 output_asm_insn ("and %0,%1,3\n\tror %0,%0\n\tror %0,%0", operands
);
3672 #if 1 /* Need some scheduling comparisons. */
3673 output_asm_insn ("add.f %4,%1,%1\n\tsbc %0,%0,%0\n\t"
3674 "add.f 0,%4,%4\n\trlc %0,%0", operands
);
3676 output_asm_insn ("add.f %4,%1,%1\n\tbxor %0,%4,31\n\t"
3677 "sbc.f %0,%0,%4\n\trlc %0,%0", operands
);
3682 output_asm_insn ("add.f %4,%1,%1\n\trlc %0,0\n\t"
3683 "add.f 0,%4,%4\n\trlc %0,%0", operands
);
3685 output_asm_insn ("add.f %0,%1,%1\n\trlc.f %0,0\n\t"
3686 "and %0,%0,1\n\trlc %0,%0", operands
);
3693 else if (n
== BITS_PER_WORD
- 3 && code
== ASHIFT
)
3694 output_asm_insn ("and %0,%1,7\n\tror %0,%0\n\tror %0,%0\n\tror %0,%0",
3699 operands
[2] = GEN_INT (n
);
3700 output_asm_insn ("mov.f lp_count, %2", operands
);
3704 output_asm_insn ("lpnz\t2f", operands
);
3705 output_asm_insn (shift_one
, operands
);
3706 output_asm_insn ("nop", operands
);
3707 fprintf (asm_out_file
, "2:\t%s end single insn loop\n",
3716 /* Nested function support. */
3718 /* Output assembler code for a block containing the constant parts of
3719 a trampoline, leaving space for variable parts. A trampoline looks
3725 .word function's address
3726 .word static chain value
3731 arc_asm_trampoline_template (FILE *f
)
3733 asm_fprintf (f
, "\tld_s\t%s,[pcl,8]\n", ARC_TEMP_SCRATCH_REG
);
3734 asm_fprintf (f
, "\tld\t%s,[pcl,12]\n", reg_names
[STATIC_CHAIN_REGNUM
]);
3735 asm_fprintf (f
, "\tj_s\t[%s]\n", ARC_TEMP_SCRATCH_REG
);
3736 assemble_aligned_integer (UNITS_PER_WORD
, const0_rtx
);
3737 assemble_aligned_integer (UNITS_PER_WORD
, const0_rtx
);
3740 /* Emit RTL insns to initialize the variable parts of a trampoline.
3741 FNADDR is an RTX for the address of the function's pure code. CXT
3742 is an RTX for the static chain value for the function.
3744 The fastest trampoline to execute for trampolines within +-8KB of CTX
3748 j [limm] 0x20200f80 limm
3750 and that would also be faster to write to the stack by computing
3751 the offset from CTX to TRAMP at compile time. However, it would
3752 really be better to get rid of the high cost of cache invalidation
3753 when generating trampolines, which requires that the code part of
3754 trampolines stays constant, and additionally either making sure
3755 that no executable code but trampolines is on the stack, no icache
3756 entries linger for the area of the stack from when before the stack
3757 was allocated, and allocating trampolines in trampoline-only cache
3758 lines or allocate trampolines fram a special pool of pre-allocated
3762 arc_initialize_trampoline (rtx tramp
, tree fndecl
, rtx cxt
)
3764 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
3766 emit_block_move (tramp
, assemble_trampoline_template (),
3767 GEN_INT (TRAMPOLINE_SIZE
), BLOCK_OP_NORMAL
);
3768 emit_move_insn (adjust_address (tramp
, SImode
, 8), fnaddr
);
3769 emit_move_insn (adjust_address (tramp
, SImode
, 12), cxt
);
3770 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__clear_cache"),
3771 LCT_NORMAL
, VOIDmode
, XEXP (tramp
, 0), Pmode
,
3772 plus_constant (Pmode
, XEXP (tramp
, 0), TRAMPOLINE_SIZE
),
3776 /* Add the given function declaration to emit code in JLI section. */
3779 arc_add_jli_section (rtx pat
)
3783 arc_jli_section
*sec
= arc_jli_sections
, *new_section
;
3784 tree decl
= SYMBOL_REF_DECL (pat
);
3791 /* For fixed locations do not generate the jli table entry. It
3792 should be provided by the user as an asm file. */
3793 attrs
= TYPE_ATTRIBUTES (TREE_TYPE (decl
));
3794 if (lookup_attribute ("jli_fixed", attrs
))
3798 name
= XSTR (pat
, 0);
3800 /* Don't insert the same symbol twice. */
3803 if(strcmp (name
, sec
->name
) == 0)
3808 /* New name, insert it. */
3809 new_section
= (arc_jli_section
*) xmalloc (sizeof (arc_jli_section
));
3810 gcc_assert (new_section
!= NULL
);
3811 new_section
->name
= name
;
3812 new_section
->next
= arc_jli_sections
;
3813 arc_jli_sections
= new_section
;
3816 /* This is set briefly to 1 when we output a ".as" address modifer, and then
3817 reset when we output the scaled address. */
3818 static int output_scaled
= 0;
3820 /* Set when we force sdata output. */
3821 static int output_sdata
= 0;
3823 /* Print operand X (an rtx) in assembler syntax to file FILE.
3824 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3825 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3826 /* In final.c:output_asm_insn:
3829 'c' : constant address if CONSTANT_ADDRESS_P
3835 'p': bit Position of lsb
3836 's': size of bit field
3837 '#': condbranch delay slot suffix
3838 '*': jump delay slot suffix
3839 '?' : nonjump-insn suffix for conditional execution or short instruction
3840 '!' : jump / call suffix for conditional execution or short instruction
3841 '`': fold constant inside unary o-perator, re-recognize, and emit.
3845 'S': JLI instruction
3846 'j': used by mov instruction to properly emit jli related labels.
3847 'B': Branch comparison operand - suppress sda reference
3848 'H': Most significant word
3849 'L': Least significant word
3850 'A': ASCII decimal representation of floating point value
3851 'U': Load/store update or scaling indicator
3852 'V': cache bypass indicator for volatile
3857 'o': original symbol - no @ prepending. */
3860 arc_print_operand (FILE *file
, rtx x
, int code
)
3865 if (GET_CODE (x
) == CONST_INT
)
3866 fprintf (file
, "%d",exact_log2(INTVAL (x
) + 1) - 1 );
3868 output_operand_lossage ("invalid operand to %%Z code");
3873 if (GET_CODE (x
) == CONST_INT
)
3874 fprintf (file
, "%d",exact_log2(INTVAL (x
)) );
3876 output_operand_lossage ("invalid operand to %%z code");
3881 if (GET_CODE (x
) == CONST_INT
)
3882 fprintf (file
, "%ld", INTVAL (x
) );
3884 output_operand_lossage ("invalid operands to %%c code");
3889 if (GET_CODE (x
) == CONST_INT
)
3890 fprintf (file
, "%d",exact_log2(~INTVAL (x
)) );
3892 output_operand_lossage ("invalid operand to %%M code");
3897 if (GET_CODE (x
) == CONST_INT
)
3898 fprintf (file
, "%d", exact_log2 (INTVAL (x
) & -INTVAL (x
)));
3900 output_operand_lossage ("invalid operand to %%p code");
3904 if (GET_CODE (x
) == CONST_INT
)
3906 HOST_WIDE_INT i
= INTVAL (x
);
3907 HOST_WIDE_INT s
= exact_log2 (i
& -i
);
3908 fprintf (file
, "%d", exact_log2 (((0xffffffffUL
& i
) >> s
) + 1));
3911 output_operand_lossage ("invalid operand to %%s code");
3915 /* Conditional branches depending on condition codes.
3916 Note that this is only for branches that were known to depend on
3917 condition codes before delay slot scheduling;
3918 out-of-range brcc / bbit expansions should use '*'.
3919 This distinction is important because of the different
3920 allowable delay slot insns and the output of the delay suffix
3921 for TARGET_AT_DBR_COND_EXEC. */
3923 /* Unconditional branches / branches not depending on condition codes.
3924 This could also be a CALL_INSN.
3925 Output the appropriate delay slot suffix. */
3926 if (final_sequence
&& final_sequence
->len () != 1)
3928 rtx_insn
*jump
= final_sequence
->insn (0);
3929 rtx_insn
*delay
= final_sequence
->insn (1);
3931 /* For TARGET_PAD_RETURN we might have grabbed the delay insn. */
3932 if (delay
->deleted ())
3934 if (JUMP_P (jump
) && INSN_ANNULLED_BRANCH_P (jump
))
3935 fputs (INSN_FROM_TARGET_P (delay
) ? ".d"
3936 : TARGET_AT_DBR_CONDEXEC
&& code
== '#' ? ".d"
3937 : get_attr_type (jump
) == TYPE_RETURN
&& code
== '#' ? ""
3944 case '?' : /* with leading "." */
3945 case '!' : /* without leading "." */
3946 /* This insn can be conditionally executed. See if the ccfsm machinery
3947 says it should be conditionalized.
3948 If it shouldn't, we'll check the compact attribute if this insn
3949 has a short variant, which may be used depending on code size and
3950 alignment considerations. */
3951 if (current_insn_predicate
)
3952 arc_ccfsm_current
.cc
3953 = get_arc_condition_code (current_insn_predicate
);
3954 if (ARC_CCFSM_COND_EXEC_P (&arc_ccfsm_current
))
3956 /* Is this insn in a delay slot sequence? */
3957 if (!final_sequence
|| XVECLEN (final_sequence
, 0) < 2
3958 || current_insn_predicate
3959 || CALL_P (final_sequence
->insn (0))
3960 || simplejump_p (final_sequence
->insn (0)))
3962 /* This insn isn't in a delay slot sequence, or conditionalized
3963 independently of its position in a delay slot. */
3964 fprintf (file
, "%s%s",
3965 code
== '?' ? "." : "",
3966 arc_condition_codes
[arc_ccfsm_current
.cc
]);
3967 /* If this is a jump, there are still short variants. However,
3968 only beq_s / bne_s have the same offset range as b_s,
3969 and the only short conditional returns are jeq_s and jne_s. */
3971 && (arc_ccfsm_current
.cc
== ARC_CC_EQ
3972 || arc_ccfsm_current
.cc
== ARC_CC_NE
3973 || 0 /* FIXME: check if branch in 7 bit range. */))
3974 output_short_suffix (file
);
3976 else if (code
== '!') /* Jump with delay slot. */
3977 fputs (arc_condition_codes
[arc_ccfsm_current
.cc
], file
);
3978 else /* An Instruction in a delay slot of a jump or call. */
3980 rtx jump
= XVECEXP (final_sequence
, 0, 0);
3981 rtx insn
= XVECEXP (final_sequence
, 0, 1);
3983 /* If the insn is annulled and is from the target path, we need
3984 to inverse the condition test. */
3985 if (JUMP_P (jump
) && INSN_ANNULLED_BRANCH_P (jump
))
3987 if (INSN_FROM_TARGET_P (insn
))
3988 fprintf (file
, "%s%s",
3989 code
== '?' ? "." : "",
3990 arc_condition_codes
[ARC_INVERSE_CONDITION_CODE (arc_ccfsm_current
.cc
)]);
3992 fprintf (file
, "%s%s",
3993 code
== '?' ? "." : "",
3994 arc_condition_codes
[arc_ccfsm_current
.cc
]);
3995 if (arc_ccfsm_current
.state
== 5)
3996 arc_ccfsm_current
.state
= 0;
3999 /* This insn is executed for either path, so don't
4000 conditionalize it at all. */
4001 output_short_suffix (file
);
4006 output_short_suffix (file
);
4009 /* FIXME: fold constant inside unary operator, re-recognize, and emit. */
4012 fputs (arc_condition_codes
[get_arc_condition_code (x
)], file
);
4015 fputs (arc_condition_codes
[ARC_INVERSE_CONDITION_CODE
4016 (get_arc_condition_code (x
))],
4020 /* Write second word of DImode or DFmode reference,
4021 register or memory. */
4022 if (GET_CODE (x
) == REG
)
4023 fputs (reg_names
[REGNO (x
)+1], file
);
4024 else if (GET_CODE (x
) == MEM
)
4028 /* Handle possible auto-increment. For PRE_INC / PRE_DEC /
4029 PRE_MODIFY, we will have handled the first word already;
4030 For POST_INC / POST_DEC / POST_MODIFY, the access to the
4031 first word will be done later. In either case, the access
4032 to the first word will do the modify, and we only have
4033 to add an offset of four here. */
4034 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
4035 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
4036 || GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
4037 || GET_CODE (XEXP (x
, 0)) == POST_INC
4038 || GET_CODE (XEXP (x
, 0)) == POST_DEC
4039 || GET_CODE (XEXP (x
, 0)) == POST_MODIFY
)
4040 output_address (VOIDmode
,
4041 plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 4));
4042 else if (output_scaled
)
4044 rtx addr
= XEXP (x
, 0);
4045 int size
= GET_MODE_SIZE (GET_MODE (x
));
4047 output_address (VOIDmode
,
4048 plus_constant (Pmode
, XEXP (addr
, 0),
4049 ((INTVAL (XEXP (addr
, 1)) + 4)
4050 >> (size
== 2 ? 1 : 2))));
4054 output_address (VOIDmode
,
4055 plus_constant (Pmode
, XEXP (x
, 0), 4));
4059 output_operand_lossage ("invalid operand to %%R code");
4063 if (GET_CODE (x
) == SYMBOL_REF
4064 && arc_is_jli_call_p (x
))
4066 if (SYMBOL_REF_DECL (x
))
4068 tree attrs
= (TREE_TYPE (SYMBOL_REF_DECL (x
)) != error_mark_node
4069 ? TYPE_ATTRIBUTES (TREE_TYPE (SYMBOL_REF_DECL (x
)))
4071 if (lookup_attribute ("jli_fixed", attrs
))
4073 /* No special treatment for jli_fixed functions. */
4076 fprintf (file
, "%ld\t; @",
4077 TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attrs
))));
4078 assemble_name (file
, XSTR (x
, 0));
4082 fprintf (file
, "@__jli.");
4083 assemble_name (file
, XSTR (x
, 0));
4085 arc_add_jli_section (x
);
4088 if (GET_CODE (x
) == SYMBOL_REF
4089 && arc_is_secure_call_p (x
))
4091 /* No special treatment for secure functions. */
4094 tree attrs
= (TREE_TYPE (SYMBOL_REF_DECL (x
)) != error_mark_node
4095 ? TYPE_ATTRIBUTES (TREE_TYPE (SYMBOL_REF_DECL (x
)))
4097 fprintf (file
, "%ld\t; @",
4098 TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attrs
))));
4099 assemble_name (file
, XSTR (x
, 0));
4103 case 'B' /* Branch or other LIMM ref - must not use sda references. */ :
4106 output_addr_const (file
, x
);
4112 if (GET_CODE (x
) == REG
)
4114 /* L = least significant word, H = most significant word. */
4115 if ((WORDS_BIG_ENDIAN
!= 0) ^ (code
== 'L'))
4116 fputs (reg_names
[REGNO (x
)], file
);
4118 fputs (reg_names
[REGNO (x
)+1], file
);
4120 else if (GET_CODE (x
) == CONST_INT
4121 || GET_CODE (x
) == CONST_DOUBLE
)
4123 rtx first
, second
, word
;
4125 split_double (x
, &first
, &second
);
4127 if((WORDS_BIG_ENDIAN
) == 0)
4128 word
= (code
== 'L' ? first
: second
);
4130 word
= (code
== 'L' ? second
: first
);
4132 fprintf (file
, "0x%08" PRIx32
, ((uint32_t) INTVAL (word
)));
4135 output_operand_lossage ("invalid operand to %%H/%%L code");
4141 gcc_assert (GET_CODE (x
) == CONST_DOUBLE
4142 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
);
4144 real_to_decimal (str
, CONST_DOUBLE_REAL_VALUE (x
), sizeof (str
), 0, 1);
4145 fprintf (file
, "%s", str
);
4149 /* Output a load/store with update indicator if appropriate. */
4150 if (GET_CODE (x
) == MEM
)
4152 rtx addr
= XEXP (x
, 0);
4153 switch (GET_CODE (addr
))
4155 case PRE_INC
: case PRE_DEC
: case PRE_MODIFY
:
4156 fputs (".a", file
); break;
4157 case POST_INC
: case POST_DEC
: case POST_MODIFY
:
4158 fputs (".ab", file
); break;
4160 /* Are we using a scaled index? */
4161 if (GET_CODE (XEXP (addr
, 0)) == MULT
)
4162 fputs (".as", file
);
4163 /* Can we use a scaled offset? */
4164 else if (CONST_INT_P (XEXP (addr
, 1))
4165 && GET_MODE_SIZE (GET_MODE (x
)) > 1
4166 && (!(INTVAL (XEXP (addr
, 1))
4167 & (GET_MODE_SIZE (GET_MODE (x
)) - 1) & 3))
4168 /* Does it make a difference? */
4169 && !SMALL_INT_RANGE(INTVAL (XEXP (addr
, 1)),
4170 GET_MODE_SIZE (GET_MODE (x
)) - 2, 0))
4172 fputs (".as", file
);
4178 if (legitimate_small_data_address_p (addr
)
4179 && GET_MODE_SIZE (GET_MODE (x
)) > 1)
4181 int align
= get_symbol_alignment (addr
);
4183 switch (GET_MODE (x
))
4192 if (align
&& ((align
& mask
) == 0))
4193 fputs (".as", file
);
4199 gcc_assert (CONSTANT_P (addr
)); break;
4203 output_operand_lossage ("invalid operand to %%U code");
4206 /* Output cache bypass indicator for a load/store insn. Volatile memory
4207 refs are defined to use the cache bypass mechanism. */
4208 if (GET_CODE (x
) == MEM
)
4210 if ((MEM_VOLATILE_P (x
) && !TARGET_VOLATILE_CACHE_SET
)
4211 || arc_is_uncached_mem_p (x
))
4212 fputs (".di", file
);
4215 output_operand_lossage ("invalid operand to %%V code");
4220 /* Do nothing special. */
4223 fputs (reg_names
[REGNO (x
)]+1, file
);
4226 /* This punctuation character is needed because label references are
4227 printed in the output template using %l. This is a front end
4228 character, and when we want to emit a '@' before it, we have to use
4234 /* Output an operator. */
4235 switch (GET_CODE (x
))
4237 case PLUS
: fputs ("add", file
); return;
4238 case SS_PLUS
: fputs ("adds", file
); return;
4239 case AND
: fputs ("and", file
); return;
4240 case IOR
: fputs ("or", file
); return;
4241 case XOR
: fputs ("xor", file
); return;
4242 case MINUS
: fputs ("sub", file
); return;
4243 case SS_MINUS
: fputs ("subs", file
); return;
4244 case ASHIFT
: fputs ("asl", file
); return;
4245 case ASHIFTRT
: fputs ("asr", file
); return;
4246 case LSHIFTRT
: fputs ("lsr", file
); return;
4247 case ROTATERT
: fputs ("ror", file
); return;
4248 case MULT
: fputs ("mpy", file
); return;
4249 case ABS
: fputs ("abs", file
); return; /* Unconditional. */
4250 case NEG
: fputs ("neg", file
); return;
4251 case SS_NEG
: fputs ("negs", file
); return;
4252 case NOT
: fputs ("not", file
); return; /* Unconditional. */
4254 fputs ("ext", file
); /* bmsk allows predication. */
4256 case SIGN_EXTEND
: /* Unconditional. */
4257 fputs ("sex", file
);
4259 switch (GET_MODE (XEXP (x
, 0)))
4261 case E_QImode
: fputs ("b", file
); return;
4262 case E_HImode
: fputs ("w", file
); return;
4267 if (GET_MODE (x
) != HImode
)
4269 fputs ("sat16", file
);
4272 output_operand_lossage ("invalid operand to %%O code"); return;
4274 if (GET_CODE (x
) == SYMBOL_REF
)
4276 assemble_name (file
, XSTR (x
, 0));
4281 if (TARGET_ANNOTATE_ALIGN
&& cfun
->machine
->size_reason
)
4282 fprintf (file
, "; unalign: %d", cfun
->machine
->unalign
);
4298 output_operand_lossage ("invalid operand output code");
4301 switch (GET_CODE (x
))
4304 fputs (reg_names
[REGNO (x
)], file
);
4308 rtx addr
= XEXP (x
, 0);
4309 int size
= GET_MODE_SIZE (GET_MODE (x
));
4311 if (legitimate_small_data_address_p (addr
))
4316 switch (GET_CODE (addr
))
4318 case PRE_INC
: case POST_INC
:
4319 output_address (VOIDmode
,
4320 plus_constant (Pmode
, XEXP (addr
, 0), size
)); break;
4321 case PRE_DEC
: case POST_DEC
:
4322 output_address (VOIDmode
,
4323 plus_constant (Pmode
, XEXP (addr
, 0), -size
));
4325 case PRE_MODIFY
: case POST_MODIFY
:
4326 output_address (VOIDmode
, XEXP (addr
, 1)); break;
4330 output_address (VOIDmode
,
4331 plus_constant (Pmode
, XEXP (addr
, 0),
4332 (INTVAL (XEXP (addr
, 1))
4333 >> (size
== 2 ? 1 : 2))));
4337 output_address (VOIDmode
, addr
);
4340 if (flag_pic
&& CONSTANT_ADDRESS_P (addr
))
4341 arc_output_pic_addr_const (file
, addr
, code
);
4343 output_address (VOIDmode
, addr
);
4350 /* We handle SFmode constants here as output_addr_const doesn't. */
4351 if (GET_MODE (x
) == SFmode
)
4355 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x
), l
);
4356 fprintf (file
, "0x%08lx", l
);
4360 /* Let output_addr_const deal with it. */
4363 || (GET_CODE (x
) == CONST
4364 && GET_CODE (XEXP (x
, 0)) == UNSPEC
4365 && (XINT (XEXP (x
, 0), 1) == UNSPEC_TLS_OFF
4366 || XINT (XEXP (x
, 0), 1) == UNSPEC_TLS_GD
))
4367 || (GET_CODE (x
) == CONST
4368 && GET_CODE (XEXP (x
, 0)) == PLUS
4369 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == UNSPEC
4370 && (XINT (XEXP (XEXP (x
, 0), 0), 1) == UNSPEC_TLS_OFF
4371 || XINT (XEXP (XEXP (x
, 0), 0), 1) == UNSPEC_TLS_GD
)))
4372 arc_output_pic_addr_const (file
, x
, code
);
4374 output_addr_const (file
, x
);
4379 /* Print a memory address as an operand to reference that memory location. */
4382 arc_print_operand_address (FILE *file
, rtx addr
)
4384 register rtx base
, index
= 0;
4386 switch (GET_CODE (addr
))
4389 fputs (reg_names
[REGNO (addr
)], file
);
4393 fputs ("gp,", file
);
4394 output_addr_const (file
, addr
);
4396 fputs ("@sda", file
);
4400 if (GET_CODE (XEXP (addr
, 0)) == MULT
)
4401 index
= XEXP (XEXP (addr
, 0), 0), base
= XEXP (addr
, 1);
4402 else if (CONST_INT_P (XEXP (addr
, 0)))
4403 index
= XEXP (addr
, 0), base
= XEXP (addr
, 1);
4405 base
= XEXP (addr
, 0), index
= XEXP (addr
, 1);
4407 gcc_assert (OBJECT_P (base
));
4408 arc_print_operand_address (file
, base
);
4409 if (CONSTANT_P (base
) && CONST_INT_P (index
))
4413 gcc_assert (OBJECT_P (index
));
4414 arc_print_operand_address (file
, index
);
4418 rtx c
= XEXP (addr
, 0);
4420 if ((GET_CODE (c
) == UNSPEC
4421 && (XINT (c
, 1) == UNSPEC_TLS_OFF
4422 || XINT (c
, 1) == UNSPEC_TLS_IE
))
4423 || (GET_CODE (c
) == PLUS
4424 && GET_CODE (XEXP (c
, 0)) == UNSPEC
4425 && (XINT (XEXP (c
, 0), 1) == UNSPEC_TLS_OFF
4426 || XINT (XEXP (c
, 0), 1) == ARC_UNSPEC_GOTOFFPC
)))
4428 arc_output_pic_addr_const (file
, c
, 0);
4431 gcc_assert (GET_CODE (c
) == PLUS
);
4432 gcc_assert (GET_CODE (XEXP (c
, 0)) == SYMBOL_REF
);
4433 gcc_assert (GET_CODE (XEXP (c
, 1)) == CONST_INT
);
4435 output_address (VOIDmode
, XEXP (addr
, 0));
4441 /* We shouldn't get here as we've lost the mode of the memory object
4442 (which says how much to inc/dec by. */
4447 arc_output_pic_addr_const (file
, addr
, 0);
4449 output_addr_const (file
, addr
);
4454 /* Conditional execution support.
4456 This is based on the ARM port but for now is much simpler.
4458 A finite state machine takes care of noticing whether or not instructions
4459 can be conditionally executed, and thus decrease execution time and code
4460 size by deleting branch instructions. The fsm is controlled by
4461 arc_ccfsm_advance (called by arc_final_prescan_insn), and controls the
4462 actions of PRINT_OPERAND. The patterns in the .md file for the branch
4463 insns also have a hand in this. */
4464 /* The way we leave dealing with non-anulled or annull-false delay slot
4465 insns to the consumer is awkward. */
4467 /* The state of the fsm controlling condition codes are:
4468 0: normal, do nothing special
4469 1: don't output this insn
4470 2: don't output this insn
4471 3: make insns conditional
4472 4: make insns conditional
4473 5: make insn conditional (only for outputting anulled delay slot insns)
4475 special value for cfun->machine->uid_ccfsm_state:
4476 6: return with but one insn before it since function start / call
4478 State transitions (state->state by whom, under what condition):
4479 0 -> 1 arc_ccfsm_advance, if insn is a conditional branch skipping over
4481 0 -> 2 arc_ccfsm_advance, if insn is a conditional branch followed
4482 by zero or more non-jump insns and an unconditional branch with
4483 the same target label as the condbranch.
4484 1 -> 3 branch patterns, after having not output the conditional branch
4485 2 -> 4 branch patterns, after having not output the conditional branch
4486 0 -> 5 branch patterns, for anulled delay slot insn.
4487 3 -> 0 ASM_OUTPUT_INTERNAL_LABEL, if the `target' label is reached
4488 (the target label has CODE_LABEL_NUMBER equal to
4489 arc_ccfsm_target_label).
4490 4 -> 0 arc_ccfsm_advance, if `target' unconditional branch is reached
4491 3 -> 1 arc_ccfsm_advance, finding an 'else' jump skipping over some insns.
4492 5 -> 0 when outputting the delay slot insn
4494 If the jump clobbers the conditions then we use states 2 and 4.
4496 A similar thing can be done with conditional return insns.
4498 We also handle separating branches from sets of the condition code.
4499 This is done here because knowledge of the ccfsm state is required,
4500 we may not be outputting the branch. */
4502 /* arc_final_prescan_insn calls arc_ccfsm_advance to adjust arc_ccfsm_current,
4503 before letting final output INSN. */
4506 arc_ccfsm_advance (rtx_insn
*insn
, struct arc_ccfsm
*state
)
4508 /* BODY will hold the body of INSN. */
4511 /* This will be 1 if trying to repeat the trick (ie: do the `else' part of
4512 an if/then/else), and things need to be reversed. */
4515 /* If we start with a return insn, we only succeed if we find another one. */
4516 int seeking_return
= 0;
4518 /* START_INSN will hold the insn from where we start looking. This is the
4519 first insn after the following code_label if REVERSE is true. */
4520 rtx_insn
*start_insn
= insn
;
4522 /* Type of the jump_insn. Brcc insns don't affect ccfsm changes,
4523 since they don't rely on a cmp preceding the. */
4524 enum attr_type jump_insn_type
;
4526 /* Allow -mdebug-ccfsm to turn this off so we can see how well it does.
4527 We can't do this in macro FINAL_PRESCAN_INSN because its called from
4528 final_scan_insn which has `optimize' as a local. */
4529 if (optimize
< 2 || TARGET_NO_COND_EXEC
)
4532 /* Ignore notes and labels. */
4535 body
= PATTERN (insn
);
4536 /* If in state 4, check if the target branch is reached, in order to
4537 change back to state 0. */
4538 if (state
->state
== 4)
4540 if (insn
== state
->target_insn
)
4542 state
->target_insn
= NULL
;
4548 /* If in state 3, it is possible to repeat the trick, if this insn is an
4549 unconditional branch to a label, and immediately following this branch
4550 is the previous target label which is only used once, and the label this
4551 branch jumps to is not too far off. Or in other words "we've done the
4552 `then' part, see if we can do the `else' part." */
4553 if (state
->state
== 3)
4555 if (simplejump_p (insn
))
4557 start_insn
= next_nonnote_insn (start_insn
);
4558 if (GET_CODE (start_insn
) == BARRIER
)
4560 /* ??? Isn't this always a barrier? */
4561 start_insn
= next_nonnote_insn (start_insn
);
4563 if (GET_CODE (start_insn
) == CODE_LABEL
4564 && CODE_LABEL_NUMBER (start_insn
) == state
->target_label
4565 && LABEL_NUSES (start_insn
) == 1)
4570 else if (GET_CODE (body
) == SIMPLE_RETURN
)
4572 start_insn
= next_nonnote_insn (start_insn
);
4573 if (GET_CODE (start_insn
) == BARRIER
)
4574 start_insn
= next_nonnote_insn (start_insn
);
4575 if (GET_CODE (start_insn
) == CODE_LABEL
4576 && CODE_LABEL_NUMBER (start_insn
) == state
->target_label
4577 && LABEL_NUSES (start_insn
) == 1)
4589 if (GET_CODE (insn
) != JUMP_INSN
4590 || GET_CODE (PATTERN (insn
)) == ADDR_VEC
4591 || GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
)
4594 /* We can't predicate BRCC or loop ends.
4595 Also, when generating PIC code, and considering a medium range call,
4596 we can't predicate the call. */
4597 jump_insn_type
= get_attr_type (insn
);
4598 if (jump_insn_type
== TYPE_BRCC
4599 || jump_insn_type
== TYPE_BRCC_NO_DELAY_SLOT
4600 || jump_insn_type
== TYPE_LOOP_END
4601 || (jump_insn_type
== TYPE_CALL
&& !get_attr_predicable (insn
)))
4604 /* This jump might be paralleled with a clobber of the condition codes,
4605 the jump should always come first. */
4606 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
4607 body
= XVECEXP (body
, 0, 0);
4610 || (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
4611 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
))
4613 int insns_skipped
= 0, fail
= FALSE
, succeed
= FALSE
;
4614 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
4615 int then_not_else
= TRUE
;
4616 /* Nonzero if next insn must be the target label. */
4617 int next_must_be_target_label_p
;
4618 rtx_insn
*this_insn
= start_insn
;
4621 /* Register the insn jumped to. */
4624 if (!seeking_return
)
4625 label
= XEXP (SET_SRC (body
), 0);
4627 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == LABEL_REF
)
4628 label
= XEXP (XEXP (SET_SRC (body
), 1), 0);
4629 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == LABEL_REF
)
4631 label
= XEXP (XEXP (SET_SRC (body
), 2), 0);
4632 then_not_else
= FALSE
;
4634 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == SIMPLE_RETURN
)
4636 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == SIMPLE_RETURN
)
4639 then_not_else
= FALSE
;
4644 /* If this is a non-annulled branch with a delay slot, there is
4645 no need to conditionalize the delay slot. */
4646 if ((GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn
)))) == SEQUENCE
)
4647 && state
->state
== 0 && !INSN_ANNULLED_BRANCH_P (insn
))
4649 this_insn
= NEXT_INSN (this_insn
);
4651 /* See how many insns this branch skips, and what kind of insns. If all
4652 insns are okay, and the label or unconditional branch to the same
4653 label is not too far away, succeed. */
4654 for (insns_skipped
= 0, next_must_be_target_label_p
= FALSE
;
4655 !fail
&& !succeed
&& insns_skipped
< MAX_INSNS_SKIPPED
;
4660 this_insn
= next_nonnote_insn (this_insn
);
4664 if (next_must_be_target_label_p
)
4666 if (GET_CODE (this_insn
) == BARRIER
)
4668 if (GET_CODE (this_insn
) == CODE_LABEL
4669 && this_insn
== label
)
4679 switch (GET_CODE (this_insn
))
4682 /* Succeed if it is the target label, otherwise fail since
4683 control falls in from somewhere else. */
4684 if (this_insn
== label
)
4694 /* Succeed if the following insn is the target label.
4696 If return insns are used then the last insn in a function
4697 will be a barrier. */
4698 next_must_be_target_label_p
= TRUE
;
4702 /* Can handle a call insn if there are no insns after it.
4703 IE: The next "insn" is the target label. We don't have to
4704 worry about delay slots as such insns are SEQUENCE's inside
4705 INSN's. ??? It is possible to handle such insns though. */
4706 if (get_attr_cond (this_insn
) == COND_CANUSE
)
4707 next_must_be_target_label_p
= TRUE
;
4713 scanbody
= PATTERN (this_insn
);
4715 /* If this is an unconditional branch to the same label, succeed.
4716 If it is to another label, do nothing. If it is conditional,
4718 /* ??? Probably, the test for the SET and the PC are
4721 if (GET_CODE (scanbody
) == SET
4722 && GET_CODE (SET_DEST (scanbody
)) == PC
)
4724 if (GET_CODE (SET_SRC (scanbody
)) == LABEL_REF
4725 && XEXP (SET_SRC (scanbody
), 0) == label
&& !reverse
)
4730 else if (GET_CODE (SET_SRC (scanbody
)) == IF_THEN_ELSE
)
4732 else if (get_attr_cond (this_insn
) != COND_CANUSE
)
4735 else if (GET_CODE (scanbody
) == SIMPLE_RETURN
4741 else if (GET_CODE (scanbody
) == PARALLEL
)
4743 if (get_attr_cond (this_insn
) != COND_CANUSE
)
4749 scanbody
= PATTERN (this_insn
);
4751 /* We can only do this with insns that can use the condition
4752 codes (and don't set them). */
4753 if (GET_CODE (scanbody
) == SET
4754 || GET_CODE (scanbody
) == PARALLEL
)
4756 if (get_attr_cond (this_insn
) != COND_CANUSE
)
4759 /* We can't handle other insns like sequences. */
4771 if ((!seeking_return
) && (state
->state
== 1 || reverse
))
4772 state
->target_label
= CODE_LABEL_NUMBER (label
);
4773 else if (seeking_return
|| state
->state
== 2)
4775 while (this_insn
&& GET_CODE (PATTERN (this_insn
)) == USE
)
4777 this_insn
= next_nonnote_insn (this_insn
);
4779 gcc_assert (!this_insn
||
4780 (GET_CODE (this_insn
) != BARRIER
4781 && GET_CODE (this_insn
) != CODE_LABEL
));
4785 /* Oh dear! we ran off the end, give up. */
4786 extract_insn_cached (insn
);
4788 state
->target_insn
= NULL
;
4791 state
->target_insn
= this_insn
;
4796 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
4800 state
->cond
= XEXP (SET_SRC (body
), 0);
4801 state
->cc
= get_arc_condition_code (XEXP (SET_SRC (body
), 0));
4804 if (reverse
|| then_not_else
)
4805 state
->cc
= ARC_INVERSE_CONDITION_CODE (state
->cc
);
4808 /* Restore recog_operand. Getting the attributes of other insns can
4809 destroy this array, but final.c assumes that it remains intact
4810 across this call; since the insn has been recognized already we
4811 call insn_extract direct. */
4812 extract_insn_cached (insn
);
4816 /* Record that we are currently outputting label NUM with prefix PREFIX.
4817 It it's the label we're looking for, reset the ccfsm machinery.
4819 Called from ASM_OUTPUT_INTERNAL_LABEL. */
4822 arc_ccfsm_at_label (const char *prefix
, int num
, struct arc_ccfsm
*state
)
4824 if (state
->state
== 3 && state
->target_label
== num
4825 && !strcmp (prefix
, "L"))
4828 state
->target_insn
= NULL
;
4832 /* We are considering a conditional branch with the condition COND.
4833 Check if we want to conditionalize a delay slot insn, and if so modify
4834 the ccfsm state accordingly.
4835 REVERSE says branch will branch when the condition is false. */
4837 arc_ccfsm_record_condition (rtx cond
, bool reverse
, rtx_insn
*jump
,
4838 struct arc_ccfsm
*state
)
4840 rtx_insn
*seq_insn
= NEXT_INSN (PREV_INSN (jump
));
4842 state
= &arc_ccfsm_current
;
4844 gcc_assert (state
->state
== 0);
4845 if (seq_insn
!= jump
)
4847 rtx insn
= XVECEXP (PATTERN (seq_insn
), 0, 1);
4849 if (!as_a
<rtx_insn
*> (insn
)->deleted ()
4850 && INSN_ANNULLED_BRANCH_P (jump
)
4851 && (TARGET_AT_DBR_CONDEXEC
|| INSN_FROM_TARGET_P (insn
)))
4854 state
->cc
= get_arc_condition_code (cond
);
4856 arc_ccfsm_current
.cc
4857 = ARC_INVERSE_CONDITION_CODE (state
->cc
);
4858 rtx pat
= PATTERN (insn
);
4859 if (GET_CODE (pat
) == COND_EXEC
)
4860 gcc_assert ((INSN_FROM_TARGET_P (insn
)
4861 ? ARC_INVERSE_CONDITION_CODE (state
->cc
) : state
->cc
)
4862 == get_arc_condition_code (XEXP (pat
, 0)));
4869 /* Update *STATE as we would when we emit INSN. */
4872 arc_ccfsm_post_advance (rtx_insn
*insn
, struct arc_ccfsm
*state
)
4874 enum attr_type type
;
4877 arc_ccfsm_at_label ("L", CODE_LABEL_NUMBER (insn
), state
);
4878 else if (JUMP_P (insn
)
4879 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
4880 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
4881 && ((type
= get_attr_type (insn
)) == TYPE_BRANCH
4882 || ((type
== TYPE_UNCOND_BRANCH
4883 || type
== TYPE_RETURN
)
4884 && ARC_CCFSM_BRANCH_DELETED_P (state
))))
4886 if (ARC_CCFSM_BRANCH_DELETED_P (state
))
4887 ARC_CCFSM_RECORD_BRANCH_DELETED (state
);
4890 rtx src
= SET_SRC (PATTERN (insn
));
4891 arc_ccfsm_record_condition (XEXP (src
, 0), XEXP (src
, 1) == pc_rtx
,
4895 else if (arc_ccfsm_current
.state
== 5)
4896 arc_ccfsm_current
.state
= 0;
4899 /* Return true if the current insn, which is a conditional branch, is to be
4903 arc_ccfsm_branch_deleted_p (void)
4905 return ARC_CCFSM_BRANCH_DELETED_P (&arc_ccfsm_current
);
4908 /* Record a branch isn't output because subsequent insns can be
4912 arc_ccfsm_record_branch_deleted (void)
4914 ARC_CCFSM_RECORD_BRANCH_DELETED (&arc_ccfsm_current
);
4917 /* During insn output, indicate if the current insn is predicated. */
4920 arc_ccfsm_cond_exec_p (void)
4922 return (cfun
->machine
->prescan_initialized
4923 && ARC_CCFSM_COND_EXEC_P (&arc_ccfsm_current
));
4926 /* When deciding if an insn should be output short, we want to know something
4927 about the following insns:
4928 - if another insn follows which we know we can output as a short insn
4929 before an alignment-sensitive point, we can output this insn short:
4930 the decision about the eventual alignment can be postponed.
4931 - if a to-be-aligned label comes next, we should output this insn such
4932 as to get / preserve 4-byte alignment.
4933 - if a likely branch without delay slot insn, or a call with an immediately
4934 following short insn comes next, we should out output this insn such as to
4935 get / preserve 2 mod 4 unalignment.
4936 - do the same for a not completely unlikely branch with a short insn
4937 following before any other branch / label.
4938 - in order to decide if we are actually looking at a branch, we need to
4939 call arc_ccfsm_advance.
4940 - in order to decide if we are looking at a short insn, we should know
4941 if it is conditionalized. To a first order of approximation this is
4942 the case if the state from arc_ccfsm_advance from before this insn
4943 indicates the insn is conditionalized. However, a further refinement
4944 could be to not conditionalize an insn if the destination register(s)
4945 is/are dead in the non-executed case. */
4946 /* Return non-zero if INSN should be output as a short insn. UNALIGN is
4947 zero if the current insn is aligned to a 4-byte-boundary, two otherwise.
4948 If CHECK_ATTR is greater than 0, check the iscompact attribute first. */
4951 arc_verify_short (rtx_insn
*insn
, int, int check_attr
)
4953 enum attr_iscompact iscompact
;
4954 struct machine_function
*machine
;
4958 iscompact
= get_attr_iscompact (insn
);
4959 if (iscompact
== ISCOMPACT_FALSE
)
4962 machine
= cfun
->machine
;
4964 if (machine
->force_short_suffix
>= 0)
4965 return machine
->force_short_suffix
;
4967 return (get_attr_length (insn
) & 2) != 0;
4970 /* When outputting an instruction (alternative) that can potentially be short,
4971 output the short suffix if the insn is in fact short, and update
4972 cfun->machine->unalign accordingly. */
4975 output_short_suffix (FILE *file
)
4977 rtx_insn
*insn
= current_output_insn
;
4979 if (arc_verify_short (insn
, cfun
->machine
->unalign
, 1))
4981 fprintf (file
, "_s");
4982 cfun
->machine
->unalign
^= 2;
4984 /* Restore recog_operand. */
4985 extract_insn_cached (insn
);
4988 /* Implement FINAL_PRESCAN_INSN. */
4991 arc_final_prescan_insn (rtx_insn
*insn
, rtx
*opvec ATTRIBUTE_UNUSED
,
4992 int noperands ATTRIBUTE_UNUSED
)
4994 if (TARGET_DUMPISIZE
)
4995 fprintf (asm_out_file
, "\n; at %04x\n", INSN_ADDRESSES (INSN_UID (insn
)));
4997 if (!cfun
->machine
->prescan_initialized
)
4999 /* Clear lingering state from branch shortening. */
5000 memset (&arc_ccfsm_current
, 0, sizeof arc_ccfsm_current
);
5001 cfun
->machine
->prescan_initialized
= 1;
5003 arc_ccfsm_advance (insn
, &arc_ccfsm_current
);
5005 cfun
->machine
->size_reason
= 0;
5008 /* Given FROM and TO register numbers, say whether this elimination is allowed.
5009 Frame pointer elimination is automatically handled.
5011 All eliminations are permissible. If we need a frame
5012 pointer, we must eliminate ARG_POINTER_REGNUM into
5013 FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
5016 arc_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
5018 return ((to
== FRAME_POINTER_REGNUM
) || !arc_frame_pointer_needed ());
5021 /* Define the offset between two registers, one to be eliminated, and
5022 the other its replacement, at the start of a routine. */
5025 arc_initial_elimination_offset (int from
, int to
)
5027 if (!cfun
->machine
->frame_info
.initialized
)
5028 arc_compute_frame_size ();
5030 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
5032 return (cfun
->machine
->frame_info
.extra_size
5033 + cfun
->machine
->frame_info
.reg_size
);
5036 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
5038 return (cfun
->machine
->frame_info
.total_size
5039 - cfun
->machine
->frame_info
.pretend_size
);
5042 if ((from
== FRAME_POINTER_REGNUM
) && (to
== STACK_POINTER_REGNUM
))
5044 return (cfun
->machine
->frame_info
.total_size
5045 - (cfun
->machine
->frame_info
.pretend_size
5046 + cfun
->machine
->frame_info
.extra_size
5047 + cfun
->machine
->frame_info
.reg_size
));
5054 arc_frame_pointer_required (void)
5056 return cfun
->calls_alloca
|| crtl
->calls_eh_return
;
5060 /* Return the destination address of a branch. */
5063 branch_dest (rtx branch
)
5065 rtx pat
= PATTERN (branch
);
5066 rtx dest
= (GET_CODE (pat
) == PARALLEL
5067 ? SET_SRC (XVECEXP (pat
, 0, 0)) : SET_SRC (pat
));
5070 if (GET_CODE (dest
) == IF_THEN_ELSE
)
5071 dest
= XEXP (dest
, XEXP (dest
, 1) == pc_rtx
? 2 : 1);
5073 dest
= XEXP (dest
, 0);
5074 dest_uid
= INSN_UID (dest
);
5076 return INSN_ADDRESSES (dest_uid
);
5080 /* Implement TARGET_ENCODE_SECTION_INFO hook. */
5083 arc_encode_section_info (tree decl
, rtx rtl
, int first
)
5085 /* For sdata, SYMBOL_FLAG_LOCAL and SYMBOL_FLAG_FUNCTION.
5086 This clears machine specific flags, so has to come first. */
5087 default_encode_section_info (decl
, rtl
, first
);
5089 /* Check if it is a function, and whether it has the
5090 [long/medium/short]_call attribute specified. */
5091 if (TREE_CODE (decl
) == FUNCTION_DECL
)
5093 rtx symbol
= XEXP (rtl
, 0);
5094 int flags
= SYMBOL_REF_FLAGS (symbol
);
5096 tree attr
= (TREE_TYPE (decl
) != error_mark_node
5097 ? TYPE_ATTRIBUTES (TREE_TYPE (decl
)) : NULL_TREE
);
5098 tree long_call_attr
= lookup_attribute ("long_call", attr
);
5099 tree medium_call_attr
= lookup_attribute ("medium_call", attr
);
5100 tree short_call_attr
= lookup_attribute ("short_call", attr
);
5102 if (long_call_attr
!= NULL_TREE
)
5103 flags
|= SYMBOL_FLAG_LONG_CALL
;
5104 else if (medium_call_attr
!= NULL_TREE
)
5105 flags
|= SYMBOL_FLAG_MEDIUM_CALL
;
5106 else if (short_call_attr
!= NULL_TREE
)
5107 flags
|= SYMBOL_FLAG_SHORT_CALL
;
5109 SYMBOL_REF_FLAGS (symbol
) = flags
;
5111 else if (TREE_CODE (decl
) == VAR_DECL
)
5113 rtx symbol
= XEXP (rtl
, 0);
5115 tree attr
= (TREE_TYPE (decl
) != error_mark_node
5116 ? DECL_ATTRIBUTES (decl
) : NULL_TREE
);
5118 tree sec_attr
= lookup_attribute ("section", attr
);
5121 const char *sec_name
5122 = TREE_STRING_POINTER (TREE_VALUE (TREE_VALUE (sec_attr
)));
5123 if (strcmp (sec_name
, ".cmem") == 0
5124 || strcmp (sec_name
, ".cmem_shared") == 0
5125 || strcmp (sec_name
, ".cmem_private") == 0)
5126 SYMBOL_REF_FLAGS (symbol
) |= SYMBOL_FLAG_CMEM
;
5131 /* This is how to output a definition of an internal numbered label where
5132 PREFIX is the class of label and NUM is the number within the class. */
5134 static void arc_internal_label (FILE *stream
, const char *prefix
, unsigned long labelno
)
5137 arc_ccfsm_at_label (prefix
, labelno
, &arc_ccfsm_current
);
5138 default_internal_label (stream
, prefix
, labelno
);
5141 /* Set the cpu type and print out other fancy things,
5142 at the top of the file. */
5144 static void arc_file_start (void)
5146 default_file_start ();
5147 fprintf (asm_out_file
, "\t.cpu %s\n", arc_cpu_string
);
5149 /* Set some want to have build attributes. */
5150 asm_fprintf (asm_out_file
, "\t.arc_attribute Tag_ARC_PCS_config, %d\n",
5152 asm_fprintf (asm_out_file
, "\t.arc_attribute Tag_ARC_ABI_rf16, %d\n",
5153 TARGET_RF16
? 1 : 0);
5154 asm_fprintf (asm_out_file
, "\t.arc_attribute Tag_ARC_ABI_pic, %d\n",
5156 asm_fprintf (asm_out_file
, "\t.arc_attribute Tag_ARC_ABI_tls, %d\n",
5157 (arc_tp_regno
!= -1) ? 1 : 0);
5158 asm_fprintf (asm_out_file
, "\t.arc_attribute Tag_ARC_ABI_sda, %d\n",
5159 TARGET_NO_SDATA_SET
? 0 : 2);
5160 asm_fprintf (asm_out_file
, "\t.arc_attribute Tag_ARC_ABI_exceptions, %d\n",
5161 TARGET_OPTFPE
? 1 : 0);
5163 asm_fprintf (asm_out_file
, "\t.arc_attribute Tag_ARC_CPU_variation, %d\n",
5164 arc_tune
== ARC_TUNE_CORE_3
? 3 : 2);
5167 /* Implement `TARGET_ASM_FILE_END'. */
5168 /* Outputs to the stdio stream FILE jli related text. */
5170 void arc_file_end (void)
5172 arc_jli_section
*sec
= arc_jli_sections
;
5176 fprintf (asm_out_file
, "\n");
5177 fprintf (asm_out_file
, "# JLI entry for function ");
5178 assemble_name (asm_out_file
, sec
->name
);
5179 fprintf (asm_out_file
, "\n\t.section .jlitab, \"axG\", @progbits, "
5181 assemble_name (asm_out_file
, sec
->name
);
5182 fprintf (asm_out_file
,", comdat\n");
5184 fprintf (asm_out_file
, "\t.align\t4\n");
5185 fprintf (asm_out_file
, "__jli.");
5186 assemble_name (asm_out_file
, sec
->name
);
5187 fprintf (asm_out_file
, ":\n\t.weak __jli.");
5188 assemble_name (asm_out_file
, sec
->name
);
5189 fprintf (asm_out_file
, "\n\tb\t@");
5190 assemble_name (asm_out_file
, sec
->name
);
5191 fprintf (asm_out_file
, "\n");
5194 file_end_indicate_exec_stack ();
5197 /* Cost functions. */
5199 /* Compute a (partial) cost for rtx X. Return true if the complete
5200 cost has been computed, and false if subexpressions should be
5201 scanned. In either case, *TOTAL contains the cost result. */
5204 arc_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
5205 int opno ATTRIBUTE_UNUSED
, int *total
, bool speed
)
5207 int code
= GET_CODE (x
);
5211 /* Small integers are as cheap as registers. */
5214 bool nolimm
= false; /* Can we do without long immediate? */
5215 bool fast
= false; /* Is the result available immediately? */
5216 bool condexec
= false; /* Does this allow conditiobnal execution? */
5217 bool compact
= false; /* Is a 16 bit opcode available? */
5218 /* CONDEXEC also implies that we can have an unconditional
5219 3-address operation. */
5221 nolimm
= compact
= condexec
= false;
5222 if (UNSIGNED_INT6 (INTVAL (x
)))
5223 nolimm
= condexec
= compact
= true;
5226 if (SMALL_INT (INTVAL (x
)))
5227 nolimm
= fast
= true;
5230 case AND
: /* bclr, bmsk, ext[bw] */
5231 if (satisfies_constraint_Ccp (x
) /* bclr */
5232 || satisfies_constraint_C1p (x
) /* bmsk */)
5233 nolimm
= fast
= condexec
= compact
= true;
5235 case IOR
: /* bset */
5236 if (satisfies_constraint_C0p (x
)) /* bset */
5237 nolimm
= fast
= condexec
= compact
= true;
5240 if (satisfies_constraint_C0p (x
)) /* bxor */
5241 nolimm
= fast
= condexec
= true;
5244 if (satisfies_constraint_Crr (x
)) /* ror b,u6 */
5250 /* FIXME: Add target options to attach a small cost if
5251 condexec / compact is not true. */
5260 /* 4 byte values can be fetched as immediate constants -
5261 let's give that the cost of an extra insn. */
5265 *total
= COSTS_N_INSNS (1);
5274 *total
= COSTS_N_INSNS (1);
5277 split_double (x
, &first
, &second
);
5278 *total
= COSTS_N_INSNS (!SMALL_INT (INTVAL (first
))
5279 + !SMALL_INT (INTVAL (second
)));
5283 /* Encourage synth_mult to find a synthetic multiply when reasonable.
5284 If we need more than 12 insns to do a multiply, then go out-of-line,
5285 since the call overhead will be < 10% of the cost of the multiply. */
5289 if (TARGET_BARREL_SHIFTER
)
5291 /* If we want to shift a constant, we need a LIMM. */
5292 /* ??? when the optimizers want to know if a constant should be
5293 hoisted, they ask for the cost of the constant. OUTER_CODE is
5294 insufficient context for shifts since we don't know which operand
5295 we are looking at. */
5296 if (CONSTANT_P (XEXP (x
, 0)))
5298 *total
+= (COSTS_N_INSNS (2)
5299 + rtx_cost (XEXP (x
, 1), mode
, (enum rtx_code
) code
,
5303 *total
= COSTS_N_INSNS (1);
5305 else if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
5306 *total
= COSTS_N_INSNS (16);
5309 *total
= COSTS_N_INSNS (INTVAL (XEXP ((x
), 1)));
5310 /* ??? want_to_gcse_p can throw negative shift counts at us,
5311 and then panics when it gets a negative cost as result.
5312 Seen for gcc.c-torture/compile/20020710-1.c -Os . */
5321 *total
= COSTS_N_INSNS(30);
5323 *total
= COSTS_N_INSNS(1);
5327 if ((TARGET_DPFP
&& GET_MODE (x
) == DFmode
))
5328 *total
= COSTS_N_INSNS (1);
5330 *total
= arc_multcost
;
5331 /* We do not want synth_mult sequences when optimizing
5333 else if (TARGET_MUL64_SET
|| TARGET_ARC700_MPY
)
5334 *total
= COSTS_N_INSNS (1);
5336 *total
= COSTS_N_INSNS (2);
5339 if ((GET_CODE (XEXP (x
, 0)) == ASHIFT
5340 && _1_2_3_operand (XEXP (XEXP (x
, 0), 1), VOIDmode
))
5341 || (GET_CODE (XEXP (x
, 0)) == MULT
5342 && _2_4_8_operand (XEXP (XEXP (x
, 0), 1), VOIDmode
)))
5344 *total
+= (rtx_cost (XEXP (x
, 1), mode
, PLUS
, 0, speed
)
5345 + rtx_cost (XEXP (XEXP (x
, 0), 0), mode
, PLUS
, 1, speed
));
5350 if ((GET_CODE (XEXP (x
, 1)) == ASHIFT
5351 && _1_2_3_operand (XEXP (XEXP (x
, 1), 1), VOIDmode
))
5352 || (GET_CODE (XEXP (x
, 1)) == MULT
5353 && _2_4_8_operand (XEXP (XEXP (x
, 1), 1), VOIDmode
)))
5355 *total
+= (rtx_cost (XEXP (x
, 0), mode
, PLUS
, 0, speed
)
5356 + rtx_cost (XEXP (XEXP (x
, 1), 0), mode
, PLUS
, 1, speed
));
5362 rtx op0
= XEXP (x
, 0);
5363 rtx op1
= XEXP (x
, 1);
5365 if (GET_CODE (op0
) == ZERO_EXTRACT
&& op1
== const0_rtx
5366 && XEXP (op0
, 1) == const1_rtx
)
5368 /* btst / bbit0 / bbit1:
5369 Small integers and registers are free; everything else can
5370 be put in a register. */
5371 mode
= GET_MODE (XEXP (op0
, 0));
5372 *total
= (rtx_cost (XEXP (op0
, 0), mode
, SET
, 1, speed
)
5373 + rtx_cost (XEXP (op0
, 2), mode
, SET
, 1, speed
));
5376 if (GET_CODE (op0
) == AND
&& op1
== const0_rtx
5377 && satisfies_constraint_C1p (XEXP (op0
, 1)))
5380 *total
= rtx_cost (XEXP (op0
, 0), VOIDmode
, SET
, 1, speed
);
5384 if (GET_CODE (op1
) == NEG
)
5386 /* op0 might be constant, the inside of op1 is rather
5387 unlikely to be so. So swapping the operands might lower
5389 mode
= GET_MODE (op0
);
5390 *total
= (rtx_cost (op0
, mode
, PLUS
, 1, speed
)
5391 + rtx_cost (XEXP (op1
, 0), mode
, PLUS
, 0, speed
));
5396 if (outer_code
== IF_THEN_ELSE
5397 && GET_CODE (XEXP (x
, 0)) == ZERO_EXTRACT
5398 && XEXP (x
, 1) == const0_rtx
5399 && XEXP (XEXP (x
, 0), 1) == const1_rtx
)
5401 /* btst / bbit0 / bbit1:
5402 Small integers and registers are free; everything else can
5403 be put in a register. */
5404 rtx op0
= XEXP (x
, 0);
5406 mode
= GET_MODE (XEXP (op0
, 0));
5407 *total
= (rtx_cost (XEXP (op0
, 0), mode
, SET
, 1, speed
)
5408 + rtx_cost (XEXP (op0
, 2), mode
, SET
, 1, speed
));
5412 /* scc_insn expands into two insns. */
5413 case GTU
: case GEU
: case LEU
:
5415 *total
+= COSTS_N_INSNS (1);
5417 case LTU
: /* might use adc. */
5419 *total
+= COSTS_N_INSNS (1) - 1;
5426 /* Return true if ADDR is a valid pic address.
5427 A valid pic address on arc should look like
5428 const (unspec (SYMBOL_REF/LABEL) (ARC_UNSPEC_GOTOFF/ARC_UNSPEC_GOT)) */
5431 arc_legitimate_pic_addr_p (rtx addr
)
5433 if (GET_CODE (addr
) != CONST
)
5436 addr
= XEXP (addr
, 0);
5439 if (GET_CODE (addr
) == PLUS
)
5441 if (GET_CODE (XEXP (addr
, 1)) != CONST_INT
)
5443 addr
= XEXP (addr
, 0);
5446 if (GET_CODE (addr
) != UNSPEC
5447 || XVECLEN (addr
, 0) != 1)
5450 /* Must be one of @GOT, @GOTOFF, @GOTOFFPC, @tlsgd, tlsie. */
5451 if (XINT (addr
, 1) != ARC_UNSPEC_GOT
5452 && XINT (addr
, 1) != ARC_UNSPEC_GOTOFF
5453 && XINT (addr
, 1) != ARC_UNSPEC_GOTOFFPC
5454 && XINT (addr
, 1) != UNSPEC_TLS_GD
5455 && XINT (addr
, 1) != UNSPEC_TLS_IE
)
5458 if (GET_CODE (XVECEXP (addr
, 0, 0)) != SYMBOL_REF
5459 && GET_CODE (XVECEXP (addr
, 0, 0)) != LABEL_REF
)
5467 /* Return true if OP contains a symbol reference. */
5470 symbolic_reference_mentioned_p (rtx op
)
5472 register const char *fmt
;
5475 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
5478 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
5479 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
5485 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
5486 if (symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
5490 else if (fmt
[i
] == 'e' && symbolic_reference_mentioned_p (XEXP (op
, i
)))
5497 /* Return true if OP contains a SYMBOL_REF that is not wrapped in an unspec.
5498 If SKIP_LOCAL is true, skip symbols that bind locally.
5499 This is used further down in this file, and, without SKIP_LOCAL,
5500 in the addsi3 / subsi3 expanders when generating PIC code. */
5503 arc_raw_symbolic_reference_mentioned_p (rtx op
, bool skip_local
)
5505 register const char *fmt
;
5508 if (GET_CODE(op
) == UNSPEC
)
5511 if (GET_CODE (op
) == SYMBOL_REF
)
5513 if (SYMBOL_REF_TLS_MODEL (op
))
5517 tree decl
= SYMBOL_REF_DECL (op
);
5518 return !skip_local
|| !decl
|| !default_binds_local_p (decl
);
5521 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
5522 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
5528 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
5529 if (arc_raw_symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
),
5534 else if (fmt
[i
] == 'e'
5535 && arc_raw_symbolic_reference_mentioned_p (XEXP (op
, i
),
5543 /* Get the thread pointer. */
5548 /* If arc_tp_regno has been set, we can use that hard register
5549 directly as a base register. */
5550 if (arc_tp_regno
!= -1)
5551 return gen_rtx_REG (Pmode
, arc_tp_regno
);
5553 /* Otherwise, call __read_tp. Copy the result to a pseudo to avoid
5554 conflicts with function arguments / results. */
5555 rtx reg
= gen_reg_rtx (Pmode
);
5556 emit_insn (gen_tls_load_tp_soft ());
5557 emit_move_insn (reg
, gen_rtx_REG (Pmode
, R0_REG
));
5561 /* Helper to be used by TLS Global dynamic model. */
5564 arc_emit_call_tls_get_addr (rtx sym
, int reloc
, rtx eqv
)
5566 rtx r0
= gen_rtx_REG (Pmode
, R0_REG
);
5567 rtx call_fusage
= NULL_RTX
;
5571 rtx x
= arc_unspec_offset (sym
, reloc
);
5572 emit_move_insn (r0
, x
);
5573 use_reg (&call_fusage
, r0
);
5575 gcc_assert (reloc
== UNSPEC_TLS_GD
);
5576 rtx call_insn
= emit_call_insn (gen_tls_gd_get_addr (sym
));
5577 /* Should we set RTL_CONST_CALL_P? We read memory, but not in a
5578 way that the application should care. */
5579 RTL_PURE_CALL_P (call_insn
) = 1;
5580 add_function_usage_to (call_insn
, call_fusage
);
5582 rtx_insn
*insns
= get_insns ();
5585 rtx dest
= gen_reg_rtx (Pmode
);
5586 emit_libcall_block (insns
, dest
, r0
, eqv
);
5590 #define DTPOFF_ZERO_SYM ".tdata"
5592 /* Return a legitimized address for ADDR,
5593 which is a SYMBOL_REF with tls_model MODEL. */
5596 arc_legitimize_tls_address (rtx addr
, enum tls_model model
)
5598 if (!flag_pic
&& model
== TLS_MODEL_LOCAL_DYNAMIC
)
5599 model
= TLS_MODEL_LOCAL_EXEC
;
5603 case TLS_MODEL_LOCAL_DYNAMIC
:
5606 const char *base_name
;
5609 decl
= SYMBOL_REF_DECL (addr
);
5610 base_name
= DTPOFF_ZERO_SYM
;
5611 if (decl
&& bss_initializer_p (decl
))
5612 base_name
= ".tbss";
5614 base
= gen_rtx_SYMBOL_REF (Pmode
, base_name
);
5615 if (strcmp (base_name
, DTPOFF_ZERO_SYM
) == 0)
5619 v
= gen_rtvec (1, addr
);
5622 v
= gen_rtvec (2, addr
, base
);
5623 addr
= gen_rtx_UNSPEC (Pmode
, v
, UNSPEC_TLS_OFF
);
5624 addr
= gen_rtx_CONST (Pmode
, addr
);
5625 base
= arc_legitimize_tls_address (base
, TLS_MODEL_GLOBAL_DYNAMIC
);
5626 return gen_rtx_PLUS (Pmode
, force_reg (Pmode
, base
), addr
);
5628 case TLS_MODEL_GLOBAL_DYNAMIC
:
5629 return arc_emit_call_tls_get_addr (addr
, UNSPEC_TLS_GD
, addr
);
5631 case TLS_MODEL_INITIAL_EXEC
:
5632 addr
= arc_unspec_offset (addr
, UNSPEC_TLS_IE
);
5633 addr
= copy_to_mode_reg (Pmode
, gen_const_mem (Pmode
, addr
));
5634 return gen_rtx_PLUS (Pmode
, arc_get_tp (), addr
);
5636 case TLS_MODEL_LOCAL_EXEC
:
5638 addr
= arc_unspec_offset (addr
, UNSPEC_TLS_OFF
);
5639 return gen_rtx_PLUS (Pmode
, arc_get_tp (), addr
);
5645 /* Legitimize a pic address reference in ORIG.
5646 The return value is the legitimated address.
5647 If OLDX is non-zero, it is the target to assign the address to first. */
5650 arc_legitimize_pic_address (rtx orig
, rtx oldx
)
5659 if (GET_CODE (addr
) == LABEL_REF
)
5661 else if (GET_CODE (addr
) == SYMBOL_REF
)
5663 enum tls_model model
= SYMBOL_REF_TLS_MODEL (addr
);
5665 return arc_legitimize_tls_address (addr
, model
);
5668 else if (CONSTANT_POOL_ADDRESS_P (addr
) || SYMBOL_REF_LOCAL_P (addr
))
5669 return arc_unspec_offset (addr
, ARC_UNSPEC_GOTOFFPC
);
5671 /* This symbol must be referenced via a load from the Global
5672 Offset Table (@GOTPC). */
5673 pat
= arc_unspec_offset (addr
, ARC_UNSPEC_GOT
);
5674 pat
= gen_const_mem (Pmode
, pat
);
5677 oldx
= gen_reg_rtx (Pmode
);
5679 emit_move_insn (oldx
, pat
);
5684 if (GET_CODE (addr
) == CONST
)
5686 addr
= XEXP (addr
, 0);
5687 if (GET_CODE (addr
) == UNSPEC
)
5689 /* Check that the unspec is one of the ones we generate? */
5692 /* fwprop is placing in the REG_EQUIV notes constant pic
5693 unspecs expressions. Then, loop may use these notes for
5694 optimizations resulting in complex patterns that are not
5695 supported by the current implementation. The following
5696 two if-cases are simplifying the complex patters to
5698 else if (GET_CODE (addr
) == MINUS
)
5700 rtx op0
= XEXP (addr
, 0);
5701 rtx op1
= XEXP (addr
, 1);
5703 gcc_assert (GET_CODE (op1
) == UNSPEC
);
5705 emit_move_insn (oldx
,
5706 gen_rtx_CONST (SImode
,
5707 arc_legitimize_pic_address (op1
,
5709 emit_insn (gen_rtx_SET (oldx
, gen_rtx_MINUS (SImode
, op0
, oldx
)));
5713 else if (GET_CODE (addr
) != PLUS
)
5715 rtx tmp
= XEXP (addr
, 0);
5716 enum rtx_code code
= GET_CODE (addr
);
5718 /* It only works for UNARY operations. */
5719 gcc_assert (UNARY_P (addr
));
5720 gcc_assert (GET_CODE (tmp
) == UNSPEC
);
5725 gen_rtx_CONST (SImode
,
5726 arc_legitimize_pic_address (tmp
,
5729 emit_insn (gen_rtx_SET (oldx
,
5730 gen_rtx_fmt_ee (code
, SImode
,
5731 oldx
, const0_rtx
)));
5737 gcc_assert (GET_CODE (addr
) == PLUS
);
5738 if (GET_CODE (XEXP (addr
, 0)) == UNSPEC
)
5743 if (GET_CODE (addr
) == PLUS
)
5745 rtx op0
= XEXP (addr
, 0), op1
= XEXP (addr
, 1);
5747 base
= arc_legitimize_pic_address (op0
, oldx
);
5748 pat
= arc_legitimize_pic_address (op1
,
5749 base
== oldx
? NULL_RTX
: oldx
);
5751 if (base
== op0
&& pat
== op1
)
5754 if (GET_CODE (pat
) == CONST_INT
)
5755 pat
= plus_constant (Pmode
, base
, INTVAL (pat
));
5758 if (GET_CODE (pat
) == PLUS
&& CONSTANT_P (XEXP (pat
, 1)))
5760 base
= gen_rtx_PLUS (Pmode
, base
, XEXP (pat
, 0));
5761 pat
= XEXP (pat
, 1);
5763 pat
= gen_rtx_PLUS (Pmode
, base
, pat
);
5771 /* Output address constant X to FILE, taking PIC into account. */
5774 arc_output_pic_addr_const (FILE * file
, rtx x
, int code
)
5779 switch (GET_CODE (x
))
5789 output_addr_const (file
, x
);
5791 /* Local functions do not get references through the PLT. */
5792 if (code
== 'P' && ! SYMBOL_REF_LOCAL_P (x
))
5793 fputs ("@plt", file
);
5797 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (XEXP (x
, 0)));
5798 assemble_name (file
, buf
);
5802 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (x
));
5803 assemble_name (file
, buf
);
5807 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
5811 arc_output_pic_addr_const (file
, XEXP (x
, 0), code
);
5815 if (GET_MODE (x
) == VOIDmode
)
5817 /* We can use %d if the number is one word and positive. */
5818 if (CONST_DOUBLE_HIGH (x
))
5819 fprintf (file
, HOST_WIDE_INT_PRINT_DOUBLE_HEX
,
5820 CONST_DOUBLE_HIGH (x
), CONST_DOUBLE_LOW (x
));
5821 else if (CONST_DOUBLE_LOW (x
) < 0)
5822 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, CONST_DOUBLE_LOW (x
));
5824 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, CONST_DOUBLE_LOW (x
));
5827 /* We can't handle floating point constants;
5828 PRINT_OPERAND must handle them. */
5829 output_operand_lossage ("floating constant misused");
5833 /* FIXME: Not needed here. */
5834 /* Some assemblers need integer constants to appear last (eg masm). */
5835 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5837 arc_output_pic_addr_const (file
, XEXP (x
, 1), code
);
5838 fprintf (file
, "+");
5839 arc_output_pic_addr_const (file
, XEXP (x
, 0), code
);
5841 else if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
5843 arc_output_pic_addr_const (file
, XEXP (x
, 0), code
);
5844 if (INTVAL (XEXP (x
, 1)) >= 0)
5845 fprintf (file
, "+");
5846 arc_output_pic_addr_const (file
, XEXP (x
, 1), code
);
5853 /* Avoid outputting things like x-x or x+5-x,
5854 since some assemblers can't handle that. */
5855 x
= simplify_subtraction (x
);
5856 if (GET_CODE (x
) != MINUS
)
5859 arc_output_pic_addr_const (file
, XEXP (x
, 0), code
);
5860 fprintf (file
, "-");
5861 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
5862 && INTVAL (XEXP (x
, 1)) < 0)
5864 fprintf (file
, "(");
5865 arc_output_pic_addr_const (file
, XEXP (x
, 1), code
);
5866 fprintf (file
, ")");
5869 arc_output_pic_addr_const (file
, XEXP (x
, 1), code
);
5874 arc_output_pic_addr_const (file
, XEXP (x
, 0), code
);
5880 bool pcrel
; pcrel
= false;
5881 rtx base
; base
= NULL
;
5882 gcc_assert (XVECLEN (x
, 0) >= 1);
5883 switch (XINT (x
, 1))
5885 case ARC_UNSPEC_GOT
:
5886 suffix
= "@gotpc", pcrel
= true;
5888 case ARC_UNSPEC_GOTOFF
:
5891 case ARC_UNSPEC_GOTOFFPC
:
5892 suffix
= "@pcl", pcrel
= true;
5894 case ARC_UNSPEC_PLT
:
5898 suffix
= "@tlsgd", pcrel
= true;
5901 suffix
= "@tlsie", pcrel
= true;
5903 case UNSPEC_TLS_OFF
:
5904 if (XVECLEN (x
, 0) == 2)
5905 base
= XVECEXP (x
, 0, 1);
5906 if (SYMBOL_REF_TLS_MODEL (XVECEXP (x
, 0, 0)) == TLS_MODEL_LOCAL_EXEC
5907 || (!flag_pic
&& !base
))
5913 suffix
= "@invalid";
5914 output_operand_lossage ("invalid UNSPEC as operand: %d", XINT (x
,1));
5918 fputs ("pcl,", file
);
5919 arc_output_pic_addr_const (file
, XVECEXP (x
, 0, 0), code
);
5920 fputs (suffix
, file
);
5922 arc_output_pic_addr_const (file
, base
, code
);
5926 output_operand_lossage ("invalid expression as operand");
5930 #define SYMBOLIC_CONST(X) \
5931 (GET_CODE (X) == SYMBOL_REF \
5932 || GET_CODE (X) == LABEL_REF \
5933 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
5935 /* Emit insns to move operands[1] into operands[0]. */
5938 prepare_pic_move (rtx
*operands
, machine_mode
)
5940 if (GET_CODE (operands
[0]) == MEM
&& SYMBOLIC_CONST (operands
[1])
5942 operands
[1] = force_reg (Pmode
, operands
[1]);
5945 rtx temp
= (reload_in_progress
? operands
[0]
5946 : flag_pic
? gen_reg_rtx (Pmode
) : NULL_RTX
);
5947 operands
[1] = arc_legitimize_pic_address (operands
[1], temp
);
5952 /* The function returning the number of words, at the beginning of an
5953 argument, must be put in registers. The returned value must be
5954 zero for arguments that are passed entirely in registers or that
5955 are entirely pushed on the stack.
5957 On some machines, certain arguments must be passed partially in
5958 registers and partially in memory. On these machines, typically
5959 the first N words of arguments are passed in registers, and the
5960 rest on the stack. If a multi-word argument (a `double' or a
5961 structure) crosses that boundary, its first few words must be
5962 passed in registers and the rest must be pushed. This function
5963 tells the compiler when this occurs, and how many of the words
5964 should go in registers.
5966 `FUNCTION_ARG' for these arguments should return the first register
5967 to be used by the caller for this argument; likewise
5968 `FUNCTION_INCOMING_ARG', for the called function.
5970 The function is used to implement macro FUNCTION_ARG_PARTIAL_NREGS. */
5972 /* If REGNO is the least arg reg available then what is the total number of arg
5974 #define GPR_REST_ARG_REGS(REGNO) \
5975 ((REGNO) <= MAX_ARC_PARM_REGS ? MAX_ARC_PARM_REGS - (REGNO) : 0 )
5977 /* Since arc parm regs are contiguous. */
5978 #define ARC_NEXT_ARG_REG(REGNO) ( (REGNO) + 1 )
5980 /* Implement TARGET_ARG_PARTIAL_BYTES. */
5983 arc_arg_partial_bytes (cumulative_args_t cum_v
, machine_mode mode
,
5984 tree type
, bool named ATTRIBUTE_UNUSED
)
5986 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
5987 int bytes
= (mode
== BLKmode
5988 ? int_size_in_bytes (type
) : (int) GET_MODE_SIZE (mode
));
5989 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
5993 arg_num
= ROUND_ADVANCE_CUM (arg_num
, mode
, type
);
5994 ret
= GPR_REST_ARG_REGS (arg_num
);
5996 /* ICEd at function.c:2361, and ret is copied to data->partial */
5997 ret
= (ret
>= words
? 0 : ret
* UNITS_PER_WORD
);
6002 /* This function is used to control a function argument is passed in a
6003 register, and which register.
6005 The arguments are CUM, of type CUMULATIVE_ARGS, which summarizes
6006 (in a way defined by INIT_CUMULATIVE_ARGS and FUNCTION_ARG_ADVANCE)
6007 all of the previous arguments so far passed in registers; MODE, the
6008 machine mode of the argument; TYPE, the data type of the argument
6009 as a tree node or 0 if that is not known (which happens for C
6010 support library functions); and NAMED, which is 1 for an ordinary
6011 argument and 0 for nameless arguments that correspond to `...' in
6012 the called function's prototype.
6014 The returned value should either be a `reg' RTX for the hard
6015 register in which to pass the argument, or zero to pass the
6016 argument on the stack.
6018 For machines like the Vax and 68000, where normally all arguments
6019 are pushed, zero suffices as a definition.
6021 The usual way to make the ANSI library `stdarg.h' work on a machine
6022 where some arguments are usually passed in registers, is to cause
6023 nameless arguments to be passed on the stack instead. This is done
6024 by making the function return 0 whenever NAMED is 0.
6026 You may use the macro `MUST_PASS_IN_STACK (MODE, TYPE)' in the
6027 definition of this function to determine if this argument is of a
6028 type that must be passed in the stack. If `REG_PARM_STACK_SPACE'
6029 is not defined and the function returns non-zero for such an
6030 argument, the compiler will abort. If `REG_PARM_STACK_SPACE' is
6031 defined, the argument will be computed in the stack and then loaded
6034 The function is used to implement macro FUNCTION_ARG. */
6035 /* On the ARC the first MAX_ARC_PARM_REGS args are normally in registers
6036 and the rest are pushed. */
6039 arc_function_arg (cumulative_args_t cum_v
,
6041 const_tree type ATTRIBUTE_UNUSED
,
6042 bool named ATTRIBUTE_UNUSED
)
6044 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
6047 const char *debstr ATTRIBUTE_UNUSED
;
6049 arg_num
= ROUND_ADVANCE_CUM (arg_num
, mode
, type
);
6050 /* Return a marker for use in the call instruction. */
6051 if (mode
== VOIDmode
)
6056 else if (GPR_REST_ARG_REGS (arg_num
) > 0)
6058 ret
= gen_rtx_REG (mode
, arg_num
);
6059 debstr
= reg_names
[arg_num
];
6069 /* The function to update the summarizer variable *CUM to advance past
6070 an argument in the argument list. The values MODE, TYPE and NAMED
6071 describe that argument. Once this is done, the variable *CUM is
6072 suitable for analyzing the *following* argument with
6073 `FUNCTION_ARG', etc.
6075 This function need not do anything if the argument in question was
6076 passed on the stack. The compiler knows how to track the amount of
6077 stack space used for arguments without any special help.
6079 The function is used to implement macro FUNCTION_ARG_ADVANCE. */
6080 /* For the ARC: the cum set here is passed on to function_arg where we
6081 look at its value and say which reg to use. Strategy: advance the
6082 regnumber here till we run out of arg regs, then set *cum to last
6083 reg. In function_arg, since *cum > last arg reg we would return 0
6084 and thus the arg will end up on the stack. For straddling args of
6085 course function_arg_partial_nregs will come into play. */
6088 arc_function_arg_advance (cumulative_args_t cum_v
,
6091 bool named ATTRIBUTE_UNUSED
)
6093 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
6094 int bytes
= (mode
== BLKmode
6095 ? int_size_in_bytes (type
) : (int) GET_MODE_SIZE (mode
));
6096 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
6100 *cum
= ROUND_ADVANCE_CUM (*cum
, mode
, type
);
6101 for (i
= 0; i
< words
; i
++)
6102 *cum
= ARC_NEXT_ARG_REG (*cum
);
6106 /* Define how to find the value returned by a function.
6107 VALTYPE is the data type of the value (as a tree).
6108 If the precise function being called is known, FN_DECL_OR_TYPE is its
6109 FUNCTION_DECL; otherwise, FN_DECL_OR_TYPE is its type. */
6112 arc_function_value (const_tree valtype
,
6113 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
6114 bool outgoing ATTRIBUTE_UNUSED
)
6116 machine_mode mode
= TYPE_MODE (valtype
);
6117 int unsignedp ATTRIBUTE_UNUSED
;
6119 unsignedp
= TYPE_UNSIGNED (valtype
);
6120 if (INTEGRAL_TYPE_P (valtype
) || TREE_CODE (valtype
) == OFFSET_TYPE
)
6121 PROMOTE_MODE (mode
, unsignedp
, valtype
);
6122 return gen_rtx_REG (mode
, 0);
6125 /* Returns the return address that is used by builtin_return_address. */
6128 arc_return_addr_rtx (int count
, ATTRIBUTE_UNUSED rtx frame
)
6133 return get_hard_reg_initial_val (Pmode
, RETURN_ADDR_REGNUM
);
6136 /* Determine if a given RTX is a valid constant. We already know this
6137 satisfies CONSTANT_P. */
6140 arc_legitimate_constant_p (machine_mode mode
, rtx x
)
6142 switch (GET_CODE (x
))
6147 if (arc_legitimate_pic_addr_p (x
))
6150 return arc_legitimate_constant_p (mode
, XEXP (x
, 0));
6153 if (SYMBOL_REF_TLS_MODEL (x
))
6165 return arc_legitimate_constant_p (mode
, XEXP (x
, 0));
6170 bool t1
= arc_legitimate_constant_p (mode
, XEXP (x
, 0));
6171 bool t2
= arc_legitimate_constant_p (mode
, XEXP (x
, 1));
6180 return TARGET_PLUS_DMPY
;
6183 return TARGET_PLUS_QMACW
;
6189 switch (XINT (x
, 1))
6192 case UNSPEC_TLS_OFF
:
6196 /* Any other unspec ending here are pic related, hence the above
6197 constant pic address checking returned false. */
6203 fatal_insn ("unrecognized supposed constant", x
);
6210 arc_legitimate_address_p (machine_mode mode
, rtx x
, bool strict
)
6212 if (RTX_OK_FOR_BASE_P (x
, strict
))
6214 if (legitimate_offset_address_p (mode
, x
, TARGET_INDEXED_LOADS
, strict
))
6216 if (legitimate_scaled_address_p (mode
, x
, strict
))
6218 if (legitimate_small_data_address_p (x
))
6220 if (GET_CODE (x
) == CONST_INT
&& LARGE_INT (INTVAL (x
)))
6223 /* When we compile for size avoid const (@sym + offset)
6225 if (!flag_pic
&& optimize_size
&& !reload_completed
6226 && (GET_CODE (x
) == CONST
)
6227 && (GET_CODE (XEXP (x
, 0)) == PLUS
)
6228 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
)
6229 && SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x
, 0), 0)) == 0
6230 && !SYMBOL_REF_FUNCTION_P (XEXP (XEXP (x
, 0), 0)))
6232 rtx addend
= XEXP (XEXP (x
, 0), 1);
6233 gcc_assert (CONST_INT_P (addend
));
6234 HOST_WIDE_INT offset
= INTVAL (addend
);
6236 /* Allow addresses having a large offset to pass. Anyhow they
6237 will end in a limm. */
6238 return !(offset
> -1024 && offset
< 1020);
6241 if ((GET_MODE_SIZE (mode
) != 16) && CONSTANT_P (x
))
6243 return arc_legitimate_constant_p (mode
, x
);
6245 if ((GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == PRE_INC
6246 || GET_CODE (x
) == POST_DEC
|| GET_CODE (x
) == POST_INC
)
6247 && RTX_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
6249 /* We're restricted here by the `st' insn. */
6250 if ((GET_CODE (x
) == PRE_MODIFY
|| GET_CODE (x
) == POST_MODIFY
)
6251 && GET_CODE (XEXP ((x
), 1)) == PLUS
6252 && rtx_equal_p (XEXP ((x
), 0), XEXP (XEXP (x
, 1), 0))
6253 && legitimate_offset_address_p (QImode
, XEXP (x
, 1),
6254 TARGET_AUTO_MODIFY_REG
, strict
))
6259 /* Return true iff ADDR (a legitimate address expression)
6260 has an effect that depends on the machine mode it is used for. */
6263 arc_mode_dependent_address_p (const_rtx addr
, addr_space_t
)
6265 /* SYMBOL_REF is not mode dependent: it is either a small data reference,
6266 which is valid for loads and stores, or a limm offset, which is valid for
6267 loads. Scaled indices are scaled by the access mode. */
6268 if (GET_CODE (addr
) == PLUS
6269 && GET_CODE (XEXP ((addr
), 0)) == MULT
)
6274 /* Determine if it's legal to put X into the constant pool. */
6277 arc_cannot_force_const_mem (machine_mode mode
, rtx x
)
6279 return !arc_legitimate_constant_p (mode
, x
);
6282 /* IDs for all the ARC builtins. */
6286 #define DEF_BUILTIN(NAME, N_ARGS, TYPE, ICODE, MASK) \
6287 ARC_BUILTIN_ ## NAME,
6288 #include "builtins.def"
6294 struct GTY(()) arc_builtin_description
6296 enum insn_code icode
;
6301 static GTY(()) struct arc_builtin_description
6302 arc_bdesc
[ARC_BUILTIN_COUNT
] =
6304 #define DEF_BUILTIN(NAME, N_ARGS, TYPE, ICODE, MASK) \
6305 { (enum insn_code) CODE_FOR_ ## ICODE, N_ARGS, NULL_TREE },
6306 #include "builtins.def"
6310 /* Transform UP into lowercase and write the result to LO.
6311 You must provide enough space for LO. Return LO. */
6314 arc_tolower (char *lo
, const char *up
)
6318 for (; *up
; up
++, lo
++)
6319 *lo
= TOLOWER (*up
);
6326 /* Implement `TARGET_BUILTIN_DECL'. */
6329 arc_builtin_decl (unsigned id
, bool initialize_p ATTRIBUTE_UNUSED
)
6331 if (id
< ARC_BUILTIN_COUNT
)
6332 return arc_bdesc
[id
].fndecl
;
6334 return error_mark_node
;
6338 arc_init_builtins (void)
6340 tree V4HI_type_node
;
6341 tree V2SI_type_node
;
6342 tree V2HI_type_node
;
6344 /* Vector types based on HS SIMD elements. */
6345 V4HI_type_node
= build_vector_type_for_mode (intHI_type_node
, V4HImode
);
6346 V2SI_type_node
= build_vector_type_for_mode (intSI_type_node
, V2SImode
);
6347 V2HI_type_node
= build_vector_type_for_mode (intHI_type_node
, V2HImode
);
6349 tree pcvoid_type_node
6350 = build_pointer_type (build_qualified_type (void_type_node
,
6352 tree V8HI_type_node
= build_vector_type_for_mode (intHI_type_node
,
6355 tree void_ftype_void
6356 = build_function_type_list (void_type_node
, NULL_TREE
);
6358 = build_function_type_list (integer_type_node
, integer_type_node
,
6360 tree int_ftype_pcvoid_int
6361 = build_function_type_list (integer_type_node
, pcvoid_type_node
,
6362 integer_type_node
, NULL_TREE
);
6363 tree void_ftype_usint_usint
6364 = build_function_type_list (void_type_node
, long_unsigned_type_node
,
6365 long_unsigned_type_node
, NULL_TREE
);
6366 tree int_ftype_int_int
6367 = build_function_type_list (integer_type_node
, integer_type_node
,
6368 integer_type_node
, NULL_TREE
);
6369 tree usint_ftype_usint
6370 = build_function_type_list (long_unsigned_type_node
,
6371 long_unsigned_type_node
, NULL_TREE
);
6372 tree void_ftype_usint
6373 = build_function_type_list (void_type_node
, long_unsigned_type_node
,
6376 = build_function_type_list (integer_type_node
, void_type_node
,
6379 = build_function_type_list (void_type_node
, integer_type_node
,
6381 tree int_ftype_short
6382 = build_function_type_list (integer_type_node
, short_integer_type_node
,
6385 /* Old ARC SIMD types. */
6386 tree v8hi_ftype_v8hi_v8hi
6387 = build_function_type_list (V8HI_type_node
, V8HI_type_node
,
6388 V8HI_type_node
, NULL_TREE
);
6389 tree v8hi_ftype_v8hi_int
6390 = build_function_type_list (V8HI_type_node
, V8HI_type_node
,
6391 integer_type_node
, NULL_TREE
);
6392 tree v8hi_ftype_v8hi_int_int
6393 = build_function_type_list (V8HI_type_node
, V8HI_type_node
,
6394 integer_type_node
, integer_type_node
,
6396 tree void_ftype_v8hi_int_int
6397 = build_function_type_list (void_type_node
, V8HI_type_node
,
6398 integer_type_node
, integer_type_node
,
6400 tree void_ftype_v8hi_int_int_int
6401 = build_function_type_list (void_type_node
, V8HI_type_node
,
6402 integer_type_node
, integer_type_node
,
6403 integer_type_node
, NULL_TREE
);
6404 tree v8hi_ftype_int_int
6405 = build_function_type_list (V8HI_type_node
, integer_type_node
,
6406 integer_type_node
, NULL_TREE
);
6407 tree void_ftype_int_int
6408 = build_function_type_list (void_type_node
, integer_type_node
,
6409 integer_type_node
, NULL_TREE
);
6410 tree v8hi_ftype_v8hi
6411 = build_function_type_list (V8HI_type_node
, V8HI_type_node
,
6413 /* ARCv2 SIMD types. */
6414 tree long_ftype_v4hi_v4hi
6415 = build_function_type_list (long_long_integer_type_node
,
6416 V4HI_type_node
, V4HI_type_node
, NULL_TREE
);
6417 tree int_ftype_v2hi_v2hi
6418 = build_function_type_list (integer_type_node
,
6419 V2HI_type_node
, V2HI_type_node
, NULL_TREE
);
6420 tree v2si_ftype_v2hi_v2hi
6421 = build_function_type_list (V2SI_type_node
,
6422 V2HI_type_node
, V2HI_type_node
, NULL_TREE
);
6423 tree v2hi_ftype_v2hi_v2hi
6424 = build_function_type_list (V2HI_type_node
,
6425 V2HI_type_node
, V2HI_type_node
, NULL_TREE
);
6426 tree v2si_ftype_v2si_v2si
6427 = build_function_type_list (V2SI_type_node
,
6428 V2SI_type_node
, V2SI_type_node
, NULL_TREE
);
6429 tree v4hi_ftype_v4hi_v4hi
6430 = build_function_type_list (V4HI_type_node
,
6431 V4HI_type_node
, V4HI_type_node
, NULL_TREE
);
6432 tree long_ftype_v2si_v2hi
6433 = build_function_type_list (long_long_integer_type_node
,
6434 V2SI_type_node
, V2HI_type_node
, NULL_TREE
);
6436 /* Add the builtins. */
6437 #define DEF_BUILTIN(NAME, N_ARGS, TYPE, ICODE, MASK) \
6439 int id = ARC_BUILTIN_ ## NAME; \
6440 const char *Name = "__builtin_arc_" #NAME; \
6441 char *name = (char*) alloca (1 + strlen (Name)); \
6443 gcc_assert (id < ARC_BUILTIN_COUNT); \
6445 arc_bdesc[id].fndecl \
6446 = add_builtin_function (arc_tolower(name, Name), TYPE, id, \
6447 BUILT_IN_MD, NULL, NULL_TREE); \
6449 #include "builtins.def"
6453 /* Helper to expand __builtin_arc_aligned (void* val, int
6457 arc_expand_builtin_aligned (tree exp
)
6459 tree arg0
= CALL_EXPR_ARG (exp
, 0);
6460 tree arg1
= CALL_EXPR_ARG (exp
, 1);
6462 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
6463 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
6465 if (!CONST_INT_P (op1
))
6467 /* If we can't fold the alignment to a constant integer
6468 whilst optimizing, this is probably a user error. */
6470 warning (0, "__builtin_arc_aligned with non-constant alignment");
6474 HOST_WIDE_INT alignTest
= INTVAL (op1
);
6475 /* Check alignTest is positive, and a power of two. */
6476 if (alignTest
<= 0 || alignTest
!= (alignTest
& -alignTest
))
6478 error ("invalid alignment value for __builtin_arc_aligned");
6482 if (CONST_INT_P (op0
))
6484 HOST_WIDE_INT pnt
= INTVAL (op0
);
6486 if ((pnt
& (alignTest
- 1)) == 0)
6491 unsigned align
= get_pointer_alignment (arg0
);
6492 unsigned numBits
= alignTest
* BITS_PER_UNIT
;
6494 if (align
&& align
>= numBits
)
6496 /* Another attempt to ascertain alignment. Check the type
6497 we are pointing to. */
6498 if (POINTER_TYPE_P (TREE_TYPE (arg0
))
6499 && TYPE_ALIGN (TREE_TYPE (TREE_TYPE (arg0
))) >= numBits
)
6504 /* Default to false. */
6508 /* Helper arc_expand_builtin, generates a pattern for the given icode
6512 apply_GEN_FCN (enum insn_code icode
, rtx
*arg
)
6514 switch (insn_data
[icode
].n_generator_args
)
6517 return GEN_FCN (icode
) ();
6519 return GEN_FCN (icode
) (arg
[0]);
6521 return GEN_FCN (icode
) (arg
[0], arg
[1]);
6523 return GEN_FCN (icode
) (arg
[0], arg
[1], arg
[2]);
6525 return GEN_FCN (icode
) (arg
[0], arg
[1], arg
[2], arg
[3]);
6527 return GEN_FCN (icode
) (arg
[0], arg
[1], arg
[2], arg
[3], arg
[4]);
6533 /* Expand an expression EXP that calls a built-in function,
6534 with result going to TARGET if that's convenient
6535 (and in mode MODE if that's convenient).
6536 SUBTARGET may be used as the target for computing one of EXP's operands.
6537 IGNORE is nonzero if the value is to be ignored. */
6540 arc_expand_builtin (tree exp
,
6542 rtx subtarget ATTRIBUTE_UNUSED
,
6543 machine_mode mode ATTRIBUTE_UNUSED
,
6544 int ignore ATTRIBUTE_UNUSED
)
6546 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
6547 unsigned int id
= DECL_FUNCTION_CODE (fndecl
);
6548 const struct arc_builtin_description
*d
= &arc_bdesc
[id
];
6549 int i
, j
, n_args
= call_expr_nargs (exp
);
6552 enum insn_code icode
= d
->icode
;
6553 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6570 if (id
>= ARC_BUILTIN_COUNT
)
6571 internal_error ("bad builtin fcode");
6573 /* 1st part: Expand special builtins. */
6576 case ARC_BUILTIN_NOP
:
6577 emit_insn (gen_nopv ());
6580 case ARC_BUILTIN_RTIE
:
6581 case ARC_BUILTIN_SYNC
:
6582 case ARC_BUILTIN_BRK
:
6583 case ARC_BUILTIN_SWI
:
6584 case ARC_BUILTIN_UNIMP_S
:
6585 gcc_assert (icode
!= 0);
6586 emit_insn (GEN_FCN (icode
) (const1_rtx
));
6589 case ARC_BUILTIN_ALIGNED
:
6590 return arc_expand_builtin_aligned (exp
);
6592 case ARC_BUILTIN_CLRI
:
6593 target
= gen_reg_rtx (SImode
);
6594 emit_insn (gen_clri (target
, const1_rtx
));
6597 case ARC_BUILTIN_TRAP_S
:
6598 case ARC_BUILTIN_SLEEP
:
6599 arg0
= CALL_EXPR_ARG (exp
, 0);
6601 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
6603 gcc_assert (icode
!= 0);
6604 emit_insn (GEN_FCN (icode
) (op0
));
6607 case ARC_BUILTIN_VDORUN
:
6608 case ARC_BUILTIN_VDIRUN
:
6609 arg0
= CALL_EXPR_ARG (exp
, 0);
6610 arg1
= CALL_EXPR_ARG (exp
, 1);
6611 op0
= expand_expr (arg0
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
6612 op1
= expand_expr (arg1
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
6614 target
= gen_rtx_REG (SImode
, (id
== ARC_BUILTIN_VDIRUN
) ? 131 : 139);
6616 mode0
= insn_data
[icode
].operand
[1].mode
;
6617 mode1
= insn_data
[icode
].operand
[2].mode
;
6619 if (!insn_data
[icode
].operand
[1].predicate (op0
, mode0
))
6620 op0
= copy_to_mode_reg (mode0
, op0
);
6622 if (!insn_data
[icode
].operand
[2].predicate (op1
, mode1
))
6623 op1
= copy_to_mode_reg (mode1
, op1
);
6625 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
6632 case ARC_BUILTIN_VDIWR
:
6633 case ARC_BUILTIN_VDOWR
:
6634 arg0
= CALL_EXPR_ARG (exp
, 0);
6635 arg1
= CALL_EXPR_ARG (exp
, 1);
6636 op0
= expand_expr (arg0
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
6637 op1
= expand_expr (arg1
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
6639 if (!CONST_INT_P (op0
)
6640 || !(UNSIGNED_INT3 (INTVAL (op0
))))
6641 error ("operand 1 should be an unsigned 3-bit immediate");
6643 mode1
= insn_data
[icode
].operand
[1].mode
;
6645 if (icode
== CODE_FOR_vdiwr_insn
)
6646 target
= gen_rtx_REG (SImode
,
6647 ARC_FIRST_SIMD_DMA_CONFIG_IN_REG
+ INTVAL (op0
));
6648 else if (icode
== CODE_FOR_vdowr_insn
)
6649 target
= gen_rtx_REG (SImode
,
6650 ARC_FIRST_SIMD_DMA_CONFIG_OUT_REG
+ INTVAL (op0
));
6654 if (!insn_data
[icode
].operand
[2].predicate (op1
, mode1
))
6655 op1
= copy_to_mode_reg (mode1
, op1
);
6657 pat
= GEN_FCN (icode
) (target
, op1
);
6664 case ARC_BUILTIN_VASRW
:
6665 case ARC_BUILTIN_VSR8
:
6666 case ARC_BUILTIN_VSR8AW
:
6667 arg0
= CALL_EXPR_ARG (exp
, 0);
6668 arg1
= CALL_EXPR_ARG (exp
, 1);
6669 op0
= expand_expr (arg0
, NULL_RTX
, V8HImode
, EXPAND_NORMAL
);
6670 op1
= expand_expr (arg1
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
6671 op2
= gen_rtx_REG (V8HImode
, ARC_FIRST_SIMD_VR_REG
);
6673 target
= gen_reg_rtx (V8HImode
);
6674 mode0
= insn_data
[icode
].operand
[1].mode
;
6675 mode1
= insn_data
[icode
].operand
[2].mode
;
6677 if (!insn_data
[icode
].operand
[1].predicate (op0
, mode0
))
6678 op0
= copy_to_mode_reg (mode0
, op0
);
6680 if ((!insn_data
[icode
].operand
[2].predicate (op1
, mode1
))
6681 || !(UNSIGNED_INT3 (INTVAL (op1
))))
6682 error ("operand 2 should be an unsigned 3-bit value (I0-I7)");
6684 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
6691 case ARC_BUILTIN_VLD32WH
:
6692 case ARC_BUILTIN_VLD32WL
:
6693 case ARC_BUILTIN_VLD64
:
6694 case ARC_BUILTIN_VLD32
:
6697 arg0
= CALL_EXPR_ARG (exp
, 0); /* source vreg. */
6698 arg1
= CALL_EXPR_ARG (exp
, 1); /* [I]0-7. */
6699 arg2
= CALL_EXPR_ARG (exp
, 2); /* u8. */
6701 src_vreg
= expand_expr (arg0
, NULL_RTX
, V8HImode
, EXPAND_NORMAL
);
6702 op0
= expand_expr (arg1
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
6703 op1
= expand_expr (arg2
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
6704 op2
= gen_rtx_REG (V8HImode
, ARC_FIRST_SIMD_VR_REG
);
6706 /* target <- src vreg. */
6707 emit_insn (gen_move_insn (target
, src_vreg
));
6709 /* target <- vec_concat: target, mem (Ib, u8). */
6710 mode0
= insn_data
[icode
].operand
[3].mode
;
6711 mode1
= insn_data
[icode
].operand
[1].mode
;
6713 if ((!insn_data
[icode
].operand
[3].predicate (op0
, mode0
))
6714 || !(UNSIGNED_INT3 (INTVAL (op0
))))
6715 error ("operand 1 should be an unsigned 3-bit value (I0-I7)");
6717 if ((!insn_data
[icode
].operand
[1].predicate (op1
, mode1
))
6718 || !(UNSIGNED_INT8 (INTVAL (op1
))))
6719 error ("operand 2 should be an unsigned 8-bit value");
6721 pat
= GEN_FCN (icode
) (target
, op1
, op2
, op0
);
6728 case ARC_BUILTIN_VLD64W
:
6729 case ARC_BUILTIN_VLD128
:
6730 arg0
= CALL_EXPR_ARG (exp
, 0); /* dest vreg. */
6731 arg1
= CALL_EXPR_ARG (exp
, 1); /* [I]0-7. */
6733 op0
= gen_rtx_REG (V8HImode
, ARC_FIRST_SIMD_VR_REG
);
6734 op1
= expand_expr (arg0
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
6735 op2
= expand_expr (arg1
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
6737 /* target <- src vreg. */
6738 target
= gen_reg_rtx (V8HImode
);
6740 /* target <- vec_concat: target, mem (Ib, u8). */
6741 mode0
= insn_data
[icode
].operand
[1].mode
;
6742 mode1
= insn_data
[icode
].operand
[2].mode
;
6743 mode2
= insn_data
[icode
].operand
[3].mode
;
6745 if ((!insn_data
[icode
].operand
[2].predicate (op1
, mode1
))
6746 || !(UNSIGNED_INT3 (INTVAL (op1
))))
6747 error ("operand 1 should be an unsigned 3-bit value (I0-I7)");
6749 if ((!insn_data
[icode
].operand
[3].predicate (op2
, mode2
))
6750 || !(UNSIGNED_INT8 (INTVAL (op2
))))
6751 error ("operand 2 should be an unsigned 8-bit value");
6753 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
6761 case ARC_BUILTIN_VST128
:
6762 case ARC_BUILTIN_VST64
:
6763 arg0
= CALL_EXPR_ARG (exp
, 0); /* src vreg. */
6764 arg1
= CALL_EXPR_ARG (exp
, 1); /* [I]0-7. */
6765 arg2
= CALL_EXPR_ARG (exp
, 2); /* u8. */
6767 op0
= gen_rtx_REG (V8HImode
, ARC_FIRST_SIMD_VR_REG
);
6768 op1
= expand_expr (arg1
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
6769 op2
= expand_expr (arg2
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
6770 op3
= expand_expr (arg0
, NULL_RTX
, V8HImode
, EXPAND_NORMAL
);
6772 mode0
= insn_data
[icode
].operand
[0].mode
;
6773 mode1
= insn_data
[icode
].operand
[1].mode
;
6774 mode2
= insn_data
[icode
].operand
[2].mode
;
6775 mode3
= insn_data
[icode
].operand
[3].mode
;
6777 if ((!insn_data
[icode
].operand
[1].predicate (op1
, mode1
))
6778 || !(UNSIGNED_INT3 (INTVAL (op1
))))
6779 error ("operand 2 should be an unsigned 3-bit value (I0-I7)");
6781 if ((!insn_data
[icode
].operand
[2].predicate (op2
, mode2
))
6782 || !(UNSIGNED_INT8 (INTVAL (op2
))))
6783 error ("operand 3 should be an unsigned 8-bit value");
6785 if (!insn_data
[icode
].operand
[3].predicate (op3
, mode3
))
6786 op3
= copy_to_mode_reg (mode3
, op3
);
6788 pat
= GEN_FCN (icode
) (op0
, op1
, op2
, op3
);
6795 case ARC_BUILTIN_VST16_N
:
6796 case ARC_BUILTIN_VST32_N
:
6797 arg0
= CALL_EXPR_ARG (exp
, 0); /* source vreg. */
6798 arg1
= CALL_EXPR_ARG (exp
, 1); /* u3. */
6799 arg2
= CALL_EXPR_ARG (exp
, 2); /* [I]0-7. */
6800 arg3
= CALL_EXPR_ARG (exp
, 3); /* u8. */
6802 op0
= expand_expr (arg3
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
6803 op1
= gen_rtx_REG (V8HImode
, ARC_FIRST_SIMD_VR_REG
);
6804 op2
= expand_expr (arg2
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
6805 op3
= expand_expr (arg0
, NULL_RTX
, V8HImode
, EXPAND_NORMAL
);
6806 op4
= expand_expr (arg1
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
6808 mode0
= insn_data
[icode
].operand
[0].mode
;
6809 mode2
= insn_data
[icode
].operand
[2].mode
;
6810 mode3
= insn_data
[icode
].operand
[3].mode
;
6811 mode4
= insn_data
[icode
].operand
[4].mode
;
6813 /* Do some correctness checks for the operands. */
6814 if ((!insn_data
[icode
].operand
[0].predicate (op0
, mode0
))
6815 || !(UNSIGNED_INT8 (INTVAL (op0
))))
6816 error ("operand 4 should be an unsigned 8-bit value (0-255)");
6818 if ((!insn_data
[icode
].operand
[2].predicate (op2
, mode2
))
6819 || !(UNSIGNED_INT3 (INTVAL (op2
))))
6820 error ("operand 3 should be an unsigned 3-bit value (I0-I7)");
6822 if (!insn_data
[icode
].operand
[3].predicate (op3
, mode3
))
6823 op3
= copy_to_mode_reg (mode3
, op3
);
6825 if ((!insn_data
[icode
].operand
[4].predicate (op4
, mode4
))
6826 || !(UNSIGNED_INT3 (INTVAL (op4
))))
6827 error ("operand 2 should be an unsigned 3-bit value (subreg 0-7)");
6828 else if (icode
== CODE_FOR_vst32_n_insn
6829 && ((INTVAL (op4
) % 2) != 0))
6830 error ("operand 2 should be an even 3-bit value (subreg 0,2,4,6)");
6832 pat
= GEN_FCN (icode
) (op0
, op1
, op2
, op3
, op4
);
6843 /* 2nd part: Expand regular builtins. */
6845 internal_error ("bad builtin fcode");
6847 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
6852 if (target
== NULL_RTX
6853 || GET_MODE (target
) != tmode
6854 || !insn_data
[icode
].operand
[0].predicate (target
, tmode
))
6856 target
= gen_reg_rtx (tmode
);
6861 gcc_assert (n_args
<= 4);
6862 for (i
= 0; i
< n_args
; i
++, j
++)
6864 tree arg
= CALL_EXPR_ARG (exp
, i
);
6865 machine_mode mode
= insn_data
[icode
].operand
[j
].mode
;
6866 rtx op
= expand_expr (arg
, NULL_RTX
, mode
, EXPAND_NORMAL
);
6867 machine_mode opmode
= GET_MODE (op
);
6868 char c
= insn_data
[icode
].operand
[j
].constraint
[0];
6870 /* SIMD extension requires exact immediate operand match. */
6871 if ((id
> ARC_BUILTIN_SIMD_BEGIN
)
6872 && (id
< ARC_BUILTIN_SIMD_END
)
6876 if (!CONST_INT_P (op
))
6877 error ("builtin requires an immediate for operand %d", j
);
6881 if (!satisfies_constraint_L (op
))
6882 error ("operand %d should be a 6 bit unsigned immediate", j
);
6885 if (!satisfies_constraint_P (op
))
6886 error ("operand %d should be a 8 bit unsigned immediate", j
);
6889 if (!satisfies_constraint_K (op
))
6890 error ("operand %d should be a 3 bit unsigned immediate", j
);
6893 error ("unknown builtin immediate operand type for operand %d",
6898 if (CONST_INT_P (op
))
6901 if ((opmode
== SImode
) && (mode
== HImode
))
6904 op
= gen_lowpart (HImode
, op
);
6907 /* In case the insn wants input operands in modes different from
6908 the result, abort. */
6909 gcc_assert (opmode
== mode
|| opmode
== VOIDmode
);
6911 if (!insn_data
[icode
].operand
[i
+ nonvoid
].predicate (op
, mode
))
6912 op
= copy_to_mode_reg (mode
, op
);
6917 pat
= apply_GEN_FCN (icode
, xop
);
6918 if (pat
== NULL_RTX
)
6929 /* Returns true if the operands[opno] is a valid compile-time constant to be
6930 used as register number in the code for builtins. Else it flags an error
6931 and returns false. */
6934 check_if_valid_regno_const (rtx
*operands
, int opno
)
6937 switch (GET_CODE (operands
[opno
]))
6944 error ("register number must be a compile-time constant. Try giving higher optimization levels");
6950 /* Return true if it is ok to make a tail-call to DECL. */
6953 arc_function_ok_for_sibcall (tree decl
,
6954 tree exp ATTRIBUTE_UNUSED
)
6956 tree attrs
= NULL_TREE
;
6958 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
6959 if (ARC_INTERRUPT_P (arc_compute_function_type (cfun
)))
6964 attrs
= TYPE_ATTRIBUTES (TREE_TYPE (decl
));
6966 if (lookup_attribute ("jli_always", attrs
))
6968 if (lookup_attribute ("jli_fixed", attrs
))
6970 if (lookup_attribute ("secure_call", attrs
))
6974 /* Everything else is ok. */
6978 /* Output code to add DELTA to the first argument, and then jump
6979 to FUNCTION. Used for C++ multiple inheritance. */
6982 arc_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
6983 HOST_WIDE_INT delta
,
6984 HOST_WIDE_INT vcall_offset
,
6987 int mi_delta
= delta
;
6988 const char *const mi_op
= mi_delta
< 0 ? "sub" : "add";
6991 = aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
) ? 1 : 0;
6995 mi_delta
= - mi_delta
;
6997 /* Add DELTA. When possible use a plain add, otherwise load it into
6998 a register first. */
7000 while (mi_delta
!= 0)
7002 if ((mi_delta
& (3 << shift
)) == 0)
7006 asm_fprintf (file
, "\t%s\t%s, %s, %d\n",
7007 mi_op
, reg_names
[this_regno
], reg_names
[this_regno
],
7008 mi_delta
& (0xff << shift
));
7009 mi_delta
&= ~(0xff << shift
);
7014 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
7015 if (vcall_offset
!= 0)
7017 /* ld r12,[this] --> temp = *this
7018 add r12,r12,vcall_offset --> temp = *(*this + vcall_offset)
7020 add this,this,r12 --> this+ = *(*this + vcall_offset) */
7021 asm_fprintf (file
, "\tld\t%s, [%s]\n",
7022 ARC_TEMP_SCRATCH_REG
, reg_names
[this_regno
]);
7023 asm_fprintf (file
, "\tadd\t%s, %s, " HOST_WIDE_INT_PRINT_DEC
"\n",
7024 ARC_TEMP_SCRATCH_REG
, ARC_TEMP_SCRATCH_REG
, vcall_offset
);
7025 asm_fprintf (file
, "\tld\t%s, [%s]\n",
7026 ARC_TEMP_SCRATCH_REG
, ARC_TEMP_SCRATCH_REG
);
7027 asm_fprintf (file
, "\tadd\t%s, %s, %s\n", reg_names
[this_regno
],
7028 reg_names
[this_regno
], ARC_TEMP_SCRATCH_REG
);
7031 fnaddr
= XEXP (DECL_RTL (function
), 0);
7033 if (arc_is_longcall_p (fnaddr
))
7037 asm_fprintf (file
, "\tld\t%s, [pcl, @",
7038 ARC_TEMP_SCRATCH_REG
);
7039 assemble_name (file
, XSTR (fnaddr
, 0));
7040 fputs ("@gotpc]\n", file
);
7041 asm_fprintf (file
, "\tj\t[%s]", ARC_TEMP_SCRATCH_REG
);
7045 fputs ("\tj\t@", file
);
7046 assemble_name (file
, XSTR (fnaddr
, 0));
7051 fputs ("\tb\t@", file
);
7052 assemble_name (file
, XSTR (fnaddr
, 0));
7054 fputs ("@plt\n", file
);
7059 /* Return true if a 32 bit "long_call" should be generated for
7060 this calling SYM_REF. We generate a long_call if the function:
7062 a. has an __attribute__((long call))
7063 or b. the -mlong-calls command line switch has been specified
7065 However we do not generate a long call if the function has an
7066 __attribute__ ((short_call)) or __attribute__ ((medium_call))
7068 This function will be called by C fragments contained in the machine
7069 description file. */
7072 arc_is_longcall_p (rtx sym_ref
)
7074 if (GET_CODE (sym_ref
) != SYMBOL_REF
)
7077 return (SYMBOL_REF_LONG_CALL_P (sym_ref
)
7078 || (TARGET_LONG_CALLS_SET
7079 && !SYMBOL_REF_SHORT_CALL_P (sym_ref
)
7080 && !SYMBOL_REF_MEDIUM_CALL_P (sym_ref
)));
7084 /* Likewise for short calls. */
7087 arc_is_shortcall_p (rtx sym_ref
)
7089 if (GET_CODE (sym_ref
) != SYMBOL_REF
)
7092 return (SYMBOL_REF_SHORT_CALL_P (sym_ref
)
7093 || (!TARGET_LONG_CALLS_SET
&& !TARGET_MEDIUM_CALLS
7094 && !SYMBOL_REF_LONG_CALL_P (sym_ref
)
7095 && !SYMBOL_REF_MEDIUM_CALL_P (sym_ref
)));
7099 /* Worker function for TARGET_RETURN_IN_MEMORY. */
7102 arc_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
7104 if (AGGREGATE_TYPE_P (type
) || TREE_ADDRESSABLE (type
))
7108 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7109 return (size
== -1 || size
> (TARGET_V2
? 16 : 8));
7114 arc_pass_by_reference (cumulative_args_t ca_v ATTRIBUTE_UNUSED
,
7115 machine_mode mode ATTRIBUTE_UNUSED
,
7117 bool named ATTRIBUTE_UNUSED
)
7120 && (TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
7121 || TREE_ADDRESSABLE (type
)));
7124 /* Implement TARGET_CAN_USE_DOLOOP_P. */
7127 arc_can_use_doloop_p (const widest_int
&,
7128 const widest_int
&iterations_max
,
7129 unsigned int loop_depth
, bool entered_at_top
)
7131 /* Considering limitations in the hardware, only use doloop
7132 for innermost loops which must be entered from the top. */
7133 if (loop_depth
> 1 || !entered_at_top
)
7136 /* Check for lp_count width boundary. */
7137 if (arc_lpcwidth
!= 32
7138 && (wi::gtu_p (iterations_max
, ((1 << arc_lpcwidth
) - 1))
7139 || wi::eq_p (iterations_max
, 0)))
7144 /* NULL if INSN insn is valid within a low-overhead loop. Otherwise
7145 return why doloop cannot be applied. */
7148 arc_invalid_within_doloop (const rtx_insn
*insn
)
7151 return "Function call in the loop.";
7153 /* FIXME! add here all the ZOL exceptions. */
7157 /* Return true if a load instruction (CONSUMER) uses the same address as a
7158 store instruction (PRODUCER). This function is used to avoid st/ld
7159 address hazard in ARC700 cores. */
7161 arc_store_addr_hazard_p (rtx_insn
* producer
, rtx_insn
* consumer
)
7163 rtx in_set
, out_set
;
7164 rtx out_addr
, in_addr
;
7172 /* Peel the producer and the consumer for the address. */
7173 out_set
= single_set (producer
);
7176 out_addr
= SET_DEST (out_set
);
7179 if (GET_CODE (out_addr
) == ZERO_EXTEND
7180 || GET_CODE (out_addr
) == SIGN_EXTEND
)
7181 out_addr
= XEXP (out_addr
, 0);
7183 if (!MEM_P (out_addr
))
7186 in_set
= single_set (consumer
);
7189 in_addr
= SET_SRC (in_set
);
7192 if (GET_CODE (in_addr
) == ZERO_EXTEND
7193 || GET_CODE (in_addr
) == SIGN_EXTEND
)
7194 in_addr
= XEXP (in_addr
, 0);
7196 if (!MEM_P (in_addr
))
7198 /* Get rid of the MEM and check if the addresses are
7200 in_addr
= XEXP (in_addr
, 0);
7201 out_addr
= XEXP (out_addr
, 0);
7203 return exp_equiv_p (in_addr
, out_addr
, 0, true);
7209 /* The same functionality as arc_hazard. It is called in machine
7210 reorg before any other optimization. Hence, the NOP size is taken
7211 into account when doing branch shortening. */
7214 workaround_arc_anomaly (void)
7216 rtx_insn
*insn
, *succ0
;
7218 /* For any architecture: call arc_hazard here. */
7219 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
7221 succ0
= next_real_insn (insn
);
7222 if (arc_hazard (insn
, succ0
))
7224 emit_insn_before (gen_nopv (), succ0
);
7232 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
7234 succ0
= next_real_insn (insn
);
7235 if (arc_store_addr_hazard_p (insn
, succ0
))
7237 emit_insn_after (gen_nopv (), insn
);
7238 emit_insn_after (gen_nopv (), insn
);
7242 /* Avoid adding nops if the instruction between the ST and LD is
7244 succ1
= next_real_insn (succ0
);
7245 if (succ0
&& !JUMP_P (succ0
) && !CALL_P (succ0
)
7246 && arc_store_addr_hazard_p (insn
, succ1
))
7247 emit_insn_after (gen_nopv (), insn
);
7252 /* A callback for the hw-doloop pass. Called when a loop we have discovered
7253 turns out not to be optimizable; we have to split the loop_end pattern into
7254 a subtract and a test. */
7257 hwloop_fail (hwloop_info loop
)
7260 rtx insn
= loop
->loop_end
;
7263 && (loop
->length
&& (loop
->length
<= ARC_MAX_LOOP_LENGTH
))
7264 && REG_P (loop
->iter_reg
))
7266 /* TARGET_V2 core3 has dbnz instructions. */
7267 test
= gen_dbnz (loop
->iter_reg
, loop
->start_label
);
7268 insn
= emit_jump_insn_before (test
, loop
->loop_end
);
7270 else if (REG_P (loop
->iter_reg
) && (REGNO (loop
->iter_reg
) == LP_COUNT
))
7272 /* We have the lp_count as loop iterator, try to use it. */
7273 emit_insn_before (gen_loop_fail (), loop
->loop_end
);
7274 test
= gen_rtx_NE (VOIDmode
, gen_rtx_REG (CC_ZNmode
, CC_REG
),
7276 test
= gen_rtx_IF_THEN_ELSE (VOIDmode
, test
,
7277 gen_rtx_LABEL_REF (Pmode
, loop
->start_label
),
7279 insn
= emit_jump_insn_before (gen_rtx_SET (pc_rtx
, test
),
7284 emit_insn_before (gen_addsi3 (loop
->iter_reg
,
7288 test
= gen_rtx_NE (VOIDmode
, loop
->iter_reg
, const0_rtx
);
7289 insn
= emit_jump_insn_before (gen_cbranchsi4 (test
,
7295 JUMP_LABEL (insn
) = loop
->start_label
;
7296 LABEL_NUSES (loop
->start_label
)++;
7297 delete_insn (loop
->loop_end
);
7300 /* Optimize LOOP. */
7303 hwloop_optimize (hwloop_info loop
)
7307 basic_block entry_bb
, bb
;
7308 rtx iter_reg
, end_label
;
7309 rtx_insn
*insn
, *seq
, *entry_after
, *last_insn
;
7310 unsigned int length
;
7311 bool need_fix
= false;
7312 rtx lp_reg
= gen_rtx_REG (SImode
, LP_COUNT
);
7314 if (loop
->depth
> 1)
7317 fprintf (dump_file
, ";; loop %d is not innermost\n",
7322 if (!loop
->incoming_dest
)
7325 fprintf (dump_file
, ";; loop %d has more than one entry\n",
7330 if (loop
->incoming_dest
!= loop
->head
)
7333 fprintf (dump_file
, ";; loop %d is not entered from head\n",
7338 if (loop
->has_call
|| loop
->has_asm
)
7341 fprintf (dump_file
, ";; loop %d has invalid insn\n",
7346 /* Scan all the blocks to make sure they don't use iter_reg. */
7347 if (loop
->iter_reg_used
|| loop
->iter_reg_used_outside
)
7350 fprintf (dump_file
, ";; loop %d uses iterator\n",
7355 /* Check if start_label appears before doloop_end. */
7357 for (insn
= loop
->start_label
;
7358 insn
&& insn
!= loop
->loop_end
;
7359 insn
= NEXT_INSN (insn
))
7360 length
+= NONDEBUG_INSN_P (insn
) ? get_attr_length (insn
) : 0;
7365 fprintf (dump_file
, ";; loop %d start_label not before loop_end\n",
7370 loop
->length
= length
;
7371 if (loop
->length
> ARC_MAX_LOOP_LENGTH
)
7374 fprintf (dump_file
, ";; loop %d too long\n", loop
->loop_no
);
7377 else if (!loop
->length
)
7380 fprintf (dump_file
, ";; loop %d is empty\n", loop
->loop_no
);
7384 /* Check if we use a register or not. */
7385 if (!REG_P (loop
->iter_reg
))
7388 fprintf (dump_file
, ";; loop %d iterator is MEM\n",
7393 /* Check if loop register is lpcount. */
7394 if (REG_P (loop
->iter_reg
) && (REGNO (loop
->iter_reg
)) != LP_COUNT
)
7397 fprintf (dump_file
, ";; loop %d doesn't use lp_count as loop"
7400 /* This loop doesn't use the lp_count, check though if we can
7402 if (TEST_HARD_REG_BIT (loop
->regs_set_in_loop
, LP_COUNT
)
7403 /* In very unique cases we may have LP_COUNT alive. */
7404 || (loop
->incoming_src
7405 && REGNO_REG_SET_P (df_get_live_out (loop
->incoming_src
),
7412 /* Check for control like instruction as the last instruction of a
7415 last_insn
= PREV_INSN (loop
->loop_end
);
7419 for (; last_insn
!= BB_HEAD (bb
);
7420 last_insn
= PREV_INSN (last_insn
))
7421 if (NONDEBUG_INSN_P (last_insn
))
7424 if (last_insn
!= BB_HEAD (bb
))
7427 if (single_pred_p (bb
)
7428 && single_pred_edge (bb
)->flags
& EDGE_FALLTHRU
7429 && single_pred (bb
) != ENTRY_BLOCK_PTR_FOR_FN (cfun
))
7431 bb
= single_pred (bb
);
7432 last_insn
= BB_END (bb
);
7445 fprintf (dump_file
, ";; loop %d has no last instruction\n",
7450 if ((TARGET_ARC600_FAMILY
|| TARGET_HS
)
7451 && INSN_P (last_insn
)
7452 && (JUMP_P (last_insn
) || CALL_P (last_insn
)
7453 || GET_CODE (PATTERN (last_insn
)) == SEQUENCE
7454 /* At this stage we can have (insn (clobber (mem:BLK
7455 (reg)))) instructions, ignore them. */
7456 || (GET_CODE (PATTERN (last_insn
)) != CLOBBER
7457 && (get_attr_type (last_insn
) == TYPE_BRCC
7458 || get_attr_type (last_insn
) == TYPE_BRCC_NO_DELAY_SLOT
))))
7460 if (loop
->length
+ 2 > ARC_MAX_LOOP_LENGTH
)
7463 fprintf (dump_file
, ";; loop %d too long\n", loop
->loop_no
);
7467 fprintf (dump_file
, ";; loop %d has a control like last insn;"
7471 last_insn
= emit_insn_after (gen_nopv (), last_insn
);
7474 if (LABEL_P (last_insn
))
7477 fprintf (dump_file
, ";; loop %d has a label as last insn;"
7480 last_insn
= emit_insn_after (gen_nopv (), last_insn
);
7483 /* SAVE_NOTE is used by haifa scheduler. However, we are after it
7484 and we can use it to indicate the last ZOL instruction cannot be
7485 part of a delay slot. */
7486 add_reg_note (last_insn
, REG_SAVE_NOTE
, GEN_INT (2));
7488 loop
->last_insn
= last_insn
;
7490 /* Get the loop iteration register. */
7491 iter_reg
= loop
->iter_reg
;
7493 gcc_assert (REG_P (iter_reg
));
7497 FOR_EACH_VEC_SAFE_ELT (loop
->incoming
, i
, entry_edge
)
7498 if (entry_edge
->flags
& EDGE_FALLTHRU
)
7501 if (entry_edge
== NULL
)
7504 fprintf (dump_file
, ";; loop %d has no fallthru edge jumping"
7509 /* The loop is good. */
7510 end_label
= gen_label_rtx ();
7511 loop
->end_label
= end_label
;
7513 /* Place the zero_cost_loop_start instruction before the loop. */
7514 entry_bb
= entry_edge
->src
;
7520 /* The loop uses a R-register, but the lp_count is free, thus
7522 emit_insn (gen_movsi (lp_reg
, iter_reg
));
7523 SET_HARD_REG_BIT (loop
->regs_set_in_loop
, LP_COUNT
);
7527 fprintf (dump_file
, ";; fix loop %d to use lp_count\n",
7532 insn
= emit_insn (gen_arc_lp (iter_reg
,
7539 entry_after
= BB_END (entry_bb
);
7540 if (!single_succ_p (entry_bb
) || vec_safe_length (loop
->incoming
) > 1
7547 emit_insn_before (seq
, BB_HEAD (loop
->head
));
7548 seq
= emit_label_before (gen_label_rtx (), seq
);
7549 new_bb
= create_basic_block (seq
, insn
, entry_bb
);
7550 FOR_EACH_EDGE (e
, ei
, loop
->incoming
)
7552 if (!(e
->flags
& EDGE_FALLTHRU
))
7553 redirect_edge_and_branch_force (e
, new_bb
);
7555 redirect_edge_succ (e
, new_bb
);
7558 make_edge (new_bb
, loop
->head
, 0);
7563 while (DEBUG_INSN_P (entry_after
)
7564 || (NOTE_P (entry_after
)
7565 && NOTE_KIND (entry_after
) != NOTE_INSN_BASIC_BLOCK
))
7566 entry_after
= NEXT_INSN (entry_after
);
7568 entry_after
= next_nonnote_nondebug_insn_bb (entry_after
);
7570 gcc_assert (entry_after
);
7571 emit_insn_before (seq
, entry_after
);
7574 delete_insn (loop
->loop_end
);
7575 /* Insert the loop end label before the last instruction of the
7577 emit_label_after (end_label
, loop
->last_insn
);
7578 /* Make sure we mark the begining and end label as used. */
7579 LABEL_NUSES (loop
->end_label
)++;
7580 LABEL_NUSES (loop
->start_label
)++;
7585 /* A callback for the hw-doloop pass. This function examines INSN; if
7586 it is a loop_end pattern we recognize, return the reg rtx for the
7587 loop counter. Otherwise, return NULL_RTX. */
7590 hwloop_pattern_reg (rtx_insn
*insn
)
7594 if (!JUMP_P (insn
) || recog_memoized (insn
) != CODE_FOR_loop_end
)
7597 reg
= SET_DEST (XVECEXP (PATTERN (insn
), 0, 1));
7603 static struct hw_doloop_hooks arc_doloop_hooks
=
7610 /* Run from machine_dependent_reorg, this pass looks for doloop_end insns
7611 and tries to rewrite the RTL of these loops so that proper Blackfin
7612 hardware loops are generated. */
7615 arc_reorg_loops (void)
7617 reorg_loops (true, &arc_doloop_hooks
);
7620 /* Scan all calls and add symbols to be emitted in the jli section if
7624 jli_call_scan (void)
7628 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
7633 rtx pat
= PATTERN (insn
);
7634 if (GET_CODE (pat
) == COND_EXEC
)
7635 pat
= COND_EXEC_CODE (pat
);
7636 pat
= XVECEXP (pat
, 0, 0);
7637 if (GET_CODE (pat
) == SET
)
7638 pat
= SET_SRC (pat
);
7640 pat
= XEXP (XEXP (pat
, 0), 0);
7641 if (GET_CODE (pat
) == SYMBOL_REF
7642 && arc_is_jli_call_p (pat
))
7643 arc_add_jli_section (pat
);
7647 static int arc_reorg_in_progress
= 0;
7649 /* ARC's machince specific reorg function. */
7660 cfun
->machine
->arc_reorg_started
= 1;
7661 arc_reorg_in_progress
= 1;
7663 compute_bb_for_insn ();
7667 /* Doloop optimization. */
7670 workaround_arc_anomaly ();
7673 /* FIXME: should anticipate ccfsm action, generate special patterns for
7674 to-be-deleted branches that have no delay slot and have at least the
7675 length of the size increase forced on other insns that are conditionalized.
7676 This can also have an insn_list inside that enumerates insns which are
7677 not actually conditionalized because the destinations are dead in the
7679 Could also tag branches that we want to be unaligned if they get no delay
7680 slot, or even ones that we don't want to do delay slot sheduling for
7681 because we can unalign them.
7683 However, there are cases when conditional execution is only possible after
7684 delay slot scheduling:
7686 - If a delay slot is filled with a nocond/set insn from above, the previous
7687 basic block can become elegible for conditional execution.
7688 - If a delay slot is filled with a nocond insn from the fall-through path,
7689 the branch with that delay slot can become eligble for conditional
7690 execution (however, with the same sort of data flow analysis that dbr
7691 does, we could have figured out before that we don't need to
7692 conditionalize this insn.)
7693 - If a delay slot insn is filled with an insn from the target, the
7694 target label gets its uses decremented (even deleted if falling to zero),
7695 thus possibly creating more condexec opportunities there.
7696 Therefore, we should still be prepared to apply condexec optimization on
7697 non-prepared branches if the size increase of conditionalized insns is no
7698 more than the size saved from eliminating the branch. An invocation option
7699 could also be used to reserve a bit of extra size for condbranches so that
7700 this'll work more often (could also test in arc_reorg if the block is
7701 'close enough' to be eligible for condexec to make this likely, and
7702 estimate required size increase). */
7703 /* Generate BRcc insns, by combining cmp and Bcc insns wherever possible. */
7704 if (TARGET_NO_BRCC_SET
)
7709 init_insn_lengths();
7712 if (optimize
> 1 && !TARGET_NO_COND_EXEC
)
7715 unsigned int flags
= pass_data_arc_ifcvt
.todo_flags_finish
;
7716 df_finish_pass ((flags
& TODO_df_verify
) != 0);
7720 fprintf (dump_file
, ";; After if conversion:\n\n");
7721 print_rtl (dump_file
, get_insns ());
7725 /* Call shorten_branches to calculate the insn lengths. */
7726 shorten_branches (get_insns());
7727 cfun
->machine
->ccfsm_current_insn
= NULL_RTX
;
7729 if (!INSN_ADDRESSES_SET_P())
7730 fatal_error (input_location
, "Insn addresses not set after shorten_branches");
7732 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
7735 enum attr_type insn_type
;
7737 /* If a non-jump insn (or a casesi jump table), continue. */
7738 if (GET_CODE (insn
) != JUMP_INSN
||
7739 GET_CODE (PATTERN (insn
)) == ADDR_VEC
7740 || GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
)
7743 /* If we already have a brcc, note if it is suitable for brcc_s.
7744 Be a bit generous with the brcc_s range so that we can take
7745 advantage of any code shortening from delay slot scheduling. */
7746 if (recog_memoized (insn
) == CODE_FOR_cbranchsi4_scratch
)
7748 rtx pat
= PATTERN (insn
);
7749 rtx op
= XEXP (SET_SRC (XVECEXP (pat
, 0, 0)), 0);
7750 rtx
*ccp
= &XEXP (XVECEXP (pat
, 0, 1), 0);
7752 offset
= branch_dest (insn
) - INSN_ADDRESSES (INSN_UID (insn
));
7753 if ((offset
>= -140 && offset
< 140)
7754 && rtx_equal_p (XEXP (op
, 1), const0_rtx
)
7755 && compact_register_operand (XEXP (op
, 0), VOIDmode
)
7756 && equality_comparison_operator (op
, VOIDmode
))
7757 PUT_MODE (*ccp
, CC_Zmode
);
7758 else if (GET_MODE (*ccp
) == CC_Zmode
)
7759 PUT_MODE (*ccp
, CC_ZNmode
);
7762 if ((insn_type
= get_attr_type (insn
)) == TYPE_BRCC
7763 || insn_type
== TYPE_BRCC_NO_DELAY_SLOT
)
7766 /* OK. so we have a jump insn. */
7767 /* We need to check that it is a bcc. */
7768 /* Bcc => set (pc) (if_then_else ) */
7769 pattern
= PATTERN (insn
);
7770 if (GET_CODE (pattern
) != SET
7771 || GET_CODE (SET_SRC (pattern
)) != IF_THEN_ELSE
7772 || ANY_RETURN_P (XEXP (SET_SRC (pattern
), 1)))
7775 /* Now check if the jump is beyond the s9 range. */
7776 if (CROSSING_JUMP_P (insn
))
7778 offset
= branch_dest (insn
) - INSN_ADDRESSES (INSN_UID (insn
));
7780 if(offset
> 253 || offset
< -254)
7783 pc_target
= SET_SRC (pattern
);
7785 /* Avoid FPU instructions. */
7786 if ((GET_MODE (XEXP (XEXP (pc_target
, 0), 0)) == CC_FPUmode
)
7787 || (GET_MODE (XEXP (XEXP (pc_target
, 0), 0)) == CC_FPU_UNEQmode
))
7790 /* Now go back and search for the set cc insn. */
7792 label
= XEXP (pc_target
, 1);
7796 rtx_insn
*scan
, *link_insn
= NULL
;
7798 for (scan
= PREV_INSN (insn
);
7799 scan
&& GET_CODE (scan
) != CODE_LABEL
;
7800 scan
= PREV_INSN (scan
))
7802 if (! INSN_P (scan
))
7804 pat
= PATTERN (scan
);
7805 if (GET_CODE (pat
) == SET
7806 && cc_register (SET_DEST (pat
), VOIDmode
))
7815 /* Check if this is a data dependency. */
7817 rtx op
, cc_clob_rtx
, op0
, op1
, brcc_insn
, note
;
7820 /* Ok this is the set cc. copy args here. */
7821 op
= XEXP (pc_target
, 0);
7823 op0
= cmp0
= XEXP (SET_SRC (pat
), 0);
7824 op1
= cmp1
= XEXP (SET_SRC (pat
), 1);
7825 if (GET_CODE (op0
) == ZERO_EXTRACT
7826 && XEXP (op0
, 1) == const1_rtx
7827 && (GET_CODE (op
) == EQ
7828 || GET_CODE (op
) == NE
))
7830 /* btst / b{eq,ne} -> bbit{0,1} */
7831 op0
= XEXP (cmp0
, 0);
7832 op1
= XEXP (cmp0
, 2);
7834 else if (!register_operand (op0
, VOIDmode
)
7835 || !general_operand (op1
, VOIDmode
))
7837 /* Be careful not to break what cmpsfpx_raw is
7838 trying to create for checking equality of
7839 single-precision floats. */
7840 else if (TARGET_SPFP
7841 && GET_MODE (op0
) == SFmode
7842 && GET_MODE (op1
) == SFmode
)
7845 /* None of the two cmp operands should be set between the
7846 cmp and the branch. */
7847 if (reg_set_between_p (op0
, link_insn
, insn
))
7850 if (reg_set_between_p (op1
, link_insn
, insn
))
7853 /* Since the MODE check does not work, check that this is
7854 CC reg's last set location before insn, and also no
7855 instruction between the cmp and branch uses the
7857 if ((reg_set_between_p (SET_DEST (pat
), link_insn
, insn
))
7858 || (reg_used_between_p (SET_DEST (pat
), link_insn
, insn
)))
7861 /* CC reg should be dead after insn. */
7862 if (!find_regno_note (insn
, REG_DEAD
, CC_REG
))
7865 op
= gen_rtx_fmt_ee (GET_CODE (op
),
7866 GET_MODE (op
), cmp0
, cmp1
);
7867 /* If we create a LIMM where there was none before,
7868 we only benefit if we can avoid a scheduling bubble
7869 for the ARC600. Otherwise, we'd only forgo chances
7870 at short insn generation, and risk out-of-range
7872 if (!brcc_nolimm_operator (op
, VOIDmode
)
7873 && !long_immediate_operand (op1
, VOIDmode
)
7875 || next_active_insn (link_insn
) != insn
))
7878 /* Emit bbit / brcc (or brcc_s if possible).
7879 CC_Zmode indicates that brcc_s is possible. */
7882 cc_clob_rtx
= gen_rtx_REG (CC_ZNmode
, CC_REG
);
7883 else if ((offset
>= -140 && offset
< 140)
7884 && rtx_equal_p (op1
, const0_rtx
)
7885 && compact_register_operand (op0
, VOIDmode
)
7886 && (GET_CODE (op
) == EQ
7887 || GET_CODE (op
) == NE
))
7888 cc_clob_rtx
= gen_rtx_REG (CC_Zmode
, CC_REG
);
7890 cc_clob_rtx
= gen_rtx_REG (CCmode
, CC_REG
);
7893 = gen_rtx_IF_THEN_ELSE (VOIDmode
, op
, label
, pc_rtx
);
7894 brcc_insn
= gen_rtx_SET (pc_rtx
, brcc_insn
);
7895 cc_clob_rtx
= gen_rtx_CLOBBER (VOIDmode
, cc_clob_rtx
);
7898 (VOIDmode
, gen_rtvec (2, brcc_insn
, cc_clob_rtx
));
7899 brcc_insn
= emit_jump_insn_before (brcc_insn
, insn
);
7901 JUMP_LABEL (brcc_insn
) = JUMP_LABEL (insn
);
7902 note
= find_reg_note (insn
, REG_BR_PROB
, 0);
7905 XEXP (note
, 1) = REG_NOTES (brcc_insn
);
7906 REG_NOTES (brcc_insn
) = note
;
7908 note
= find_reg_note (link_insn
, REG_DEAD
, op0
);
7911 remove_note (link_insn
, note
);
7912 XEXP (note
, 1) = REG_NOTES (brcc_insn
);
7913 REG_NOTES (brcc_insn
) = note
;
7915 note
= find_reg_note (link_insn
, REG_DEAD
, op1
);
7918 XEXP (note
, 1) = REG_NOTES (brcc_insn
);
7919 REG_NOTES (brcc_insn
) = note
;
7924 /* Delete the bcc insn. */
7925 set_insn_deleted (insn
);
7927 /* Delete the cmp insn. */
7928 set_insn_deleted (link_insn
);
7933 /* Clear out insn_addresses. */
7934 INSN_ADDRESSES_FREE ();
7938 if (INSN_ADDRESSES_SET_P())
7939 fatal_error (input_location
, "insn addresses not freed");
7941 arc_reorg_in_progress
= 0;
7944 /* Check if the operands are valid for BRcc.d generation
7945 Valid Brcc.d patterns are
7949 For cc={GT, LE, GTU, LEU}, u6=63 can not be allowed,
7950 since they are encoded by the assembler as {GE, LT, HS, LS} 64, which
7951 does not have a delay slot
7953 Assumed precondition: Second operand is either a register or a u6 value. */
7956 valid_brcc_with_delay_p (rtx
*operands
)
7958 if (optimize_size
&& GET_MODE (operands
[4]) == CC_Zmode
)
7960 return brcc_nolimm_operator (operands
[0], VOIDmode
);
7963 /* Implement TARGET_IN_SMALL_DATA_P. Return true if it would be safe to
7964 access DECL using %gp_rel(...)($gp). */
7967 arc_in_small_data_p (const_tree decl
)
7972 /* Only variables are going into small data area. */
7973 if (TREE_CODE (decl
) != VAR_DECL
)
7976 if (TARGET_NO_SDATA_SET
)
7979 /* Disable sdata references to weak variables. */
7980 if (DECL_WEAK (decl
))
7983 /* Don't put constants into the small data section: we want them to
7984 be in ROM rather than RAM. */
7985 if (TREE_READONLY (decl
))
7988 /* To ensure -mvolatile-cache works ld.di does not have a
7989 gp-relative variant. */
7990 if (!TARGET_VOLATILE_CACHE_SET
7991 && TREE_THIS_VOLATILE (decl
))
7994 /* Likewise for uncached data. */
7995 attr
= TYPE_ATTRIBUTES (TREE_TYPE (decl
));
7996 if (lookup_attribute ("uncached", attr
))
7999 /* and for aux regs. */
8000 attr
= DECL_ATTRIBUTES (decl
);
8001 if (lookup_attribute ("aux", attr
))
8004 if (DECL_SECTION_NAME (decl
) != 0)
8006 const char *name
= DECL_SECTION_NAME (decl
);
8007 if (strcmp (name
, ".sdata") == 0
8008 || strcmp (name
, ".sbss") == 0)
8011 /* If it's not public, there's no need to put it in the small data
8013 else if (TREE_PUBLIC (decl
))
8015 size
= int_size_in_bytes (TREE_TYPE (decl
));
8016 return (size
> 0 && size
<= g_switch_value
);
8021 /* Return true if OP is an acceptable memory operand for ARCompact
8022 16-bit gp-relative load instructions.
8024 /* volatile cache option still to be handled. */
8027 compact_sda_memory_operand (rtx op
, machine_mode mode
, bool short_p
)
8034 /* Eliminate non-memory operations. */
8035 if (GET_CODE (op
) != MEM
)
8038 if (mode
== VOIDmode
)
8039 mode
= GET_MODE (op
);
8041 size
= GET_MODE_SIZE (mode
);
8043 /* dword operations really put out 2 instructions, so eliminate them. */
8044 if (size
> UNITS_PER_WORD
)
8047 /* Decode the address now. */
8048 addr
= XEXP (op
, 0);
8050 if (!legitimate_small_data_address_p (addr
))
8053 if (!short_p
|| size
== 1)
8056 /* Now check for the alignment, the short loads using gp require the
8057 addresses to be aligned. */
8058 align
= get_symbol_alignment (addr
);
8069 if (align
&& ((align
& mask
) == 0))
8074 /* Return TRUE if PAT is accessing an aux-reg. */
8077 arc_is_aux_reg_p (rtx pat
)
8079 tree attrs
= NULL_TREE
;
8085 /* Get the memory attributes. */
8086 addr
= MEM_EXPR (pat
);
8090 /* Get the attributes. */
8091 if (TREE_CODE (addr
) == VAR_DECL
)
8092 attrs
= DECL_ATTRIBUTES (addr
);
8093 else if (TREE_CODE (addr
) == MEM_REF
)
8094 attrs
= TYPE_ATTRIBUTES (TREE_TYPE (TREE_OPERAND (addr
, 0)));
8098 if (lookup_attribute ("aux", attrs
))
8103 /* Implement ASM_OUTPUT_ALIGNED_DECL_LOCAL. */
8106 arc_asm_output_aligned_decl_local (FILE * stream
, tree decl
, const char * name
,
8107 unsigned HOST_WIDE_INT size
,
8108 unsigned HOST_WIDE_INT align
,
8109 unsigned HOST_WIDE_INT globalize_p
)
8111 int in_small_data
= arc_in_small_data_p (decl
);
8112 rtx mem
= decl
== NULL_TREE
? NULL_RTX
: DECL_RTL (decl
);
8114 /* Don't output aux-reg symbols. */
8115 if (mem
!= NULL_RTX
&& MEM_P (mem
)
8116 && SYMBOL_REF_P (XEXP (mem
, 0))
8117 && arc_is_aux_reg_p (mem
))
8121 switch_to_section (get_named_section (NULL
, ".sbss", 0));
8122 /* named_section (0,".sbss",0); */
8124 switch_to_section (bss_section
);
8127 (*targetm
.asm_out
.globalize_label
) (stream
, name
);
8129 ASM_OUTPUT_ALIGN (stream
, floor_log2 ((align
) / BITS_PER_UNIT
));
8130 ASM_OUTPUT_TYPE_DIRECTIVE (stream
, name
, "object");
8131 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
8132 ASM_OUTPUT_LABEL (stream
, name
);
8135 ASM_OUTPUT_SKIP (stream
, size
);
8139 arc_preserve_reload_p (rtx in
)
8141 return (GET_CODE (in
) == PLUS
8142 && RTX_OK_FOR_BASE_P (XEXP (in
, 0), true)
8143 && CONST_INT_P (XEXP (in
, 1))
8144 && !((INTVAL (XEXP (in
, 1)) & 511)));
8148 arc_register_move_cost (machine_mode
,
8149 enum reg_class from_class
, enum reg_class to_class
)
8151 /* The ARC600 has no bypass for extension registers, hence a nop might be
8152 needed to be inserted after a write so that reads are safe. */
8155 if (to_class
== MPY_WRITABLE_CORE_REGS
)
8157 /* Instructions modifying LP_COUNT need 4 additional cycles before
8158 the register will actually contain the value. */
8159 else if (to_class
== LPCOUNT_REG
)
8161 else if (to_class
== WRITABLE_CORE_REGS
)
8165 /* Using lp_count as scratch reg is a VERY bad idea. */
8166 if (from_class
== LPCOUNT_REG
)
8168 if (to_class
== LPCOUNT_REG
)
8171 /* Force an attempt to 'mov Dy,Dx' to spill. */
8172 if ((TARGET_ARC700
|| TARGET_EM
) && TARGET_DPFP
8173 && from_class
== DOUBLE_REGS
&& to_class
== DOUBLE_REGS
)
8179 /* Emit code for an addsi3 instruction with OPERANDS.
8180 COND_P indicates if this will use conditional execution.
8181 Return the length of the instruction.
8182 If OUTPUT_P is false, don't actually output the instruction, just return
8185 arc_output_addsi (rtx
*operands
, bool cond_p
, bool output_p
)
8189 int match
= operands_match_p (operands
[0], operands
[1]);
8190 int match2
= operands_match_p (operands
[0], operands
[2]);
8191 int intval
= (REG_P (operands
[2]) ? 1
8192 : CONST_INT_P (operands
[2]) ? INTVAL (operands
[2]) : 0xbadc057);
8193 int neg_intval
= -intval
;
8194 int short_0
= satisfies_constraint_Rcq (operands
[0]);
8195 int short_p
= (!cond_p
&& short_0
&& satisfies_constraint_Rcq (operands
[1]));
8198 #define REG_H_P(OP) (REG_P (OP) && ((TARGET_V2 && REGNO (OP) <= 31 \
8199 && REGNO (OP) != 30) \
8202 #define ADDSI_OUTPUT1(FORMAT) do {\
8204 output_asm_insn (FORMAT, operands);\
8207 #define ADDSI_OUTPUT(LIST) do {\
8210 ADDSI_OUTPUT1 (format);\
8214 /* First try to emit a 16 bit insn. */
8217 /* If we are actually about to output this insn, don't try a 16 bit
8218 variant if we already decided that we don't want that
8219 (I.e. we upsized this insn to align some following insn.)
8220 E.g. add_s r0,sp,70 is 16 bit, but add r0,sp,70 requires a LIMM -
8221 but add1 r0,sp,35 doesn't. */
8222 && (!output_p
|| (get_attr_length (current_output_insn
) & 2)))
8224 /* Generate add_s a,b,c; add_s b,b,u7; add_s c,b,u3; add_s b,b,h
8227 && ((REG_H_P (operands
[2])
8228 && (match
|| satisfies_constraint_Rcq (operands
[2])))
8229 || (CONST_INT_P (operands
[2])
8230 && ((unsigned) intval
<= (match
? 127 : 7)))))
8231 ADDSI_OUTPUT1 ("add%? %0,%1,%2 ;1");
8233 /* Generate add_s b,b,h patterns. */
8234 if (short_0
&& match2
&& REG_H_P (operands
[1]))
8235 ADDSI_OUTPUT1 ("add%? %0,%2,%1 ;2");
8237 /* Generate add_s b,sp,u7; add_s sp,sp,u7 patterns. */
8238 if ((short_0
|| REGNO (operands
[0]) == STACK_POINTER_REGNUM
)
8239 && REGNO (operands
[1]) == STACK_POINTER_REGNUM
&& !(intval
& ~124))
8240 ADDSI_OUTPUT1 ("add%? %0,%1,%2 ;3");
8242 if ((short_p
&& (unsigned) neg_intval
<= (match
? 31 : 7))
8243 || (REGNO (operands
[0]) == STACK_POINTER_REGNUM
8244 && match
&& !(neg_intval
& ~124)))
8245 ADDSI_OUTPUT1 ("sub%? %0,%1,%n2 ;4");
8247 /* Generate add_s h,h,s3 patterns. */
8248 if (REG_H_P (operands
[0]) && match
&& TARGET_V2
8249 && CONST_INT_P (operands
[2]) && ((intval
>= -1) && (intval
<= 6)))
8250 ADDSI_OUTPUT1 ("add%? %0,%1,%2 ;5");
8252 /* Generate add_s r0,b,u6; add_s r1,b,u6 patterns. */
8253 if (TARGET_CODE_DENSITY
&& REG_P (operands
[0]) && REG_P (operands
[1])
8254 && ((REGNO (operands
[0]) == 0) || (REGNO (operands
[0]) == 1))
8255 && satisfies_constraint_Rcq (operands
[1])
8256 && satisfies_constraint_L (operands
[2]))
8257 ADDSI_OUTPUT1 ("add%? %0,%1,%2 ;6");
8260 /* Now try to emit a 32 bit insn without long immediate. */
8262 if (!match
&& match2
&& REG_P (operands
[1]))
8263 ADDSI_OUTPUT1 ("add%? %0,%2,%1");
8264 if (match
|| !cond_p
)
8266 int limit
= (match
&& !cond_p
) ? 0x7ff : 0x3f;
8267 int range_factor
= neg_intval
& intval
;
8270 if (intval
== (HOST_WIDE_INT
) (HOST_WIDE_INT_M1U
<< 31))
8271 ADDSI_OUTPUT1 ("bxor%? %0,%1,31");
8273 /* If we can use a straight add / sub instead of a {add,sub}[123] of
8274 same size, do, so - the insn latency is lower. */
8275 /* -0x800 is a 12-bit constant for add /add3 / sub / sub3, but
8277 if ((intval
>= 0 && intval
<= limit
)
8278 || (intval
== -0x800 && limit
== 0x7ff))
8279 ADDSI_OUTPUT1 ("add%? %0,%1,%2");
8280 else if ((intval
< 0 && neg_intval
<= limit
)
8281 || (intval
== 0x800 && limit
== 0x7ff))
8282 ADDSI_OUTPUT1 ("sub%? %0,%1,%n2");
8283 shift
= range_factor
>= 8 ? 3 : (range_factor
>> 1);
8284 gcc_assert (shift
== 0 || shift
== 1 || shift
== 2 || shift
== 3);
8285 gcc_assert ((((1 << shift
) - 1) & intval
) == 0);
8286 if (((intval
< 0 && intval
!= -0x4000)
8287 /* sub[123] is slower than add_s / sub, only use it if it
8288 avoids a long immediate. */
8289 && neg_intval
<= limit
<< shift
)
8290 || (intval
== 0x4000 && limit
== 0x7ff))
8291 ADDSI_OUTPUT ((format
, "sub%d%%? %%0,%%1,%d",
8292 shift
, neg_intval
>> shift
));
8293 else if ((intval
>= 0 && intval
<= limit
<< shift
)
8294 || (intval
== -0x4000 && limit
== 0x7ff))
8295 ADDSI_OUTPUT ((format
, "add%d%%? %%0,%%1,%d", shift
, intval
>> shift
));
8297 /* Try to emit a 16 bit opcode with long immediate. */
8299 if (short_p
&& match
)
8300 ADDSI_OUTPUT1 ("add%? %0,%1,%2");
8302 /* We have to use a 32 bit opcode, and with a long immediate. */
8304 ADDSI_OUTPUT1 (intval
< 0 ? "sub%? %0,%1,%n2" : "add%? %0,%1,%2");
8307 /* Emit code for an commutative_cond_exec instruction with OPERANDS.
8308 Return the length of the instruction.
8309 If OUTPUT_P is false, don't actually output the instruction, just return
8312 arc_output_commutative_cond_exec (rtx
*operands
, bool output_p
)
8314 enum rtx_code commutative_op
= GET_CODE (operands
[3]);
8315 const char *pat
= NULL
;
8317 /* Canonical rtl should not have a constant in the first operand position. */
8318 gcc_assert (!CONSTANT_P (operands
[1]));
8320 switch (commutative_op
)
8323 if (satisfies_constraint_C1p (operands
[2]))
8324 pat
= "bmsk%? %0,%1,%Z2";
8325 else if (satisfies_constraint_C2p (operands
[2]))
8327 operands
[2] = GEN_INT ((~INTVAL (operands
[2])));
8328 pat
= "bmskn%? %0,%1,%Z2";
8330 else if (satisfies_constraint_Ccp (operands
[2]))
8331 pat
= "bclr%? %0,%1,%M2";
8332 else if (satisfies_constraint_CnL (operands
[2]))
8333 pat
= "bic%? %0,%1,%n2-1";
8336 if (satisfies_constraint_C0p (operands
[2]))
8337 pat
= "bset%? %0,%1,%z2";
8340 if (satisfies_constraint_C0p (operands
[2]))
8341 pat
= "bxor%? %0,%1,%z2";
8344 return arc_output_addsi (operands
, true, output_p
);
8348 output_asm_insn (pat
? pat
: "%O3.%d5 %0,%1,%2", operands
);
8349 if (pat
|| REG_P (operands
[2]) || satisfies_constraint_L (operands
[2]))
8354 /* Helper function of arc_expand_movmem. ADDR points to a chunk of memory.
8355 Emit code and return an potentially modified address such that offsets
8356 up to SIZE are can be added to yield a legitimate address.
8357 if REUSE is set, ADDR is a register that may be modified. */
8360 force_offsettable (rtx addr
, HOST_WIDE_INT size
, bool reuse
)
8363 rtx offs
= const0_rtx
;
8365 if (GET_CODE (base
) == PLUS
)
8367 offs
= XEXP (base
, 1);
8368 base
= XEXP (base
, 0);
8371 || (REGNO (base
) != STACK_POINTER_REGNUM
8372 && REGNO_PTR_FRAME_P (REGNO (base
)))
8373 || !CONST_INT_P (offs
) || !SMALL_INT (INTVAL (offs
))
8374 || !SMALL_INT (INTVAL (offs
) + size
))
8377 emit_insn (gen_add2_insn (addr
, offs
));
8379 addr
= copy_to_mode_reg (Pmode
, addr
);
8384 /* Like move_by_pieces, but take account of load latency, and actual
8385 offset ranges. Return true on success. */
8388 arc_expand_movmem (rtx
*operands
)
8390 rtx dst
= operands
[0];
8391 rtx src
= operands
[1];
8392 rtx dst_addr
, src_addr
;
8394 int align
= INTVAL (operands
[3]);
8401 if (!CONST_INT_P (operands
[2]))
8403 size
= INTVAL (operands
[2]);
8404 /* move_by_pieces_ninsns is static, so we can't use it. */
8408 n_pieces
= (size
+ 4) / 8U + ((size
>> 1) & 1) + (size
& 1);
8410 n_pieces
= (size
+ 2) / 4U + (size
& 1);
8412 else if (align
== 2)
8413 n_pieces
= (size
+ 1) / 2U;
8416 if (n_pieces
>= (unsigned int) (optimize_size
? 3 : 15))
8418 /* Force 32 bit aligned and larger datum to use 64 bit transfers, if
8420 if (TARGET_LL64
&& (piece
>= 4) && (size
>= 8))
8424 dst_addr
= force_offsettable (XEXP (operands
[0], 0), size
, 0);
8425 src_addr
= force_offsettable (XEXP (operands
[1], 0), size
, 0);
8426 store
[0] = store
[1] = NULL_RTX
;
8427 tmpx
[0] = tmpx
[1] = NULL_RTX
;
8428 for (i
= 0; size
> 0; i
^= 1, size
-= piece
)
8433 while (piece
> size
)
8435 mode
= smallest_int_mode_for_size (piece
* BITS_PER_UNIT
);
8436 /* If we don't re-use temporaries, the scheduler gets carried away,
8437 and the register pressure gets unnecessarily high. */
8438 if (0 && tmpx
[i
] && GET_MODE (tmpx
[i
]) == mode
)
8441 tmpx
[i
] = tmp
= gen_reg_rtx (mode
);
8442 dst_addr
= force_offsettable (dst_addr
, piece
, 1);
8443 src_addr
= force_offsettable (src_addr
, piece
, 1);
8445 emit_insn (store
[i
]);
8446 emit_move_insn (tmp
, change_address (src
, mode
, src_addr
));
8447 store
[i
] = gen_move_insn (change_address (dst
, mode
, dst_addr
), tmp
);
8448 dst_addr
= plus_constant (Pmode
, dst_addr
, piece
);
8449 src_addr
= plus_constant (Pmode
, src_addr
, piece
);
8452 emit_insn (store
[i
]);
8454 emit_insn (store
[i
^1]);
8459 arc_get_aux_arg (rtx pat
, int *auxr
)
8461 tree attr
, addr
= MEM_EXPR (pat
);
8462 if (TREE_CODE (addr
) != VAR_DECL
)
8465 attr
= DECL_ATTRIBUTES (addr
);
8466 if (lookup_attribute ("aux", attr
))
8468 tree arg
= TREE_VALUE (attr
);
8471 *auxr
= TREE_INT_CST_LOW (TREE_VALUE (arg
));
8479 /* Prepare operands for move in MODE. Return true iff the move has
8483 prepare_move_operands (rtx
*operands
, machine_mode mode
)
8485 /* First handle aux attribute. */
8487 && (MEM_P (operands
[0]) || MEM_P (operands
[1])))
8491 if (MEM_P (operands
[0]) && arc_is_aux_reg_p (operands
[0]))
8493 /* Save operation. */
8494 if (arc_get_aux_arg (operands
[0], &auxr
))
8496 tmp
= gen_reg_rtx (SImode
);
8497 emit_move_insn (tmp
, GEN_INT (auxr
));
8501 tmp
= XEXP (operands
[0], 0);
8504 operands
[1] = force_reg (SImode
, operands
[1]);
8505 emit_insn (gen_rtx_UNSPEC_VOLATILE
8506 (VOIDmode
, gen_rtvec (2, operands
[1], tmp
),
8510 if (MEM_P (operands
[1]) && arc_is_aux_reg_p (operands
[1]))
8512 if (arc_get_aux_arg (operands
[1], &auxr
))
8514 tmp
= gen_reg_rtx (SImode
);
8515 emit_move_insn (tmp
, GEN_INT (auxr
));
8519 tmp
= XEXP (operands
[1], 0);
8520 gcc_assert (GET_CODE (tmp
) == SYMBOL_REF
);
8522 /* Load operation. */
8523 gcc_assert (REG_P (operands
[0]));
8524 emit_insn (gen_rtx_SET (operands
[0],
8525 gen_rtx_UNSPEC_VOLATILE
8526 (SImode
, gen_rtvec (1, tmp
),
8532 if (mode
== SImode
&& SYMBOLIC_CONST (operands
[1]))
8534 prepare_pic_move (operands
, SImode
);
8536 /* Disable any REG_EQUALs associated with the symref
8537 otherwise the optimization pass undoes the work done
8538 here and references the variable directly. */
8541 if (MEM_P (operands
[0])
8542 && !(reload_in_progress
|| reload_completed
))
8544 operands
[1] = force_reg (mode
, operands
[1]);
8545 if (!move_dest_operand (operands
[0], mode
))
8547 rtx addr
= copy_to_mode_reg (Pmode
, XEXP (operands
[0], 0));
8548 /* This is like change_address_1 (operands[0], mode, 0, 1) ,
8549 except that we can't use that function because it is static. */
8550 rtx pat
= change_address (operands
[0], mode
, addr
);
8551 MEM_COPY_ATTRIBUTES (pat
, operands
[0]);
8554 if (!cse_not_expected
)
8556 rtx pat
= XEXP (operands
[0], 0);
8558 pat
= arc_legitimize_address_0 (pat
, pat
, mode
);
8561 pat
= change_address (operands
[0], mode
, pat
);
8562 MEM_COPY_ATTRIBUTES (pat
, operands
[0]);
8568 if (MEM_P (operands
[1]) && !cse_not_expected
)
8570 rtx pat
= XEXP (operands
[1], 0);
8572 pat
= arc_legitimize_address_0 (pat
, pat
, mode
);
8575 pat
= change_address (operands
[1], mode
, pat
);
8576 MEM_COPY_ATTRIBUTES (pat
, operands
[1]);
8584 /* Output a library call to a function called FNAME that has been arranged
8585 to be local to any dso. */
8588 arc_output_libcall (const char *fname
)
8590 unsigned len
= strlen (fname
);
8591 static char buf
[64];
8593 gcc_assert (len
< sizeof buf
- 35);
8594 if (TARGET_LONG_CALLS_SET
8595 || (TARGET_MEDIUM_CALLS
&& arc_ccfsm_cond_exec_p ()))
8598 sprintf (buf
, "add r12,pcl,@%s@pcl\n\tjl%%!%%* [r12]", fname
);
8600 sprintf (buf
, "jl%%! @%s", fname
);
8603 sprintf (buf
, "bl%%!%%* @%s", fname
);
8607 /* Return the SImode highpart of the DImode value IN. */
8610 disi_highpart (rtx in
)
8612 return simplify_gen_subreg (SImode
, in
, DImode
, TARGET_BIG_ENDIAN
? 0 : 4);
8615 /* Return length adjustment for INSN.
8617 A write to a core reg greater or equal to 32 must not be immediately
8618 followed by a use. Anticipate the length requirement to insert a nop
8619 between PRED and SUCC to prevent a hazard. */
8622 arc600_corereg_hazard (rtx_insn
*pred
, rtx_insn
*succ
)
8626 if (GET_CODE (PATTERN (pred
)) == SEQUENCE
)
8627 pred
= as_a
<rtx_sequence
*> (PATTERN (pred
))->insn (1);
8628 if (GET_CODE (PATTERN (succ
)) == SEQUENCE
)
8629 succ
= as_a
<rtx_sequence
*> (PATTERN (succ
))->insn (0);
8630 if (recog_memoized (pred
) == CODE_FOR_mulsi_600
8631 || recog_memoized (pred
) == CODE_FOR_umul_600
8632 || recog_memoized (pred
) == CODE_FOR_mac_600
8633 || recog_memoized (pred
) == CODE_FOR_mul64_600
8634 || recog_memoized (pred
) == CODE_FOR_mac64_600
8635 || recog_memoized (pred
) == CODE_FOR_umul64_600
8636 || recog_memoized (pred
) == CODE_FOR_umac64_600
)
8638 subrtx_iterator::array_type array
;
8639 FOR_EACH_SUBRTX (iter
, array
, PATTERN (pred
), NONCONST
)
8641 const_rtx x
= *iter
;
8642 switch (GET_CODE (x
))
8644 case SET
: case POST_INC
: case POST_DEC
: case PRE_INC
: case PRE_DEC
:
8647 /* This is also fine for PRE/POST_MODIFY, because they
8651 rtx dest
= XEXP (x
, 0);
8652 /* Check if this sets a an extension register. N.B. we use 61 for the
8653 condition codes, which is definitely not an extension register. */
8654 if (REG_P (dest
) && REGNO (dest
) >= 32 && REGNO (dest
) < 61
8655 /* Check if the same register is used by the PAT. */
8656 && (refers_to_regno_p
8658 REGNO (dest
) + (GET_MODE_SIZE (GET_MODE (dest
)) + 3) / 4U,
8659 PATTERN (succ
), 0)))
8665 /* Given a rtx, check if it is an assembly instruction or not. */
8668 arc_asm_insn_p (rtx x
)
8675 switch (GET_CODE (x
))
8682 return arc_asm_insn_p (SET_SRC (x
));
8686 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
8687 j
+= arc_asm_insn_p (XVECEXP (x
, 0, i
));
8700 A write to a core reg greater or equal to 32 must not be immediately
8701 followed by a use. Anticipate the length requirement to insert a nop
8702 between PRED and SUCC to prevent a hazard. */
8705 arc_hazard (rtx_insn
*pred
, rtx_insn
*succ
)
8707 if (!pred
|| !INSN_P (pred
) || !succ
|| !INSN_P (succ
))
8711 return arc600_corereg_hazard (pred
, succ
);
8716 /* Return length adjustment for INSN. */
8719 arc_adjust_insn_length (rtx_insn
*insn
, int len
, bool)
8723 /* We already handle sequences by ignoring the delay sequence flag. */
8724 if (GET_CODE (PATTERN (insn
)) == SEQUENCE
)
8727 /* Check for return with but one preceding insn since function
8729 if (TARGET_PAD_RETURN
8731 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
8732 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
8733 && get_attr_type (insn
) == TYPE_RETURN
)
8735 rtx_insn
*prev
= prev_active_insn (insn
);
8737 if (!prev
|| !(prev
= prev_active_insn (prev
))
8738 || ((NONJUMP_INSN_P (prev
)
8739 && GET_CODE (PATTERN (prev
)) == SEQUENCE
)
8740 ? CALL_ATTR (as_a
<rtx_sequence
*> (PATTERN (prev
))->insn (0),
8742 : CALL_ATTR (prev
, NON_SIBCALL
)))
8747 rtx_insn
*succ
= next_real_insn (insn
);
8749 /* One the ARC600, a write to an extension register must be separated
8751 if (succ
&& INSN_P (succ
))
8752 len
+= arc600_corereg_hazard (insn
, succ
);
8755 /* Restore extracted operands - otherwise splitters like the addsi3_mixed one
8757 extract_constrain_insn_cached (insn
);
8762 /* Return a copy of COND from *STATEP, inverted if that is indicated by the
8763 CC field of *STATEP. */
8766 arc_get_ccfsm_cond (struct arc_ccfsm
*statep
, bool reverse
)
8768 rtx cond
= statep
->cond
;
8769 int raw_cc
= get_arc_condition_code (cond
);
8771 raw_cc
= ARC_INVERSE_CONDITION_CODE (raw_cc
);
8773 if (statep
->cc
== raw_cc
)
8774 return copy_rtx (cond
);
8776 gcc_assert (ARC_INVERSE_CONDITION_CODE (raw_cc
) == statep
->cc
);
8778 machine_mode ccm
= GET_MODE (XEXP (cond
, 0));
8779 enum rtx_code code
= reverse_condition (GET_CODE (cond
));
8780 if (code
== UNKNOWN
|| ccm
== CC_FP_GTmode
|| ccm
== CC_FP_GEmode
)
8781 code
= reverse_condition_maybe_unordered (GET_CODE (cond
));
8783 return gen_rtx_fmt_ee (code
, GET_MODE (cond
),
8784 copy_rtx (XEXP (cond
, 0)), copy_rtx (XEXP (cond
, 1)));
8787 /* Return version of PAT conditionalized with COND, which is part of INSN.
8788 ANNULLED indicates if INSN is an annulled delay-slot insn.
8789 Register further changes if necessary. */
8791 conditionalize_nonjump (rtx pat
, rtx cond
, rtx insn
, bool annulled
)
8793 /* For commutative operators, we generally prefer to have
8794 the first source match the destination. */
8795 if (GET_CODE (pat
) == SET
)
8797 rtx src
= SET_SRC (pat
);
8799 if (COMMUTATIVE_P (src
))
8801 rtx src0
= XEXP (src
, 0);
8802 rtx src1
= XEXP (src
, 1);
8803 rtx dst
= SET_DEST (pat
);
8805 if (rtx_equal_p (src1
, dst
) && !rtx_equal_p (src0
, dst
)
8806 /* Leave add_n alone - the canonical form is to
8807 have the complex summand first. */
8809 pat
= gen_rtx_SET (dst
,
8810 gen_rtx_fmt_ee (GET_CODE (src
), GET_MODE (src
),
8815 /* dwarf2out.c:dwarf2out_frame_debug_expr doesn't know
8816 what to do with COND_EXEC. */
8817 if (RTX_FRAME_RELATED_P (insn
))
8819 /* If this is the delay slot insn of an anulled branch,
8820 dwarf2out.c:scan_trace understands the anulling semantics
8821 without the COND_EXEC. */
8822 gcc_assert (annulled
);
8823 rtx note
= alloc_reg_note (REG_FRAME_RELATED_EXPR
, pat
,
8825 validate_change (insn
, ®_NOTES (insn
), note
, 1);
8827 pat
= gen_rtx_COND_EXEC (VOIDmode
, cond
, pat
);
8831 /* Use the ccfsm machinery to do if conversion. */
8836 struct arc_ccfsm
*statep
= &cfun
->machine
->ccfsm_current
;
8838 memset (statep
, 0, sizeof *statep
);
8839 for (rtx_insn
*insn
= get_insns (); insn
; insn
= next_insn (insn
))
8841 arc_ccfsm_advance (insn
, statep
);
8843 switch (statep
->state
)
8849 /* Deleted branch. */
8850 arc_ccfsm_post_advance (insn
, statep
);
8851 gcc_assert (!IN_RANGE (statep
->state
, 1, 2));
8852 rtx_insn
*seq
= NEXT_INSN (PREV_INSN (insn
));
8853 if (GET_CODE (PATTERN (seq
)) == SEQUENCE
)
8855 rtx slot
= XVECEXP (PATTERN (seq
), 0, 1);
8856 rtx pat
= PATTERN (slot
);
8857 if (INSN_ANNULLED_BRANCH_P (insn
))
8860 = arc_get_ccfsm_cond (statep
, INSN_FROM_TARGET_P (slot
));
8861 pat
= gen_rtx_COND_EXEC (VOIDmode
, cond
, pat
);
8863 if (!validate_change (seq
, &PATTERN (seq
), pat
, 0))
8865 PUT_CODE (slot
, NOTE
);
8866 NOTE_KIND (slot
) = NOTE_INSN_DELETED
;
8870 set_insn_deleted (insn
);
8876 && statep
->target_label
== CODE_LABEL_NUMBER (insn
))
8878 arc_ccfsm_post_advance (insn
, statep
);
8879 if (--LABEL_NUSES (insn
) == 0)
8885 if (!NONDEBUG_INSN_P (insn
))
8888 /* Conditionalized insn. */
8890 rtx_insn
*prev
, *pprev
;
8891 rtx
*patp
, pat
, cond
;
8892 bool annulled
; annulled
= false;
8894 /* If this is a delay slot insn in a non-annulled branch,
8895 don't conditionalize it. N.B., this should be fine for
8896 conditional return too. However, don't do this for
8897 unconditional branches, as these would be encountered when
8898 processing an 'else' part. */
8899 prev
= PREV_INSN (insn
);
8900 pprev
= PREV_INSN (prev
);
8901 if (pprev
&& NEXT_INSN (NEXT_INSN (pprev
)) == NEXT_INSN (insn
)
8902 && JUMP_P (prev
) && get_attr_cond (prev
) == COND_USE
)
8904 if (!INSN_ANNULLED_BRANCH_P (prev
))
8909 patp
= &PATTERN (insn
);
8911 cond
= arc_get_ccfsm_cond (statep
, INSN_FROM_TARGET_P (insn
));
8912 if (NONJUMP_INSN_P (insn
) || CALL_P (insn
))
8914 /* ??? don't conditionalize if all side effects are dead
8915 in the not-execute case. */
8917 pat
= conditionalize_nonjump (pat
, cond
, insn
, annulled
);
8919 else if (simplejump_p (insn
))
8921 patp
= &SET_SRC (pat
);
8922 pat
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, *patp
, pc_rtx
);
8924 else if (JUMP_P (insn
) && ANY_RETURN_P (PATTERN (insn
)))
8926 pat
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, pat
, pc_rtx
);
8927 pat
= gen_rtx_SET (pc_rtx
, pat
);
8931 validate_change (insn
, patp
, pat
, 1);
8932 if (!apply_change_group ())
8936 rtx_insn
*next
= next_nonnote_insn (insn
);
8937 if (GET_CODE (next
) == BARRIER
)
8939 if (statep
->state
== 3)
8946 arc_ccfsm_post_advance (insn
, statep
);
8951 /* Find annulled delay insns and convert them to use the appropriate predicate.
8952 This allows branch shortening to size up these insns properly. */
8955 arc_predicate_delay_insns (void)
8957 for (rtx_insn
*insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
8959 rtx pat
, jump
, dlay
, src
, cond
, *patp
;
8962 if (!NONJUMP_INSN_P (insn
)
8963 || GET_CODE (pat
= PATTERN (insn
)) != SEQUENCE
)
8965 jump
= XVECEXP (pat
, 0, 0);
8966 dlay
= XVECEXP (pat
, 0, 1);
8967 if (!JUMP_P (jump
) || !INSN_ANNULLED_BRANCH_P (jump
))
8969 /* If the branch insn does the annulling, leave the delay insn alone. */
8970 if (!TARGET_AT_DBR_CONDEXEC
&& !INSN_FROM_TARGET_P (dlay
))
8972 /* ??? Could also leave DLAY un-conditionalized if its target is dead
8973 on the other path. */
8974 gcc_assert (GET_CODE (PATTERN (jump
)) == SET
);
8975 gcc_assert (SET_DEST (PATTERN (jump
)) == pc_rtx
);
8976 src
= SET_SRC (PATTERN (jump
));
8977 gcc_assert (GET_CODE (src
) == IF_THEN_ELSE
);
8978 cond
= XEXP (src
, 0);
8979 if (XEXP (src
, 2) == pc_rtx
)
8981 else if (XEXP (src
, 1) == pc_rtx
)
8985 if (reverse
!= !INSN_FROM_TARGET_P (dlay
))
8987 machine_mode ccm
= GET_MODE (XEXP (cond
, 0));
8988 enum rtx_code code
= reverse_condition (GET_CODE (cond
));
8989 if (code
== UNKNOWN
|| ccm
== CC_FP_GTmode
|| ccm
== CC_FP_GEmode
)
8990 code
= reverse_condition_maybe_unordered (GET_CODE (cond
));
8992 cond
= gen_rtx_fmt_ee (code
, GET_MODE (cond
),
8993 copy_rtx (XEXP (cond
, 0)),
8994 copy_rtx (XEXP (cond
, 1)));
8997 cond
= copy_rtx (cond
);
8998 patp
= &PATTERN (dlay
);
9000 pat
= conditionalize_nonjump (pat
, cond
, dlay
, true);
9001 validate_change (dlay
, patp
, pat
, 1);
9002 if (!apply_change_group ())
9008 /* For ARC600: If a write to a core reg >=32 appears in a delay slot
9009 (other than of a forward brcc), it creates a hazard when there is a read
9010 of the same register at the branch target. We can't know what is at the
9011 branch target of calls, and for branches, we don't really know before the
9012 end of delay slot scheduling, either. Not only can individual instruction
9013 be hoisted out into a delay slot, a basic block can also be emptied this
9014 way, and branch and/or fall through targets be redirected. Hence we don't
9015 want such writes in a delay slot. */
9017 /* Return nonzreo iff INSN writes to an extension core register. */
9020 arc_write_ext_corereg (rtx insn
)
9022 subrtx_iterator::array_type array
;
9023 FOR_EACH_SUBRTX (iter
, array
, PATTERN (insn
), NONCONST
)
9025 const_rtx x
= *iter
;
9026 switch (GET_CODE (x
))
9028 case SET
: case POST_INC
: case POST_DEC
: case PRE_INC
: case PRE_DEC
:
9031 /* This is also fine for PRE/POST_MODIFY, because they
9035 const_rtx dest
= XEXP (x
, 0);
9036 if (REG_P (dest
) && REGNO (dest
) >= 32 && REGNO (dest
) < 61)
9042 /* This is like the hook, but returns NULL when it can't / won't generate
9043 a legitimate address. */
9046 arc_legitimize_address_0 (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
9051 if (flag_pic
&& SYMBOLIC_CONST (x
))
9052 (x
) = arc_legitimize_pic_address (x
, 0);
9054 if (GET_CODE (addr
) == CONST
)
9055 addr
= XEXP (addr
, 0);
9056 if (GET_CODE (addr
) == PLUS
9057 && CONST_INT_P (XEXP (addr
, 1))
9058 && ((GET_CODE (XEXP (addr
, 0)) == SYMBOL_REF
9059 && !SYMBOL_REF_FUNCTION_P (XEXP (addr
, 0)))
9060 || (REG_P (XEXP (addr
, 0))
9061 && (INTVAL (XEXP (addr
, 1)) & 252))))
9063 HOST_WIDE_INT offs
, upper
;
9064 int size
= GET_MODE_SIZE (mode
);
9066 offs
= INTVAL (XEXP (addr
, 1));
9067 upper
= (offs
+ 256 * size
) & ~511 * size
;
9068 inner
= plus_constant (Pmode
, XEXP (addr
, 0), upper
);
9069 #if 0 /* ??? this produces worse code for EEMBC idctrn01 */
9070 if (GET_CODE (x
) == CONST
)
9071 inner
= gen_rtx_CONST (Pmode
, inner
);
9073 addr
= plus_constant (Pmode
, force_reg (Pmode
, inner
), offs
- upper
);
9076 else if (GET_CODE (addr
) == SYMBOL_REF
&& !SYMBOL_REF_FUNCTION_P (addr
))
9077 x
= force_reg (Pmode
, x
);
9078 if (memory_address_p ((machine_mode
) mode
, x
))
9084 arc_legitimize_address (rtx orig_x
, rtx oldx
, machine_mode mode
)
9086 if (GET_CODE (orig_x
) == SYMBOL_REF
)
9088 enum tls_model model
= SYMBOL_REF_TLS_MODEL (orig_x
);
9090 return arc_legitimize_tls_address (orig_x
, model
);
9093 rtx new_x
= arc_legitimize_address_0 (orig_x
, oldx
, mode
);
9101 arc_delegitimize_address_0 (rtx op
)
9103 switch (GET_CODE (op
))
9106 return arc_delegitimize_address_0 (XEXP (op
, 0));
9109 switch (XINT (op
, 1))
9111 case ARC_UNSPEC_GOT
:
9112 case ARC_UNSPEC_GOTOFFPC
:
9113 return XVECEXP (op
, 0, 0);
9121 rtx t1
= arc_delegitimize_address_0 (XEXP (op
, 0));
9122 rtx t2
= XEXP (op
, 1);
9125 return gen_rtx_PLUS (GET_MODE (op
), t1
, t2
);
9136 arc_delegitimize_address (rtx orig_x
)
9143 x
= arc_delegitimize_address_0 (x
);
9148 x
= replace_equiv_address_nv (orig_x
, x
);
9152 /* Return a REG rtx for acc1. N.B. the gcc-internal representation may
9153 differ from the hardware register number in order to allow the generic
9154 code to correctly split the concatenation of acc1 and acc2. */
9159 return gen_rtx_REG (SImode
, TARGET_BIG_ENDIAN
? 56: 57);
9162 /* Return a REG rtx for acc2. N.B. the gcc-internal representation may
9163 differ from the hardware register number in order to allow the generic
9164 code to correctly split the concatenation of acc1 and acc2. */
9169 return gen_rtx_REG (SImode
, TARGET_BIG_ENDIAN
? 57: 56);
9172 /* Return a REG rtx for mlo. N.B. the gcc-internal representation may
9173 differ from the hardware register number in order to allow the generic
9174 code to correctly split the concatenation of mhi and mlo. */
9179 return gen_rtx_REG (SImode
, TARGET_BIG_ENDIAN
? 59: 58);
9182 /* Return a REG rtx for mhi. N.B. the gcc-internal representation may
9183 differ from the hardware register number in order to allow the generic
9184 code to correctly split the concatenation of mhi and mlo. */
9189 return gen_rtx_REG (SImode
, TARGET_BIG_ENDIAN
? 58: 59);
9192 /* FIXME: a parameter should be added, and code added to final.c,
9193 to reproduce this functionality in shorten_branches. */
9195 /* Return nonzero iff BRANCH should be unaligned if possible by upsizing
9196 a previous instruction. */
9198 arc_unalign_branch_p (rtx branch
)
9202 if (!TARGET_UNALIGN_BRANCH
)
9204 /* Do not do this if we have a filled delay slot. */
9205 if (get_attr_delay_slot_filled (branch
) == DELAY_SLOT_FILLED_YES
9206 && !NEXT_INSN (branch
)->deleted ())
9208 note
= find_reg_note (branch
, REG_BR_PROB
, 0);
9210 || (arc_unalign_prob_threshold
&& !br_prob_note_reliable_p (note
))
9211 || INTVAL (XEXP (note
, 0)) < arc_unalign_prob_threshold
);
9215 /* When estimating sizes during arc_reorg, when optimizing for speed, there
9216 are three reasons why we need to consider branches to be length 6:
9217 - annull-false delay slot insns are implemented using conditional execution,
9218 thus preventing short insn formation where used.
9219 - for ARC600: annul-true delay slot insns are implemented where possible
9220 using conditional execution, preventing short insn formation where used.
9221 - for ARC700: likely or somewhat likely taken branches are made long and
9222 unaligned if possible to avoid branch penalty. */
9225 arc_branch_size_unknown_p (void)
9227 return !optimize_size
&& arc_reorg_in_progress
;
9230 /* We are about to output a return insn. Add padding if necessary to avoid
9231 a mispredict. A return could happen immediately after the function
9232 start, but after a call we know that there will be at least a blink
9236 arc_pad_return (void)
9238 rtx_insn
*insn
= current_output_insn
;
9239 rtx_insn
*prev
= prev_active_insn (insn
);
9244 fputs ("\tnop_s\n", asm_out_file
);
9245 cfun
->machine
->unalign
^= 2;
9248 /* If PREV is a sequence, we know it must be a branch / jump or a tailcall,
9249 because after a call, we'd have to restore blink first. */
9250 else if (GET_CODE (PATTERN (prev
)) == SEQUENCE
)
9254 want_long
= (get_attr_length (prev
) == 2);
9255 prev
= prev_active_insn (prev
);
9258 || ((NONJUMP_INSN_P (prev
) && GET_CODE (PATTERN (prev
)) == SEQUENCE
)
9259 ? CALL_ATTR (as_a
<rtx_sequence
*> (PATTERN (prev
))->insn (0),
9261 : CALL_ATTR (prev
, NON_SIBCALL
)))
9264 cfun
->machine
->size_reason
9265 = "call/return and return/return must be 6 bytes apart to avoid mispredict";
9266 else if (TARGET_UNALIGN_BRANCH
&& cfun
->machine
->unalign
)
9268 cfun
->machine
->size_reason
9269 = "Long unaligned jump avoids non-delay slot penalty";
9272 /* Disgorge delay insn, if there is any, and it may be moved. */
9274 /* ??? Annulled would be OK if we can and do conditionalize
9275 the delay slot insn accordingly. */
9276 && !INSN_ANNULLED_BRANCH_P (insn
)
9277 && (get_attr_cond (insn
) != COND_USE
9278 || !reg_set_p (gen_rtx_REG (CCmode
, CC_REG
),
9279 XVECEXP (final_sequence
, 0, 1))))
9281 prev
= as_a
<rtx_insn
*> (XVECEXP (final_sequence
, 0, 1));
9282 gcc_assert (!prev_real_insn (insn
)
9283 || !arc_hazard (prev_real_insn (insn
), prev
));
9284 cfun
->machine
->force_short_suffix
= !want_long
;
9285 rtx save_pred
= current_insn_predicate
;
9286 final_scan_insn (prev
, asm_out_file
, optimize
, 1, NULL
);
9287 cfun
->machine
->force_short_suffix
= -1;
9288 prev
->set_deleted ();
9289 current_output_insn
= insn
;
9290 current_insn_predicate
= save_pred
;
9293 fputs ("\tnop\n", asm_out_file
);
9296 fputs ("\tnop_s\n", asm_out_file
);
9297 cfun
->machine
->unalign
^= 2;
9303 /* The usual; we set up our machine_function data. */
9305 static struct machine_function
*
9306 arc_init_machine_status (void)
9308 struct machine_function
*machine
;
9309 machine
= ggc_cleared_alloc
<machine_function
> ();
9310 machine
->fn_type
= ARC_FUNCTION_UNKNOWN
;
9311 machine
->force_short_suffix
= -1;
9316 /* Implements INIT_EXPANDERS. We just set up to call the above
9320 arc_init_expanders (void)
9322 init_machine_status
= arc_init_machine_status
;
9325 /* Check if OP is a proper parallel of a millicode call pattern. OFFSET
9326 indicates a number of elements to ignore - that allows to have a
9327 sibcall pattern that starts with (return). LOAD_P is zero for store
9328 multiple (for prologues), and one for load multiples (for epilogues),
9329 and two for load multiples where no final clobber of blink is required.
9330 We also skip the first load / store element since this is supposed to
9331 be checked in the instruction pattern. */
9334 arc_check_millicode (rtx op
, int offset
, int load_p
)
9336 int len
= XVECLEN (op
, 0) - offset
;
9341 if (len
< 2 || len
> 13)
9347 rtx elt
= XVECEXP (op
, 0, --len
);
9349 if (GET_CODE (elt
) != CLOBBER
9350 || !REG_P (XEXP (elt
, 0))
9351 || REGNO (XEXP (elt
, 0)) != RETURN_ADDR_REGNUM
9352 || len
< 3 || len
> 13)
9355 for (i
= 1; i
< len
; i
++)
9357 rtx elt
= XVECEXP (op
, 0, i
+ offset
);
9360 if (GET_CODE (elt
) != SET
)
9362 mem
= XEXP (elt
, load_p
);
9363 reg
= XEXP (elt
, 1-load_p
);
9364 if (!REG_P (reg
) || REGNO (reg
) != 13U+i
|| !MEM_P (mem
))
9366 addr
= XEXP (mem
, 0);
9367 if (GET_CODE (addr
) != PLUS
9368 || !rtx_equal_p (stack_pointer_rtx
, XEXP (addr
, 0))
9369 || !CONST_INT_P (XEXP (addr
, 1)) || INTVAL (XEXP (addr
, 1)) != i
*4)
9375 /* Accessor functions for cfun->machine->unalign. */
9378 arc_get_unalign (void)
9380 return cfun
->machine
->unalign
;
9384 arc_clear_unalign (void)
9387 cfun
->machine
->unalign
= 0;
9391 arc_toggle_unalign (void)
9393 cfun
->machine
->unalign
^= 2;
9396 /* Operands 0..2 are the operands of a addsi which uses a 12 bit
9397 constant in operand 2, but which would require a LIMM because of
9399 operands 3 and 4 are new SET_SRCs for operands 0. */
9402 split_addsi (rtx
*operands
)
9404 int val
= INTVAL (operands
[2]);
9406 /* Try for two short insns first. Lengths being equal, we prefer
9407 expansions with shorter register lifetimes. */
9408 if (val
> 127 && val
<= 255
9409 && satisfies_constraint_Rcq (operands
[0]))
9411 operands
[3] = operands
[2];
9412 operands
[4] = gen_rtx_PLUS (SImode
, operands
[0], operands
[1]);
9416 operands
[3] = operands
[1];
9417 operands
[4] = gen_rtx_PLUS (SImode
, operands
[0], operands
[2]);
9421 /* Operands 0..2 are the operands of a subsi which uses a 12 bit
9422 constant in operand 1, but which would require a LIMM because of
9424 operands 3 and 4 are new SET_SRCs for operands 0. */
9427 split_subsi (rtx
*operands
)
9429 int val
= INTVAL (operands
[1]);
9431 /* Try for two short insns first. Lengths being equal, we prefer
9432 expansions with shorter register lifetimes. */
9433 if (satisfies_constraint_Rcq (operands
[0])
9434 && satisfies_constraint_Rcq (operands
[2]))
9436 if (val
>= -31 && val
<= 127)
9438 operands
[3] = gen_rtx_NEG (SImode
, operands
[2]);
9439 operands
[4] = gen_rtx_PLUS (SImode
, operands
[0], operands
[1]);
9442 else if (val
>= 0 && val
< 255)
9444 operands
[3] = operands
[1];
9445 operands
[4] = gen_rtx_MINUS (SImode
, operands
[0], operands
[2]);
9449 /* If the destination is not an ARCompact16 register, we might
9450 still have a chance to make a short insn if the source is;
9451 we need to start with a reg-reg move for this. */
9452 operands
[3] = operands
[2];
9453 operands
[4] = gen_rtx_MINUS (SImode
, operands
[1], operands
[0]);
9456 /* Handle DOUBLE_REGS uses.
9457 Operand 0: destination register
9458 Operand 1: source register */
9461 arc_process_double_reg_moves (rtx
*operands
)
9463 rtx dest
= operands
[0];
9464 rtx src
= operands
[1];
9466 enum usesDxState
{ none
, srcDx
, destDx
, maxDx
};
9467 enum usesDxState state
= none
;
9469 if (refers_to_regno_p (40, 44, src
, 0))
9471 if (refers_to_regno_p (40, 44, dest
, 0))
9473 /* Via arc_register_move_cost, we should never see D,D moves. */
9474 gcc_assert (state
== none
);
9483 /* Without the LR insn, we need to split this into a
9484 sequence of insns which will use the DEXCLx and DADDHxy
9485 insns to be able to read the Dx register in question. */
9486 if (TARGET_DPFP_DISABLE_LRSR
)
9488 /* gen *movdf_insn_nolrsr */
9489 rtx set
= gen_rtx_SET (dest
, src
);
9490 rtx use1
= gen_rtx_USE (VOIDmode
, const1_rtx
);
9491 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, use1
)));
9495 /* When we have 'mov D, r' or 'mov D, D' then get the target
9496 register pair for use with LR insn. */
9497 rtx destHigh
= simplify_gen_subreg (SImode
, dest
, DFmode
,
9498 TARGET_BIG_ENDIAN
? 0 : 4);
9499 rtx destLow
= simplify_gen_subreg (SImode
, dest
, DFmode
,
9500 TARGET_BIG_ENDIAN
? 4 : 0);
9502 /* Produce the two LR insns to get the high and low parts. */
9503 emit_insn (gen_rtx_SET (destHigh
,
9504 gen_rtx_UNSPEC_VOLATILE (Pmode
,
9506 VUNSPEC_ARC_LR_HIGH
)));
9507 emit_insn (gen_rtx_SET (destLow
,
9508 gen_rtx_UNSPEC_VOLATILE (Pmode
,
9513 else if (state
== destDx
)
9515 /* When we have 'mov r, D' or 'mov D, D' and we have access to the
9516 LR insn get the target register pair. */
9517 rtx srcHigh
= simplify_gen_subreg (SImode
, src
, DFmode
,
9518 TARGET_BIG_ENDIAN
? 0 : 4);
9519 rtx srcLow
= simplify_gen_subreg (SImode
, src
, DFmode
,
9520 TARGET_BIG_ENDIAN
? 4 : 0);
9522 emit_insn (gen_dexcl_2op (dest
, srcHigh
, srcLow
));
9530 /* operands 0..1 are the operands of a 64 bit move instruction.
9531 split it into two moves with operands 2/3 and 4/5. */
9534 arc_split_move (rtx
*operands
)
9536 machine_mode mode
= GET_MODE (operands
[0]);
9543 if (arc_process_double_reg_moves (operands
))
9548 && ((memory_operand (operands
[0], mode
)
9549 && (even_register_operand (operands
[1], mode
)
9550 || satisfies_constraint_Cm3 (operands
[1])))
9551 || (memory_operand (operands
[1], mode
)
9552 && even_register_operand (operands
[0], mode
))))
9554 emit_move_insn (operands
[0], operands
[1]);
9558 if (TARGET_PLUS_QMACW
9559 && GET_CODE (operands
[1]) == CONST_VECTOR
)
9561 HOST_WIDE_INT intval0
, intval1
;
9562 if (GET_MODE (operands
[1]) == V2SImode
)
9564 intval0
= INTVAL (XVECEXP (operands
[1], 0, 0));
9565 intval1
= INTVAL (XVECEXP (operands
[1], 0, 1));
9569 intval1
= INTVAL (XVECEXP (operands
[1], 0, 3)) << 16;
9570 intval1
|= INTVAL (XVECEXP (operands
[1], 0, 2)) & 0xFFFF;
9571 intval0
= INTVAL (XVECEXP (operands
[1], 0, 1)) << 16;
9572 intval0
|= INTVAL (XVECEXP (operands
[1], 0, 0)) & 0xFFFF;
9574 xop
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]));
9575 xop
[3] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
9576 xop
[2] = GEN_INT (trunc_int_for_mode (intval0
, SImode
));
9577 xop
[1] = GEN_INT (trunc_int_for_mode (intval1
, SImode
));
9578 emit_move_insn (xop
[0], xop
[2]);
9579 emit_move_insn (xop
[3], xop
[1]);
9583 for (i
= 0; i
< 2; i
++)
9585 if (MEM_P (operands
[i
]) && auto_inc_p (XEXP (operands
[i
], 0)))
9587 rtx addr
= XEXP (operands
[i
], 0);
9591 gcc_assert (!reg_overlap_mentioned_p (operands
[0], addr
));
9592 switch (GET_CODE (addr
))
9594 case PRE_DEC
: o
= GEN_INT (-8); goto pre_modify
;
9595 case PRE_INC
: o
= GEN_INT (8); goto pre_modify
;
9596 case PRE_MODIFY
: o
= XEXP (XEXP (addr
, 1), 1);
9600 case POST_DEC
: o
= GEN_INT (-8); goto post_modify
;
9601 case POST_INC
: o
= GEN_INT (8); goto post_modify
;
9602 case POST_MODIFY
: o
= XEXP (XEXP (addr
, 1), 1);
9611 xop
[0+i
] = adjust_automodify_address_nv
9612 (operands
[i
], SImode
,
9613 gen_rtx_fmt_ee (code
, Pmode
, r
,
9614 gen_rtx_PLUS (Pmode
, r
, o
)),
9616 xop
[2+i
] = adjust_automodify_address_nv
9617 (operands
[i
], SImode
, plus_constant (Pmode
, r
, 4), 4);
9621 xop
[0+i
] = operand_subword (operands
[i
], 0, 0, mode
);
9622 xop
[2+i
] = operand_subword (operands
[i
], 1, 0, mode
);
9625 if (reg_overlap_mentioned_p (xop
[0], xop
[3]))
9628 gcc_assert (!reg_overlap_mentioned_p (xop
[2], xop
[1]));
9631 emit_move_insn (xop
[0 + swap
], xop
[1 + swap
]);
9632 emit_move_insn (xop
[2 - swap
], xop
[3 - swap
]);
9636 /* Select between the instruction output templates s_tmpl (for short INSNs)
9637 and l_tmpl (for long INSNs). */
9640 arc_short_long (rtx_insn
*insn
, const char *s_tmpl
, const char *l_tmpl
)
9642 int is_short
= arc_verify_short (insn
, cfun
->machine
->unalign
, -1);
9644 extract_constrain_insn_cached (insn
);
9645 return is_short
? s_tmpl
: l_tmpl
;
9648 /* Searches X for any reference to REGNO, returning the rtx of the
9649 reference found if any. Otherwise, returns NULL_RTX. */
9652 arc_regno_use_in (unsigned int regno
, rtx x
)
9658 if (REG_P (x
) && refers_to_regno_p (regno
, x
))
9661 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
9662 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
9666 if ((tem
= regno_use_in (regno
, XEXP (x
, i
))))
9669 else if (fmt
[i
] == 'E')
9670 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9671 if ((tem
= regno_use_in (regno
, XVECEXP (x
, i
, j
))))
9678 /* Return the integer value of the "type" attribute for INSN, or -1 if
9679 INSN can't have attributes. */
9682 arc_attr_type (rtx_insn
*insn
)
9684 if (NONJUMP_INSN_P (insn
)
9685 ? (GET_CODE (PATTERN (insn
)) == USE
9686 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
9688 ? (GET_CODE (PATTERN (insn
)) == ADDR_VEC
9689 || GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
)
9692 return get_attr_type (insn
);
9695 /* Return true if insn sets the condition codes. */
9698 arc_sets_cc_p (rtx_insn
*insn
)
9700 if (NONJUMP_INSN_P (insn
))
9701 if (rtx_sequence
*seq
= dyn_cast
<rtx_sequence
*> (PATTERN (insn
)))
9702 insn
= seq
->insn (seq
->len () - 1);
9703 return arc_attr_type (insn
) == TYPE_COMPARE
;
9706 /* Return true if INSN is an instruction with a delay slot we may want
9710 arc_need_delay (rtx_insn
*insn
)
9714 if (!flag_delayed_branch
)
9716 /* The return at the end of a function needs a delay slot. */
9717 if (NONJUMP_INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == USE
9718 && (!(next
= next_active_insn (insn
))
9719 || ((!NONJUMP_INSN_P (next
) || GET_CODE (PATTERN (next
)) != SEQUENCE
)
9720 && arc_attr_type (next
) == TYPE_RETURN
))
9721 && (!TARGET_PAD_RETURN
9722 || (prev_active_insn (insn
)
9723 && prev_active_insn (prev_active_insn (insn
))
9724 && prev_active_insn (prev_active_insn (prev_active_insn (insn
))))))
9726 if (NONJUMP_INSN_P (insn
)
9727 ? (GET_CODE (PATTERN (insn
)) == USE
9728 || GET_CODE (PATTERN (insn
)) == CLOBBER
9729 || GET_CODE (PATTERN (insn
)) == SEQUENCE
)
9731 ? (GET_CODE (PATTERN (insn
)) == ADDR_VEC
9732 || GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
)
9735 return num_delay_slots (insn
) != 0;
9738 /* Return true if the scheduling pass(es) has/have already run,
9739 i.e. where possible, we should try to mitigate high latencies
9740 by different instruction selection. */
9743 arc_scheduling_not_expected (void)
9745 return cfun
->machine
->arc_reorg_started
;
9749 arc_label_align (rtx_insn
*label
)
9751 /* Code has a minimum p2 alignment of 1, which we must restore after an
9753 if (align_labels_log
< 1)
9755 rtx_insn
*next
= next_nonnote_nondebug_insn (label
);
9756 if (INSN_P (next
) && recog_memoized (next
) >= 0)
9759 return align_labels_log
;
9762 /* Return true if LABEL is in executable code. */
9765 arc_text_label (rtx_insn
*label
)
9769 /* ??? We use deleted labels like they were still there, see
9770 gcc.c-torture/compile/20000326-2.c . */
9771 gcc_assert (GET_CODE (label
) == CODE_LABEL
9772 || (GET_CODE (label
) == NOTE
9773 && NOTE_KIND (label
) == NOTE_INSN_DELETED_LABEL
));
9774 next
= next_nonnote_insn (label
);
9776 return (!JUMP_TABLE_DATA_P (next
)
9777 || GET_CODE (PATTERN (next
)) != ADDR_VEC
);
9778 else if (!PREV_INSN (label
))
9779 /* ??? sometimes text labels get inserted very late, see
9780 gcc.dg/torture/stackalign/comp-goto-1.c */
9785 /* Without this, gcc.dg/tree-prof/bb-reorg.c fails to assemble
9786 when compiling with -O2 -freorder-blocks-and-partition -fprofile-use
9787 -D_PROFILE_USE; delay branch scheduling then follows a crossing jump
9788 to redirect two breqs. */
9791 arc_can_follow_jump (const rtx_insn
*follower
, const rtx_insn
*followee
)
9793 /* ??? get_attr_type is declared to take an rtx. */
9794 union { const rtx_insn
*c
; rtx_insn
*r
; } u
;
9797 if (CROSSING_JUMP_P (followee
))
9798 switch (get_attr_type (u
.r
))
9801 if (get_attr_length (u
.r
) != 2)
9805 case TYPE_BRCC_NO_DELAY_SLOT
:
9813 /* Return the register number of the register holding the return address
9814 for a function of type TYPE. */
9817 arc_return_address_register (unsigned int fn_type
)
9821 if (ARC_INTERRUPT_P (fn_type
))
9823 if (((fn_type
& ARC_FUNCTION_ILINK1
) | ARC_FUNCTION_FIRQ
) != 0)
9824 regno
= ILINK1_REGNUM
;
9825 else if ((fn_type
& ARC_FUNCTION_ILINK2
) != 0)
9826 regno
= ILINK2_REGNUM
;
9830 else if (ARC_NORMAL_P (fn_type
) || ARC_NAKED_P (fn_type
))
9831 regno
= RETURN_ADDR_REGNUM
;
9833 gcc_assert (regno
!= 0);
9837 /* Implement EPILOGUE_USES.
9838 Return true if REGNO should be added to the deemed uses of the epilogue.
9840 We have to make sure all the register restore instructions are
9841 known to be live in interrupt functions, plus the blink register if
9842 it is clobbered by the isr. */
9845 arc_epilogue_uses (int regno
)
9847 unsigned int fn_type
;
9849 if (regno
== arc_tp_regno
)
9852 fn_type
= arc_compute_function_type (cfun
);
9853 if (reload_completed
)
9855 if (ARC_INTERRUPT_P (cfun
->machine
->fn_type
))
9857 if (!fixed_regs
[regno
])
9859 return ((regno
== arc_return_address_register (fn_type
))
9860 || (regno
== RETURN_ADDR_REGNUM
));
9863 return regno
== RETURN_ADDR_REGNUM
;
9866 return regno
== arc_return_address_register (fn_type
);
9869 /* Helper for EH_USES macro. */
9872 arc_eh_uses (int regno
)
9874 if (regno
== arc_tp_regno
)
9879 #ifndef TARGET_NO_LRA
9880 #define TARGET_NO_LRA !TARGET_LRA
9886 return !TARGET_NO_LRA
;
9889 /* ??? Should we define TARGET_REGISTER_PRIORITY? We might perfer to use
9890 Rcq registers, because some insn are shorter with them. OTOH we already
9891 have separate alternatives for this purpose, and other insns don't
9892 mind, so maybe we should rather prefer the other registers?
9893 We need more data, and we can only get that if we allow people to
9896 arc_register_priority (int r
)
9898 switch (arc_lra_priority_tag
)
9900 case ARC_LRA_PRIORITY_NONE
:
9902 case ARC_LRA_PRIORITY_NONCOMPACT
:
9903 return ((((r
& 7) ^ 4) - 4) & 15) != r
;
9904 case ARC_LRA_PRIORITY_COMPACT
:
9905 return ((((r
& 7) ^ 4) - 4) & 15) == r
;
9912 arc_spill_class (reg_class_t
/* orig_class */, machine_mode
)
9914 return GENERAL_REGS
;
9918 arc_legitimize_reload_address (rtx
*p
, machine_mode mode
, int opnum
,
9922 enum reload_type type
= (enum reload_type
) itype
;
9924 if (GET_CODE (x
) == PLUS
9925 && CONST_INT_P (XEXP (x
, 1))
9926 && (RTX_OK_FOR_BASE_P (XEXP (x
, 0), true)
9927 || (REG_P (XEXP (x
, 0))
9928 && reg_equiv_constant (REGNO (XEXP (x
, 0))))))
9930 int scale
= GET_MODE_SIZE (mode
);
9932 rtx index_rtx
= XEXP (x
, 1);
9933 HOST_WIDE_INT offset
= INTVAL (index_rtx
), offset_base
;
9938 if ((scale
-1) & offset
)
9942 = ((offset
+ (256 << shift
))
9943 & ((HOST_WIDE_INT
)((unsigned HOST_WIDE_INT
) -512 << shift
)));
9944 /* Sometimes the normal form does not suit DImode. We
9945 could avoid that by using smaller ranges, but that
9946 would give less optimized code when SImode is
9948 if (GET_MODE_SIZE (mode
) + offset
- offset_base
<= (256 << shift
))
9953 regno
= REGNO (reg
);
9954 sum2
= sum
= plus_constant (Pmode
, reg
, offset_base
);
9956 if (reg_equiv_constant (regno
))
9958 sum2
= plus_constant (Pmode
, reg_equiv_constant (regno
),
9960 if (GET_CODE (sum2
) == PLUS
)
9961 sum2
= gen_rtx_CONST (Pmode
, sum2
);
9963 *p
= gen_rtx_PLUS (Pmode
, sum
, GEN_INT (offset
- offset_base
));
9964 push_reload (sum2
, NULL_RTX
, &XEXP (*p
, 0), NULL
,
9965 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0, opnum
,
9970 /* We must re-recognize what we created before. */
9971 else if (GET_CODE (x
) == PLUS
9972 && GET_CODE (XEXP (x
, 0)) == PLUS
9973 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
9974 && REG_P (XEXP (XEXP (x
, 0), 0))
9975 && CONST_INT_P (XEXP (x
, 1)))
9977 /* Because this address is so complex, we know it must have
9978 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus,
9979 it is already unshared, and needs no further unsharing. */
9980 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
9981 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0, opnum
, type
);
9987 /* Implement TARGET_USE_BY_PIECES_INFRASTRUCTURE_P. */
9990 arc_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size
,
9992 enum by_pieces_operation op
,
9995 /* Let the movmem expander handle small block moves. */
9996 if (op
== MOVE_BY_PIECES
)
9999 return default_use_by_pieces_infrastructure_p (size
, align
, op
, speed_p
);
10002 /* Emit a (pre) memory barrier around an atomic sequence according to
10006 arc_pre_atomic_barrier (enum memmodel model
)
10008 if (need_atomic_barrier_p (model
, true))
10009 emit_insn (gen_memory_barrier ());
10012 /* Emit a (post) memory barrier around an atomic sequence according to
10016 arc_post_atomic_barrier (enum memmodel model
)
10018 if (need_atomic_barrier_p (model
, false))
10019 emit_insn (gen_memory_barrier ());
10022 /* Expand a compare and swap pattern. */
10025 emit_unlikely_jump (rtx insn
)
10027 rtx_insn
*jump
= emit_jump_insn (insn
);
10028 add_reg_br_prob_note (jump
, profile_probability::very_unlikely ());
10031 /* Expand code to perform a 8 or 16-bit compare and swap by doing
10032 32-bit compare and swap on the word containing the byte or
10033 half-word. The difference between a weak and a strong CAS is that
10034 the weak version may simply fail. The strong version relies on two
10035 loops, one checks if the SCOND op is succsfully or not, the other
10036 checks if the 32 bit accessed location which contains the 8 or 16
10037 bit datum is not changed by other thread. The first loop is
10038 implemented by the atomic_compare_and_swapsi_1 pattern. The second
10039 loops is implemented by this routine. */
10042 arc_expand_compare_and_swap_qh (rtx bool_result
, rtx result
, rtx mem
,
10043 rtx oldval
, rtx newval
, rtx weak
,
10044 rtx mod_s
, rtx mod_f
)
10046 rtx addr1
= force_reg (Pmode
, XEXP (mem
, 0));
10047 rtx addr
= gen_reg_rtx (Pmode
);
10048 rtx off
= gen_reg_rtx (SImode
);
10049 rtx oldv
= gen_reg_rtx (SImode
);
10050 rtx newv
= gen_reg_rtx (SImode
);
10051 rtx oldvalue
= gen_reg_rtx (SImode
);
10052 rtx newvalue
= gen_reg_rtx (SImode
);
10053 rtx res
= gen_reg_rtx (SImode
);
10054 rtx resv
= gen_reg_rtx (SImode
);
10055 rtx memsi
, val
, mask
, end_label
, loop_label
, cc
, x
;
10057 bool is_weak
= (weak
!= const0_rtx
);
10059 /* Truncate the address. */
10060 emit_insn (gen_rtx_SET (addr
,
10061 gen_rtx_AND (Pmode
, addr1
, GEN_INT (-4))));
10063 /* Compute the datum offset. */
10064 emit_insn (gen_rtx_SET (off
,
10065 gen_rtx_AND (SImode
, addr1
, GEN_INT (3))));
10066 if (TARGET_BIG_ENDIAN
)
10067 emit_insn (gen_rtx_SET (off
,
10068 gen_rtx_MINUS (SImode
,
10069 (GET_MODE (mem
) == QImode
) ?
10070 GEN_INT (3) : GEN_INT (2), off
)));
10072 /* Normal read from truncated address. */
10073 memsi
= gen_rtx_MEM (SImode
, addr
);
10074 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
10075 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
10077 val
= copy_to_reg (memsi
);
10079 /* Convert the offset in bits. */
10080 emit_insn (gen_rtx_SET (off
,
10081 gen_rtx_ASHIFT (SImode
, off
, GEN_INT (3))));
10083 /* Get the proper mask. */
10084 if (GET_MODE (mem
) == QImode
)
10085 mask
= force_reg (SImode
, GEN_INT (0xff));
10087 mask
= force_reg (SImode
, GEN_INT (0xffff));
10089 emit_insn (gen_rtx_SET (mask
,
10090 gen_rtx_ASHIFT (SImode
, mask
, off
)));
10092 /* Prepare the old and new values. */
10093 emit_insn (gen_rtx_SET (val
,
10094 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
10097 oldval
= gen_lowpart (SImode
, oldval
);
10098 emit_insn (gen_rtx_SET (oldv
,
10099 gen_rtx_ASHIFT (SImode
, oldval
, off
)));
10101 newval
= gen_lowpart_common (SImode
, newval
);
10102 emit_insn (gen_rtx_SET (newv
,
10103 gen_rtx_ASHIFT (SImode
, newval
, off
)));
10105 emit_insn (gen_rtx_SET (oldv
,
10106 gen_rtx_AND (SImode
, oldv
, mask
)));
10108 emit_insn (gen_rtx_SET (newv
,
10109 gen_rtx_AND (SImode
, newv
, mask
)));
10113 end_label
= gen_label_rtx ();
10114 loop_label
= gen_label_rtx ();
10115 emit_label (loop_label
);
10118 /* Make the old and new values. */
10119 emit_insn (gen_rtx_SET (oldvalue
,
10120 gen_rtx_IOR (SImode
, oldv
, val
)));
10122 emit_insn (gen_rtx_SET (newvalue
,
10123 gen_rtx_IOR (SImode
, newv
, val
)));
10125 /* Try an 32bit atomic compare and swap. It clobbers the CC
10127 emit_insn (gen_atomic_compare_and_swapsi_1 (res
, memsi
, oldvalue
, newvalue
,
10128 weak
, mod_s
, mod_f
));
10130 /* Regardless of the weakness of the operation, a proper boolean
10131 result needs to be provided. */
10132 x
= gen_rtx_REG (CC_Zmode
, CC_REG
);
10133 x
= gen_rtx_EQ (SImode
, x
, const0_rtx
);
10134 emit_insn (gen_rtx_SET (bool_result
, x
));
10138 /* Check the results: if the atomic op is successfully the goto
10140 x
= gen_rtx_REG (CC_Zmode
, CC_REG
);
10141 x
= gen_rtx_EQ (VOIDmode
, x
, const0_rtx
);
10142 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, x
,
10143 gen_rtx_LABEL_REF (Pmode
, end_label
), pc_rtx
);
10144 emit_jump_insn (gen_rtx_SET (pc_rtx
, x
));
10146 /* Wait for the right moment when the accessed 32-bit location
10148 emit_insn (gen_rtx_SET (resv
,
10149 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
10151 mode
= SELECT_CC_MODE (NE
, resv
, val
);
10152 cc
= gen_rtx_REG (mode
, CC_REG
);
10153 emit_insn (gen_rtx_SET (cc
, gen_rtx_COMPARE (mode
, resv
, val
)));
10155 /* Set the new value of the 32 bit location, proper masked. */
10156 emit_insn (gen_rtx_SET (val
, resv
));
10158 /* Try again if location is unstable. Fall through if only
10159 scond op failed. */
10160 x
= gen_rtx_NE (VOIDmode
, cc
, const0_rtx
);
10161 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, x
,
10162 gen_rtx_LABEL_REF (Pmode
, loop_label
), pc_rtx
);
10163 emit_unlikely_jump (gen_rtx_SET (pc_rtx
, x
));
10165 emit_label (end_label
);
10168 /* End: proper return the result for the given mode. */
10169 emit_insn (gen_rtx_SET (res
,
10170 gen_rtx_AND (SImode
, res
, mask
)));
10172 emit_insn (gen_rtx_SET (res
,
10173 gen_rtx_LSHIFTRT (SImode
, res
, off
)));
10175 emit_move_insn (result
, gen_lowpart (GET_MODE (result
), res
));
10178 /* Helper function used by "atomic_compare_and_swap" expand
10182 arc_expand_compare_and_swap (rtx operands
[])
10184 rtx bval
, rval
, mem
, oldval
, newval
, is_weak
, mod_s
, mod_f
, x
;
10187 bval
= operands
[0];
10188 rval
= operands
[1];
10190 oldval
= operands
[3];
10191 newval
= operands
[4];
10192 is_weak
= operands
[5];
10193 mod_s
= operands
[6];
10194 mod_f
= operands
[7];
10195 mode
= GET_MODE (mem
);
10197 if (reg_overlap_mentioned_p (rval
, oldval
))
10198 oldval
= copy_to_reg (oldval
);
10200 if (mode
== SImode
)
10202 emit_insn (gen_atomic_compare_and_swapsi_1 (rval
, mem
, oldval
, newval
,
10203 is_weak
, mod_s
, mod_f
));
10204 x
= gen_rtx_REG (CC_Zmode
, CC_REG
);
10205 x
= gen_rtx_EQ (SImode
, x
, const0_rtx
);
10206 emit_insn (gen_rtx_SET (bval
, x
));
10210 arc_expand_compare_and_swap_qh (bval
, rval
, mem
, oldval
, newval
,
10211 is_weak
, mod_s
, mod_f
);
10215 /* Helper function used by the "atomic_compare_and_swapsi_1"
10219 arc_split_compare_and_swap (rtx operands
[])
10221 rtx rval
, mem
, oldval
, newval
;
10223 enum memmodel mod_s
, mod_f
;
10225 rtx label1
, label2
, x
, cond
;
10227 rval
= operands
[0];
10229 oldval
= operands
[2];
10230 newval
= operands
[3];
10231 is_weak
= (operands
[4] != const0_rtx
);
10232 mod_s
= (enum memmodel
) INTVAL (operands
[5]);
10233 mod_f
= (enum memmodel
) INTVAL (operands
[6]);
10234 mode
= GET_MODE (mem
);
10236 /* ARC atomic ops work only with 32-bit aligned memories. */
10237 gcc_assert (mode
== SImode
);
10239 arc_pre_atomic_barrier (mod_s
);
10244 label1
= gen_label_rtx ();
10245 emit_label (label1
);
10247 label2
= gen_label_rtx ();
10249 /* Load exclusive. */
10250 emit_insn (gen_arc_load_exclusivesi (rval
, mem
));
10252 /* Check if it is oldval. */
10253 mode
= SELECT_CC_MODE (NE
, rval
, oldval
);
10254 cond
= gen_rtx_REG (mode
, CC_REG
);
10255 emit_insn (gen_rtx_SET (cond
, gen_rtx_COMPARE (mode
, rval
, oldval
)));
10257 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
10258 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, x
,
10259 gen_rtx_LABEL_REF (Pmode
, label2
), pc_rtx
);
10260 emit_unlikely_jump (gen_rtx_SET (pc_rtx
, x
));
10262 /* Exclusively store new item. Store clobbers CC reg. */
10263 emit_insn (gen_arc_store_exclusivesi (mem
, newval
));
10267 /* Check the result of the store. */
10268 cond
= gen_rtx_REG (CC_Zmode
, CC_REG
);
10269 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
10270 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, x
,
10271 gen_rtx_LABEL_REF (Pmode
, label1
), pc_rtx
);
10272 emit_unlikely_jump (gen_rtx_SET (pc_rtx
, x
));
10275 if (mod_f
!= MEMMODEL_RELAXED
)
10276 emit_label (label2
);
10278 arc_post_atomic_barrier (mod_s
);
10280 if (mod_f
== MEMMODEL_RELAXED
)
10281 emit_label (label2
);
10284 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
10285 to perform. MEM is the memory on which to operate. VAL is the second
10286 operand of the binary operator. BEFORE and AFTER are optional locations to
10287 return the value of MEM either before of after the operation. MODEL_RTX
10288 is a CONST_INT containing the memory model to use. */
10291 arc_expand_atomic_op (enum rtx_code code
, rtx mem
, rtx val
,
10292 rtx orig_before
, rtx orig_after
, rtx model_rtx
)
10294 enum memmodel model
= (enum memmodel
) INTVAL (model_rtx
);
10295 machine_mode mode
= GET_MODE (mem
);
10296 rtx label
, x
, cond
;
10297 rtx before
= orig_before
, after
= orig_after
;
10299 /* ARC atomic ops work only with 32-bit aligned memories. */
10300 gcc_assert (mode
== SImode
);
10302 arc_pre_atomic_barrier (model
);
10304 label
= gen_label_rtx ();
10305 emit_label (label
);
10306 label
= gen_rtx_LABEL_REF (VOIDmode
, label
);
10308 if (before
== NULL_RTX
)
10309 before
= gen_reg_rtx (mode
);
10311 if (after
== NULL_RTX
)
10312 after
= gen_reg_rtx (mode
);
10314 /* Load exclusive. */
10315 emit_insn (gen_arc_load_exclusivesi (before
, mem
));
10320 x
= gen_rtx_AND (mode
, before
, val
);
10321 emit_insn (gen_rtx_SET (after
, x
));
10322 x
= gen_rtx_NOT (mode
, after
);
10323 emit_insn (gen_rtx_SET (after
, x
));
10327 if (CONST_INT_P (val
))
10329 val
= GEN_INT (-INTVAL (val
));
10335 x
= gen_rtx_fmt_ee (code
, mode
, before
, val
);
10336 emit_insn (gen_rtx_SET (after
, x
));
10340 /* Exclusively store new item. Store clobbers CC reg. */
10341 emit_insn (gen_arc_store_exclusivesi (mem
, after
));
10343 /* Check the result of the store. */
10344 cond
= gen_rtx_REG (CC_Zmode
, CC_REG
);
10345 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
10346 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, x
,
10348 emit_unlikely_jump (gen_rtx_SET (pc_rtx
, x
));
10350 arc_post_atomic_barrier (model
);
10353 /* Implement TARGET_NO_SPECULATION_IN_DELAY_SLOTS_P. */
10356 arc_no_speculation_in_delay_slots_p ()
10361 /* Return a parallel of registers to represent where to find the
10362 register pieces if required, otherwise NULL_RTX. */
10365 arc_dwarf_register_span (rtx rtl
)
10367 machine_mode mode
= GET_MODE (rtl
);
10371 if (GET_MODE_SIZE (mode
) != 8)
10374 p
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (2));
10375 regno
= REGNO (rtl
);
10376 XVECEXP (p
, 0, 0) = gen_rtx_REG (SImode
, regno
);
10377 XVECEXP (p
, 0, 1) = gen_rtx_REG (SImode
, regno
+ 1);
10382 /* Return true if OP is an acceptable memory operand for ARCompact
10383 16-bit load instructions of MODE.
10385 AV2SHORT: TRUE if address needs to fit into the new ARCv2 short
10386 non scaled instructions.
10388 SCALED: TRUE if address can be scaled. */
10391 compact_memory_operand_p (rtx op
, machine_mode mode
,
10392 bool av2short
, bool scaled
)
10394 rtx addr
, plus0
, plus1
;
10397 /* Eliminate non-memory operations. */
10398 if (GET_CODE (op
) != MEM
)
10401 /* .di instructions have no 16-bit form. */
10402 if (MEM_VOLATILE_P (op
) && !TARGET_VOLATILE_CACHE_SET
)
10405 if (mode
== VOIDmode
)
10406 mode
= GET_MODE (op
);
10408 size
= GET_MODE_SIZE (mode
);
10410 /* dword operations really put out 2 instructions, so eliminate
10412 if (size
> UNITS_PER_WORD
)
10415 /* Decode the address now. */
10416 addr
= XEXP (op
, 0);
10417 switch (GET_CODE (addr
))
10420 return (REGNO (addr
) >= FIRST_PSEUDO_REGISTER
10421 || COMPACT_GP_REG_P (REGNO (addr
))
10422 || (SP_REG_P (REGNO (addr
)) && (size
!= 2)));
10424 plus0
= XEXP (addr
, 0);
10425 plus1
= XEXP (addr
, 1);
10427 if ((GET_CODE (plus0
) == REG
)
10428 && ((REGNO (plus0
) >= FIRST_PSEUDO_REGISTER
)
10429 || COMPACT_GP_REG_P (REGNO (plus0
)))
10430 && ((GET_CODE (plus1
) == REG
)
10431 && ((REGNO (plus1
) >= FIRST_PSEUDO_REGISTER
)
10432 || COMPACT_GP_REG_P (REGNO (plus1
)))))
10437 if ((GET_CODE (plus0
) == REG
)
10438 && ((REGNO (plus0
) >= FIRST_PSEUDO_REGISTER
)
10439 || (COMPACT_GP_REG_P (REGNO (plus0
)) && !av2short
)
10440 || (IN_RANGE (REGNO (plus0
), 0, 31) && av2short
))
10441 && (GET_CODE (plus1
) == CONST_INT
))
10443 bool valid
= false;
10445 off
= INTVAL (plus1
);
10447 /* Negative offset is not supported in 16-bit load/store insns. */
10451 /* Only u5 immediates allowed in code density instructions. */
10459 /* This is an ldh_s.x instruction, check the u6
10461 if (COMPACT_GP_REG_P (REGNO (plus0
)))
10465 /* Only u5 immediates allowed in 32bit access code
10466 density instructions. */
10467 if (REGNO (plus0
) <= 31)
10468 return ((off
< 32) && (off
% 4 == 0));
10475 if (COMPACT_GP_REG_P (REGNO (plus0
)))
10486 /* The 6-bit constant get shifted to fit the real
10487 5-bits field. Check also for the alignment. */
10488 return ((off
< 64) && (off
% 2 == 0));
10490 return ((off
< 128) && (off
% 4 == 0));
10497 if (REG_P (plus0
) && CONST_INT_P (plus1
)
10498 && ((REGNO (plus0
) >= FIRST_PSEUDO_REGISTER
)
10499 || SP_REG_P (REGNO (plus0
)))
10502 off
= INTVAL (plus1
);
10503 return ((size
!= 2) && (off
>= 0 && off
< 128) && (off
% 4 == 0));
10506 if ((GET_CODE (plus0
) == MULT
)
10507 && (GET_CODE (XEXP (plus0
, 0)) == REG
)
10508 && ((REGNO (XEXP (plus0
, 0)) >= FIRST_PSEUDO_REGISTER
)
10509 || COMPACT_GP_REG_P (REGNO (XEXP (plus0
, 0))))
10510 && (GET_CODE (plus1
) == REG
)
10511 && ((REGNO (plus1
) >= FIRST_PSEUDO_REGISTER
)
10512 || COMPACT_GP_REG_P (REGNO (plus1
))))
10516 /* TODO: 'gp' and 'pcl' are to supported as base address operand
10517 for 16-bit load instructions. */
10522 /* Return the frame pointer value to be backed up in the setjmp buffer. */
10525 arc_builtin_setjmp_frame_value (void)
10527 /* We always want to preserve whatever value is currently in the frame
10528 pointer register. For frames that are using the frame pointer the new
10529 value of the frame pointer register will have already been computed
10530 (as part of the prologue). For frames that are not using the frame
10531 pointer it is important that we backup whatever value is in the frame
10532 pointer register, as earlier (more outer) frames may have placed a
10533 value into the frame pointer register. It might be tempting to try
10534 and use `frame_pointer_rtx` here, however, this is not what we want.
10535 For frames that are using the frame pointer this will give the
10536 correct value. However, for frames that are not using the frame
10537 pointer this will still give the value that _would_ have been the
10538 frame pointer value for this frame (if the use of the frame pointer
10539 had not been removed). We really do want the raw frame pointer
10541 return gen_raw_REG (Pmode
, FRAME_POINTER_REGNUM
);
10544 /* Return nonzero if a jli call should be generated for a call from
10545 the current function to DECL. */
10548 arc_is_jli_call_p (rtx pat
)
10551 tree decl
= SYMBOL_REF_DECL (pat
);
10553 /* If it is not a well defined public function then return false. */
10554 if (!decl
|| !SYMBOL_REF_FUNCTION_P (pat
) || !TREE_PUBLIC (decl
))
10557 attrs
= TYPE_ATTRIBUTES (TREE_TYPE (decl
));
10558 if (lookup_attribute ("jli_always", attrs
))
10561 if (lookup_attribute ("jli_fixed", attrs
))
10564 return TARGET_JLI_ALWAYS
;
10567 /* Handle and "jli" attribute; arguments as in struct
10568 attribute_spec.handler. */
10571 arc_handle_jli_attribute (tree
*node ATTRIBUTE_UNUSED
,
10572 tree name
, tree args
, int,
10573 bool *no_add_attrs
)
10577 warning (OPT_Wattributes
,
10578 "%qE attribute only valid for ARCv2 architecture",
10580 *no_add_attrs
= true;
10583 if (args
== NULL_TREE
)
10585 warning (OPT_Wattributes
,
10586 "argument of %qE attribute is missing",
10588 *no_add_attrs
= true;
10592 if (TREE_CODE (TREE_VALUE (args
)) == NON_LVALUE_EXPR
)
10593 TREE_VALUE (args
) = TREE_OPERAND (TREE_VALUE (args
), 0);
10594 tree arg
= TREE_VALUE (args
);
10595 if (TREE_CODE (arg
) != INTEGER_CST
)
10597 warning (0, "%qE attribute allows only an integer constant argument",
10599 *no_add_attrs
= true;
10601 /* FIXME! add range check. TREE_INT_CST_LOW (arg) */
10606 /* Handle and "scure" attribute; arguments as in struct
10607 attribute_spec.handler. */
10610 arc_handle_secure_attribute (tree
*node ATTRIBUTE_UNUSED
,
10611 tree name
, tree args
, int,
10612 bool *no_add_attrs
)
10616 warning (OPT_Wattributes
,
10617 "%qE attribute only valid for ARC EM architecture",
10619 *no_add_attrs
= true;
10622 if (args
== NULL_TREE
)
10624 warning (OPT_Wattributes
,
10625 "argument of %qE attribute is missing",
10627 *no_add_attrs
= true;
10631 if (TREE_CODE (TREE_VALUE (args
)) == NON_LVALUE_EXPR
)
10632 TREE_VALUE (args
) = TREE_OPERAND (TREE_VALUE (args
), 0);
10633 tree arg
= TREE_VALUE (args
);
10634 if (TREE_CODE (arg
) != INTEGER_CST
)
10636 warning (0, "%qE attribute allows only an integer constant argument",
10638 *no_add_attrs
= true;
10644 /* Return nonzero if the symbol is a secure function. */
10647 arc_is_secure_call_p (rtx pat
)
10650 tree decl
= SYMBOL_REF_DECL (pat
);
10655 attrs
= TYPE_ATTRIBUTES (TREE_TYPE (decl
));
10656 if (lookup_attribute ("secure_call", attrs
))
10662 /* Handle "uncached" qualifier. */
10665 arc_handle_uncached_attribute (tree
*node
,
10666 tree name
, tree args
,
10667 int flags ATTRIBUTE_UNUSED
,
10668 bool *no_add_attrs
)
10670 if (DECL_P (*node
) && TREE_CODE (*node
) != TYPE_DECL
)
10672 error ("%qE attribute only applies to types",
10674 *no_add_attrs
= true;
10678 warning (OPT_Wattributes
, "argument of %qE attribute ignored", name
);
10683 /* Return TRUE if PAT is a memory addressing an uncached data. */
10686 arc_is_uncached_mem_p (rtx pat
)
10690 struct mem_attrs
*refattrs
;
10695 /* Get the memory attributes. */
10696 refattrs
= MEM_ATTRS (pat
);
10698 || !refattrs
->expr
)
10701 /* Get the type declaration. */
10702 ttype
= TREE_TYPE (refattrs
->expr
);
10706 /* Get the type attributes. */
10707 attrs
= TYPE_ATTRIBUTES (ttype
);
10708 if (lookup_attribute ("uncached", attrs
))
10713 /* Handle aux attribute. The auxiliary registers are addressed using
10714 special instructions lr and sr. The attribute 'aux' indicates if a
10715 variable refers to the aux-regs and what is the register number
10719 arc_handle_aux_attribute (tree
*node
,
10720 tree name
, tree args
, int,
10721 bool *no_add_attrs
)
10723 /* Isn't it better to use address spaces for the aux-regs? */
10724 if (DECL_P (*node
))
10726 if (TREE_CODE (*node
) != VAR_DECL
)
10728 error ("%qE attribute only applies to variables", name
);
10729 *no_add_attrs
= true;
10733 if (TREE_CODE (TREE_VALUE (args
)) == NON_LVALUE_EXPR
)
10734 TREE_VALUE (args
) = TREE_OPERAND (TREE_VALUE (args
), 0);
10735 tree arg
= TREE_VALUE (args
);
10736 if (TREE_CODE (arg
) != INTEGER_CST
)
10738 warning (OPT_Wattributes
, "%qE attribute allows only an integer "
10739 "constant argument", name
);
10740 *no_add_attrs
= true;
10742 /* FIXME! add range check. TREE_INT_CST_LOW (arg) */
10745 if (TREE_CODE (*node
) == VAR_DECL
)
10747 tree fntype
= TREE_TYPE (*node
);
10748 if (fntype
&& TREE_CODE (fntype
) == POINTER_TYPE
)
10750 tree attrs
= tree_cons (get_identifier ("aux"), NULL_TREE
,
10751 TYPE_ATTRIBUTES (fntype
));
10752 TYPE_ATTRIBUTES (fntype
) = attrs
;
10759 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
10760 anchors for small data: the GP register acts as an anchor in that
10761 case. We also don't want to use them for PC-relative accesses,
10762 where the PC acts as an anchor. Prohibit also TLS symbols to use
10766 arc_use_anchors_for_symbol_p (const_rtx symbol
)
10768 if (SYMBOL_REF_TLS_MODEL (symbol
))
10774 if (SYMBOL_REF_SMALL_P (symbol
))
10777 return default_use_anchors_for_symbol_p (symbol
);
10780 /* Return true if SUBST can't safely replace its equivalent during RA. */
10782 arc_cannot_substitute_mem_equiv_p (rtx
)
10784 /* If SUBST is mem[base+index], the address may not fit ISA,
10785 thus return true. */
10789 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
10790 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P arc_use_anchors_for_symbol_p
10792 #undef TARGET_CONSTANT_ALIGNMENT
10793 #define TARGET_CONSTANT_ALIGNMENT constant_alignment_word_strings
10795 #undef TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV_P
10796 #define TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV_P arc_cannot_substitute_mem_equiv_p
10798 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
10799 #define TARGET_ASM_TRAMPOLINE_TEMPLATE arc_asm_trampoline_template
10801 struct gcc_target targetm
= TARGET_INITIALIZER
;
10803 #include "gt-arc.h"