1 ; Options for the Synopsys DesignWare ARC port of the compiler
3 ; Copyright (C) 2005-2023 Free Software Foundation, Inc.
5 ; This file is part of GCC.
7 ; GCC is free software; you can redistribute it and/or modify it under
8 ; the terms of the GNU General Public License as published by the Free
9 ; Software Foundation; either version 3, or (at your option) any later
12 ; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ; License for more details.
17 ; You should have received a copy of the GNU General Public License
18 ; along with GCC; see the file COPYING3. If not see
19 ; <http://www.gnu.org/licenses/>.
25 Target RejectNegative Mask(BIG_ENDIAN)
26 Compile code for big endian mode.
29 Target RejectNegative InverseMask(BIG_ENDIAN)
30 Compile code for little endian mode. This is the default.
33 Target RejectNegative Mask(NO_COND_EXEC)
34 Disable ARCompact specific pass to generate conditional execution instructions.
38 Generate ARCompact 32-bit code for ARC600 processor.
46 Generate ARCompact 32-bit code for ARC601 processor.
50 Generate ARCompact 32-bit code for ARC700 processor.
57 Target Mask(JLI_ALWAYS)
58 Force all calls to be made via a jli instruction.
61 Target RejectNegative Joined Enum(arc_mpy) Var(arc_mpy_option) Init(DEFAULT_arc_mpy_option)
62 -mmpy-option=MPY Compile ARCv2 code with a multiplier design option.
65 Name(arc_mpy) Type(int)
68 Enum(arc_mpy) String(0) Value(0)
71 Enum(arc_mpy) String(none) Value(0) Canonical
74 Enum(arc_mpy) String(1) Value(1)
77 Enum(arc_mpy) String(w) Value(1) Canonical
80 Enum(arc_mpy) String(2) Value(2)
83 Enum(arc_mpy) String(mpy) Value(2)
86 Enum(arc_mpy) String(wlh1) Value(2) Canonical
89 Enum(arc_mpy) String(3) Value(3)
92 Enum(arc_mpy) String(wlh2) Value(3) Canonical
95 Enum(arc_mpy) String(4) Value(4)
98 Enum(arc_mpy) String(wlh3) Value(4) Canonical
101 Enum(arc_mpy) String(5) Value(5)
104 Enum(arc_mpy) String(wlh4) Value(5) Canonical
107 Enum(arc_mpy) String(6) Value(6)
110 Enum(arc_mpy) String(wlh5) Value(6) Canonical
113 Enum(arc_mpy) String(7) Value(7)
116 Enum(arc_mpy) String(plus_dmpy) Value(7) Canonical
119 Enum(arc_mpy) String(8) Value(8)
122 Enum(arc_mpy) String(plus_macd) Value(8) Canonical
125 Enum(arc_mpy) String(9) Value(9)
128 Enum(arc_mpy) String(plus_qmacw) Value(9) Canonical
132 Enable DIV-REM instructions for ARCv2.
135 Target Mask(CODE_DENSITY)
136 Enable code density instructions for ARCv2.
140 Does nothing. Preserved for backward compatibility.
142 ; We use an explict definition for the negative form because that is the
143 ; actually interesting option, and we want that to have its own comment.
145 Target RejectNegative Mask(VOLATILE_CACHE_SET)
146 Use ordinarily cached memory accesses for volatile references.
149 Target RejectNegative InverseMask(VOLATILE_CACHE_SET)
150 Enable cache bypass for volatile references.
153 Target Mask(BARREL_SHIFTER)
154 Generate instructions supported by barrel shifter.
157 Target Mask(NORM_SET)
158 Generate norm instruction.
161 Target Mask(SWAP_SET)
162 Generate swap instruction.
165 Target Mask(MUL64_SET)
166 Generate mul64 and mulu64 instructions.
169 Target Mask(NOMPY_SET) Warn(%qs is deprecated)
170 Do not generate mpy instructions for ARC700.
174 Generate extended arithmetic instructions, only valid for ARC700.
178 Dummy flag. This is the default unless FPX switches are provided explicitly.
181 Target Mask(LONG_CALLS_SET)
182 Generate call insns as register indirect calls.
185 Target Mask(NO_BRCC_SET)
186 Do no generate BRcc instructions in arc_reorg.
189 Target InverseMask(NO_SDATA_SET)
190 Generate sdata references. This is the default, unless you compile for PIC.
193 Target Mask(MILLICODE_THUNK_SET)
194 Generate millicode thunks.
197 Target Mask(SPFP_COMPACT_SET)
198 FPX: Generate Single Precision FPX (compact) instructions.
201 Target Mask(SPFP_COMPACT_SET) MaskExists
202 FPX: Generate Single Precision FPX (compact) instructions.
205 Target Mask(SPFP_FAST_SET)
206 FPX: Generate Single Precision FPX (fast) instructions.
209 Target Mask(ARGONAUT_SET)
210 FPX: Enable Argonaut ARC CPU Double Precision Floating Point extensions.
213 Target Mask(DPFP_COMPACT_SET)
214 FPX: Generate Double Precision FPX (compact) instructions.
217 Target Mask(DPFP_COMPACT_SET) MaskExists
218 FPX: Generate Double Precision FPX (compact) instructions.
221 Target Mask(DPFP_FAST_SET)
222 FPX: Generate Double Precision FPX (fast) instructions.
225 Target Mask(DPFP_DISABLE_LRSR)
226 Disable LR and SR instructions from using FPX extension aux registers.
229 Target Mask(SIMD_SET)
230 Enable generation of ARC SIMD instructions via target-specific builtins.
233 Target RejectNegative Joined Var(arc_cpu) Enum(processor_type) Init(PROCESSOR_NONE)
234 -mcpu=CPU Compile code for ARC variant CPU.
237 Target RejectNegative Joined UInteger Var(arc_size_opt_level) Init(-1)
238 Size optimization level: 0:none 1:opportunistic 2: regalloc 3:drop align, -Os.
241 Target PchIgnore Var(TARGET_DUMPISIZE)
242 Annotate assembler instructions with estimated addresses.
245 Target RejectNegative Joined UInteger Var(arc_multcost) Init(-1)
246 Cost to assume for a multiply instruction, with 4 being equal to a normal insn.
249 Target RejectNegative ToLower Joined Var(arc_tune) Enum(arc_tune_attr) Init(ARC_TUNE_NONE)
250 -mtune=TUNE Tune code for given ARC variant.
253 Name(arc_tune_attr) Type(int)
256 Enum(arc_tune_attr) String(arc600) Value(ARC_TUNE_ARC600)
259 Enum(arc_tune_attr) String(arc601) Value(ARC_TUNE_ARC600)
262 Enum(arc_tune_attr) String(arc7xx) Value(ARC_TUNE_ARC7XX)
265 Enum(arc_tune_attr) String(arc700) Value(ARC_TUNE_ARC700_4_2_STD)
268 Enum(arc_tune_attr) String(arc700-xmac) Value(ARC_TUNE_ARC700_4_2_XMAC)
271 Enum(arc_tune_attr) String(arc725d) Value(ARC_TUNE_ARC700_4_2_XMAC)
274 Enum(arc_tune_attr) String(arc750d) Value(ARC_TUNE_ARC700_4_2_XMAC)
277 Enum(arc_tune_attr) String(core3) Value(ARC_TUNE_CORE_3)
280 Enum(arc_tune_attr) String(release31a) Value(ARC_TUNE_ARCHS4X_REL31A)
283 Target Var(TARGET_INDEXED_LOADS) Init(TARGET_INDEXED_LOADS_DEFAULT)
284 Enable the use of indexed loads.
287 Target Var(TARGET_AUTO_MODIFY_REG) Init(TARGET_AUTO_MODIFY_REG_DEFAULT)
288 Enable the use of pre/post modify with register displacement.
291 Target Mask(MULMAC_32BY16_SET)
292 Generate 32x16 multiply and mac instructions.
294 munalign-prob-threshold=
296 Does nothing. Preserved for backward compatibility.
299 Target Var(TARGET_MEDIUM_CALLS) Init(TARGET_MMEDIUM_CALLS_DEFAULT)
300 Don't use less than 25 bit addressing range for calls.
303 Target Var(TARGET_ANNOTATE_ALIGN)
304 Explain what alignment considerations lead to the decision to make an insn short or long.
308 Does nothing. Preserved for backward compatibility.
312 Does nothing. Preserved for backward compatibility.
317 Does nothing. Preserved for backward compatibility.
321 Target Var(TARGET_EARLY_CBRANCHSI)
322 Enable pre-reload use of cbranchsi pattern.
325 Target Var(TARGET_BBIT_PEEPHOLE)
326 Enable bbit peephole2.
329 Target Var(TARGET_CASE_VECTOR_PC_RELATIVE)
330 Use pc-relative switch case tables - this enables case table shortening.
333 Target Warn(%qs is deprecated)
334 Enable compact casesi pattern.
337 Target Warn(%qs is deprecated)
338 Enable 'q' instruction alternatives.
341 Target Warn(%qs is deprecated)
342 Expand adddi3 and subdi3 at rtl generation time into add.f / adc etc.
345 ; Flags used by the assembler, but for which we define preprocessor
346 ; macro symbols as well.
348 Target Warn(%qs is deprecated)
349 Enable variable polynomial CRC extension.
352 Target Warn(%qs is deprecated)
353 Enable DSP 3.1 Pack A extensions.
356 Target Warn(%qs is deprecated)
357 Enable dual viterbi butterfly extension.
360 Target Undocumented Warn(%qs is deprecated)
363 Target Undocumented Warn(%qs is deprecated)
366 Target RejectNegative Warn(%qs is deprecated)
367 Enable Dual and Single Operand Instructions for Telephony.
371 Enable XY Memory extension (DSP version 3).
373 ; ARC700 4.10 extension instructions
376 Enable Locked Load/Store Conditional extension.
380 Enable swap byte ordering extension instruction.
383 Target Warn(%qs is deprecated)
384 Enable 64-bit Time-Stamp Counter extension instruction.
388 Pass -EB option through to linker.
392 Pass -EL option through to linker.
396 Pass -marclinux option through to linker.
400 Pass -marclinux_prof option through to linker.
402 ;; lra is still unproven for ARC, so allow to fall back to reload with -mno-lra.
404 Target Var(arc_lra_flag) Init(1) Save
405 Use LRA instead of reload.
408 Target RejectNegative Var(arc_lra_priority_tag, ARC_LRA_PRIORITY_NONE)
409 Don't indicate any priority with TARGET_REGISTER_PRIORITY.
411 mlra-priority-compact
412 Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_COMPACT)
413 Indicate priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY.
415 mlra-priority-noncompact
416 Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_NONCOMPACT)
417 Reduce priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY.
419 ; backward-compatibility aliases, translated by DRIVER_SELF_SPECS
425 Target RejectNegative Joined
429 Enable atomic instructions.
433 Enable double load/store instructions for ARC HS.
436 Target RejectNegative Joined Enum(arc_fpu) Var(arc_fpu_build) Init(DEFAULT_arc_fpu_build)
437 Specify the name of the target floating point configuration.
440 Name(arc_fpu) Type(int)
443 Enum(arc_fpu) String(fpus) Value(FPU_FPUS)
446 Enum(arc_fpu) String(fpud) Value(FPU_FPUD)
449 Enum(arc_fpu) String(fpuda) Value(FPU_FPUDA)
452 Enum(arc_fpu) String(fpuda_div) Value(FPU_FPUDA_DIV)
455 Enum(arc_fpu) String(fpuda_fma) Value(FPU_FPUDA_FMA)
458 Enum(arc_fpu) String(fpuda_all) Value(FPU_FPUDA_ALL)
461 Enum(arc_fpu) String(fpus_div) Value(FPU_FPUS_DIV)
464 Enum(arc_fpu) String(fpud_div) Value(FPU_FPUD_DIV)
467 Enum(arc_fpu) String(fpus_fma) Value(FPU_FPUS_FMA)
470 Enum(arc_fpu) String(fpud_fma) Value(FPU_FPUD_FMA)
473 Enum(arc_fpu) String(fpus_all) Value(FPU_FPUS_ALL)
476 Enum(arc_fpu) String(fpud_all) Value(FPU_FPUD_ALL)
479 Target RejectNegative Joined UInteger Var(arc_tp_regno) Init(TARGET_ARC_TP_REGNO_DEFAULT)
480 Specify thread pointer register number.
483 Target RejectNegative Var(arc_tp_regno,-1)
486 Target Var(TARGET_NPS_BITOPS) Init(TARGET_NPS_BITOPS_DEFAULT)
487 Enable use of NPS400 bit operations.
490 Target Var(TARGET_NPS_CMEM) Init(TARGET_NPS_CMEM_DEFAULT)
491 Enable use of NPS400 xld/xst extension.
494 Target Var(unaligned_access) Init(UNALIGNED_ACCESS_DEFAULT)
495 Enable unaligned word and halfword accesses to packed data.
498 Target RejectNegative Joined Var(arc_deferred_options) Defer
499 Specifies the registers that the processor saves on an interrupt entry and exit.
502 Target RejectNegative Joined Var(arc_deferred_options) Defer
503 Specifies the number of registers replicated in second register bank on entry to fast interrupt.
506 Target RejectNegative Joined Enum(arc_lpc) Var(arc_lpcwidth) Init(32)
507 Sets LP_COUNT register width. Possible values are 8, 16, 20, 24, 28, and 32.
510 Name(arc_lpc) Type(int)
513 Enum(arc_lpc) String(8) Value(8)
516 Enum(arc_lpc) String(16) Value(16)
519 Enum(arc_lpc) String(20) Value(20)
522 Enum(arc_lpc) String(24) Value(24)
525 Enum(arc_lpc) String(28) Value(28)
528 Enum(arc_lpc) String(32) Value(32)
532 Enable 16-entry register file.
535 Target Var(TARGET_BRANCH_INDEX) Init(DEFAULT_BRANCH_INDEX)
536 Enable use of BI/BIH instructions when available.
539 Target Var(TARGET_CODE_DENSITY_FRAME) Init(TARGET_CODE_DENSITY_FRAME_DEFAULT)
540 Enable ENTER_S and LEAVE_S opcodes for ARCv2.