gcc/config/arc/arc.opt

   1 ; Options for the Synopsys DesignWare ARC port of the compiler
   2 ;
   3 ; Copyright (C) 2005-2022 Free Software Foundation, Inc.
   4 ;
   5 ; This file is part of GCC.
   6 ;
   7 ; GCC is free software; you can redistribute it and/or modify it under
   8 ; the terms of the GNU General Public License as published by the Free
   9 ; Software Foundation; either version 3, or (at your option) any later
  10 ; version.
  11 ;
  12 ; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ; License for more details.
  16 ;
  17 ; You should have received a copy of the GNU General Public License
  18 ; along with GCC; see the file COPYING3.  If not see
  19 ; <http://www.gnu.org/licenses/>.
  20
  21 HeaderInclude
  22 config/arc/arc-opts.h
  23
  24 mbig-endian
  25 Target RejectNegative Mask(BIG_ENDIAN)
  26 Compile code for big endian mode.
  27
  28 mlittle-endian
  29 Target RejectNegative InverseMask(BIG_ENDIAN)
  30 Compile code for little endian mode.  This is the default.
  31
  32 mno-cond-exec
  33 Target RejectNegative Mask(NO_COND_EXEC)
  34 Disable ARCompact specific pass to generate conditional execution instructions.
  35
  36 mA6
  37 Target
  38 Generate ARCompact 32-bit code for ARC600 processor.
  39
  40 mARC600
  41 Target
  42 Same as -mA6.
  43
  44 mARC601
  45 Target
  46 Generate ARCompact 32-bit code for ARC601 processor.
  47
  48 mA7
  49 Target
  50 Generate ARCompact 32-bit code for ARC700 processor.
  51
  52 mARC700
  53 Target
  54 Same as -mA7.
  55
  56 mjli-always
  57 Target Mask(JLI_ALWAYS)
  58 Force all calls to be made via a jli instruction.
  59
  60 mmpy-option=
  61 Target RejectNegative Joined Enum(arc_mpy) Var(arc_mpy_option) Init(DEFAULT_arc_mpy_option)
  62 -mmpy-option=MPY        Compile ARCv2 code with a multiplier design option.
  63
  64 Enum
  65 Name(arc_mpy) Type(int)
  66
  67 EnumValue
  68 Enum(arc_mpy) String(0) Value(0)
  69
  70 EnumValue
  71 Enum(arc_mpy) String(none) Value(0) Canonical
  72
  73 EnumValue
  74 Enum(arc_mpy) String(1) Value(1)
  75
  76 EnumValue
  77 Enum(arc_mpy) String(w) Value(1) Canonical
  78
  79 EnumValue
  80 Enum(arc_mpy) String(2) Value(2)
  81
  82 EnumValue
  83 Enum(arc_mpy) String(mpy) Value(2)
  84
  85 EnumValue
  86 Enum(arc_mpy) String(wlh1) Value(2) Canonical
  87
  88 EnumValue
  89 Enum(arc_mpy) String(3) Value(3)
  90
  91 EnumValue
  92 Enum(arc_mpy) String(wlh2) Value(3) Canonical
  93
  94 EnumValue
  95 Enum(arc_mpy) String(4) Value(4)
  96
  97 EnumValue
  98 Enum(arc_mpy) String(wlh3) Value(4) Canonical
  99
 100 EnumValue
 101 Enum(arc_mpy) String(5) Value(5)
 102
 103 EnumValue
 104 Enum(arc_mpy) String(wlh4) Value(5) Canonical
 105
 106 EnumValue
 107 Enum(arc_mpy) String(6) Value(6)
 108
 109 EnumValue
 110 Enum(arc_mpy) String(wlh5) Value(6) Canonical
 111
 112 EnumValue
 113 Enum(arc_mpy) String(7) Value(7)
 114
 115 EnumValue
 116 Enum(arc_mpy) String(plus_dmpy) Value(7) Canonical
 117
 118 EnumValue
 119 Enum(arc_mpy) String(8) Value(8)
 120
 121 EnumValue
 122 Enum(arc_mpy) String(plus_macd) Value(8) Canonical
 123
 124 EnumValue
 125 Enum(arc_mpy) String(9) Value(9)
 126
 127 EnumValue
 128 Enum(arc_mpy) String(plus_qmacw) Value(9) Canonical
 129
 130 mdiv-rem
 131 Target Mask(DIVREM)
 132 Enable DIV-REM instructions for ARCv2.
 133
 134 mcode-density
 135 Target Mask(CODE_DENSITY)
 136 Enable code density instructions for ARCv2.
 137
 138 mmixed-code
 139 Target Ignore
 140 Does nothing.  Preserved for backward compatibility.
 141
 142 ; We use an explict definition for the negative form because that is the
 143 ; actually interesting option, and we want that to have its own comment.
 144 mvolatile-cache
 145 Target RejectNegative Mask(VOLATILE_CACHE_SET)
 146 Use ordinarily cached memory accesses for volatile references.
 147
 148 mno-volatile-cache
 149 Target RejectNegative InverseMask(VOLATILE_CACHE_SET)
 150 Enable cache bypass for volatile references.
 151
 152 mbarrel-shifter
 153 Target Mask(BARREL_SHIFTER)
 154 Generate instructions supported by barrel shifter.
 155
 156 mnorm
 157 Target Mask(NORM_SET)
 158 Generate norm instruction.
 159
 160 mswap
 161 Target Mask(SWAP_SET)
 162 Generate swap instruction.
 163
 164 mmul64
 165 Target Mask(MUL64_SET)
 166 Generate mul64 and mulu64 instructions.
 167
 168 mno-mpy
 169 Target Mask(NOMPY_SET) Warn(%qs is deprecated)
 170 Do not generate mpy instructions for ARC700.
 171
 172 mea
 173 Target Mask(EA_SET)
 174 Generate extended arithmetic instructions, only valid for ARC700.
 175
 176 msoft-float
 177 Target Mask(0)
 178 Dummy flag. This is the default unless FPX switches are provided explicitly.
 179
 180 mlong-calls
 181 Target Mask(LONG_CALLS_SET)
 182 Generate call insns as register indirect calls.
 183
 184 mno-brcc
 185 Target Mask(NO_BRCC_SET)
 186 Do no generate BRcc instructions in arc_reorg.
 187
 188 msdata
 189 Target InverseMask(NO_SDATA_SET)
 190 Generate sdata references.  This is the default, unless you compile for PIC.
 191
 192 mmillicode
 193 Target Mask(MILLICODE_THUNK_SET)
 194 Generate millicode thunks.
 195
 196 mspfp
 197 Target Mask(SPFP_COMPACT_SET)
 198 FPX: Generate Single Precision FPX (compact) instructions.
 199
 200 mspfp-compact
 201 Target Mask(SPFP_COMPACT_SET) MaskExists
 202 FPX: Generate Single Precision FPX (compact) instructions.
 203
 204 mspfp-fast
 205 Target Mask(SPFP_FAST_SET)
 206 FPX: Generate Single Precision FPX (fast) instructions.
 207
 208 margonaut
 209 Target Mask(ARGONAUT_SET)
 210 FPX: Enable Argonaut ARC CPU Double Precision Floating Point extensions.
 211
 212 mdpfp
 213 Target Mask(DPFP_COMPACT_SET)
 214 FPX: Generate Double Precision FPX (compact) instructions.
 215
 216 mdpfp-compact
 217 Target Mask(DPFP_COMPACT_SET) MaskExists
 218 FPX: Generate Double Precision FPX (compact) instructions.
 219
 220 mdpfp-fast
 221 Target Mask(DPFP_FAST_SET)
 222 FPX: Generate Double Precision FPX (fast) instructions.
 223
 224 mno-dpfp-lrsr
 225 Target Mask(DPFP_DISABLE_LRSR)
 226 Disable LR and SR instructions from using FPX extension aux registers.
 227
 228 msimd
 229 Target Mask(SIMD_SET)
 230 Enable generation of ARC SIMD instructions via target-specific builtins.
 231
 232 mcpu=
 233 Target RejectNegative Joined Var(arc_cpu) Enum(processor_type) Init(PROCESSOR_NONE)
 234 -mcpu=CPU       Compile code for ARC variant CPU.
 235
 236 msize-level=
 237 Target RejectNegative Joined UInteger Var(arc_size_opt_level) Init(-1)
 238 Size optimization level: 0:none 1:opportunistic 2: regalloc 3:drop align, -Os.
 239
 240 misize
 241 Target PchIgnore Var(TARGET_DUMPISIZE)
 242 Annotate assembler instructions with estimated addresses.
 243
 244 mmultcost=
 245 Target RejectNegative Joined UInteger Var(arc_multcost) Init(-1)
 246 Cost to assume for a multiply instruction, with 4 being equal to a normal insn.
 247
 248 mtune=
 249 Target RejectNegative ToLower Joined Var(arc_tune) Enum(arc_tune_attr) Init(ARC_TUNE_NONE)
 250 -mtune=TUNE     Tune code for given ARC variant.
 251
 252 Enum
 253 Name(arc_tune_attr) Type(int)
 254
 255 EnumValue
 256 Enum(arc_tune_attr) String(arc600) Value(ARC_TUNE_ARC600)
 257
 258 EnumValue
 259 Enum(arc_tune_attr) String(arc601) Value(ARC_TUNE_ARC600)
 260
 261 EnumValue
 262 Enum(arc_tune_attr) String(arc7xx) Value(ARC_TUNE_ARC7XX)
 263
 264 EnumValue
 265 Enum(arc_tune_attr) String(arc700) Value(ARC_TUNE_ARC700_4_2_STD)
 266
 267 EnumValue
 268 Enum(arc_tune_attr) String(arc700-xmac) Value(ARC_TUNE_ARC700_4_2_XMAC)
 269
 270 EnumValue
 271 Enum(arc_tune_attr) String(arc725d) Value(ARC_TUNE_ARC700_4_2_XMAC)
 272
 273 EnumValue
 274 Enum(arc_tune_attr) String(arc750d) Value(ARC_TUNE_ARC700_4_2_XMAC)
 275
 276 EnumValue
 277 Enum(arc_tune_attr) String(core3) Value(ARC_TUNE_CORE_3)
 278
 279 mindexed-loads
 280 Target Var(TARGET_INDEXED_LOADS) Init(TARGET_INDEXED_LOADS_DEFAULT)
 281 Enable the use of indexed loads.
 282
 283 mauto-modify-reg
 284 Target Var(TARGET_AUTO_MODIFY_REG) Init(TARGET_AUTO_MODIFY_REG_DEFAULT)
 285 Enable the use of pre/post modify with register displacement.
 286
 287 mmul32x16
 288 Target Mask(MULMAC_32BY16_SET)
 289 Generate 32x16 multiply and mac instructions.
 290
 291 munalign-prob-threshold=
 292 Target Ignore
 293 Does nothing.  Preserved for backward compatibility.
 294
 295 mmedium-calls
 296 Target Var(TARGET_MEDIUM_CALLS) Init(TARGET_MMEDIUM_CALLS_DEFAULT)
 297 Don't use less than 25 bit addressing range for calls.
 298
 299 mannotate-align
 300 Target Var(TARGET_ANNOTATE_ALIGN)
 301 Explain what alignment considerations lead to the decision to make an insn short or long.
 302
 303 malign-call
 304 Target Ignore
 305 Does nothing.  Preserved for backward compatibility.
 306
 307 mRcq
 308 Target Var(TARGET_Rcq)
 309 Enable Rcq constraint handling - most short code generation depends on this.
 310
 311 mRcw
 312 Target Var(TARGET_Rcw)
 313 Enable Rcw constraint handling - ccfsm condexec mostly depends on this.
 314
 315 mearly-cbranchsi
 316 Target Var(TARGET_EARLY_CBRANCHSI)
 317 Enable pre-reload use of cbranchsi pattern.
 318
 319 mbbit-peephole
 320 Target Var(TARGET_BBIT_PEEPHOLE)
 321 Enable bbit peephole2.
 322
 323 mcase-vector-pcrel
 324 Target Var(TARGET_CASE_VECTOR_PC_RELATIVE)
 325 Use pc-relative switch case tables - this enables case table shortening.
 326
 327 mcompact-casesi
 328 Target Warn(%qs is deprecated)
 329 Enable compact casesi pattern.
 330
 331 mq-class
 332 Target Warn(%qs is deprecated)
 333 Enable 'q' instruction alternatives.
 334
 335 mexpand-adddi
 336 Target Warn(%qs is deprecated)
 337 Expand adddi3 and subdi3 at rtl generation time into add.f / adc etc.
 338
 339
 340 ; Flags used by the assembler, but for which we define preprocessor
 341 ; macro symbols as well.
 342 mcrc
 343 Target Warn(%qs is deprecated)
 344 Enable variable polynomial CRC extension.
 345
 346 mdsp-packa
 347 Target Warn(%qs is deprecated)
 348 Enable DSP 3.1 Pack A extensions.
 349
 350 mdvbf
 351 Target Warn(%qs is deprecated)
 352 Enable dual viterbi butterfly extension.
 353
 354 mmac-d16
 355 Target Undocumented Warn(%qs is deprecated)
 356
 357 mmac-24
 358 Target Undocumented Warn(%qs is deprecated)
 359
 360 mtelephony
 361 Target RejectNegative Warn(%qs is deprecated)
 362 Enable Dual and Single Operand Instructions for Telephony.
 363
 364 mxy
 365 Target
 366 Enable XY Memory extension (DSP version 3).
 367
 368 ; ARC700 4.10 extension instructions
 369 mlock
 370 Target
 371 Enable Locked Load/Store Conditional extension.
 372
 373 mswape
 374 Target
 375 Enable swap byte ordering extension instruction.
 376
 377 mrtsc
 378 Target Warn(%qs is deprecated)
 379 Enable 64-bit Time-Stamp Counter extension instruction.
 380
 381 EB
 382 Target
 383 Pass -EB option through to linker.
 384
 385 EL
 386 Target
 387 Pass -EL option through to linker.
 388
 389 marclinux
 390 Target
 391 Pass -marclinux option through to linker.
 392
 393 marclinux_prof
 394 Target
 395 Pass -marclinux_prof option through to linker.
 396
 397 ;; lra is still unproven for ARC, so allow to fall back to reload with -mno-lra.
 398 mlra
 399 Target Var(arc_lra_flag) Init(1) Save
 400 Use LRA instead of reload.
 401
 402 mlra-priority-none
 403 Target RejectNegative Var(arc_lra_priority_tag, ARC_LRA_PRIORITY_NONE)
 404 Don't indicate any priority with TARGET_REGISTER_PRIORITY.
 405
 406 mlra-priority-compact
 407 Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_COMPACT)
 408 Indicate priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY.
 409
 410 mlra-priority-noncompact
 411 Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_NONCOMPACT)
 412 Reduce priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY.
 413
 414 ; backward-compatibility aliases, translated by DRIVER_SELF_SPECS
 415
 416 mEA
 417 Target
 418
 419 multcost=
 420 Target RejectNegative Joined
 421
 422 matomic
 423 Target Mask(ATOMIC)
 424 Enable atomic instructions.
 425
 426 mll64
 427 Target Mask(LL64)
 428 Enable double load/store instructions for ARC HS.
 429
 430 mfpu=
 431 Target RejectNegative Joined Enum(arc_fpu) Var(arc_fpu_build) Init(DEFAULT_arc_fpu_build)
 432 Specify the name of the target floating point configuration.
 433
 434 Enum
 435 Name(arc_fpu) Type(int)
 436
 437 EnumValue
 438 Enum(arc_fpu) String(fpus) Value(FPU_FPUS)
 439
 440 EnumValue
 441 Enum(arc_fpu) String(fpud) Value(FPU_FPUD)
 442
 443 EnumValue
 444 Enum(arc_fpu) String(fpuda) Value(FPU_FPUDA)
 445
 446 EnumValue
 447 Enum(arc_fpu) String(fpuda_div) Value(FPU_FPUDA_DIV)
 448
 449 EnumValue
 450 Enum(arc_fpu) String(fpuda_fma) Value(FPU_FPUDA_FMA)
 451
 452 EnumValue
 453 Enum(arc_fpu) String(fpuda_all) Value(FPU_FPUDA_ALL)
 454
 455 EnumValue
 456 Enum(arc_fpu) String(fpus_div) Value(FPU_FPUS_DIV)
 457
 458 EnumValue
 459 Enum(arc_fpu) String(fpud_div) Value(FPU_FPUD_DIV)
 460
 461 EnumValue
 462 Enum(arc_fpu) String(fpus_fma) Value(FPU_FPUS_FMA)
 463
 464 EnumValue
 465 Enum(arc_fpu) String(fpud_fma) Value(FPU_FPUD_FMA)
 466
 467 EnumValue
 468 Enum(arc_fpu) String(fpus_all) Value(FPU_FPUS_ALL)
 469
 470 EnumValue
 471 Enum(arc_fpu) String(fpud_all) Value(FPU_FPUD_ALL)
 472
 473 mtp-regno=
 474 Target RejectNegative Joined UInteger Var(arc_tp_regno) Init(TARGET_ARC_TP_REGNO_DEFAULT)
 475 Specify thread pointer register number.
 476
 477 mtp-regno=none
 478 Target RejectNegative Var(arc_tp_regno,-1)
 479
 480 mbitops
 481 Target Var(TARGET_NPS_BITOPS) Init(TARGET_NPS_BITOPS_DEFAULT)
 482 Enable use of NPS400 bit operations.
 483
 484 mcmem
 485 Target Var(TARGET_NPS_CMEM) Init(TARGET_NPS_CMEM_DEFAULT)
 486 Enable use of NPS400 xld/xst extension.
 487
 488 munaligned-access
 489 Target Var(unaligned_access) Init(UNALIGNED_ACCESS_DEFAULT)
 490 Enable unaligned word and halfword accesses to packed data.
 491
 492 mirq-ctrl-saved=
 493 Target RejectNegative Joined Var(arc_deferred_options) Defer
 494 Specifies the registers that the processor saves on an interrupt entry and exit.
 495
 496 mrgf-banked-regs=
 497 Target RejectNegative Joined Var(arc_deferred_options) Defer
 498 Specifies the number of registers replicated in second register bank on entry to fast interrupt.
 499
 500 mlpc-width=
 501 Target RejectNegative Joined Enum(arc_lpc) Var(arc_lpcwidth) Init(32)
 502 Sets LP_COUNT register width.  Possible values are 8, 16, 20, 24, 28, and 32.
 503
 504 Enum
 505 Name(arc_lpc) Type(int)
 506
 507 EnumValue
 508 Enum(arc_lpc) String(8) Value(8)
 509
 510 EnumValue
 511 Enum(arc_lpc) String(16) Value(16)
 512
 513 EnumValue
 514 Enum(arc_lpc) String(20) Value(20)
 515
 516 EnumValue
 517 Enum(arc_lpc) String(24) Value(24)
 518
 519 EnumValue
 520 Enum(arc_lpc) String(28) Value(28)
 521
 522 EnumValue
 523 Enum(arc_lpc) String(32) Value(32)
 524
 525 mrf16
 526 Target Mask(RF16)
 527 Enable 16-entry register file.
 528
 529 mbranch-index
 530 Target Var(TARGET_BRANCH_INDEX) Init(DEFAULT_BRANCH_INDEX)
 531 Enable use of BI/BIH instructions when available.
 532
 533 mcode-density-frame
 534 Target Var(TARGET_CODE_DENSITY_FRAME) Init(TARGET_CODE_DENSITY_FRAME_DEFAULT)
 535 Enable ENTER_S and LEAVE_S opcodes for ARCv2.