gcc/config/arc/arc.opt

   1 ; Options for the Synopsys DesignWare ARC port of the compiler
   2 ;
   3 ; Copyright (C) 2005-2018 Free Software Foundation, Inc.
   4 ;
   5 ; This file is part of GCC.
   6 ;
   7 ; GCC is free software; you can redistribute it and/or modify it under
   8 ; the terms of the GNU General Public License as published by the Free
   9 ; Software Foundation; either version 3, or (at your option) any later
  10 ; version.
  11 ;
  12 ; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ; License for more details.
  16 ;
  17 ; You should have received a copy of the GNU General Public License
  18 ; along with GCC; see the file COPYING3.  If not see
  19 ; <http://www.gnu.org/licenses/>.
  20
  21 HeaderInclude
  22 config/arc/arc-opts.h
  23
  24 mbig-endian
  25 Target Report RejectNegative Mask(BIG_ENDIAN)
  26 Compile code for big endian mode.
  27
  28 mlittle-endian
  29 Target Report RejectNegative InverseMask(BIG_ENDIAN)
  30 Compile code for little endian mode.  This is the default.
  31
  32 mno-cond-exec
  33 Target Report RejectNegative Mask(NO_COND_EXEC)
  34 Disable ARCompact specific pass to generate conditional execution instructions.
  35
  36 mA6
  37 Target Report
  38 Generate ARCompact 32-bit code for ARC600 processor.
  39
  40 mARC600
  41 Target Report
  42 Same as -mA6.
  43
  44 mARC601
  45 Target Report
  46 Generate ARCompact 32-bit code for ARC601 processor.
  47
  48 mA7
  49 Target Report
  50 Generate ARCompact 32-bit code for ARC700 processor.
  51
  52 mARC700
  53 Target Report
  54 Same as -mA7.
  55
  56 mjli-always
  57 Target Report Mask(JLI_ALWAYS)
  58 Force all calls to be made via a jli instruction.
  59
  60 mmpy-option=
  61 Target RejectNegative Joined Enum(arc_mpy) Var(arc_mpy_option) Init(DEFAULT_arc_mpy_option)
  62 -mmpy-option=MPY Compile ARCv2 code with a multiplier design option.
  63
  64 Enum
  65 Name(arc_mpy) Type(int)
  66
  67 EnumValue
  68 Enum(arc_mpy) String(0) Value(0)
  69
  70 EnumValue
  71 Enum(arc_mpy) String(none) Value(0) Canonical
  72
  73 EnumValue
  74 Enum(arc_mpy) String(1) Value(1)
  75
  76 EnumValue
  77 Enum(arc_mpy) String(w) Value(1) Canonical
  78
  79 EnumValue
  80 Enum(arc_mpy) String(2) Value(2)
  81
  82 EnumValue
  83 Enum(arc_mpy) String(mpy) Value(2)
  84
  85 EnumValue
  86 Enum(arc_mpy) String(wlh1) Value(2) Canonical
  87
  88 EnumValue
  89 Enum(arc_mpy) String(3) Value(3)
  90
  91 EnumValue
  92 Enum(arc_mpy) String(wlh2) Value(3) Canonical
  93
  94 EnumValue
  95 Enum(arc_mpy) String(4) Value(4)
  96
  97 EnumValue
  98 Enum(arc_mpy) String(wlh3) Value(4) Canonical
  99
 100 EnumValue
 101 Enum(arc_mpy) String(5) Value(5)
 102
 103 EnumValue
 104 Enum(arc_mpy) String(wlh4) Value(5) Canonical
 105
 106 EnumValue
 107 Enum(arc_mpy) String(6) Value(6)
 108
 109 EnumValue
 110 Enum(arc_mpy) String(wlh5) Value(6) Canonical
 111
 112 EnumValue
 113 Enum(arc_mpy) String(7) Value(7)
 114
 115 EnumValue
 116 Enum(arc_mpy) String(plus_dmpy) Value(7) Canonical
 117
 118 EnumValue
 119 Enum(arc_mpy) String(8) Value(8)
 120
 121 EnumValue
 122 Enum(arc_mpy) String(plus_macd) Value(8) Canonical
 123
 124 EnumValue
 125 Enum(arc_mpy) String(9) Value(9)
 126
 127 EnumValue
 128 Enum(arc_mpy) String(plus_qmacw) Value(9) Canonical
 129
 130 mdiv-rem
 131 Target Report Mask(DIVREM)
 132 Enable DIV-REM instructions for ARCv2.
 133
 134 mcode-density
 135 Target Report Mask(CODE_DENSITY)
 136 Enable code density instructions for ARCv2.
 137
 138 mmixed-code
 139 Target Report Mask(MIXED_CODE_SET)
 140 Tweak register allocation to help 16-bit instruction generation.
 141 ; originally this was:
 142 ;Generate ARCompact 16-bit instructions intermixed with 32-bit instructions
 143 ; but we do that without -mmixed-code, too, it's just a different instruction
 144 ; count / size tradeoff.
 145
 146 ; We use an explict definition for the negative form because that is the
 147 ; actually interesting option, and we want that to have its own comment.
 148 mvolatile-cache
 149 Target Report RejectNegative Mask(VOLATILE_CACHE_SET)
 150 Use ordinarily cached memory accesses for volatile references.
 151
 152 mno-volatile-cache
 153 Target Report RejectNegative InverseMask(VOLATILE_CACHE_SET)
 154 Enable cache bypass for volatile references.
 155
 156 mbarrel-shifter
 157 Target Report Mask(BARREL_SHIFTER)
 158 Generate instructions supported by barrel shifter.
 159
 160 mnorm
 161 Target Report Mask(NORM_SET)
 162 Generate norm instruction.
 163
 164 mswap
 165 Target Report Mask(SWAP_SET)
 166 Generate swap instruction.
 167
 168 mmul64
 169 Target Report Mask(MUL64_SET)
 170 Generate mul64 and mulu64 instructions.
 171
 172 mno-mpy
 173 Target Report Mask(NOMPY_SET) Warn(%qs is deprecated)
 174 Do not generate mpy instructions for ARC700.
 175
 176 mea
 177 Target Report Mask(EA_SET)
 178 Generate Extended arithmetic instructions.  Currently only divaw, adds, subs and sat16 are supported.
 179
 180 msoft-float
 181 Target Report Mask(0)
 182 Dummy flag. This is the default unless FPX switches are provided explicitly.
 183
 184 mlong-calls
 185 Target Report Mask(LONG_CALLS_SET)
 186 Generate call insns as register indirect calls.
 187
 188 mno-brcc
 189 Target Report Mask(NO_BRCC_SET)
 190 Do no generate BRcc instructions in arc_reorg.
 191
 192 msdata
 193 Target Report InverseMask(NO_SDATA_SET)
 194 Generate sdata references.  This is the default, unless you compile for PIC.
 195
 196 mno-millicode
 197 Target Report Mask(NO_MILLICODE_THUNK_SET)
 198 Do not generate millicode thunks (needed only with -Os).
 199
 200 mspfp
 201 Target Report Mask(SPFP_COMPACT_SET)
 202 FPX: Generate Single Precision FPX (compact) instructions.
 203
 204 mspfp-compact
 205 Target Report Mask(SPFP_COMPACT_SET) MaskExists
 206 FPX: Generate Single Precision FPX (compact) instructions.
 207
 208 mspfp-fast
 209 Target Report Mask(SPFP_FAST_SET)
 210 FPX: Generate Single Precision FPX (fast) instructions.
 211
 212 margonaut
 213 Target Report Mask(ARGONAUT_SET)
 214 FPX: Enable Argonaut ARC CPU Double Precision Floating Point extensions.
 215
 216 mdpfp
 217 Target Report Mask(DPFP_COMPACT_SET)
 218 FPX: Generate Double Precision FPX (compact) instructions.
 219
 220 mdpfp-compact
 221 Target Report Mask(DPFP_COMPACT_SET) MaskExists
 222 FPX: Generate Double Precision FPX (compact) instructions.
 223
 224 mdpfp-fast
 225 Target Report Mask(DPFP_FAST_SET)
 226 FPX: Generate Double Precision FPX (fast) instructions.
 227
 228 mno-dpfp-lrsr
 229 Target Report Mask(DPFP_DISABLE_LRSR)
 230 Disable LR and SR instructions from using FPX extension aux registers.
 231
 232 msimd
 233 Target Report Mask(SIMD_SET)
 234 Enable generation of ARC SIMD instructions via target-specific builtins.
 235
 236 mcpu=
 237 Target RejectNegative Joined Var(arc_cpu) Enum(processor_type) Init(PROCESSOR_NONE)
 238 -mcpu=CPU       Compile code for ARC variant CPU.
 239
 240 msize-level=
 241 Target RejectNegative Joined UInteger Var(arc_size_opt_level) Init(-1)
 242 size optimization level: 0:none 1:opportunistic 2: regalloc 3:drop align, -Os.
 243
 244 misize
 245 Target Report PchIgnore Var(TARGET_DUMPISIZE)
 246 Annotate assembler instructions with estimated addresses.
 247
 248 mmultcost=
 249 Target RejectNegative Joined UInteger Var(arc_multcost) Init(-1)
 250 Cost to assume for a multiply instruction, with 4 being equal to a normal insn.
 251
 252 mtune=ARC600
 253 Target RejectNegative Var(arc_tune, TUNE_ARC600)
 254 Tune for ARC600 cpu.
 255
 256 mtune=ARC601
 257 Target RejectNegative Var(arc_tune, TUNE_ARC600)
 258 Tune for ARC601 cpu.
 259
 260 mtune=ARC700
 261 Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_STD)
 262 Tune for ARC700 R4.2 Cpu with standard multiplier block.
 263
 264 mtune=ARC700-xmac
 265 Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_XMAC)
 266 Tune for ARC700 R4.2 Cpu with XMAC block.
 267
 268 mtune=ARC725D
 269 Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_XMAC)
 270 Tune for ARC700 R4.2 Cpu with XMAC block.
 271
 272 mtune=ARC750D
 273 Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_XMAC)
 274 Tune for ARC700 R4.2 Cpu with XMAC block.
 275
 276 mindexed-loads
 277 Target Var(TARGET_INDEXED_LOADS) Init(TARGET_INDEXED_LOADS_DEFAULT)
 278 Enable the use of indexed loads.
 279
 280 mauto-modify-reg
 281 Target Var(TARGET_AUTO_MODIFY_REG) Init(TARGET_AUTO_MODIFY_REG_DEFAULT)
 282 Enable the use of pre/post modify with register displacement.
 283
 284 mmul32x16
 285 Target Report Mask(MULMAC_32BY16_SET)
 286 Generate 32x16 multiply and mac instructions.
 287
 288 ; the initializer is supposed to be: Init(REG_BR_PROB_BASE/2) ,
 289 ; alas, basic-block.h is not included in options.c .
 290 munalign-prob-threshold=
 291 Target RejectNegative Joined UInteger Var(arc_unalign_prob_threshold) Init(10000/2)
 292 Set probability threshold for unaligning branches.
 293
 294 mmedium-calls
 295 Target Var(TARGET_MEDIUM_CALLS) Init(TARGET_MMEDIUM_CALLS_DEFAULT)
 296 Don't use less than 25 bit addressing range for calls.
 297
 298 mannotate-align
 299 Target Var(TARGET_ANNOTATE_ALIGN)
 300 Explain what alignment considerations lead to the decision to make an insn short or long.
 301
 302 malign-call
 303 Target Var(TARGET_ALIGN_CALL)
 304 Do alignment optimizations for call instructions.
 305
 306 mRcq
 307 Target Var(TARGET_Rcq)
 308 Enable Rcq constraint handling - most short code generation depends on this.
 309
 310 mRcw
 311 Target Var(TARGET_Rcw)
 312 Enable Rcw constraint handling - ccfsm condexec mostly depends on this.
 313
 314 mearly-cbranchsi
 315 Target Var(TARGET_EARLY_CBRANCHSI)
 316 Enable pre-reload use of cbranchsi pattern.
 317
 318 mbbit-peephole
 319 Target Var(TARGET_BBIT_PEEPHOLE)
 320 Enable bbit peephole2.
 321
 322 mcase-vector-pcrel
 323 Target Var(TARGET_CASE_VECTOR_PC_RELATIVE)
 324 Use pc-relative switch case tables - this enables case table shortening.
 325
 326 mcompact-casesi
 327 Target Var(TARGET_COMPACT_CASESI)
 328 Enable compact casesi pattern.
 329
 330 mq-class
 331 Target Var(TARGET_Q_CLASS)
 332 Enable 'q' instruction alternatives.
 333
 334 mexpand-adddi
 335 Target Warn(%qs is deprecated)
 336 Expand adddi3 and subdi3 at rtl generation time into add.f / adc etc.
 337
 338
 339 ; Flags used by the assembler, but for which we define preprocessor
 340 ; macro symbols as well.
 341 mcrc
 342 Target Report Warn(%qs is deprecated)
 343 Enable variable polynomial CRC extension.
 344
 345 mdsp-packa
 346 Target Report Warn(%qs is deprecated)
 347 Enable DSP 3.1 Pack A extensions.
 348
 349 mdvbf
 350 Target Report Warn(%qs is deprecated)
 351 Enable dual viterbi butterfly extension.
 352
 353 mmac-d16
 354 Target Report Undocumented Warn(%qs is deprecated)
 355
 356 mmac-24
 357 Target Report Undocumented Warn(%qs is deprecated)
 358
 359 mtelephony
 360 Target Report RejectNegative Warn(%qs is deprecated)
 361 Enable Dual and Single Operand Instructions for Telephony.
 362
 363 mxy
 364 Target Report
 365 Enable XY Memory extension (DSP version 3).
 366
 367 ; ARC700 4.10 extension instructions
 368 mlock
 369 Target Report
 370 Enable Locked Load/Store Conditional extension.
 371
 372 mswape
 373 Target Report
 374 Enable swap byte ordering extension instruction.
 375
 376 mrtsc
 377 Target Report Warn(%qs is deprecated)
 378 Enable 64-bit Time-Stamp Counter extension instruction.
 379
 380 EB
 381 Target
 382 Pass -EB option through to linker.
 383
 384 EL
 385 Target
 386 Pass -EL option through to linker.
 387
 388 marclinux
 389 Target
 390 Pass -marclinux option through to linker.
 391
 392 marclinux_prof
 393 Target
 394 Pass -marclinux_prof option through to linker.
 395
 396 ;; lra is still unproven for ARC, so allow to fall back to reload with -mno-lra.
 397 ;Target InverseMask(NO_LRA)
 398 ; lra still won't allow to configure libgcc; see PR rtl-optimization/55464.
 399 ; so don't enable by default.
 400 mlra
 401 Target Mask(LRA)
 402 Enable lra.
 403
 404 mlra-priority-none
 405 Target RejectNegative Var(arc_lra_priority_tag, ARC_LRA_PRIORITY_NONE)
 406 Don't indicate any priority with TARGET_REGISTER_PRIORITY.
 407
 408 mlra-priority-compact
 409 Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_COMPACT)
 410 Indicate priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY.
 411
 412 mlra-priority-noncompact
 413 Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_NONCOMPACT)
 414 Reduce priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY.
 415
 416 ; backward-compatibility aliases, translated by DRIVER_SELF_SPECS
 417
 418 mEA
 419 Target
 420
 421 multcost=
 422 Target RejectNegative Joined
 423
 424 matomic
 425 Target Report Mask(ATOMIC)
 426 Enable atomic instructions.
 427
 428 mll64
 429 Target Report Mask(LL64)
 430 Enable double load/store instructions for ARC HS.
 431
 432 mfpu=
 433 Target RejectNegative Joined Enum(arc_fpu) Var(arc_fpu_build) Init(DEFAULT_arc_fpu_build)
 434 Specify the name of the target floating point configuration.
 435
 436 Enum
 437 Name(arc_fpu) Type(int)
 438
 439 EnumValue
 440 Enum(arc_fpu) String(fpus) Value(FPU_FPUS)
 441
 442 EnumValue
 443 Enum(arc_fpu) String(fpud) Value(FPU_FPUD)
 444
 445 EnumValue
 446 Enum(arc_fpu) String(fpuda) Value(FPU_FPUDA)
 447
 448 EnumValue
 449 Enum(arc_fpu) String(fpuda_div) Value(FPU_FPUDA_DIV)
 450
 451 EnumValue
 452 Enum(arc_fpu) String(fpuda_fma) Value(FPU_FPUDA_FMA)
 453
 454 EnumValue
 455 Enum(arc_fpu) String(fpuda_all) Value(FPU_FPUDA_ALL)
 456
 457 EnumValue
 458 Enum(arc_fpu) String(fpus_div) Value(FPU_FPUS_DIV)
 459
 460 EnumValue
 461 Enum(arc_fpu) String(fpud_div) Value(FPU_FPUD_DIV)
 462
 463 EnumValue
 464 Enum(arc_fpu) String(fpus_fma) Value(FPU_FPUS_FMA)
 465
 466 EnumValue
 467 Enum(arc_fpu) String(fpud_fma) Value(FPU_FPUD_FMA)
 468
 469 EnumValue
 470 Enum(arc_fpu) String(fpus_all) Value(FPU_FPUS_ALL)
 471
 472 EnumValue
 473 Enum(arc_fpu) String(fpud_all) Value(FPU_FPUD_ALL)
 474
 475 mtp-regno=
 476 Target RejectNegative Joined UInteger Var(arc_tp_regno) Init(TARGET_ARC_TP_REGNO_DEFAULT)
 477 Specify thread pointer register number.
 478
 479 mtp-regno=none
 480 Target RejectNegative Var(arc_tp_regno,-1)
 481
 482 mbitops
 483 Target Report Var(TARGET_NPS_BITOPS) Init(TARGET_NPS_BITOPS_DEFAULT)
 484 Enable use of NPS400 bit operations.
 485
 486 mcmem
 487 Target Report Var(TARGET_NPS_CMEM) Init(TARGET_NPS_CMEM_DEFAULT)
 488 Enable use of NPS400 xld/xst extension.
 489
 490 munaligned-access
 491 Target Report Var(unaligned_access) Init(UNALIGNED_ACCESS_DEFAULT)
 492 Enable unaligned word and halfword accesses to packed data.
 493
 494 mirq-ctrl-saved=
 495 Target RejectNegative Joined Var(arc_deferred_options) Defer
 496 Specifies the registers that the processor saves on an interrupt entry and exit.
 497
 498 mrgf-banked-regs=
 499 Target RejectNegative Joined Var(arc_deferred_options) Defer
 500 Specifies the number of registers replicated in second register bank on entry to fast interrupt.
 501
 502 mlpc-width=
 503 Target RejectNegative Joined Enum(arc_lpc) Var(arc_lpcwidth) Init(32)
 504 Sets LP_COUNT register width.  Possible values are 8, 16, 20, 24, 28, and 32.
 505
 506 Enum
 507 Name(arc_lpc) Type(int)
 508
 509 EnumValue
 510 Enum(arc_lpc) String(8) Value(8)
 511
 512 EnumValue
 513 Enum(arc_lpc) String(16) Value(16)
 514
 515 EnumValue
 516 Enum(arc_lpc) String(20) Value(20)
 517
 518 EnumValue
 519 Enum(arc_lpc) String(24) Value(24)
 520
 521 EnumValue
 522 Enum(arc_lpc) String(28) Value(28)
 523
 524 EnumValue
 525 Enum(arc_lpc) String(32) Value(32)
 526
 527 mrf16
 528 Target Report Mask(RF16)
 529 Enable 16-entry register file.