1 ; Options for the Synopsys DesignWare ARC port of the compiler
3 ; Copyright (C) 2005-2016 Free Software Foundation, Inc.
5 ; This file is part of GCC.
7 ; GCC is free software; you can redistribute it and/or modify it under
8 ; the terms of the GNU General Public License as published by the Free
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15 ; License for more details.
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18 ; along with GCC; see the file COPYING3. If not see
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25 Target Report RejectNegative Mask(BIG_ENDIAN)
26 Compile code for big endian mode.
29 Target Report RejectNegative InverseMask(BIG_ENDIAN)
30 Compile code for little endian mode. This is the default.
33 Target Report RejectNegative Mask(NO_COND_EXEC)
34 Disable ARCompact specific pass to generate conditional execution instructions.
38 Generate ARCompact 32-bit code for ARC600 processor.
46 Generate ARCompact 32-bit code for ARC601 processor.
50 Generate ARCompact 32-bit code for ARC700 processor.
57 Target RejectNegative Joined UInteger Var(arc_mpy_option) Init(2)
58 -mmpy-option={0,1,2,3,4,5,6,7,8,9} Compile ARCv2 code with a multiplier design option. Option 2 is default on.
61 Target Report Mask(DIVREM)
62 Enable DIV-REM instructions for ARCv2.
65 Target Report Mask(CODE_DENSITY)
66 Enable code density instructions for ARCv2.
69 Target Report Mask(MIXED_CODE_SET)
70 Tweak register allocation to help 16-bit instruction generation.
71 ; originally this was:
72 ;Generate ARCompact 16-bit instructions intermixed with 32-bit instructions
73 ; but we do that without -mmixed-code, too, it's just a different instruction
74 ; count / size tradeoff.
76 ; We use an explict definition for the negative form because that is the
77 ; actually interesting option, and we want that to have its own comment.
79 Target Report RejectNegative Mask(VOLATILE_CACHE_SET)
80 Use ordinarily cached memory accesses for volatile references.
83 Target Report RejectNegative InverseMask(VOLATILE_CACHE_SET)
84 Enable cache bypass for volatile references.
87 Target Report Mask(BARREL_SHIFTER)
88 Generate instructions supported by barrel shifter.
91 Target Report Mask(NORM_SET)
92 Generate norm instruction.
95 Target Report Mask(SWAP_SET)
96 Generate swap instruction.
99 Target Report Mask(MUL64_SET)
100 Generate mul64 and mulu64 instructions.
103 Target Report Mask(NOMPY_SET)
104 Do not generate mpy instructions for ARC700.
107 Target Report Mask(EA_SET)
108 Generate Extended arithmetic instructions. Currently only divaw, adds, subs and sat16 are supported.
111 Target Report Mask(0)
112 Dummy flag. This is the default unless FPX switches are provided explicitly.
115 Target Report Mask(LONG_CALLS_SET)
116 Generate call insns as register indirect calls.
119 Target Report Mask(NO_BRCC_SET)
120 Do no generate BRcc instructions in arc_reorg.
123 Target Report InverseMask(NO_SDATA_SET)
124 Generate sdata references. This is the default, unless you compile for PIC.
127 Target Report Mask(NO_MILLICODE_THUNK_SET)
128 Do not generate millicode thunks (needed only with -Os).
131 Target Report Mask(SPFP_COMPACT_SET)
132 FPX: Generate Single Precision FPX (compact) instructions.
135 Target Report Mask(SPFP_COMPACT_SET) MaskExists
136 FPX: Generate Single Precision FPX (compact) instructions.
139 Target Report Mask(SPFP_FAST_SET)
140 FPX: Generate Single Precision FPX (fast) instructions.
143 Target Report Mask(ARGONAUT_SET)
144 FPX: Enable Argonaut ARC CPU Double Precision Floating Point extensions.
147 Target Report Mask(DPFP_COMPACT_SET)
148 FPX: Generate Double Precision FPX (compact) instructions.
151 Target Report Mask(DPFP_COMPACT_SET) MaskExists
152 FPX: Generate Double Precision FPX (compact) instructions.
155 Target Report Mask(DPFP_FAST_SET)
156 FPX: Generate Double Precision FPX (fast) instructions.
159 Target Report Mask(DPFP_DISABLE_LRSR)
160 Disable LR and SR instructions from using FPX extension aux registers.
163 Target Report Mask(SIMD_SET)
164 Enable generation of ARC SIMD instructions via target-specific builtins.
167 Target RejectNegative Joined Var(arc_cpu) Enum(processor_type) Init(PROCESSOR_NONE)
168 -mcpu=CPU Compile code for ARC variant CPU.
171 Name(processor_type) Type(enum processor_type)
174 Enum(processor_type) String(ARC600) Value(PROCESSOR_ARC600)
177 Enum(processor_type) String(arc600) Value(PROCESSOR_ARC600)
180 Enum(processor_type) String(ARC601) Value(PROCESSOR_ARC601)
183 Enum(processor_type) String(arc601) Value(PROCESSOR_ARC601)
186 Enum(processor_type) String(ARC700) Value(PROCESSOR_ARC700)
189 Enum(processor_type) String(arc700) Value(PROCESSOR_ARC700)
192 Enum(processor_type) String(nps400) Value(PROCESSOR_NPS400)
195 Enum(processor_type) String(NPS400) Value(PROCESSOR_NPS400)
198 Enum(processor_type) String(ARCEM) Value(PROCESSOR_ARCEM)
201 Enum(processor_type) String(arcem) Value(PROCESSOR_ARCEM)
204 Enum(processor_type) String(ARCHS) Value(PROCESSOR_ARCHS)
207 Enum(processor_type) String(archs) Value(PROCESSOR_ARCHS)
210 Target RejectNegative Joined UInteger Var(arc_size_opt_level) Init(-1)
211 size optimization level: 0:none 1:opportunistic 2: regalloc 3:drop align, -Os.
214 Target Report PchIgnore Var(TARGET_DUMPISIZE)
215 Annotate assembler instructions with estimated addresses.
218 Target RejectNegative Joined UInteger Var(arc_multcost) Init(-1)
219 Cost to assume for a multiply instruction, with 4 being equal to a normal insn.
222 Target RejectNegative Var(arc_tune, TUNE_ARC600)
226 Target RejectNegative Var(arc_tune, TUNE_ARC600)
230 Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_STD)
231 Tune for ARC700 R4.2 Cpu with standard multiplier block.
234 Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_XMAC)
235 Tune for ARC700 R4.2 Cpu with XMAC block.
238 Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_XMAC)
239 Tune for ARC700 R4.2 Cpu with XMAC block.
242 Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_XMAC)
243 Tune for ARC700 R4.2 Cpu with XMAC block.
246 Target Var(TARGET_INDEXED_LOADS)
247 Enable the use of indexed loads.
250 Target Var(TARGET_AUTO_MODIFY_REG)
251 Enable the use of pre/post modify with register displacement.
254 Target Report Mask(MULMAC_32BY16_SET)
255 Generate 32x16 multiply and mac instructions.
257 ; the initializer is supposed to be: Init(REG_BR_PROB_BASE/2) ,
258 ; alas, basic-block.h is not included in options.c .
259 munalign-prob-threshold=
260 Target RejectNegative Joined UInteger Var(arc_unalign_prob_threshold) Init(10000/2)
261 Set probability threshold for unaligning branches.
264 Target Var(TARGET_MEDIUM_CALLS) Init(TARGET_MMEDIUM_CALLS_DEFAULT)
265 Don't use less than 25 bit addressing range for calls.
268 Target Var(TARGET_ANNOTATE_ALIGN)
269 Explain what alignment considerations lead to the decision to make an insn short or long.
272 Target Var(TARGET_ALIGN_CALL)
273 Do alignment optimizations for call instructions.
276 Target Var(TARGET_Rcq)
277 Enable Rcq constraint handling - most short code generation depends on this.
280 Target Var(TARGET_Rcw)
281 Enable Rcw constraint handling - ccfsm condexec mostly depends on this.
284 Target Var(TARGET_EARLY_CBRANCHSI)
285 Enable pre-reload use of cbranchsi pattern.
288 Target Var(TARGET_BBIT_PEEPHOLE)
289 Enable bbit peephole2.
292 Target Var(TARGET_CASE_VECTOR_PC_RELATIVE)
293 Use pc-relative switch case tables - this enables case table shortening.
296 Target Var(TARGET_COMPACT_CASESI)
297 Enable compact casesi pattern.
300 Target Var(TARGET_Q_CLASS)
301 Enable 'q' instruction alternatives.
304 Target Var(TARGET_EXPAND_ADDDI)
305 Expand adddi3 and subdi3 at rtl generation time into add.f / adc etc.
308 ; Flags used by the assembler, but for which we define preprocessor
309 ; macro symbols as well.
312 Enable variable polynomial CRC extension.
316 Enable DSP 3.1 Pack A extensions.
320 Enable dual viterbi butterfly extension.
323 Target Report Undocumented
326 Target Report Undocumented
329 Target Report RejectNegative
330 Enable Dual and Single Operand Instructions for Telephony.
334 Enable XY Memory extension (DSP version 3).
336 ; ARC700 4.10 extension instructions
339 Enable Locked Load/Store Conditional extension.
343 Enable swap byte ordering extension instruction.
347 Enable 64-bit Time-Stamp Counter extension instruction.
351 Pass -EB option through to linker.
355 Pass -EL option through to linker.
359 Pass -marclinux option through to linker.
363 Pass -marclinux_prof option through to linker.
365 ;; lra is still unproven for ARC, so allow to fall back to reload with -mno-lra.
366 ;Target InverseMask(NO_LRA)
367 ; lra still won't allow to configure libgcc; see PR rtl-optimization/55464.
368 ; so don't enable by default.
374 Target RejectNegative Var(arc_lra_priority_tag, ARC_LRA_PRIORITY_NONE)
375 Don't indicate any priority with TARGET_REGISTER_PRIORITY.
377 mlra-priority-compact
378 Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_COMPACT)
379 Indicate priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY.
381 mlra-priority-noncompact
382 Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_NONCOMPACT)
383 Reduce priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY.
386 Target Report Var(TARGET_UCB_MCOUNT)
387 instrument with mcount calls as in the ucb code.
389 ; backward-compatibility aliases, translated by DRIVER_SELF_SPECS
395 Target RejectNegative Joined
397 ; Unfortunately, listing the full option name gives us clashes
398 ; with OPT_opt_name being claimed for both opt_name and opt-name,
399 ; so we leave out the last character or more.
416 Target Report Mask(ATOMIC)
417 Enable atomic instructions.
420 Target Report Mask(LL64)
421 Enable double load/store instructions for ARC HS.
424 Target RejectNegative Joined Enum(arc_fpu) Var(arc_fpu_build) Init(0)
425 Specify the name of the target floating point configuration.
428 Name(arc_fpu) Type(int)
431 Enum(arc_fpu) String(fpus) Value(FPU_SP | FPU_SC)
434 Enum(arc_fpu) String(fpud) Value(FPU_SP | FPU_SC | FPU_DP | FPU_DC)
437 Enum(arc_fpu) String(fpuda) Value(FPU_SP | FPU_SC | FPX_DP)
440 Enum(arc_fpu) String(fpuda_div) Value(FPU_SP | FPU_SC | FPU_SD | FPX_DP)
443 Enum(arc_fpu) String(fpuda_fma) Value(FPU_SP | FPU_SC | FPU_SF | FPX_DP)
446 Enum(arc_fpu) String(fpuda_all) Value(FPU_SP | FPU_SC | FPU_SF | FPU_SD | FPX_DP)
449 Enum(arc_fpu) String(fpus_div) Value(FPU_SP | FPU_SC | FPU_SD)
452 Enum(arc_fpu) String(fpud_div) Value(FPU_SP | FPU_SC | FPU_SD | FPU_DP | FPU_DC | FPU_DD)
455 Enum(arc_fpu) String(fpus_fma) Value(FPU_SP | FPU_SC | FPU_SF)
458 Enum(arc_fpu) String(fpud_fma) Value(FPU_SP | FPU_SC | FPU_SF | FPU_DP | FPU_DC | FPU_DF)
461 Enum(arc_fpu) String(fpus_all) Value(FPU_SP | FPU_SC | FPU_SF | FPU_SD)
464 Enum(arc_fpu) String(fpud_all) Value(FPU_SP | FPU_SC | FPU_SF | FPU_SD | FPU_DP | FPU_DC | FPU_DF | FPU_DD)
467 Target RejectNegative Joined UInteger Var(arc_tp_regno) Init(25)
468 Specify thread pointer register number
471 Target RejectNegative Var(arc_tp_regno,-1)
474 Target Report Var(TARGET_NPS_CMEM) Init(TARGET_NPS_CMEM_DEFAULT)
475 Enable use of NPS400 xld/xst extension.
478 Target Report Var(unaligned_access) Init(UNALIGNED_ACCESS_DEFAULT)
479 Enable unaligned word and halfword accesses to packed data.