1 ; Options for the Synopsys DesignWare ARC port of the compiler
3 ; Copyright (C) 2005-2021 Free Software Foundation, Inc.
5 ; This file is part of GCC.
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8 ; the terms of the GNU General Public License as published by the Free
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15 ; License for more details.
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25 Target RejectNegative Mask(BIG_ENDIAN)
26 Compile code for big endian mode.
29 Target RejectNegative InverseMask(BIG_ENDIAN)
30 Compile code for little endian mode. This is the default.
33 Target RejectNegative Mask(NO_COND_EXEC)
34 Disable ARCompact specific pass to generate conditional execution instructions.
38 Generate ARCompact 32-bit code for ARC600 processor.
46 Generate ARCompact 32-bit code for ARC601 processor.
50 Generate ARCompact 32-bit code for ARC700 processor.
57 Target Mask(JLI_ALWAYS)
58 Force all calls to be made via a jli instruction.
61 Target RejectNegative Joined Enum(arc_mpy) Var(arc_mpy_option) Init(DEFAULT_arc_mpy_option)
62 -mmpy-option=MPY Compile ARCv2 code with a multiplier design option.
65 Name(arc_mpy) Type(int)
68 Enum(arc_mpy) String(0) Value(0)
71 Enum(arc_mpy) String(none) Value(0) Canonical
74 Enum(arc_mpy) String(1) Value(1)
77 Enum(arc_mpy) String(w) Value(1) Canonical
80 Enum(arc_mpy) String(2) Value(2)
83 Enum(arc_mpy) String(mpy) Value(2)
86 Enum(arc_mpy) String(wlh1) Value(2) Canonical
89 Enum(arc_mpy) String(3) Value(3)
92 Enum(arc_mpy) String(wlh2) Value(3) Canonical
95 Enum(arc_mpy) String(4) Value(4)
98 Enum(arc_mpy) String(wlh3) Value(4) Canonical
101 Enum(arc_mpy) String(5) Value(5)
104 Enum(arc_mpy) String(wlh4) Value(5) Canonical
107 Enum(arc_mpy) String(6) Value(6)
110 Enum(arc_mpy) String(wlh5) Value(6) Canonical
113 Enum(arc_mpy) String(7) Value(7)
116 Enum(arc_mpy) String(plus_dmpy) Value(7) Canonical
119 Enum(arc_mpy) String(8) Value(8)
122 Enum(arc_mpy) String(plus_macd) Value(8) Canonical
125 Enum(arc_mpy) String(9) Value(9)
128 Enum(arc_mpy) String(plus_qmacw) Value(9) Canonical
132 Enable DIV-REM instructions for ARCv2.
135 Target Mask(CODE_DENSITY)
136 Enable code density instructions for ARCv2.
139 Target Mask(MIXED_CODE_SET)
140 Tweak register allocation to help 16-bit instruction generation.
141 ; originally this was:
142 ;Generate ARCompact 16-bit instructions intermixed with 32-bit instructions
143 ; but we do that without -mmixed-code, too, it's just a different instruction
144 ; count / size tradeoff.
146 ; We use an explict definition for the negative form because that is the
147 ; actually interesting option, and we want that to have its own comment.
149 Target RejectNegative Mask(VOLATILE_CACHE_SET)
150 Use ordinarily cached memory accesses for volatile references.
153 Target RejectNegative InverseMask(VOLATILE_CACHE_SET)
154 Enable cache bypass for volatile references.
157 Target Mask(BARREL_SHIFTER)
158 Generate instructions supported by barrel shifter.
161 Target Mask(NORM_SET)
162 Generate norm instruction.
165 Target Mask(SWAP_SET)
166 Generate swap instruction.
169 Target Mask(MUL64_SET)
170 Generate mul64 and mulu64 instructions.
173 Target Mask(NOMPY_SET) Warn(%qs is deprecated)
174 Do not generate mpy instructions for ARC700.
178 Generate extended arithmetic instructions, only valid for ARC700.
182 Dummy flag. This is the default unless FPX switches are provided explicitly.
185 Target Mask(LONG_CALLS_SET)
186 Generate call insns as register indirect calls.
189 Target Mask(NO_BRCC_SET)
190 Do no generate BRcc instructions in arc_reorg.
193 Target InverseMask(NO_SDATA_SET)
194 Generate sdata references. This is the default, unless you compile for PIC.
197 Target Mask(MILLICODE_THUNK_SET)
198 Generate millicode thunks.
201 Target Mask(SPFP_COMPACT_SET)
202 FPX: Generate Single Precision FPX (compact) instructions.
205 Target Mask(SPFP_COMPACT_SET) MaskExists
206 FPX: Generate Single Precision FPX (compact) instructions.
209 Target Mask(SPFP_FAST_SET)
210 FPX: Generate Single Precision FPX (fast) instructions.
213 Target Mask(ARGONAUT_SET)
214 FPX: Enable Argonaut ARC CPU Double Precision Floating Point extensions.
217 Target Mask(DPFP_COMPACT_SET)
218 FPX: Generate Double Precision FPX (compact) instructions.
221 Target Mask(DPFP_COMPACT_SET) MaskExists
222 FPX: Generate Double Precision FPX (compact) instructions.
225 Target Mask(DPFP_FAST_SET)
226 FPX: Generate Double Precision FPX (fast) instructions.
229 Target Mask(DPFP_DISABLE_LRSR)
230 Disable LR and SR instructions from using FPX extension aux registers.
233 Target Mask(SIMD_SET)
234 Enable generation of ARC SIMD instructions via target-specific builtins.
237 Target RejectNegative Joined Var(arc_cpu) Enum(processor_type) Init(PROCESSOR_NONE)
238 -mcpu=CPU Compile code for ARC variant CPU.
241 Target RejectNegative Joined UInteger Var(arc_size_opt_level) Init(-1)
242 Size optimization level: 0:none 1:opportunistic 2: regalloc 3:drop align, -Os.
245 Target PchIgnore Var(TARGET_DUMPISIZE)
246 Annotate assembler instructions with estimated addresses.
249 Target RejectNegative Joined UInteger Var(arc_multcost) Init(-1)
250 Cost to assume for a multiply instruction, with 4 being equal to a normal insn.
253 Target RejectNegative ToLower Joined Var(arc_tune) Enum(arc_tune_attr) Init(ARC_TUNE_NONE)
254 -mtune=TUNE Tune code for given ARC variant.
257 Name(arc_tune_attr) Type(int)
260 Enum(arc_tune_attr) String(arc600) Value(ARC_TUNE_ARC600)
263 Enum(arc_tune_attr) String(arc601) Value(ARC_TUNE_ARC600)
266 Enum(arc_tune_attr) String(arc7xx) Value(ARC_TUNE_ARC7XX)
269 Enum(arc_tune_attr) String(arc700) Value(ARC_TUNE_ARC700_4_2_STD)
272 Enum(arc_tune_attr) String(arc700-xmac) Value(ARC_TUNE_ARC700_4_2_XMAC)
275 Enum(arc_tune_attr) String(arc725d) Value(ARC_TUNE_ARC700_4_2_XMAC)
278 Enum(arc_tune_attr) String(arc750d) Value(ARC_TUNE_ARC700_4_2_XMAC)
281 Enum(arc_tune_attr) String(core3) Value(ARC_TUNE_CORE_3)
284 Target Var(TARGET_INDEXED_LOADS) Init(TARGET_INDEXED_LOADS_DEFAULT)
285 Enable the use of indexed loads.
288 Target Var(TARGET_AUTO_MODIFY_REG) Init(TARGET_AUTO_MODIFY_REG_DEFAULT)
289 Enable the use of pre/post modify with register displacement.
292 Target Mask(MULMAC_32BY16_SET)
293 Generate 32x16 multiply and mac instructions.
295 ; the initializer is supposed to be: Init(REG_BR_PROB_BASE/2) ,
296 ; alas, basic-block.h is not included in options.c .
297 munalign-prob-threshold=
298 Target RejectNegative Joined UInteger Var(arc_unalign_prob_threshold) Init(10000/2)
299 Set probability threshold for unaligning branches.
302 Target Var(TARGET_MEDIUM_CALLS) Init(TARGET_MMEDIUM_CALLS_DEFAULT)
303 Don't use less than 25 bit addressing range for calls.
306 Target Var(TARGET_ANNOTATE_ALIGN)
307 Explain what alignment considerations lead to the decision to make an insn short or long.
310 Target Var(TARGET_ALIGN_CALL)
311 Do alignment optimizations for call instructions.
314 Target Var(TARGET_Rcq)
315 Enable Rcq constraint handling - most short code generation depends on this.
318 Target Var(TARGET_Rcw)
319 Enable Rcw constraint handling - ccfsm condexec mostly depends on this.
322 Target Var(TARGET_EARLY_CBRANCHSI)
323 Enable pre-reload use of cbranchsi pattern.
326 Target Var(TARGET_BBIT_PEEPHOLE)
327 Enable bbit peephole2.
330 Target Var(TARGET_CASE_VECTOR_PC_RELATIVE)
331 Use pc-relative switch case tables - this enables case table shortening.
334 Target Warn(%qs is deprecated)
335 Enable compact casesi pattern.
338 Target Warn(%qs is deprecated)
339 Enable 'q' instruction alternatives.
342 Target Warn(%qs is deprecated)
343 Expand adddi3 and subdi3 at rtl generation time into add.f / adc etc.
346 ; Flags used by the assembler, but for which we define preprocessor
347 ; macro symbols as well.
349 Target Warn(%qs is deprecated)
350 Enable variable polynomial CRC extension.
353 Target Warn(%qs is deprecated)
354 Enable DSP 3.1 Pack A extensions.
357 Target Warn(%qs is deprecated)
358 Enable dual viterbi butterfly extension.
361 Target Undocumented Warn(%qs is deprecated)
364 Target Undocumented Warn(%qs is deprecated)
367 Target RejectNegative Warn(%qs is deprecated)
368 Enable Dual and Single Operand Instructions for Telephony.
372 Enable XY Memory extension (DSP version 3).
374 ; ARC700 4.10 extension instructions
377 Enable Locked Load/Store Conditional extension.
381 Enable swap byte ordering extension instruction.
384 Target Warn(%qs is deprecated)
385 Enable 64-bit Time-Stamp Counter extension instruction.
389 Pass -EB option through to linker.
393 Pass -EL option through to linker.
397 Pass -marclinux option through to linker.
401 Pass -marclinux_prof option through to linker.
403 ;; lra is still unproven for ARC, so allow to fall back to reload with -mno-lra.
405 Target Var(arc_lra_flag) Init(1) Save
406 Use LRA instead of reload.
409 Target RejectNegative Var(arc_lra_priority_tag, ARC_LRA_PRIORITY_NONE)
410 Don't indicate any priority with TARGET_REGISTER_PRIORITY.
412 mlra-priority-compact
413 Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_COMPACT)
414 Indicate priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY.
416 mlra-priority-noncompact
417 Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_NONCOMPACT)
418 Reduce priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY.
420 ; backward-compatibility aliases, translated by DRIVER_SELF_SPECS
426 Target RejectNegative Joined
430 Enable atomic instructions.
434 Enable double load/store instructions for ARC HS.
437 Target RejectNegative Joined Enum(arc_fpu) Var(arc_fpu_build) Init(DEFAULT_arc_fpu_build)
438 Specify the name of the target floating point configuration.
441 Name(arc_fpu) Type(int)
444 Enum(arc_fpu) String(fpus) Value(FPU_FPUS)
447 Enum(arc_fpu) String(fpud) Value(FPU_FPUD)
450 Enum(arc_fpu) String(fpuda) Value(FPU_FPUDA)
453 Enum(arc_fpu) String(fpuda_div) Value(FPU_FPUDA_DIV)
456 Enum(arc_fpu) String(fpuda_fma) Value(FPU_FPUDA_FMA)
459 Enum(arc_fpu) String(fpuda_all) Value(FPU_FPUDA_ALL)
462 Enum(arc_fpu) String(fpus_div) Value(FPU_FPUS_DIV)
465 Enum(arc_fpu) String(fpud_div) Value(FPU_FPUD_DIV)
468 Enum(arc_fpu) String(fpus_fma) Value(FPU_FPUS_FMA)
471 Enum(arc_fpu) String(fpud_fma) Value(FPU_FPUD_FMA)
474 Enum(arc_fpu) String(fpus_all) Value(FPU_FPUS_ALL)
477 Enum(arc_fpu) String(fpud_all) Value(FPU_FPUD_ALL)
480 Target RejectNegative Joined UInteger Var(arc_tp_regno) Init(TARGET_ARC_TP_REGNO_DEFAULT)
481 Specify thread pointer register number.
484 Target RejectNegative Var(arc_tp_regno,-1)
487 Target Var(TARGET_NPS_BITOPS) Init(TARGET_NPS_BITOPS_DEFAULT)
488 Enable use of NPS400 bit operations.
491 Target Var(TARGET_NPS_CMEM) Init(TARGET_NPS_CMEM_DEFAULT)
492 Enable use of NPS400 xld/xst extension.
495 Target Var(unaligned_access) Init(UNALIGNED_ACCESS_DEFAULT)
496 Enable unaligned word and halfword accesses to packed data.
499 Target RejectNegative Joined Var(arc_deferred_options) Defer
500 Specifies the registers that the processor saves on an interrupt entry and exit.
503 Target RejectNegative Joined Var(arc_deferred_options) Defer
504 Specifies the number of registers replicated in second register bank on entry to fast interrupt.
507 Target RejectNegative Joined Enum(arc_lpc) Var(arc_lpcwidth) Init(32)
508 Sets LP_COUNT register width. Possible values are 8, 16, 20, 24, 28, and 32.
511 Name(arc_lpc) Type(int)
514 Enum(arc_lpc) String(8) Value(8)
517 Enum(arc_lpc) String(16) Value(16)
520 Enum(arc_lpc) String(20) Value(20)
523 Enum(arc_lpc) String(24) Value(24)
526 Enum(arc_lpc) String(28) Value(28)
529 Enum(arc_lpc) String(32) Value(32)
533 Enable 16-entry register file.
536 Target Var(TARGET_BRANCH_INDEX) Init(DEFAULT_BRANCH_INDEX)
537 Enable use of BI/BIH instructions when available.
540 Target Var(TARGET_CODE_DENSITY_FRAME) Init(TARGET_CODE_DENSITY_FRAME_DEFAULT)
541 Enable ENTER_S and LEAVE_S opcodes for ARCv2.