gcc/config/arc/arc.opt

   1 ; Options for the Synopsys DesignWare ARC port of the compiler
   2 ;
   3 ; Copyright (C) 2005-2017 Free Software Foundation, Inc.
   4 ;
   5 ; This file is part of GCC.
   6 ;
   7 ; GCC is free software; you can redistribute it and/or modify it under
   8 ; the terms of the GNU General Public License as published by the Free
   9 ; Software Foundation; either version 3, or (at your option) any later
  10 ; version.
  11 ;
  12 ; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ; License for more details.
  16 ;
  17 ; You should have received a copy of the GNU General Public License
  18 ; along with GCC; see the file COPYING3.  If not see
  19 ; <http://www.gnu.org/licenses/>.
  20
  21 HeaderInclude
  22 config/arc/arc-opts.h
  23
  24 mbig-endian
  25 Target Report RejectNegative Mask(BIG_ENDIAN)
  26 Compile code for big endian mode.
  27
  28 mlittle-endian
  29 Target Report RejectNegative InverseMask(BIG_ENDIAN)
  30 Compile code for little endian mode.  This is the default.
  31
  32 mno-cond-exec
  33 Target Report RejectNegative Mask(NO_COND_EXEC)
  34 Disable ARCompact specific pass to generate conditional execution instructions.
  35
  36 mA6
  37 Target Report
  38 Generate ARCompact 32-bit code for ARC600 processor.
  39
  40 mARC600
  41 Target Report
  42 Same as -mA6.
  43
  44 mARC601
  45 Target Report
  46 Generate ARCompact 32-bit code for ARC601 processor.
  47
  48 mA7
  49 Target Report
  50 Generate ARCompact 32-bit code for ARC700 processor.
  51
  52 mARC700
  53 Target Report
  54 Same as -mA7.
  55
  56 mmpy-option=
  57 Target RejectNegative Joined Enum(arc_mpy) Var(arc_mpy_option) Init(DEFAULT_arc_mpy_option)
  58 -mmpy-option=MPY Compile ARCv2 code with a multiplier design option.
  59
  60 Enum
  61 Name(arc_mpy) Type(int)
  62
  63 EnumValue
  64 Enum(arc_mpy) String(0) Value(0)
  65
  66 EnumValue
  67 Enum(arc_mpy) String(none) Value(0) Canonical
  68
  69 EnumValue
  70 Enum(arc_mpy) String(1) Value(1)
  71
  72 EnumValue
  73 Enum(arc_mpy) String(w) Value(1) Canonical
  74
  75 EnumValue
  76 Enum(arc_mpy) String(2) Value(2)
  77
  78 EnumValue
  79 Enum(arc_mpy) String(mpy) Value(2)
  80
  81 EnumValue
  82 Enum(arc_mpy) String(wlh1) Value(2) Canonical
  83
  84 EnumValue
  85 Enum(arc_mpy) String(3) Value(3)
  86
  87 EnumValue
  88 Enum(arc_mpy) String(wlh2) Value(3) Canonical
  89
  90 EnumValue
  91 Enum(arc_mpy) String(4) Value(4)
  92
  93 EnumValue
  94 Enum(arc_mpy) String(wlh3) Value(4) Canonical
  95
  96 EnumValue
  97 Enum(arc_mpy) String(5) Value(5)
  98
  99 EnumValue
 100 Enum(arc_mpy) String(wlh4) Value(5) Canonical
 101
 102 EnumValue
 103 Enum(arc_mpy) String(6) Value(6)
 104
 105 EnumValue
 106 Enum(arc_mpy) String(wlh5) Value(6) Canonical
 107
 108 EnumValue
 109 Enum(arc_mpy) String(7) Value(7)
 110
 111 EnumValue
 112 Enum(arc_mpy) String(plus_dmpy) Value(7) Canonical
 113
 114 EnumValue
 115 Enum(arc_mpy) String(8) Value(8)
 116
 117 EnumValue
 118 Enum(arc_mpy) String(plus_macd) Value(8) Canonical
 119
 120 EnumValue
 121 Enum(arc_mpy) String(9) Value(9)
 122
 123 EnumValue
 124 Enum(arc_mpy) String(plus_qmacw) Value(9) Canonical
 125
 126 mdiv-rem
 127 Target Report Mask(DIVREM)
 128 Enable DIV-REM instructions for ARCv2.
 129
 130 mcode-density
 131 Target Report Mask(CODE_DENSITY)
 132 Enable code density instructions for ARCv2.
 133
 134 mmixed-code
 135 Target Report Mask(MIXED_CODE_SET)
 136 Tweak register allocation to help 16-bit instruction generation.
 137 ; originally this was:
 138 ;Generate ARCompact 16-bit instructions intermixed with 32-bit instructions
 139 ; but we do that without -mmixed-code, too, it's just a different instruction
 140 ; count / size tradeoff.
 141
 142 ; We use an explict definition for the negative form because that is the
 143 ; actually interesting option, and we want that to have its own comment.
 144 mvolatile-cache
 145 Target Report RejectNegative Mask(VOLATILE_CACHE_SET)
 146 Use ordinarily cached memory accesses for volatile references.
 147
 148 mno-volatile-cache
 149 Target Report RejectNegative InverseMask(VOLATILE_CACHE_SET)
 150 Enable cache bypass for volatile references.
 151
 152 mbarrel-shifter
 153 Target Report Mask(BARREL_SHIFTER)
 154 Generate instructions supported by barrel shifter.
 155
 156 mnorm
 157 Target Report Mask(NORM_SET)
 158 Generate norm instruction.
 159
 160 mswap
 161 Target Report Mask(SWAP_SET)
 162 Generate swap instruction.
 163
 164 mmul64
 165 Target Report Mask(MUL64_SET)
 166 Generate mul64 and mulu64 instructions.
 167
 168 mno-mpy
 169 Target Report Mask(NOMPY_SET) Warn(%qs is deprecated)
 170 Do not generate mpy instructions for ARC700.
 171
 172 mea
 173 Target Report Mask(EA_SET)
 174 Generate Extended arithmetic instructions.  Currently only divaw, adds, subs and sat16 are supported.
 175
 176 msoft-float
 177 Target Report Mask(0)
 178 Dummy flag. This is the default unless FPX switches are provided explicitly.
 179
 180 mlong-calls
 181 Target Report Mask(LONG_CALLS_SET)
 182 Generate call insns as register indirect calls.
 183
 184 mno-brcc
 185 Target Report Mask(NO_BRCC_SET)
 186 Do no generate BRcc instructions in arc_reorg.
 187
 188 msdata
 189 Target Report InverseMask(NO_SDATA_SET)
 190 Generate sdata references.  This is the default, unless you compile for PIC.
 191
 192 mno-millicode
 193 Target Report Mask(NO_MILLICODE_THUNK_SET)
 194 Do not generate millicode thunks (needed only with -Os).
 195
 196 mspfp
 197 Target Report Mask(SPFP_COMPACT_SET)
 198 FPX: Generate Single Precision FPX (compact) instructions.
 199
 200 mspfp-compact
 201 Target Report Mask(SPFP_COMPACT_SET) MaskExists
 202 FPX: Generate Single Precision FPX (compact) instructions.
 203
 204 mspfp-fast
 205 Target Report Mask(SPFP_FAST_SET)
 206 FPX: Generate Single Precision FPX (fast) instructions.
 207
 208 margonaut
 209 Target Report Mask(ARGONAUT_SET)
 210 FPX: Enable Argonaut ARC CPU Double Precision Floating Point extensions.
 211
 212 mdpfp
 213 Target Report Mask(DPFP_COMPACT_SET)
 214 FPX: Generate Double Precision FPX (compact) instructions.
 215
 216 mdpfp-compact
 217 Target Report Mask(DPFP_COMPACT_SET) MaskExists
 218 FPX: Generate Double Precision FPX (compact) instructions.
 219
 220 mdpfp-fast
 221 Target Report Mask(DPFP_FAST_SET)
 222 FPX: Generate Double Precision FPX (fast) instructions.
 223
 224 mno-dpfp-lrsr
 225 Target Report Mask(DPFP_DISABLE_LRSR)
 226 Disable LR and SR instructions from using FPX extension aux registers.
 227
 228 msimd
 229 Target Report Mask(SIMD_SET)
 230 Enable generation of ARC SIMD instructions via target-specific builtins.
 231
 232 mcpu=
 233 Target RejectNegative Joined Var(arc_cpu) Enum(processor_type) Init(PROCESSOR_NONE)
 234 -mcpu=CPU       Compile code for ARC variant CPU.
 235
 236 msize-level=
 237 Target RejectNegative Joined UInteger Var(arc_size_opt_level) Init(-1)
 238 size optimization level: 0:none 1:opportunistic 2: regalloc 3:drop align, -Os.
 239
 240 misize
 241 Target Report PchIgnore Var(TARGET_DUMPISIZE)
 242 Annotate assembler instructions with estimated addresses.
 243
 244 mmultcost=
 245 Target RejectNegative Joined UInteger Var(arc_multcost) Init(-1)
 246 Cost to assume for a multiply instruction, with 4 being equal to a normal insn.
 247
 248 mtune=ARC600
 249 Target RejectNegative Var(arc_tune, TUNE_ARC600)
 250 Tune for ARC600 cpu.
 251
 252 mtune=ARC601
 253 Target RejectNegative Var(arc_tune, TUNE_ARC600)
 254 Tune for ARC601 cpu.
 255
 256 mtune=ARC700
 257 Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_STD)
 258 Tune for ARC700 R4.2 Cpu with standard multiplier block.
 259
 260 mtune=ARC700-xmac
 261 Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_XMAC)
 262 Tune for ARC700 R4.2 Cpu with XMAC block.
 263
 264 mtune=ARC725D
 265 Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_XMAC)
 266 Tune for ARC700 R4.2 Cpu with XMAC block.
 267
 268 mtune=ARC750D
 269 Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_XMAC)
 270 Tune for ARC700 R4.2 Cpu with XMAC block.
 271
 272 mindexed-loads
 273 Target Var(TARGET_INDEXED_LOADS) Init(TARGET_INDEXED_LOADS_DEFAULT)
 274 Enable the use of indexed loads.
 275
 276 mauto-modify-reg
 277 Target Var(TARGET_AUTO_MODIFY_REG) Init(TARGET_AUTO_MODIFY_REG_DEFAULT)
 278 Enable the use of pre/post modify with register displacement.
 279
 280 mmul32x16
 281 Target Report Mask(MULMAC_32BY16_SET)
 282 Generate 32x16 multiply and mac instructions.
 283
 284 ; the initializer is supposed to be: Init(REG_BR_PROB_BASE/2) ,
 285 ; alas, basic-block.h is not included in options.c .
 286 munalign-prob-threshold=
 287 Target RejectNegative Joined UInteger Var(arc_unalign_prob_threshold) Init(10000/2)
 288 Set probability threshold for unaligning branches.
 289
 290 mmedium-calls
 291 Target Var(TARGET_MEDIUM_CALLS) Init(TARGET_MMEDIUM_CALLS_DEFAULT)
 292 Don't use less than 25 bit addressing range for calls.
 293
 294 mannotate-align
 295 Target Var(TARGET_ANNOTATE_ALIGN)
 296 Explain what alignment considerations lead to the decision to make an insn short or long.
 297
 298 malign-call
 299 Target Var(TARGET_ALIGN_CALL)
 300 Do alignment optimizations for call instructions.
 301
 302 mRcq
 303 Target Var(TARGET_Rcq)
 304 Enable Rcq constraint handling - most short code generation depends on this.
 305
 306 mRcw
 307 Target Var(TARGET_Rcw)
 308 Enable Rcw constraint handling - ccfsm condexec mostly depends on this.
 309
 310 mearly-cbranchsi
 311 Target Var(TARGET_EARLY_CBRANCHSI)
 312 Enable pre-reload use of cbranchsi pattern.
 313
 314 mbbit-peephole
 315 Target Var(TARGET_BBIT_PEEPHOLE)
 316 Enable bbit peephole2.
 317
 318 mcase-vector-pcrel
 319 Target Var(TARGET_CASE_VECTOR_PC_RELATIVE)
 320 Use pc-relative switch case tables - this enables case table shortening.
 321
 322 mcompact-casesi
 323 Target Var(TARGET_COMPACT_CASESI)
 324 Enable compact casesi pattern.
 325
 326 mq-class
 327 Target Var(TARGET_Q_CLASS)
 328 Enable 'q' instruction alternatives.
 329
 330 mexpand-adddi
 331 Target Warn(%qs is deprecated)
 332 Expand adddi3 and subdi3 at rtl generation time into add.f / adc etc.
 333
 334
 335 ; Flags used by the assembler, but for which we define preprocessor
 336 ; macro symbols as well.
 337 mcrc
 338 Target Report Warn(%qs is deprecated)
 339 Enable variable polynomial CRC extension.
 340
 341 mdsp-packa
 342 Target Report Warn(%qs is deprecated)
 343 Enable DSP 3.1 Pack A extensions.
 344
 345 mdvbf
 346 Target Report Warn(%qs is deprecated)
 347 Enable dual viterbi butterfly extension.
 348
 349 mmac-d16
 350 Target Report Undocumented Warn(%qs is deprecated)
 351
 352 mmac-24
 353 Target Report Undocumented Warn(%qs is deprecated)
 354
 355 mtelephony
 356 Target Report RejectNegative Warn(%qs is deprecated)
 357 Enable Dual and Single Operand Instructions for Telephony.
 358
 359 mxy
 360 Target Report
 361 Enable XY Memory extension (DSP version 3).
 362
 363 ; ARC700 4.10 extension instructions
 364 mlock
 365 Target Report
 366 Enable Locked Load/Store Conditional extension.
 367
 368 mswape
 369 Target Report
 370 Enable swap byte ordering extension instruction.
 371
 372 mrtsc
 373 Target Report Warn(%qs is deprecated)
 374 Enable 64-bit Time-Stamp Counter extension instruction.
 375
 376 EB
 377 Target
 378 Pass -EB option through to linker.
 379
 380 EL
 381 Target
 382 Pass -EL option through to linker.
 383
 384 marclinux
 385 Target
 386 Pass -marclinux option through to linker.
 387
 388 marclinux_prof
 389 Target
 390 Pass -marclinux_prof option through to linker.
 391
 392 ;; lra is still unproven for ARC, so allow to fall back to reload with -mno-lra.
 393 ;Target InverseMask(NO_LRA)
 394 ; lra still won't allow to configure libgcc; see PR rtl-optimization/55464.
 395 ; so don't enable by default.
 396 mlra
 397 Target Mask(LRA)
 398 Enable lra.
 399
 400 mlra-priority-none
 401 Target RejectNegative Var(arc_lra_priority_tag, ARC_LRA_PRIORITY_NONE)
 402 Don't indicate any priority with TARGET_REGISTER_PRIORITY.
 403
 404 mlra-priority-compact
 405 Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_COMPACT)
 406 Indicate priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY.
 407
 408 mlra-priority-noncompact
 409 Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_NONCOMPACT)
 410 Reduce priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY.
 411
 412 ; backward-compatibility aliases, translated by DRIVER_SELF_SPECS
 413
 414 mEA
 415 Target
 416
 417 multcost=
 418 Target RejectNegative Joined
 419
 420 matomic
 421 Target Report Mask(ATOMIC)
 422 Enable atomic instructions.
 423
 424 mll64
 425 Target Report Mask(LL64)
 426 Enable double load/store instructions for ARC HS.
 427
 428 mfpu=
 429 Target RejectNegative Joined Enum(arc_fpu) Var(arc_fpu_build) Init(DEFAULT_arc_fpu_build)
 430 Specify the name of the target floating point configuration.
 431
 432 Enum
 433 Name(arc_fpu) Type(int)
 434
 435 EnumValue
 436 Enum(arc_fpu) String(fpus) Value(FPU_FPUS)
 437
 438 EnumValue
 439 Enum(arc_fpu) String(fpud) Value(FPU_FPUD)
 440
 441 EnumValue
 442 Enum(arc_fpu) String(fpuda) Value(FPU_FPUDA)
 443
 444 EnumValue
 445 Enum(arc_fpu) String(fpuda_div) Value(FPU_FPUDA_DIV)
 446
 447 EnumValue
 448 Enum(arc_fpu) String(fpuda_fma) Value(FPU_FPUDA_FMA)
 449
 450 EnumValue
 451 Enum(arc_fpu) String(fpuda_all) Value(FPU_FPUDA_ALL)
 452
 453 EnumValue
 454 Enum(arc_fpu) String(fpus_div) Value(FPU_FPUS_DIV)
 455
 456 EnumValue
 457 Enum(arc_fpu) String(fpud_div) Value(FPU_FPUD_DIV)
 458
 459 EnumValue
 460 Enum(arc_fpu) String(fpus_fma) Value(FPU_FPUS_FMA)
 461
 462 EnumValue
 463 Enum(arc_fpu) String(fpud_fma) Value(FPU_FPUD_FMA)
 464
 465 EnumValue
 466 Enum(arc_fpu) String(fpus_all) Value(FPU_FPUS_ALL)
 467
 468 EnumValue
 469 Enum(arc_fpu) String(fpud_all) Value(FPU_FPUD_ALL)
 470
 471 mtp-regno=
 472 Target RejectNegative Joined UInteger Var(arc_tp_regno) Init(TARGET_ARC_TP_REGNO_DEFAULT)
 473 Specify thread pointer register number.
 474
 475 mtp-regno=none
 476 Target RejectNegative Var(arc_tp_regno,-1)
 477
 478 mbitops
 479 Target Report Var(TARGET_NPS_BITOPS) Init(TARGET_NPS_BITOPS_DEFAULT)
 480 Enable use of NPS400 bit operations.
 481
 482 mcmem
 483 Target Report Var(TARGET_NPS_CMEM) Init(TARGET_NPS_CMEM_DEFAULT)
 484 Enable use of NPS400 xld/xst extension.
 485
 486 munaligned-access
 487 Target Report Var(unaligned_access) Init(UNALIGNED_ACCESS_DEFAULT)
 488 Enable unaligned word and halfword accesses to packed data.
 489
 490 mirq-ctrl-saved=
 491 Target RejectNegative Joined Var(arc_deferred_options) Defer
 492 Specifies the registers that the processor saves on an interrupt entry and exit.
 493
 494 mrgf-banked-regs=
 495 Target RejectNegative Joined Var(arc_deferred_options) Defer
 496 Specifies the number of registers replicated in second register bank on entry to fast interrupt.
 497
 498 mlpc-width=
 499 Target RejectNegative Joined Enum(arc_lpc) Var(arc_lpcwidth) Init(32)
 500 Sets LP_COUNT register width.  Possible values are 8, 16, 20, 24, 28, and 32.
 501
 502 Enum
 503 Name(arc_lpc) Type(int)
 504
 505 EnumValue
 506 Enum(arc_lpc) String(8) Value(8)
 507
 508 EnumValue
 509 Enum(arc_lpc) String(16) Value(16)
 510
 511 EnumValue
 512 Enum(arc_lpc) String(20) Value(20)
 513
 514 EnumValue
 515 Enum(arc_lpc) String(24) Value(24)
 516
 517 EnumValue
 518 Enum(arc_lpc) String(28) Value(28)
 519
 520 EnumValue
 521 Enum(arc_lpc) String(32) Value(32)