gcc/config/arc/arc.opt

   1 ; Options for the Synopsys DesignWare ARC port of the compiler
   2 ;
   3 ; Copyright (C) 2005-2016 Free Software Foundation, Inc.
   4 ;
   5 ; This file is part of GCC.
   6 ;
   7 ; GCC is free software; you can redistribute it and/or modify it under
   8 ; the terms of the GNU General Public License as published by the Free
   9 ; Software Foundation; either version 3, or (at your option) any later
  10 ; version.
  11 ;
  12 ; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ; License for more details.
  16 ;
  17 ; You should have received a copy of the GNU General Public License
  18 ; along with GCC; see the file COPYING3.  If not see
  19 ; <http://www.gnu.org/licenses/>.
  20
  21 HeaderInclude
  22 config/arc/arc-opts.h
  23
  24 mbig-endian
  25 Target Report RejectNegative Mask(BIG_ENDIAN)
  26 Compile code for big endian mode.
  27
  28 mlittle-endian
  29 Target Report RejectNegative InverseMask(BIG_ENDIAN)
  30 Compile code for little endian mode.  This is the default.
  31
  32 mno-cond-exec
  33 Target Report RejectNegative Mask(NO_COND_EXEC)
  34 Disable ARCompact specific pass to generate conditional execution instructions.
  35
  36 mA6
  37 Target Report
  38 Generate ARCompact 32-bit code for ARC600 processor.
  39
  40 mARC600
  41 Target Report
  42 Same as -mA6.
  43
  44 mARC601
  45 Target Report
  46 Generate ARCompact 32-bit code for ARC601 processor.
  47
  48 mA7
  49 Target Report
  50 Generate ARCompact 32-bit code for ARC700 processor.
  51
  52 mARC700
  53 Target Report
  54 Same as -mA7.
  55
  56 mmpy-option=
  57 Target RejectNegative Joined UInteger Var(arc_mpy_option) Init(2)
  58 -mmpy-option={0,1,2,3,4,5,6,7,8,9} Compile ARCv2 code with a multiplier design option.  Option 2 is default on.
  59
  60 mdiv-rem
  61 Target Report Mask(DIVREM)
  62 Enable DIV-REM instructions for ARCv2.
  63
  64 mcode-density
  65 Target Report Mask(CODE_DENSITY)
  66 Enable code density instructions for ARCv2.
  67
  68 mmixed-code
  69 Target Report Mask(MIXED_CODE_SET)
  70 Tweak register allocation to help 16-bit instruction generation.
  71 ; originally this was:
  72 ;Generate ARCompact 16-bit instructions intermixed with 32-bit instructions
  73 ; but we do that without -mmixed-code, too, it's just a different instruction
  74 ; count / size tradeoff.
  75
  76 ; We use an explict definition for the negative form because that is the
  77 ; actually interesting option, and we want that to have its own comment.
  78 mvolatile-cache
  79 Target Report RejectNegative Mask(VOLATILE_CACHE_SET)
  80 Use ordinarily cached memory accesses for volatile references.
  81
  82 mno-volatile-cache
  83 Target Report RejectNegative InverseMask(VOLATILE_CACHE_SET)
  84 Enable cache bypass for volatile references.
  85
  86 mbarrel-shifter
  87 Target Report Mask(BARREL_SHIFTER)
  88 Generate instructions supported by barrel shifter.
  89
  90 mnorm
  91 Target Report Mask(NORM_SET)
  92 Generate norm instruction.
  93
  94 mswap
  95 Target Report Mask(SWAP_SET)
  96 Generate swap instruction.
  97
  98 mmul64
  99 Target Report Mask(MUL64_SET)
 100 Generate mul64 and mulu64 instructions.
 101
 102 mno-mpy
 103 Target Report Mask(NOMPY_SET)
 104 Do not generate mpy instructions for ARC700.
 105
 106 mea
 107 Target Report Mask(EA_SET)
 108 Generate Extended arithmetic instructions.  Currently only divaw, adds, subs and sat16 are supported.
 109
 110 msoft-float
 111 Target Report Mask(0)
 112 Dummy flag. This is the default unless FPX switches are provided explicitly.
 113
 114 mlong-calls
 115 Target Report Mask(LONG_CALLS_SET)
 116 Generate call insns as register indirect calls.
 117
 118 mno-brcc
 119 Target Report Mask(NO_BRCC_SET)
 120 Do no generate BRcc instructions in arc_reorg.
 121
 122 msdata
 123 Target Report InverseMask(NO_SDATA_SET)
 124 Generate sdata references.  This is the default, unless you compile for PIC.
 125
 126 mno-millicode
 127 Target Report Mask(NO_MILLICODE_THUNK_SET)
 128 Do not generate millicode thunks (needed only with -Os).
 129
 130 mspfp
 131 Target Report Mask(SPFP_COMPACT_SET)
 132 FPX: Generate Single Precision FPX (compact) instructions.
 133
 134 mspfp-compact
 135 Target Report Mask(SPFP_COMPACT_SET) MaskExists
 136 FPX: Generate Single Precision FPX (compact) instructions.
 137
 138 mspfp-fast
 139 Target Report Mask(SPFP_FAST_SET)
 140 FPX: Generate Single Precision FPX (fast) instructions.
 141
 142 margonaut
 143 Target Report Mask(ARGONAUT_SET)
 144 FPX: Enable Argonaut ARC CPU Double Precision Floating Point extensions.
 145
 146 mdpfp
 147 Target Report Mask(DPFP_COMPACT_SET)
 148 FPX: Generate Double Precision FPX (compact) instructions.
 149
 150 mdpfp-compact
 151 Target Report Mask(DPFP_COMPACT_SET) MaskExists
 152 FPX: Generate Double Precision FPX (compact) instructions.
 153
 154 mdpfp-fast
 155 Target Report Mask(DPFP_FAST_SET)
 156 FPX: Generate Double Precision FPX (fast) instructions.
 157
 158 mno-dpfp-lrsr
 159 Target Report Mask(DPFP_DISABLE_LRSR)
 160 Disable LR and SR instructions from using FPX extension aux registers.
 161
 162 msimd
 163 Target Report Mask(SIMD_SET)
 164 Enable generation of ARC SIMD instructions via target-specific builtins.
 165
 166 mcpu=
 167 Target RejectNegative Joined Var(arc_cpu) Enum(processor_type) Init(PROCESSOR_NONE)
 168 -mcpu=CPU       Compile code for ARC variant CPU.
 169
 170 Enum
 171 Name(processor_type) Type(enum processor_type)
 172
 173 EnumValue
 174 Enum(processor_type) String(ARC600) Value(PROCESSOR_ARC600)
 175
 176 EnumValue
 177 Enum(processor_type) String(arc600) Value(PROCESSOR_ARC600)
 178
 179 EnumValue
 180 Enum(processor_type) String(ARC601) Value(PROCESSOR_ARC601)
 181
 182 EnumValue
 183 Enum(processor_type) String(arc601) Value(PROCESSOR_ARC601)
 184
 185 EnumValue
 186 Enum(processor_type) String(ARC700) Value(PROCESSOR_ARC700)
 187
 188 EnumValue
 189 Enum(processor_type) String(arc700) Value(PROCESSOR_ARC700)
 190
 191 EnumValue
 192 Enum(processor_type) String(nps400) Value(PROCESSOR_NPS400)
 193
 194 EnumValue
 195 Enum(processor_type) String(NPS400) Value(PROCESSOR_NPS400)
 196
 197 EnumValue
 198 Enum(processor_type) String(ARCEM) Value(PROCESSOR_ARCEM)
 199
 200 EnumValue
 201 Enum(processor_type) String(arcem) Value(PROCESSOR_ARCEM)
 202
 203 EnumValue
 204 Enum(processor_type) String(ARCHS) Value(PROCESSOR_ARCHS)
 205
 206 EnumValue
 207 Enum(processor_type) String(archs) Value(PROCESSOR_ARCHS)
 208
 209 msize-level=
 210 Target RejectNegative Joined UInteger Var(arc_size_opt_level) Init(-1)
 211 size optimization level: 0:none 1:opportunistic 2: regalloc 3:drop align, -Os.
 212
 213 misize
 214 Target Report PchIgnore Var(TARGET_DUMPISIZE)
 215 Annotate assembler instructions with estimated addresses.
 216
 217 mmultcost=
 218 Target RejectNegative Joined UInteger Var(arc_multcost) Init(-1)
 219 Cost to assume for a multiply instruction, with 4 being equal to a normal insn.
 220
 221 mtune=ARC600
 222 Target RejectNegative Var(arc_tune, TUNE_ARC600)
 223 Tune for ARC600 cpu.
 224
 225 mtune=ARC601
 226 Target RejectNegative Var(arc_tune, TUNE_ARC600)
 227 Tune for ARC601 cpu.
 228
 229 mtune=ARC700
 230 Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_STD)
 231 Tune for ARC700 R4.2 Cpu with standard multiplier block.
 232
 233 mtune=ARC700-xmac
 234 Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_XMAC)
 235 Tune for ARC700 R4.2 Cpu with XMAC block.
 236
 237 mtune=ARC725D
 238 Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_XMAC)
 239 Tune for ARC700 R4.2 Cpu with XMAC block.
 240
 241 mtune=ARC750D
 242 Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_XMAC)
 243 Tune for ARC700 R4.2 Cpu with XMAC block.
 244
 245 mindexed-loads
 246 Target Var(TARGET_INDEXED_LOADS)
 247 Enable the use of indexed loads.
 248
 249 mauto-modify-reg
 250 Target Var(TARGET_AUTO_MODIFY_REG)
 251 Enable the use of pre/post modify with register displacement.
 252
 253 mmul32x16
 254 Target Report Mask(MULMAC_32BY16_SET)
 255 Generate 32x16 multiply and mac instructions.
 256
 257 ; the initializer is supposed to be: Init(REG_BR_PROB_BASE/2) ,
 258 ; alas, basic-block.h is not included in options.c .
 259 munalign-prob-threshold=
 260 Target RejectNegative Joined UInteger Var(arc_unalign_prob_threshold) Init(10000/2)
 261 Set probability threshold for unaligning branches.
 262
 263 mmedium-calls
 264 Target Var(TARGET_MEDIUM_CALLS) Init(TARGET_MMEDIUM_CALLS_DEFAULT)
 265 Don't use less than 25 bit addressing range for calls.
 266
 267 mannotate-align
 268 Target Var(TARGET_ANNOTATE_ALIGN)
 269 Explain what alignment considerations lead to the decision to make an insn short or long.
 270
 271 malign-call
 272 Target Var(TARGET_ALIGN_CALL)
 273 Do alignment optimizations for call instructions.
 274
 275 mRcq
 276 Target Var(TARGET_Rcq)
 277 Enable Rcq constraint handling - most short code generation depends on this.
 278
 279 mRcw
 280 Target Var(TARGET_Rcw)
 281 Enable Rcw constraint handling - ccfsm condexec mostly depends on this.
 282
 283 mearly-cbranchsi
 284 Target Var(TARGET_EARLY_CBRANCHSI)
 285 Enable pre-reload use of cbranchsi pattern.
 286
 287 mbbit-peephole
 288 Target Var(TARGET_BBIT_PEEPHOLE)
 289 Enable bbit peephole2.
 290
 291 mcase-vector-pcrel
 292 Target Var(TARGET_CASE_VECTOR_PC_RELATIVE)
 293 Use pc-relative switch case tables - this enables case table shortening.
 294
 295 mcompact-casesi
 296 Target Var(TARGET_COMPACT_CASESI)
 297 Enable compact casesi pattern.
 298
 299 mq-class
 300 Target Var(TARGET_Q_CLASS)
 301 Enable 'q' instruction alternatives.
 302
 303 mexpand-adddi
 304 Target Var(TARGET_EXPAND_ADDDI)
 305 Expand adddi3 and subdi3 at rtl generation time into add.f / adc etc.
 306
 307
 308 ; Flags used by the assembler, but for which we define preprocessor
 309 ; macro symbols as well.
 310 mcrc
 311 Target Report
 312 Enable variable polynomial CRC extension.
 313
 314 mdsp-packa
 315 Target Report
 316 Enable DSP 3.1 Pack A extensions.
 317
 318 mdvbf
 319 Target Report
 320 Enable dual viterbi butterfly extension.
 321
 322 mmac-d16
 323 Target Report Undocumented
 324
 325 mmac-24
 326 Target Report Undocumented
 327
 328 mtelephony
 329 Target Report RejectNegative
 330 Enable Dual and Single Operand Instructions for Telephony.
 331
 332 mxy
 333 Target Report
 334 Enable XY Memory extension (DSP version 3).
 335
 336 ; ARC700 4.10 extension instructions
 337 mlock
 338 Target Report
 339 Enable Locked Load/Store Conditional extension.
 340
 341 mswape
 342 Target Report
 343 Enable swap byte ordering extension instruction.
 344
 345 mrtsc
 346 Target Report
 347 Enable 64-bit Time-Stamp Counter extension instruction.
 348
 349 EB
 350 Target
 351 Pass -EB option through to linker.
 352
 353 EL
 354 Target
 355 Pass -EL option through to linker.
 356
 357 marclinux
 358 target
 359 Pass -marclinux option through to linker.
 360
 361 marclinux_prof
 362 target
 363 Pass -marclinux_prof option through to linker.
 364
 365 ;; lra is still unproven for ARC, so allow to fall back to reload with -mno-lra.
 366 ;Target InverseMask(NO_LRA)
 367 ; lra still won't allow to configure libgcc; see PR rtl-optimization/55464.
 368 ; so don't enable by default.
 369 mlra
 370 Target Mask(LRA)
 371 Enable lra.
 372
 373 mlra-priority-none
 374 Target RejectNegative Var(arc_lra_priority_tag, ARC_LRA_PRIORITY_NONE)
 375 Don't indicate any priority with TARGET_REGISTER_PRIORITY.
 376
 377 mlra-priority-compact
 378 Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_COMPACT)
 379 Indicate priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY.
 380
 381 mlra-priority-noncompact
 382 Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_NONCOMPACT)
 383 Reduce priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY.
 384
 385 mucb-mcount
 386 Target Report Var(TARGET_UCB_MCOUNT)
 387 instrument with mcount calls as in the ucb code.
 388
 389 ; backward-compatibility aliases, translated by DRIVER_SELF_SPECS
 390
 391 mEA
 392 Target
 393
 394 multcost=
 395 Target RejectNegative Joined
 396
 397 ; Unfortunately, listing the full option name gives us clashes
 398 ; with OPT_opt_name being claimed for both opt_name and opt-name,
 399 ; so we leave out the last character or more.
 400 mbarrel_shifte
 401 Target Joined
 402
 403 mspfp_
 404 Target Joined
 405
 406 mdpfp_
 407 Target Joined
 408
 409 mdsp_pack
 410 Target Joined
 411
 412 mmac_
 413 Target Joined
 414
 415 matomic
 416 Target Report Mask(ATOMIC)
 417 Enable atomic instructions.
 418
 419 mll64
 420 Target Report Mask(LL64)
 421 Enable double load/store instructions for ARC HS.
 422
 423 mfpu=
 424 Target RejectNegative Joined Enum(arc_fpu) Var(arc_fpu_build) Init(0)
 425 Specify the name of the target floating point configuration.
 426
 427 Enum
 428 Name(arc_fpu) Type(int)
 429
 430 EnumValue
 431 Enum(arc_fpu) String(fpus) Value(FPU_SP | FPU_SC)
 432
 433 EnumValue
 434 Enum(arc_fpu) String(fpud) Value(FPU_SP | FPU_SC | FPU_DP | FPU_DC)
 435
 436 EnumValue
 437 Enum(arc_fpu) String(fpuda) Value(FPU_SP | FPU_SC | FPX_DP)
 438
 439 EnumValue
 440 Enum(arc_fpu) String(fpuda_div) Value(FPU_SP | FPU_SC | FPU_SD | FPX_DP)
 441
 442 EnumValue
 443 Enum(arc_fpu) String(fpuda_fma) Value(FPU_SP | FPU_SC | FPU_SF | FPX_DP)
 444
 445 EnumValue
 446 Enum(arc_fpu) String(fpuda_all) Value(FPU_SP | FPU_SC | FPU_SF | FPU_SD | FPX_DP)
 447
 448 EnumValue
 449 Enum(arc_fpu) String(fpus_div) Value(FPU_SP | FPU_SC | FPU_SD)
 450
 451 EnumValue
 452 Enum(arc_fpu) String(fpud_div) Value(FPU_SP | FPU_SC | FPU_SD | FPU_DP | FPU_DC | FPU_DD)
 453
 454 EnumValue
 455 Enum(arc_fpu) String(fpus_fma) Value(FPU_SP | FPU_SC | FPU_SF)
 456
 457 EnumValue
 458 Enum(arc_fpu) String(fpud_fma) Value(FPU_SP | FPU_SC | FPU_SF | FPU_DP | FPU_DC | FPU_DF)
 459
 460 EnumValue
 461 Enum(arc_fpu) String(fpus_all) Value(FPU_SP | FPU_SC | FPU_SF | FPU_SD)
 462
 463 EnumValue
 464 Enum(arc_fpu) String(fpud_all) Value(FPU_SP | FPU_SC | FPU_SF | FPU_SD | FPU_DP | FPU_DC | FPU_DF | FPU_DD)
 465
 466 mtp-regno=
 467 Target RejectNegative Joined UInteger Var(arc_tp_regno) Init(25)
 468 Specify thread pointer register number
 469
 470 mtp-regno=none
 471 Target RejectNegative Var(arc_tp_regno,-1)
 472
 473 mbitops
 474 Target Report Var(TARGET_NPS_BITOPS) Init(TARGET_NPS_BITOPS_DEFAULT)
 475 Enable use of NPS400 bit operations.
 476
 477 mcmem
 478 Target Report Var(TARGET_NPS_CMEM) Init(TARGET_NPS_CMEM_DEFAULT)
 479 Enable use of NPS400 xld/xst extension.
 480
 481 munaligned-access
 482 Target Report Var(unaligned_access) Init(UNALIGNED_ACCESS_DEFAULT)
 483 Enable unaligned word and halfword accesses to packed data.