gcc/config/arc/arc.opt

   1 ; Options for the Synopsys DesignWare ARC port of the compiler
   2 ;
   3 ; Copyright (C) 2005-2015 Free Software Foundation, Inc.
   4 ;
   5 ; This file is part of GCC.
   6 ;
   7 ; GCC is free software; you can redistribute it and/or modify it under
   8 ; the terms of the GNU General Public License as published by the Free
   9 ; Software Foundation; either version 3, or (at your option) any later
  10 ; version.
  11 ;
  12 ; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ; License for more details.
  16 ;
  17 ; You should have received a copy of the GNU General Public License
  18 ; along with GCC; see the file COPYING3.  If not see
  19 ; <http://www.gnu.org/licenses/>.
  20
  21 HeaderInclude
  22 config/arc/arc-opts.h
  23
  24 mbig-endian
  25 Target Report RejectNegative Mask(BIG_ENDIAN)
  26 Compile code for big endian mode.
  27
  28 mlittle-endian
  29 Target Report RejectNegative InverseMask(BIG_ENDIAN)
  30 Compile code for little endian mode.  This is the default.
  31
  32 mno-cond-exec
  33 Target Report RejectNegative Mask(NO_COND_EXEC)
  34 Disable ARCompact specific pass to generate conditional execution instructions.
  35
  36 mA6
  37 Target Report
  38 Generate ARCompact 32-bit code for ARC600 processor.
  39
  40 mARC600
  41 Target Report
  42 Same as -mA6.
  43
  44 mARC601
  45 Target Report
  46 Generate ARCompact 32-bit code for ARC601 processor.
  47
  48 mA7
  49 Target Report
  50 Generate ARCompact 32-bit code for ARC700 processor.
  51
  52 mARC700
  53 Target Report
  54 Same as -mA7.
  55
  56 mmpy-option=
  57 Target RejectNegative Joined UInteger Var(arc_mpy_option) Init(2)
  58 -mmpy-option={0,1,2,3,4,5,6,7,8,9} Compile ARCv2 code with a multiplier design option.  Option 2 is default on.
  59
  60 mdiv-rem
  61 Target Report Mask(DIVREM)
  62 Enable DIV-REM instructions for ARCv2
  63
  64 mcode-density
  65 Target Report Mask(CODE_DENSITY)
  66 Enable code density instructions for ARCv2
  67
  68 mmixed-code
  69 Target Report Mask(MIXED_CODE_SET)
  70 Tweak register allocation to help 16-bit instruction generation.
  71 ; originally this was:
  72 ;Generate ARCompact 16-bit instructions intermixed with 32-bit instructions
  73 ; but we do that without -mmixed-code, too, it's just a different instruction
  74 ; count / size tradeoff.
  75
  76 ; We use an explict definition for the negative form because that is the
  77 ; actually interesting option, and we want that to have its own comment.
  78 mvolatile-cache
  79 Target Report RejectNegative Mask(VOLATILE_CACHE_SET)
  80 Use ordinarily cached memory accesses for volatile references.
  81
  82 mno-volatile-cache
  83 Target Report RejectNegative InverseMask(VOLATILE_CACHE_SET)
  84 Enable cache bypass for volatile references.
  85
  86 mbarrel-shifter
  87 Target Report Mask(BARREL_SHIFTER)
  88 Generate instructions supported by barrel shifter.
  89
  90 mnorm
  91 Target Report Mask(NORM_SET)
  92 Generate norm instruction.
  93
  94 mswap
  95 Target Report Mask(SWAP_SET)
  96 Generate swap instruction.
  97
  98 mmul64
  99 Target Report Mask(MUL64_SET)
 100 Generate mul64 and mulu64 instructions.
 101
 102 mno-mpy
 103 Target Report Mask(NOMPY_SET)
 104 Do not generate mpy instructions for ARC700.
 105
 106 mea
 107 Target Report Mask(EA_SET)
 108 Generate Extended arithmetic instructions.  Currently only divaw, adds, subs and sat16 are supported.
 109
 110 msoft-float
 111 Target Report Mask(0)
 112 Dummy flag. This is the default unless FPX switches are provided explicitly.
 113
 114 mlong-calls
 115 Target Report Mask(LONG_CALLS_SET)
 116 Generate call insns as register indirect calls.
 117
 118 mno-brcc
 119 Target Report Mask(NO_BRCC_SET)
 120 Do no generate BRcc instructions in arc_reorg.
 121
 122 msdata
 123 Target Report InverseMask(NO_SDATA_SET)
 124 Generate sdata references.  This is the default, unless you compile for PIC.
 125
 126 mno-millicode
 127 Target Report Mask(NO_MILLICODE_THUNK_SET)
 128 Do not generate millicode thunks (needed only with -Os).
 129
 130 mspfp
 131 Target Report Mask(SPFP_COMPACT_SET)
 132 FPX: Generate Single Precision FPX (compact) instructions.
 133
 134 mspfp-compact
 135 Target Report Mask(SPFP_COMPACT_SET) MaskExists
 136 FPX: Generate Single Precision FPX (compact) instructions.
 137
 138 mspfp-fast
 139 Target Report Mask(SPFP_FAST_SET)
 140 FPX: Generate Single Precision FPX (fast) instructions.
 141
 142 margonaut
 143 Target Report Mask(ARGONAUT_SET)
 144 FPX: Enable Argonaut ARC CPU Double Precision Floating Point extensions.
 145
 146 mdpfp
 147 Target Report Mask(DPFP_COMPACT_SET)
 148 FPX: Generate Double Precision FPX (compact) instructions.
 149
 150 mdpfp-compact
 151 Target Report Mask(DPFP_COMPACT_SET) MaskExists
 152 FPX: Generate Double Precision FPX (compact) instructions.
 153
 154 mdpfp-fast
 155 Target Report Mask(DPFP_FAST_SET)
 156 FPX: Generate Double Precision FPX (fast) instructions.
 157
 158 mno-dpfp-lrsr
 159 Target Report Mask(DPFP_DISABLE_LRSR)
 160 Disable LR and SR instructions from using FPX extension aux registers.
 161
 162 msimd
 163 Target Report Mask(SIMD_SET)
 164 Enable generation of ARC SIMD instructions via target-specific builtins.
 165
 166 mcpu=
 167 Target RejectNegative Joined Var(arc_cpu) Enum(processor_type) Init(PROCESSOR_NONE)
 168 -mcpu=CPU       Compile code for ARC variant CPU.
 169
 170 Enum
 171 Name(processor_type) Type(enum processor_type)
 172
 173 EnumValue
 174 Enum(processor_type) String(ARC600) Value(PROCESSOR_ARC600)
 175
 176 EnumValue
 177 Enum(processor_type) String(arc600) Value(PROCESSOR_ARC600)
 178
 179 EnumValue
 180 Enum(processor_type) String(ARC601) Value(PROCESSOR_ARC601)
 181
 182 EnumValue
 183 Enum(processor_type) String(arc601) Value(PROCESSOR_ARC601)
 184
 185 EnumValue
 186 Enum(processor_type) String(ARC700) Value(PROCESSOR_ARC700)
 187
 188 EnumValue
 189 Enum(processor_type) String(arc700) Value(PROCESSOR_ARC700)
 190
 191 EnumValue
 192 Enum(processor_type) String(ARCEM) Value(PROCESSOR_ARCEM)
 193
 194 EnumValue
 195 Enum(processor_type) String(arcem) Value(PROCESSOR_ARCEM)
 196
 197 EnumValue
 198 Enum(processor_type) String(ARCHS) Value(PROCESSOR_ARCHS)
 199
 200 EnumValue
 201 Enum(processor_type) String(archs) Value(PROCESSOR_ARCHS)
 202
 203 msize-level=
 204 Target RejectNegative Joined UInteger Var(arc_size_opt_level) Init(-1)
 205 size optimization level: 0:none 1:opportunistic 2: regalloc 3:drop align, -Os.
 206
 207 misize
 208 Target Report PchIgnore Var(TARGET_DUMPISIZE)
 209 Annotate assembler instructions with estimated addresses.
 210
 211 mmultcost=
 212 Target RejectNegative Joined UInteger Var(arc_multcost) Init(-1)
 213 Cost to assume for a multiply instruction, with 4 being equal to a normal insn.
 214
 215 mtune=ARC600
 216 Target RejectNegative Var(arc_tune, TUNE_ARC600)
 217 Tune for ARC600 cpu.
 218
 219 mtune=ARC601
 220 Target RejectNegative Var(arc_tune, TUNE_ARC600)
 221 Tune for ARC601 cpu.
 222
 223 mtune=ARC700
 224 Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_STD)
 225 Tune for ARC700 R4.2 Cpu with standard multiplier block.
 226
 227 mtune=ARC700-xmac
 228 Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_XMAC)
 229 Tune for ARC700 R4.2 Cpu with XMAC block.
 230
 231 mtune=ARC725D
 232 Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_XMAC)
 233 Tune for ARC700 R4.2 Cpu with XMAC block.
 234
 235 mtune=ARC750D
 236 Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_XMAC)
 237 Tune for ARC700 R4.2 Cpu with XMAC block.
 238
 239 mindexed-loads
 240 Target Var(TARGET_INDEXED_LOADS)
 241 Enable the use of indexed loads.
 242
 243 mauto-modify-reg
 244 Target Var(TARGET_AUTO_MODIFY_REG)
 245 Enable the use of pre/post modify with register displacement.
 246
 247 mmul32x16
 248 Target Report Mask(MULMAC_32BY16_SET)
 249 Generate 32x16 multiply and mac instructions.
 250
 251 ; the initializer is supposed to be: Init(REG_BR_PROB_BASE/2) ,
 252 ; alas, basic-block.h is not included in options.c .
 253 munalign-prob-threshold=
 254 Target RejectNegative Joined UInteger Var(arc_unalign_prob_threshold) Init(10000/2)
 255 Set probability threshold for unaligning branches.
 256
 257 mmedium-calls
 258 Target Var(TARGET_MEDIUM_CALLS) Init(TARGET_MMEDIUM_CALLS_DEFAULT)
 259 Don't use less than 25 bit addressing range for calls.
 260
 261 mannotate-align
 262 Target Var(TARGET_ANNOTATE_ALIGN)
 263 Explain what alignment considerations lead to the decision to make an insn short or long.
 264
 265 malign-call
 266 Target Var(TARGET_ALIGN_CALL)
 267 Do alignment optimizations for call instructions.
 268
 269 mRcq
 270 Target Var(TARGET_Rcq)
 271 Enable Rcq constraint handling - most short code generation depends on this.
 272
 273 mRcw
 274 Target Var(TARGET_Rcw)
 275 Enable Rcw constraint handling - ccfsm condexec mostly depends on this.
 276
 277 mearly-cbranchsi
 278 Target Var(TARGET_EARLY_CBRANCHSI)
 279 Enable pre-reload use of cbranchsi pattern.
 280
 281 mbbit-peephole
 282 Target Var(TARGET_BBIT_PEEPHOLE)
 283 Enable bbit peephole2.
 284
 285 mcase-vector-pcrel
 286 Target Var(TARGET_CASE_VECTOR_PC_RELATIVE)
 287 Use pc-relative switch case tables - this enables case table shortening.
 288
 289 mcompact-casesi
 290 Target Var(TARGET_COMPACT_CASESI)
 291 Enable compact casesi pattern.
 292
 293 mq-class
 294 Target Var(TARGET_Q_CLASS)
 295 Enable 'q' instruction alternatives.
 296
 297 mexpand-adddi
 298 Target Var(TARGET_EXPAND_ADDDI)
 299 Expand adddi3 and subdi3 at rtl generation time into add.f / adc etc.
 300
 301
 302 ; Flags used by the assembler, but for which we define preprocessor
 303 ; macro symbols as well.
 304 mcrc
 305 Target Report
 306 Enable variable polynomial CRC extension.
 307
 308 mdsp-packa
 309 Target Report
 310 Enable DSP 3.1 Pack A extensions.
 311
 312 mdvbf
 313 Target Report
 314 Enable dual viterbi butterfly extension.
 315
 316 mmac-d16
 317 Target Report Undocumented
 318
 319 mmac-24
 320 Target Report Undocumented
 321
 322 mtelephony
 323 Target Report RejectNegative
 324 Enable Dual and Single Operand Instructions for Telephony.
 325
 326 mxy
 327 Target Report
 328 Enable XY Memory extension (DSP version 3).
 329
 330 ; ARC700 4.10 extension instructions
 331 mlock
 332 Target Report
 333 Enable Locked Load/Store Conditional extension.
 334
 335 mswape
 336 Target Report
 337 Enable swap byte ordering extension instruction.
 338
 339 mrtsc
 340 Target Report
 341 Enable 64-bit Time-Stamp Counter extension instruction.
 342
 343 mno-epilogue-cfi
 344 Target Report RejectNegative InverseMask(EPILOGUE_CFI)
 345 Disable generation of cfi for epilogues.
 346
 347 mepilogue-cfi
 348 Target RejectNegative Mask(EPILOGUE_CFI)
 349 Enable generation of cfi for epilogues.
 350
 351 EB
 352 Target
 353 Pass -EB option through to linker.
 354
 355 EL
 356 Target
 357 Pass -EL option through to linker.
 358
 359 marclinux
 360 target
 361 Pass -marclinux option through to linker.
 362
 363 marclinux_prof
 364 target
 365 Pass -marclinux_prof option through to linker.
 366
 367 ;; lra is still unproven for ARC, so allow to fall back to reload with -mno-lra.
 368 ;Target InverseMask(NO_LRA)
 369 ; lra still won't allow to configure libgcc; see PR rtl-optimization/55464.
 370 ; so don't enable by default.
 371 mlra
 372 Target Mask(LRA)
 373 Enable lra.
 374
 375 mlra-priority-none
 376 Target RejectNegative Var(arc_lra_priority_tag, ARC_LRA_PRIORITY_NONE)
 377 Don't indicate any priority with TARGET_REGISTER_PRIORITY.
 378
 379 mlra-priority-compact
 380 Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_COMPACT)
 381 Indicate priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY.
 382
 383 mlra-priority-noncompact
 384 Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_NONCOMPACT)
 385 Reduce priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY.
 386
 387 mucb-mcount
 388 Target Report Var(TARGET_UCB_MCOUNT)
 389 instrument with mcount calls as in the ucb code.
 390
 391 ; backward-compatibility aliases, translated by DRIVER_SELF_SPECS
 392
 393 mEA
 394 Target
 395
 396 multcost=
 397 Target RejectNegative Joined
 398
 399 ; Unfortunately, listing the full option name gives us clashes
 400 ; with OPT_opt_name being claimed for both opt_name and opt-name,
 401 ; so we leave out the last character or more.
 402 mbarrel_shifte
 403 Target Joined
 404
 405 mspfp_
 406 Target Joined
 407
 408 mdpfp_
 409 Target Joined
 410
 411 mdsp_pack
 412 Target Joined
 413
 414 mmac_
 415 Target Joined
 416