gcc/config/arc/arcHS.md

   1 ;; DFA scheduling description of the Synopsys DesignWare ARC HS cpu
   2 ;; for GNU C compiler
   3 ;; Copyright (C) 2007-2016 Free Software Foundation, Inc.
   4 ;; Contributor: Claudiu Zissulescu <claudiu.zissulescu@synopsys.com>
   5
   6 ;; This file is part of GCC.
   7
   8 ;; GCC is free software; you can redistribute it and/or modify
   9 ;; it under the terms of the GNU General Public License as published by
  10 ;; the Free Software Foundation; either version 3, or (at your option)
  11 ;; any later version.
  12
  13 ;; GCC is distributed in the hope that it will be useful,
  14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 ;; GNU General Public License for more details.
  17
  18 ;; You should have received a copy of the GNU General Public License
  19 ;; along with GCC; see the file COPYING3.  If not see
  20 ;; <http://www.gnu.org/licenses/>.
  21
  22 (define_automaton "ARCHS")
  23
  24 (define_cpu_unit "hs_issue, hs_ld_st, divrem_hs, mul_hs, x1, x2" "ARCHS")
  25
  26 (define_insn_reservation "hs_data_load" 4
  27   (and (match_test "TARGET_HS")
  28        (eq_attr "type" "load"))
  29   "hs_issue+hs_ld_st,hs_ld_st,nothing*2")
  30
  31 (define_insn_reservation "hs_data_store" 1
  32   (and (match_test "TARGET_HS")
  33        (eq_attr "type" "store"))
  34   "hs_issue+hs_ld_st")
  35
  36 (define_insn_reservation "hs_alu0" 2
  37   (and (match_test "TARGET_HS")
  38        (eq_attr "type" "cc_arith, two_cycle_core, shift, lr, sr"))
  39   "hs_issue+x1,x2")
  40
  41 (define_insn_reservation "hs_alu1" 4
  42   (and (match_test "TARGET_HS")
  43        (eq_attr "type" "move, cmove, unary, binary, compare, misc"))
  44   "hs_issue+x1, nothing*3")
  45
  46 (define_insn_reservation "hs_divrem" 13
  47   (and (match_test "TARGET_HS")
  48        (match_test "TARGET_DIVREM")
  49        (eq_attr "type" "div_rem"))
  50   "hs_issue+divrem_hs, (divrem_hs)*12")
  51
  52 (define_insn_reservation "hs_mul" 3
  53   (and (match_test "TARGET_HS")
  54        (eq_attr "type" "mul16_em, multi, umulti"))
  55   "hs_issue+mul_hs, nothing*3")
  56
  57 ;; BYPASS EALU ->
  58 (define_bypass 1 "hs_alu0" "hs_divrem")
  59 (define_bypass 1 "hs_alu0" "hs_mul")
  60
  61 ;; BYPASS BALU ->
  62 (define_bypass 1 "hs_alu1" "hs_alu1")
  63 (define_bypass 1 "hs_alu1" "hs_data_store" "store_data_bypass_p")
  64
  65 ;; BYPASS LD ->
  66 (define_bypass 1 "hs_data_load" "hs_alu1")
  67 (define_bypass 3 "hs_data_load" "hs_divrem")
  68 (define_bypass 3 "hs_data_load" "hs_data_load")
  69 (define_bypass 3 "hs_data_load" "hs_mul")
  70 (define_bypass 1 "hs_data_load" "hs_data_store" "store_data_bypass_p")
  71
  72 ;; BYPASS MPY ->
  73 ;;(define_bypass 3 "hs_mul" "hs_mul")
  74 (define_bypass 1 "hs_mul" "hs_alu1")
  75 (define_bypass 3 "hs_mul" "hs_divrem")
  76 (define_bypass 1 "hs_mul" "hs_data_store" "store_data_bypass_p")