gcc/config/arc/constraints.md

   1 ;; Constraint definitions for Synopsys DesignWare ARC.
   2 ;; Copyright (C) 2007-2019 Free Software Foundation, Inc.
   3 ;;
   4 ;; This file is part of GCC.
   5 ;;
   6 ;; GCC is free software; you can redistribute it and/or modify
   7 ;; it under the terms of the GNU General Public License as published by
   8 ;; the Free Software Foundation; either version 3, or (at your option)
   9 ;; any later version.
  10 ;;
  11 ;; GCC is distributed in the hope that it will be useful,
  12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ;; GNU General Public License for more details.
  15 ;;
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING3.  If not see
  18 ;; <http://www.gnu.org/licenses/>.
  19
  20 ;; Register constraints
  21
  22 ; Most instructions accept arbitrary core registers for their inputs, even
  23 ; if the core register in question cannot be written to, like the multiply
  24 ; result registers of ARC600.
  25 ; First, define a class for core registers that can be read cheaply.  This
  26 ; is most or all core registers for ARC600, but only r0-r31 for ARC700
  27 (define_register_constraint "c" "GENERAL_REGS"
  28   "Legacy, core register @code{r0}-@code{r31}, @code{ap},@code{pcl}")
  29
  30 ; All core regs - e.g. for when we must have a way to reload a register.
  31 (define_register_constraint "Rac" "GENERAL_REGS"
  32   "Legacy, core register @code{r0}-@code{r60}, @code{ap},@code{pcl}")
  33
  34 ; Some core registers (.e.g lp_count) aren't general registers because they
  35 ; can't be used as the destination of a multi-cycle operation like
  36 ; load and/or multiply, yet they are still writable in the sense that
  37 ; register-register moves and single-cycle arithmetic (e.g "add", "and",
  38 ; but not "mpy") can write to them.
  39 (define_register_constraint "w" "GENERAL_REGS"
  40   "Legacy, writable core register: @code{r0}-@code{r31}, @code{r60},
  41    nonfixed core register")
  42
  43 (define_register_constraint "W" "GENERAL_REGS"
  44   "Legacy, writable core register except @code{LP_COUNT} (@code{r60}):
  45    @code{r0}-@code{r31}, nonfixed core register")
  46
  47 (define_constraint "l"
  48   "@internal
  49    Loop count register @code{r60}"
  50   (and (match_code "reg")
  51        (match_test "REGNO (op) == LP_COUNT")))
  52
  53 (define_register_constraint "x" "R0_REGS"
  54   "@code{R0} register.")
  55
  56 (define_register_constraint "q" "TARGET_Q_CLASS ? ARCOMPACT16_REGS : NO_REGS"
  57   "Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3},
  58    @code{r12}-@code{r15}")
  59
  60 ; NPS400 bitfield instructions require registers from the r0-r3,r12-r15
  61 ; range, and thus we need a register class and constraint that works
  62 ; independently of size optimization.
  63 (define_register_constraint
  64  "Rrq" "TARGET_RRQ_CLASS ? ARCOMPACT16_REGS : NO_REGS"
  65   "Registers usable in NPS400 bitfield instructions: @code{r0}-@code{r3},
  66    @code{r12}-@code{r15}")
  67
  68 (define_register_constraint "D" "DOUBLE_REGS"
  69   "ARC FPX (dpfp) 64-bit registers. @code{D0}, @code{D1}")
  70
  71 (define_register_constraint "d" "SIMD_DMA_CONFIG_REGS"
  72   "@internal
  73    ARC SIMD DMA configuration registers @code{di0}-@code{di7},
  74    @code{do0}-@code{do7}")
  75
  76 (define_register_constraint "v" "SIMD_VR_REGS"
  77   "ARC SIMD 128-bit registers @code{VR0}-@code{VR23}")
  78
  79 ; We could allow call-saved registers for sibling calls if we restored them
  80 ; in the delay slot of the call.  However, that would not allow to adjust the
  81 ; stack pointer afterwards, so the call-saved register would have to be
  82 ; restored from a call-used register that was just loaded with the value
  83 ; before.  So sticking to call-used registers for sibcalls will likely
  84 ; generate better code overall.
  85 (define_register_constraint "Rsc" "SIBCALL_REGS"
  86   "@internal
  87    Sibling call register")
  88
  89 ;; Integer constraints
  90
  91 (define_constraint "I"
  92   "@internal
  93    A signed 12-bit integer constant."
  94   (and (match_code "const_int")
  95        (match_test "SIGNED_INT12 (ival)")))
  96
  97 (define_constraint "K"
  98   "@internal
  99    A 3-bit unsigned integer constant"
 100   (and (match_code "const_int")
 101        (match_test "UNSIGNED_INT3 (ival)")))
 102
 103 (define_constraint "L"
 104   "@internal
 105    A 6-bit unsigned integer constant"
 106   (and (match_code "const_int")
 107        (match_test "UNSIGNED_INT6 (ival)")))
 108
 109 (define_constraint "CnL"
 110   "@internal
 111    One's complement of a 6-bit unsigned integer constant"
 112   (and (match_code "const_int")
 113        (match_test "UNSIGNED_INT6 (~ival)")))
 114
 115 (define_constraint "CmL"
 116   "@internal
 117    Two's complement of a 6-bit unsigned integer constant"
 118   (and (match_code "const_int")
 119        (match_test "UNSIGNED_INT6 (-ival)")))
 120
 121 (define_constraint "C16"
 122   "@internal
 123    A 16-bit signed integer constant"
 124   (and (match_code "const_int")
 125        (match_test "SIGNED_INT16 (ival)")))
 126
 127 (define_constraint "M"
 128   "@internal
 129    A 5-bit unsigned integer constant"
 130   (and (match_code "const_int")
 131        (match_test "UNSIGNED_INT5 (ival)")))
 132
 133 (define_constraint "N"
 134   "@internal
 135    Integer constant 1"
 136   (and (match_code "const_int")
 137        (match_test "IS_ONE (ival)")))
 138
 139 (define_constraint "O"
 140   "@internal
 141    A 7-bit unsigned integer constant"
 142   (and (match_code "const_int")
 143        (match_test "UNSIGNED_INT7 (ival)")))
 144
 145 (define_constraint "P"
 146   "@internal
 147    An 8-bit unsigned integer constant"
 148   (and (match_code "const_int")
 149        (match_test "UNSIGNED_INT8 (ival)")))
 150
 151 (define_constraint "C_0"
 152   "@internal
 153    Zero"
 154   (and (match_code "const_int")
 155        (match_test "ival == 0")))
 156
 157 (define_constraint "Cn0"
 158   "@internal
 159    Negative or zero"
 160   (and (match_code "const_int")
 161        (match_test "ival <= 0")))
 162
 163 (define_constraint "Cca"
 164   "@internal
 165    Conditional or three-address add / sub constant"
 166   (and (match_code "const_int")
 167        (match_test "ival == (HOST_WIDE_INT)(HOST_WIDE_INT_M1U << 31)
 168                     || (ival >= -0x1f8 && ival <= 0x1f8
 169                         && ((ival >= 0 ? ival : -ival)
 170                             <= 0x3f * (ival & -ival)))")))
 171
 172 ; intersection of "O" and "Cca".
 173 (define_constraint "CL2"
 174   "@internal
 175    A 6-bit unsigned integer constant times 2"
 176   (and (match_code "const_int")
 177        (match_test "!(ival & ~126)")))
 178
 179 (define_constraint "CM4"
 180   "@internal
 181    A 5-bit unsigned integer constant times 4"
 182   (and (match_code "const_int")
 183        (match_test "!(ival & ~124)")))
 184
 185 (define_constraint "Csp"
 186   "@internal
 187    A valid stack pointer offset for a short add"
 188   (and (match_code "const_int")
 189        (match_test "!(ival & ~124) || !(-ival & ~124)")))
 190
 191 (define_constraint "C2a"
 192   "@internal
 193    Unconditional two-address add / sub constant"
 194   (and (match_code "const_int")
 195        (match_test "ival == (HOST_WIDE_INT) (HOST_WIDE_INT_M1U << 31)
 196                     || (ival >= -0x4000 && ival <= 0x4000
 197                         && ((ival >= 0 ? ival : -ival)
 198                             <= 0x7ff * (ival & -ival)))")))
 199
 200 (define_constraint "C0p"
 201  "@internal
 202   power of two"
 203   (and (match_code "const_int")
 204        (match_test "IS_POWEROF2_P (ival)")))
 205
 206 (define_constraint "C1p"
 207  "@internal
 208   constant such that x+1 is a power of two, and x != 0"
 209   (and (match_code "const_int")
 210        (match_test "ival && IS_POWEROF2_P (ival + 1)")))
 211
 212 (define_constraint "C2p"
 213  "@internal
 214   constant such that (~x)+1 is a power of two, and x < -1"
 215   (and (match_code "const_int")
 216        (match_test "TARGET_V2
 217                     && (ival < -1)
 218                     && IS_POWEROF2_P ((~ival) + 1)")))
 219
 220 (define_constraint "C3p"
 221  "@internal
 222   constant int used to select xbfu a,b,u6 instruction.  The values accepted are 1 and 2."
 223   (and (match_code "const_int")
 224        (match_test "((ival == 1) || (ival == 2))")))
 225
 226 (define_constraint "Ccp"
 227  "@internal
 228   constant such that ~x (one's Complement) is a power of two"
 229   (and (match_code "const_int")
 230        (match_test "IS_POWEROF2_P (~ival)")))
 231
 232 (define_constraint "Cux"
 233  "@internal
 234   constant such that AND gives an unsigned extension"
 235   (and (match_code "const_int")
 236        (match_test "ival == 0xff || ival == 0xffff")))
 237
 238 (define_constraint "Chs"
 239  "@internal
 240   constant for a highpart that can be checked with a shift (asr.f 0,rn,m)"
 241   (and (match_code "const_int")
 242        (match_test "IS_POWEROF2_P (-ival)")
 243        (match_test "TARGET_BARREL_SHIFTER")))
 244
 245 (define_constraint "Clo"
 246  "@internal
 247   constant that fits into 16 lower bits, for movl"
 248   (and (match_code "const_int")
 249        (match_test "TARGET_NPS_BITOPS")
 250        (match_test "(ival & ~0xffffU) == 0")))
 251
 252 (define_constraint "Chi"
 253  "@internal
 254   constant that fits into 16 higher bits, for movh_i"
 255   (and (match_code "const_int")
 256        (match_test "TARGET_NPS_BITOPS")
 257        (match_test "trunc_int_for_mode (ival >> 16, HImode) << 16 == ival")))
 258
 259 (define_constraint "Cbf"
 260  "@internal
 261   a mask for a bit field, for AND using movb_i"
 262   (and (match_code "const_int")
 263        (match_test "TARGET_NPS_BITOPS")
 264        (match_test "IS_POWEROF2_OR_0_P (ival + (ival & -ival))")))
 265
 266 (define_constraint "Cbn"
 267  "@internal
 268   a constant integer, valid only if TARGET_NPS_BITOPS is true"
 269   (and (match_code "const_int")
 270        (match_test "TARGET_NPS_BITOPS")))
 271
 272 (define_constraint "C18"
 273  "@internal
 274   1,2,4 or 8"
 275   (and (match_code "const_int")
 276        (match_test "ival == 1 || ival == 2 || ival == 4 || ival == 8")))
 277
 278 (define_constraint "Crr"
 279  "@internal
 280   constant that can be loaded with ror b,u6"
 281   (and (match_code "const_int")
 282        (match_test "(ival & ~0x8000001f) == 0 && !arc_ccfsm_cond_exec_p ()")))
 283
 284 (define_constraint "Cbi"
 285  "@internal
 286   constant that can be loaded with movbi.cl"
 287   (and (match_code "const_int")
 288        (match_test "TARGET_NPS_BITOPS")
 289        (match_test "!ival
 290                     || ((ival & 0xffffffffUL) >> exact_log2 (ival & -ival)
 291                         <= 0xff)")))
 292
 293 ;; Floating-point constraints
 294
 295 (define_constraint "G"
 296   "@internal
 297    A 32-bit constant double value"
 298   (and (match_code "const_double")
 299        (match_test "arc_double_limm_p (op)")))
 300
 301 (define_constraint "H"
 302   "@internal
 303    All const_double values (including 64-bit values)"
 304   (and (match_code "const_double")
 305        (match_test "1")))
 306
 307 (define_constraint "CfZ"
 308   "@internal
 309    Match a floating-point zero"
 310   (and (match_code "const_double")
 311        (match_test "op == CONST0_RTX (SFmode)")))
 312
 313 ;; Memory constraints
 314 (define_memory_constraint "T"
 315   "@internal
 316    A valid memory operand for ARCompact load instructions"
 317   (and (match_code "mem")
 318        (match_test "compact_memory_operand_p (op, mode, false, false)")))
 319
 320 (define_memory_constraint "Uts"
 321   "@internal
 322    A valid memory operand for ARCompact load instructions scaled"
 323   (and (match_code "mem")
 324        (match_test "compact_memory_operand_p (op, mode, false, TARGET_CODE_DENSITY)")))
 325
 326 (define_memory_constraint "S"
 327   "@internal
 328    A valid memory operand for ARCompact store instructions"
 329   (and (match_code "mem")
 330        (match_test "compact_store_memory_operand (op, VOIDmode)")))
 331
 332 (define_memory_constraint "Uex"
 333   "@internal
 334    A valid memory operand for limm-free extend instructions"
 335   (and (match_code "mem")
 336        (match_test "!cmem_address (XEXP (op, 0), SImode)")
 337        (not (match_operand 0 "long_immediate_loadstore_operand"))))
 338
 339 (define_memory_constraint "Usd"
 340    "@internal
 341     A valid _small-data_ memory operand for ARCompact instructions"
 342    (and (match_code "mem")
 343         (match_test "compact_sda_memory_operand (op, VOIDmode, true)")))
 344
 345 ; Usc constant is only used for storing long constants, hence we can
 346 ; have only [b,s9], and [b] types of addresses.
 347 (define_memory_constraint "Usc"
 348   "@internal
 349    A valid memory operand for storing constants"
 350   (and (match_code "mem")
 351        (match_test "!CONSTANT_P (XEXP (op,0))")))
 352
 353 (define_constraint "Us<"
 354   "@internal
 355    Stack pre-decrement"
 356   (and (match_code "mem")
 357        (match_test "GET_CODE (XEXP (op, 0)) == PRE_DEC")
 358        (match_test "REG_P (XEXP (XEXP (op, 0), 0))")
 359        (match_test "REGNO (XEXP (XEXP (op, 0), 0)) == SP_REG")))
 360
 361 (define_constraint "Us>"
 362   "@internal
 363    Stack post-increment"
 364   (and (match_code "mem")
 365        (match_test "GET_CODE (XEXP (op, 0)) == POST_INC")
 366        (match_test "REG_P (XEXP (XEXP (op, 0), 0))")
 367        (match_test "REGNO (XEXP (XEXP (op, 0), 0)) == SP_REG")))
 368
 369 (define_constraint "Ucm"
 370   "@internal
 371   cmem access"
 372   (and (match_code "mem")
 373        (match_test "TARGET_NPS_CMEM && cmem_address (XEXP (op, 0), VOIDmode)")))
 374
 375 ;; General constraints
 376
 377 (define_constraint "Cbr"
 378   "Branch destination"
 379   (ior (and (match_code "symbol_ref")
 380             (match_test "!arc_is_longcall_p (op)"))
 381        (match_code "label_ref")))
 382
 383 (define_constraint "Cbp"
 384   "predicable branch/call destination"
 385   (ior (and (match_code "symbol_ref")
 386             (match_test "arc_is_shortcall_p (op)"))
 387        (match_code "label_ref")))
 388
 389 (define_constraint "Cji"
 390   "JLI call"
 391   (and (match_code "symbol_ref")
 392        (match_test "TARGET_CODE_DENSITY")
 393        (match_test "arc_is_jli_call_p (op)")))
 394
 395 (define_constraint "Csc"
 396   "Secure call"
 397   (and (match_code "symbol_ref")
 398        (match_test "TARGET_CODE_DENSITY")
 399        (match_test "TARGET_EM")
 400        (match_test "arc_is_secure_call_p (op)")))
 401
 402 (define_constraint "Cpc"
 403   "pc-relative constant"
 404   (match_test "arc_legitimate_pic_addr_p (op)"))
 405
 406 (define_constraint "Clb"
 407   "label"
 408   (and (match_code "label_ref")
 409        (match_test "arc_text_label (as_a <rtx_insn *> (XEXP (op, 0)))")))
 410
 411 (define_constraint "Cal"
 412   "constant for arithmetic/logical operations"
 413   (match_test "immediate_operand (op, VOIDmode) && !arc_legitimate_pic_addr_p (op)"))
 414
 415 (define_constraint "C32"
 416   "32 bit constant for arithmetic/logical operations"
 417   (match_test "immediate_operand (op, VOIDmode)
 418                && !arc_legitimate_pic_addr_p (op)
 419                && !satisfies_constraint_I (op)"))
 420
 421 (define_constraint "Csz"
 422   "a 32 bit constant avoided when compiling for size."
 423   (match_test "immediate_operand (op, VOIDmode)
 424                && !arc_legitimate_pic_addr_p (op)
 425                && !(satisfies_constraint_I (op) && optimize_size)"))
 426
 427 ; Note that the 'cryptic' register constraints will not make reload use the
 428 ; associated class to reload into, but this will not penalize reloading of any
 429 ; other operands, or using an alternate part of the same alternative.
 430
 431 ; Rcq is different in three important ways from a register class constraint:
 432 ; - It does not imply a register class, hence reload will not use it to drive
 433 ;   reloads.
 434 ; - It matches even when there is no register class to describe its accepted
 435 ;   set; not having such a set again lessens the impact on register allocation.
 436 ; - It won't match when the instruction is conditionalized by the ccfsm.
 437 (define_constraint "Rcq"
 438   "@internal
 439    Cryptic q - for short insn generation while not affecting register allocation
 440    Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3},
 441    @code{r12}-@code{r15}"
 442   (and (match_code "reg")
 443        (match_test "TARGET_Rcq
 444                     && !arc_ccfsm_cond_exec_p ()
 445                     && IN_RANGE (REGNO (op) ^ 4, 4, 11)")))
 446
 447 ; If we need a reload, we generally want to steer reload to use three-address
 448 ; alternatives in preference of two-address alternatives, unless the
 449 ; three-address alternative introduces a LIMM that is unnecessary for the
 450 ; two-address alternative.
 451 (define_constraint "Rcw"
 452   "@internal
 453    Cryptic w - for use in early alternatives with matching constraint"
 454   (and (match_code "reg")
 455        (match_test
 456         "TARGET_Rcw
 457          && REGNO (op) < FIRST_PSEUDO_REGISTER
 458          && TEST_HARD_REG_BIT (reg_class_contents[GENERAL_REGS],
 459                                REGNO (op))")))
 460
 461 (define_constraint "Rcr"
 462   "@internal
 463    Cryptic r - for use in early alternatives with matching constraint"
 464   (and (match_code "reg")
 465        (match_test
 466         "TARGET_Rcw
 467          && REGNO (op) < FIRST_PSEUDO_REGISTER
 468          && TEST_HARD_REG_BIT (reg_class_contents[GENERAL_REGS],
 469                                REGNO (op))")))
 470
 471 (define_constraint "Rcb"
 472   "@internal
 473    Stack Pointer register @code{r28} - do not reload into its class"
 474   (and (match_code "reg")
 475        (match_test "REGNO (op) == 28")))
 476
 477 (define_constraint "Rck"
 478   "@internal
 479    blink (usful for push_s / pop_s)"
 480   (and (match_code "reg")
 481        (match_test "REGNO (op) == 31")))
 482
 483 (define_constraint "Rs5"
 484   "@internal
 485    sibcall register - only allow one of the five available 16 bit isnsn.
 486    Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3},
 487    @code{r12}"
 488   (and (match_code "reg")
 489        (match_test "!arc_ccfsm_cond_exec_p ()")
 490        (ior (match_test "(unsigned) REGNO (op) <= 3")
 491             (match_test "REGNO (op) == 12"))))
 492
 493 (define_constraint "Rcc"
 494   "@internal
 495   Condition Codes"
 496   (and (match_code "reg") (match_test "cc_register (op, VOIDmode)")))
 497
 498
 499 (define_constraint "Q"
 500   "@internal
 501    Integer constant zero"
 502   (and (match_code "const_int")
 503        (match_test "IS_ZERO (ival)")))
 504
 505 (define_constraint "Cm1"
 506   "@internal
 507    Integer signed constant in the interval [-1,6]"
 508   (and (match_code "const_int")
 509        (match_test "(ival >= -1) && (ival <=6)")
 510        (match_test "TARGET_V2")))
 511
 512 (define_constraint "Cm2"
 513   "@internal
 514    A signed 9-bit integer constant."
 515   (and (match_code "const_int")
 516        (match_test "(ival >= -256) && (ival <=255)")))
 517
 518 (define_constraint "Cm3"
 519   "@internal
 520    A signed 6-bit integer constant."
 521   (and (match_code "const_int")
 522        (match_test "(ival >= -32) && (ival <=31)")
 523        (match_test "TARGET_V2")))
 524
 525 (define_constraint "C62"
 526   "@internal
 527    An unsigned 6-bit integer constant, up to 62."
 528   (and (match_code "const_int")
 529        (match_test "UNSIGNED_INT6 (ival - 1)")))
 530
 531 ;; Memory constraint used for atomic ops.
 532 (define_memory_constraint "ATO"
 533   "A memory with only a base register"
 534   (match_operand 0 "mem_noofs_operand"))
 535
 536 (define_constraint "J12"
 537   "@internal
 538    An unsigned 12-bit integer constant."
 539   (and (match_code "const_int")
 540        (match_test "UNSIGNED_INT12 (ival)")))
 541
 542 (define_constraint "J16"
 543   "@internal
 544    An unsigned 16-bit integer constant"
 545   (and (match_code "const_int")
 546        (match_test "UNSIGNED_INT16 (ival)")))
 547
 548 ; Memory addresses suited for code density load ops
 549 (define_memory_constraint "Ucd"
 550   "@internal
 551    A valid memory operand for use with code density load ops"
 552   (and (match_code "mem")
 553        (match_test "compact_memory_operand_p (op, mode, true, false)")
 554        (match_test "TARGET_V2")))
 555
 556 (define_register_constraint "h"
 557   "TARGET_V2 ? AC16_H_REGS : NO_REGS"
 558   "5-bit h register set except @code{r30} and @code{r29}:
 559    @code{r0}-@code{r31}, nonfixed core register")
 560
 561 ; Code density registers
 562 (define_register_constraint "Rcd"
 563   "TARGET_CODE_DENSITY ? R0R3_CD_REGS : NO_REGS"
 564   "@internal
 565    core register @code{r0}-@code{r3}")
 566
 567 (define_register_constraint "Rsd"
 568   "TARGET_CODE_DENSITY ? R0R1_CD_REGS : NO_REGS"
 569   "@internal
 570    core register @code{r0}-@code{r1}")
 571
 572 (define_register_constraint "Rzd"
 573   "TARGET_CODE_DENSITY ? R0_REGS : NO_REGS"
 574   "@internal
 575    @code{r0} register for code density instructions.")