gcc/config/arc/constraints.md

   1 ;; Constraint definitions for Synopsys DesignWare ARC.
   2 ;; Copyright (C) 2007-2018 Free Software Foundation, Inc.
   3 ;;
   4 ;; This file is part of GCC.
   5 ;;
   6 ;; GCC is free software; you can redistribute it and/or modify
   7 ;; it under the terms of the GNU General Public License as published by
   8 ;; the Free Software Foundation; either version 3, or (at your option)
   9 ;; any later version.
  10 ;;
  11 ;; GCC is distributed in the hope that it will be useful,
  12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ;; GNU General Public License for more details.
  15 ;;
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING3.  If not see
  18 ;; <http://www.gnu.org/licenses/>.
  19
  20 ;; Register constraints
  21
  22 ; Most instructions accept arbitrary core registers for their inputs, even
  23 ; if the core register in question cannot be written to, like the multiply
  24 ; result registers of ARC600.
  25 ; First, define a class for core registers that can be read cheaply.  This
  26 ; is most or all core registers for ARC600, but only r0-r31 for ARC700
  27 (define_register_constraint "c" "CHEAP_CORE_REGS"
  28   "core register @code{r0}-@code{r31}, @code{ap},@code{pcl}")
  29
  30 ; All core regs - e.g. for when we must have a way to reload a register.
  31 (define_register_constraint "Rac" "ALL_CORE_REGS"
  32   "core register @code{r0}-@code{r60}, @code{ap},@code{pcl}")
  33
  34 ; Some core registers (.e.g lp_count) aren't general registers because they
  35 ; can't be used as the destination of a multi-cycle operation like
  36 ; load and/or multiply, yet they are still writable in the sense that
  37 ; register-register moves and single-cycle arithmetic (e.g "add", "and",
  38 ; but not "mpy") can write to them.
  39 (define_register_constraint "w" "WRITABLE_CORE_REGS"
  40   "writable core register: @code{r0}-@code{r31}, @code{r60}, nonfixed core register")
  41
  42 (define_register_constraint "W" "MPY_WRITABLE_CORE_REGS"
  43   "writable core register except @code{LP_COUNT} (@code{r60}): @code{r0}-@code{r31}, nonfixed core register")
  44
  45 (define_register_constraint "l" "LPCOUNT_REG"
  46   "@internal
  47    Loop count register @code{r60}")
  48
  49 (define_register_constraint "x" "R0_REGS"
  50   "@code{R0} register.")
  51
  52 (define_register_constraint "Rgp" "GP_REG"
  53   "@internal
  54    Global Pointer register @code{r26}")
  55
  56 (define_register_constraint "f" "FP_REG"
  57   "@internal
  58    Frame Pointer register @code{r27}")
  59
  60 (define_register_constraint "b" "SP_REGS"
  61   "@internal
  62    Stack Pointer register @code{r28}")
  63
  64 (define_register_constraint "k" "LINK_REGS"
  65   "@internal
  66    Link Registers @code{ilink1}:@code{r29}, @code{ilink2}:@code{r30},
  67    @code{blink}:@code{r31},")
  68
  69 (define_register_constraint "q" "TARGET_Q_CLASS ? ARCOMPACT16_REGS : NO_REGS"
  70   "Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3},
  71    @code{r12}-@code{r15}")
  72
  73 ; NPS400 bitfield instructions require registers from the r0-r3,r12-r15
  74 ; range, and thus we need a register class and constraint that works
  75 ; independently of size optimization.
  76 (define_register_constraint
  77  "Rrq" "TARGET_RRQ_CLASS ? ARCOMPACT16_REGS : NO_REGS"
  78   "Registers usable in NPS400 bitfield instructions: @code{r0}-@code{r3},
  79    @code{r12}-@code{r15}")
  80
  81 (define_register_constraint "e" "AC16_BASE_REGS"
  82   "Registers usable as base-regs of memory addresses in ARCompact 16-bit memory
  83    instructions: @code{r0}-@code{r3}, @code{r12}-@code{r15}, @code{sp}")
  84
  85 (define_register_constraint "D" "DOUBLE_REGS"
  86   "ARC FPX (dpfp) 64-bit registers. @code{D0}, @code{D1}")
  87
  88 (define_register_constraint "d" "SIMD_DMA_CONFIG_REGS"
  89   "@internal
  90    ARC SIMD DMA configuration registers @code{di0}-@code{di7},
  91    @code{do0}-@code{do7}")
  92
  93 (define_register_constraint "v" "SIMD_VR_REGS"
  94   "ARC SIMD 128-bit registers @code{VR0}-@code{VR23}")
  95
  96 ; We could allow call-saved registers for sibling calls if we restored them
  97 ; in the delay slot of the call.  However, that would not allow to adjust the
  98 ; stack pointer afterwards, so the call-saved register would have to be
  99 ; restored from a call-used register that was just loaded with the value
 100 ; before.  So sticking to call-used registers for sibcalls will likely
 101 ; generate better code overall.
 102 (define_register_constraint "Rsc" "SIBCALL_REGS"
 103   "@internal
 104    Sibling call register")
 105
 106 ;; Integer constraints
 107
 108 (define_constraint "I"
 109   "@internal
 110    A signed 12-bit integer constant."
 111   (and (match_code "const_int")
 112        (match_test "SIGNED_INT12 (ival)")))
 113
 114 (define_constraint "K"
 115   "@internal
 116    A 3-bit unsigned integer constant"
 117   (and (match_code "const_int")
 118        (match_test "UNSIGNED_INT3 (ival)")))
 119
 120 (define_constraint "L"
 121   "@internal
 122    A 6-bit unsigned integer constant"
 123   (and (match_code "const_int")
 124        (match_test "UNSIGNED_INT6 (ival)")))
 125
 126 (define_constraint "CnL"
 127   "@internal
 128    One's complement of a 6-bit unsigned integer constant"
 129   (and (match_code "const_int")
 130        (match_test "UNSIGNED_INT6 (~ival)")))
 131
 132 (define_constraint "CmL"
 133   "@internal
 134    Two's complement of a 6-bit unsigned integer constant"
 135   (and (match_code "const_int")
 136        (match_test "UNSIGNED_INT6 (-ival)")))
 137
 138 (define_constraint "C16"
 139   "@internal
 140    A 16-bit signed integer constant"
 141   (and (match_code "const_int")
 142        (match_test "SIGNED_INT16 (ival)")))
 143
 144 (define_constraint "M"
 145   "@internal
 146    A 5-bit unsigned integer constant"
 147   (and (match_code "const_int")
 148        (match_test "UNSIGNED_INT5 (ival)")))
 149
 150 (define_constraint "N"
 151   "@internal
 152    Integer constant 1"
 153   (and (match_code "const_int")
 154        (match_test "IS_ONE (ival)")))
 155
 156 (define_constraint "O"
 157   "@internal
 158    A 7-bit unsigned integer constant"
 159   (and (match_code "const_int")
 160        (match_test "UNSIGNED_INT7 (ival)")))
 161
 162 (define_constraint "P"
 163   "@internal
 164    An 8-bit unsigned integer constant"
 165   (and (match_code "const_int")
 166        (match_test "UNSIGNED_INT8 (ival)")))
 167
 168 (define_constraint "C_0"
 169   "@internal
 170    Zero"
 171   (and (match_code "const_int")
 172        (match_test "ival == 0")))
 173
 174 (define_constraint "Cn0"
 175   "@internal
 176    Negative or zero"
 177   (and (match_code "const_int")
 178        (match_test "ival <= 0")))
 179
 180 (define_constraint "Cca"
 181   "@internal
 182    Conditional or three-address add / sub constant"
 183   (and (match_code "const_int")
 184        (match_test "ival == (HOST_WIDE_INT)(HOST_WIDE_INT_M1U << 31)
 185                     || (ival >= -0x1f8 && ival <= 0x1f8
 186                         && ((ival >= 0 ? ival : -ival)
 187                             <= 0x3f * (ival & -ival)))")))
 188
 189 ; intersection of "O" and "Cca".
 190 (define_constraint "CL2"
 191   "@internal
 192    A 6-bit unsigned integer constant times 2"
 193   (and (match_code "const_int")
 194        (match_test "!(ival & ~126)")))
 195
 196 (define_constraint "CM4"
 197   "@internal
 198    A 5-bit unsigned integer constant times 4"
 199   (and (match_code "const_int")
 200        (match_test "!(ival & ~124)")))
 201
 202 (define_constraint "Csp"
 203   "@internal
 204    A valid stack pointer offset for a short add"
 205   (and (match_code "const_int")
 206        (match_test "!(ival & ~124) || !(-ival & ~124)")))
 207
 208 (define_constraint "C2a"
 209   "@internal
 210    Unconditional two-address add / sub constant"
 211   (and (match_code "const_int")
 212        (match_test "ival == (HOST_WIDE_INT) (HOST_WIDE_INT_M1U << 31)
 213                     || (ival >= -0x4000 && ival <= 0x4000
 214                         && ((ival >= 0 ? ival : -ival)
 215                             <= 0x7ff * (ival & -ival)))")))
 216
 217 (define_constraint "C0p"
 218  "@internal
 219   power of two"
 220   (and (match_code "const_int")
 221        (match_test "IS_POWEROF2_P (ival)")))
 222
 223 (define_constraint "C1p"
 224  "@internal
 225   constant such that x+1 is a power of two, and x != 0"
 226   (and (match_code "const_int")
 227        (match_test "ival && IS_POWEROF2_P (ival + 1)")))
 228
 229 (define_constraint "C2p"
 230  "@internal
 231   constant such that (~x)+1 is a power of two, and x < -1"
 232   (and (match_code "const_int")
 233        (match_test "TARGET_V2
 234                     && (ival < -1)
 235                     && IS_POWEROF2_P ((~ival) + 1)")))
 236
 237 (define_constraint "C3p"
 238  "@internal
 239   constant int used to select xbfu a,b,u6 instruction.  The values accepted are 1 and 2."
 240   (and (match_code "const_int")
 241        (match_test "((ival == 1) || (ival == 2))")))
 242
 243 (define_constraint "Ccp"
 244  "@internal
 245   constant such that ~x (one's Complement) is a power of two"
 246   (and (match_code "const_int")
 247        (match_test "IS_POWEROF2_P (~ival)")))
 248
 249 (define_constraint "Cux"
 250  "@internal
 251   constant such that AND gives an unsigned extension"
 252   (and (match_code "const_int")
 253        (match_test "ival == 0xff || ival == 0xffff")))
 254
 255 (define_constraint "Chs"
 256  "@internal
 257   constant for a highpart that can be checked with a shift (asr.f 0,rn,m)"
 258   (and (match_code "const_int")
 259        (match_test "IS_POWEROF2_P (-ival)")
 260        (match_test "TARGET_BARREL_SHIFTER")))
 261
 262 (define_constraint "Clo"
 263  "@internal
 264   constant that fits into 16 lower bits, for movl"
 265   (and (match_code "const_int")
 266        (match_test "TARGET_NPS_BITOPS")
 267        (match_test "(ival & ~0xffffU) == 0")))
 268
 269 (define_constraint "Chi"
 270  "@internal
 271   constant that fits into 16 higher bits, for movh_i"
 272   (and (match_code "const_int")
 273        (match_test "TARGET_NPS_BITOPS")
 274        (match_test "trunc_int_for_mode (ival >> 16, HImode) << 16 == ival")))
 275
 276 (define_constraint "Cbf"
 277  "@internal
 278   a mask for a bit field, for AND using movb_i"
 279   (and (match_code "const_int")
 280        (match_test "TARGET_NPS_BITOPS")
 281        (match_test "IS_POWEROF2_OR_0_P (ival + (ival & -ival))")))
 282
 283 (define_constraint "Cbn"
 284  "@internal
 285   a constant integer, valid only if TARGET_NPS_BITOPS is true"
 286   (and (match_code "const_int")
 287        (match_test "TARGET_NPS_BITOPS")))
 288
 289 (define_constraint "C18"
 290  "@internal
 291   1,2,4 or 8"
 292   (and (match_code "const_int")
 293        (match_test "ival == 1 || ival == 2 || ival == 4 || ival == 8")))
 294
 295 (define_constraint "Crr"
 296  "@internal
 297   constant that can be loaded with ror b,u6"
 298   (and (match_code "const_int")
 299        (match_test "(ival & ~0x8000001f) == 0 && !arc_ccfsm_cond_exec_p ()")))
 300
 301 (define_constraint "Cbi"
 302  "@internal
 303   constant that can be loaded with movbi.cl"
 304   (and (match_code "const_int")
 305        (match_test "TARGET_NPS_BITOPS")
 306        (match_test "!ival
 307                     || ((ival & 0xffffffffUL) >> exact_log2 (ival & -ival)
 308                         <= 0xff)")))
 309
 310 ;; Floating-point constraints
 311
 312 (define_constraint "G"
 313   "@internal
 314    A 32-bit constant double value"
 315   (and (match_code "const_double")
 316        (match_test "arc_double_limm_p (op)")))
 317
 318 (define_constraint "H"
 319   "@internal
 320    All const_double values (including 64-bit values)"
 321   (and (match_code "const_double")
 322        (match_test "1")))
 323
 324 ;; Memory constraints
 325 (define_memory_constraint "T"
 326   "@internal
 327    A valid memory operand for ARCompact load instructions"
 328   (and (match_code "mem")
 329        (match_test "compact_memory_operand_p (op, mode, false, false)")))
 330
 331 (define_memory_constraint "Uts"
 332   "@internal
 333    A valid memory operand for ARCompact load instructions scaled"
 334   (and (match_code "mem")
 335        (match_test "compact_memory_operand_p (op, mode, false, TARGET_CODE_DENSITY)")))
 336
 337 (define_memory_constraint "S"
 338   "@internal
 339    A valid memory operand for ARCompact store instructions"
 340   (and (match_code "mem")
 341        (match_test "compact_store_memory_operand (op, VOIDmode)")))
 342
 343 (define_memory_constraint "Uex"
 344   "@internal
 345    A valid memory operand for limm-free extend instructions"
 346   (and (match_code "mem")
 347        (match_test "!cmem_address (XEXP (op, 0), SImode)")
 348        (not (match_operand 0 "long_immediate_loadstore_operand"))))
 349
 350 ; Don't use define_memory_constraint here as the relocation patching
 351 ; for small data symbols only works within a ld/st instruction and
 352 ; define_memory_constraint may result in the address being calculated
 353 ; into a register first.
 354 (define_constraint "Usd"
 355    "@internal
 356     A valid _small-data_ memory operand for ARCompact instructions"
 357    (and (match_code "mem")
 358         (match_test "compact_sda_memory_operand (op, VOIDmode, true)")))
 359
 360 ; Usc constant is only used for storing long constants, hence we can
 361 ; have only [b,s9], and [b] types of addresses.
 362 (define_memory_constraint "Usc"
 363   "@internal
 364    A valid memory operand for storing constants"
 365   (and (match_code "mem")
 366        (match_test "!CONSTANT_P (XEXP (op,0))")))
 367
 368 (define_constraint "Us<"
 369   "@internal
 370    Stack pre-decrement"
 371   (and (match_code "mem")
 372        (match_test "GET_CODE (XEXP (op, 0)) == PRE_DEC")
 373        (match_test "REG_P (XEXP (XEXP (op, 0), 0))")
 374        (match_test "REGNO (XEXP (XEXP (op, 0), 0)) == SP_REG")))
 375
 376 (define_constraint "Us>"
 377   "@internal
 378    Stack post-increment"
 379   (and (match_code "mem")
 380        (match_test "GET_CODE (XEXP (op, 0)) == POST_INC")
 381        (match_test "REG_P (XEXP (XEXP (op, 0), 0))")
 382        (match_test "REGNO (XEXP (XEXP (op, 0), 0)) == SP_REG")))
 383
 384 (define_constraint "Ucm"
 385   "@internal
 386   cmem access"
 387   (and (match_code "mem")
 388        (match_test "TARGET_NPS_CMEM && cmem_address (XEXP (op, 0), VOIDmode)")))
 389
 390 ;; General constraints
 391
 392 (define_constraint "Cbr"
 393   "Branch destination"
 394   (ior (and (match_code "symbol_ref")
 395             (match_test "!arc_is_longcall_p (op)"))
 396        (match_code "label_ref")))
 397
 398 (define_constraint "Cbp"
 399   "predicable branch/call destination"
 400   (ior (and (match_code "symbol_ref")
 401             (match_test "arc_is_shortcall_p (op)"))
 402        (match_code "label_ref")))
 403
 404 (define_constraint "Cji"
 405   "JLI call"
 406   (and (match_code "symbol_ref")
 407        (match_test "TARGET_CODE_DENSITY")
 408        (match_test "arc_is_jli_call_p (op)")))
 409
 410 (define_constraint "Cpc"
 411   "pc-relative constant"
 412   (match_test "arc_legitimate_pic_addr_p (op)"))
 413
 414 (define_constraint "Clb"
 415   "label"
 416   (and (match_code "label_ref")
 417        (match_test "arc_text_label (as_a <rtx_insn *> (XEXP (op, 0)))")))
 418
 419 (define_constraint "Cal"
 420   "constant for arithmetic/logical operations"
 421   (match_test "immediate_operand (op, VOIDmode) && !arc_legitimate_pic_addr_p (op)"))
 422
 423 (define_constraint "C32"
 424   "32 bit constant for arithmetic/logical operations"
 425   (match_test "immediate_operand (op, VOIDmode)
 426                && !arc_legitimate_pic_addr_p (op)
 427                && !satisfies_constraint_I (op)"))
 428
 429 ; Note that the 'cryptic' register constraints will not make reload use the
 430 ; associated class to reload into, but this will not penalize reloading of any
 431 ; other operands, or using an alternate part of the same alternative.
 432
 433 ; Rcq is different in three important ways from a register class constraint:
 434 ; - It does not imply a register class, hence reload will not use it to drive
 435 ;   reloads.
 436 ; - It matches even when there is no register class to describe its accepted
 437 ;   set; not having such a set again lessens the impact on register allocation.
 438 ; - It won't match when the instruction is conditionalized by the ccfsm.
 439 (define_constraint "Rcq"
 440   "@internal
 441    Cryptic q - for short insn generation while not affecting register allocation
 442    Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3},
 443    @code{r12}-@code{r15}"
 444   (and (match_code "reg")
 445        (match_test "TARGET_Rcq
 446                     && !arc_ccfsm_cond_exec_p ()
 447                     && IN_RANGE (REGNO (op) ^ 4, 4, 11)")))
 448
 449 ; If we need a reload, we generally want to steer reload to use three-address
 450 ; alternatives in preference of two-address alternatives, unless the
 451 ; three-address alternative introduces a LIMM that is unnecessary for the
 452 ; two-address alternative.
 453 (define_constraint "Rcw"
 454   "@internal
 455    Cryptic w - for use in early alternatives with matching constraint"
 456   (and (match_code "reg")
 457        (match_test
 458         "TARGET_Rcw
 459          && REGNO (op) < FIRST_PSEUDO_REGISTER
 460          && TEST_HARD_REG_BIT (reg_class_contents[WRITABLE_CORE_REGS],
 461                                REGNO (op))")))
 462
 463 (define_constraint "Rcr"
 464   "@internal
 465    Cryptic r - for use in early alternatives with matching constraint"
 466   (and (match_code "reg")
 467        (match_test
 468         "TARGET_Rcw
 469          && REGNO (op) < FIRST_PSEUDO_REGISTER
 470          && TEST_HARD_REG_BIT (reg_class_contents[GENERAL_REGS],
 471                                REGNO (op))")))
 472
 473 (define_constraint "Rcb"
 474   "@internal
 475    Stack Pointer register @code{r28} - do not reload into its class"
 476   (and (match_code "reg")
 477        (match_test "REGNO (op) == 28")))
 478
 479 (define_constraint "Rck"
 480   "@internal
 481    blink (usful for push_s / pop_s)"
 482   (and (match_code "reg")
 483        (match_test "REGNO (op) == 31")))
 484
 485 (define_constraint "Rs5"
 486   "@internal
 487    sibcall register - only allow one of the five available 16 bit isnsn.
 488    Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3},
 489    @code{r12}"
 490   (and (match_code "reg")
 491        (match_test "!arc_ccfsm_cond_exec_p ()")
 492        (ior (match_test "(unsigned) REGNO (op) <= 3")
 493             (match_test "REGNO (op) == 12"))))
 494
 495 (define_constraint "Rcc"
 496   "@internal
 497   Condition Codes"
 498   (and (match_code "reg") (match_test "cc_register (op, VOIDmode)")))
 499
 500
 501 (define_constraint "Q"
 502   "@internal
 503    Integer constant zero"
 504   (and (match_code "const_int")
 505        (match_test "IS_ZERO (ival)")))
 506
 507 (define_constraint "Cm1"
 508   "@internal
 509    Integer signed constant in the interval [-1,6]"
 510   (and (match_code "const_int")
 511        (match_test "(ival >= -1) && (ival <=6)")
 512        (match_test "TARGET_V2")))
 513
 514 (define_constraint "Cm2"
 515   "@internal
 516    A signed 9-bit integer constant."
 517   (and (match_code "const_int")
 518        (match_test "(ival >= -256) && (ival <=255)")))
 519
 520 (define_constraint "Cm3"
 521   "@internal
 522    A signed 6-bit integer constant."
 523   (and (match_code "const_int")
 524        (match_test "(ival >= -32) && (ival <=31)")
 525        (match_test "TARGET_V2")))
 526
 527 (define_constraint "C62"
 528   "@internal
 529    An unsigned 6-bit integer constant, up to 62."
 530   (and (match_code "const_int")
 531        (match_test "UNSIGNED_INT6 (ival - 1)")))
 532
 533 ;; Memory constraint used for atomic ops.
 534 (define_memory_constraint "ATO"
 535   "A memory with only a base register"
 536   (match_operand 0 "mem_noofs_operand"))
 537
 538 (define_constraint "J12"
 539   "@internal
 540    An unsigned 12-bit integer constant."
 541   (and (match_code "const_int")
 542        (match_test "UNSIGNED_INT12 (ival)")))
 543
 544 (define_constraint "J16"
 545   "@internal
 546    An unsigned 16-bit integer constant"
 547   (and (match_code "const_int")
 548        (match_test "UNSIGNED_INT16 (ival)")))
 549
 550 ; Memory addresses suited for code density load ops
 551 (define_memory_constraint "Ucd"
 552   "@internal
 553    A valid memory operand for use with code density load ops"
 554   (and (match_code "mem")
 555        (match_test "compact_memory_operand_p (op, mode, true, false)")
 556        (match_test "TARGET_V2")))
 557
 558 (define_register_constraint "h"
 559   "TARGET_V2 ? AC16_H_REGS : NO_REGS"
 560   "5-bit h register set except @code{r30} and @code{r29}:
 561    @code{r0}-@code{r31}, nonfixed core register")
 562
 563 ; Code density registers
 564 (define_register_constraint "Rcd"
 565   "TARGET_CODE_DENSITY ? R0R3_CD_REGS : NO_REGS"
 566   "@internal
 567    core register @code{r0}-@code{r3}")
 568
 569 (define_register_constraint "Rsd"
 570   "TARGET_CODE_DENSITY ? R0R1_CD_REGS : NO_REGS"
 571   "@internal
 572    core register @code{r0}-@code{r1}")
 573
 574 (define_register_constraint "Rzd"
 575   "TARGET_CODE_DENSITY ? R0_REGS : NO_REGS"
 576   "@internal
 577    @code{r0} register for code density instructions.")