gcc/config/arc/simdext.md

   1 ;; Machine description of the Synopsys DesignWare ARC cpu for GNU C compiler
   2 ;; Copyright (C) 2007-2015 Free Software Foundation, Inc.
   3
   4 ;; This file is part of GCC.
   5
   6 ;; GCC is free software; you can redistribute it and/or modify
   7 ;; it under the terms of the GNU General Public License as published by
   8 ;; the Free Software Foundation; either version 3, or (at your option)
   9 ;; any later version.
  10
  11 ;; GCC is distributed in the hope that it will be useful,
  12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ;; GNU General Public License for more details.
  15
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING3.  If not see
  18 ;; <http://www.gnu.org/licenses/>.
  19
  20 (define_constants
  21   [
  22   ;; Va, Vb, Vc builtins
  23   (UNSPEC_ARC_SIMD_VADDAW     1000)
  24   (UNSPEC_ARC_SIMD_VADDW      1001)
  25   (UNSPEC_ARC_SIMD_VAVB       1002)
  26   (UNSPEC_ARC_SIMD_VAVRB      1003)
  27   (UNSPEC_ARC_SIMD_VDIFAW     1004)
  28   (UNSPEC_ARC_SIMD_VDIFW      1005)
  29   (UNSPEC_ARC_SIMD_VMAXAW     1006)
  30   (UNSPEC_ARC_SIMD_VMAXW      1007)
  31   (UNSPEC_ARC_SIMD_VMINAW     1008)
  32   (UNSPEC_ARC_SIMD_VMINW      1009)
  33   (UNSPEC_ARC_SIMD_VMULAW     1010)
  34   (UNSPEC_ARC_SIMD_VMULFAW    1011)
  35   (UNSPEC_ARC_SIMD_VMULFW     1012)
  36   (UNSPEC_ARC_SIMD_VMULW      1013)
  37   (UNSPEC_ARC_SIMD_VSUBAW     1014)
  38   (UNSPEC_ARC_SIMD_VSUBW      1015)
  39   (UNSPEC_ARC_SIMD_VSUMMW     1016)
  40   (UNSPEC_ARC_SIMD_VAND       1017)
  41   (UNSPEC_ARC_SIMD_VANDAW     1018)
  42   (UNSPEC_ARC_SIMD_VBIC       1019)
  43   (UNSPEC_ARC_SIMD_VBICAW     1020)
  44   (UNSPEC_ARC_SIMD_VOR        1021)
  45   (UNSPEC_ARC_SIMD_VXOR       1022)
  46   (UNSPEC_ARC_SIMD_VXORAW     1023)
  47   (UNSPEC_ARC_SIMD_VEQW       1024)
  48   (UNSPEC_ARC_SIMD_VLEW       1025)
  49   (UNSPEC_ARC_SIMD_VLTW       1026)
  50   (UNSPEC_ARC_SIMD_VNEW       1027)
  51   (UNSPEC_ARC_SIMD_VMR1AW     1028)
  52   (UNSPEC_ARC_SIMD_VMR1W      1029)
  53   (UNSPEC_ARC_SIMD_VMR2AW     1030)
  54   (UNSPEC_ARC_SIMD_VMR2W      1031)
  55   (UNSPEC_ARC_SIMD_VMR3AW     1032)
  56   (UNSPEC_ARC_SIMD_VMR3W      1033)
  57   (UNSPEC_ARC_SIMD_VMR4AW     1034)
  58   (UNSPEC_ARC_SIMD_VMR4W      1035)
  59   (UNSPEC_ARC_SIMD_VMR5AW     1036)
  60   (UNSPEC_ARC_SIMD_VMR5W      1037)
  61   (UNSPEC_ARC_SIMD_VMR6AW     1038)
  62   (UNSPEC_ARC_SIMD_VMR6W      1039)
  63   (UNSPEC_ARC_SIMD_VMR7AW     1040)
  64   (UNSPEC_ARC_SIMD_VMR7W      1041)
  65   (UNSPEC_ARC_SIMD_VMRB       1042)
  66   (UNSPEC_ARC_SIMD_VH264F     1043)
  67   (UNSPEC_ARC_SIMD_VH264FT    1044)
  68   (UNSPEC_ARC_SIMD_VH264FW    1045)
  69   (UNSPEC_ARC_SIMD_VVC1F      1046)
  70   (UNSPEC_ARC_SIMD_VVC1FT     1047)
  71   ;; Va, Vb, rc/limm builtins
  72   (UNSPEC_ARC_SIMD_VBADDW     1050)
  73   (UNSPEC_ARC_SIMD_VBMAXW     1051)
  74   (UNSPEC_ARC_SIMD_VBMINW     1052)
  75   (UNSPEC_ARC_SIMD_VBMULAW    1053)
  76   (UNSPEC_ARC_SIMD_VBMULFW    1054)
  77   (UNSPEC_ARC_SIMD_VBMULW     1055)
  78   (UNSPEC_ARC_SIMD_VBRSUBW    1056)
  79   (UNSPEC_ARC_SIMD_VBSUBW     1057)
  80
  81   ;; Va, Vb, Ic builtins
  82   (UNSPEC_ARC_SIMD_VASRW      1060)
  83   (UNSPEC_ARC_SIMD_VSR8       1061)
  84   (UNSPEC_ARC_SIMD_VSR8AW     1062)
  85
  86   ;; Va, Vb, Ic builtins
  87   (UNSPEC_ARC_SIMD_VASRRWi    1065)
  88   (UNSPEC_ARC_SIMD_VASRSRWi   1066)
  89   (UNSPEC_ARC_SIMD_VASRWi     1067)
  90   (UNSPEC_ARC_SIMD_VASRPWBi   1068)
  91   (UNSPEC_ARC_SIMD_VASRRPWBi  1069)
  92   (UNSPEC_ARC_SIMD_VSR8AWi    1070)
  93   (UNSPEC_ARC_SIMD_VSR8i      1071)
  94
  95   ;; Va, Vb, u8 (simm) builtins
  96   (UNSPEC_ARC_SIMD_VMVAW      1075)
  97   (UNSPEC_ARC_SIMD_VMVW       1076)
  98   (UNSPEC_ARC_SIMD_VMVZW      1077)
  99   (UNSPEC_ARC_SIMD_VD6TAPF    1078)
 100
 101   ;; Va, rlimm, u8 (simm) builtins
 102   (UNSPEC_ARC_SIMD_VMOVAW     1080)
 103   (UNSPEC_ARC_SIMD_VMOVW      1081)
 104   (UNSPEC_ARC_SIMD_VMOVZW     1082)
 105
 106   ;; Va, Vb builtins
 107   (UNSPEC_ARC_SIMD_VABSAW     1085)
 108   (UNSPEC_ARC_SIMD_VABSW      1086)
 109   (UNSPEC_ARC_SIMD_VADDSUW    1087)
 110   (UNSPEC_ARC_SIMD_VSIGNW     1088)
 111   (UNSPEC_ARC_SIMD_VEXCH1     1089)
 112   (UNSPEC_ARC_SIMD_VEXCH2     1090)
 113   (UNSPEC_ARC_SIMD_VEXCH4     1091)
 114   (UNSPEC_ARC_SIMD_VUPBAW     1092)
 115   (UNSPEC_ARC_SIMD_VUPBW      1093)
 116   (UNSPEC_ARC_SIMD_VUPSBAW    1094)
 117   (UNSPEC_ARC_SIMD_VUPSBW     1095)
 118
 119   (UNSPEC_ARC_SIMD_VDIRUN     1100)
 120   (UNSPEC_ARC_SIMD_VDORUN     1101)
 121   (UNSPEC_ARC_SIMD_VDIWR      1102)
 122   (UNSPEC_ARC_SIMD_VDOWR      1103)
 123
 124   (UNSPEC_ARC_SIMD_VREC      1105)
 125   (UNSPEC_ARC_SIMD_VRUN      1106)
 126   (UNSPEC_ARC_SIMD_VRECRUN   1107)
 127   (UNSPEC_ARC_SIMD_VENDREC   1108)
 128
 129   (UNSPEC_ARC_SIMD_VCAST     1200)
 130   (UNSPEC_ARC_SIMD_VINTI     1201)
 131    ]
 132 )
 133
 134 ;; Scheduler descriptions for the simd instructions
 135 (define_insn_reservation "simd_lat_0_insn" 1
 136   (eq_attr "type" "simd_dma, simd_vstore, simd_vcontrol")
 137   "issue+simd_unit")
 138
 139 (define_insn_reservation "simd_lat_1_insn" 2
 140        (eq_attr "type" "simd_vcompare, simd_vlogic,
 141                         simd_vmove_else_zero, simd_varith_1cycle")
 142   "issue+simd_unit, nothing")
 143
 144 (define_insn_reservation "simd_lat_2_insn" 3
 145        (eq_attr "type" "simd_valign, simd_vpermute,
 146                         simd_vpack, simd_varith_2cycle")
 147   "issue+simd_unit, nothing*2")
 148
 149 (define_insn_reservation "simd_lat_3_insn" 4
 150        (eq_attr "type" "simd_valign_with_acc, simd_vpack_with_acc,
 151                         simd_vlogic_with_acc, simd_vload128,
 152                         simd_vmove_with_acc, simd_vspecial_3cycle,
 153                         simd_varith_with_acc")
 154   "issue+simd_unit, nothing*3")
 155
 156 (define_insn_reservation "simd_lat_4_insn" 5
 157        (eq_attr "type" "simd_vload, simd_vmove, simd_vspecial_4cycle")
 158   "issue+simd_unit, nothing*4")
 159
 160 (define_expand "movv8hi"
 161   [(set (match_operand:V8HI 0 "general_operand" "")
 162         (match_operand:V8HI 1 "general_operand" ""))]
 163   ""
 164   "
 165 {
 166   /* Everything except mem = const or mem = mem can be done easily.  */
 167
 168   if (GET_CODE (operands[0]) == MEM && GET_CODE(operands[1]) == MEM)
 169     operands[1] = force_reg (V8HImode, operands[1]);
 170 }")
 171
 172 ;; This pattern should appear before the movv8hi_insn pattern
 173 (define_insn "vld128_insn"
 174   [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
 175         (mem:V8HI (plus:SI (zero_extend:SI (vec_select:HI (match_operand:V8HI 1 "vector_register_operand"  "v")
 176                                                           (parallel [(match_operand:SI 2 "immediate_operand" "L")])))
 177                            (match_operand:SI 3 "immediate_operand" "P"))))]
 178  "TARGET_SIMD_SET"
 179  "vld128 %0, [i%2, %3]"
 180  [(set_attr "type" "simd_vload128")
 181   (set_attr "length" "4")
 182   (set_attr "cond" "nocond")]
 183 )
 184
 185 (define_insn "vst128_insn"
 186   [(set (mem:V8HI (plus:SI (zero_extend:SI (vec_select:HI (match_operand:V8HI 0 "vector_register_operand"  "v")
 187                                                           (parallel [(match_operand:SI 1 "immediate_operand" "L")])))
 188                            (match_operand:SI 2 "immediate_operand" "P")))
 189         (match_operand:V8HI 3 "vector_register_operand" "=v"))]
 190  "TARGET_SIMD_SET"
 191  "vst128 %3, [i%1, %2]"
 192  [(set_attr "type" "simd_vstore")
 193   (set_attr "length" "4")
 194   (set_attr "cond" "nocond")]
 195 )
 196
 197 (define_insn "vst64_insn"
 198   [(set (mem:V4HI (plus:SI (zero_extend:SI (vec_select:HI (match_operand:V8HI 0 "vector_register_operand"  "v")
 199                                                           (parallel [(match_operand:SI 1 "immediate_operand" "L")])))
 200                            (match_operand:SI 2 "immediate_operand" "P")))
 201         (vec_select:V4HI (match_operand:V8HI 3 "vector_register_operand" "=v")
 202                          (parallel [(const_int 0)])))]
 203  "TARGET_SIMD_SET"
 204  "vst64 %3, [i%1, %2]"
 205  [(set_attr "type" "simd_vstore")
 206   (set_attr "length" "4")
 207   (set_attr "cond" "nocond")]
 208 )
 209
 210 (define_insn "movv8hi_insn"
 211   [(set (match_operand:V8HI 0 "vector_register_or_memory_operand" "=v,m,v")
 212         (match_operand:V8HI 1 "vector_register_or_memory_operand" "m,v,v"))]
 213   "TARGET_SIMD_SET && !(GET_CODE (operands[0]) == MEM && GET_CODE(operands[1]) == MEM)"
 214   "@
 215     vld128r %0, %1
 216     vst128r %1, %0
 217     vmvzw %0,%1,0xffff"
 218   [(set_attr "type" "simd_vload128,simd_vstore,simd_vmove_else_zero")
 219    (set_attr "length" "8,8,4")
 220    (set_attr "cond" "nocond, nocond, nocond")])
 221
 222 (define_insn "movti_insn"
 223   [(set (match_operand:TI 0 "vector_register_or_memory_operand" "=v,m,v")
 224         (match_operand:TI 1 "vector_register_or_memory_operand" "m,v,v"))]
 225   ""
 226   "@
 227     vld128r %0, %1
 228     vst128r %1, %0
 229     vmvzw %0,%1,0xffff"
 230   [(set_attr "type" "simd_vload128,simd_vstore,simd_vmove_else_zero")
 231    (set_attr "length" "8,8,4")
 232    (set_attr "cond" "nocond, nocond, nocond")])
 233
 234 ;; (define_insn "*movv8hi_insn_rr"
 235 ;;   [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
 236 ;;      (match_operand:V8HI 1 "vector_register_operand" "v"))]
 237 ;;   ""
 238 ;;   "mov reg,reg"
 239 ;;   [(set_attr "length" "8")
 240 ;;   (set_attr "type" "move")])
 241
 242 ;; (define_insn "*movv8_out"
 243 ;;   [(set (match_operand:V8HI 0 "memory_operand" "=m")
 244 ;;      (match_operand:V8HI 1 "vector_register_operand" "v"))]
 245 ;;   ""
 246 ;;   "mov out"
 247 ;;   [(set_attr "length" "8")
 248 ;;   (set_attr "type" "move")])
 249
 250
 251 ;; (define_insn "addv8hi3"
 252 ;;   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 253 ;;      (plus:V8HI (match_operand:V8HI 1 "vector_register_operand"  "v")
 254 ;;                 (match_operand:V8HI 2 "vector_register_operand" "v")))]
 255 ;;   "TARGET_SIMD_SET"
 256 ;;   "vaddw %0, %1, %2"
 257 ;;   [(set_attr "length" "8")
 258 ;;    (set_attr "cond" "nocond")])
 259
 260 ;; (define_insn "vaddw_insn"
 261 ;;   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 262 ;;      (unspec [(match_operand:V8HI 1 "vector_register_operand"  "v")
 263 ;;                       (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VADDW))]
 264 ;;   "TARGET_SIMD_SET"
 265 ;;   "vaddw %0, %1, %2"
 266 ;;   [(set_attr "length" "8")
 267 ;;    (set_attr "cond" "nocond")])
 268
 269 ;; V V V Insns
 270 (define_insn "vaddaw_insn"
 271   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 272         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 273                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VADDAW))]
 274   "TARGET_SIMD_SET"
 275   "vaddaw %0, %1, %2"
 276   [(set_attr "type" "simd_varith_with_acc")
 277    (set_attr "length" "4")
 278    (set_attr "cond" "nocond")])
 279
 280 (define_insn "vaddw_insn"
 281   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 282         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 283                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VADDW))]
 284   "TARGET_SIMD_SET"
 285   "vaddw %0, %1, %2"
 286   [(set_attr "type" "simd_varith_1cycle")
 287    (set_attr "length" "4")
 288    (set_attr "cond" "nocond")])
 289
 290 (define_insn "vavb_insn"
 291   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 292         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 293                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VAVB))]
 294   "TARGET_SIMD_SET"
 295   "vavb %0, %1, %2"
 296   [(set_attr "type" "simd_varith_1cycle")
 297    (set_attr "length" "4")
 298    (set_attr "cond" "nocond")])
 299
 300 (define_insn "vavrb_insn"
 301   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 302         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 303                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VAVRB))]
 304   "TARGET_SIMD_SET"
 305   "vavrb %0, %1, %2"
 306   [(set_attr "type" "simd_varith_1cycle")
 307    (set_attr "length" "4")
 308    (set_attr "cond" "nocond")])
 309
 310 (define_insn "vdifaw_insn"
 311   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 312         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 313                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VDIFAW))]
 314   "TARGET_SIMD_SET"
 315   "vdifaw %0, %1, %2"
 316   [(set_attr "type" "simd_varith_with_acc")
 317    (set_attr "length" "4")
 318    (set_attr "cond" "nocond")])
 319
 320 (define_insn "vdifw_insn"
 321   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 322         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 323                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VDIFW))]
 324   "TARGET_SIMD_SET"
 325   "vdifw %0, %1, %2"
 326   [(set_attr "type" "simd_varith_1cycle")
 327    (set_attr "length" "4")
 328    (set_attr "cond" "nocond")])
 329
 330 (define_insn "vmaxaw_insn"
 331   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 332         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 333                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMAXAW))]
 334   "TARGET_SIMD_SET"
 335   "vmaxaw %0, %1, %2"
 336   [(set_attr "type" "simd_varith_with_acc")
 337    (set_attr "length" "4")
 338    (set_attr "cond" "nocond")])
 339
 340 (define_insn "vmaxw_insn"
 341   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 342         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 343                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMAXW))]
 344   "TARGET_SIMD_SET"
 345   "vmaxw %0, %1, %2"
 346   [(set_attr "type" "simd_varith_1cycle")
 347    (set_attr "length" "4")
 348    (set_attr "cond" "nocond")])
 349
 350 (define_insn "vminaw_insn"
 351   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 352         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 353                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMINAW))]
 354   "TARGET_SIMD_SET"
 355   "vminaw %0, %1, %2"
 356   [(set_attr "type" "simd_varith_with_acc")
 357    (set_attr "length" "4")
 358    (set_attr "cond" "nocond")])
 359
 360 (define_insn "vminw_insn"
 361   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 362         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 363                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMINW))]
 364   "TARGET_SIMD_SET"
 365   "vminw %0, %1, %2"
 366   [(set_attr "type" "simd_varith_1cycle")
 367    (set_attr "length" "4")
 368    (set_attr "cond" "nocond")])
 369
 370 (define_insn "vmulaw_insn"
 371   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 372         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 373                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMULAW))]
 374   "TARGET_SIMD_SET"
 375   "vmulaw %0, %1, %2"
 376   [(set_attr "type" "simd_varith_with_acc")
 377    (set_attr "length" "4")
 378    (set_attr "cond" "nocond")])
 379
 380 (define_insn "vmulfaw_insn"
 381   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 382         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 383                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMULFAW))]
 384   "TARGET_SIMD_SET"
 385   "vmulfaw %0, %1, %2"
 386   [(set_attr "type" "simd_varith_with_acc")
 387    (set_attr "length" "4")
 388    (set_attr "cond" "nocond")])
 389
 390 (define_insn "vmulfw_insn"
 391   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 392         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 393                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMULFW))]
 394   "TARGET_SIMD_SET"
 395   "vmulfw %0, %1, %2"
 396   [(set_attr "type" "simd_varith_2cycle")
 397    (set_attr "length" "4")
 398    (set_attr "cond" "nocond")])
 399
 400 (define_insn "vmulw_insn"
 401   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 402         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 403                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMULW))]
 404   "TARGET_SIMD_SET"
 405   "vmulw %0, %1, %2"
 406   [(set_attr "type" "simd_varith_2cycle")
 407    (set_attr "length" "4")
 408    (set_attr "cond" "nocond")])
 409
 410 (define_insn "vsubaw_insn"
 411   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 412         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 413                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VSUBAW))]
 414   "TARGET_SIMD_SET"
 415   "vsubaw %0, %1, %2"
 416   [(set_attr "type" "simd_varith_with_acc")
 417    (set_attr "length" "4")
 418    (set_attr "cond" "nocond")])
 419
 420 (define_insn "vsubw_insn"
 421   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 422         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 423                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VSUBW))]
 424   "TARGET_SIMD_SET"
 425   "vsubw %0, %1, %2"
 426   [(set_attr "type" "simd_varith_1cycle")
 427    (set_attr "length" "4")
 428    (set_attr "cond" "nocond")])
 429
 430 (define_insn "vsummw_insn"
 431   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 432         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 433                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VSUMMW))]
 434   "TARGET_SIMD_SET"
 435   "vsummw %0, %1, %2"
 436   [(set_attr "type" "simd_varith_2cycle")
 437    (set_attr "length" "4")
 438    (set_attr "cond" "nocond")])
 439
 440 (define_insn "vand_insn"
 441   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 442         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 443                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VAND))]
 444   "TARGET_SIMD_SET"
 445   "vand %0, %1, %2"
 446   [(set_attr "type" "simd_vlogic")
 447    (set_attr "length" "4")
 448    (set_attr "cond" "nocond")])
 449
 450 (define_insn "vandaw_insn"
 451   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 452         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 453                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VANDAW))]
 454   "TARGET_SIMD_SET"
 455   "vandaw %0, %1, %2"
 456   [(set_attr "type" "simd_vlogic_with_acc")
 457    (set_attr "length" "4")
 458    (set_attr "cond" "nocond")])
 459
 460 (define_insn "vbic_insn"
 461   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 462         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 463                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VBIC))]
 464   "TARGET_SIMD_SET"
 465   "vbic %0, %1, %2"
 466   [(set_attr "type" "simd_vlogic")
 467    (set_attr "length" "4")
 468    (set_attr "cond" "nocond")])
 469
 470 (define_insn "vbicaw_insn"
 471   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 472         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 473                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VBICAW))]
 474   "TARGET_SIMD_SET"
 475   "vbicaw %0, %1, %2"
 476   [(set_attr "type" "simd_vlogic_with_acc")
 477    (set_attr "length" "4")
 478    (set_attr "cond" "nocond")])
 479
 480 (define_insn "vor_insn"
 481   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 482         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 483                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VOR))]
 484   "TARGET_SIMD_SET"
 485   "vor %0, %1, %2"
 486   [(set_attr "type" "simd_vlogic")
 487    (set_attr "length" "4")
 488    (set_attr "cond" "nocond")])
 489
 490 (define_insn "vxor_insn"
 491   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 492         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 493                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VXOR))]
 494   "TARGET_SIMD_SET"
 495   "vxor %0, %1, %2"
 496   [(set_attr "type" "simd_vlogic")
 497    (set_attr "length" "4")
 498    (set_attr "cond" "nocond")])
 499
 500 (define_insn "vxoraw_insn"
 501   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 502         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 503                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VXORAW))]
 504   "TARGET_SIMD_SET"
 505   "vxoraw %0, %1, %2"
 506   [(set_attr "type" "simd_vlogic_with_acc")
 507    (set_attr "length" "4")
 508    (set_attr "cond" "nocond")])
 509
 510 (define_insn "veqw_insn"
 511   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 512         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 513                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VEQW))]
 514   "TARGET_SIMD_SET"
 515   "veqw %0, %1, %2"
 516   [(set_attr "type" "simd_vcompare")
 517    (set_attr "length" "4")
 518    (set_attr "cond" "nocond")])
 519
 520 (define_insn "vlew_insn"
 521   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 522         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 523                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VLEW))]
 524   "TARGET_SIMD_SET"
 525   "vlew %0, %1, %2"
 526   [(set_attr "type" "simd_vcompare")
 527    (set_attr "length" "4")
 528    (set_attr "cond" "nocond")])
 529
 530 (define_insn "vltw_insn"
 531   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 532         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 533                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VLTW))]
 534   "TARGET_SIMD_SET"
 535   "vltw %0, %1, %2"
 536   [(set_attr "type" "simd_vcompare")
 537    (set_attr "length" "4")
 538    (set_attr "cond" "nocond")])
 539
 540 (define_insn "vnew_insn"
 541   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 542         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 543                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VNEW))]
 544   "TARGET_SIMD_SET"
 545   "vnew %0, %1, %2"
 546   [(set_attr "type" "simd_vcompare")
 547    (set_attr "length" "4")
 548    (set_attr "cond" "nocond")])
 549
 550 (define_insn "vmr1aw_insn"
 551   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 552         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 553                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR1AW))]
 554   "TARGET_SIMD_SET"
 555   "vmr1aw %0, %1, %2"
 556   [(set_attr "type" "simd_valign_with_acc")
 557    (set_attr "length" "4")
 558    (set_attr "cond" "nocond")])
 559
 560 (define_insn "vmr1w_insn"
 561   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 562         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 563                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR1W))]
 564   "TARGET_SIMD_SET"
 565   "vmr1w %0, %1, %2"
 566   [(set_attr "type" "simd_valign")
 567    (set_attr "length" "4")
 568    (set_attr "cond" "nocond")])
 569
 570 (define_insn "vmr2aw_insn"
 571   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 572         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 573                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR2AW))]
 574   "TARGET_SIMD_SET"
 575   "vmr2aw %0, %1, %2"
 576   [(set_attr "type" "simd_valign_with_acc")
 577    (set_attr "length" "4")
 578    (set_attr "cond" "nocond")])
 579
 580 (define_insn "vmr2w_insn"
 581   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 582         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 583                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR2W))]
 584   "TARGET_SIMD_SET"
 585   "vmr2w %0, %1, %2"
 586   [(set_attr "type" "simd_valign")
 587    (set_attr "length" "4")
 588    (set_attr "cond" "nocond")])
 589
 590 (define_insn "vmr3aw_insn"
 591   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 592         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 593                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR3AW))]
 594   "TARGET_SIMD_SET"
 595   "vmr3aw %0, %1, %2"
 596   [(set_attr "type" "simd_valign_with_acc")
 597    (set_attr "length" "4")
 598    (set_attr "cond" "nocond")])
 599
 600 (define_insn "vmr3w_insn"
 601   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 602         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 603                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR3W))]
 604   "TARGET_SIMD_SET"
 605   "vmr3w %0, %1, %2"
 606   [(set_attr "type" "simd_valign")
 607    (set_attr "length" "4")
 608    (set_attr "cond" "nocond")])
 609
 610 (define_insn "vmr4aw_insn"
 611   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 612         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 613                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR4AW))]
 614   "TARGET_SIMD_SET"
 615   "vmr4aw %0, %1, %2"
 616   [(set_attr "type" "simd_valign_with_acc")
 617    (set_attr "length" "4")
 618    (set_attr "cond" "nocond")])
 619
 620 (define_insn "vmr4w_insn"
 621   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 622         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 623                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR4W))]
 624   "TARGET_SIMD_SET"
 625   "vmr4w %0, %1, %2"
 626   [(set_attr "type" "simd_valign")
 627    (set_attr "length" "4")
 628    (set_attr "cond" "nocond")])
 629
 630 (define_insn "vmr5aw_insn"
 631   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 632         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 633                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR5AW))]
 634   "TARGET_SIMD_SET"
 635   "vmr5aw %0, %1, %2"
 636   [(set_attr "type" "simd_valign_with_acc")
 637    (set_attr "length" "4")
 638    (set_attr "cond" "nocond")])
 639
 640 (define_insn "vmr5w_insn"
 641   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 642         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 643                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR5W))]
 644   "TARGET_SIMD_SET"
 645   "vmr5w %0, %1, %2"
 646   [(set_attr "type" "simd_valign")
 647    (set_attr "length" "4")
 648    (set_attr "cond" "nocond")])
 649
 650 (define_insn "vmr6aw_insn"
 651   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 652         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 653                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR6AW))]
 654   "TARGET_SIMD_SET"
 655   "vmr6aw %0, %1, %2"
 656   [(set_attr "type" "simd_valign_with_acc")
 657    (set_attr "length" "4")
 658    (set_attr "cond" "nocond")])
 659
 660 (define_insn "vmr6w_insn"
 661   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 662         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 663                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR6W))]
 664   "TARGET_SIMD_SET"
 665   "vmr6w %0, %1, %2"
 666   [(set_attr "type" "simd_valign")
 667    (set_attr "length" "4")
 668    (set_attr "cond" "nocond")])
 669
 670 (define_insn "vmr7aw_insn"
 671   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 672         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 673                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR7AW))]
 674   "TARGET_SIMD_SET"
 675   "vmr7aw %0, %1, %2"
 676   [(set_attr "type" "simd_valign_with_acc")
 677    (set_attr "length" "4")
 678    (set_attr "cond" "nocond")])
 679
 680 (define_insn "vmr7w_insn"
 681   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 682         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 683                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR7W))]
 684   "TARGET_SIMD_SET"
 685   "vmr7w %0, %1, %2"
 686   [(set_attr "type" "simd_valign")
 687    (set_attr "length" "4")
 688    (set_attr "cond" "nocond")])
 689
 690 (define_insn "vmrb_insn"
 691   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 692         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 693                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMRB))]
 694   "TARGET_SIMD_SET"
 695   "vmrb %0, %1, %2"
 696   [(set_attr "type" "simd_valign")
 697    (set_attr "length" "4")
 698    (set_attr "cond" "nocond")])
 699
 700 (define_insn "vh264f_insn"
 701   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 702         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 703                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VH264F))]
 704   "TARGET_SIMD_SET"
 705   "vh264f %0, %1, %2"
 706   [(set_attr "type" "simd_vspecial_3cycle")
 707    (set_attr "length" "4")
 708    (set_attr "cond" "nocond")])
 709
 710 (define_insn "vh264ft_insn"
 711   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 712         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 713                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VH264FT))]
 714   "TARGET_SIMD_SET"
 715   "vh264ft %0, %1, %2"
 716   [(set_attr "type" "simd_vspecial_3cycle")
 717    (set_attr "length" "4")
 718    (set_attr "cond" "nocond")])
 719
 720 (define_insn "vh264fw_insn"
 721   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 722         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 723                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VH264FW))]
 724   "TARGET_SIMD_SET"
 725   "vh264fw %0, %1, %2"
 726   [(set_attr "type" "simd_vspecial_3cycle")
 727    (set_attr "length" "4")
 728    (set_attr "cond" "nocond")])
 729
 730 (define_insn "vvc1f_insn"
 731   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 732         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 733                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VVC1F))]
 734   "TARGET_SIMD_SET"
 735   "vvc1f %0, %1, %2"
 736   [(set_attr "type" "simd_vspecial_3cycle")
 737    (set_attr "length" "4")
 738    (set_attr "cond" "nocond")])
 739
 740 (define_insn "vvc1ft_insn"
 741   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 742         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 743                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VVC1FT))]
 744   "TARGET_SIMD_SET"
 745   "vvc1ft %0, %1, %2"
 746   [(set_attr "type" "simd_vspecial_3cycle")
 747    (set_attr "length" "4")
 748    (set_attr "cond" "nocond")])
 749
 750
 751
 752 ;;---
 753 ;; V V r/limm Insns
 754
 755 ;; (define_insn "vbaddw_insn"
 756 ;;   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 757 ;;      (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 758 ;;                            (match_operand:SI 2 "nonmemory_operand" "rCal")] UNSPEC_ARC_SIMD_VBADDW))]
 759 ;;   "TARGET_SIMD_SET"
 760 ;;   "vbaddw %0, %1, %2"
 761 ;;   [(set_attr "length" "4")
 762 ;;    (set_attr "cond" "nocond")])
 763
 764 (define_insn "vbaddw_insn"
 765   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 766         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 767                       (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBADDW))]
 768   "TARGET_SIMD_SET"
 769   "vbaddw %0, %1, %2"
 770   [(set_attr "type" "simd_varith_1cycle")
 771    (set_attr "length" "4")
 772    (set_attr "cond" "nocond")])
 773
 774 (define_insn "vbmaxw_insn"
 775   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 776         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 777                       (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBMAXW))]
 778   "TARGET_SIMD_SET"
 779   "vbmaxw %0, %1, %2"
 780   [(set_attr "type" "simd_varith_1cycle")
 781    (set_attr "length" "4")
 782    (set_attr "cond" "nocond")])
 783
 784 (define_insn "vbminw_insn"
 785   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 786         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 787                       (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBMINW))]
 788   "TARGET_SIMD_SET"
 789   "vbminw %0, %1, %2"
 790   [(set_attr "type" "simd_varith_1cycle")
 791    (set_attr "length" "4")
 792    (set_attr "cond" "nocond")])
 793
 794 (define_insn "vbmulaw_insn"
 795   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 796         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 797                       (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBMULAW))]
 798   "TARGET_SIMD_SET"
 799   "vbmulaw %0, %1, %2"
 800   [(set_attr "type" "simd_varith_with_acc")
 801    (set_attr "length" "4")
 802    (set_attr "cond" "nocond")])
 803
 804 (define_insn "vbmulfw_insn"
 805   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 806         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 807                       (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBMULFW))]
 808   "TARGET_SIMD_SET"
 809   "vbmulfw %0, %1, %2"
 810   [(set_attr "type" "simd_varith_2cycle")
 811    (set_attr "length" "4")
 812    (set_attr "cond" "nocond")])
 813
 814 (define_insn "vbmulw_insn"
 815   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 816         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 817                       (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBMULW))]
 818   "TARGET_SIMD_SET"
 819   "vbmulw %0, %1, %2"
 820   [(set_attr "type" "simd_varith_2cycle")
 821    (set_attr "length" "4")
 822    (set_attr "cond" "nocond")])
 823
 824 (define_insn "vbrsubw_insn"
 825   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 826         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 827                      (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBRSUBW))]
 828   "TARGET_SIMD_SET"
 829   "vbrsubw %0, %1, %2"
 830   [(set_attr "type" "simd_varith_1cycle")
 831    (set_attr "length" "4")
 832    (set_attr "cond" "nocond")])
 833
 834 (define_insn "vbsubw_insn"
 835   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 836         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 837                       (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBSUBW))]
 838   "TARGET_SIMD_SET"
 839   "vbsubw %0, %1, %2"
 840   [(set_attr "type" "simd_varith_1cycle")
 841    (set_attr "length" "4")
 842    (set_attr "cond" "nocond")])
 843 ; Va, Vb, Ic instructions
 844
 845 ; Va, Vb, u6 instructions
 846 (define_insn "vasrrwi_insn"
 847   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 848         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 849                       (match_operand:SI 2 "immediate_operand" "L")] UNSPEC_ARC_SIMD_VASRRWi))]
 850   "TARGET_SIMD_SET"
 851   "vasrrwi %0, %1, %2"
 852   [(set_attr "type" "simd_varith_2cycle")
 853    (set_attr "length" "4")
 854    (set_attr "cond" "nocond")])
 855
 856 (define_insn "vasrsrwi_insn"
 857   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 858         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 859                      (match_operand:SI 2 "immediate_operand" "L")] UNSPEC_ARC_SIMD_VASRSRWi))]
 860   "TARGET_SIMD_SET"
 861   "vasrsrwi %0, %1, %2"
 862   [(set_attr "type" "simd_varith_2cycle")
 863    (set_attr "length" "4")
 864    (set_attr "cond" "nocond")])
 865
 866 (define_insn "vasrwi_insn"
 867   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 868         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 869                       (match_operand:SI 2 "immediate_operand" "L")] UNSPEC_ARC_SIMD_VASRWi))]
 870   "TARGET_SIMD_SET"
 871   "vasrwi %0, %1, %2"
 872   [(set_attr "type" "simd_varith_1cycle")
 873    (set_attr "length" "4")
 874    (set_attr "cond" "nocond")])
 875
 876 (define_insn "vasrpwbi_insn"
 877   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 878         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 879                       (match_operand:SI 2 "immediate_operand" "L")] UNSPEC_ARC_SIMD_VASRPWBi))]
 880   "TARGET_SIMD_SET"
 881   "vasrpwbi %0, %1, %2"
 882   [(set_attr "type" "simd_vpack")
 883    (set_attr "length" "4")
 884    (set_attr "cond" "nocond")])
 885
 886 (define_insn "vasrrpwbi_insn"
 887   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 888         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 889                       (match_operand:SI 2 "immediate_operand" "L")] UNSPEC_ARC_SIMD_VASRRPWBi))]
 890   "TARGET_SIMD_SET"
 891   "vasrrpwbi %0, %1, %2"
 892   [(set_attr "type" "simd_vpack")
 893    (set_attr "length" "4")
 894    (set_attr "cond" "nocond")])
 895
 896 (define_insn "vsr8awi_insn"
 897   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 898         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 899                       (match_operand:SI 2 "immediate_operand" "L")] UNSPEC_ARC_SIMD_VSR8AWi))]
 900   "TARGET_SIMD_SET"
 901   "vsr8awi %0, %1, %2"
 902   [(set_attr "type" "simd_valign_with_acc")
 903    (set_attr "length" "4")
 904    (set_attr "cond" "nocond")])
 905
 906 (define_insn "vsr8i_insn"
 907   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 908         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 909                       (match_operand:SI 2 "immediate_operand" "L")] UNSPEC_ARC_SIMD_VSR8i))]
 910   "TARGET_SIMD_SET"
 911   "vsr8i %0, %1, %2"
 912   [(set_attr "type" "simd_valign")
 913    (set_attr "length" "4")
 914    (set_attr "cond" "nocond")])
 915
 916 ;; Va, Vb, u8 (simm) insns
 917
 918 (define_insn "vmvaw_insn"
 919   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 920         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 921                       (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMVAW))]
 922   "TARGET_SIMD_SET"
 923   "vmvaw %0, %1, %2"
 924   [(set_attr "type" "simd_vmove_with_acc")
 925    (set_attr "length" "4")
 926    (set_attr "cond" "nocond")])
 927
 928 (define_insn "vmvw_insn"
 929   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 930         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 931                       (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMVW))]
 932   "TARGET_SIMD_SET"
 933   "vmvw %0, %1, %2"
 934   [(set_attr "type" "simd_vmove")
 935    (set_attr "length" "4")
 936    (set_attr "cond" "nocond")])
 937
 938 (define_insn "vmvzw_insn"
 939   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 940         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 941                       (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMVZW))]
 942   "TARGET_SIMD_SET"
 943   "vmvzw %0, %1, %2"
 944   [(set_attr "type" "simd_vmove_else_zero")
 945    (set_attr "length" "4")
 946    (set_attr "cond" "nocond")])
 947
 948 (define_insn "vd6tapf_insn"
 949   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 950         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 951                       (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VD6TAPF))]
 952   "TARGET_SIMD_SET"
 953   "vd6tapf %0, %1, %2"
 954   [(set_attr "type" "simd_vspecial_4cycle")
 955    (set_attr "length" "4")
 956    (set_attr "cond" "nocond")])
 957
 958 ;; Va, rlimm, u8 (simm) insns
 959 (define_insn "vmovaw_insn"
 960   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 961         (unspec:V8HI [(match_operand:SI 1 "nonmemory_operand"  "r")
 962                       (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMOVAW))]
 963   "TARGET_SIMD_SET"
 964   "vmovaw %0, %1, %2"
 965   [(set_attr "type" "simd_vmove_with_acc")
 966    (set_attr "length" "4")
 967    (set_attr "cond" "nocond")])
 968
 969 (define_insn "vmovw_insn"
 970   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 971         (unspec:V8HI [(match_operand:SI 1 "nonmemory_operand"  "r")
 972                       (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMOVW))]
 973   "TARGET_SIMD_SET"
 974   "vmovw %0, %1, %2"
 975   [(set_attr "type" "simd_vmove")
 976    (set_attr "length" "4")
 977    (set_attr "cond" "nocond")])
 978
 979 (define_insn "vmovzw_insn"
 980   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 981         (unspec:V8HI [(match_operand:SI 1 "nonmemory_operand"  "r")
 982                       (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMOVZW))]
 983   "TARGET_SIMD_SET"
 984   "vmovzw %0, %1, %2"
 985   [(set_attr "type" "simd_vmove_else_zero")
 986    (set_attr "length" "4")
 987    (set_attr "cond" "nocond")])
 988
 989 ;; Va, rlimm, Ic insns
 990 (define_insn "vsr8_insn"
 991   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 992         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 993                       (match_operand:SI 2 "immediate_operand" "K")
 994                       (match_operand:V8HI 3 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VSR8))]
 995   "TARGET_SIMD_SET"
 996   "vsr8 %0, %1, i%2"
 997   [(set_attr "type" "simd_valign")
 998    (set_attr "length" "4")
 999    (set_attr "cond" "nocond")])
1000
1001 (define_insn "vasrw_insn"
1002   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
1003         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
1004                       (match_operand:SI 2 "immediate_operand" "K")
1005                       (match_operand:V8HI 3 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VASRW))]
1006   "TARGET_SIMD_SET"
1007   "vasrw %0, %1, i%2"
1008   [(set_attr "type" "simd_varith_1cycle")
1009    (set_attr "length" "4")
1010    (set_attr "cond" "nocond")])
1011
1012 (define_insn "vsr8aw_insn"
1013   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
1014         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
1015                       (match_operand:SI 2 "immediate_operand" "K")
1016                       (match_operand:V8HI 3 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VSR8AW))]
1017   "TARGET_SIMD_SET"
1018   "vsr8aw %0, %1, i%2"
1019   [(set_attr "type" "simd_valign_with_acc")
1020    (set_attr "length" "4")
1021    (set_attr "cond" "nocond")])
1022
1023 ;; Va, Vb insns
1024 (define_insn "vabsaw_insn"
1025   [(set (match_operand:V8HI 0 "vector_register_operand"  "=v")
1026         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VABSAW))]
1027   "TARGET_SIMD_SET"
1028   "vabsaw %0, %1"
1029   [(set_attr "type" "simd_varith_with_acc")
1030    (set_attr "length" "4")
1031    (set_attr "cond" "nocond")])
1032
1033 (define_insn "vabsw_insn"
1034   [(set (match_operand:V8HI 0 "vector_register_operand"  "=v")
1035         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VABSW))]
1036   "TARGET_SIMD_SET"
1037   "vabsw %0, %1"
1038   [(set_attr "type" "simd_varith_1cycle")
1039    (set_attr "length" "4")
1040    (set_attr "cond" "nocond")])
1041
1042 (define_insn "vaddsuw_insn"
1043   [(set (match_operand:V8HI 0 "vector_register_operand"  "=v")
1044         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VADDSUW))]
1045   "TARGET_SIMD_SET"
1046   "vaddsuw %0, %1"
1047   [(set_attr "type" "simd_varith_1cycle")
1048    (set_attr "length" "4")
1049    (set_attr "cond" "nocond")])
1050
1051 (define_insn "vsignw_insn"
1052   [(set (match_operand:V8HI 0 "vector_register_operand"  "=v")
1053         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VSIGNW))]
1054   "TARGET_SIMD_SET"
1055   "vsignw %0, %1"
1056   [(set_attr "type" "simd_varith_1cycle")
1057    (set_attr "length" "4")
1058    (set_attr "cond" "nocond")])
1059
1060 (define_insn "vexch1_insn"
1061   [(set (match_operand:V8HI 0 "vector_register_operand"  "=v")
1062         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VEXCH1))]
1063   "TARGET_SIMD_SET"
1064   "vexch1 %0, %1"
1065   [(set_attr "type" "simd_vpermute")
1066    (set_attr "length" "4")
1067    (set_attr "cond" "nocond")])
1068
1069 (define_insn "vexch2_insn"
1070   [(set (match_operand:V8HI 0 "vector_register_operand"  "=v")
1071         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VEXCH2))]
1072   "TARGET_SIMD_SET"
1073   "vexch2 %0, %1"
1074   [(set_attr "type" "simd_vpermute")
1075    (set_attr "length" "4")
1076    (set_attr "cond" "nocond")])
1077
1078 (define_insn "vexch4_insn"
1079   [(set (match_operand:V8HI 0 "vector_register_operand"  "=v")
1080         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VEXCH4))]
1081   "TARGET_SIMD_SET"
1082   "vexch4 %0, %1"
1083   [(set_attr "type" "simd_vpermute")
1084    (set_attr "length" "4")
1085    (set_attr "cond" "nocond")])
1086
1087 (define_insn "vupbaw_insn"
1088   [(set (match_operand:V8HI 0 "vector_register_operand"  "=v")
1089         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VUPBAW))]
1090   "TARGET_SIMD_SET"
1091   "vupbaw %0, %1"
1092   [(set_attr "type" "simd_vpack_with_acc")
1093    (set_attr "length" "4")
1094    (set_attr "cond" "nocond")])
1095
1096 (define_insn "vupbw_insn"
1097   [(set (match_operand:V8HI 0 "vector_register_operand"  "=v")
1098         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VUPBW))]
1099   "TARGET_SIMD_SET"
1100   "vupbw %0, %1"
1101   [(set_attr "type" "simd_vpack")
1102    (set_attr "length" "4")
1103    (set_attr "cond" "nocond")])
1104
1105 (define_insn "vupsbaw_insn"
1106   [(set (match_operand:V8HI 0 "vector_register_operand"  "=v")
1107         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VUPSBAW))]
1108   "TARGET_SIMD_SET"
1109   "vupsbaw %0, %1"
1110   [(set_attr "type" "simd_vpack_with_acc")
1111    (set_attr "length" "4")
1112    (set_attr "cond" "nocond")])
1113
1114 (define_insn "vupsbw_insn"
1115   [(set (match_operand:V8HI 0 "vector_register_operand"  "=v")
1116         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VUPSBW))]
1117   "TARGET_SIMD_SET"
1118   "vupsbw %0, %1"
1119   [(set_attr "type" "simd_vpack")
1120    (set_attr "length" "4")
1121    (set_attr "cond" "nocond")])
1122
1123 ; DMA setup instructions
1124 (define_insn "vdirun_insn"
1125   [(set (match_operand:SI 0 "arc_simd_dma_register_operand"           "=d")
1126         (unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand"  "r")
1127                              (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VDIRUN))]
1128   "TARGET_SIMD_SET"
1129   "vdirun %1, %2"
1130   [(set_attr "type" "simd_dma")
1131    (set_attr "length" "4")
1132    (set_attr "cond" "nocond")])
1133
1134 (define_insn "vdorun_insn"
1135   [(set (match_operand:SI 0 "arc_simd_dma_register_operand"              "=d")
1136         (unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand"     "r")
1137                              (match_operand:SI 2 "nonmemory_operand"     "r")] UNSPEC_ARC_SIMD_VDORUN))]
1138   "TARGET_SIMD_SET"
1139   "vdorun %1, %2"
1140   [(set_attr "type" "simd_dma")
1141    (set_attr "length" "4")
1142    (set_attr "cond" "nocond")])
1143
1144 (define_insn "vdiwr_insn"
1145   [(set (match_operand:SI 0 "arc_simd_dma_register_operand"           "=d,d")
1146         (unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand"  "r,Cal")] UNSPEC_ARC_SIMD_VDIWR))]
1147   "TARGET_SIMD_SET"
1148   "vdiwr %0, %1"
1149   [(set_attr "type" "simd_dma")
1150    (set_attr "length" "4,8")
1151    (set_attr "cond" "nocond,nocond")])
1152
1153 (define_insn "vdowr_insn"
1154   [(set (match_operand:SI 0 "arc_simd_dma_register_operand"           "=d,d")
1155         (unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand"  "r,Cal")] UNSPEC_ARC_SIMD_VDOWR))]
1156   "TARGET_SIMD_SET"
1157   "vdowr %0, %1"
1158   [(set_attr "type" "simd_dma")
1159    (set_attr "length" "4,8")
1160    (set_attr "cond" "nocond,nocond")])
1161
1162 ;; vector record and run instructions
1163 (define_insn "vrec_insn"
1164   [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand"  "r")] UNSPEC_ARC_SIMD_VREC)]
1165   "TARGET_SIMD_SET"
1166   "vrec %0"
1167   [(set_attr "type" "simd_vcontrol")
1168    (set_attr "length" "4")
1169    (set_attr "cond" "nocond")])
1170
1171 (define_insn "vrun_insn"
1172   [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand"  "r")] UNSPEC_ARC_SIMD_VRUN)]
1173   "TARGET_SIMD_SET"
1174   "vrun %0"
1175   [(set_attr "type" "simd_vcontrol")
1176    (set_attr "length" "4")
1177    (set_attr "cond" "nocond")])
1178
1179 (define_insn "vrecrun_insn"
1180   [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand"  "r")] UNSPEC_ARC_SIMD_VRECRUN)]
1181   "TARGET_SIMD_SET"
1182   "vrecrun %0"
1183   [(set_attr "type" "simd_vcontrol")
1184    (set_attr "length" "4")
1185    (set_attr "cond" "nocond")])
1186
1187 (define_insn "vendrec_insn"
1188   [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand"  "r")] UNSPEC_ARC_SIMD_VENDREC)]
1189   "TARGET_SIMD_SET"
1190   "vendrec %S0"
1191   [(set_attr "type" "simd_vcontrol")
1192    (set_attr "length" "4")
1193    (set_attr "cond" "nocond")])
1194
1195 (define_insn "vld32wh_insn"
1196   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
1197         (vec_concat:V8HI (zero_extend:V4HI (mem:V4QI (plus:SI (match_operand:SI 1 "immediate_operand" "P")
1198                                                               (zero_extend: SI (vec_select:HI (match_operand:V8HI 2 "vector_register_operand"  "v")
1199                                                                                               (parallel [(match_operand:SI 3 "immediate_operand" "L")]))))))
1200                          (vec_select:V4HI (match_dup 0)
1201                                           (parallel [(const_int 0)]))))]
1202   "TARGET_SIMD_SET"
1203   "vld32wh %0, [i%3,%1]"
1204   [(set_attr "type" "simd_vload")
1205    (set_attr "length" "4")
1206    (set_attr "cond" "nocond")])
1207
1208 (define_insn "vld32wl_insn"
1209   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
1210         (vec_concat:V8HI (vec_select:V4HI (match_dup 0)
1211                                           (parallel [(const_int 1)]))
1212                          (zero_extend:V4HI (mem:V4QI (plus:SI (match_operand:SI 1 "immediate_operand" "P")
1213                                                               (zero_extend: SI (vec_select:HI (match_operand:V8HI 2 "vector_register_operand"  "v")
1214                                                                                               (parallel [(match_operand:SI 3 "immediate_operand" "L")])))))) ))]
1215   "TARGET_SIMD_SET"
1216   "vld32wl %0, [i%3,%1]"
1217   [(set_attr "type" "simd_vload")
1218    (set_attr "length" "4")
1219    (set_attr "cond" "nocond")])
1220
1221 (define_insn "vld64w_insn"
1222   [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
1223         (zero_extend:V8HI (mem:V4HI (plus:SI (zero_extend:SI (vec_select:HI (match_operand:V8HI 1 "vector_register_operand"  "v")
1224                                                                             (parallel [(match_operand:SI 2 "immediate_operand" "L")])))
1225                                              (match_operand:SI 3 "immediate_operand" "P")))))]
1226  "TARGET_SIMD_SET"
1227  "vld64w %0, [i%2, %3]"
1228  [(set_attr "type" "simd_vload")
1229   (set_attr "length" "4")
1230   (set_attr "cond" "nocond")]
1231 )
1232
1233 (define_insn "vld64_insn"
1234   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
1235         (vec_concat:V8HI (vec_select:V4HI (match_dup 0)
1236                                           (parallel [(const_int 1)]))
1237                          (mem:V4HI (plus:SI (match_operand:SI 1 "immediate_operand" "P")
1238                                             (zero_extend: SI (vec_select:HI (match_operand:V8HI 2 "vector_register_operand"  "v")
1239                                                                             (parallel [(match_operand:SI 3 "immediate_operand" "L")]))))) ))]
1240   "TARGET_SIMD_SET"
1241   "vld64 %0, [i%3,%1]"
1242   [(set_attr "type" "simd_vload")
1243    (set_attr "length" "4")
1244    (set_attr "cond" "nocond")])
1245
1246 (define_insn "vld32_insn"
1247   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
1248         (vec_concat:V8HI (vec_select:V4HI (match_dup 0)
1249                                           (parallel [(const_int 1)]))
1250                          (vec_concat:V4HI  (vec_select:V2HI (match_dup 0)
1251                                                             (parallel [(const_int 1)]))
1252                                            (mem:V2HI (plus:SI (match_operand:SI 1 "immediate_operand" "P")
1253                                                               (zero_extend: SI (vec_select:HI (match_operand:V8HI 2 "vector_register_operand"  "v")
1254                                                                                               (parallel [(match_operand:SI 3 "immediate_operand" "L")])))))) ))]
1255   "TARGET_SIMD_SET"
1256   "vld32 %0, [i%3,%1]"
1257   [(set_attr "type" "simd_vload")
1258    (set_attr "length" "4")
1259    (set_attr "cond" "nocond")])
1260
1261 (define_insn "vst16_n_insn"
1262   [(set  (mem:HI (plus:SI (match_operand:SI 0 "immediate_operand" "P")
1263                           (zero_extend: SI (vec_select:HI (match_operand:V8HI 1 "vector_register_operand"  "v")
1264                                                           (parallel [(match_operand:SI 2 "immediate_operand" "L")])))))
1265          (vec_select:HI (match_operand:V8HI 3 "vector_register_operand" "v")
1266                         (parallel [(match_operand:SI 4 "immediate_operand" "L")])))]
1267  "TARGET_SIMD_SET"
1268  "vst16_%4 %3,[i%2, %0]"
1269  [(set_attr "type" "simd_vstore")
1270   (set_attr "length" "4")
1271   (set_attr "cond" "nocond")])
1272
1273 (define_insn "vst32_n_insn"
1274   [(set  (mem:SI (plus:SI (match_operand:SI 0 "immediate_operand" "P")
1275                           (zero_extend: SI (vec_select:HI (match_operand:V8HI 1 "vector_register_operand"  "v")
1276                                                           (parallel [(match_operand:SI 2 "immediate_operand" "L")])))))
1277          (vec_select:SI (unspec:V4SI [(match_operand:V8HI 3 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VCAST)
1278                         (parallel [(match_operand:SI 4 "immediate_operand" "L")])))]
1279  "TARGET_SIMD_SET"
1280  "vst32_%4 %3,[i%2, %0]"
1281  [(set_attr "type" "simd_vstore")
1282   (set_attr "length" "4")
1283   (set_attr "cond" "nocond")])
1284
1285 ;; SIMD unit interrupt
1286 (define_insn "vinti_insn"
1287   [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand"  "L")] UNSPEC_ARC_SIMD_VINTI)]
1288   "TARGET_SIMD_SET"
1289   "vinti %0"
1290   [(set_attr "type" "simd_vcontrol")
1291    (set_attr "length" "4")
1292    (set_attr "cond" "nocond")])