gcc/config/arc/simdext.md

   1 ;; Machine description of the Synopsys DesignWare ARC cpu for GNU C compiler
   2 ;; Copyright (C) 2007-2015 Free Software Foundation, Inc.
   3
   4 ;; This file is part of GCC.
   5
   6 ;; GCC is free software; you can redistribute it and/or modify
   7 ;; it under the terms of the GNU General Public License as published by
   8 ;; the Free Software Foundation; either version 3, or (at your option)
   9 ;; any later version.
  10
  11 ;; GCC is distributed in the hope that it will be useful,
  12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ;; GNU General Public License for more details.
  15
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING3.  If not see
  18 ;; <http://www.gnu.org/licenses/>.
  19
  20 (define_c_enum "unspec" [
  21   ;; Va, Vb, Vc builtins
  22   UNSPEC_ARC_SIMD_VADDAW
  23   UNSPEC_ARC_SIMD_VADDW
  24   UNSPEC_ARC_SIMD_VAVB
  25   UNSPEC_ARC_SIMD_VAVRB
  26   UNSPEC_ARC_SIMD_VDIFAW
  27   UNSPEC_ARC_SIMD_VDIFW
  28   UNSPEC_ARC_SIMD_VMAXAW
  29   UNSPEC_ARC_SIMD_VMAXW
  30   UNSPEC_ARC_SIMD_VMINAW
  31   UNSPEC_ARC_SIMD_VMINW
  32   UNSPEC_ARC_SIMD_VMULAW
  33   UNSPEC_ARC_SIMD_VMULFAW
  34   UNSPEC_ARC_SIMD_VMULFW
  35   UNSPEC_ARC_SIMD_VMULW
  36   UNSPEC_ARC_SIMD_VSUBAW
  37   UNSPEC_ARC_SIMD_VSUBW
  38   UNSPEC_ARC_SIMD_VSUMMW
  39   UNSPEC_ARC_SIMD_VAND
  40   UNSPEC_ARC_SIMD_VANDAW
  41   UNSPEC_ARC_SIMD_VBIC
  42   UNSPEC_ARC_SIMD_VBICAW
  43   UNSPEC_ARC_SIMD_VOR
  44   UNSPEC_ARC_SIMD_VXOR
  45   UNSPEC_ARC_SIMD_VXORAW
  46   UNSPEC_ARC_SIMD_VEQW
  47   UNSPEC_ARC_SIMD_VLEW
  48   UNSPEC_ARC_SIMD_VLTW
  49   UNSPEC_ARC_SIMD_VNEW
  50   UNSPEC_ARC_SIMD_VMR1AW
  51   UNSPEC_ARC_SIMD_VMR1W
  52   UNSPEC_ARC_SIMD_VMR2AW
  53   UNSPEC_ARC_SIMD_VMR2W
  54   UNSPEC_ARC_SIMD_VMR3AW
  55   UNSPEC_ARC_SIMD_VMR3W
  56   UNSPEC_ARC_SIMD_VMR4AW
  57   UNSPEC_ARC_SIMD_VMR4W
  58   UNSPEC_ARC_SIMD_VMR5AW
  59   UNSPEC_ARC_SIMD_VMR5W
  60   UNSPEC_ARC_SIMD_VMR6AW
  61   UNSPEC_ARC_SIMD_VMR6W
  62   UNSPEC_ARC_SIMD_VMR7AW
  63   UNSPEC_ARC_SIMD_VMR7W
  64   UNSPEC_ARC_SIMD_VMRB
  65   UNSPEC_ARC_SIMD_VH264F
  66   UNSPEC_ARC_SIMD_VH264FT
  67   UNSPEC_ARC_SIMD_VH264FW
  68   UNSPEC_ARC_SIMD_VVC1F
  69   UNSPEC_ARC_SIMD_VVC1FT
  70   ;; Va, Vb, rc/limm builtins
  71   UNSPEC_ARC_SIMD_VBADDW
  72   UNSPEC_ARC_SIMD_VBMAXW
  73   UNSPEC_ARC_SIMD_VBMINW
  74   UNSPEC_ARC_SIMD_VBMULAW
  75   UNSPEC_ARC_SIMD_VBMULFW
  76   UNSPEC_ARC_SIMD_VBMULW
  77   UNSPEC_ARC_SIMD_VBRSUBW
  78   UNSPEC_ARC_SIMD_VBSUBW
  79
  80   ;; Va, Vb, Ic builtins
  81   UNSPEC_ARC_SIMD_VASRW
  82   UNSPEC_ARC_SIMD_VSR8
  83   UNSPEC_ARC_SIMD_VSR8AW
  84
  85   ;; Va, Vb, Ic builtins
  86   UNSPEC_ARC_SIMD_VASRRWi
  87   UNSPEC_ARC_SIMD_VASRSRWi
  88   UNSPEC_ARC_SIMD_VASRWi
  89   UNSPEC_ARC_SIMD_VASRPWBi
  90   UNSPEC_ARC_SIMD_VASRRPWBi
  91   UNSPEC_ARC_SIMD_VSR8AWi
  92   UNSPEC_ARC_SIMD_VSR8i
  93
  94   ;; Va, Vb, u8 (simm) builtins
  95   UNSPEC_ARC_SIMD_VMVAW
  96   UNSPEC_ARC_SIMD_VMVW
  97   UNSPEC_ARC_SIMD_VMVZW
  98   UNSPEC_ARC_SIMD_VD6TAPF
  99
 100   ;; Va, rlimm, u8 (simm) builtins
 101   UNSPEC_ARC_SIMD_VMOVAW
 102   UNSPEC_ARC_SIMD_VMOVW
 103   UNSPEC_ARC_SIMD_VMOVZW
 104
 105   ;; Va, Vb builtins
 106   UNSPEC_ARC_SIMD_VABSAW
 107   UNSPEC_ARC_SIMD_VABSW
 108   UNSPEC_ARC_SIMD_VADDSUW
 109   UNSPEC_ARC_SIMD_VSIGNW
 110   UNSPEC_ARC_SIMD_VEXCH1
 111   UNSPEC_ARC_SIMD_VEXCH2
 112   UNSPEC_ARC_SIMD_VEXCH4
 113   UNSPEC_ARC_SIMD_VUPBAW
 114   UNSPEC_ARC_SIMD_VUPBW
 115   UNSPEC_ARC_SIMD_VUPSBAW
 116   UNSPEC_ARC_SIMD_VUPSBW
 117
 118   UNSPEC_ARC_SIMD_VDIRUN
 119   UNSPEC_ARC_SIMD_VDORUN
 120   UNSPEC_ARC_SIMD_VDIWR
 121   UNSPEC_ARC_SIMD_VDOWR
 122
 123   UNSPEC_ARC_SIMD_VREC
 124   UNSPEC_ARC_SIMD_VRUN
 125   UNSPEC_ARC_SIMD_VRECRUN
 126   UNSPEC_ARC_SIMD_VENDREC
 127
 128   UNSPEC_ARC_SIMD_VCAST
 129   UNSPEC_ARC_SIMD_VINTI
 130   ])
 131
 132 ;; Scheduler descriptions for the simd instructions
 133 (define_insn_reservation "simd_lat_0_insn" 1
 134   (eq_attr "type" "simd_dma, simd_vstore, simd_vcontrol")
 135   "issue+simd_unit")
 136
 137 (define_insn_reservation "simd_lat_1_insn" 2
 138        (eq_attr "type" "simd_vcompare, simd_vlogic,
 139                         simd_vmove_else_zero, simd_varith_1cycle")
 140   "issue+simd_unit, nothing")
 141
 142 (define_insn_reservation "simd_lat_2_insn" 3
 143        (eq_attr "type" "simd_valign, simd_vpermute,
 144                         simd_vpack, simd_varith_2cycle")
 145   "issue+simd_unit, nothing*2")
 146
 147 (define_insn_reservation "simd_lat_3_insn" 4
 148        (eq_attr "type" "simd_valign_with_acc, simd_vpack_with_acc,
 149                         simd_vlogic_with_acc, simd_vload128,
 150                         simd_vmove_with_acc, simd_vspecial_3cycle,
 151                         simd_varith_with_acc")
 152   "issue+simd_unit, nothing*3")
 153
 154 (define_insn_reservation "simd_lat_4_insn" 5
 155        (eq_attr "type" "simd_vload, simd_vmove, simd_vspecial_4cycle")
 156   "issue+simd_unit, nothing*4")
 157
 158 (define_expand "movv8hi"
 159   [(set (match_operand:V8HI 0 "general_operand" "")
 160         (match_operand:V8HI 1 "general_operand" ""))]
 161   ""
 162   "
 163 {
 164   /* Everything except mem = const or mem = mem can be done easily.  */
 165
 166   if (GET_CODE (operands[0]) == MEM && GET_CODE(operands[1]) == MEM)
 167     operands[1] = force_reg (V8HImode, operands[1]);
 168 }")
 169
 170 ;; This pattern should appear before the movv8hi_insn pattern
 171 (define_insn "vld128_insn"
 172   [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
 173         (mem:V8HI (plus:SI (zero_extend:SI (vec_select:HI (match_operand:V8HI 1 "vector_register_operand"  "v")
 174                                                           (parallel [(match_operand:SI 2 "immediate_operand" "L")])))
 175                            (match_operand:SI 3 "immediate_operand" "P"))))]
 176  "TARGET_SIMD_SET"
 177  "vld128 %0, [i%2, %3]"
 178  [(set_attr "type" "simd_vload128")
 179   (set_attr "length" "4")
 180   (set_attr "cond" "nocond")]
 181 )
 182
 183 (define_insn "vst128_insn"
 184   [(set (mem:V8HI (plus:SI (zero_extend:SI (vec_select:HI (match_operand:V8HI 0 "vector_register_operand"  "v")
 185                                                           (parallel [(match_operand:SI 1 "immediate_operand" "L")])))
 186                            (match_operand:SI 2 "immediate_operand" "P")))
 187         (match_operand:V8HI 3 "vector_register_operand" "=v"))]
 188  "TARGET_SIMD_SET"
 189  "vst128 %3, [i%1, %2]"
 190  [(set_attr "type" "simd_vstore")
 191   (set_attr "length" "4")
 192   (set_attr "cond" "nocond")]
 193 )
 194
 195 (define_insn "vst64_insn"
 196   [(set (mem:V4HI (plus:SI (zero_extend:SI (vec_select:HI (match_operand:V8HI 0 "vector_register_operand"  "v")
 197                                                           (parallel [(match_operand:SI 1 "immediate_operand" "L")])))
 198                            (match_operand:SI 2 "immediate_operand" "P")))
 199         (vec_select:V4HI (match_operand:V8HI 3 "vector_register_operand" "=v")
 200                          (parallel [(const_int 0)])))]
 201  "TARGET_SIMD_SET"
 202  "vst64 %3, [i%1, %2]"
 203  [(set_attr "type" "simd_vstore")
 204   (set_attr "length" "4")
 205   (set_attr "cond" "nocond")]
 206 )
 207
 208 (define_insn "movv8hi_insn"
 209   [(set (match_operand:V8HI 0 "vector_register_or_memory_operand" "=v,m,v")
 210         (match_operand:V8HI 1 "vector_register_or_memory_operand" "m,v,v"))]
 211   "TARGET_SIMD_SET && !(GET_CODE (operands[0]) == MEM && GET_CODE(operands[1]) == MEM)"
 212   "@
 213     vld128r %0, %1
 214     vst128r %1, %0
 215     vmvzw %0,%1,0xffff"
 216   [(set_attr "type" "simd_vload128,simd_vstore,simd_vmove_else_zero")
 217    (set_attr "length" "8,8,4")
 218    (set_attr "cond" "nocond, nocond, nocond")])
 219
 220 (define_insn "movti_insn"
 221   [(set (match_operand:TI 0 "vector_register_or_memory_operand" "=v,m,v")
 222         (match_operand:TI 1 "vector_register_or_memory_operand" "m,v,v"))]
 223   ""
 224   "@
 225     vld128r %0, %1
 226     vst128r %1, %0
 227     vmvzw %0,%1,0xffff"
 228   [(set_attr "type" "simd_vload128,simd_vstore,simd_vmove_else_zero")
 229    (set_attr "length" "8,8,4")
 230    (set_attr "cond" "nocond, nocond, nocond")])
 231
 232 ;; (define_insn "*movv8hi_insn_rr"
 233 ;;   [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
 234 ;;      (match_operand:V8HI 1 "vector_register_operand" "v"))]
 235 ;;   ""
 236 ;;   "mov reg,reg"
 237 ;;   [(set_attr "length" "8")
 238 ;;   (set_attr "type" "move")])
 239
 240 ;; (define_insn "*movv8_out"
 241 ;;   [(set (match_operand:V8HI 0 "memory_operand" "=m")
 242 ;;      (match_operand:V8HI 1 "vector_register_operand" "v"))]
 243 ;;   ""
 244 ;;   "mov out"
 245 ;;   [(set_attr "length" "8")
 246 ;;   (set_attr "type" "move")])
 247
 248
 249 ;; (define_insn "addv8hi3"
 250 ;;   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 251 ;;      (plus:V8HI (match_operand:V8HI 1 "vector_register_operand"  "v")
 252 ;;                 (match_operand:V8HI 2 "vector_register_operand" "v")))]
 253 ;;   "TARGET_SIMD_SET"
 254 ;;   "vaddw %0, %1, %2"
 255 ;;   [(set_attr "length" "8")
 256 ;;    (set_attr "cond" "nocond")])
 257
 258 ;; (define_insn "vaddw_insn"
 259 ;;   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 260 ;;      (unspec [(match_operand:V8HI 1 "vector_register_operand"  "v")
 261 ;;                       (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VADDW))]
 262 ;;   "TARGET_SIMD_SET"
 263 ;;   "vaddw %0, %1, %2"
 264 ;;   [(set_attr "length" "8")
 265 ;;    (set_attr "cond" "nocond")])
 266
 267 ;; V V V Insns
 268 (define_insn "vaddaw_insn"
 269   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 270         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 271                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VADDAW))]
 272   "TARGET_SIMD_SET"
 273   "vaddaw %0, %1, %2"
 274   [(set_attr "type" "simd_varith_with_acc")
 275    (set_attr "length" "4")
 276    (set_attr "cond" "nocond")])
 277
 278 (define_insn "vaddw_insn"
 279   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 280         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 281                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VADDW))]
 282   "TARGET_SIMD_SET"
 283   "vaddw %0, %1, %2"
 284   [(set_attr "type" "simd_varith_1cycle")
 285    (set_attr "length" "4")
 286    (set_attr "cond" "nocond")])
 287
 288 (define_insn "vavb_insn"
 289   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 290         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 291                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VAVB))]
 292   "TARGET_SIMD_SET"
 293   "vavb %0, %1, %2"
 294   [(set_attr "type" "simd_varith_1cycle")
 295    (set_attr "length" "4")
 296    (set_attr "cond" "nocond")])
 297
 298 (define_insn "vavrb_insn"
 299   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 300         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 301                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VAVRB))]
 302   "TARGET_SIMD_SET"
 303   "vavrb %0, %1, %2"
 304   [(set_attr "type" "simd_varith_1cycle")
 305    (set_attr "length" "4")
 306    (set_attr "cond" "nocond")])
 307
 308 (define_insn "vdifaw_insn"
 309   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 310         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 311                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VDIFAW))]
 312   "TARGET_SIMD_SET"
 313   "vdifaw %0, %1, %2"
 314   [(set_attr "type" "simd_varith_with_acc")
 315    (set_attr "length" "4")
 316    (set_attr "cond" "nocond")])
 317
 318 (define_insn "vdifw_insn"
 319   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 320         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 321                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VDIFW))]
 322   "TARGET_SIMD_SET"
 323   "vdifw %0, %1, %2"
 324   [(set_attr "type" "simd_varith_1cycle")
 325    (set_attr "length" "4")
 326    (set_attr "cond" "nocond")])
 327
 328 (define_insn "vmaxaw_insn"
 329   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 330         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 331                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMAXAW))]
 332   "TARGET_SIMD_SET"
 333   "vmaxaw %0, %1, %2"
 334   [(set_attr "type" "simd_varith_with_acc")
 335    (set_attr "length" "4")
 336    (set_attr "cond" "nocond")])
 337
 338 (define_insn "vmaxw_insn"
 339   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 340         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 341                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMAXW))]
 342   "TARGET_SIMD_SET"
 343   "vmaxw %0, %1, %2"
 344   [(set_attr "type" "simd_varith_1cycle")
 345    (set_attr "length" "4")
 346    (set_attr "cond" "nocond")])
 347
 348 (define_insn "vminaw_insn"
 349   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 350         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 351                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMINAW))]
 352   "TARGET_SIMD_SET"
 353   "vminaw %0, %1, %2"
 354   [(set_attr "type" "simd_varith_with_acc")
 355    (set_attr "length" "4")
 356    (set_attr "cond" "nocond")])
 357
 358 (define_insn "vminw_insn"
 359   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 360         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 361                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMINW))]
 362   "TARGET_SIMD_SET"
 363   "vminw %0, %1, %2"
 364   [(set_attr "type" "simd_varith_1cycle")
 365    (set_attr "length" "4")
 366    (set_attr "cond" "nocond")])
 367
 368 (define_insn "vmulaw_insn"
 369   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 370         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 371                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMULAW))]
 372   "TARGET_SIMD_SET"
 373   "vmulaw %0, %1, %2"
 374   [(set_attr "type" "simd_varith_with_acc")
 375    (set_attr "length" "4")
 376    (set_attr "cond" "nocond")])
 377
 378 (define_insn "vmulfaw_insn"
 379   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 380         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 381                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMULFAW))]
 382   "TARGET_SIMD_SET"
 383   "vmulfaw %0, %1, %2"
 384   [(set_attr "type" "simd_varith_with_acc")
 385    (set_attr "length" "4")
 386    (set_attr "cond" "nocond")])
 387
 388 (define_insn "vmulfw_insn"
 389   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 390         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 391                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMULFW))]
 392   "TARGET_SIMD_SET"
 393   "vmulfw %0, %1, %2"
 394   [(set_attr "type" "simd_varith_2cycle")
 395    (set_attr "length" "4")
 396    (set_attr "cond" "nocond")])
 397
 398 (define_insn "vmulw_insn"
 399   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 400         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 401                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMULW))]
 402   "TARGET_SIMD_SET"
 403   "vmulw %0, %1, %2"
 404   [(set_attr "type" "simd_varith_2cycle")
 405    (set_attr "length" "4")
 406    (set_attr "cond" "nocond")])
 407
 408 (define_insn "vsubaw_insn"
 409   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 410         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 411                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VSUBAW))]
 412   "TARGET_SIMD_SET"
 413   "vsubaw %0, %1, %2"
 414   [(set_attr "type" "simd_varith_with_acc")
 415    (set_attr "length" "4")
 416    (set_attr "cond" "nocond")])
 417
 418 (define_insn "vsubw_insn"
 419   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 420         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 421                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VSUBW))]
 422   "TARGET_SIMD_SET"
 423   "vsubw %0, %1, %2"
 424   [(set_attr "type" "simd_varith_1cycle")
 425    (set_attr "length" "4")
 426    (set_attr "cond" "nocond")])
 427
 428 (define_insn "vsummw_insn"
 429   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 430         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 431                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VSUMMW))]
 432   "TARGET_SIMD_SET"
 433   "vsummw %0, %1, %2"
 434   [(set_attr "type" "simd_varith_2cycle")
 435    (set_attr "length" "4")
 436    (set_attr "cond" "nocond")])
 437
 438 (define_insn "vand_insn"
 439   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 440         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 441                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VAND))]
 442   "TARGET_SIMD_SET"
 443   "vand %0, %1, %2"
 444   [(set_attr "type" "simd_vlogic")
 445    (set_attr "length" "4")
 446    (set_attr "cond" "nocond")])
 447
 448 (define_insn "vandaw_insn"
 449   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 450         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 451                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VANDAW))]
 452   "TARGET_SIMD_SET"
 453   "vandaw %0, %1, %2"
 454   [(set_attr "type" "simd_vlogic_with_acc")
 455    (set_attr "length" "4")
 456    (set_attr "cond" "nocond")])
 457
 458 (define_insn "vbic_insn"
 459   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 460         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 461                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VBIC))]
 462   "TARGET_SIMD_SET"
 463   "vbic %0, %1, %2"
 464   [(set_attr "type" "simd_vlogic")
 465    (set_attr "length" "4")
 466    (set_attr "cond" "nocond")])
 467
 468 (define_insn "vbicaw_insn"
 469   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 470         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 471                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VBICAW))]
 472   "TARGET_SIMD_SET"
 473   "vbicaw %0, %1, %2"
 474   [(set_attr "type" "simd_vlogic_with_acc")
 475    (set_attr "length" "4")
 476    (set_attr "cond" "nocond")])
 477
 478 (define_insn "vor_insn"
 479   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 480         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 481                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VOR))]
 482   "TARGET_SIMD_SET"
 483   "vor %0, %1, %2"
 484   [(set_attr "type" "simd_vlogic")
 485    (set_attr "length" "4")
 486    (set_attr "cond" "nocond")])
 487
 488 (define_insn "vxor_insn"
 489   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 490         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 491                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VXOR))]
 492   "TARGET_SIMD_SET"
 493   "vxor %0, %1, %2"
 494   [(set_attr "type" "simd_vlogic")
 495    (set_attr "length" "4")
 496    (set_attr "cond" "nocond")])
 497
 498 (define_insn "vxoraw_insn"
 499   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 500         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 501                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VXORAW))]
 502   "TARGET_SIMD_SET"
 503   "vxoraw %0, %1, %2"
 504   [(set_attr "type" "simd_vlogic_with_acc")
 505    (set_attr "length" "4")
 506    (set_attr "cond" "nocond")])
 507
 508 (define_insn "veqw_insn"
 509   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 510         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 511                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VEQW))]
 512   "TARGET_SIMD_SET"
 513   "veqw %0, %1, %2"
 514   [(set_attr "type" "simd_vcompare")
 515    (set_attr "length" "4")
 516    (set_attr "cond" "nocond")])
 517
 518 (define_insn "vlew_insn"
 519   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 520         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 521                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VLEW))]
 522   "TARGET_SIMD_SET"
 523   "vlew %0, %1, %2"
 524   [(set_attr "type" "simd_vcompare")
 525    (set_attr "length" "4")
 526    (set_attr "cond" "nocond")])
 527
 528 (define_insn "vltw_insn"
 529   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 530         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 531                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VLTW))]
 532   "TARGET_SIMD_SET"
 533   "vltw %0, %1, %2"
 534   [(set_attr "type" "simd_vcompare")
 535    (set_attr "length" "4")
 536    (set_attr "cond" "nocond")])
 537
 538 (define_insn "vnew_insn"
 539   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 540         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 541                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VNEW))]
 542   "TARGET_SIMD_SET"
 543   "vnew %0, %1, %2"
 544   [(set_attr "type" "simd_vcompare")
 545    (set_attr "length" "4")
 546    (set_attr "cond" "nocond")])
 547
 548 (define_insn "vmr1aw_insn"
 549   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 550         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 551                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR1AW))]
 552   "TARGET_SIMD_SET"
 553   "vmr1aw %0, %1, %2"
 554   [(set_attr "type" "simd_valign_with_acc")
 555    (set_attr "length" "4")
 556    (set_attr "cond" "nocond")])
 557
 558 (define_insn "vmr1w_insn"
 559   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 560         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 561                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR1W))]
 562   "TARGET_SIMD_SET"
 563   "vmr1w %0, %1, %2"
 564   [(set_attr "type" "simd_valign")
 565    (set_attr "length" "4")
 566    (set_attr "cond" "nocond")])
 567
 568 (define_insn "vmr2aw_insn"
 569   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 570         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 571                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR2AW))]
 572   "TARGET_SIMD_SET"
 573   "vmr2aw %0, %1, %2"
 574   [(set_attr "type" "simd_valign_with_acc")
 575    (set_attr "length" "4")
 576    (set_attr "cond" "nocond")])
 577
 578 (define_insn "vmr2w_insn"
 579   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 580         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 581                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR2W))]
 582   "TARGET_SIMD_SET"
 583   "vmr2w %0, %1, %2"
 584   [(set_attr "type" "simd_valign")
 585    (set_attr "length" "4")
 586    (set_attr "cond" "nocond")])
 587
 588 (define_insn "vmr3aw_insn"
 589   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 590         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 591                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR3AW))]
 592   "TARGET_SIMD_SET"
 593   "vmr3aw %0, %1, %2"
 594   [(set_attr "type" "simd_valign_with_acc")
 595    (set_attr "length" "4")
 596    (set_attr "cond" "nocond")])
 597
 598 (define_insn "vmr3w_insn"
 599   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 600         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 601                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR3W))]
 602   "TARGET_SIMD_SET"
 603   "vmr3w %0, %1, %2"
 604   [(set_attr "type" "simd_valign")
 605    (set_attr "length" "4")
 606    (set_attr "cond" "nocond")])
 607
 608 (define_insn "vmr4aw_insn"
 609   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 610         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 611                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR4AW))]
 612   "TARGET_SIMD_SET"
 613   "vmr4aw %0, %1, %2"
 614   [(set_attr "type" "simd_valign_with_acc")
 615    (set_attr "length" "4")
 616    (set_attr "cond" "nocond")])
 617
 618 (define_insn "vmr4w_insn"
 619   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 620         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 621                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR4W))]
 622   "TARGET_SIMD_SET"
 623   "vmr4w %0, %1, %2"
 624   [(set_attr "type" "simd_valign")
 625    (set_attr "length" "4")
 626    (set_attr "cond" "nocond")])
 627
 628 (define_insn "vmr5aw_insn"
 629   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 630         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 631                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR5AW))]
 632   "TARGET_SIMD_SET"
 633   "vmr5aw %0, %1, %2"
 634   [(set_attr "type" "simd_valign_with_acc")
 635    (set_attr "length" "4")
 636    (set_attr "cond" "nocond")])
 637
 638 (define_insn "vmr5w_insn"
 639   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 640         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 641                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR5W))]
 642   "TARGET_SIMD_SET"
 643   "vmr5w %0, %1, %2"
 644   [(set_attr "type" "simd_valign")
 645    (set_attr "length" "4")
 646    (set_attr "cond" "nocond")])
 647
 648 (define_insn "vmr6aw_insn"
 649   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 650         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 651                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR6AW))]
 652   "TARGET_SIMD_SET"
 653   "vmr6aw %0, %1, %2"
 654   [(set_attr "type" "simd_valign_with_acc")
 655    (set_attr "length" "4")
 656    (set_attr "cond" "nocond")])
 657
 658 (define_insn "vmr6w_insn"
 659   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 660         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 661                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR6W))]
 662   "TARGET_SIMD_SET"
 663   "vmr6w %0, %1, %2"
 664   [(set_attr "type" "simd_valign")
 665    (set_attr "length" "4")
 666    (set_attr "cond" "nocond")])
 667
 668 (define_insn "vmr7aw_insn"
 669   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 670         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 671                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR7AW))]
 672   "TARGET_SIMD_SET"
 673   "vmr7aw %0, %1, %2"
 674   [(set_attr "type" "simd_valign_with_acc")
 675    (set_attr "length" "4")
 676    (set_attr "cond" "nocond")])
 677
 678 (define_insn "vmr7w_insn"
 679   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 680         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 681                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR7W))]
 682   "TARGET_SIMD_SET"
 683   "vmr7w %0, %1, %2"
 684   [(set_attr "type" "simd_valign")
 685    (set_attr "length" "4")
 686    (set_attr "cond" "nocond")])
 687
 688 (define_insn "vmrb_insn"
 689   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 690         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 691                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMRB))]
 692   "TARGET_SIMD_SET"
 693   "vmrb %0, %1, %2"
 694   [(set_attr "type" "simd_valign")
 695    (set_attr "length" "4")
 696    (set_attr "cond" "nocond")])
 697
 698 (define_insn "vh264f_insn"
 699   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 700         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 701                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VH264F))]
 702   "TARGET_SIMD_SET"
 703   "vh264f %0, %1, %2"
 704   [(set_attr "type" "simd_vspecial_3cycle")
 705    (set_attr "length" "4")
 706    (set_attr "cond" "nocond")])
 707
 708 (define_insn "vh264ft_insn"
 709   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 710         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 711                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VH264FT))]
 712   "TARGET_SIMD_SET"
 713   "vh264ft %0, %1, %2"
 714   [(set_attr "type" "simd_vspecial_3cycle")
 715    (set_attr "length" "4")
 716    (set_attr "cond" "nocond")])
 717
 718 (define_insn "vh264fw_insn"
 719   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 720         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 721                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VH264FW))]
 722   "TARGET_SIMD_SET"
 723   "vh264fw %0, %1, %2"
 724   [(set_attr "type" "simd_vspecial_3cycle")
 725    (set_attr "length" "4")
 726    (set_attr "cond" "nocond")])
 727
 728 (define_insn "vvc1f_insn"
 729   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 730         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 731                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VVC1F))]
 732   "TARGET_SIMD_SET"
 733   "vvc1f %0, %1, %2"
 734   [(set_attr "type" "simd_vspecial_3cycle")
 735    (set_attr "length" "4")
 736    (set_attr "cond" "nocond")])
 737
 738 (define_insn "vvc1ft_insn"
 739   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 740         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 741                          (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VVC1FT))]
 742   "TARGET_SIMD_SET"
 743   "vvc1ft %0, %1, %2"
 744   [(set_attr "type" "simd_vspecial_3cycle")
 745    (set_attr "length" "4")
 746    (set_attr "cond" "nocond")])
 747
 748
 749
 750 ;;---
 751 ;; V V r/limm Insns
 752
 753 ;; (define_insn "vbaddw_insn"
 754 ;;   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 755 ;;      (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 756 ;;                            (match_operand:SI 2 "nonmemory_operand" "rCal")] UNSPEC_ARC_SIMD_VBADDW))]
 757 ;;   "TARGET_SIMD_SET"
 758 ;;   "vbaddw %0, %1, %2"
 759 ;;   [(set_attr "length" "4")
 760 ;;    (set_attr "cond" "nocond")])
 761
 762 (define_insn "vbaddw_insn"
 763   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 764         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 765                       (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBADDW))]
 766   "TARGET_SIMD_SET"
 767   "vbaddw %0, %1, %2"
 768   [(set_attr "type" "simd_varith_1cycle")
 769    (set_attr "length" "4")
 770    (set_attr "cond" "nocond")])
 771
 772 (define_insn "vbmaxw_insn"
 773   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 774         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 775                       (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBMAXW))]
 776   "TARGET_SIMD_SET"
 777   "vbmaxw %0, %1, %2"
 778   [(set_attr "type" "simd_varith_1cycle")
 779    (set_attr "length" "4")
 780    (set_attr "cond" "nocond")])
 781
 782 (define_insn "vbminw_insn"
 783   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 784         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 785                       (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBMINW))]
 786   "TARGET_SIMD_SET"
 787   "vbminw %0, %1, %2"
 788   [(set_attr "type" "simd_varith_1cycle")
 789    (set_attr "length" "4")
 790    (set_attr "cond" "nocond")])
 791
 792 (define_insn "vbmulaw_insn"
 793   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 794         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 795                       (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBMULAW))]
 796   "TARGET_SIMD_SET"
 797   "vbmulaw %0, %1, %2"
 798   [(set_attr "type" "simd_varith_with_acc")
 799    (set_attr "length" "4")
 800    (set_attr "cond" "nocond")])
 801
 802 (define_insn "vbmulfw_insn"
 803   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 804         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 805                       (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBMULFW))]
 806   "TARGET_SIMD_SET"
 807   "vbmulfw %0, %1, %2"
 808   [(set_attr "type" "simd_varith_2cycle")
 809    (set_attr "length" "4")
 810    (set_attr "cond" "nocond")])
 811
 812 (define_insn "vbmulw_insn"
 813   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 814         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 815                       (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBMULW))]
 816   "TARGET_SIMD_SET"
 817   "vbmulw %0, %1, %2"
 818   [(set_attr "type" "simd_varith_2cycle")
 819    (set_attr "length" "4")
 820    (set_attr "cond" "nocond")])
 821
 822 (define_insn "vbrsubw_insn"
 823   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 824         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 825                      (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBRSUBW))]
 826   "TARGET_SIMD_SET"
 827   "vbrsubw %0, %1, %2"
 828   [(set_attr "type" "simd_varith_1cycle")
 829    (set_attr "length" "4")
 830    (set_attr "cond" "nocond")])
 831
 832 (define_insn "vbsubw_insn"
 833   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 834         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 835                       (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBSUBW))]
 836   "TARGET_SIMD_SET"
 837   "vbsubw %0, %1, %2"
 838   [(set_attr "type" "simd_varith_1cycle")
 839    (set_attr "length" "4")
 840    (set_attr "cond" "nocond")])
 841 ; Va, Vb, Ic instructions
 842
 843 ; Va, Vb, u6 instructions
 844 (define_insn "vasrrwi_insn"
 845   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 846         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 847                       (match_operand:SI 2 "immediate_operand" "L")] UNSPEC_ARC_SIMD_VASRRWi))]
 848   "TARGET_SIMD_SET"
 849   "vasrrwi %0, %1, %2"
 850   [(set_attr "type" "simd_varith_2cycle")
 851    (set_attr "length" "4")
 852    (set_attr "cond" "nocond")])
 853
 854 (define_insn "vasrsrwi_insn"
 855   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 856         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 857                      (match_operand:SI 2 "immediate_operand" "L")] UNSPEC_ARC_SIMD_VASRSRWi))]
 858   "TARGET_SIMD_SET"
 859   "vasrsrwi %0, %1, %2"
 860   [(set_attr "type" "simd_varith_2cycle")
 861    (set_attr "length" "4")
 862    (set_attr "cond" "nocond")])
 863
 864 (define_insn "vasrwi_insn"
 865   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 866         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 867                       (match_operand:SI 2 "immediate_operand" "L")] UNSPEC_ARC_SIMD_VASRWi))]
 868   "TARGET_SIMD_SET"
 869   "vasrwi %0, %1, %2"
 870   [(set_attr "type" "simd_varith_1cycle")
 871    (set_attr "length" "4")
 872    (set_attr "cond" "nocond")])
 873
 874 (define_insn "vasrpwbi_insn"
 875   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 876         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 877                       (match_operand:SI 2 "immediate_operand" "L")] UNSPEC_ARC_SIMD_VASRPWBi))]
 878   "TARGET_SIMD_SET"
 879   "vasrpwbi %0, %1, %2"
 880   [(set_attr "type" "simd_vpack")
 881    (set_attr "length" "4")
 882    (set_attr "cond" "nocond")])
 883
 884 (define_insn "vasrrpwbi_insn"
 885   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 886         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 887                       (match_operand:SI 2 "immediate_operand" "L")] UNSPEC_ARC_SIMD_VASRRPWBi))]
 888   "TARGET_SIMD_SET"
 889   "vasrrpwbi %0, %1, %2"
 890   [(set_attr "type" "simd_vpack")
 891    (set_attr "length" "4")
 892    (set_attr "cond" "nocond")])
 893
 894 (define_insn "vsr8awi_insn"
 895   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 896         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 897                       (match_operand:SI 2 "immediate_operand" "L")] UNSPEC_ARC_SIMD_VSR8AWi))]
 898   "TARGET_SIMD_SET"
 899   "vsr8awi %0, %1, %2"
 900   [(set_attr "type" "simd_valign_with_acc")
 901    (set_attr "length" "4")
 902    (set_attr "cond" "nocond")])
 903
 904 (define_insn "vsr8i_insn"
 905   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 906         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 907                       (match_operand:SI 2 "immediate_operand" "L")] UNSPEC_ARC_SIMD_VSR8i))]
 908   "TARGET_SIMD_SET"
 909   "vsr8i %0, %1, %2"
 910   [(set_attr "type" "simd_valign")
 911    (set_attr "length" "4")
 912    (set_attr "cond" "nocond")])
 913
 914 ;; Va, Vb, u8 (simm) insns
 915
 916 (define_insn "vmvaw_insn"
 917   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 918         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 919                       (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMVAW))]
 920   "TARGET_SIMD_SET"
 921   "vmvaw %0, %1, %2"
 922   [(set_attr "type" "simd_vmove_with_acc")
 923    (set_attr "length" "4")
 924    (set_attr "cond" "nocond")])
 925
 926 (define_insn "vmvw_insn"
 927   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 928         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 929                       (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMVW))]
 930   "TARGET_SIMD_SET"
 931   "vmvw %0, %1, %2"
 932   [(set_attr "type" "simd_vmove")
 933    (set_attr "length" "4")
 934    (set_attr "cond" "nocond")])
 935
 936 (define_insn "vmvzw_insn"
 937   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 938         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 939                       (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMVZW))]
 940   "TARGET_SIMD_SET"
 941   "vmvzw %0, %1, %2"
 942   [(set_attr "type" "simd_vmove_else_zero")
 943    (set_attr "length" "4")
 944    (set_attr "cond" "nocond")])
 945
 946 (define_insn "vd6tapf_insn"
 947   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 948         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 949                       (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VD6TAPF))]
 950   "TARGET_SIMD_SET"
 951   "vd6tapf %0, %1, %2"
 952   [(set_attr "type" "simd_vspecial_4cycle")
 953    (set_attr "length" "4")
 954    (set_attr "cond" "nocond")])
 955
 956 ;; Va, rlimm, u8 (simm) insns
 957 (define_insn "vmovaw_insn"
 958   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 959         (unspec:V8HI [(match_operand:SI 1 "nonmemory_operand"  "r")
 960                       (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMOVAW))]
 961   "TARGET_SIMD_SET"
 962   "vmovaw %0, %1, %2"
 963   [(set_attr "type" "simd_vmove_with_acc")
 964    (set_attr "length" "4")
 965    (set_attr "cond" "nocond")])
 966
 967 (define_insn "vmovw_insn"
 968   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 969         (unspec:V8HI [(match_operand:SI 1 "nonmemory_operand"  "r")
 970                       (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMOVW))]
 971   "TARGET_SIMD_SET"
 972   "vmovw %0, %1, %2"
 973   [(set_attr "type" "simd_vmove")
 974    (set_attr "length" "4")
 975    (set_attr "cond" "nocond")])
 976
 977 (define_insn "vmovzw_insn"
 978   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 979         (unspec:V8HI [(match_operand:SI 1 "nonmemory_operand"  "r")
 980                       (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMOVZW))]
 981   "TARGET_SIMD_SET"
 982   "vmovzw %0, %1, %2"
 983   [(set_attr "type" "simd_vmove_else_zero")
 984    (set_attr "length" "4")
 985    (set_attr "cond" "nocond")])
 986
 987 ;; Va, rlimm, Ic insns
 988 (define_insn "vsr8_insn"
 989   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 990         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 991                       (match_operand:SI 2 "immediate_operand" "K")
 992                       (match_operand:V8HI 3 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VSR8))]
 993   "TARGET_SIMD_SET"
 994   "vsr8 %0, %1, i%2"
 995   [(set_attr "type" "simd_valign")
 996    (set_attr "length" "4")
 997    (set_attr "cond" "nocond")])
 998
 999 (define_insn "vasrw_insn"
1000   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
1001         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
1002                       (match_operand:SI 2 "immediate_operand" "K")
1003                       (match_operand:V8HI 3 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VASRW))]
1004   "TARGET_SIMD_SET"
1005   "vasrw %0, %1, i%2"
1006   [(set_attr "type" "simd_varith_1cycle")
1007    (set_attr "length" "4")
1008    (set_attr "cond" "nocond")])
1009
1010 (define_insn "vsr8aw_insn"
1011   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
1012         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
1013                       (match_operand:SI 2 "immediate_operand" "K")
1014                       (match_operand:V8HI 3 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VSR8AW))]
1015   "TARGET_SIMD_SET"
1016   "vsr8aw %0, %1, i%2"
1017   [(set_attr "type" "simd_valign_with_acc")
1018    (set_attr "length" "4")
1019    (set_attr "cond" "nocond")])
1020
1021 ;; Va, Vb insns
1022 (define_insn "vabsaw_insn"
1023   [(set (match_operand:V8HI 0 "vector_register_operand"  "=v")
1024         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VABSAW))]
1025   "TARGET_SIMD_SET"
1026   "vabsaw %0, %1"
1027   [(set_attr "type" "simd_varith_with_acc")
1028    (set_attr "length" "4")
1029    (set_attr "cond" "nocond")])
1030
1031 (define_insn "vabsw_insn"
1032   [(set (match_operand:V8HI 0 "vector_register_operand"  "=v")
1033         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VABSW))]
1034   "TARGET_SIMD_SET"
1035   "vabsw %0, %1"
1036   [(set_attr "type" "simd_varith_1cycle")
1037    (set_attr "length" "4")
1038    (set_attr "cond" "nocond")])
1039
1040 (define_insn "vaddsuw_insn"
1041   [(set (match_operand:V8HI 0 "vector_register_operand"  "=v")
1042         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VADDSUW))]
1043   "TARGET_SIMD_SET"
1044   "vaddsuw %0, %1"
1045   [(set_attr "type" "simd_varith_1cycle")
1046    (set_attr "length" "4")
1047    (set_attr "cond" "nocond")])
1048
1049 (define_insn "vsignw_insn"
1050   [(set (match_operand:V8HI 0 "vector_register_operand"  "=v")
1051         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VSIGNW))]
1052   "TARGET_SIMD_SET"
1053   "vsignw %0, %1"
1054   [(set_attr "type" "simd_varith_1cycle")
1055    (set_attr "length" "4")
1056    (set_attr "cond" "nocond")])
1057
1058 (define_insn "vexch1_insn"
1059   [(set (match_operand:V8HI 0 "vector_register_operand"  "=v")
1060         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VEXCH1))]
1061   "TARGET_SIMD_SET"
1062   "vexch1 %0, %1"
1063   [(set_attr "type" "simd_vpermute")
1064    (set_attr "length" "4")
1065    (set_attr "cond" "nocond")])
1066
1067 (define_insn "vexch2_insn"
1068   [(set (match_operand:V8HI 0 "vector_register_operand"  "=v")
1069         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VEXCH2))]
1070   "TARGET_SIMD_SET"
1071   "vexch2 %0, %1"
1072   [(set_attr "type" "simd_vpermute")
1073    (set_attr "length" "4")
1074    (set_attr "cond" "nocond")])
1075
1076 (define_insn "vexch4_insn"
1077   [(set (match_operand:V8HI 0 "vector_register_operand"  "=v")
1078         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VEXCH4))]
1079   "TARGET_SIMD_SET"
1080   "vexch4 %0, %1"
1081   [(set_attr "type" "simd_vpermute")
1082    (set_attr "length" "4")
1083    (set_attr "cond" "nocond")])
1084
1085 (define_insn "vupbaw_insn"
1086   [(set (match_operand:V8HI 0 "vector_register_operand"  "=v")
1087         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VUPBAW))]
1088   "TARGET_SIMD_SET"
1089   "vupbaw %0, %1"
1090   [(set_attr "type" "simd_vpack_with_acc")
1091    (set_attr "length" "4")
1092    (set_attr "cond" "nocond")])
1093
1094 (define_insn "vupbw_insn"
1095   [(set (match_operand:V8HI 0 "vector_register_operand"  "=v")
1096         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VUPBW))]
1097   "TARGET_SIMD_SET"
1098   "vupbw %0, %1"
1099   [(set_attr "type" "simd_vpack")
1100    (set_attr "length" "4")
1101    (set_attr "cond" "nocond")])
1102
1103 (define_insn "vupsbaw_insn"
1104   [(set (match_operand:V8HI 0 "vector_register_operand"  "=v")
1105         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VUPSBAW))]
1106   "TARGET_SIMD_SET"
1107   "vupsbaw %0, %1"
1108   [(set_attr "type" "simd_vpack_with_acc")
1109    (set_attr "length" "4")
1110    (set_attr "cond" "nocond")])
1111
1112 (define_insn "vupsbw_insn"
1113   [(set (match_operand:V8HI 0 "vector_register_operand"  "=v")
1114         (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VUPSBW))]
1115   "TARGET_SIMD_SET"
1116   "vupsbw %0, %1"
1117   [(set_attr "type" "simd_vpack")
1118    (set_attr "length" "4")
1119    (set_attr "cond" "nocond")])
1120
1121 ; DMA setup instructions
1122 (define_insn "vdirun_insn"
1123   [(set (match_operand:SI 0 "arc_simd_dma_register_operand"           "=d")
1124         (unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand"  "r")
1125                              (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VDIRUN))]
1126   "TARGET_SIMD_SET"
1127   "vdirun %1, %2"
1128   [(set_attr "type" "simd_dma")
1129    (set_attr "length" "4")
1130    (set_attr "cond" "nocond")])
1131
1132 (define_insn "vdorun_insn"
1133   [(set (match_operand:SI 0 "arc_simd_dma_register_operand"              "=d")
1134         (unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand"     "r")
1135                              (match_operand:SI 2 "nonmemory_operand"     "r")] UNSPEC_ARC_SIMD_VDORUN))]
1136   "TARGET_SIMD_SET"
1137   "vdorun %1, %2"
1138   [(set_attr "type" "simd_dma")
1139    (set_attr "length" "4")
1140    (set_attr "cond" "nocond")])
1141
1142 (define_insn "vdiwr_insn"
1143   [(set (match_operand:SI 0 "arc_simd_dma_register_operand"           "=d,d")
1144         (unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand"  "r,Cal")] UNSPEC_ARC_SIMD_VDIWR))]
1145   "TARGET_SIMD_SET"
1146   "vdiwr %0, %1"
1147   [(set_attr "type" "simd_dma")
1148    (set_attr "length" "4,8")
1149    (set_attr "cond" "nocond,nocond")])
1150
1151 (define_insn "vdowr_insn"
1152   [(set (match_operand:SI 0 "arc_simd_dma_register_operand"           "=d,d")
1153         (unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand"  "r,Cal")] UNSPEC_ARC_SIMD_VDOWR))]
1154   "TARGET_SIMD_SET"
1155   "vdowr %0, %1"
1156   [(set_attr "type" "simd_dma")
1157    (set_attr "length" "4,8")
1158    (set_attr "cond" "nocond,nocond")])
1159
1160 ;; vector record and run instructions
1161 (define_insn "vrec_insn"
1162   [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand"  "r")] UNSPEC_ARC_SIMD_VREC)]
1163   "TARGET_SIMD_SET"
1164   "vrec %0"
1165   [(set_attr "type" "simd_vcontrol")
1166    (set_attr "length" "4")
1167    (set_attr "cond" "nocond")])
1168
1169 (define_insn "vrun_insn"
1170   [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand"  "r")] UNSPEC_ARC_SIMD_VRUN)]
1171   "TARGET_SIMD_SET"
1172   "vrun %0"
1173   [(set_attr "type" "simd_vcontrol")
1174    (set_attr "length" "4")
1175    (set_attr "cond" "nocond")])
1176
1177 (define_insn "vrecrun_insn"
1178   [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand"  "r")] UNSPEC_ARC_SIMD_VRECRUN)]
1179   "TARGET_SIMD_SET"
1180   "vrecrun %0"
1181   [(set_attr "type" "simd_vcontrol")
1182    (set_attr "length" "4")
1183    (set_attr "cond" "nocond")])
1184
1185 (define_insn "vendrec_insn"
1186   [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand"  "r")] UNSPEC_ARC_SIMD_VENDREC)]
1187   "TARGET_SIMD_SET"
1188   "vendrec %S0"
1189   [(set_attr "type" "simd_vcontrol")
1190    (set_attr "length" "4")
1191    (set_attr "cond" "nocond")])
1192
1193 (define_insn "vld32wh_insn"
1194   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
1195         (vec_concat:V8HI (zero_extend:V4HI (mem:V4QI (plus:SI (match_operand:SI 1 "immediate_operand" "P")
1196                                                               (zero_extend: SI (vec_select:HI (match_operand:V8HI 2 "vector_register_operand"  "v")
1197                                                                                               (parallel [(match_operand:SI 3 "immediate_operand" "L")]))))))
1198                          (vec_select:V4HI (match_dup 0)
1199                                           (parallel [(const_int 0)]))))]
1200   "TARGET_SIMD_SET"
1201   "vld32wh %0, [i%3,%1]"
1202   [(set_attr "type" "simd_vload")
1203    (set_attr "length" "4")
1204    (set_attr "cond" "nocond")])
1205
1206 (define_insn "vld32wl_insn"
1207   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
1208         (vec_concat:V8HI (vec_select:V4HI (match_dup 0)
1209                                           (parallel [(const_int 1)]))
1210                          (zero_extend:V4HI (mem:V4QI (plus:SI (match_operand:SI 1 "immediate_operand" "P")
1211                                                               (zero_extend: SI (vec_select:HI (match_operand:V8HI 2 "vector_register_operand"  "v")
1212                                                                                               (parallel [(match_operand:SI 3 "immediate_operand" "L")])))))) ))]
1213   "TARGET_SIMD_SET"
1214   "vld32wl %0, [i%3,%1]"
1215   [(set_attr "type" "simd_vload")
1216    (set_attr "length" "4")
1217    (set_attr "cond" "nocond")])
1218
1219 (define_insn "vld64w_insn"
1220   [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
1221         (zero_extend:V8HI (mem:V4HI (plus:SI (zero_extend:SI (vec_select:HI (match_operand:V8HI 1 "vector_register_operand"  "v")
1222                                                                             (parallel [(match_operand:SI 2 "immediate_operand" "L")])))
1223                                              (match_operand:SI 3 "immediate_operand" "P")))))]
1224  "TARGET_SIMD_SET"
1225  "vld64w %0, [i%2, %3]"
1226  [(set_attr "type" "simd_vload")
1227   (set_attr "length" "4")
1228   (set_attr "cond" "nocond")]
1229 )
1230
1231 (define_insn "vld64_insn"
1232   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
1233         (vec_concat:V8HI (vec_select:V4HI (match_dup 0)
1234                                           (parallel [(const_int 1)]))
1235                          (mem:V4HI (plus:SI (match_operand:SI 1 "immediate_operand" "P")
1236                                             (zero_extend: SI (vec_select:HI (match_operand:V8HI 2 "vector_register_operand"  "v")
1237                                                                             (parallel [(match_operand:SI 3 "immediate_operand" "L")]))))) ))]
1238   "TARGET_SIMD_SET"
1239   "vld64 %0, [i%3,%1]"
1240   [(set_attr "type" "simd_vload")
1241    (set_attr "length" "4")
1242    (set_attr "cond" "nocond")])
1243
1244 (define_insn "vld32_insn"
1245   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
1246         (vec_concat:V8HI (vec_select:V4HI (match_dup 0)
1247                                           (parallel [(const_int 1)]))
1248                          (vec_concat:V4HI  (vec_select:V2HI (match_dup 0)
1249                                                             (parallel [(const_int 1)]))
1250                                            (mem:V2HI (plus:SI (match_operand:SI 1 "immediate_operand" "P")
1251                                                               (zero_extend: SI (vec_select:HI (match_operand:V8HI 2 "vector_register_operand"  "v")
1252                                                                                               (parallel [(match_operand:SI 3 "immediate_operand" "L")])))))) ))]
1253   "TARGET_SIMD_SET"
1254   "vld32 %0, [i%3,%1]"
1255   [(set_attr "type" "simd_vload")
1256    (set_attr "length" "4")
1257    (set_attr "cond" "nocond")])
1258
1259 (define_insn "vst16_n_insn"
1260   [(set  (mem:HI (plus:SI (match_operand:SI 0 "immediate_operand" "P")
1261                           (zero_extend: SI (vec_select:HI (match_operand:V8HI 1 "vector_register_operand"  "v")
1262                                                           (parallel [(match_operand:SI 2 "immediate_operand" "L")])))))
1263          (vec_select:HI (match_operand:V8HI 3 "vector_register_operand" "v")
1264                         (parallel [(match_operand:SI 4 "immediate_operand" "L")])))]
1265  "TARGET_SIMD_SET"
1266  "vst16_%4 %3,[i%2, %0]"
1267  [(set_attr "type" "simd_vstore")
1268   (set_attr "length" "4")
1269   (set_attr "cond" "nocond")])
1270
1271 (define_insn "vst32_n_insn"
1272   [(set  (mem:SI (plus:SI (match_operand:SI 0 "immediate_operand" "P")
1273                           (zero_extend: SI (vec_select:HI (match_operand:V8HI 1 "vector_register_operand"  "v")
1274                                                           (parallel [(match_operand:SI 2 "immediate_operand" "L")])))))
1275          (vec_select:SI (unspec:V4SI [(match_operand:V8HI 3 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VCAST)
1276                         (parallel [(match_operand:SI 4 "immediate_operand" "L")])))]
1277  "TARGET_SIMD_SET"
1278  "vst32_%4 %3,[i%2, %0]"
1279  [(set_attr "type" "simd_vstore")
1280   (set_attr "length" "4")
1281   (set_attr "cond" "nocond")])
1282
1283 ;; SIMD unit interrupt
1284 (define_insn "vinti_insn"
1285   [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand"  "L")] UNSPEC_ARC_SIMD_VINTI)]
1286   "TARGET_SIMD_SET"
1287   "vinti %0"
1288   [(set_attr "type" "simd_vcontrol")
1289    (set_attr "length" "4")
1290    (set_attr "cond" "nocond")])