]> git.ipfire.org Git - thirdparty/gcc.git/blob - gcc/config/arm/arm-cpu-cdata.h
Remove aarch32 support for falkor/qdf24xx, not in released hardware.
[thirdparty/gcc.git] / gcc / config / arm / arm-cpu-cdata.h
1 /* -*- buffer-read-only: t -*-
2 Generated automatically by parsecpu.awk from arm-cpus.in.
3 Do not edit.
4
5 Copyright (C) 2011-2017 Free Software Foundation, Inc.
6
7 This file is part of GCC.
8
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as
11 published by the Free Software Foundation; either version 3,
12 or (at your option) any later version.
13
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public
20 License along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
22
23 static const struct arm_arch_core_flag arm_arch_core_flags[] =
24 {
25 {
26 "arm2",
27 {
28 ISA_ARMv2,isa_bit_mode26,
29 isa_nobit
30 },
31 },
32 {
33 "arm250",
34 {
35 ISA_ARMv2,isa_bit_mode26,
36 isa_nobit
37 },
38 },
39 {
40 "arm3",
41 {
42 ISA_ARMv2,isa_bit_mode26,
43 isa_nobit
44 },
45 },
46 {
47 "arm6",
48 {
49 ISA_ARMv3,isa_bit_mode26,
50 isa_nobit
51 },
52 },
53 {
54 "arm60",
55 {
56 ISA_ARMv3,isa_bit_mode26,
57 isa_nobit
58 },
59 },
60 {
61 "arm600",
62 {
63 ISA_ARMv3,isa_bit_mode26,
64 isa_nobit
65 },
66 },
67 {
68 "arm610",
69 {
70 ISA_ARMv3,isa_bit_mode26,
71 isa_nobit
72 },
73 },
74 {
75 "arm620",
76 {
77 ISA_ARMv3,isa_bit_mode26,
78 isa_nobit
79 },
80 },
81 {
82 "arm7",
83 {
84 ISA_ARMv3,isa_bit_mode26,
85 isa_nobit
86 },
87 },
88 {
89 "arm7d",
90 {
91 ISA_ARMv3,isa_bit_mode26,
92 isa_nobit
93 },
94 },
95 {
96 "arm7di",
97 {
98 ISA_ARMv3,isa_bit_mode26,
99 isa_nobit
100 },
101 },
102 {
103 "arm70",
104 {
105 ISA_ARMv3,isa_bit_mode26,
106 isa_nobit
107 },
108 },
109 {
110 "arm700",
111 {
112 ISA_ARMv3,isa_bit_mode26,
113 isa_nobit
114 },
115 },
116 {
117 "arm700i",
118 {
119 ISA_ARMv3,isa_bit_mode26,
120 isa_nobit
121 },
122 },
123 {
124 "arm710",
125 {
126 ISA_ARMv3,isa_bit_mode26,
127 isa_nobit
128 },
129 },
130 {
131 "arm720",
132 {
133 ISA_ARMv3,isa_bit_mode26,
134 isa_nobit
135 },
136 },
137 {
138 "arm710c",
139 {
140 ISA_ARMv3,isa_bit_mode26,
141 isa_nobit
142 },
143 },
144 {
145 "arm7100",
146 {
147 ISA_ARMv3,isa_bit_mode26,
148 isa_nobit
149 },
150 },
151 {
152 "arm7500",
153 {
154 ISA_ARMv3,isa_bit_mode26,
155 isa_nobit
156 },
157 },
158 {
159 "arm7500fe",
160 {
161 ISA_ARMv3,isa_bit_mode26,
162 isa_nobit
163 },
164 },
165 {
166 "arm7m",
167 {
168 ISA_ARMv3m,isa_bit_mode26,
169 isa_nobit
170 },
171 },
172 {
173 "arm7dm",
174 {
175 ISA_ARMv3m,isa_bit_mode26,
176 isa_nobit
177 },
178 },
179 {
180 "arm7dmi",
181 {
182 ISA_ARMv3m,isa_bit_mode26,
183 isa_nobit
184 },
185 },
186 {
187 "arm8",
188 {
189 ISA_ARMv4,isa_bit_mode26,
190 isa_nobit
191 },
192 },
193 {
194 "arm810",
195 {
196 ISA_ARMv4,isa_bit_mode26,
197 isa_nobit
198 },
199 },
200 {
201 "strongarm",
202 {
203 ISA_ARMv4,isa_bit_mode26,
204 isa_nobit
205 },
206 },
207 {
208 "strongarm110",
209 {
210 ISA_ARMv4,isa_bit_mode26,
211 isa_nobit
212 },
213 },
214 {
215 "strongarm1100",
216 {
217 ISA_ARMv4,isa_bit_mode26,
218 isa_nobit
219 },
220 },
221 {
222 "strongarm1110",
223 {
224 ISA_ARMv4,isa_bit_mode26,
225 isa_nobit
226 },
227 },
228 {
229 "fa526",
230 {
231 ISA_ARMv4,isa_bit_mode26,
232 isa_nobit
233 },
234 },
235 {
236 "fa626",
237 {
238 ISA_ARMv4,isa_bit_mode26,
239 isa_nobit
240 },
241 },
242 {
243 "arm7tdmi",
244 {
245 ISA_ARMv4t,
246 isa_nobit
247 },
248 },
249 {
250 "arm7tdmi-s",
251 {
252 ISA_ARMv4t,
253 isa_nobit
254 },
255 },
256 {
257 "arm710t",
258 {
259 ISA_ARMv4t,
260 isa_nobit
261 },
262 },
263 {
264 "arm720t",
265 {
266 ISA_ARMv4t,
267 isa_nobit
268 },
269 },
270 {
271 "arm740t",
272 {
273 ISA_ARMv4t,
274 isa_nobit
275 },
276 },
277 {
278 "arm9",
279 {
280 ISA_ARMv4t,
281 isa_nobit
282 },
283 },
284 {
285 "arm9tdmi",
286 {
287 ISA_ARMv4t,
288 isa_nobit
289 },
290 },
291 {
292 "arm920",
293 {
294 ISA_ARMv4t,
295 isa_nobit
296 },
297 },
298 {
299 "arm920t",
300 {
301 ISA_ARMv4t,
302 isa_nobit
303 },
304 },
305 {
306 "arm922t",
307 {
308 ISA_ARMv4t,
309 isa_nobit
310 },
311 },
312 {
313 "arm940t",
314 {
315 ISA_ARMv4t,
316 isa_nobit
317 },
318 },
319 {
320 "ep9312",
321 {
322 ISA_ARMv4t,
323 isa_nobit
324 },
325 },
326 {
327 "arm10tdmi",
328 {
329 ISA_ARMv5t,
330 isa_nobit
331 },
332 },
333 {
334 "arm1020t",
335 {
336 ISA_ARMv5t,
337 isa_nobit
338 },
339 },
340 {
341 "arm9e",
342 {
343 ISA_ARMv5te,
344 isa_nobit
345 },
346 },
347 {
348 "arm946e-s",
349 {
350 ISA_ARMv5te,
351 isa_nobit
352 },
353 },
354 {
355 "arm966e-s",
356 {
357 ISA_ARMv5te,
358 isa_nobit
359 },
360 },
361 {
362 "arm968e-s",
363 {
364 ISA_ARMv5te,
365 isa_nobit
366 },
367 },
368 {
369 "arm10e",
370 {
371 ISA_ARMv5te,
372 isa_nobit
373 },
374 },
375 {
376 "arm1020e",
377 {
378 ISA_ARMv5te,
379 isa_nobit
380 },
381 },
382 {
383 "arm1022e",
384 {
385 ISA_ARMv5te,
386 isa_nobit
387 },
388 },
389 {
390 "xscale",
391 {
392 ISA_ARMv5te,
393 isa_bit_xscale,
394 isa_nobit
395 },
396 },
397 {
398 "iwmmxt",
399 {
400 ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,
401 isa_nobit
402 },
403 },
404 {
405 "iwmmxt2",
406 {
407 ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,isa_bit_iwmmxt2,
408 isa_nobit
409 },
410 },
411 {
412 "fa606te",
413 {
414 ISA_ARMv5te,
415 isa_nobit
416 },
417 },
418 {
419 "fa626te",
420 {
421 ISA_ARMv5te,
422 isa_nobit
423 },
424 },
425 {
426 "fmp626",
427 {
428 ISA_ARMv5te,
429 isa_nobit
430 },
431 },
432 {
433 "fa726te",
434 {
435 ISA_ARMv5te,
436 isa_nobit
437 },
438 },
439 {
440 "arm926ej-s",
441 {
442 ISA_ARMv5tej,
443 isa_nobit
444 },
445 },
446 {
447 "arm1026ej-s",
448 {
449 ISA_ARMv5tej,
450 isa_nobit
451 },
452 },
453 {
454 "arm1136j-s",
455 {
456 ISA_ARMv6j,
457 isa_nobit
458 },
459 },
460 {
461 "arm1136jf-s",
462 {
463 ISA_ARMv6j,
464 ISA_VFPv2,ISA_FP_DBL,
465 isa_nobit
466 },
467 },
468 {
469 "arm1176jz-s",
470 {
471 ISA_ARMv6kz,
472 isa_nobit
473 },
474 },
475 {
476 "arm1176jzf-s",
477 {
478 ISA_ARMv6kz,
479 ISA_VFPv2,ISA_FP_DBL,
480 isa_nobit
481 },
482 },
483 {
484 "mpcorenovfp",
485 {
486 ISA_ARMv6k,
487 isa_nobit
488 },
489 },
490 {
491 "mpcore",
492 {
493 ISA_ARMv6k,
494 ISA_VFPv2,ISA_FP_DBL,
495 isa_nobit
496 },
497 },
498 {
499 "arm1156t2-s",
500 {
501 ISA_ARMv6t2,
502 isa_nobit
503 },
504 },
505 {
506 "arm1156t2f-s",
507 {
508 ISA_ARMv6t2,
509 ISA_VFPv2,ISA_FP_DBL,
510 isa_nobit
511 },
512 },
513 {
514 "cortex-m1",
515 {
516 ISA_ARMv6m,
517 isa_nobit
518 },
519 },
520 {
521 "cortex-m0",
522 {
523 ISA_ARMv6m,
524 isa_nobit
525 },
526 },
527 {
528 "cortex-m0plus",
529 {
530 ISA_ARMv6m,
531 isa_nobit
532 },
533 },
534 {
535 "cortex-m1.small-multiply",
536 {
537 ISA_ARMv6m,
538 isa_nobit
539 },
540 },
541 {
542 "cortex-m0.small-multiply",
543 {
544 ISA_ARMv6m,
545 isa_nobit
546 },
547 },
548 {
549 "cortex-m0plus.small-multiply",
550 {
551 ISA_ARMv6m,
552 isa_nobit
553 },
554 },
555 {
556 "generic-armv7-a",
557 {
558 ISA_ARMv7a,
559 isa_nobit
560 },
561 },
562 {
563 "cortex-a5",
564 {
565 ISA_ARMv7a,
566 isa_nobit
567 },
568 },
569 {
570 "cortex-a7",
571 {
572 ISA_ARMv7ve,
573 isa_nobit
574 },
575 },
576 {
577 "cortex-a8",
578 {
579 ISA_ARMv7a,
580 isa_nobit
581 },
582 },
583 {
584 "cortex-a9",
585 {
586 ISA_ARMv7a,
587 isa_nobit
588 },
589 },
590 {
591 "cortex-a12",
592 {
593 ISA_ARMv7ve,
594 isa_nobit
595 },
596 },
597 {
598 "cortex-a15",
599 {
600 ISA_ARMv7ve,
601 isa_nobit
602 },
603 },
604 {
605 "cortex-a17",
606 {
607 ISA_ARMv7ve,
608 isa_nobit
609 },
610 },
611 {
612 "cortex-r4",
613 {
614 ISA_ARMv7r,
615 isa_nobit
616 },
617 },
618 {
619 "cortex-r4f",
620 {
621 ISA_ARMv7r,
622 isa_nobit
623 },
624 },
625 {
626 "cortex-r5",
627 {
628 ISA_ARMv7r,
629 isa_bit_adiv,
630 isa_nobit
631 },
632 },
633 {
634 "cortex-r7",
635 {
636 ISA_ARMv7r,
637 isa_bit_adiv,
638 isa_nobit
639 },
640 },
641 {
642 "cortex-r8",
643 {
644 ISA_ARMv7r,
645 isa_bit_adiv,
646 isa_nobit
647 },
648 },
649 {
650 "cortex-m7",
651 {
652 ISA_ARMv7em,
653 isa_quirk_no_volatile_ce,
654 isa_nobit
655 },
656 },
657 {
658 "cortex-m4",
659 {
660 ISA_ARMv7em,
661 isa_nobit
662 },
663 },
664 {
665 "cortex-m3",
666 {
667 ISA_ARMv7m,
668 isa_quirk_cm3_ldrd,
669 isa_nobit
670 },
671 },
672 {
673 "marvell-pj4",
674 {
675 ISA_ARMv7a,
676 isa_nobit
677 },
678 },
679 {
680 "cortex-a15.cortex-a7",
681 {
682 ISA_ARMv7ve,
683 isa_nobit
684 },
685 },
686 {
687 "cortex-a17.cortex-a7",
688 {
689 ISA_ARMv7ve,
690 isa_nobit
691 },
692 },
693 {
694 "cortex-a32",
695 {
696 ISA_ARMv8a,isa_bit_crc32,
697 isa_nobit
698 },
699 },
700 {
701 "cortex-a35",
702 {
703 ISA_ARMv8a,isa_bit_crc32,
704 isa_nobit
705 },
706 },
707 {
708 "cortex-a53",
709 {
710 ISA_ARMv8a,isa_bit_crc32,
711 isa_nobit
712 },
713 },
714 {
715 "cortex-a57",
716 {
717 ISA_ARMv8a,isa_bit_crc32,
718 isa_nobit
719 },
720 },
721 {
722 "cortex-a72",
723 {
724 ISA_ARMv8a,isa_bit_crc32,
725 isa_nobit
726 },
727 },
728 {
729 "cortex-a73",
730 {
731 ISA_ARMv8a,isa_bit_crc32,
732 isa_nobit
733 },
734 },
735 {
736 "exynos-m1",
737 {
738 ISA_ARMv8a,isa_bit_crc32,
739 isa_nobit
740 },
741 },
742 {
743 "xgene1",
744 {
745 ISA_ARMv8a,
746 isa_nobit
747 },
748 },
749 {
750 "cortex-a57.cortex-a53",
751 {
752 ISA_ARMv8a,isa_bit_crc32,
753 isa_nobit
754 },
755 },
756 {
757 "cortex-a72.cortex-a53",
758 {
759 ISA_ARMv8a,isa_bit_crc32,
760 isa_nobit
761 },
762 },
763 {
764 "cortex-a73.cortex-a35",
765 {
766 ISA_ARMv8a,isa_bit_crc32,
767 isa_nobit
768 },
769 },
770 {
771 "cortex-a73.cortex-a53",
772 {
773 ISA_ARMv8a,isa_bit_crc32,
774 isa_nobit
775 },
776 },
777 {
778 "cortex-m23",
779 {
780 ISA_ARMv8m_base,
781 isa_nobit
782 },
783 },
784 {
785 "cortex-m33",
786 {
787 ISA_ARMv8m_main,isa_bit_ARMv7em,
788 isa_nobit
789 },
790 },
791 {
792 "armv2",
793 {
794 ISA_ARMv2,isa_bit_mode26,
795 isa_nobit
796 },
797 },
798 {
799 "armv2a",
800 {
801 ISA_ARMv2,isa_bit_mode26,
802 isa_nobit
803 },
804 },
805 {
806 "armv3",
807 {
808 ISA_ARMv3,isa_bit_mode26,
809 isa_nobit
810 },
811 },
812 {
813 "armv3m",
814 {
815 ISA_ARMv3m,isa_bit_mode26,
816 isa_nobit
817 },
818 },
819 {
820 "armv4",
821 {
822 ISA_ARMv4,isa_bit_mode26,
823 isa_nobit
824 },
825 },
826 {
827 "armv4t",
828 {
829 ISA_ARMv4t,
830 isa_nobit
831 },
832 },
833 {
834 "armv5",
835 {
836 ISA_ARMv5,
837 isa_nobit
838 },
839 },
840 {
841 "armv5t",
842 {
843 ISA_ARMv5t,
844 isa_nobit
845 },
846 },
847 {
848 "armv5e",
849 {
850 ISA_ARMv5e,
851 isa_nobit
852 },
853 },
854 {
855 "armv5te",
856 {
857 ISA_ARMv5te,
858 isa_nobit
859 },
860 },
861 {
862 "armv5tej",
863 {
864 ISA_ARMv5tej,
865 isa_nobit
866 },
867 },
868 {
869 "armv6",
870 {
871 ISA_ARMv6,
872 isa_nobit
873 },
874 },
875 {
876 "armv6j",
877 {
878 ISA_ARMv6j,
879 isa_nobit
880 },
881 },
882 {
883 "armv6k",
884 {
885 ISA_ARMv6k,
886 isa_nobit
887 },
888 },
889 {
890 "armv6z",
891 {
892 ISA_ARMv6z,
893 isa_nobit
894 },
895 },
896 {
897 "armv6kz",
898 {
899 ISA_ARMv6kz,
900 isa_nobit
901 },
902 },
903 {
904 "armv6zk",
905 {
906 ISA_ARMv6kz,
907 isa_nobit
908 },
909 },
910 {
911 "armv6t2",
912 {
913 ISA_ARMv6t2,
914 isa_nobit
915 },
916 },
917 {
918 "armv6-m",
919 {
920 ISA_ARMv6m,
921 isa_nobit
922 },
923 },
924 {
925 "armv6s-m",
926 {
927 ISA_ARMv6m,
928 isa_nobit
929 },
930 },
931 {
932 "armv7",
933 {
934 ISA_ARMv7,
935 isa_nobit
936 },
937 },
938 {
939 "armv7-a",
940 {
941 ISA_ARMv7a,
942 isa_nobit
943 },
944 },
945 {
946 "armv7ve",
947 {
948 ISA_ARMv7ve,
949 isa_nobit
950 },
951 },
952 {
953 "armv7-r",
954 {
955 ISA_ARMv7r,
956 isa_nobit
957 },
958 },
959 {
960 "armv7-m",
961 {
962 ISA_ARMv7m,
963 isa_nobit
964 },
965 },
966 {
967 "armv7e-m",
968 {
969 ISA_ARMv7em,
970 isa_nobit
971 },
972 },
973 {
974 "armv8-a",
975 {
976 ISA_ARMv8a,
977 isa_nobit
978 },
979 },
980 {
981 "armv8-a+crc",
982 {
983 ISA_ARMv8a,isa_bit_crc32,
984 isa_nobit
985 },
986 },
987 {
988 "armv8.1-a",
989 {
990 ISA_ARMv8_1a,
991 isa_nobit
992 },
993 },
994 {
995 "armv8.2-a",
996 {
997 ISA_ARMv8_2a,
998 isa_nobit
999 },
1000 },
1001 {
1002 "armv8.2-a+fp16",
1003 {
1004 ISA_ARMv8_2a,isa_bit_fp16,
1005 isa_nobit
1006 },
1007 },
1008 {
1009 "armv8-m.base",
1010 {
1011 ISA_ARMv8m_base,
1012 isa_nobit
1013 },
1014 },
1015 {
1016 "armv8-m.main",
1017 {
1018 ISA_ARMv8m_main,
1019 isa_nobit
1020 },
1021 },
1022 {
1023 "armv8-m.main+dsp",
1024 {
1025 ISA_ARMv8m_main,isa_bit_ARMv7em,
1026 isa_nobit
1027 },
1028 },
1029 {
1030 "iwmmxt",
1031 {
1032 ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,
1033 isa_nobit
1034 },
1035 },
1036 {
1037 "iwmmxt2",
1038 {
1039 ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,isa_bit_iwmmxt2,
1040 isa_nobit
1041 },
1042 },
1043 };
1044