gcc/config/arm/arm-cpu-data.h

   1 /* -*- buffer-read-only: t -*-
   2    Generated automatically by parsecpu.awk from arm-cpus.in.
   3    Do not edit.
   4
   5    Copyright (C) 2011-2017 Free Software Foundation, Inc.
   6
   7    This file is part of GCC.
   8
   9    GCC is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as
  11    published by the Free Software Foundation; either version 3,
  12    or (at your option) any later version.
  13
  14    GCC is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public
  20    License along with GCC; see the file COPYING3.  If not see
  21    <http://www.gnu.org/licenses/>.  */
  22
  23 static const struct processors all_cores[] =
  24 {
  25   {
  26     "arm2",
  27     TARGET_CPU_arm2,
  28     (TF_CO_PROC | TF_NO_MODE32),
  29     "2", BASE_ARCH_2,
  30     {
  31       ISA_ARMv2,isa_bit_mode26,
  32       isa_nobit
  33     },
  34     &arm_slowmul_tune
  35   },
  36   {
  37     "arm250",
  38     TARGET_CPU_arm250,
  39     (TF_CO_PROC | TF_NO_MODE32),
  40     "2", BASE_ARCH_2,
  41     {
  42       ISA_ARMv2,isa_bit_mode26,
  43       isa_nobit
  44     },
  45     &arm_slowmul_tune
  46   },
  47   {
  48     "arm3",
  49     TARGET_CPU_arm3,
  50     (TF_CO_PROC | TF_NO_MODE32),
  51     "2", BASE_ARCH_2,
  52     {
  53       ISA_ARMv2,isa_bit_mode26,
  54       isa_nobit
  55     },
  56     &arm_slowmul_tune
  57   },
  58   {
  59     "arm6",
  60     TARGET_CPU_arm6,
  61     (TF_CO_PROC),
  62     "3", BASE_ARCH_3,
  63     {
  64       ISA_ARMv3,isa_bit_mode26,
  65       isa_nobit
  66     },
  67     &arm_slowmul_tune
  68   },
  69   {
  70     "arm60",
  71     TARGET_CPU_arm60,
  72     (TF_CO_PROC),
  73     "3", BASE_ARCH_3,
  74     {
  75       ISA_ARMv3,isa_bit_mode26,
  76       isa_nobit
  77     },
  78     &arm_slowmul_tune
  79   },
  80   {
  81     "arm600",
  82     TARGET_CPU_arm600,
  83     (TF_CO_PROC | TF_WBUF),
  84     "3", BASE_ARCH_3,
  85     {
  86       ISA_ARMv3,isa_bit_mode26,
  87       isa_nobit
  88     },
  89     &arm_slowmul_tune
  90   },
  91   {
  92     "arm610",
  93     TARGET_CPU_arm610,
  94     (TF_WBUF),
  95     "3", BASE_ARCH_3,
  96     {
  97       ISA_ARMv3,isa_bit_mode26,
  98       isa_nobit
  99     },
 100     &arm_slowmul_tune
 101   },
 102   {
 103     "arm620",
 104     TARGET_CPU_arm620,
 105     (TF_CO_PROC | TF_WBUF),
 106     "3", BASE_ARCH_3,
 107     {
 108       ISA_ARMv3,isa_bit_mode26,
 109       isa_nobit
 110     },
 111     &arm_slowmul_tune
 112   },
 113   {
 114     "arm7",
 115     TARGET_CPU_arm7,
 116     (TF_CO_PROC),
 117     "3", BASE_ARCH_3,
 118     {
 119       ISA_ARMv3,isa_bit_mode26,
 120       isa_nobit
 121     },
 122     &arm_slowmul_tune
 123   },
 124   {
 125     "arm7d",
 126     TARGET_CPU_arm7d,
 127     (TF_CO_PROC),
 128     "3", BASE_ARCH_3,
 129     {
 130       ISA_ARMv3,isa_bit_mode26,
 131       isa_nobit
 132     },
 133     &arm_slowmul_tune
 134   },
 135   {
 136     "arm7di",
 137     TARGET_CPU_arm7di,
 138     (TF_CO_PROC),
 139     "3", BASE_ARCH_3,
 140     {
 141       ISA_ARMv3,isa_bit_mode26,
 142       isa_nobit
 143     },
 144     &arm_slowmul_tune
 145   },
 146   {
 147     "arm70",
 148     TARGET_CPU_arm70,
 149     (TF_CO_PROC),
 150     "3", BASE_ARCH_3,
 151     {
 152       ISA_ARMv3,isa_bit_mode26,
 153       isa_nobit
 154     },
 155     &arm_slowmul_tune
 156   },
 157   {
 158     "arm700",
 159     TARGET_CPU_arm700,
 160     (TF_CO_PROC | TF_WBUF),
 161     "3", BASE_ARCH_3,
 162     {
 163       ISA_ARMv3,isa_bit_mode26,
 164       isa_nobit
 165     },
 166     &arm_slowmul_tune
 167   },
 168   {
 169     "arm700i",
 170     TARGET_CPU_arm700i,
 171     (TF_CO_PROC | TF_WBUF),
 172     "3", BASE_ARCH_3,
 173     {
 174       ISA_ARMv3,isa_bit_mode26,
 175       isa_nobit
 176     },
 177     &arm_slowmul_tune
 178   },
 179   {
 180     "arm710",
 181     TARGET_CPU_arm710,
 182     (TF_WBUF),
 183     "3", BASE_ARCH_3,
 184     {
 185       ISA_ARMv3,isa_bit_mode26,
 186       isa_nobit
 187     },
 188     &arm_slowmul_tune
 189   },
 190   {
 191     "arm720",
 192     TARGET_CPU_arm720,
 193     (TF_WBUF),
 194     "3", BASE_ARCH_3,
 195     {
 196       ISA_ARMv3,isa_bit_mode26,
 197       isa_nobit
 198     },
 199     &arm_slowmul_tune
 200   },
 201   {
 202     "arm710c",
 203     TARGET_CPU_arm710c,
 204     (TF_WBUF),
 205     "3", BASE_ARCH_3,
 206     {
 207       ISA_ARMv3,isa_bit_mode26,
 208       isa_nobit
 209     },
 210     &arm_slowmul_tune
 211   },
 212   {
 213     "arm7100",
 214     TARGET_CPU_arm7100,
 215     (TF_WBUF),
 216     "3", BASE_ARCH_3,
 217     {
 218       ISA_ARMv3,isa_bit_mode26,
 219       isa_nobit
 220     },
 221     &arm_slowmul_tune
 222   },
 223   {
 224     "arm7500",
 225     TARGET_CPU_arm7500,
 226     (TF_WBUF),
 227     "3", BASE_ARCH_3,
 228     {
 229       ISA_ARMv3,isa_bit_mode26,
 230       isa_nobit
 231     },
 232     &arm_slowmul_tune
 233   },
 234   {
 235     "arm7500fe",
 236     TARGET_CPU_arm7500fe,
 237     (TF_CO_PROC | TF_WBUF),
 238     "3", BASE_ARCH_3,
 239     {
 240       ISA_ARMv3,isa_bit_mode26,
 241       isa_nobit
 242     },
 243     &arm_slowmul_tune
 244   },
 245   {
 246     "arm7m",
 247     TARGET_CPU_arm7m,
 248     (TF_CO_PROC),
 249     "3M", BASE_ARCH_3M,
 250     {
 251       ISA_ARMv3m,isa_bit_mode26,
 252       isa_nobit
 253     },
 254     &arm_fastmul_tune
 255   },
 256   {
 257     "arm7dm",
 258     TARGET_CPU_arm7dm,
 259     (TF_CO_PROC),
 260     "3M", BASE_ARCH_3M,
 261     {
 262       ISA_ARMv3m,isa_bit_mode26,
 263       isa_nobit
 264     },
 265     &arm_fastmul_tune
 266   },
 267   {
 268     "arm7dmi",
 269     TARGET_CPU_arm7dmi,
 270     (TF_CO_PROC),
 271     "3M", BASE_ARCH_3M,
 272     {
 273       ISA_ARMv3m,isa_bit_mode26,
 274       isa_nobit
 275     },
 276     &arm_fastmul_tune
 277   },
 278   {
 279     "arm8",
 280     TARGET_CPU_arm8,
 281     (TF_LDSCHED),
 282     "4", BASE_ARCH_4,
 283     {
 284       ISA_ARMv4,isa_bit_mode26,
 285       isa_nobit
 286     },
 287     &arm_fastmul_tune
 288   },
 289   {
 290     "arm810",
 291     TARGET_CPU_arm810,
 292     (TF_LDSCHED),
 293     "4", BASE_ARCH_4,
 294     {
 295       ISA_ARMv4,isa_bit_mode26,
 296       isa_nobit
 297     },
 298     &arm_fastmul_tune
 299   },
 300   {
 301     "strongarm",
 302     TARGET_CPU_strongarm,
 303     (TF_LDSCHED | TF_STRONG),
 304     "4", BASE_ARCH_4,
 305     {
 306       ISA_ARMv4,isa_bit_mode26,
 307       isa_nobit
 308     },
 309     &arm_strongarm_tune
 310   },
 311   {
 312     "strongarm110",
 313     TARGET_CPU_strongarm110,
 314     (TF_LDSCHED | TF_STRONG),
 315     "4", BASE_ARCH_4,
 316     {
 317       ISA_ARMv4,isa_bit_mode26,
 318       isa_nobit
 319     },
 320     &arm_strongarm_tune
 321   },
 322   {
 323     "strongarm1100",
 324     TARGET_CPU_strongarm1100,
 325     (TF_LDSCHED | TF_STRONG),
 326     "4", BASE_ARCH_4,
 327     {
 328       ISA_ARMv4,isa_bit_mode26,
 329       isa_nobit
 330     },
 331     &arm_strongarm_tune
 332   },
 333   {
 334     "strongarm1110",
 335     TARGET_CPU_strongarm1110,
 336     (TF_LDSCHED | TF_STRONG),
 337     "4", BASE_ARCH_4,
 338     {
 339       ISA_ARMv4,isa_bit_mode26,
 340       isa_nobit
 341     },
 342     &arm_strongarm_tune
 343   },
 344   {
 345     "fa526",
 346     TARGET_CPU_fa526,
 347     (TF_LDSCHED),
 348     "4", BASE_ARCH_4,
 349     {
 350       ISA_ARMv4,isa_bit_mode26,
 351       isa_nobit
 352     },
 353     &arm_fastmul_tune
 354   },
 355   {
 356     "fa626",
 357     TARGET_CPU_fa626,
 358     (TF_LDSCHED),
 359     "4", BASE_ARCH_4,
 360     {
 361       ISA_ARMv4,isa_bit_mode26,
 362       isa_nobit
 363     },
 364     &arm_fastmul_tune
 365   },
 366   {
 367     "arm7tdmi",
 368     TARGET_CPU_arm7tdmi,
 369     (TF_CO_PROC),
 370     "4T", BASE_ARCH_4T,
 371     {
 372       ISA_ARMv4t,
 373       isa_nobit
 374     },
 375     &arm_fastmul_tune
 376   },
 377   {
 378     "arm7tdmi-s",
 379     TARGET_CPU_arm7tdmis,
 380     (TF_CO_PROC),
 381     "4T", BASE_ARCH_4T,
 382     {
 383       ISA_ARMv4t,
 384       isa_nobit
 385     },
 386     &arm_fastmul_tune
 387   },
 388   {
 389     "arm710t",
 390     TARGET_CPU_arm710t,
 391     (TF_WBUF),
 392     "4T", BASE_ARCH_4T,
 393     {
 394       ISA_ARMv4t,
 395       isa_nobit
 396     },
 397     &arm_fastmul_tune
 398   },
 399   {
 400     "arm720t",
 401     TARGET_CPU_arm720t,
 402     (TF_WBUF),
 403     "4T", BASE_ARCH_4T,
 404     {
 405       ISA_ARMv4t,
 406       isa_nobit
 407     },
 408     &arm_fastmul_tune
 409   },
 410   {
 411     "arm740t",
 412     TARGET_CPU_arm740t,
 413     (TF_WBUF),
 414     "4T", BASE_ARCH_4T,
 415     {
 416       ISA_ARMv4t,
 417       isa_nobit
 418     },
 419     &arm_fastmul_tune
 420   },
 421   {
 422     "arm9",
 423     TARGET_CPU_arm9,
 424     (TF_LDSCHED),
 425     "4T", BASE_ARCH_4T,
 426     {
 427       ISA_ARMv4t,
 428       isa_nobit
 429     },
 430     &arm_fastmul_tune
 431   },
 432   {
 433     "arm9tdmi",
 434     TARGET_CPU_arm9tdmi,
 435     (TF_LDSCHED),
 436     "4T", BASE_ARCH_4T,
 437     {
 438       ISA_ARMv4t,
 439       isa_nobit
 440     },
 441     &arm_fastmul_tune
 442   },
 443   {
 444     "arm920",
 445     TARGET_CPU_arm920,
 446     (TF_LDSCHED),
 447     "4T", BASE_ARCH_4T,
 448     {
 449       ISA_ARMv4t,
 450       isa_nobit
 451     },
 452     &arm_fastmul_tune
 453   },
 454   {
 455     "arm920t",
 456     TARGET_CPU_arm920t,
 457     (TF_LDSCHED),
 458     "4T", BASE_ARCH_4T,
 459     {
 460       ISA_ARMv4t,
 461       isa_nobit
 462     },
 463     &arm_fastmul_tune
 464   },
 465   {
 466     "arm922t",
 467     TARGET_CPU_arm922t,
 468     (TF_LDSCHED),
 469     "4T", BASE_ARCH_4T,
 470     {
 471       ISA_ARMv4t,
 472       isa_nobit
 473     },
 474     &arm_fastmul_tune
 475   },
 476   {
 477     "arm940t",
 478     TARGET_CPU_arm940t,
 479     (TF_LDSCHED),
 480     "4T", BASE_ARCH_4T,
 481     {
 482       ISA_ARMv4t,
 483       isa_nobit
 484     },
 485     &arm_fastmul_tune
 486   },
 487   {
 488     "ep9312",
 489     TARGET_CPU_ep9312,
 490     (TF_LDSCHED),
 491     "4T", BASE_ARCH_4T,
 492     {
 493       ISA_ARMv4t,
 494       isa_nobit
 495     },
 496     &arm_fastmul_tune
 497   },
 498   {
 499     "arm10tdmi",
 500     TARGET_CPU_arm10tdmi,
 501     (TF_LDSCHED),
 502     "5T", BASE_ARCH_5T,
 503     {
 504       ISA_ARMv5t,
 505       isa_nobit
 506     },
 507     &arm_fastmul_tune
 508   },
 509   {
 510     "arm1020t",
 511     TARGET_CPU_arm1020t,
 512     (TF_LDSCHED),
 513     "5T", BASE_ARCH_5T,
 514     {
 515       ISA_ARMv5t,
 516       isa_nobit
 517     },
 518     &arm_fastmul_tune
 519   },
 520   {
 521     "arm9e",
 522     TARGET_CPU_arm9e,
 523     (TF_LDSCHED),
 524     "5TE", BASE_ARCH_5TE,
 525     {
 526       ISA_ARMv5te,
 527       isa_nobit
 528     },
 529     &arm_9e_tune
 530   },
 531   {
 532     "arm946e-s",
 533     TARGET_CPU_arm946es,
 534     (TF_LDSCHED),
 535     "5TE", BASE_ARCH_5TE,
 536     {
 537       ISA_ARMv5te,
 538       isa_nobit
 539     },
 540     &arm_9e_tune
 541   },
 542   {
 543     "arm966e-s",
 544     TARGET_CPU_arm966es,
 545     (TF_LDSCHED),
 546     "5TE", BASE_ARCH_5TE,
 547     {
 548       ISA_ARMv5te,
 549       isa_nobit
 550     },
 551     &arm_9e_tune
 552   },
 553   {
 554     "arm968e-s",
 555     TARGET_CPU_arm968es,
 556     (TF_LDSCHED),
 557     "5TE", BASE_ARCH_5TE,
 558     {
 559       ISA_ARMv5te,
 560       isa_nobit
 561     },
 562     &arm_9e_tune
 563   },
 564   {
 565     "arm10e",
 566     TARGET_CPU_arm10e,
 567     (TF_LDSCHED),
 568     "5TE", BASE_ARCH_5TE,
 569     {
 570       ISA_ARMv5te,
 571       isa_nobit
 572     },
 573     &arm_fastmul_tune
 574   },
 575   {
 576     "arm1020e",
 577     TARGET_CPU_arm1020e,
 578     (TF_LDSCHED),
 579     "5TE", BASE_ARCH_5TE,
 580     {
 581       ISA_ARMv5te,
 582       isa_nobit
 583     },
 584     &arm_fastmul_tune
 585   },
 586   {
 587     "arm1022e",
 588     TARGET_CPU_arm1022e,
 589     (TF_LDSCHED),
 590     "5TE", BASE_ARCH_5TE,
 591     {
 592       ISA_ARMv5te,
 593       isa_nobit
 594     },
 595     &arm_fastmul_tune
 596   },
 597   {
 598     "xscale",
 599     TARGET_CPU_xscale,
 600     (TF_LDSCHED | TF_XSCALE),
 601     "5TE", BASE_ARCH_5TE,
 602     {
 603       ISA_ARMv5te,
 604       isa_bit_xscale,
 605       isa_nobit
 606     },
 607     &arm_xscale_tune
 608   },
 609   {
 610     "iwmmxt",
 611     TARGET_CPU_iwmmxt,
 612     (TF_LDSCHED | TF_XSCALE),
 613     "5TE", BASE_ARCH_5TE,
 614     {
 615       ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,
 616       isa_nobit
 617     },
 618     &arm_xscale_tune
 619   },
 620   {
 621     "iwmmxt2",
 622     TARGET_CPU_iwmmxt2,
 623     (TF_LDSCHED | TF_XSCALE),
 624     "5TE", BASE_ARCH_5TE,
 625     {
 626       ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,isa_bit_iwmmxt2,
 627       isa_nobit
 628     },
 629     &arm_xscale_tune
 630   },
 631   {
 632     "fa606te",
 633     TARGET_CPU_fa606te,
 634     (TF_LDSCHED),
 635     "5TE", BASE_ARCH_5TE,
 636     {
 637       ISA_ARMv5te,
 638       isa_nobit
 639     },
 640     &arm_9e_tune
 641   },
 642   {
 643     "fa626te",
 644     TARGET_CPU_fa626te,
 645     (TF_LDSCHED),
 646     "5TE", BASE_ARCH_5TE,
 647     {
 648       ISA_ARMv5te,
 649       isa_nobit
 650     },
 651     &arm_9e_tune
 652   },
 653   {
 654     "fmp626",
 655     TARGET_CPU_fmp626,
 656     (TF_LDSCHED),
 657     "5TE", BASE_ARCH_5TE,
 658     {
 659       ISA_ARMv5te,
 660       isa_nobit
 661     },
 662     &arm_9e_tune
 663   },
 664   {
 665     "fa726te",
 666     TARGET_CPU_fa726te,
 667     (TF_LDSCHED),
 668     "5TE", BASE_ARCH_5TE,
 669     {
 670       ISA_ARMv5te,
 671       isa_nobit
 672     },
 673     &arm_fa726te_tune
 674   },
 675   {
 676     "arm926ej-s",
 677     TARGET_CPU_arm926ejs,
 678     (TF_LDSCHED),
 679     "5TEJ", BASE_ARCH_5TEJ,
 680     {
 681       ISA_ARMv5tej,
 682       isa_nobit
 683     },
 684     &arm_9e_tune
 685   },
 686   {
 687     "arm1026ej-s",
 688     TARGET_CPU_arm1026ejs,
 689     (TF_LDSCHED),
 690     "5TEJ", BASE_ARCH_5TEJ,
 691     {
 692       ISA_ARMv5tej,
 693       isa_nobit
 694     },
 695     &arm_9e_tune
 696   },
 697   {
 698     "arm1136j-s",
 699     TARGET_CPU_arm1136js,
 700     (TF_LDSCHED),
 701     "6J", BASE_ARCH_6J,
 702     {
 703       ISA_ARMv6j,
 704       isa_nobit
 705     },
 706     &arm_9e_tune
 707   },
 708   {
 709     "arm1136jf-s",
 710     TARGET_CPU_arm1136jfs,
 711     (TF_LDSCHED),
 712     "6J", BASE_ARCH_6J,
 713     {
 714       ISA_ARMv6j,
 715       ISA_VFPv2,ISA_FP_DBL,
 716       isa_nobit
 717     },
 718     &arm_9e_tune
 719   },
 720   {
 721     "arm1176jz-s",
 722     TARGET_CPU_arm1176jzs,
 723     (TF_LDSCHED),
 724     "6KZ", BASE_ARCH_6KZ,
 725     {
 726       ISA_ARMv6kz,
 727       isa_nobit
 728     },
 729     &arm_9e_tune
 730   },
 731   {
 732     "arm1176jzf-s",
 733     TARGET_CPU_arm1176jzfs,
 734     (TF_LDSCHED),
 735     "6KZ", BASE_ARCH_6KZ,
 736     {
 737       ISA_ARMv6kz,
 738       ISA_VFPv2,ISA_FP_DBL,
 739       isa_nobit
 740     },
 741     &arm_9e_tune
 742   },
 743   {
 744     "mpcorenovfp",
 745     TARGET_CPU_mpcorenovfp,
 746     (TF_LDSCHED),
 747     "6K", BASE_ARCH_6K,
 748     {
 749       ISA_ARMv6k,
 750       isa_nobit
 751     },
 752     &arm_9e_tune
 753   },
 754   {
 755     "mpcore",
 756     TARGET_CPU_mpcore,
 757     (TF_LDSCHED),
 758     "6K", BASE_ARCH_6K,
 759     {
 760       ISA_ARMv6k,
 761       ISA_VFPv2,ISA_FP_DBL,
 762       isa_nobit
 763     },
 764     &arm_9e_tune
 765   },
 766   {
 767     "arm1156t2-s",
 768     TARGET_CPU_arm1156t2s,
 769     (TF_LDSCHED),
 770     "6T2", BASE_ARCH_6T2,
 771     {
 772       ISA_ARMv6t2,
 773       isa_nobit
 774     },
 775     &arm_v6t2_tune
 776   },
 777   {
 778     "arm1156t2f-s",
 779     TARGET_CPU_arm1156t2fs,
 780     (TF_LDSCHED),
 781     "6T2", BASE_ARCH_6T2,
 782     {
 783       ISA_ARMv6t2,
 784       ISA_VFPv2,ISA_FP_DBL,
 785       isa_nobit
 786     },
 787     &arm_v6t2_tune
 788   },
 789   {
 790     "cortex-m1",
 791     TARGET_CPU_cortexm1,
 792     (TF_LDSCHED),
 793     "6M", BASE_ARCH_6M,
 794     {
 795       ISA_ARMv6m,
 796       isa_nobit
 797     },
 798     &arm_v6m_tune
 799   },
 800   {
 801     "cortex-m0",
 802     TARGET_CPU_cortexm0,
 803     (TF_LDSCHED),
 804     "6M", BASE_ARCH_6M,
 805     {
 806       ISA_ARMv6m,
 807       isa_nobit
 808     },
 809     &arm_v6m_tune
 810   },
 811   {
 812     "cortex-m0plus",
 813     TARGET_CPU_cortexm0plus,
 814     (TF_LDSCHED),
 815     "6M", BASE_ARCH_6M,
 816     {
 817       ISA_ARMv6m,
 818       isa_nobit
 819     },
 820     &arm_v6m_tune
 821   },
 822   {
 823     "cortex-m1.small-multiply",
 824     TARGET_CPU_cortexm1,
 825     (TF_LDSCHED | TF_SMALLMUL),
 826     "6M", BASE_ARCH_6M,
 827     {
 828       ISA_ARMv6m,
 829       isa_nobit
 830     },
 831     &arm_v6m_tune
 832   },
 833   {
 834     "cortex-m0.small-multiply",
 835     TARGET_CPU_cortexm0,
 836     (TF_LDSCHED | TF_SMALLMUL),
 837     "6M", BASE_ARCH_6M,
 838     {
 839       ISA_ARMv6m,
 840       isa_nobit
 841     },
 842     &arm_v6m_tune
 843   },
 844   {
 845     "cortex-m0plus.small-multiply",
 846     TARGET_CPU_cortexm0plus,
 847     (TF_LDSCHED | TF_SMALLMUL),
 848     "6M", BASE_ARCH_6M,
 849     {
 850       ISA_ARMv6m,
 851       isa_nobit
 852     },
 853     &arm_v6m_tune
 854   },
 855   {
 856     "generic-armv7-a",
 857     TARGET_CPU_genericv7a,
 858     (TF_LDSCHED),
 859     "7A", BASE_ARCH_7A,
 860     {
 861       ISA_ARMv7a,
 862       isa_nobit
 863     },
 864     &arm_cortex_tune
 865   },
 866   {
 867     "cortex-a5",
 868     TARGET_CPU_cortexa5,
 869     (TF_LDSCHED),
 870     "7A", BASE_ARCH_7A,
 871     {
 872       ISA_ARMv7a,
 873       isa_nobit
 874     },
 875     &arm_cortex_a5_tune
 876   },
 877   {
 878     "cortex-a7",
 879     TARGET_CPU_cortexa7,
 880     (TF_LDSCHED),
 881     "7A", BASE_ARCH_7A,
 882     {
 883       ISA_ARMv7ve,
 884       isa_nobit
 885     },
 886     &arm_cortex_a7_tune
 887   },
 888   {
 889     "cortex-a8",
 890     TARGET_CPU_cortexa8,
 891     (TF_LDSCHED),
 892     "7A", BASE_ARCH_7A,
 893     {
 894       ISA_ARMv7a,
 895       isa_nobit
 896     },
 897     &arm_cortex_a8_tune
 898   },
 899   {
 900     "cortex-a9",
 901     TARGET_CPU_cortexa9,
 902     (TF_LDSCHED),
 903     "7A", BASE_ARCH_7A,
 904     {
 905       ISA_ARMv7a,
 906       isa_nobit
 907     },
 908     &arm_cortex_a9_tune
 909   },
 910   {
 911     "cortex-a12",
 912     TARGET_CPU_cortexa17,
 913     (TF_LDSCHED),
 914     "7A", BASE_ARCH_7A,
 915     {
 916       ISA_ARMv7ve,
 917       isa_nobit
 918     },
 919     &arm_cortex_a12_tune
 920   },
 921   {
 922     "cortex-a15",
 923     TARGET_CPU_cortexa15,
 924     (TF_LDSCHED),
 925     "7A", BASE_ARCH_7A,
 926     {
 927       ISA_ARMv7ve,
 928       isa_nobit
 929     },
 930     &arm_cortex_a15_tune
 931   },
 932   {
 933     "cortex-a17",
 934     TARGET_CPU_cortexa17,
 935     (TF_LDSCHED),
 936     "7A", BASE_ARCH_7A,
 937     {
 938       ISA_ARMv7ve,
 939       isa_nobit
 940     },
 941     &arm_cortex_a12_tune
 942   },
 943   {
 944     "cortex-r4",
 945     TARGET_CPU_cortexr4,
 946     (TF_LDSCHED),
 947     "7R", BASE_ARCH_7R,
 948     {
 949       ISA_ARMv7r,
 950       isa_nobit
 951     },
 952     &arm_cortex_tune
 953   },
 954   {
 955     "cortex-r4f",
 956     TARGET_CPU_cortexr4f,
 957     (TF_LDSCHED),
 958     "7R", BASE_ARCH_7R,
 959     {
 960       ISA_ARMv7r,
 961       isa_nobit
 962     },
 963     &arm_cortex_tune
 964   },
 965   {
 966     "cortex-r5",
 967     TARGET_CPU_cortexr5,
 968     (TF_LDSCHED),
 969     "7R", BASE_ARCH_7R,
 970     {
 971       ISA_ARMv7r,
 972       isa_bit_adiv,
 973       isa_nobit
 974     },
 975     &arm_cortex_tune
 976   },
 977   {
 978     "cortex-r7",
 979     TARGET_CPU_cortexr7,
 980     (TF_LDSCHED),
 981     "7R", BASE_ARCH_7R,
 982     {
 983       ISA_ARMv7r,
 984       isa_bit_adiv,
 985       isa_nobit
 986     },
 987     &arm_cortex_tune
 988   },
 989   {
 990     "cortex-r8",
 991     TARGET_CPU_cortexr7,
 992     (TF_LDSCHED),
 993     "7R", BASE_ARCH_7R,
 994     {
 995       ISA_ARMv7r,
 996       isa_bit_adiv,
 997       isa_nobit
 998     },
 999     &arm_cortex_tune
1000   },
1001   {
1002     "cortex-m7",
1003     TARGET_CPU_cortexm7,
1004     (TF_LDSCHED),
1005     "7EM", BASE_ARCH_7EM,
1006     {
1007       ISA_ARMv7em,
1008       isa_quirk_no_volatile_ce,
1009       isa_nobit
1010     },
1011     &arm_cortex_m7_tune
1012   },
1013   {
1014     "cortex-m4",
1015     TARGET_CPU_cortexm4,
1016     (TF_LDSCHED),
1017     "7EM", BASE_ARCH_7EM,
1018     {
1019       ISA_ARMv7em,
1020       isa_nobit
1021     },
1022     &arm_v7m_tune
1023   },
1024   {
1025     "cortex-m3",
1026     TARGET_CPU_cortexm3,
1027     (TF_LDSCHED),
1028     "7M", BASE_ARCH_7M,
1029     {
1030       ISA_ARMv7m,
1031       isa_quirk_cm3_ldrd,
1032       isa_nobit
1033     },
1034     &arm_v7m_tune
1035   },
1036   {
1037     "marvell-pj4",
1038     TARGET_CPU_marvell_pj4,
1039     (TF_LDSCHED),
1040     "7A", BASE_ARCH_7A,
1041     {
1042       ISA_ARMv7a,
1043       isa_nobit
1044     },
1045     &arm_marvell_pj4_tune
1046   },
1047   {
1048     "cortex-a15.cortex-a7",
1049     TARGET_CPU_cortexa7,
1050     (TF_LDSCHED),
1051     "7A", BASE_ARCH_7A,
1052     {
1053       ISA_ARMv7ve,
1054       isa_nobit
1055     },
1056     &arm_cortex_a15_tune
1057   },
1058   {
1059     "cortex-a17.cortex-a7",
1060     TARGET_CPU_cortexa7,
1061     (TF_LDSCHED),
1062     "7A", BASE_ARCH_7A,
1063     {
1064       ISA_ARMv7ve,
1065       isa_nobit
1066     },
1067     &arm_cortex_a12_tune
1068   },
1069   {
1070     "cortex-a32",
1071     TARGET_CPU_cortexa53,
1072     (TF_LDSCHED),
1073     "8A", BASE_ARCH_8A,
1074     {
1075       ISA_ARMv8a,isa_bit_crc32,
1076       isa_nobit
1077     },
1078     &arm_cortex_a35_tune
1079   },
1080   {
1081     "cortex-a35",
1082     TARGET_CPU_cortexa53,
1083     (TF_LDSCHED),
1084     "8A", BASE_ARCH_8A,
1085     {
1086       ISA_ARMv8a,isa_bit_crc32,
1087       isa_nobit
1088     },
1089     &arm_cortex_a35_tune
1090   },
1091   {
1092     "cortex-a53",
1093     TARGET_CPU_cortexa53,
1094     (TF_LDSCHED),
1095     "8A", BASE_ARCH_8A,
1096     {
1097       ISA_ARMv8a,isa_bit_crc32,
1098       isa_nobit
1099     },
1100     &arm_cortex_a53_tune
1101   },
1102   {
1103     "cortex-a57",
1104     TARGET_CPU_cortexa57,
1105     (TF_LDSCHED),
1106     "8A", BASE_ARCH_8A,
1107     {
1108       ISA_ARMv8a,isa_bit_crc32,
1109       isa_nobit
1110     },
1111     &arm_cortex_a57_tune
1112   },
1113   {
1114     "cortex-a72",
1115     TARGET_CPU_cortexa57,
1116     (TF_LDSCHED),
1117     "8A", BASE_ARCH_8A,
1118     {
1119       ISA_ARMv8a,isa_bit_crc32,
1120       isa_nobit
1121     },
1122     &arm_cortex_a57_tune
1123   },
1124   {
1125     "cortex-a73",
1126     TARGET_CPU_cortexa57,
1127     (TF_LDSCHED),
1128     "8A", BASE_ARCH_8A,
1129     {
1130       ISA_ARMv8a,isa_bit_crc32,
1131       isa_nobit
1132     },
1133     &arm_cortex_a73_tune
1134   },
1135   {
1136     "exynos-m1",
1137     TARGET_CPU_exynosm1,
1138     (TF_LDSCHED),
1139     "8A", BASE_ARCH_8A,
1140     {
1141       ISA_ARMv8a,isa_bit_crc32,
1142       isa_nobit
1143     },
1144     &arm_exynosm1_tune
1145   },
1146   {
1147     "xgene1",
1148     TARGET_CPU_xgene1,
1149     (TF_LDSCHED),
1150     "8A", BASE_ARCH_8A,
1151     {
1152       ISA_ARMv8a,
1153       isa_nobit
1154     },
1155     &arm_xgene1_tune
1156   },
1157   {
1158     "cortex-a57.cortex-a53",
1159     TARGET_CPU_cortexa53,
1160     (TF_LDSCHED),
1161     "8A", BASE_ARCH_8A,
1162     {
1163       ISA_ARMv8a,isa_bit_crc32,
1164       isa_nobit
1165     },
1166     &arm_cortex_a57_tune
1167   },
1168   {
1169     "cortex-a72.cortex-a53",
1170     TARGET_CPU_cortexa53,
1171     (TF_LDSCHED),
1172     "8A", BASE_ARCH_8A,
1173     {
1174       ISA_ARMv8a,isa_bit_crc32,
1175       isa_nobit
1176     },
1177     &arm_cortex_a57_tune
1178   },
1179   {
1180     "cortex-a73.cortex-a35",
1181     TARGET_CPU_cortexa53,
1182     (TF_LDSCHED),
1183     "8A", BASE_ARCH_8A,
1184     {
1185       ISA_ARMv8a,isa_bit_crc32,
1186       isa_nobit
1187     },
1188     &arm_cortex_a73_tune
1189   },
1190   {
1191     "cortex-a73.cortex-a53",
1192     TARGET_CPU_cortexa53,
1193     (TF_LDSCHED),
1194     "8A", BASE_ARCH_8A,
1195     {
1196       ISA_ARMv8a,isa_bit_crc32,
1197       isa_nobit
1198     },
1199     &arm_cortex_a73_tune
1200   },
1201   {
1202     "cortex-m23",
1203     TARGET_CPU_cortexm23,
1204     (TF_LDSCHED),
1205     "8M_BASE", BASE_ARCH_8M_BASE,
1206     {
1207       ISA_ARMv8m_base,
1208       isa_nobit
1209     },
1210     &arm_v6m_tune
1211   },
1212   {
1213     "cortex-m33",
1214     TARGET_CPU_cortexm33,
1215     (TF_LDSCHED),
1216     "8M_MAIN", BASE_ARCH_8M_MAIN,
1217     {
1218       ISA_ARMv8m_main,isa_bit_ARMv7em,
1219       isa_nobit
1220     },
1221     &arm_v7m_tune
1222   },
1223   {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, {isa_nobit}, NULL}
1224 };
1225
1226 static const struct processors all_architectures[] =
1227 {
1228   {
1229     "armv2", TARGET_CPU_arm2,
1230     (TF_CO_PROC | TF_NO_MODE32),
1231     "2", BASE_ARCH_2,
1232     {
1233       ISA_ARMv2,isa_bit_mode26,
1234       isa_nobit
1235     },
1236     NULL
1237   },
1238   {
1239     "armv2a", TARGET_CPU_arm2,
1240     (TF_CO_PROC | TF_NO_MODE32),
1241     "2", BASE_ARCH_2,
1242     {
1243       ISA_ARMv2,isa_bit_mode26,
1244       isa_nobit
1245     },
1246     NULL
1247   },
1248   {
1249     "armv3", TARGET_CPU_arm6,
1250     (TF_CO_PROC),
1251     "3", BASE_ARCH_3,
1252     {
1253       ISA_ARMv3,isa_bit_mode26,
1254       isa_nobit
1255     },
1256     NULL
1257   },
1258   {
1259     "armv3m", TARGET_CPU_arm7m,
1260     (TF_CO_PROC),
1261     "3M", BASE_ARCH_3M,
1262     {
1263       ISA_ARMv3m,isa_bit_mode26,
1264       isa_nobit
1265     },
1266     NULL
1267   },
1268   {
1269     "armv4", TARGET_CPU_arm7tdmi,
1270     (TF_CO_PROC),
1271     "4", BASE_ARCH_4,
1272     {
1273       ISA_ARMv4,isa_bit_mode26,
1274       isa_nobit
1275     },
1276     NULL
1277   },
1278   {
1279     "armv4t", TARGET_CPU_arm7tdmi,
1280     (TF_CO_PROC),
1281     "4T", BASE_ARCH_4T,
1282     {
1283       ISA_ARMv4t,
1284       isa_nobit
1285     },
1286     NULL
1287   },
1288   {
1289     "armv5", TARGET_CPU_arm10tdmi,
1290     (TF_CO_PROC),
1291     "5", BASE_ARCH_5,
1292     {
1293       ISA_ARMv5,
1294       isa_nobit
1295     },
1296     NULL
1297   },
1298   {
1299     "armv5t", TARGET_CPU_arm10tdmi,
1300     (TF_CO_PROC),
1301     "5T", BASE_ARCH_5T,
1302     {
1303       ISA_ARMv5t,
1304       isa_nobit
1305     },
1306     NULL
1307   },
1308   {
1309     "armv5e", TARGET_CPU_arm1026ejs,
1310     (TF_CO_PROC),
1311     "5E", BASE_ARCH_5E,
1312     {
1313       ISA_ARMv5e,
1314       isa_nobit
1315     },
1316     NULL
1317   },
1318   {
1319     "armv5te", TARGET_CPU_arm1026ejs,
1320     (TF_CO_PROC),
1321     "5TE", BASE_ARCH_5TE,
1322     {
1323       ISA_ARMv5te,
1324       isa_nobit
1325     },
1326     NULL
1327   },
1328   {
1329     "armv5tej", TARGET_CPU_arm1026ejs,
1330     (TF_CO_PROC),
1331     "5TEJ", BASE_ARCH_5TEJ,
1332     {
1333       ISA_ARMv5tej,
1334       isa_nobit
1335     },
1336     NULL
1337   },
1338   {
1339     "armv6", TARGET_CPU_arm1136js,
1340     (TF_CO_PROC),
1341     "6", BASE_ARCH_6,
1342     {
1343       ISA_ARMv6,
1344       isa_nobit
1345     },
1346     NULL
1347   },
1348   {
1349     "armv6j", TARGET_CPU_arm1136js,
1350     (TF_CO_PROC),
1351     "6J", BASE_ARCH_6J,
1352     {
1353       ISA_ARMv6j,
1354       isa_nobit
1355     },
1356     NULL
1357   },
1358   {
1359     "armv6k", TARGET_CPU_mpcore,
1360     (TF_CO_PROC),
1361     "6K", BASE_ARCH_6K,
1362     {
1363       ISA_ARMv6k,
1364       isa_nobit
1365     },
1366     NULL
1367   },
1368   {
1369     "armv6z", TARGET_CPU_arm1176jzs,
1370     (TF_CO_PROC),
1371     "6Z", BASE_ARCH_6Z,
1372     {
1373       ISA_ARMv6z,
1374       isa_nobit
1375     },
1376     NULL
1377   },
1378   {
1379     "armv6kz", TARGET_CPU_arm1176jzs,
1380     (TF_CO_PROC),
1381     "6KZ", BASE_ARCH_6KZ,
1382     {
1383       ISA_ARMv6kz,
1384       isa_nobit
1385     },
1386     NULL
1387   },
1388   {
1389     "armv6zk", TARGET_CPU_arm1176jzs,
1390     (TF_CO_PROC),
1391     "6KZ", BASE_ARCH_6KZ,
1392     {
1393       ISA_ARMv6kz,
1394       isa_nobit
1395     },
1396     NULL
1397   },
1398   {
1399     "armv6t2", TARGET_CPU_arm1156t2s,
1400     (TF_CO_PROC),
1401     "6T2", BASE_ARCH_6T2,
1402     {
1403       ISA_ARMv6t2,
1404       isa_nobit
1405     },
1406     NULL
1407   },
1408   {
1409     "armv6-m", TARGET_CPU_cortexm1,
1410     0,
1411     "6M", BASE_ARCH_6M,
1412     {
1413       ISA_ARMv6m,
1414       isa_nobit
1415     },
1416     NULL
1417   },
1418   {
1419     "armv6s-m", TARGET_CPU_cortexm1,
1420     0,
1421     "6M", BASE_ARCH_6M,
1422     {
1423       ISA_ARMv6m,
1424       isa_nobit
1425     },
1426     NULL
1427   },
1428   {
1429     "armv7", TARGET_CPU_cortexa8,
1430     (TF_CO_PROC),
1431     "7", BASE_ARCH_7,
1432     {
1433       ISA_ARMv7,
1434       isa_nobit
1435     },
1436     NULL
1437   },
1438   {
1439     "armv7-a", TARGET_CPU_cortexa8,
1440     (TF_CO_PROC),
1441     "7A", BASE_ARCH_7A,
1442     {
1443       ISA_ARMv7a,
1444       isa_nobit
1445     },
1446     NULL
1447   },
1448   {
1449     "armv7ve", TARGET_CPU_cortexa8,
1450     (TF_CO_PROC),
1451     "7A", BASE_ARCH_7A,
1452     {
1453       ISA_ARMv7ve,
1454       isa_nobit
1455     },
1456     NULL
1457   },
1458   {
1459     "armv7-r", TARGET_CPU_cortexr4,
1460     (TF_CO_PROC),
1461     "7R", BASE_ARCH_7R,
1462     {
1463       ISA_ARMv7r,
1464       isa_nobit
1465     },
1466     NULL
1467   },
1468   {
1469     "armv7-m", TARGET_CPU_cortexm3,
1470     (TF_CO_PROC),
1471     "7M", BASE_ARCH_7M,
1472     {
1473       ISA_ARMv7m,
1474       isa_nobit
1475     },
1476     NULL
1477   },
1478   {
1479     "armv7e-m", TARGET_CPU_cortexm4,
1480     (TF_CO_PROC),
1481     "7EM", BASE_ARCH_7EM,
1482     {
1483       ISA_ARMv7em,
1484       isa_nobit
1485     },
1486     NULL
1487   },
1488   {
1489     "armv8-a", TARGET_CPU_cortexa53,
1490     (TF_CO_PROC),
1491     "8A", BASE_ARCH_8A,
1492     {
1493       ISA_ARMv8a,
1494       isa_nobit
1495     },
1496     NULL
1497   },
1498   {
1499     "armv8-a+crc", TARGET_CPU_cortexa53,
1500     (TF_CO_PROC),
1501     "8A", BASE_ARCH_8A,
1502     {
1503       ISA_ARMv8a,isa_bit_crc32,
1504       isa_nobit
1505     },
1506     NULL
1507   },
1508   {
1509     "armv8.1-a", TARGET_CPU_cortexa53,
1510     (TF_CO_PROC),
1511     "8A", BASE_ARCH_8A,
1512     {
1513       ISA_ARMv8_1a,
1514       isa_nobit
1515     },
1516     NULL
1517   },
1518   {
1519     "armv8.2-a", TARGET_CPU_cortexa53,
1520     (TF_CO_PROC),
1521     "8A", BASE_ARCH_8A,
1522     {
1523       ISA_ARMv8_2a,
1524       isa_nobit
1525     },
1526     NULL
1527   },
1528   {
1529     "armv8.2-a+fp16", TARGET_CPU_cortexa53,
1530     (TF_CO_PROC),
1531     "8A", BASE_ARCH_8A,
1532     {
1533       ISA_ARMv8_2a,isa_bit_fp16,
1534       isa_nobit
1535     },
1536     NULL
1537   },
1538   {
1539     "armv8-m.base", TARGET_CPU_cortexm23,
1540     0,
1541     "8M_BASE", BASE_ARCH_8M_BASE,
1542     {
1543       ISA_ARMv8m_base,
1544       isa_nobit
1545     },
1546     NULL
1547   },
1548   {
1549     "armv8-m.main", TARGET_CPU_cortexm7,
1550     (TF_CO_PROC),
1551     "8M_MAIN", BASE_ARCH_8M_MAIN,
1552     {
1553       ISA_ARMv8m_main,
1554       isa_nobit
1555     },
1556     NULL
1557   },
1558   {
1559     "armv8-m.main+dsp", TARGET_CPU_cortexm33,
1560     (TF_CO_PROC),
1561     "8M_MAIN", BASE_ARCH_8M_MAIN,
1562     {
1563       ISA_ARMv8m_main,isa_bit_ARMv7em,
1564       isa_nobit
1565     },
1566     NULL
1567   },
1568   {
1569     "iwmmxt", TARGET_CPU_iwmmxt,
1570     (TF_LDSCHED | TF_STRONG | TF_XSCALE),
1571     "5TE", BASE_ARCH_5TE,
1572     {
1573       ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,
1574       isa_nobit
1575     },
1576     NULL
1577   },
1578   {
1579     "iwmmxt2", TARGET_CPU_iwmmxt2,
1580     (TF_LDSCHED | TF_STRONG | TF_XSCALE),
1581     "5TE", BASE_ARCH_5TE,
1582     {
1583       ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,isa_bit_iwmmxt2,
1584       isa_nobit
1585     },
1586     NULL
1587   },
1588   {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, {isa_nobit}, NULL}
1589 };
1590
1591 const struct arm_fpu_desc all_fpus[] =
1592 {
1593   {
1594     "vfp",
1595     {
1596       ISA_VFPv2,ISA_FP_DBL,
1597       isa_nobit
1598     }
1599   },
1600   {
1601     "vfpv2",
1602     {
1603       ISA_VFPv2,ISA_FP_DBL,
1604       isa_nobit
1605     }
1606   },
1607   {
1608     "vfpv3",
1609     {
1610       ISA_VFPv3,ISA_FP_D32,
1611       isa_nobit
1612     }
1613   },
1614   {
1615     "vfpv3-fp16",
1616     {
1617       ISA_VFPv3,ISA_FP_D32,isa_bit_fp16conv,
1618       isa_nobit
1619     }
1620   },
1621   {
1622     "vfpv3-d16",
1623     {
1624       ISA_VFPv3,ISA_FP_DBL,
1625       isa_nobit
1626     }
1627   },
1628   {
1629     "vfpv3-d16-fp16",
1630     {
1631       ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv,
1632       isa_nobit
1633     }
1634   },
1635   {
1636     "vfpv3xd",
1637     {
1638       ISA_VFPv3,
1639       isa_nobit
1640     }
1641   },
1642   {
1643     "vfpv3xd-fp16",
1644     {
1645       ISA_VFPv3,isa_bit_fp16conv,
1646       isa_nobit
1647     }
1648   },
1649   {
1650     "neon",
1651     {
1652       ISA_VFPv3,ISA_NEON,
1653       isa_nobit
1654     }
1655   },
1656   {
1657     "neon-vfpv3",
1658     {
1659       ISA_VFPv3,ISA_NEON,
1660       isa_nobit
1661     }
1662   },
1663   {
1664     "neon-fp16",
1665     {
1666       ISA_VFPv3,ISA_NEON,isa_bit_fp16conv,
1667       isa_nobit
1668     }
1669   },
1670   {
1671     "vfpv4",
1672     {
1673       ISA_VFPv4,ISA_FP_D32,
1674       isa_nobit
1675     }
1676   },
1677   {
1678     "neon-vfpv4",
1679     {
1680       ISA_VFPv4,ISA_NEON,
1681       isa_nobit
1682     }
1683   },
1684   {
1685     "vfpv4-d16",
1686     {
1687       ISA_VFPv4,ISA_FP_DBL,
1688       isa_nobit
1689     }
1690   },
1691   {
1692     "fpv4-sp-d16",
1693     {
1694       ISA_VFPv4,
1695       isa_nobit
1696     }
1697   },
1698   {
1699     "fpv5-sp-d16",
1700     {
1701       ISA_FPv5,
1702       isa_nobit
1703     }
1704   },
1705   {
1706     "fpv5-d16",
1707     {
1708       ISA_FPv5,ISA_FP_DBL,
1709       isa_nobit
1710     }
1711   },
1712   {
1713     "fp-armv8",
1714     {
1715       ISA_FP_ARMv8,ISA_FP_D32,
1716       isa_nobit
1717     }
1718   },
1719   {
1720     "neon-fp-armv8",
1721     {
1722       ISA_FP_ARMv8,ISA_NEON,
1723       isa_nobit
1724     }
1725   },
1726   {
1727     "crypto-neon-fp-armv8",
1728     {
1729       ISA_FP_ARMv8,ISA_CRYPTO,
1730       isa_nobit
1731     }
1732   },
1733   {
1734     "vfp3",
1735     {
1736       ISA_VFPv3,ISA_FP_D32,
1737       isa_nobit
1738     }
1739   },
1740 };