gcc/config/arm/arm-generic.md

   1 ;; Generic ARM Pipeline Description
   2 ;; Copyright (C) 2003-2016 Free Software Foundation, Inc.
   3 ;;
   4 ;; This file is part of GCC.
   5 ;;
   6 ;; GCC is free software; you can redistribute it and/or modify it
   7 ;; under the terms of the GNU General Public License as published by
   8 ;; the Free Software Foundation; either version 3, or (at your option)
   9 ;; any later version.
  10 ;;
  11 ;; GCC is distributed in the hope that it will be useful, but
  12 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 ;; General Public License for more details.
  15 ;;
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING3.  If not see
  18 ;; <http://www.gnu.org/licenses/>.  */
  19
  20 (define_automaton "arm")
  21
  22 ;; Write buffer
  23 ;
  24 ; Strictly, we should model a 4-deep write buffer for ARM7xx based chips
  25 ;
  26 ; The write buffer on some of the arm6 processors is hard to model exactly.
  27 ; There is room in the buffer for up to two addresses and up to eight words
  28 ; of memory, but the two needn't be split evenly.  When writing the two
  29 ; addresses are fully pipelined.  However, a read from memory that is not
  30 ; currently in the cache will block until the writes have completed.
  31 ; It is normally the case that FCLK and MCLK will be in the ratio 2:1, so
  32 ; writes will take 2 FCLK cycles per word, if FCLK and MCLK are asynchronous
  33 ; (they aren't allowed to be at present) then there is a startup cost of 1MCLK
  34 ; cycle to add as well.
  35 (define_cpu_unit "write_buf" "arm")
  36
  37 ;; Write blockage unit
  38 ;
  39 ; The write_blockage unit models (partially), the fact that reads will stall
  40 ; until the write buffer empties.
  41 (define_cpu_unit "write_blockage" "arm")
  42
  43 ;; Core
  44 ;
  45 (define_cpu_unit "core" "arm")
  46
  47 (define_insn_reservation "store_wbuf" 5
  48   (and (eq_attr "generic_sched" "yes")
  49        (and (eq_attr "model_wbuf" "yes")
  50             (eq_attr "type" "store1")))
  51   "core+write_buf*3+write_blockage*5")
  52
  53 (define_insn_reservation "store2_wbuf" 7
  54   (and (eq_attr "generic_sched" "yes")
  55        (and (eq_attr "model_wbuf" "yes")
  56             (eq_attr "type" "store2")))
  57   "core+write_buf*4+write_blockage*7")
  58
  59 (define_insn_reservation "store3_wbuf" 9
  60   (and (eq_attr "generic_sched" "yes")
  61        (and (eq_attr "model_wbuf" "yes")
  62             (eq_attr "type" "store3")))
  63   "core+write_buf*5+write_blockage*9")
  64
  65 (define_insn_reservation "store4_wbuf" 11
  66   (and (eq_attr "generic_sched" "yes")
  67        (and (eq_attr "model_wbuf" "yes")
  68             (eq_attr "type" "store4")))
  69   "core+write_buf*6+write_blockage*11")
  70
  71 (define_insn_reservation "store2" 3
  72   (and (eq_attr "generic_sched" "yes")
  73        (and (eq_attr "model_wbuf" "no")
  74             (eq_attr "type" "store2")))
  75   "core*3")
  76
  77 (define_insn_reservation "store3" 4
  78   (and (eq_attr "generic_sched" "yes")
  79        (and (eq_attr "model_wbuf" "no")
  80             (eq_attr "type" "store3")))
  81   "core*4")
  82
  83 (define_insn_reservation "store4" 5
  84   (and (eq_attr "generic_sched" "yes")
  85        (and (eq_attr "model_wbuf" "no")
  86             (eq_attr "type" "store4")))
  87   "core*5")
  88
  89 (define_insn_reservation "store_ldsched" 1
  90   (and (eq_attr "generic_sched" "yes")
  91        (and (eq_attr "ldsched" "yes")
  92             (eq_attr "type" "store1")))
  93   "core")
  94
  95 (define_insn_reservation "load_ldsched_xscale" 3
  96   (and (eq_attr "generic_sched" "yes")
  97        (and (eq_attr "ldsched" "yes")
  98             (and (eq_attr "type" "load_byte,load1")
  99                  (eq_attr "tune" "xscale,iwmmxt,iwmmxt2"))))
 100   "core")
 101
 102 (define_insn_reservation "load_ldsched" 2
 103   (and (eq_attr "generic_sched" "yes")
 104        (and (eq_attr "ldsched" "yes")
 105             (and (eq_attr "type" "load_byte,load1")
 106                  (eq_attr "tune" "!xscale,iwmmxt,iwmmxt2"))))
 107   "core")
 108
 109 (define_insn_reservation "load_or_store" 2
 110   (and (eq_attr "generic_sched" "yes")
 111        (and (eq_attr "ldsched" "!yes")
 112             (eq_attr "type" "load_byte,load1,load2,load3,load4,store1")))
 113   "core*2")
 114
 115 (define_insn_reservation "mult" 16
 116   (and (eq_attr "generic_sched" "yes")
 117        (and (eq_attr "ldsched" "no")
 118             (ior (eq_attr "mul32" "yes")
 119                  (eq_attr "mul64" "yes"))))
 120   "core*16")
 121
 122 (define_insn_reservation "mult_ldsched_strongarm" 3
 123   (and (eq_attr "generic_sched" "yes")
 124        (and (eq_attr "ldsched" "yes")
 125             (and (eq_attr "tune"
 126                   "strongarm,strongarm110,strongarm1100,strongarm1110")
 127                  (ior (eq_attr "mul32" "yes")
 128                       (eq_attr "mul64" "yes")))))
 129   "core*2")
 130
 131 (define_insn_reservation "mult_ldsched" 4
 132   (and (eq_attr "generic_sched" "yes")
 133        (and (eq_attr "ldsched" "yes")
 134             (and (eq_attr "tune"
 135                   "!strongarm,strongarm110,strongarm1100,strongarm1110")
 136                  (ior (eq_attr "mul32" "yes")
 137                       (eq_attr "mul64" "yes")))))
 138   "core*4")
 139
 140 (define_insn_reservation "multi_cycle" 32
 141   (and (eq_attr "generic_sched" "yes")
 142        (and (eq_attr "core_cycles" "multi")
 143             (and (eq_attr "type" "!load_byte,load1,load2,load3,load4,\
 144                                   store1,store2,store3,store4")
 145                  (not (ior (eq_attr "mul32" "yes")
 146                            (eq_attr "mul64" "yes"))))))
 147   "core*32")
 148
 149 (define_insn_reservation "single_cycle" 1
 150   (and (eq_attr "generic_sched" "yes")
 151        (eq_attr "core_cycles" "single"))
 152   "core")