1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991-2014 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rearnsha@arm.com)
6 Minor hacks by Nick Clifton (nickc@cygnus.com)
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 3, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 Under Section 7 of GPL version 3, you are granted additional
21 permissions described in the GCC Runtime Library Exception, version
22 3.1, as published by the Free Software Foundation.
24 You should have received a copy of the GNU General Public License and
25 a copy of the GCC Runtime Library Exception along with this program;
26 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
27 <http://www.gnu.org/licenses/>. */
32 /* We can't use machine_mode inside a generator file because it
33 hasn't been created yet; we shouldn't be using any code that
34 needs the real definition though, so this ought to be safe. */
38 #include "insn-modes.h"
39 #define MACHMODE machine_mode
42 #include "config/vxworks-dummy.h"
44 /* The architecture define. */
45 extern char arm_arch_name
[];
47 /* Target CPU builtins. */
48 #define TARGET_CPU_CPP_BUILTINS() \
51 if (TARGET_DSP_MULTIPLY) \
52 builtin_define ("__ARM_FEATURE_DSP"); \
53 if (TARGET_ARM_QBIT) \
54 builtin_define ("__ARM_FEATURE_QBIT"); \
56 builtin_define ("__ARM_FEATURE_SAT"); \
58 builtin_define ("__ARM_FEATURE_CRYPTO"); \
59 if (unaligned_access) \
60 builtin_define ("__ARM_FEATURE_UNALIGNED"); \
62 builtin_define ("__ARM_FEATURE_CRC32"); \
64 builtin_define ("__ARM_32BIT_STATE"); \
65 if (TARGET_ARM_FEATURE_LDREX) \
66 builtin_define_with_int_value ( \
67 "__ARM_FEATURE_LDREX", TARGET_ARM_FEATURE_LDREX); \
68 if ((TARGET_ARM_ARCH >= 5 && !TARGET_THUMB) \
69 || TARGET_ARM_ARCH_ISA_THUMB >=2) \
70 builtin_define ("__ARM_FEATURE_CLZ"); \
71 if (TARGET_INT_SIMD) \
72 builtin_define ("__ARM_FEATURE_SIMD32"); \
74 builtin_define_with_int_value ( \
75 "__ARM_SIZEOF_MINIMAL_ENUM", \
76 flag_short_enums ? 1 : 4); \
77 builtin_define_type_sizeof ("__ARM_SIZEOF_WCHAR_T", \
79 if (TARGET_ARM_ARCH_PROFILE) \
80 builtin_define_with_int_value ( \
81 "__ARM_ARCH_PROFILE", TARGET_ARM_ARCH_PROFILE); \
83 /* Define __arm__ even when in thumb mode, for \
84 consistency with armcc. */ \
85 builtin_define ("__arm__"); \
86 if (TARGET_ARM_ARCH) \
87 builtin_define_with_int_value ( \
88 "__ARM_ARCH", TARGET_ARM_ARCH); \
90 builtin_define ("__ARM_ARCH_ISA_ARM"); \
91 builtin_define ("__APCS_32__"); \
93 builtin_define ("__thumb__"); \
95 builtin_define ("__thumb2__"); \
96 if (TARGET_ARM_ARCH_ISA_THUMB) \
97 builtin_define_with_int_value ( \
98 "__ARM_ARCH_ISA_THUMB", \
99 TARGET_ARM_ARCH_ISA_THUMB); \
101 if (TARGET_BIG_END) \
103 builtin_define ("__ARMEB__"); \
104 builtin_define ("__ARM_BIG_ENDIAN"); \
106 builtin_define ("__THUMBEB__"); \
110 builtin_define ("__ARMEL__"); \
112 builtin_define ("__THUMBEL__"); \
115 if (TARGET_SOFT_FLOAT) \
116 builtin_define ("__SOFTFP__"); \
119 builtin_define ("__VFP_FP__"); \
122 builtin_define_with_int_value ( \
123 "__ARM_FP", TARGET_ARM_FP); \
124 if (arm_fp16_format == ARM_FP16_FORMAT_IEEE) \
125 builtin_define ("__ARM_FP16_FORMAT_IEEE"); \
126 if (arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE) \
127 builtin_define ("__ARM_FP16_FORMAT_ALTERNATIVE"); \
129 builtin_define ("__ARM_FEATURE_FMA"); \
133 builtin_define ("__ARM_NEON__"); \
134 builtin_define ("__ARM_NEON"); \
136 if (TARGET_NEON_FP) \
137 builtin_define_with_int_value ( \
138 "__ARM_NEON_FP", TARGET_NEON_FP); \
140 /* Add a define for interworking. \
141 Needed when building libgcc.a. */ \
142 if (arm_cpp_interwork) \
143 builtin_define ("__THUMB_INTERWORK__"); \
145 builtin_assert ("cpu=arm"); \
146 builtin_assert ("machine=arm"); \
148 builtin_define (arm_arch_name); \
149 if (arm_arch_xscale) \
150 builtin_define ("__XSCALE__"); \
151 if (arm_arch_iwmmxt) \
153 builtin_define ("__IWMMXT__"); \
154 builtin_define ("__ARM_WMMX"); \
156 if (arm_arch_iwmmxt2) \
157 builtin_define ("__IWMMXT2__"); \
158 if (TARGET_AAPCS_BASED) \
160 if (arm_pcs_default == ARM_PCS_AAPCS_VFP) \
161 builtin_define ("__ARM_PCS_VFP"); \
162 else if (arm_pcs_default == ARM_PCS_AAPCS) \
163 builtin_define ("__ARM_PCS"); \
164 builtin_define ("__ARM_EABI__"); \
168 builtin_define ("__ARM_ARCH_EXT_IDIV__"); \
169 builtin_define ("__ARM_FEATURE_IDIV__"); \
173 #include "config/arm/arm-opts.h"
177 #define ARM_CORE(NAME, INTERNAL_IDENT, IDENT, ARCH, FLAGS, COSTS) \
178 TARGET_CPU_##INTERNAL_IDENT,
179 #include "arm-cores.def"
184 /* The processor for which instructions should be scheduled. */
185 extern enum processor_type arm_tune
;
187 typedef enum arm_cond_code
189 ARM_EQ
= 0, ARM_NE
, ARM_CS
, ARM_CC
, ARM_MI
, ARM_PL
, ARM_VS
, ARM_VC
,
190 ARM_HI
, ARM_LS
, ARM_GE
, ARM_LT
, ARM_GT
, ARM_LE
, ARM_AL
, ARM_NV
194 extern arm_cc arm_current_cc
;
196 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
198 /* The maximum number of instructions that is beneficial to
199 conditionally execute. */
200 #undef MAX_CONDITIONAL_EXECUTE
201 #define MAX_CONDITIONAL_EXECUTE arm_max_conditional_execute ()
203 extern int arm_target_label
;
204 extern int arm_ccfsm_state
;
205 extern GTY(()) rtx arm_target_insn
;
206 /* The label of the current constant pool. */
207 extern rtx pool_vector_label
;
208 /* Set to 1 when a return insn is output, this means that the epilogue
210 extern int return_used_this_function
;
211 /* Callback to output language specific object attributes. */
212 extern void (*arm_lang_output_object_attributes_hook
)(void);
214 /* Just in case configure has failed to define anything. */
215 #ifndef TARGET_CPU_DEFAULT
216 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
221 #define CPP_SPEC "%(subtarget_cpp_spec) \
222 %{mfloat-abi=soft:%{mfloat-abi=hard: \
223 %e-mfloat-abi=soft and -mfloat-abi=hard may not be used together}} \
224 %{mbig-endian:%{mlittle-endian: \
225 %e-mbig-endian and -mlittle-endian may not be used together}}"
231 /* This macro defines names of additional specifications to put in the specs
232 that can be used in various specifications like CC1_SPEC. Its definition
233 is an initializer with a subgrouping for each command option.
235 Each subgrouping contains a string constant, that defines the
236 specification name, and a string constant that used by the GCC driver
239 Do not define this macro if it does not need to do anything. */
240 #define EXTRA_SPECS \
241 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
242 { "asm_cpu_spec", ASM_CPU_SPEC }, \
243 SUBTARGET_EXTRA_SPECS
245 #ifndef SUBTARGET_EXTRA_SPECS
246 #define SUBTARGET_EXTRA_SPECS
249 #ifndef SUBTARGET_CPP_SPEC
250 #define SUBTARGET_CPP_SPEC ""
253 /* Run-time Target Specification. */
254 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
255 /* Use hardware floating point instructions. */
256 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
257 /* Use hardware floating point calling convention. */
258 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
259 #define TARGET_VFP (arm_fpu_desc->model == ARM_FP_MODEL_VFP)
260 #define TARGET_IWMMXT (arm_arch_iwmmxt)
261 #define TARGET_IWMMXT2 (arm_arch_iwmmxt2)
262 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT)
263 #define TARGET_REALLY_IWMMXT2 (TARGET_IWMMXT2 && TARGET_32BIT)
264 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT)
265 #define TARGET_ARM (! TARGET_THUMB)
266 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
267 #define TARGET_BACKTRACE (leaf_function_p () \
268 ? TARGET_TPCS_LEAF_FRAME \
270 #define TARGET_AAPCS_BASED \
271 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
273 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
274 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
275 #define TARGET_GNU2_TLS (target_tls_dialect == TLS_GNU2)
277 /* Only 16-bit thumb code. */
278 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2)
279 /* Arm or Thumb-2 32-bit code. */
280 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2)
281 /* 32-bit Thumb-2 code. */
282 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2)
284 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm)
286 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN \
289 #define TARGET_CRC32 (arm_arch_crc)
291 /* The following two macros concern the ability to execute coprocessor
292 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently
293 only ever tested when we know we are generating for VFP hardware; we need
294 to be more careful with TARGET_NEON as noted below. */
296 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */
297 #define TARGET_VFPD32 (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_D32)
299 /* FPU supports VFPv3 instructions. */
300 #define TARGET_VFP3 (TARGET_VFP && arm_fpu_desc->rev >= 3)
302 /* FPU supports FPv5 instructions. */
303 #define TARGET_VFP5 (TARGET_VFP && arm_fpu_desc->rev >= 5)
305 /* FPU only supports VFP single-precision instructions. */
306 #define TARGET_VFP_SINGLE (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_SINGLE)
308 /* FPU supports VFP double-precision instructions. */
309 #define TARGET_VFP_DOUBLE (TARGET_VFP && arm_fpu_desc->regs != VFP_REG_SINGLE)
311 /* FPU supports half-precision floating-point with NEON element load/store. */
312 #define TARGET_NEON_FP16 \
313 (TARGET_VFP && arm_fpu_desc->neon && arm_fpu_desc->fp16)
315 /* FPU supports VFP half-precision floating-point. */
316 #define TARGET_FP16 (TARGET_VFP && arm_fpu_desc->fp16)
318 /* FPU supports fused-multiply-add operations. */
319 #define TARGET_FMA (TARGET_VFP && arm_fpu_desc->rev >= 4)
321 /* FPU is ARMv8 compatible. */
322 #define TARGET_FPU_ARMV8 (TARGET_VFP && arm_fpu_desc->rev >= 8)
324 /* FPU supports Crypto extensions. */
325 #define TARGET_CRYPTO (TARGET_VFP && arm_fpu_desc->crypto)
327 /* FPU supports Neon instructions. The setting of this macro gets
328 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT
329 and TARGET_HARD_FLOAT to ensure that NEON instructions are
331 #define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \
332 && TARGET_VFP && arm_fpu_desc->neon)
334 /* Q-bit is present. */
335 #define TARGET_ARM_QBIT \
336 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7))
337 /* Saturation operation, e.g. SSAT. */
338 #define TARGET_ARM_SAT \
339 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7))
340 /* "DSP" multiply instructions, eg. SMULxy. */
341 #define TARGET_DSP_MULTIPLY \
342 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7em))
343 /* Integer SIMD instructions, and extend-accumulate instructions. */
344 #define TARGET_INT_SIMD \
345 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em))
347 /* Should MOVW/MOVT be used in preference to a constant pool. */
348 #define TARGET_USE_MOVT \
350 && (arm_disable_literal_pool \
351 || (!optimize_size && !current_tune->prefer_constant_pool)))
353 /* We could use unified syntax for arm mode, but for now we just use it
355 #define TARGET_UNIFIED_ASM TARGET_THUMB2
357 /* Nonzero if this chip provides the DMB instruction. */
358 #define TARGET_HAVE_DMB (arm_arch6m || arm_arch7)
360 /* Nonzero if this chip implements a memory barrier via CP15. */
361 #define TARGET_HAVE_DMB_MCR (arm_arch6 && ! TARGET_HAVE_DMB \
364 /* Nonzero if this chip implements a memory barrier instruction. */
365 #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR)
367 /* Nonzero if this chip supports ldrex and strex */
368 #define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7)
370 /* Nonzero if this chip supports ldrex{bh} and strex{bh}. */
371 #define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) || arm_arch7)
373 /* Nonzero if this chip supports ldrexd and strexd. */
374 #define TARGET_HAVE_LDREXD (((arm_arch6k && TARGET_ARM) || arm_arch7) \
377 /* Nonzero if this chip supports load-acquire and store-release. */
378 #define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8)
380 /* Nonzero if integer division instructions supported. */
381 #define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \
382 || (TARGET_THUMB2 && arm_arch_thumb_hwdiv))
384 /* Should NEON be used for 64-bits bitops. */
385 #define TARGET_PREFER_NEON_64BITS (prefer_neon_for_64bits)
387 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
388 then TARGET_AAPCS_BASED must be true -- but the converse does not
389 hold. TARGET_BPABI implies the use of the BPABI runtime library,
390 etc., in addition to just the AAPCS calling conventions. */
392 #define TARGET_BPABI false
395 /* Support for a compile-time default CPU, et cetera. The rules are:
396 --with-arch is ignored if -march or -mcpu are specified.
397 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
399 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
401 --with-float is ignored if -mfloat-abi is specified.
402 --with-fpu is ignored if -mfpu is specified.
403 --with-abi is ignored if -mabi is specified.
404 --with-tls is ignored if -mtls-dialect is specified. */
405 #define OPTION_DEFAULT_SPECS \
406 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
407 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
408 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
409 {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" }, \
410 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
411 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \
412 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"}, \
413 {"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"},
415 /* Which floating point model to use. */
418 ARM_FP_MODEL_UNKNOWN
,
419 /* VFP floating point model. */
431 extern const struct arm_fpu_desc
434 enum arm_fp_model model
;
436 enum vfp_reg_type regs
;
442 /* Which floating point hardware to schedule for. */
443 extern int arm_fpu_attr
;
445 #ifndef TARGET_DEFAULT_FLOAT_ABI
446 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
449 #ifndef ARM_DEFAULT_ABI
450 #define ARM_DEFAULT_ABI ARM_ABI_APCS
453 /* Map each of the micro-architecture variants to their corresponding
454 major architecture revision. */
456 enum base_architecture
484 /* The major revision number of the ARM Architecture implemented by the target. */
485 extern enum base_architecture arm_base_arch
;
487 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
488 extern int arm_arch3m
;
490 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
491 extern int arm_arch4
;
493 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
494 extern int arm_arch4t
;
496 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
497 extern int arm_arch5
;
499 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
500 extern int arm_arch5e
;
502 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
503 extern int arm_arch6
;
505 /* Nonzero if this chip supports the ARM Architecture 6k extensions. */
506 extern int arm_arch6k
;
508 /* Nonzero if instructions present in ARMv6-M can be used. */
509 extern int arm_arch6m
;
511 /* Nonzero if this chip supports the ARM Architecture 7 extensions. */
512 extern int arm_arch7
;
514 /* Nonzero if instructions not present in the 'M' profile can be used. */
515 extern int arm_arch_notm
;
517 /* Nonzero if instructions present in ARMv7E-M can be used. */
518 extern int arm_arch7em
;
520 /* Nonzero if this chip supports the ARM Architecture 8 extensions. */
521 extern int arm_arch8
;
523 /* Nonzero if this chip can benefit from load scheduling. */
524 extern int arm_ld_sched
;
526 /* Nonzero if generating Thumb code, either Thumb-1 or Thumb-2. */
527 extern int thumb_code
;
529 /* Nonzero if generating Thumb-1 code. */
530 extern int thumb1_code
;
532 /* Nonzero if this chip is a StrongARM. */
533 extern int arm_tune_strongarm
;
535 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
536 extern int arm_arch_iwmmxt
;
538 /* Nonzero if this chip supports Intel Wireless MMX2 technology. */
539 extern int arm_arch_iwmmxt2
;
541 /* Nonzero if this chip is an XScale. */
542 extern int arm_arch_xscale
;
544 /* Nonzero if tuning for XScale. */
545 extern int arm_tune_xscale
;
547 /* Nonzero if tuning for stores via the write buffer. */
548 extern int arm_tune_wbuf
;
550 /* Nonzero if tuning for Cortex-A9. */
551 extern int arm_tune_cortex_a9
;
553 /* Nonzero if we should define __THUMB_INTERWORK__ in the
555 XXX This is a bit of a hack, it's intended to help work around
556 problems in GLD which doesn't understand that armv5t code is
557 interworking clean. */
558 extern int arm_cpp_interwork
;
560 /* Nonzero if chip supports Thumb 2. */
561 extern int arm_arch_thumb2
;
563 /* Nonzero if chip supports integer division instruction in ARM mode. */
564 extern int arm_arch_arm_hwdiv
;
566 /* Nonzero if chip supports integer division instruction in Thumb mode. */
567 extern int arm_arch_thumb_hwdiv
;
569 /* Nonzero if we should use Neon to handle 64-bits operations rather
570 than core registers. */
571 extern int prefer_neon_for_64bits
;
573 /* Nonzero if we shouldn't use literal pools. */
574 #ifndef USED_FOR_TARGET
575 extern bool arm_disable_literal_pool
;
578 /* Nonzero if chip supports the ARMv8 CRC instructions. */
579 extern int arm_arch_crc
;
581 #ifndef TARGET_DEFAULT
582 #define TARGET_DEFAULT (MASK_APCS_FRAME)
585 /* Nonzero if PIC code requires explicit qualifiers to generate
586 PLT and GOT relocs rather than the assembler doing so implicitly.
587 Subtargets can override these if required. */
588 #ifndef NEED_GOT_RELOC
589 #define NEED_GOT_RELOC 0
591 #ifndef NEED_PLT_RELOC
592 #define NEED_PLT_RELOC 0
595 #ifndef TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE
596 #define TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 1
599 /* Nonzero if we need to refer to the GOT with a PC-relative
600 offset. In other words, generate
602 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
606 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
608 The default is true, which matches NetBSD. Subtargets can
609 override this if required. */
614 /* Target machine storage Layout. */
617 /* Define this macro if it is advisable to hold scalars in registers
618 in a wider mode than that declared by the program. In such cases,
619 the value is constrained to be within the bounds of the declared
620 type, but kept valid in the wider mode. The signedness of the
621 extension may differ from that of the type. */
623 /* It is far faster to zero extend chars than to sign extend them */
625 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
626 if (GET_MODE_CLASS (MODE) == MODE_INT \
627 && GET_MODE_SIZE (MODE) < 4) \
629 if (MODE == QImode) \
631 else if (MODE == HImode) \
636 /* Define this if most significant bit is lowest numbered
637 in instructions that operate on numbered bit-fields. */
638 #define BITS_BIG_ENDIAN 0
640 /* Define this if most significant byte of a word is the lowest numbered.
641 Most ARM processors are run in little endian mode, so that is the default.
642 If you want to have it run-time selectable, change the definition in a
643 cover file to be TARGET_BIG_ENDIAN. */
644 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
646 /* Define this if most significant word of a multiword number is the lowest
648 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN)
650 #define UNITS_PER_WORD 4
652 /* True if natural alignment is used for doubleword types. */
653 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
655 #define DOUBLEWORD_ALIGNMENT 64
657 #define PARM_BOUNDARY 32
659 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
661 #define PREFERRED_STACK_BOUNDARY \
662 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
664 #define FUNCTION_BOUNDARY ((TARGET_THUMB && optimize_size) ? 16 : 32)
666 /* The lowest bit is used to indicate Thumb-mode functions, so the
667 vbit must go into the delta field of pointers to member
669 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
671 #define EMPTY_FIELD_BOUNDARY 32
673 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
675 #define MALLOC_ABI_ALIGNMENT BIGGEST_ALIGNMENT
677 /* XXX Blah -- this macro is used directly by libobjc. Since it
678 supports no vector modes, cut out the complexity and fall back
679 on BIGGEST_FIELD_ALIGNMENT. */
680 #ifdef IN_TARGET_LIBS
681 #define BIGGEST_FIELD_ALIGNMENT 64
684 /* Make strings word-aligned so strcpy from constants will be faster. */
685 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
687 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
688 ((TREE_CODE (EXP) == STRING_CST \
690 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
691 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
693 /* Align definitions of arrays, unions and structures so that
694 initializations and copies can be made more efficient. This is not
695 ABI-changing, so it only affects places where we can see the
696 definition. Increasing the alignment tends to introduce padding,
697 so don't do this when optimizing for size/conserving stack space. */
698 #define ARM_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \
699 (((COND) && ((ALIGN) < BITS_PER_WORD) \
700 && (TREE_CODE (EXP) == ARRAY_TYPE \
701 || TREE_CODE (EXP) == UNION_TYPE \
702 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
704 /* Align global data. */
705 #define DATA_ALIGNMENT(EXP, ALIGN) \
706 ARM_EXPAND_ALIGNMENT(!optimize_size, EXP, ALIGN)
708 /* Similarly, make sure that objects on the stack are sensibly aligned. */
709 #define LOCAL_ALIGNMENT(EXP, ALIGN) \
710 ARM_EXPAND_ALIGNMENT(!flag_conserve_stack, EXP, ALIGN)
712 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
713 value set in previous versions of this toolchain was 8, which produces more
714 compact structures. The command line option -mstructure_size_boundary=<n>
715 can be used to change this value. For compatibility with the ARM SDK
716 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
717 0020D) page 2-20 says "Structures are aligned on word boundaries".
718 The AAPCS specifies a value of 8. */
719 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
721 /* This is the value used to initialize arm_structure_size_boundary. If a
722 particular arm target wants to change the default value it should change
723 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
724 for an example of this. */
725 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
726 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
729 /* Nonzero if move instructions will actually fail to work
730 when given unaligned data. */
731 #define STRICT_ALIGNMENT 1
733 /* wchar_t is unsigned under the AAPCS. */
735 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
737 #define WCHAR_TYPE_SIZE BITS_PER_WORD
740 /* Sized for fixed-point types. */
742 #define SHORT_FRACT_TYPE_SIZE 8
743 #define FRACT_TYPE_SIZE 16
744 #define LONG_FRACT_TYPE_SIZE 32
745 #define LONG_LONG_FRACT_TYPE_SIZE 64
747 #define SHORT_ACCUM_TYPE_SIZE 16
748 #define ACCUM_TYPE_SIZE 32
749 #define LONG_ACCUM_TYPE_SIZE 64
750 #define LONG_LONG_ACCUM_TYPE_SIZE 64
752 #define MAX_FIXED_MODE_SIZE 64
755 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
759 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int")
762 /* AAPCS requires that structure alignment is affected by bitfields. */
763 #ifndef PCC_BITFIELD_TYPE_MATTERS
764 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
768 /* Standard register usage. */
770 /* Register allocation in ARM Procedure Call Standard
771 (S - saved over call).
773 r0 * argument word/integer result
776 r4-r8 S register variable
777 r9 S (rfp) register variable (real frame pointer)
779 r10 F S (sl) stack limit (used by -mapcs-stack-check)
780 r11 F S (fp) argument pointer
781 r12 (ip) temp workspace
782 r13 F S (sp) lower end of current stack frame
783 r14 (lr) link address/workspace
784 r15 F (pc) program counter
786 cc This is NOT a real register, but is used internally
787 to represent things that use or set the condition
789 sfp This isn't either. It is used during rtl generation
790 since the offset between the frame pointer and the
791 auto's isn't known until after register allocation.
792 afp Nor this, we only need this because of non-local
793 goto. Without it fp appears to be used and the
794 elimination code won't get rid of sfp. It tracks
795 fp exactly at all times.
797 *: See TARGET_CONDITIONAL_REGISTER_USAGE */
799 /* s0-s15 VFP scratch (aka d0-d7).
800 s16-s31 S VFP variable (aka d8-d15).
801 vfpcc Not a real register. Represents the VFP condition
804 /* The stack backtrace structure is as follows:
805 fp points to here: | save code pointer | [fp]
806 | return link value | [fp, #-4]
807 | return sp value | [fp, #-8]
808 | return fp value | [fp, #-12]
809 [| saved r10 value |]
820 r0-r3 are not normally saved in a C function. */
822 /* 1 for registers that have pervasive standard uses
823 and are not available for the register allocator. */
824 #define FIXED_REGISTERS \
846 /* 1 for registers not available across function calls.
847 These must include the FIXED_REGISTERS and also any
848 registers that can be used without being saved.
849 The latter must include the registers where values are returned
850 and the register where structure-value addresses are passed.
851 Aside from that, you can include as many other registers as you like.
852 The CC is not preserved over function calls on the ARM 6, so it is
853 easier to assume this for all. SFP is preserved, since FP is. */
854 #define CALL_USED_REGISTERS \
876 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
877 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
880 /* These are a couple of extensions to the formats accepted
882 %@ prints out ASM_COMMENT_START
883 %r prints out REGISTER_PREFIX reg_names[arg] */
884 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
886 fputs (ASM_COMMENT_START, FILE); \
890 fputs (REGISTER_PREFIX, FILE); \
891 fputs (reg_names [va_arg (ARGS, int)], FILE); \
894 /* Round X up to the nearest word. */
895 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
897 /* Convert fron bytes to ints. */
898 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
900 /* The number of (integer) registers required to hold a quantity of type MODE.
901 Also used for VFP registers. */
902 #define ARM_NUM_REGS(MODE) \
903 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
905 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
906 #define ARM_NUM_REGS2(MODE, TYPE) \
907 ARM_NUM_INTS ((MODE) == BLKmode ? \
908 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
910 /* The number of (integer) argument register available. */
911 #define NUM_ARG_REGS 4
913 /* And similarly for the VFP. */
914 #define NUM_VFP_ARG_REGS 16
916 /* Return the register number of the N'th (integer) argument. */
917 #define ARG_REGISTER(N) (N - 1)
919 /* Specify the registers used for certain standard purposes.
920 The values of these macros are register numbers. */
922 /* The number of the last argument register. */
923 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
925 /* The numbers of the Thumb register ranges. */
926 #define FIRST_LO_REGNUM 0
927 #define LAST_LO_REGNUM 7
928 #define FIRST_HI_REGNUM 8
929 #define LAST_HI_REGNUM 11
931 /* Overridden by config/arm/bpabi.h. */
932 #ifndef ARM_UNWIND_INFO
933 #define ARM_UNWIND_INFO 0
936 /* Use r0 and r1 to pass exception handling information. */
937 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
939 /* The register that holds the return address in exception handlers. */
940 #define ARM_EH_STACKADJ_REGNUM 2
941 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
943 #ifndef ARM_TARGET2_DWARF_FORMAT
944 #define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel
947 /* ttype entries (the only interesting data references used)
948 use TARGET2 relocations. */
949 #define ASM_PREFERRED_EH_DATA_FORMAT(code, data) \
950 (((code) == 0 && (data) == 1 && ARM_UNWIND_INFO) ? ARM_TARGET2_DWARF_FORMAT \
953 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
954 as an invisible last argument (possible since varargs don't exist in
955 Pascal), so the following is not true. */
956 #define STATIC_CHAIN_REGNUM 12
958 /* Define this to be where the real frame pointer is if it is not possible to
959 work out the offset between the frame pointer and the automatic variables
960 until after register allocation has taken place. FRAME_POINTER_REGNUM
961 should point to a special register that we will make sure is eliminated.
963 For the Thumb we have another problem. The TPCS defines the frame pointer
964 as r11, and GCC believes that it is always possible to use the frame pointer
965 as base register for addressing purposes. (See comments in
966 find_reloads_address()). But - the Thumb does not allow high registers,
967 including r11, to be used as base address registers. Hence our problem.
969 The solution used here, and in the old thumb port is to use r7 instead of
970 r11 as the hard frame pointer and to have special code to generate
971 backtrace structures on the stack (if required to do so via a command line
972 option) using r11. This is the only 'user visible' use of r11 as a frame
974 #define ARM_HARD_FRAME_POINTER_REGNUM 11
975 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
977 #define HARD_FRAME_POINTER_REGNUM \
979 ? ARM_HARD_FRAME_POINTER_REGNUM \
980 : THUMB_HARD_FRAME_POINTER_REGNUM)
982 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
983 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
985 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
987 /* Register to use for pushing function arguments. */
988 #define STACK_POINTER_REGNUM SP_REGNUM
990 #define FIRST_IWMMXT_REGNUM (LAST_HI_VFP_REGNUM + 1)
991 #define LAST_IWMMXT_REGNUM (FIRST_IWMMXT_REGNUM + 15)
993 /* Need to sync with WCGR in iwmmxt.md. */
994 #define FIRST_IWMMXT_GR_REGNUM (LAST_IWMMXT_REGNUM + 1)
995 #define LAST_IWMMXT_GR_REGNUM (FIRST_IWMMXT_GR_REGNUM + 3)
997 #define IS_IWMMXT_REGNUM(REGNUM) \
998 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
999 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
1000 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
1002 /* Base register for access to local variables of the function. */
1003 #define FRAME_POINTER_REGNUM 102
1005 /* Base register for access to arguments of the function. */
1006 #define ARG_POINTER_REGNUM 103
1008 #define FIRST_VFP_REGNUM 16
1009 #define D7_VFP_REGNUM (FIRST_VFP_REGNUM + 15)
1010 #define LAST_VFP_REGNUM \
1011 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM)
1013 #define IS_VFP_REGNUM(REGNUM) \
1014 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
1016 /* VFP registers are split into two types: those defined by VFP versions < 3
1017 have D registers overlaid on consecutive pairs of S registers. VFP version 3
1018 defines 16 new D registers (d16-d31) which, for simplicity and correctness
1019 in various parts of the backend, we implement as "fake" single-precision
1020 registers (which would be S32-S63, but cannot be used in that way). The
1021 following macros define these ranges of registers. */
1022 #define LAST_LO_VFP_REGNUM (FIRST_VFP_REGNUM + 31)
1023 #define FIRST_HI_VFP_REGNUM (LAST_LO_VFP_REGNUM + 1)
1024 #define LAST_HI_VFP_REGNUM (FIRST_HI_VFP_REGNUM + 31)
1026 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \
1027 ((REGNUM) <= LAST_LO_VFP_REGNUM)
1029 /* DFmode values are only valid in even register pairs. */
1030 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \
1031 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0)
1033 /* Neon Quad values must start at a multiple of four registers. */
1034 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \
1035 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0)
1037 /* Neon structures of vectors must be in even register pairs and there
1038 must be enough registers available. Because of various patterns
1039 requiring quad registers, we require them to start at a multiple of
1041 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \
1042 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \
1043 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
1045 /* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP. */
1046 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
1047 /* VFP (VFP3) adds 32 (64) + 1 VFPCC. */
1048 #define FIRST_PSEUDO_REGISTER 104
1050 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
1052 /* Value should be nonzero if functions must have frame pointers.
1053 Zero means the frame pointer need not be set up (and parms may be accessed
1054 via the stack pointer) in functions that seem suitable.
1055 If we have to have a frame pointer we might as well make use of it.
1056 APCS says that the frame pointer does not need to be pushed in leaf
1057 functions, or simple tail call functions. */
1059 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1060 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1063 /* Return number of consecutive hard regs needed starting at reg REGNO
1064 to hold something of mode MODE.
1065 This is ordinarily the length in words of a value of mode MODE
1066 but can be less for certain modes in special long registers.
1068 On the ARM core regs are UNITS_PER_WORD bits wide. */
1069 #define HARD_REGNO_NREGS(REGNO, MODE) \
1071 && REGNO > PC_REGNUM \
1072 && REGNO != FRAME_POINTER_REGNUM \
1073 && REGNO != ARG_POINTER_REGNUM) \
1074 && !IS_VFP_REGNUM (REGNO) \
1075 ? 1 : ARM_NUM_REGS (MODE))
1077 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1078 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1079 arm_hard_regno_mode_ok ((REGNO), (MODE))
1081 #define MODES_TIEABLE_P(MODE1, MODE2) arm_modes_tieable_p (MODE1, MODE2)
1083 #define VALID_IWMMXT_REG_MODE(MODE) \
1084 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
1086 /* Modes valid for Neon D registers. */
1087 #define VALID_NEON_DREG_MODE(MODE) \
1088 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
1089 || (MODE) == V4HFmode || (MODE) == V2SFmode || (MODE) == DImode)
1091 /* Modes valid for Neon Q registers. */
1092 #define VALID_NEON_QREG_MODE(MODE) \
1093 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
1094 || (MODE) == V4SFmode || (MODE) == V2DImode)
1096 /* Structure modes valid for Neon registers. */
1097 #define VALID_NEON_STRUCT_MODE(MODE) \
1098 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \
1099 || (MODE) == CImode || (MODE) == XImode)
1101 /* The register numbers in sequence, for passing to arm_gen_load_multiple. */
1102 extern int arm_regs_in_sequence
[];
1104 /* The order in which register should be allocated. It is good to use ip
1105 since no saving is required (though calls clobber it) and it never contains
1106 function parameters. It is quite good to use lr since other calls may
1107 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1108 least likely to contain a function parameter; in addition results are
1110 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7),
1111 then D8-D15. The reason for doing this is to attempt to reduce register
1112 pressure when both single- and double-precision registers are used in a
1115 #define VREG(X) (FIRST_VFP_REGNUM + (X))
1116 #define WREG(X) (FIRST_IWMMXT_REGNUM + (X))
1117 #define WGREG(X) (FIRST_IWMMXT_GR_REGNUM + (X))
1119 #define REG_ALLOC_ORDER \
1121 /* General registers. */ \
1122 3, 2, 1, 0, 12, 14, 4, 5, \
1123 6, 7, 8, 9, 10, 11, \
1124 /* High VFP registers. */ \
1125 VREG(32), VREG(33), VREG(34), VREG(35), \
1126 VREG(36), VREG(37), VREG(38), VREG(39), \
1127 VREG(40), VREG(41), VREG(42), VREG(43), \
1128 VREG(44), VREG(45), VREG(46), VREG(47), \
1129 VREG(48), VREG(49), VREG(50), VREG(51), \
1130 VREG(52), VREG(53), VREG(54), VREG(55), \
1131 VREG(56), VREG(57), VREG(58), VREG(59), \
1132 VREG(60), VREG(61), VREG(62), VREG(63), \
1133 /* VFP argument registers. */ \
1134 VREG(15), VREG(14), VREG(13), VREG(12), \
1135 VREG(11), VREG(10), VREG(9), VREG(8), \
1136 VREG(7), VREG(6), VREG(5), VREG(4), \
1137 VREG(3), VREG(2), VREG(1), VREG(0), \
1138 /* VFP call-saved registers. */ \
1139 VREG(16), VREG(17), VREG(18), VREG(19), \
1140 VREG(20), VREG(21), VREG(22), VREG(23), \
1141 VREG(24), VREG(25), VREG(26), VREG(27), \
1142 VREG(28), VREG(29), VREG(30), VREG(31), \
1143 /* IWMMX registers. */ \
1144 WREG(0), WREG(1), WREG(2), WREG(3), \
1145 WREG(4), WREG(5), WREG(6), WREG(7), \
1146 WREG(8), WREG(9), WREG(10), WREG(11), \
1147 WREG(12), WREG(13), WREG(14), WREG(15), \
1148 WGREG(0), WGREG(1), WGREG(2), WGREG(3), \
1149 /* Registers not for general use. */ \
1150 CC_REGNUM, VFPCC_REGNUM, \
1151 FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \
1152 SP_REGNUM, PC_REGNUM \
1155 /* Use different register alloc ordering for Thumb. */
1156 #define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc ()
1158 /* Tell IRA to use the order we define rather than messing it up with its
1159 own cost calculations. */
1160 #define HONOR_REG_ALLOC_ORDER 1
1162 /* Interrupt functions can only use registers that have already been
1163 saved by the prologue, even if they would normally be
1165 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1166 (! IS_INTERRUPT (cfun->machine->func_type) || \
1167 df_regs_ever_live_p (DST))
1169 /* Register and constant classes. */
1171 /* Register classes. */
1196 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1198 /* Give names of register classes as strings for dump file. */
1199 #define REG_CLASS_NAMES \
1206 "CALLER_SAVE_REGS", \
1222 /* Define which registers fit in which classes.
1223 This is an initializer for a vector of HARD_REG_SET
1224 of length N_REG_CLASSES. */
1225 #define REG_CLASS_CONTENTS \
1227 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1228 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1229 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1230 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1231 { 0x00005F00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1232 { 0x0000100F, 0x00000000, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \
1233 { 0x00005FFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1234 { 0x00007FFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \
1235 { 0xFFFF0000, 0x00000000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \
1236 { 0xFFFF0000, 0x0000FFFF, 0x00000000, 0x00000000 }, /* VFP_LO_REGS */ \
1237 { 0x00000000, 0xFFFF0000, 0x0000FFFF, 0x00000000 }, /* VFP_HI_REGS */ \
1238 { 0xFFFF0000, 0xFFFFFFFF, 0x0000FFFF, 0x00000000 }, /* VFP_REGS */ \
1239 { 0x00000000, 0x00000000, 0xFFFF0000, 0x00000000 }, /* IWMMXT_REGS */ \
1240 { 0x00000000, 0x00000000, 0x00000000, 0x0000000F }, /* IWMMXT_GR_REGS */ \
1241 { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, /* CC_REG */ \
1242 { 0x00000000, 0x00000000, 0x00000000, 0x00000020 }, /* VFPCC_REG */ \
1243 { 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \
1244 { 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \
1245 { 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000000F } /* ALL_REGS */ \
1248 /* Any of the VFP register classes. */
1249 #define IS_VFP_CLASS(X) \
1250 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \
1251 || (X) == VFP_HI_REGS || (X) == VFP_REGS)
1253 /* The same information, inverted:
1254 Return the class number of the smallest class containing
1255 reg number REGNO. This could be a conditional expression
1256 or could index an array. */
1257 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1259 /* In VFPv1, VFP registers could only be accessed in the mode they
1260 were set, so subregs would be invalid there. However, we don't
1261 support VFPv1 at the moment, and the restriction was lifted in
1263 In big-endian mode, modes greater than word size (i.e. DFmode) are stored in
1264 VFP registers in little-endian order. We can't describe that accurately to
1265 GCC, so avoid taking subregs of such values.
1266 The only exception is going from a 128-bit to a 64-bit type. In that case
1267 the data layout happens to be consistent for big-endian, so we explicitly allow
1269 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1270 (TARGET_VFP && TARGET_BIG_END \
1271 && !(GET_MODE_SIZE (FROM) == 16 && GET_MODE_SIZE (TO) == 8) \
1272 && (GET_MODE_SIZE (FROM) > UNITS_PER_WORD \
1273 || GET_MODE_SIZE (TO) > UNITS_PER_WORD) \
1274 && reg_classes_intersect_p (VFP_REGS, (CLASS)))
1276 /* The class value for index registers, and the one for base regs. */
1277 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
1278 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS)
1280 /* For the Thumb the high registers cannot be used as base registers
1281 when addressing quantities in QI or HI mode; if we don't know the
1282 mode, then we must be conservative. */
1283 #define MODE_BASE_REG_CLASS(MODE) \
1285 ? (TARGET_32BIT ? CORE_REGS \
1286 : GET_MODE_SIZE (MODE) >= 4 ? BASE_REGS \
1288 : ((TARGET_ARM || (TARGET_THUMB2 && !optimize_size)) ? CORE_REGS \
1289 : ((MODE) == SImode) ? BASE_REGS \
1292 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1293 instead of BASE_REGS. */
1294 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
1296 /* When this hook returns true for MODE, the compiler allows
1297 registers explicitly used in the rtl to be used as spill registers
1298 but prevents the compiler from extending the lifetime of these
1300 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
1301 arm_small_register_classes_for_mode_p
1303 /* Must leave BASE_REGS reloads alone */
1304 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1305 (lra_in_progress ? NO_REGS \
1306 : ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1307 ? ((true_regnum (X) == -1 ? LO_REGS \
1308 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1312 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1313 (lra_in_progress ? NO_REGS \
1314 : (CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1315 ? ((true_regnum (X) == -1 ? LO_REGS \
1316 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1320 /* Return the register class of a scratch register needed to copy IN into
1321 or out of a register in CLASS in MODE. If it can be done directly,
1322 NO_REGS is returned. */
1323 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1324 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1325 ((TARGET_VFP && TARGET_HARD_FLOAT \
1326 && IS_VFP_CLASS (CLASS)) \
1327 ? coproc_secondary_reload_class (MODE, X, FALSE) \
1328 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \
1329 ? coproc_secondary_reload_class (MODE, X, TRUE) \
1331 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1332 ? GENERAL_REGS : NO_REGS) \
1333 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1335 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1336 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1337 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1338 ((TARGET_VFP && TARGET_HARD_FLOAT \
1339 && IS_VFP_CLASS (CLASS)) \
1340 ? coproc_secondary_reload_class (MODE, X, FALSE) : \
1341 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \
1342 coproc_secondary_reload_class (MODE, X, TRUE) : \
1344 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1345 && CONSTANT_P (X)) \
1347 (((MODE) == HImode && ! arm_arch4 \
1349 || ((REG_P (X) || GET_CODE (X) == SUBREG) \
1350 && true_regnum (X) == -1))) \
1351 ? GENERAL_REGS : NO_REGS) \
1352 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1354 /* Try a machine-dependent way of reloading an illegitimate address
1355 operand. If we find one, push the reload and jump to WIN. This
1356 macro is used in only one place: `find_reloads_address' in reload.c.
1358 For the ARM, we wish to handle large displacements off a base
1359 register by splitting the addend across a MOV and the mem insn.
1360 This can cut the number of reloads needed. */
1361 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1364 if (arm_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND)) \
1369 /* XXX If an HImode FP+large_offset address is converted to an HImode
1370 SP+large_offset address, then reload won't know how to fix it. It sees
1371 only that SP isn't valid for HImode, and so reloads the SP into an index
1372 register, but the resulting address is still invalid because the offset
1373 is too big. We fix it here instead by reloading the entire address. */
1374 /* We could probably achieve better results by defining PROMOTE_MODE to help
1375 cope with the variances between the Thumb's signed and unsigned byte and
1376 halfword load instructions. */
1377 /* ??? This should be safe for thumb2, but we may be able to do better. */
1378 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
1380 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
1388 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1390 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1392 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1394 /* Return the maximum number of consecutive registers
1395 needed to represent mode MODE in a register of class CLASS.
1396 ARM regs are UNITS_PER_WORD bits.
1397 FIXME: Is this true for iWMMX? */
1398 #define CLASS_MAX_NREGS(CLASS, MODE) \
1399 (ARM_NUM_REGS (MODE))
1401 /* If defined, gives a class of registers that cannot be used as the
1402 operand of a SUBREG that changes the mode of the object illegally. */
1404 /* Stack layout; function entry, exit and calling. */
1406 /* Define this if pushing a word on the stack
1407 makes the stack pointer a smaller address. */
1408 #define STACK_GROWS_DOWNWARD 1
1410 /* Define this to nonzero if the nominal address of the stack frame
1411 is at the high-address end of the local variables;
1412 that is, each additional local variable allocated
1413 goes at a more negative offset in the frame. */
1414 #define FRAME_GROWS_DOWNWARD 1
1416 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1417 When present, it is one word in size, and sits at the top of the frame,
1418 between the soft frame pointer and either r7 or r11.
1420 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1421 and only then if some outgoing arguments are passed on the stack. It would
1422 be tempting to also check whether the stack arguments are passed by indirect
1423 calls, but there seems to be no reason in principle why a post-reload pass
1424 couldn't convert a direct call into an indirect one. */
1425 #define CALLER_INTERWORKING_SLOT_SIZE \
1426 (TARGET_CALLER_INTERWORKING \
1427 && crtl->outgoing_args_size != 0 \
1428 ? UNITS_PER_WORD : 0)
1430 /* Offset within stack frame to start allocating local variables at.
1431 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1432 first local allocated. Otherwise, it is the offset to the BEGINNING
1433 of the first local allocated. */
1434 #define STARTING_FRAME_OFFSET 0
1436 /* If we generate an insn to push BYTES bytes,
1437 this says how many the stack pointer really advances by. */
1438 /* The push insns do not do this rounding implicitly.
1439 So don't define this. */
1440 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1442 /* Define this if the maximum size of all the outgoing args is to be
1443 accumulated and pushed during the prologue. The amount can be
1444 found in the variable crtl->outgoing_args_size. */
1445 #define ACCUMULATE_OUTGOING_ARGS 1
1447 /* Offset of first parameter from the argument pointer register value. */
1448 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1450 /* Amount of memory needed for an untyped call to save all possible return
1452 #define APPLY_RESULT_SIZE arm_apply_result_size()
1454 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1455 values must be in memory. On the ARM, they need only do so if larger
1456 than a word, or if they contain elements offset from zero in the struct. */
1457 #define DEFAULT_PCC_STRUCT_RETURN 0
1459 /* These bits describe the different types of function supported
1460 by the ARM backend. They are exclusive. i.e. a function cannot be both a
1461 normal function and an interworked function, for example. Knowing the
1462 type of a function is important for determining its prologue and
1464 Note value 7 is currently unassigned. Also note that the interrupt
1465 function types all have bit 2 set, so that they can be tested for easily.
1466 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1467 machine_function structure is initialized (to zero) func_type will
1468 default to unknown. This will force the first use of arm_current_func_type
1469 to call arm_compute_func_type. */
1470 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1471 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1472 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1473 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1474 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1475 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1477 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1479 /* In addition functions can have several type modifiers,
1480 outlined by these bit masks: */
1481 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1482 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1483 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1484 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1485 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */
1487 /* Some macros to test these flags. */
1488 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1489 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1490 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1491 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1492 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1493 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN)
1496 /* Structure used to hold the function stack frame layout. Offsets are
1497 relative to the stack pointer on function entry. Positive offsets are
1498 in the direction of stack growth.
1499 Only soft_frame is used in thumb mode. */
1501 typedef struct GTY(()) arm_stack_offsets
1503 int saved_args
; /* ARG_POINTER_REGNUM. */
1504 int frame
; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1506 int soft_frame
; /* FRAME_POINTER_REGNUM. */
1507 int locals_base
; /* THUMB_HARD_FRAME_POINTER_REGNUM. */
1508 int outgoing_args
; /* STACK_POINTER_REGNUM. */
1509 unsigned int saved_regs_mask
;
1513 #ifndef GENERATOR_FILE
1514 /* A C structure for machine-specific, per-function data.
1515 This is added to the cfun structure. */
1516 typedef struct GTY(()) machine_function
1518 /* Additional stack adjustment in __builtin_eh_throw. */
1519 rtx eh_epilogue_sp_ofs
;
1520 /* Records if LR has to be saved for far jumps. */
1522 /* Records if ARG_POINTER was ever live. */
1523 int arg_pointer_live
;
1524 /* Records if the save of LR has been eliminated. */
1525 int lr_save_eliminated
;
1526 /* The size of the stack frame. Only valid after reload. */
1527 arm_stack_offsets stack_offsets
;
1528 /* Records the type of the current function. */
1529 unsigned long func_type
;
1530 /* Record if the function has a variable argument list. */
1531 int uses_anonymous_args
;
1532 /* Records if sibcalls are blocked because an argument
1533 register is needed to preserve stack alignment. */
1534 int sibcall_blocked
;
1535 /* The PIC register for this function. This might be a pseudo. */
1537 /* Labels for per-function Thumb call-via stubs. One per potential calling
1538 register. We can never call via LR or PC. We can call via SP if a
1539 trampoline happens to be on the top of the stack. */
1541 /* Set to 1 when a return insn is output, this means that the epilogue
1543 int return_used_this_function
;
1544 /* When outputting Thumb-1 code, record the last insn that provides
1545 information about condition codes, and the comparison operands. */
1549 /* Also record the CC mode that is supported. */
1550 machine_mode thumb1_cc_mode
;
1551 /* Set to 1 after arm_reorg has started. */
1552 int after_arm_reorg
;
1557 /* As in the machine_function, a global set of call-via labels, for code
1558 that is in text_section. */
1559 extern GTY(()) rtx thumb_call_via_label
[14];
1561 /* The number of potential ways of assigning to a co-processor. */
1562 #define ARM_NUM_COPROC_SLOTS 1
1564 /* Enumeration of procedure calling standard variants. We don't really
1565 support all of these yet. */
1568 ARM_PCS_AAPCS
, /* Base standard AAPCS. */
1569 ARM_PCS_AAPCS_VFP
, /* Use VFP registers for floating point values. */
1570 ARM_PCS_AAPCS_IWMMXT
, /* Use iWMMXT registers for vectors. */
1571 /* This must be the last AAPCS variant. */
1572 ARM_PCS_AAPCS_LOCAL
, /* Private call within this compilation unit. */
1573 ARM_PCS_ATPCS
, /* ATPCS. */
1574 ARM_PCS_APCS
, /* APCS (legacy Linux etc). */
1578 /* Default procedure calling standard of current compilation unit. */
1579 extern enum arm_pcs arm_pcs_default
;
1581 /* A C type for declaring a variable that is used as the first argument of
1582 `FUNCTION_ARG' and other related values. */
1585 /* This is the number of registers of arguments scanned so far. */
1587 /* This is the number of iWMMXt register arguments scanned so far. */
1591 /* Which procedure call variant to use for this call. */
1592 enum arm_pcs pcs_variant
;
1594 /* AAPCS related state tracking. */
1595 int aapcs_arg_processed
; /* No need to lay out this argument again. */
1596 int aapcs_cprc_slot
; /* Index of co-processor rules to handle
1597 this argument, or -1 if using core
1600 int aapcs_next_ncrn
;
1601 rtx aapcs_reg
; /* Register assigned to this argument. */
1602 int aapcs_partial
; /* How many bytes are passed in regs (if
1603 split between core regs and stack.
1605 int aapcs_cprc_failed
[ARM_NUM_COPROC_SLOTS
];
1606 int can_split
; /* Argument can be split between core regs
1608 /* Private data for tracking VFP register allocation */
1609 unsigned aapcs_vfp_regs_free
;
1610 unsigned aapcs_vfp_reg_alloc
;
1611 int aapcs_vfp_rcount
;
1612 MACHMODE aapcs_vfp_rmode
;
1615 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1616 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1618 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1619 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1621 /* For AAPCS, padding should never be below the argument. For other ABIs,
1622 * mimic the default. */
1623 #define PAD_VARARGS_DOWN \
1624 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1626 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1627 for a call to a function whose data type is FNTYPE.
1628 For a library call, FNTYPE is 0.
1629 On the ARM, the offset starts at 0. */
1630 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1631 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1633 /* 1 if N is a possible register number for function argument passing.
1634 On the ARM, r0-r3 are used to pass args. */
1635 #define FUNCTION_ARG_REGNO_P(REGNO) \
1636 (IN_RANGE ((REGNO), 0, 3) \
1637 || (TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT \
1638 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \
1639 || (TARGET_IWMMXT_ABI \
1640 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1643 /* If your target environment doesn't prefix user functions with an
1644 underscore, you may wish to re-define this to prevent any conflicts. */
1645 #ifndef ARM_MCOUNT_NAME
1646 #define ARM_MCOUNT_NAME "*mcount"
1649 /* Call the function profiler with a given profile label. The Acorn
1650 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1651 On the ARM the full profile code will look like:
1660 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1661 will output the .text section.
1663 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1664 ``prof'' doesn't seem to mind about this!
1666 Note - this version of the code is designed to work in both ARM and
1668 #ifndef ARM_FUNCTION_PROFILER
1669 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1674 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1675 IP_REGNUM, LR_REGNUM); \
1676 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1677 fputc ('\n', STREAM); \
1678 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1679 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1680 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1684 #ifdef THUMB_FUNCTION_PROFILER
1685 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1687 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1689 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1691 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1692 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1695 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1696 the stack pointer does not matter. The value is tested only in
1697 functions that have frame pointers.
1698 No definition is equivalent to always zero.
1700 On the ARM, the function epilogue recovers the stack pointer from the
1702 #define EXIT_IGNORE_STACK 1
1704 #define EPILOGUE_USES(REGNO) (epilogue_completed && (REGNO) == LR_REGNUM)
1706 /* Determine if the epilogue should be output as RTL.
1707 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1708 #define USE_RETURN_INSN(ISCOND) \
1709 (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0)
1711 /* Definitions for register eliminations.
1713 This is an array of structures. Each structure initializes one pair
1714 of eliminable registers. The "from" register number is given first,
1715 followed by "to". Eliminations of the same "from" register are listed
1716 in order of preference.
1718 We have two registers that can be eliminated on the ARM. First, the
1719 arg pointer register can often be eliminated in favor of the stack
1720 pointer register. Secondly, the pseudo frame pointer register can always
1721 be eliminated; it is replaced with either the stack or the real frame
1722 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1723 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1725 #define ELIMINABLE_REGS \
1726 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1727 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1728 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1729 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1730 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1731 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1732 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1734 /* Define the offset between two registers, one to be eliminated, and the
1735 other its replacement, at the start of a routine. */
1736 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1738 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1740 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1742 /* Special case handling of the location of arguments passed on the stack. */
1743 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1745 /* Initialize data used by insn expanders. This is called from insn_emit,
1746 once for every function before code is generated. */
1747 #define INIT_EXPANDERS arm_init_expanders ()
1749 /* Length in units of the trampoline for entering a nested function. */
1750 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20)
1752 /* Alignment required for a trampoline in bits. */
1753 #define TRAMPOLINE_ALIGNMENT 32
1755 /* Addressing modes, and classification of registers for them. */
1756 #define HAVE_POST_INCREMENT 1
1757 #define HAVE_PRE_INCREMENT TARGET_32BIT
1758 #define HAVE_POST_DECREMENT TARGET_32BIT
1759 #define HAVE_PRE_DECREMENT TARGET_32BIT
1760 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT
1761 #define HAVE_POST_MODIFY_DISP TARGET_32BIT
1762 #define HAVE_PRE_MODIFY_REG TARGET_32BIT
1763 #define HAVE_POST_MODIFY_REG TARGET_32BIT
1765 enum arm_auto_incmodes
1773 #define ARM_AUTOINC_VALID_FOR_MODE_P(mode, code) \
1774 (TARGET_32BIT && arm_autoinc_modes_ok_p (mode, code))
1775 #define USE_LOAD_POST_INCREMENT(mode) \
1776 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_INC)
1777 #define USE_LOAD_PRE_INCREMENT(mode) \
1778 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_INC)
1779 #define USE_LOAD_POST_DECREMENT(mode) \
1780 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_DEC)
1781 #define USE_LOAD_PRE_DECREMENT(mode) \
1782 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_DEC)
1784 #define USE_STORE_PRE_DECREMENT(mode) USE_LOAD_PRE_DECREMENT(mode)
1785 #define USE_STORE_PRE_INCREMENT(mode) USE_LOAD_PRE_INCREMENT(mode)
1786 #define USE_STORE_POST_DECREMENT(mode) USE_LOAD_POST_DECREMENT(mode)
1787 #define USE_STORE_POST_INCREMENT(mode) USE_LOAD_POST_INCREMENT(mode)
1789 /* Macros to check register numbers against specific register classes. */
1791 /* These assume that REGNO is a hard or pseudo reg number.
1792 They give nonzero only if REGNO is a hard reg of the suitable class
1793 or a pseudo reg currently allocated to a suitable hard reg.
1794 Since they use reg_renumber, they are safe only once reg_renumber
1795 has been allocated, which happens in reginfo.c during register
1797 #define TEST_REGNO(R, TEST, VALUE) \
1798 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1800 /* Don't allow the pc to be used. */
1801 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1802 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1803 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1804 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1806 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1807 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1808 || (GET_MODE_SIZE (MODE) >= 4 \
1809 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1811 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1813 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1814 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1816 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1817 For Thumb, we can not use SP + reg, so reject SP. */
1818 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1819 REGNO_MODE_OK_FOR_BASE_P (X, QImode)
1821 /* For ARM code, we don't care about the mode, but for Thumb, the index
1822 must be suitable for use in a QImode load. */
1823 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1824 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \
1825 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))
1827 /* Maximum number of registers that can appear in a valid memory address.
1828 Shifts in addresses can't be by a register. */
1829 #define MAX_REGS_PER_ADDRESS 2
1831 /* Recognize any constant value that is a valid address. */
1832 /* XXX We can address any constant, eventually... */
1833 /* ??? Should the TARGET_ARM here also apply to thumb2? */
1834 #define CONSTANT_ADDRESS_P(X) \
1835 (GET_CODE (X) == SYMBOL_REF \
1836 && (CONSTANT_POOL_ADDRESS_P (X) \
1837 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1839 /* True if SYMBOL + OFFSET constants must refer to something within
1840 SYMBOL's section. */
1841 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0
1843 /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */
1844 #ifndef TARGET_DEFAULT_WORD_RELOCATIONS
1845 #define TARGET_DEFAULT_WORD_RELOCATIONS 0
1848 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1849 #define SUBTARGET_NAME_ENCODING_LENGTHS
1852 /* This is a C fragment for the inside of a switch statement.
1853 Each case label should return the number of characters to
1854 be stripped from the start of a function's name, if that
1855 name starts with the indicated character. */
1856 #define ARM_NAME_ENCODING_LENGTHS \
1857 case '*': return 1; \
1858 SUBTARGET_NAME_ENCODING_LENGTHS
1860 /* This is how to output a reference to a user-level label named NAME.
1861 `assemble_name' uses this. */
1862 #undef ASM_OUTPUT_LABELREF
1863 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1864 arm_asm_output_labelref (FILE, NAME)
1866 /* Output IT instructions for conditionally executed Thumb-2 instructions. */
1867 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
1868 if (TARGET_THUMB2) \
1869 thumb2_asm_output_opcode (STREAM);
1871 /* The EABI specifies that constructors should go in .init_array.
1872 Other targets use .ctors for compatibility. */
1873 #ifndef ARM_EABI_CTORS_SECTION_OP
1874 #define ARM_EABI_CTORS_SECTION_OP \
1875 "\t.section\t.init_array,\"aw\",%init_array"
1877 #ifndef ARM_EABI_DTORS_SECTION_OP
1878 #define ARM_EABI_DTORS_SECTION_OP \
1879 "\t.section\t.fini_array,\"aw\",%fini_array"
1881 #define ARM_CTORS_SECTION_OP \
1882 "\t.section\t.ctors,\"aw\",%progbits"
1883 #define ARM_DTORS_SECTION_OP \
1884 "\t.section\t.dtors,\"aw\",%progbits"
1886 /* Define CTORS_SECTION_ASM_OP. */
1887 #undef CTORS_SECTION_ASM_OP
1888 #undef DTORS_SECTION_ASM_OP
1890 # define CTORS_SECTION_ASM_OP \
1891 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
1892 # define DTORS_SECTION_ASM_OP \
1893 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
1894 #else /* !defined (IN_LIBGCC2) */
1895 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
1896 so we cannot use the definition above. */
1897 # ifdef __ARM_EABI__
1898 /* The .ctors section is not part of the EABI, so we do not define
1899 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
1900 from trying to use it. We do define it when doing normal
1901 compilation, as .init_array can be used instead of .ctors. */
1902 /* There is no need to emit begin or end markers when using
1903 init_array; the dynamic linker will compute the size of the
1904 array itself based on special symbols created by the static
1905 linker. However, we do need to arrange to set up
1906 exception-handling here. */
1907 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
1908 # define CTOR_LIST_END /* empty */
1909 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
1910 # define DTOR_LIST_END /* empty */
1911 # else /* !defined (__ARM_EABI__) */
1912 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
1913 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
1914 # endif /* !defined (__ARM_EABI__) */
1915 #endif /* !defined (IN_LIBCC2) */
1917 /* True if the operating system can merge entities with vague linkage
1918 (e.g., symbols in COMDAT group) during dynamic linking. */
1919 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
1920 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
1923 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
1925 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1926 and check its validity for a certain class.
1927 We have two alternate definitions for each of them.
1928 The usual definition accepts all pseudo regs; the other rejects
1929 them unless they have been allocated suitable hard regs.
1930 The symbol REG_OK_STRICT causes the latter definition to be used.
1931 Thumb-2 has the same restrictions as arm. */
1932 #ifndef REG_OK_STRICT
1934 #define ARM_REG_OK_FOR_BASE_P(X) \
1935 (REGNO (X) <= LAST_ARM_REGNUM \
1936 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1937 || REGNO (X) == FRAME_POINTER_REGNUM \
1938 || REGNO (X) == ARG_POINTER_REGNUM)
1940 #define ARM_REG_OK_FOR_INDEX_P(X) \
1941 ((REGNO (X) <= LAST_ARM_REGNUM \
1942 && REGNO (X) != STACK_POINTER_REGNUM) \
1943 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1944 || REGNO (X) == FRAME_POINTER_REGNUM \
1945 || REGNO (X) == ARG_POINTER_REGNUM)
1947 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1948 (REGNO (X) <= LAST_LO_REGNUM \
1949 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1950 || (GET_MODE_SIZE (MODE) >= 4 \
1951 && (REGNO (X) == STACK_POINTER_REGNUM \
1952 || (X) == hard_frame_pointer_rtx \
1953 || (X) == arg_pointer_rtx)))
1955 #define REG_STRICT_P 0
1957 #else /* REG_OK_STRICT */
1959 #define ARM_REG_OK_FOR_BASE_P(X) \
1960 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
1962 #define ARM_REG_OK_FOR_INDEX_P(X) \
1963 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X))
1965 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1966 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
1968 #define REG_STRICT_P 1
1970 #endif /* REG_OK_STRICT */
1972 /* Now define some helpers in terms of the above. */
1974 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
1976 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \
1977 : ARM_REG_OK_FOR_BASE_P (X))
1979 /* For 16-bit Thumb, a valid index register is anything that can be used in
1980 a byte load instruction. */
1981 #define THUMB1_REG_OK_FOR_INDEX_P(X) \
1982 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode)
1984 /* Nonzero if X is a hard reg that can be used as an index
1985 or if it is a pseudo reg. On the Thumb, the stack pointer
1987 #define REG_OK_FOR_INDEX_P(X) \
1989 ? THUMB1_REG_OK_FOR_INDEX_P (X) \
1990 : ARM_REG_OK_FOR_INDEX_P (X))
1992 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1993 For Thumb, we can not use SP + reg, so reject SP. */
1994 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1995 REG_OK_FOR_INDEX_P (X)
1997 #define ARM_BASE_REGISTER_RTX_P(X) \
1998 (REG_P (X) && ARM_REG_OK_FOR_BASE_P (X))
2000 #define ARM_INDEX_REGISTER_RTX_P(X) \
2001 (REG_P (X) && ARM_REG_OK_FOR_INDEX_P (X))
2003 /* Specify the machine mode that this machine uses
2004 for the index in the tablejump instruction. */
2005 #define CASE_VECTOR_MODE Pmode
2007 #define CASE_VECTOR_PC_RELATIVE (TARGET_THUMB2 \
2009 && (optimize_size || flag_pic)))
2011 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \
2013 ? (min >= 0 && max < 512 \
2014 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \
2015 : min >= -256 && max < 256 \
2016 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \
2017 : min >= 0 && max < 8192 \
2018 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \
2019 : min >= -4096 && max < 4096 \
2020 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \
2022 : ((min < 0 || max >= 0x20000 || !TARGET_THUMB2) ? SImode \
2023 : (max >= 0x200) ? HImode \
2026 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2027 unsigned is probably best, but may break some code. */
2028 #ifndef DEFAULT_SIGNED_CHAR
2029 #define DEFAULT_SIGNED_CHAR 0
2032 /* Max number of bytes we can move from memory to memory
2033 in one reasonably fast instruction. */
2037 #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2)
2039 /* Define if operations between registers always perform the operation
2040 on the full register even if a narrower mode is specified. */
2041 #define WORD_REGISTER_OPERATIONS
2043 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2044 will either zero-extend or sign-extend. The value of this macro should
2045 be the code that says which one of the two operations is implicitly
2046 done, UNKNOWN if none. */
2047 #define LOAD_EXTEND_OP(MODE) \
2048 (TARGET_THUMB ? ZERO_EXTEND : \
2049 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2050 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
2052 /* Nonzero if access to memory by bytes is slow and undesirable. */
2053 #define SLOW_BYTE_ACCESS 0
2055 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2057 /* Immediate shift counts are truncated by the output routines (or was it
2058 the assembler?). Shift counts in a register are truncated by ARM. Note
2059 that the native compiler puts too large (> 32) immediate shift counts
2060 into a register and shifts by the register, letting the ARM decide what
2061 to do instead of doing that itself. */
2062 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2063 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2064 On the arm, Y in a register is used modulo 256 for the shift. Only for
2065 rotates is modulo 32 used. */
2066 /* #define SHIFT_COUNT_TRUNCATED 1 */
2068 /* All integers have the same format so truncation is easy. */
2069 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2071 /* Calling from registers is a massive pain. */
2072 #define NO_FUNCTION_CSE 1
2074 /* The machine modes of pointers and functions */
2075 #define Pmode SImode
2076 #define FUNCTION_MODE Pmode
2078 #define ARM_FRAME_RTX(X) \
2079 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2080 || (X) == arg_pointer_rtx)
2082 /* Try to generate sequences that don't involve branches, we can then use
2083 conditional instructions. */
2084 #define BRANCH_COST(speed_p, predictable_p) \
2085 (current_tune->branch_cost (speed_p, predictable_p))
2087 /* False if short circuit operation is preferred. */
2088 #define LOGICAL_OP_NON_SHORT_CIRCUIT \
2090 ? (TARGET_THUMB ? false : true) \
2091 : (current_tune->logical_op_non_short_circuit[TARGET_ARM]))
2094 /* Position Independent Code. */
2095 /* We decide which register to use based on the compilation options and
2096 the assembler in use; this is more general than the APCS restriction of
2097 using sb (r9) all the time. */
2098 extern unsigned arm_pic_register
;
2100 /* The register number of the register used to address a table of static
2101 data addresses in memory. */
2102 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2104 /* We can't directly access anything that contains a symbol,
2105 nor can we indirect via the constant pool. One exception is
2106 UNSPEC_TLS, which is always PIC. */
2107 #define LEGITIMATE_PIC_OPERAND_P(X) \
2108 (!(symbol_mentioned_p (X) \
2109 || label_mentioned_p (X) \
2110 || (GET_CODE (X) == SYMBOL_REF \
2111 && CONSTANT_POOL_ADDRESS_P (X) \
2112 && (symbol_mentioned_p (get_pool_constant (X)) \
2113 || label_mentioned_p (get_pool_constant (X))))) \
2114 || tls_mentioned_p (X))
2116 /* We need to know when we are making a constant pool; this determines
2117 whether data needs to be in the GOT or can be referenced via a GOT
2119 extern int making_const_table
;
2121 /* Handle pragmas for compatibility with Intel's compilers. */
2122 /* Also abuse this to register additional C specific EABI attributes. */
2123 #define REGISTER_TARGET_PRAGMAS() do { \
2124 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2125 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2126 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2127 arm_lang_object_attributes_init(); \
2130 /* Condition code information. */
2131 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2132 return the mode to be used for the comparison. */
2134 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2136 #define REVERSIBLE_CC_MODE(MODE) 1
2138 #define REVERSE_CONDITION(CODE,MODE) \
2139 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2140 ? reverse_condition_maybe_unordered (code) \
2141 : reverse_condition (code))
2143 /* The arm5 clz instruction returns 32. */
2144 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2145 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2147 #define CC_STATUS_INIT \
2148 do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0)
2151 #define ASM_APP_OFF (TARGET_ARM ? "" : "\t.thumb\n")
2153 /* Output a push or a pop instruction (only used when profiling).
2154 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know
2155 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and
2156 that r7 isn't used by the function profiler, so we can use it as a
2157 scratch reg. WARNING: This isn't safe in the general case! It may be
2158 sensitive to future changes in final.c:profile_function. */
2159 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2163 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2164 STACK_POINTER_REGNUM, REGNO); \
2165 else if (TARGET_THUMB1 \
2166 && (REGNO) == STATIC_CHAIN_REGNUM) \
2168 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \
2169 asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\
2170 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \
2173 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2177 /* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */
2178 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2182 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2183 STACK_POINTER_REGNUM, REGNO); \
2184 else if (TARGET_THUMB1 \
2185 && (REGNO) == STATIC_CHAIN_REGNUM) \
2187 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \
2188 asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\
2189 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \
2192 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2195 #define ADDR_VEC_ALIGN(JUMPTABLE) \
2196 ((TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) ? 2 : 0)
2198 /* Alignment for case labels comes from ADDR_VEC_ALIGN; avoid the
2199 default alignment from elfos.h. */
2200 #undef ASM_OUTPUT_BEFORE_CASE_LABEL
2201 #define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE) /* Empty. */
2203 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) \
2204 (GET_CODE (PATTERN (prev_active_insn (LABEL))) == ADDR_DIFF_VEC \
2207 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2212 if (is_called_in_ARM_mode (DECL) \
2213 || (TARGET_THUMB1 && !TARGET_THUMB1_ONLY \
2214 && cfun->is_thunk)) \
2215 fprintf (STREAM, "\t.code 32\n") ; \
2216 else if (TARGET_THUMB1) \
2217 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \
2219 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \
2221 if (TARGET_POKE_FUNCTION_NAME) \
2222 arm_poke_function_name (STREAM, (const char *) NAME); \
2226 /* For aliases of functions we use .thumb_set instead. */
2227 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2230 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2231 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2233 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2235 fprintf (FILE, "\t.thumb_set "); \
2236 assemble_name (FILE, LABEL1); \
2237 fprintf (FILE, ","); \
2238 assemble_name (FILE, LABEL2); \
2239 fprintf (FILE, "\n"); \
2242 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2246 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2247 /* To support -falign-* switches we need to use .p2align so
2248 that alignment directives in code sections will be padded
2249 with no-op instructions, rather than zeroes. */
2250 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2253 if ((MAX_SKIP) == 0) \
2254 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2256 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2257 (int) (LOG), (int) (MAX_SKIP)); \
2261 /* Add two bytes to the length of conditionally executed Thumb-2
2262 instructions for the IT instruction. */
2263 #define ADJUST_INSN_LENGTH(insn, length) \
2264 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \
2267 /* Only perform branch elimination (by making instructions conditional) if
2268 we're optimizing. For Thumb-2 check if any IT instructions need
2270 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2271 if (TARGET_ARM && optimize) \
2272 arm_final_prescan_insn (INSN); \
2273 else if (TARGET_THUMB2) \
2274 thumb2_final_prescan_insn (INSN); \
2275 else if (TARGET_THUMB1) \
2276 thumb1_final_prescan_insn (INSN)
2278 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2279 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2280 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2281 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2282 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2283 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2286 /* A C expression whose value is RTL representing the value of the return
2287 address for the frame COUNT steps up from the current frame. */
2289 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2290 arm_return_addr (COUNT, FRAME)
2292 /* Mask of the bits in the PC that contain the real return address
2293 when running in 26-bit mode. */
2294 #define RETURN_ADDR_MASK26 (0x03fffffc)
2296 /* Pick up the return address upon entry to a procedure. Used for
2297 dwarf2 unwind information. This also enables the table driven
2299 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2300 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2302 /* Used to mask out junk bits from the return address, such as
2303 processor state, interrupt status, condition codes and the like. */
2304 #define MASK_RETURN_ADDR \
2305 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2306 in 26 bit mode, the condition codes must be masked out of the \
2307 return address. This does not apply to ARM6 and later processors \
2308 when running in 32 bit mode. */ \
2309 ((arm_arch4 || TARGET_THUMB) \
2310 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2311 : arm_gen_return_addr_mask ())
2314 /* Do not emit .note.GNU-stack by default. */
2315 #ifndef NEED_INDICATE_EXEC_STACK
2316 #define NEED_INDICATE_EXEC_STACK 0
2319 #define TARGET_ARM_ARCH \
2322 #define TARGET_ARM_V6M (!arm_arch_notm && !arm_arch_thumb2)
2323 #define TARGET_ARM_V7M (!arm_arch_notm && arm_arch_thumb2)
2325 /* The highest Thumb instruction set version supported by the chip. */
2326 #define TARGET_ARM_ARCH_ISA_THUMB \
2327 (arm_arch_thumb2 ? 2 \
2328 : ((TARGET_ARM_ARCH >= 5 || arm_arch4t) ? 1 : 0))
2330 /* Expands to an upper-case char of the target's architectural
2332 #define TARGET_ARM_ARCH_PROFILE \
2336 ? (strlen (arm_arch_name) >=3 \
2337 ? (arm_arch_name[strlen (arm_arch_name) - 3]) \
2341 /* Bit-field indicating what size LDREX/STREX loads/stores are available.
2342 Bit 0 for bytes, up to bit 3 for double-words. */
2343 #define TARGET_ARM_FEATURE_LDREX \
2344 ((TARGET_HAVE_LDREX ? 4 : 0) \
2345 | (TARGET_HAVE_LDREXBH ? 3 : 0) \
2346 | (TARGET_HAVE_LDREXD ? 8 : 0))
2348 /* Set as a bit mask indicating the available widths of hardware floating
2349 point types. Where bit 1 indicates 16-bit support, bit 2 indicates
2350 32-bit support, bit 3 indicates 64-bit support. */
2351 #define TARGET_ARM_FP \
2352 (TARGET_VFP_SINGLE ? 4 \
2353 : (TARGET_VFP_DOUBLE ? (TARGET_FP16 ? 14 : 12) : 0))
2356 /* Set as a bit mask indicating the available widths of floating point
2357 types for hardware NEON floating point. This is the same as
2358 TARGET_ARM_FP without the 64-bit bit set. */
2360 #define TARGET_NEON_FP \
2361 (TARGET_ARM_FP & (0xff ^ 0x08))
2364 /* The maximum number of parallel loads or stores we support in an ldm/stm
2366 #define MAX_LDM_STM_OPS 4
2368 #define BIG_LITTLE_SPEC \
2369 " %{mcpu=*:-mcpu=%:rewrite_mcpu(%{mcpu=*:%*})}"
2371 extern const char *arm_rewrite_mcpu (int argc
, const char **argv
);
2372 #define BIG_LITTLE_CPU_SPEC_FUNCTIONS \
2373 { "rewrite_mcpu", arm_rewrite_mcpu },
2375 #define ASM_CPU_SPEC \
2376 " %{mcpu=generic-*:-march=%*;" \
2377 " :%{march=*:-march=%*}}" \
2380 /* -mcpu=native handling only makes sense with compiler running on
2382 #if defined(__arm__)
2383 extern const char *host_detect_local_cpu (int argc
, const char **argv
);
2384 # define EXTRA_SPEC_FUNCTIONS \
2385 { "local_cpu_detect", host_detect_local_cpu }, \
2386 BIG_LITTLE_CPU_SPEC_FUNCTIONS
2388 # define MCPU_MTUNE_NATIVE_SPECS \
2389 " %{march=native:%<march=native %:local_cpu_detect(arch)}" \
2390 " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \
2391 " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
2393 # define MCPU_MTUNE_NATIVE_SPECS ""
2394 # define EXTRA_SPEC_FUNCTIONS BIG_LITTLE_CPU_SPEC_FUNCTIONS
2397 #define DRIVER_SELF_SPECS MCPU_MTUNE_NATIVE_SPECS
2398 #define TARGET_SUPPORTS_WIDE_INT 1
2399 #endif /* ! GCC_ARM_H */