]> git.ipfire.org Git - thirdparty/gcc.git/blob - gcc/config/arm/arm.h
projects / thirdparty / gcc.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Turn UNITS_PER_SIMD_WORD into a target hook.
[thirdparty/gcc.git] / gcc / config / arm / arm.h
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
6 and Martin Simmons (@harleqn.co.uk).
7 More major hacks by Richard Earnshaw (rearnsha@arm.com)
8 Minor hacks by Nick Clifton (nickc@cygnus.com)
9
10 This file is part of GCC.
11
12 GCC is free software; you can redistribute it and/or modify it
13 under the terms of the GNU General Public License as published
14 by the Free Software Foundation; either version 3, or (at your
15 option) any later version.
16
17 GCC is distributed in the hope that it will be useful, but WITHOUT
18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
19 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
25
26 #ifndef GCC_ARM_H
27 #define GCC_ARM_H
28
29 /* We can't use enum machine_mode inside a generator file because it
30 hasn't been created yet; we shouldn't be using any code that
31 needs the real definition though, so this ought to be safe. */
32 #ifdef GENERATOR_FILE
33 #define MACHMODE int
34 #else
35 #include "insn-modes.h"
36 #define MACHMODE enum machine_mode
37 #endif
38
39 #include "config/vxworks-dummy.h"
40
41 /* The architecture define. */
42 extern char arm_arch_name[];
43
44 /* Target CPU builtins. */
45 #define TARGET_CPU_CPP_BUILTINS() \
46 do \
47 { \
48 /* Define __arm__ even when in thumb mode, for \
49 consistency with armcc. */ \
50 builtin_define ("__arm__"); \
51 builtin_define ("__APCS_32__"); \
52 if (TARGET_THUMB) \
53 builtin_define ("__thumb__"); \
54 if (TARGET_THUMB2) \
55 builtin_define ("__thumb2__"); \
56 \
57 if (TARGET_BIG_END) \
58 { \
59 builtin_define ("__ARMEB__"); \
60 if (TARGET_THUMB) \
61 builtin_define ("__THUMBEB__"); \
62 if (TARGET_LITTLE_WORDS) \
63 builtin_define ("__ARMWEL__"); \
64 } \
65 else \
66 { \
67 builtin_define ("__ARMEL__"); \
68 if (TARGET_THUMB) \
69 builtin_define ("__THUMBEL__"); \
70 } \
71 \
72 if (TARGET_SOFT_FLOAT) \
73 builtin_define ("__SOFTFP__"); \
74 \
75 if (TARGET_VFP) \
76 builtin_define ("__VFP_FP__"); \
77 \
78 if (TARGET_NEON) \
79 builtin_define ("__ARM_NEON__"); \
80 \
81 /* Add a define for interworking. \
82 Needed when building libgcc.a. */ \
83 if (arm_cpp_interwork) \
84 builtin_define ("__THUMB_INTERWORK__"); \
85 \
86 builtin_assert ("cpu=arm"); \
87 builtin_assert ("machine=arm"); \
88 \
89 builtin_define (arm_arch_name); \
90 if (arm_arch_cirrus) \
91 builtin_define ("__MAVERICK__"); \
92 if (arm_arch_xscale) \
93 builtin_define ("__XSCALE__"); \
94 if (arm_arch_iwmmxt) \
95 builtin_define ("__IWMMXT__"); \
96 if (TARGET_AAPCS_BASED) \
97 { \
98 if (arm_pcs_default == ARM_PCS_AAPCS_VFP) \
99 builtin_define ("__ARM_PCS_VFP"); \
100 else if (arm_pcs_default == ARM_PCS_AAPCS) \
101 builtin_define ("__ARM_PCS"); \
102 builtin_define ("__ARM_EABI__"); \
103 } \
104 } while (0)
105
106 /* The various ARM cores. */
107 enum processor_type
108 {
109 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
110 IDENT,
111 #include "arm-cores.def"
112 #undef ARM_CORE
113 /* Used to indicate that no processor has been specified. */
114 arm_none
115 };
116
117 enum target_cpus
118 {
119 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
120 TARGET_CPU_##IDENT,
121 #include "arm-cores.def"
122 #undef ARM_CORE
123 TARGET_CPU_generic
124 };
125
126 /* The processor for which instructions should be scheduled. */
127 extern enum processor_type arm_tune;
128
129 enum arm_sync_generator_tag
130 {
131 arm_sync_generator_omn,
132 arm_sync_generator_omrn
133 };
134
135 /* Wrapper to pass around a polymorphic pointer to a sync instruction
136 generator and. */
137 struct arm_sync_generator
138 {
139 enum arm_sync_generator_tag op;
140 union
141 {
142 rtx (* omn) (rtx, rtx, rtx);
143 rtx (* omrn) (rtx, rtx, rtx, rtx);
144 } u;
145 };
146
147 typedef enum arm_cond_code
148 {
149 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
150 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
151 }
152 arm_cc;
153
154 extern arm_cc arm_current_cc;
155
156 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
157
158 extern int arm_target_label;
159 extern int arm_ccfsm_state;
160 extern GTY(()) rtx arm_target_insn;
161 /* The label of the current constant pool. */
162 extern rtx pool_vector_label;
163 /* Set to 1 when a return insn is output, this means that the epilogue
164 is not needed. */
165 extern int return_used_this_function;
166 /* Callback to output language specific object attributes. */
167 extern void (*arm_lang_output_object_attributes_hook)(void);
168 \f
169 /* Just in case configure has failed to define anything. */
170 #ifndef TARGET_CPU_DEFAULT
171 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
172 #endif
173
174
175 #undef CPP_SPEC
176 #define CPP_SPEC "%(subtarget_cpp_spec) \
177 %{msoft-float:%{mhard-float: \
178 %e-msoft-float and -mhard_float may not be used together}} \
179 %{mbig-endian:%{mlittle-endian: \
180 %e-mbig-endian and -mlittle-endian may not be used together}}"
181
182 #ifndef CC1_SPEC
183 #define CC1_SPEC ""
184 #endif
185
186 /* This macro defines names of additional specifications to put in the specs
187 that can be used in various specifications like CC1_SPEC. Its definition
188 is an initializer with a subgrouping for each command option.
189
190 Each subgrouping contains a string constant, that defines the
191 specification name, and a string constant that used by the GCC driver
192 program.
193
194 Do not define this macro if it does not need to do anything. */
195 #define EXTRA_SPECS \
196 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
197 SUBTARGET_EXTRA_SPECS
198
199 #ifndef SUBTARGET_EXTRA_SPECS
200 #define SUBTARGET_EXTRA_SPECS
201 #endif
202
203 #ifndef SUBTARGET_CPP_SPEC
204 #define SUBTARGET_CPP_SPEC ""
205 #endif
206 \f
207 /* Run-time Target Specification. */
208 #ifndef TARGET_VERSION
209 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
210 #endif
211
212 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
213 /* Use hardware floating point instructions. */
214 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
215 /* Use hardware floating point calling convention. */
216 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
217 #define TARGET_FPA (arm_fpu_desc->model == ARM_FP_MODEL_FPA)
218 #define TARGET_MAVERICK (arm_fpu_desc->model == ARM_FP_MODEL_MAVERICK)
219 #define TARGET_VFP (arm_fpu_desc->model == ARM_FP_MODEL_VFP)
220 #define TARGET_IWMMXT (arm_arch_iwmmxt)
221 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT)
222 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT)
223 #define TARGET_ARM (! TARGET_THUMB)
224 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
225 #define TARGET_BACKTRACE (leaf_function_p () \
226 ? TARGET_TPCS_LEAF_FRAME \
227 : TARGET_TPCS_FRAME)
228 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
229 #define TARGET_AAPCS_BASED \
230 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
231
232 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
233 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
234
235 /* Only 16-bit thumb code. */
236 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2)
237 /* Arm or Thumb-2 32-bit code. */
238 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2)
239 /* 32-bit Thumb-2 code. */
240 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2)
241 /* Thumb-1 only. */
242 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm)
243 /* FPA emulator without LFM. */
244 #define TARGET_FPA_EMU2 (TARGET_FPA && arm_fpu_desc->rev == 2)
245
246 /* The following two macros concern the ability to execute coprocessor
247 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently
248 only ever tested when we know we are generating for VFP hardware; we need
249 to be more careful with TARGET_NEON as noted below. */
250
251 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */
252 #define TARGET_VFPD32 (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_D32)
253
254 /* FPU supports VFPv3 instructions. */
255 #define TARGET_VFP3 (TARGET_VFP && arm_fpu_desc->rev >= 3)
256
257 /* FPU only supports VFP single-precision instructions. */
258 #define TARGET_VFP_SINGLE (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_SINGLE)
259
260 /* FPU supports VFP double-precision instructions. */
261 #define TARGET_VFP_DOUBLE (TARGET_VFP && arm_fpu_desc->regs != VFP_REG_SINGLE)
262
263 /* FPU supports half-precision floating-point with NEON element load/store. */
264 #define TARGET_NEON_FP16 \
265 (TARGET_VFP && arm_fpu_desc->neon && arm_fpu_desc->fp16)
266
267 /* FPU supports VFP half-precision floating-point. */
268 #define TARGET_FP16 (TARGET_VFP && arm_fpu_desc->fp16)
269
270 /* FPU supports Neon instructions. The setting of this macro gets
271 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT
272 and TARGET_HARD_FLOAT to ensure that NEON instructions are
273 available. */
274 #define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \
275 && TARGET_VFP && arm_fpu_desc->neon)
276
277 /* "DSP" multiply instructions, eg. SMULxy. */
278 #define TARGET_DSP_MULTIPLY \
279 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7em))
280 /* Integer SIMD instructions, and extend-accumulate instructions. */
281 #define TARGET_INT_SIMD \
282 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em))
283
284 /* Should MOVW/MOVT be used in preference to a constant pool. */
285 #define TARGET_USE_MOVT (arm_arch_thumb2 && !optimize_size)
286
287 /* We could use unified syntax for arm mode, but for now we just use it
288 for Thumb-2. */
289 #define TARGET_UNIFIED_ASM TARGET_THUMB2
290
291 /* Nonzero if this chip provides the DMB instruction. */
292 #define TARGET_HAVE_DMB (arm_arch7)
293
294 /* Nonzero if this chip implements a memory barrier via CP15. */
295 #define TARGET_HAVE_DMB_MCR (arm_arch6k && ! TARGET_HAVE_DMB)
296
297 /* Nonzero if this chip implements a memory barrier instruction. */
298 #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR)
299
300 /* Nonzero if this chip supports ldrex and strex */
301 #define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7)
302
303 /* Nonzero if this chip supports ldrex{bhd} and strex{bhd}. */
304 #define TARGET_HAVE_LDREXBHD ((arm_arch6k && TARGET_ARM) || arm_arch7)
305
306 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
307 then TARGET_AAPCS_BASED must be true -- but the converse does not
308 hold. TARGET_BPABI implies the use of the BPABI runtime library,
309 etc., in addition to just the AAPCS calling conventions. */
310 #ifndef TARGET_BPABI
311 #define TARGET_BPABI false
312 #endif
313
314 /* Support for a compile-time default CPU, et cetera. The rules are:
315 --with-arch is ignored if -march or -mcpu are specified.
316 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
317 by --with-arch.
318 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
319 by -march).
320 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
321 specified.
322 --with-fpu is ignored if -mfpu is specified.
323 --with-abi is ignored is -mabi is specified. */
324 #define OPTION_DEFAULT_SPECS \
325 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
326 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
327 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
328 {"float", \
329 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
330 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
331 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \
332 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"},
333
334 /* Which floating point model to use. */
335 enum arm_fp_model
336 {
337 ARM_FP_MODEL_UNKNOWN,
338 /* FPA model (Hardware or software). */
339 ARM_FP_MODEL_FPA,
340 /* Cirrus Maverick floating point model. */
341 ARM_FP_MODEL_MAVERICK,
342 /* VFP floating point model. */
343 ARM_FP_MODEL_VFP
344 };
345
346 enum vfp_reg_type
347 {
348 VFP_NONE = 0,
349 VFP_REG_D16,
350 VFP_REG_D32,
351 VFP_REG_SINGLE
352 };
353
354 extern const struct arm_fpu_desc
355 {
356 const char *name;
357 enum arm_fp_model model;
358 int rev;
359 enum vfp_reg_type regs;
360 int neon;
361 int fp16;
362 } *arm_fpu_desc;
363
364 /* Which floating point hardware to schedule for. */
365 extern int arm_fpu_attr;
366
367 enum float_abi_type
368 {
369 ARM_FLOAT_ABI_SOFT,
370 ARM_FLOAT_ABI_SOFTFP,
371 ARM_FLOAT_ABI_HARD
372 };
373
374 extern enum float_abi_type arm_float_abi;
375
376 #ifndef TARGET_DEFAULT_FLOAT_ABI
377 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
378 #endif
379
380 /* Which __fp16 format to use.
381 The enumeration values correspond to the numbering for the
382 Tag_ABI_FP_16bit_format attribute.
383 */
384 enum arm_fp16_format_type
385 {
386 ARM_FP16_FORMAT_NONE = 0,
387 ARM_FP16_FORMAT_IEEE = 1,
388 ARM_FP16_FORMAT_ALTERNATIVE = 2
389 };
390
391 extern enum arm_fp16_format_type arm_fp16_format;
392 #define LARGEST_EXPONENT_IS_NORMAL(bits) \
393 ((bits) == 16 && arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE)
394
395 /* Which ABI to use. */
396 enum arm_abi_type
397 {
398 ARM_ABI_APCS,
399 ARM_ABI_ATPCS,
400 ARM_ABI_AAPCS,
401 ARM_ABI_IWMMXT,
402 ARM_ABI_AAPCS_LINUX
403 };
404
405 extern enum arm_abi_type arm_abi;
406
407 #ifndef ARM_DEFAULT_ABI
408 #define ARM_DEFAULT_ABI ARM_ABI_APCS
409 #endif
410
411 /* Which thread pointer access sequence to use. */
412 enum arm_tp_type {
413 TP_AUTO,
414 TP_SOFT,
415 TP_CP15
416 };
417
418 extern enum arm_tp_type target_thread_pointer;
419
420 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
421 extern int arm_arch3m;
422
423 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
424 extern int arm_arch4;
425
426 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
427 extern int arm_arch4t;
428
429 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
430 extern int arm_arch5;
431
432 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
433 extern int arm_arch5e;
434
435 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
436 extern int arm_arch6;
437
438 /* Nonzero if this chip supports the ARM Architecture 6k extensions. */
439 extern int arm_arch6k;
440
441 /* Nonzero if this chip supports the ARM Architecture 7 extensions. */
442 extern int arm_arch7;
443
444 /* Nonzero if instructions not present in the 'M' profile can be used. */
445 extern int arm_arch_notm;
446
447 /* Nonzero if instructions present in ARMv7E-M can be used. */
448 extern int arm_arch7em;
449
450 /* Nonzero if this chip can benefit from load scheduling. */
451 extern int arm_ld_sched;
452
453 /* Nonzero if generating Thumb code, either Thumb-1 or Thumb-2. */
454 extern int thumb_code;
455
456 /* Nonzero if generating Thumb-1 code. */
457 extern int thumb1_code;
458
459 /* Nonzero if this chip is a StrongARM. */
460 extern int arm_tune_strongarm;
461
462 /* Nonzero if this chip is a Cirrus variant. */
463 extern int arm_arch_cirrus;
464
465 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
466 extern int arm_arch_iwmmxt;
467
468 /* Nonzero if this chip is an XScale. */
469 extern int arm_arch_xscale;
470
471 /* Nonzero if tuning for XScale. */
472 extern int arm_tune_xscale;
473
474 /* Nonzero if tuning for stores via the write buffer. */
475 extern int arm_tune_wbuf;
476
477 /* Nonzero if tuning for Cortex-A9. */
478 extern int arm_tune_cortex_a9;
479
480 /* Nonzero if we should define __THUMB_INTERWORK__ in the
481 preprocessor.
482 XXX This is a bit of a hack, it's intended to help work around
483 problems in GLD which doesn't understand that armv5t code is
484 interworking clean. */
485 extern int arm_cpp_interwork;
486
487 /* Nonzero if chip supports Thumb 2. */
488 extern int arm_arch_thumb2;
489
490 /* Nonzero if chip supports integer division instruction. */
491 extern int arm_arch_hwdiv;
492
493 #ifndef TARGET_DEFAULT
494 #define TARGET_DEFAULT (MASK_APCS_FRAME)
495 #endif
496
497 /* The frame pointer register used in gcc has nothing to do with debugging;
498 that is controlled by the APCS-FRAME option. */
499 #define CAN_DEBUG_WITHOUT_FP
500
501 #define OVERRIDE_OPTIONS arm_override_options ()
502
503 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
504 arm_optimization_options ((LEVEL), (SIZE))
505
506 /* Nonzero if PIC code requires explicit qualifiers to generate
507 PLT and GOT relocs rather than the assembler doing so implicitly.
508 Subtargets can override these if required. */
509 #ifndef NEED_GOT_RELOC
510 #define NEED_GOT_RELOC 0
511 #endif
512 #ifndef NEED_PLT_RELOC
513 #define NEED_PLT_RELOC 0
514 #endif
515
516 /* Nonzero if we need to refer to the GOT with a PC-relative
517 offset. In other words, generate
518
519 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
520
521 rather than
522
523 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
524
525 The default is true, which matches NetBSD. Subtargets can
526 override this if required. */
527 #ifndef GOT_PCREL
528 #define GOT_PCREL 1
529 #endif
530 \f
531 /* Target machine storage Layout. */
532
533
534 /* Define this macro if it is advisable to hold scalars in registers
535 in a wider mode than that declared by the program. In such cases,
536 the value is constrained to be within the bounds of the declared
537 type, but kept valid in the wider mode. The signedness of the
538 extension may differ from that of the type. */
539
540 /* It is far faster to zero extend chars than to sign extend them */
541
542 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
543 if (GET_MODE_CLASS (MODE) == MODE_INT \
544 && GET_MODE_SIZE (MODE) < 4) \
545 { \
546 if (MODE == QImode) \
547 UNSIGNEDP = 1; \
548 else if (MODE == HImode) \
549 UNSIGNEDP = 1; \
550 (MODE) = SImode; \
551 }
552
553 /* Define this if most significant bit is lowest numbered
554 in instructions that operate on numbered bit-fields. */
555 #define BITS_BIG_ENDIAN 0
556
557 /* Define this if most significant byte of a word is the lowest numbered.
558 Most ARM processors are run in little endian mode, so that is the default.
559 If you want to have it run-time selectable, change the definition in a
560 cover file to be TARGET_BIG_ENDIAN. */
561 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
562
563 /* Define this if most significant word of a multiword number is the lowest
564 numbered.
565 This is always false, even when in big-endian mode. */
566 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
567
568 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
569 on processor pre-defineds when compiling libgcc2.c. */
570 #if defined(__ARMEB__) && !defined(__ARMWEL__)
571 #define LIBGCC2_WORDS_BIG_ENDIAN 1
572 #else
573 #define LIBGCC2_WORDS_BIG_ENDIAN 0
574 #endif
575
576 /* Define this if most significant word of doubles is the lowest numbered.
577 The rules are different based on whether or not we use FPA-format,
578 VFP-format or some other floating point co-processor's format doubles. */
579 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
580
581 #define UNITS_PER_WORD 4
582
583 /* True if natural alignment is used for doubleword types. */
584 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
585
586 #define DOUBLEWORD_ALIGNMENT 64
587
588 #define PARM_BOUNDARY 32
589
590 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
591
592 #define PREFERRED_STACK_BOUNDARY \
593 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
594
595 #define FUNCTION_BOUNDARY ((TARGET_THUMB && optimize_size) ? 16 : 32)
596
597 /* The lowest bit is used to indicate Thumb-mode functions, so the
598 vbit must go into the delta field of pointers to member
599 functions. */
600 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
601
602 #define EMPTY_FIELD_BOUNDARY 32
603
604 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
605
606 /* XXX Blah -- this macro is used directly by libobjc. Since it
607 supports no vector modes, cut out the complexity and fall back
608 on BIGGEST_FIELD_ALIGNMENT. */
609 #ifdef IN_TARGET_LIBS
610 #define BIGGEST_FIELD_ALIGNMENT 64
611 #endif
612
613 /* Make strings word-aligned so strcpy from constants will be faster. */
614 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
615
616 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
617 ((TREE_CODE (EXP) == STRING_CST \
618 && !optimize_size \
619 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
620 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
621
622 /* Align definitions of arrays, unions and structures so that
623 initializations and copies can be made more efficient. This is not
624 ABI-changing, so it only affects places where we can see the
625 definition. */
626 #define DATA_ALIGNMENT(EXP, ALIGN) \
627 ((((ALIGN) < BITS_PER_WORD) \
628 && (TREE_CODE (EXP) == ARRAY_TYPE \
629 || TREE_CODE (EXP) == UNION_TYPE \
630 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
631
632 /* Similarly, make sure that objects on the stack are sensibly aligned. */
633 #define LOCAL_ALIGNMENT(EXP, ALIGN) DATA_ALIGNMENT(EXP, ALIGN)
634
635 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
636 value set in previous versions of this toolchain was 8, which produces more
637 compact structures. The command line option -mstructure_size_boundary=<n>
638 can be used to change this value. For compatibility with the ARM SDK
639 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
640 0020D) page 2-20 says "Structures are aligned on word boundaries".
641 The AAPCS specifies a value of 8. */
642 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
643 extern int arm_structure_size_boundary;
644
645 /* This is the value used to initialize arm_structure_size_boundary. If a
646 particular arm target wants to change the default value it should change
647 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
648 for an example of this. */
649 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
650 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
651 #endif
652
653 /* Nonzero if move instructions will actually fail to work
654 when given unaligned data. */
655 #define STRICT_ALIGNMENT 1
656
657 /* wchar_t is unsigned under the AAPCS. */
658 #ifndef WCHAR_TYPE
659 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
660
661 #define WCHAR_TYPE_SIZE BITS_PER_WORD
662 #endif
663
664 #ifndef SIZE_TYPE
665 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
666 #endif
667
668 #ifndef PTRDIFF_TYPE
669 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int")
670 #endif
671
672 /* AAPCS requires that structure alignment is affected by bitfields. */
673 #ifndef PCC_BITFIELD_TYPE_MATTERS
674 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
675 #endif
676
677 \f
678 /* Standard register usage. */
679
680 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
681 (S - saved over call).
682
683 r0 * argument word/integer result
684 r1-r3 argument word
685
686 r4-r8 S register variable
687 r9 S (rfp) register variable (real frame pointer)
688
689 r10 F S (sl) stack limit (used by -mapcs-stack-check)
690 r11 F S (fp) argument pointer
691 r12 (ip) temp workspace
692 r13 F S (sp) lower end of current stack frame
693 r14 (lr) link address/workspace
694 r15 F (pc) program counter
695
696 f0 floating point result
697 f1-f3 floating point scratch
698
699 f4-f7 S floating point variable
700
701 cc This is NOT a real register, but is used internally
702 to represent things that use or set the condition
703 codes.
704 sfp This isn't either. It is used during rtl generation
705 since the offset between the frame pointer and the
706 auto's isn't known until after register allocation.
707 afp Nor this, we only need this because of non-local
708 goto. Without it fp appears to be used and the
709 elimination code won't get rid of sfp. It tracks
710 fp exactly at all times.
711
712 *: See CONDITIONAL_REGISTER_USAGE */
713
714 /*
715 mvf0 Cirrus floating point result
716 mvf1-mvf3 Cirrus floating point scratch
717 mvf4-mvf15 S Cirrus floating point variable. */
718
719 /* s0-s15 VFP scratch (aka d0-d7).
720 s16-s31 S VFP variable (aka d8-d15).
721 vfpcc Not a real register. Represents the VFP condition
722 code flags. */
723
724 /* The stack backtrace structure is as follows:
725 fp points to here: | save code pointer | [fp]
726 | return link value | [fp, #-4]
727 | return sp value | [fp, #-8]
728 | return fp value | [fp, #-12]
729 [| saved r10 value |]
730 [| saved r9 value |]
731 [| saved r8 value |]
732 [| saved r7 value |]
733 [| saved r6 value |]
734 [| saved r5 value |]
735 [| saved r4 value |]
736 [| saved r3 value |]
737 [| saved r2 value |]
738 [| saved r1 value |]
739 [| saved r0 value |]
740 [| saved f7 value |] three words
741 [| saved f6 value |] three words
742 [| saved f5 value |] three words
743 [| saved f4 value |] three words
744 r0-r3 are not normally saved in a C function. */
745
746 /* 1 for registers that have pervasive standard uses
747 and are not available for the register allocator. */
748 #define FIXED_REGISTERS \
749 { \
750 0,0,0,0,0,0,0,0, \
751 0,0,0,0,0,1,0,1, \
752 0,0,0,0,0,0,0,0, \
753 1,1,1, \
754 1,1,1,1,1,1,1,1, \
755 1,1,1,1,1,1,1,1, \
756 1,1,1,1,1,1,1,1, \
757 1,1,1,1,1,1,1,1, \
758 1,1,1,1, \
759 1,1,1,1,1,1,1,1, \
760 1,1,1,1,1,1,1,1, \
761 1,1,1,1,1,1,1,1, \
762 1,1,1,1,1,1,1,1, \
763 1,1,1,1,1,1,1,1, \
764 1,1,1,1,1,1,1,1, \
765 1,1,1,1,1,1,1,1, \
766 1,1,1,1,1,1,1,1, \
767 1 \
768 }
769
770 /* 1 for registers not available across function calls.
771 These must include the FIXED_REGISTERS and also any
772 registers that can be used without being saved.
773 The latter must include the registers where values are returned
774 and the register where structure-value addresses are passed.
775 Aside from that, you can include as many other registers as you like.
776 The CC is not preserved over function calls on the ARM 6, so it is
777 easier to assume this for all. SFP is preserved, since FP is. */
778 #define CALL_USED_REGISTERS \
779 { \
780 1,1,1,1,0,0,0,0, \
781 0,0,0,0,1,1,1,1, \
782 1,1,1,1,0,0,0,0, \
783 1,1,1, \
784 1,1,1,1,1,1,1,1, \
785 1,1,1,1,1,1,1,1, \
786 1,1,1,1,1,1,1,1, \
787 1,1,1,1,1,1,1,1, \
788 1,1,1,1, \
789 1,1,1,1,1,1,1,1, \
790 1,1,1,1,1,1,1,1, \
791 1,1,1,1,1,1,1,1, \
792 1,1,1,1,1,1,1,1, \
793 1,1,1,1,1,1,1,1, \
794 1,1,1,1,1,1,1,1, \
795 1,1,1,1,1,1,1,1, \
796 1,1,1,1,1,1,1,1, \
797 1 \
798 }
799
800 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
801 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
802 #endif
803
804 #define CONDITIONAL_REGISTER_USAGE \
805 { \
806 int regno; \
807 \
808 if (TARGET_SOFT_FLOAT || TARGET_THUMB1 || !TARGET_FPA) \
809 { \
810 for (regno = FIRST_FPA_REGNUM; \
811 regno <= LAST_FPA_REGNUM; ++regno) \
812 fixed_regs[regno] = call_used_regs[regno] = 1; \
813 } \
814 \
815 if (TARGET_THUMB1 && optimize_size) \
816 { \
817 /* When optimizing for size on Thumb-1, it's better not \
818 to use the HI regs, because of the overhead of \
819 stacking them. */ \
820 for (regno = FIRST_HI_REGNUM; \
821 regno <= LAST_HI_REGNUM; ++regno) \
822 fixed_regs[regno] = call_used_regs[regno] = 1; \
823 } \
824 \
825 /* The link register can be clobbered by any branch insn, \
826 but we have no way to track that at present, so mark \
827 it as unavailable. */ \
828 if (TARGET_THUMB1) \
829 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
830 \
831 if (TARGET_32BIT && TARGET_HARD_FLOAT) \
832 { \
833 if (TARGET_MAVERICK) \
834 { \
835 for (regno = FIRST_FPA_REGNUM; \
836 regno <= LAST_FPA_REGNUM; ++ regno) \
837 fixed_regs[regno] = call_used_regs[regno] = 1; \
838 for (regno = FIRST_CIRRUS_FP_REGNUM; \
839 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
840 { \
841 fixed_regs[regno] = 0; \
842 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
843 } \
844 } \
845 if (TARGET_VFP) \
846 { \
847 /* VFPv3 registers are disabled when earlier VFP \
848 versions are selected due to the definition of \
849 LAST_VFP_REGNUM. */ \
850 for (regno = FIRST_VFP_REGNUM; \
851 regno <= LAST_VFP_REGNUM; ++ regno) \
852 { \
853 fixed_regs[regno] = 0; \
854 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16 \
855 || regno >= FIRST_VFP_REGNUM + 32; \
856 } \
857 } \
858 } \
859 \
860 if (TARGET_REALLY_IWMMXT) \
861 { \
862 regno = FIRST_IWMMXT_GR_REGNUM; \
863 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
864 and wCG1 as call-preserved registers. The 2002/11/21 \
865 revision changed this so that all wCG registers are \
866 scratch registers. */ \
867 for (regno = FIRST_IWMMXT_GR_REGNUM; \
868 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
869 fixed_regs[regno] = 0; \
870 /* The XScale ABI has wR0 - wR9 as scratch registers, \
871 the rest as call-preserved registers. */ \
872 for (regno = FIRST_IWMMXT_REGNUM; \
873 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
874 { \
875 fixed_regs[regno] = 0; \
876 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
877 } \
878 } \
879 \
880 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
881 { \
882 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
883 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
884 } \
885 else if (TARGET_APCS_STACK) \
886 { \
887 fixed_regs[10] = 1; \
888 call_used_regs[10] = 1; \
889 } \
890 /* -mcaller-super-interworking reserves r11 for calls to \
891 _interwork_r11_call_via_rN(). Making the register global \
892 is an easy way of ensuring that it remains valid for all \
893 calls. */ \
894 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \
895 || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \
896 { \
897 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
898 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
899 if (TARGET_CALLER_INTERWORKING) \
900 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
901 } \
902 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
903 }
904
905 /* These are a couple of extensions to the formats accepted
906 by asm_fprintf:
907 %@ prints out ASM_COMMENT_START
908 %r prints out REGISTER_PREFIX reg_names[arg] */
909 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
910 case '@': \
911 fputs (ASM_COMMENT_START, FILE); \
912 break; \
913 \
914 case 'r': \
915 fputs (REGISTER_PREFIX, FILE); \
916 fputs (reg_names [va_arg (ARGS, int)], FILE); \
917 break;
918
919 /* Round X up to the nearest word. */
920 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
921
922 /* Convert fron bytes to ints. */
923 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
924
925 /* The number of (integer) registers required to hold a quantity of type MODE.
926 Also used for VFP registers. */
927 #define ARM_NUM_REGS(MODE) \
928 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
929
930 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
931 #define ARM_NUM_REGS2(MODE, TYPE) \
932 ARM_NUM_INTS ((MODE) == BLKmode ? \
933 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
934
935 /* The number of (integer) argument register available. */
936 #define NUM_ARG_REGS 4
937
938 /* And similarly for the VFP. */
939 #define NUM_VFP_ARG_REGS 16
940
941 /* Return the register number of the N'th (integer) argument. */
942 #define ARG_REGISTER(N) (N - 1)
943
944 /* Specify the registers used for certain standard purposes.
945 The values of these macros are register numbers. */
946
947 /* The number of the last argument register. */
948 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
949
950 /* The numbers of the Thumb register ranges. */
951 #define FIRST_LO_REGNUM 0
952 #define LAST_LO_REGNUM 7
953 #define FIRST_HI_REGNUM 8
954 #define LAST_HI_REGNUM 11
955
956 #ifndef TARGET_UNWIND_INFO
957 /* We use sjlj exceptions for backwards compatibility. */
958 #define MUST_USE_SJLJ_EXCEPTIONS 1
959 #endif
960
961 /* We can generate DWARF2 Unwind info, even though we don't use it. */
962 #define DWARF2_UNWIND_INFO 1
963
964 /* Use r0 and r1 to pass exception handling information. */
965 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
966
967 /* The register that holds the return address in exception handlers. */
968 #define ARM_EH_STACKADJ_REGNUM 2
969 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
970
971 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
972 as an invisible last argument (possible since varargs don't exist in
973 Pascal), so the following is not true. */
974 #define STATIC_CHAIN_REGNUM 12
975
976 /* Define this to be where the real frame pointer is if it is not possible to
977 work out the offset between the frame pointer and the automatic variables
978 until after register allocation has taken place. FRAME_POINTER_REGNUM
979 should point to a special register that we will make sure is eliminated.
980
981 For the Thumb we have another problem. The TPCS defines the frame pointer
982 as r11, and GCC believes that it is always possible to use the frame pointer
983 as base register for addressing purposes. (See comments in
984 find_reloads_address()). But - the Thumb does not allow high registers,
985 including r11, to be used as base address registers. Hence our problem.
986
987 The solution used here, and in the old thumb port is to use r7 instead of
988 r11 as the hard frame pointer and to have special code to generate
989 backtrace structures on the stack (if required to do so via a command line
990 option) using r11. This is the only 'user visible' use of r11 as a frame
991 pointer. */
992 #define ARM_HARD_FRAME_POINTER_REGNUM 11
993 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
994
995 #define HARD_FRAME_POINTER_REGNUM \
996 (TARGET_ARM \
997 ? ARM_HARD_FRAME_POINTER_REGNUM \
998 : THUMB_HARD_FRAME_POINTER_REGNUM)
999
1000 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
1001
1002 /* Register to use for pushing function arguments. */
1003 #define STACK_POINTER_REGNUM SP_REGNUM
1004
1005 /* ARM floating pointer registers. */
1006 #define FIRST_FPA_REGNUM 16
1007 #define LAST_FPA_REGNUM 23
1008 #define IS_FPA_REGNUM(REGNUM) \
1009 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
1010
1011 #define FIRST_IWMMXT_GR_REGNUM 43
1012 #define LAST_IWMMXT_GR_REGNUM 46
1013 #define FIRST_IWMMXT_REGNUM 47
1014 #define LAST_IWMMXT_REGNUM 62
1015 #define IS_IWMMXT_REGNUM(REGNUM) \
1016 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
1017 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
1018 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
1019
1020 /* Base register for access to local variables of the function. */
1021 #define FRAME_POINTER_REGNUM 25
1022
1023 /* Base register for access to arguments of the function. */
1024 #define ARG_POINTER_REGNUM 26
1025
1026 #define FIRST_CIRRUS_FP_REGNUM 27
1027 #define LAST_CIRRUS_FP_REGNUM 42
1028 #define IS_CIRRUS_REGNUM(REGNUM) \
1029 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
1030
1031 #define FIRST_VFP_REGNUM 63
1032 #define D7_VFP_REGNUM 78 /* Registers 77 and 78 == VFP reg D7. */
1033 #define LAST_VFP_REGNUM \
1034 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM)
1035
1036 #define IS_VFP_REGNUM(REGNUM) \
1037 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
1038
1039 /* VFP registers are split into two types: those defined by VFP versions < 3
1040 have D registers overlaid on consecutive pairs of S registers. VFP version 3
1041 defines 16 new D registers (d16-d31) which, for simplicity and correctness
1042 in various parts of the backend, we implement as "fake" single-precision
1043 registers (which would be S32-S63, but cannot be used in that way). The
1044 following macros define these ranges of registers. */
1045 #define LAST_LO_VFP_REGNUM 94
1046 #define FIRST_HI_VFP_REGNUM 95
1047 #define LAST_HI_VFP_REGNUM 126
1048
1049 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \
1050 ((REGNUM) <= LAST_LO_VFP_REGNUM)
1051
1052 /* DFmode values are only valid in even register pairs. */
1053 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \
1054 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0)
1055
1056 /* Neon Quad values must start at a multiple of four registers. */
1057 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \
1058 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0)
1059
1060 /* Neon structures of vectors must be in even register pairs and there
1061 must be enough registers available. Because of various patterns
1062 requiring quad registers, we require them to start at a multiple of
1063 four. */
1064 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \
1065 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \
1066 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
1067
1068 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
1069 /* + 16 Cirrus registers take us up to 43. */
1070 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
1071 /* VFP (VFP3) adds 32 (64) + 1 more. */
1072 #define FIRST_PSEUDO_REGISTER 128
1073
1074 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
1075
1076 /* Value should be nonzero if functions must have frame pointers.
1077 Zero means the frame pointer need not be set up (and parms may be accessed
1078 via the stack pointer) in functions that seem suitable.
1079 If we have to have a frame pointer we might as well make use of it.
1080 APCS says that the frame pointer does not need to be pushed in leaf
1081 functions, or simple tail call functions. */
1082
1083 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1084 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1085 #endif
1086
1087 /* Return number of consecutive hard regs needed starting at reg REGNO
1088 to hold something of mode MODE.
1089 This is ordinarily the length in words of a value of mode MODE
1090 but can be less for certain modes in special long registers.
1091
1092 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
1093 mode. */
1094 #define HARD_REGNO_NREGS(REGNO, MODE) \
1095 ((TARGET_32BIT \
1096 && REGNO >= FIRST_FPA_REGNUM \
1097 && REGNO != FRAME_POINTER_REGNUM \
1098 && REGNO != ARG_POINTER_REGNUM) \
1099 && !IS_VFP_REGNUM (REGNO) \
1100 ? 1 : ARM_NUM_REGS (MODE))
1101
1102 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1103 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1104 arm_hard_regno_mode_ok ((REGNO), (MODE))
1105
1106 /* Value is 1 if it is a good idea to tie two pseudo registers
1107 when one has mode MODE1 and one has mode MODE2.
1108 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1109 for any hard reg, then this must be 0 for correct output. */
1110 #define MODES_TIEABLE_P(MODE1, MODE2) \
1111 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1112
1113 #define VALID_IWMMXT_REG_MODE(MODE) \
1114 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
1115
1116 /* Modes valid for Neon D registers. */
1117 #define VALID_NEON_DREG_MODE(MODE) \
1118 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
1119 || (MODE) == V2SFmode || (MODE) == DImode)
1120
1121 /* Modes valid for Neon Q registers. */
1122 #define VALID_NEON_QREG_MODE(MODE) \
1123 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
1124 || (MODE) == V4SFmode || (MODE) == V2DImode)
1125
1126 /* Structure modes valid for Neon registers. */
1127 #define VALID_NEON_STRUCT_MODE(MODE) \
1128 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \
1129 || (MODE) == CImode || (MODE) == XImode)
1130
1131 /* The register numbers in sequence, for passing to arm_gen_load_multiple. */
1132 extern int arm_regs_in_sequence[];
1133
1134 /* The order in which register should be allocated. It is good to use ip
1135 since no saving is required (though calls clobber it) and it never contains
1136 function parameters. It is quite good to use lr since other calls may
1137 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1138 least likely to contain a function parameter; in addition results are
1139 returned in r0.
1140 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7),
1141 then D8-D15. The reason for doing this is to attempt to reduce register
1142 pressure when both single- and double-precision registers are used in a
1143 function. */
1144
1145 #define REG_ALLOC_ORDER \
1146 { \
1147 3, 2, 1, 0, 12, 14, 4, 5, \
1148 6, 7, 8, 10, 9, 11, 13, 15, \
1149 16, 17, 18, 19, 20, 21, 22, 23, \
1150 27, 28, 29, 30, 31, 32, 33, 34, \
1151 35, 36, 37, 38, 39, 40, 41, 42, \
1152 43, 44, 45, 46, 47, 48, 49, 50, \
1153 51, 52, 53, 54, 55, 56, 57, 58, \
1154 59, 60, 61, 62, \
1155 24, 25, 26, \
1156 95, 96, 97, 98, 99, 100, 101, 102, \
1157 103, 104, 105, 106, 107, 108, 109, 110, \
1158 111, 112, 113, 114, 115, 116, 117, 118, \
1159 119, 120, 121, 122, 123, 124, 125, 126, \
1160 78, 77, 76, 75, 74, 73, 72, 71, \
1161 70, 69, 68, 67, 66, 65, 64, 63, \
1162 79, 80, 81, 82, 83, 84, 85, 86, \
1163 87, 88, 89, 90, 91, 92, 93, 94, \
1164 127 \
1165 }
1166
1167 /* Use different register alloc ordering for Thumb. */
1168 #define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc ()
1169
1170 /* Tell IRA to use the order we define rather than messing it up with its
1171 own cost calculations. */
1172 #define HONOR_REG_ALLOC_ORDER
1173
1174 /* Interrupt functions can only use registers that have already been
1175 saved by the prologue, even if they would normally be
1176 call-clobbered. */
1177 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1178 (! IS_INTERRUPT (cfun->machine->func_type) || \
1179 df_regs_ever_live_p (DST))
1180 \f
1181 /* Register and constant classes. */
1182
1183 /* Register classes: used to be simple, just all ARM regs or all FPA regs
1184 Now that the Thumb is involved it has become more complicated. */
1185 enum reg_class
1186 {
1187 NO_REGS,
1188 FPA_REGS,
1189 CIRRUS_REGS,
1190 VFP_D0_D7_REGS,
1191 VFP_LO_REGS,
1192 VFP_HI_REGS,
1193 VFP_REGS,
1194 IWMMXT_GR_REGS,
1195 IWMMXT_REGS,
1196 LO_REGS,
1197 STACK_REG,
1198 BASE_REGS,
1199 HI_REGS,
1200 CC_REG,
1201 VFPCC_REG,
1202 GENERAL_REGS,
1203 CORE_REGS,
1204 ALL_REGS,
1205 LIM_REG_CLASSES
1206 };
1207
1208 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1209
1210 /* Give names of register classes as strings for dump file. */
1211 #define REG_CLASS_NAMES \
1212 { \
1213 "NO_REGS", \
1214 "FPA_REGS", \
1215 "CIRRUS_REGS", \
1216 "VFP_D0_D7_REGS", \
1217 "VFP_LO_REGS", \
1218 "VFP_HI_REGS", \
1219 "VFP_REGS", \
1220 "IWMMXT_GR_REGS", \
1221 "IWMMXT_REGS", \
1222 "LO_REGS", \
1223 "STACK_REG", \
1224 "BASE_REGS", \
1225 "HI_REGS", \
1226 "CC_REG", \
1227 "VFPCC_REG", \
1228 "GENERAL_REGS", \
1229 "CORE_REGS", \
1230 "ALL_REGS", \
1231 }
1232
1233 /* Define which registers fit in which classes.
1234 This is an initializer for a vector of HARD_REG_SET
1235 of length N_REG_CLASSES. */
1236 #define REG_CLASS_CONTENTS \
1237 { \
1238 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1239 { 0x00FF0000, 0x00000000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
1240 { 0xF8000000, 0x000007FF, 0x00000000, 0x00000000 }, /* CIRRUS_REGS */ \
1241 { 0x00000000, 0x80000000, 0x00007FFF, 0x00000000 }, /* VFP_D0_D7_REGS */ \
1242 { 0x00000000, 0x80000000, 0x7FFFFFFF, 0x00000000 }, /* VFP_LO_REGS */ \
1243 { 0x00000000, 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_HI_REGS */ \
1244 { 0x00000000, 0x80000000, 0xFFFFFFFF, 0x7FFFFFFF }, /* VFP_REGS */ \
1245 { 0x00000000, 0x00007800, 0x00000000, 0x00000000 }, /* IWMMXT_GR_REGS */ \
1246 { 0x00000000, 0x7FFF8000, 0x00000000, 0x00000000 }, /* IWMMXT_REGS */ \
1247 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1248 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1249 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1250 { 0x0000DF00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1251 { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1252 { 0x00000000, 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
1253 { 0x0200DFFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1254 { 0x0200FFFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \
1255 { 0xFAFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
1256 }
1257
1258 /* Any of the VFP register classes. */
1259 #define IS_VFP_CLASS(X) \
1260 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \
1261 || (X) == VFP_HI_REGS || (X) == VFP_REGS)
1262
1263 /* The same information, inverted:
1264 Return the class number of the smallest class containing
1265 reg number REGNO. This could be a conditional expression
1266 or could index an array. */
1267 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1268
1269 /* The following macro defines cover classes for Integrated Register
1270 Allocator. Cover classes is a set of non-intersected register
1271 classes covering all hard registers used for register allocation
1272 purpose. Any move between two registers of a cover class should be
1273 cheaper than load or store of the registers. The macro value is
1274 array of register classes with LIM_REG_CLASSES used as the end
1275 marker. */
1276
1277 #define IRA_COVER_CLASSES \
1278 { \
1279 GENERAL_REGS, FPA_REGS, CIRRUS_REGS, VFP_REGS, IWMMXT_GR_REGS, IWMMXT_REGS,\
1280 LIM_REG_CLASSES \
1281 }
1282
1283 /* FPA registers can't do subreg as all values are reformatted to internal
1284 precision. VFP registers may only be accessed in the mode they
1285 were set. */
1286 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1287 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1288 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1289 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1290 : 0)
1291
1292 /* We need to define this for LO_REGS on thumb. Otherwise we can end up
1293 using r0-r4 for function arguments, r7 for the stack frame and don't
1294 have enough left over to do doubleword arithmetic. */
1295 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1296 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1297 || (CLASS) == CC_REG)
1298
1299 /* The class value for index registers, and the one for base regs. */
1300 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
1301 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS)
1302
1303 /* For the Thumb the high registers cannot be used as base registers
1304 when addressing quantities in QI or HI mode; if we don't know the
1305 mode, then we must be conservative. */
1306 #define MODE_BASE_REG_CLASS(MODE) \
1307 (TARGET_32BIT ? CORE_REGS : \
1308 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1309
1310 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1311 instead of BASE_REGS. */
1312 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
1313
1314 /* When this hook returns true for MODE, the compiler allows
1315 registers explicitly used in the rtl to be used as spill registers
1316 but prevents the compiler from extending the lifetime of these
1317 registers. */
1318 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
1319 arm_small_register_classes_for_mode_p
1320
1321 /* Given an rtx X being reloaded into a reg required to be
1322 in class CLASS, return the class of reg to actually use.
1323 In general this is just CLASS, but for the Thumb core registers and
1324 immediate constants we prefer a LO_REGS class or a subset. */
1325 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1326 (TARGET_32BIT ? (CLASS) : \
1327 ((CLASS) == GENERAL_REGS || (CLASS) == HI_REGS \
1328 || (CLASS) == NO_REGS || (CLASS) == STACK_REG \
1329 ? LO_REGS : (CLASS)))
1330
1331 /* Must leave BASE_REGS reloads alone */
1332 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1333 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1334 ? ((true_regnum (X) == -1 ? LO_REGS \
1335 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1336 : NO_REGS)) \
1337 : NO_REGS)
1338
1339 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1340 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1341 ? ((true_regnum (X) == -1 ? LO_REGS \
1342 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1343 : NO_REGS)) \
1344 : NO_REGS)
1345
1346 /* Return the register class of a scratch register needed to copy IN into
1347 or out of a register in CLASS in MODE. If it can be done directly,
1348 NO_REGS is returned. */
1349 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1350 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1351 ((TARGET_VFP && TARGET_HARD_FLOAT \
1352 && IS_VFP_CLASS (CLASS)) \
1353 ? coproc_secondary_reload_class (MODE, X, FALSE) \
1354 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \
1355 ? coproc_secondary_reload_class (MODE, X, TRUE) \
1356 : TARGET_32BIT \
1357 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1358 ? GENERAL_REGS : NO_REGS) \
1359 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1360
1361 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1362 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1363 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1364 ((TARGET_VFP && TARGET_HARD_FLOAT \
1365 && IS_VFP_CLASS (CLASS)) \
1366 ? coproc_secondary_reload_class (MODE, X, FALSE) : \
1367 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \
1368 coproc_secondary_reload_class (MODE, X, TRUE) : \
1369 /* Cannot load constants into Cirrus registers. */ \
1370 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1371 && (CLASS) == CIRRUS_REGS \
1372 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1373 ? GENERAL_REGS : \
1374 (TARGET_32BIT ? \
1375 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1376 && CONSTANT_P (X)) \
1377 ? GENERAL_REGS : \
1378 (((MODE) == HImode && ! arm_arch4 \
1379 && (GET_CODE (X) == MEM \
1380 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1381 && true_regnum (X) == -1))) \
1382 ? GENERAL_REGS : NO_REGS) \
1383 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1384
1385 /* Try a machine-dependent way of reloading an illegitimate address
1386 operand. If we find one, push the reload and jump to WIN. This
1387 macro is used in only one place: `find_reloads_address' in reload.c.
1388
1389 For the ARM, we wish to handle large displacements off a base
1390 register by splitting the addend across a MOV and the mem insn.
1391 This can cut the number of reloads needed. */
1392 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1393 do \
1394 { \
1395 if (GET_CODE (X) == PLUS \
1396 && GET_CODE (XEXP (X, 0)) == REG \
1397 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1398 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1399 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1400 { \
1401 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1402 HOST_WIDE_INT low, high; \
1403 \
1404 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
1405 low = ((val & 0xf) ^ 0x8) - 0x8; \
1406 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
1407 /* Need to be careful, -256 is not a valid offset. */ \
1408 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1409 else if (MODE == SImode \
1410 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1411 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1412 /* Need to be careful, -4096 is not a valid offset. */ \
1413 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1414 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1415 /* Need to be careful, -256 is not a valid offset. */ \
1416 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1417 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1418 && TARGET_HARD_FLOAT && TARGET_FPA) \
1419 /* Need to be careful, -1024 is not a valid offset. */ \
1420 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1421 else \
1422 break; \
1423 \
1424 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1425 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1426 - (unsigned HOST_WIDE_INT) 0x80000000); \
1427 /* Check for overflow or zero */ \
1428 if (low == 0 || high == 0 || (high + low != val)) \
1429 break; \
1430 \
1431 /* Reload the high part into a base reg; leave the low part \
1432 in the mem. */ \
1433 X = gen_rtx_PLUS (GET_MODE (X), \
1434 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1435 GEN_INT (high)), \
1436 GEN_INT (low)); \
1437 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1438 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1439 VOIDmode, 0, 0, OPNUM, TYPE); \
1440 goto WIN; \
1441 } \
1442 } \
1443 while (0)
1444
1445 /* XXX If an HImode FP+large_offset address is converted to an HImode
1446 SP+large_offset address, then reload won't know how to fix it. It sees
1447 only that SP isn't valid for HImode, and so reloads the SP into an index
1448 register, but the resulting address is still invalid because the offset
1449 is too big. We fix it here instead by reloading the entire address. */
1450 /* We could probably achieve better results by defining PROMOTE_MODE to help
1451 cope with the variances between the Thumb's signed and unsigned byte and
1452 halfword load instructions. */
1453 /* ??? This should be safe for thumb2, but we may be able to do better. */
1454 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
1455 do { \
1456 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
1457 if (new_x) \
1458 { \
1459 X = new_x; \
1460 goto WIN; \
1461 } \
1462 } while (0)
1463
1464 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1465 if (TARGET_ARM) \
1466 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1467 else \
1468 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1469
1470 /* Return the maximum number of consecutive registers
1471 needed to represent mode MODE in a register of class CLASS.
1472 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1473 #define CLASS_MAX_NREGS(CLASS, MODE) \
1474 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1475
1476 /* If defined, gives a class of registers that cannot be used as the
1477 operand of a SUBREG that changes the mode of the object illegally. */
1478
1479 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns.
1480 Moves between VFP_REGS and GENERAL_REGS are a single insn, but
1481 it is typically more expensive than a single memory access. We set
1482 the cost to less than two memory accesses so that floating
1483 point to integer conversion does not go through memory. */
1484 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1485 (TARGET_32BIT ? \
1486 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1487 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1488 IS_VFP_CLASS (FROM) && !IS_VFP_CLASS (TO) ? 15 : \
1489 !IS_VFP_CLASS (FROM) && IS_VFP_CLASS (TO) ? 15 : \
1490 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1491 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1492 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1493 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1494 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1495 2) \
1496 : \
1497 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1498 \f
1499 /* Stack layout; function entry, exit and calling. */
1500
1501 /* Define this if pushing a word on the stack
1502 makes the stack pointer a smaller address. */
1503 #define STACK_GROWS_DOWNWARD 1
1504
1505 /* Define this to nonzero if the nominal address of the stack frame
1506 is at the high-address end of the local variables;
1507 that is, each additional local variable allocated
1508 goes at a more negative offset in the frame. */
1509 #define FRAME_GROWS_DOWNWARD 1
1510
1511 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1512 When present, it is one word in size, and sits at the top of the frame,
1513 between the soft frame pointer and either r7 or r11.
1514
1515 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1516 and only then if some outgoing arguments are passed on the stack. It would
1517 be tempting to also check whether the stack arguments are passed by indirect
1518 calls, but there seems to be no reason in principle why a post-reload pass
1519 couldn't convert a direct call into an indirect one. */
1520 #define CALLER_INTERWORKING_SLOT_SIZE \
1521 (TARGET_CALLER_INTERWORKING \
1522 && crtl->outgoing_args_size != 0 \
1523 ? UNITS_PER_WORD : 0)
1524
1525 /* Offset within stack frame to start allocating local variables at.
1526 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1527 first local allocated. Otherwise, it is the offset to the BEGINNING
1528 of the first local allocated. */
1529 #define STARTING_FRAME_OFFSET 0
1530
1531 /* If we generate an insn to push BYTES bytes,
1532 this says how many the stack pointer really advances by. */
1533 /* The push insns do not do this rounding implicitly.
1534 So don't define this. */
1535 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1536
1537 /* Define this if the maximum size of all the outgoing args is to be
1538 accumulated and pushed during the prologue. The amount can be
1539 found in the variable crtl->outgoing_args_size. */
1540 #define ACCUMULATE_OUTGOING_ARGS 1
1541
1542 /* Offset of first parameter from the argument pointer register value. */
1543 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1544
1545 /* Define how to find the value returned by a library function
1546 assuming the value has mode MODE. */
1547 #define LIBCALL_VALUE(MODE) \
1548 (TARGET_AAPCS_BASED ? aapcs_libcall_value (MODE) \
1549 : (TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
1550 && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
1551 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1552 : TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
1553 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1554 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1555 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
1556 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1557 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1558
1559 /* 1 if REGNO is a possible register number for a function value. */
1560 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1561 ((REGNO) == ARG_REGISTER (1) \
1562 || (TARGET_AAPCS_BASED && TARGET_32BIT \
1563 && TARGET_VFP && TARGET_HARD_FLOAT \
1564 && (REGNO) == FIRST_VFP_REGNUM) \
1565 || (TARGET_32BIT && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1566 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
1567 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
1568 || (TARGET_32BIT && ((REGNO) == FIRST_FPA_REGNUM) \
1569 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
1570
1571 /* Amount of memory needed for an untyped call to save all possible return
1572 registers. */
1573 #define APPLY_RESULT_SIZE arm_apply_result_size()
1574
1575 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1576 values must be in memory. On the ARM, they need only do so if larger
1577 than a word, or if they contain elements offset from zero in the struct. */
1578 #define DEFAULT_PCC_STRUCT_RETURN 0
1579
1580 /* These bits describe the different types of function supported
1581 by the ARM backend. They are exclusive. i.e. a function cannot be both a
1582 normal function and an interworked function, for example. Knowing the
1583 type of a function is important for determining its prologue and
1584 epilogue sequences.
1585 Note value 7 is currently unassigned. Also note that the interrupt
1586 function types all have bit 2 set, so that they can be tested for easily.
1587 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1588 machine_function structure is initialized (to zero) func_type will
1589 default to unknown. This will force the first use of arm_current_func_type
1590 to call arm_compute_func_type. */
1591 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1592 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1593 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1594 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1595 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1596 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1597
1598 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1599
1600 /* In addition functions can have several type modifiers,
1601 outlined by these bit masks: */
1602 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1603 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1604 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1605 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1606 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */
1607
1608 /* Some macros to test these flags. */
1609 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1610 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1611 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1612 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1613 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1614 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN)
1615
1616
1617 /* Structure used to hold the function stack frame layout. Offsets are
1618 relative to the stack pointer on function entry. Positive offsets are
1619 in the direction of stack growth.
1620 Only soft_frame is used in thumb mode. */
1621
1622 typedef struct GTY(()) arm_stack_offsets
1623 {
1624 int saved_args; /* ARG_POINTER_REGNUM. */
1625 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1626 int saved_regs;
1627 int soft_frame; /* FRAME_POINTER_REGNUM. */
1628 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */
1629 int outgoing_args; /* STACK_POINTER_REGNUM. */
1630 unsigned int saved_regs_mask;
1631 }
1632 arm_stack_offsets;
1633
1634 #ifndef GENERATOR_FILE
1635 /* A C structure for machine-specific, per-function data.
1636 This is added to the cfun structure. */
1637 typedef struct GTY(()) machine_function
1638 {
1639 /* Additional stack adjustment in __builtin_eh_throw. */
1640 rtx eh_epilogue_sp_ofs;
1641 /* Records if LR has to be saved for far jumps. */
1642 int far_jump_used;
1643 /* Records if ARG_POINTER was ever live. */
1644 int arg_pointer_live;
1645 /* Records if the save of LR has been eliminated. */
1646 int lr_save_eliminated;
1647 /* The size of the stack frame. Only valid after reload. */
1648 arm_stack_offsets stack_offsets;
1649 /* Records the type of the current function. */
1650 unsigned long func_type;
1651 /* Record if the function has a variable argument list. */
1652 int uses_anonymous_args;
1653 /* Records if sibcalls are blocked because an argument
1654 register is needed to preserve stack alignment. */
1655 int sibcall_blocked;
1656 /* The PIC register for this function. This might be a pseudo. */
1657 rtx pic_reg;
1658 /* Labels for per-function Thumb call-via stubs. One per potential calling
1659 register. We can never call via LR or PC. We can call via SP if a
1660 trampoline happens to be on the top of the stack. */
1661 rtx call_via[14];
1662 /* Set to 1 when a return insn is output, this means that the epilogue
1663 is not needed. */
1664 int return_used_this_function;
1665 /* When outputting Thumb-1 code, record the last insn that provides
1666 information about condition codes, and the comparison operands. */
1667 rtx thumb1_cc_insn;
1668 rtx thumb1_cc_op0;
1669 rtx thumb1_cc_op1;
1670 /* Also record the CC mode that is supported. */
1671 enum machine_mode thumb1_cc_mode;
1672 }
1673 machine_function;
1674 #endif
1675
1676 /* As in the machine_function, a global set of call-via labels, for code
1677 that is in text_section. */
1678 extern GTY(()) rtx thumb_call_via_label[14];
1679
1680 /* The number of potential ways of assigning to a co-processor. */
1681 #define ARM_NUM_COPROC_SLOTS 1
1682
1683 /* Enumeration of procedure calling standard variants. We don't really
1684 support all of these yet. */
1685 enum arm_pcs
1686 {
1687 ARM_PCS_AAPCS, /* Base standard AAPCS. */
1688 ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */
1689 ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */
1690 /* This must be the last AAPCS variant. */
1691 ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */
1692 ARM_PCS_ATPCS, /* ATPCS. */
1693 ARM_PCS_APCS, /* APCS (legacy Linux etc). */
1694 ARM_PCS_UNKNOWN
1695 };
1696
1697 /* Default procedure calling standard of current compilation unit. */
1698 extern enum arm_pcs arm_pcs_default;
1699
1700 /* A C type for declaring a variable that is used as the first argument of
1701 `FUNCTION_ARG' and other related values. */
1702 typedef struct
1703 {
1704 /* This is the number of registers of arguments scanned so far. */
1705 int nregs;
1706 /* This is the number of iWMMXt register arguments scanned so far. */
1707 int iwmmxt_nregs;
1708 int named_count;
1709 int nargs;
1710 /* Which procedure call variant to use for this call. */
1711 enum arm_pcs pcs_variant;
1712
1713 /* AAPCS related state tracking. */
1714 int aapcs_arg_processed; /* No need to lay out this argument again. */
1715 int aapcs_cprc_slot; /* Index of co-processor rules to handle
1716 this argument, or -1 if using core
1717 registers. */
1718 int aapcs_ncrn;
1719 int aapcs_next_ncrn;
1720 rtx aapcs_reg; /* Register assigned to this argument. */
1721 int aapcs_partial; /* How many bytes are passed in regs (if
1722 split between core regs and stack.
1723 Zero otherwise. */
1724 int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS];
1725 int can_split; /* Argument can be split between core regs
1726 and the stack. */
1727 /* Private data for tracking VFP register allocation */
1728 unsigned aapcs_vfp_regs_free;
1729 unsigned aapcs_vfp_reg_alloc;
1730 int aapcs_vfp_rcount;
1731 MACHMODE aapcs_vfp_rmode;
1732 } CUMULATIVE_ARGS;
1733
1734 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1735 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1736
1737 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1738 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1739
1740 /* For AAPCS, padding should never be below the argument. For other ABIs,
1741 * mimic the default. */
1742 #define PAD_VARARGS_DOWN \
1743 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1744
1745 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1746 for a call to a function whose data type is FNTYPE.
1747 For a library call, FNTYPE is 0.
1748 On the ARM, the offset starts at 0. */
1749 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1750 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1751
1752 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1753 argument with the specified mode and type. If it is not defined,
1754 `PARM_BOUNDARY' is used for all arguments. */
1755 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1756 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1757 ? DOUBLEWORD_ALIGNMENT \
1758 : PARM_BOUNDARY )
1759
1760 /* 1 if N is a possible register number for function argument passing.
1761 On the ARM, r0-r3 are used to pass args. */
1762 #define FUNCTION_ARG_REGNO_P(REGNO) \
1763 (IN_RANGE ((REGNO), 0, 3) \
1764 || (TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT \
1765 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \
1766 || (TARGET_IWMMXT_ABI \
1767 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1768
1769 \f
1770 /* If your target environment doesn't prefix user functions with an
1771 underscore, you may wish to re-define this to prevent any conflicts. */
1772 #ifndef ARM_MCOUNT_NAME
1773 #define ARM_MCOUNT_NAME "*mcount"
1774 #endif
1775
1776 /* Call the function profiler with a given profile label. The Acorn
1777 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1778 On the ARM the full profile code will look like:
1779 .data
1780 LP1
1781 .word 0
1782 .text
1783 mov ip, lr
1784 bl mcount
1785 .word LP1
1786
1787 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1788 will output the .text section.
1789
1790 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1791 ``prof'' doesn't seem to mind about this!
1792
1793 Note - this version of the code is designed to work in both ARM and
1794 Thumb modes. */
1795 #ifndef ARM_FUNCTION_PROFILER
1796 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1797 { \
1798 char temp[20]; \
1799 rtx sym; \
1800 \
1801 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1802 IP_REGNUM, LR_REGNUM); \
1803 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1804 fputc ('\n', STREAM); \
1805 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1806 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1807 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1808 }
1809 #endif
1810
1811 #ifdef THUMB_FUNCTION_PROFILER
1812 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1813 if (TARGET_ARM) \
1814 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1815 else \
1816 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1817 #else
1818 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1819 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1820 #endif
1821
1822 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1823 the stack pointer does not matter. The value is tested only in
1824 functions that have frame pointers.
1825 No definition is equivalent to always zero.
1826
1827 On the ARM, the function epilogue recovers the stack pointer from the
1828 frame. */
1829 #define EXIT_IGNORE_STACK 1
1830
1831 #define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNUM)
1832
1833 /* Determine if the epilogue should be output as RTL.
1834 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1835 #define USE_RETURN_INSN(ISCOND) \
1836 (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0)
1837
1838 /* Definitions for register eliminations.
1839
1840 This is an array of structures. Each structure initializes one pair
1841 of eliminable registers. The "from" register number is given first,
1842 followed by "to". Eliminations of the same "from" register are listed
1843 in order of preference.
1844
1845 We have two registers that can be eliminated on the ARM. First, the
1846 arg pointer register can often be eliminated in favor of the stack
1847 pointer register. Secondly, the pseudo frame pointer register can always
1848 be eliminated; it is replaced with either the stack or the real frame
1849 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1850 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1851
1852 #define ELIMINABLE_REGS \
1853 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1854 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1855 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1856 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1857 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1858 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1859 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1860
1861 /* Define the offset between two registers, one to be eliminated, and the
1862 other its replacement, at the start of a routine. */
1863 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1864 if (TARGET_ARM) \
1865 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1866 else \
1867 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1868
1869 /* Special case handling of the location of arguments passed on the stack. */
1870 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1871
1872 /* Initialize data used by insn expanders. This is called from insn_emit,
1873 once for every function before code is generated. */
1874 #define INIT_EXPANDERS arm_init_expanders ()
1875
1876 /* Length in units of the trampoline for entering a nested function. */
1877 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20)
1878
1879 /* Alignment required for a trampoline in bits. */
1880 #define TRAMPOLINE_ALIGNMENT 32
1881 \f
1882 /* Addressing modes, and classification of registers for them. */
1883 #define HAVE_POST_INCREMENT 1
1884 #define HAVE_PRE_INCREMENT TARGET_32BIT
1885 #define HAVE_POST_DECREMENT TARGET_32BIT
1886 #define HAVE_PRE_DECREMENT TARGET_32BIT
1887 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT
1888 #define HAVE_POST_MODIFY_DISP TARGET_32BIT
1889 #define HAVE_PRE_MODIFY_REG TARGET_32BIT
1890 #define HAVE_POST_MODIFY_REG TARGET_32BIT
1891
1892 /* Macros to check register numbers against specific register classes. */
1893
1894 /* These assume that REGNO is a hard or pseudo reg number.
1895 They give nonzero only if REGNO is a hard reg of the suitable class
1896 or a pseudo reg currently allocated to a suitable hard reg.
1897 Since they use reg_renumber, they are safe only once reg_renumber
1898 has been allocated, which happens in local-alloc.c. */
1899 #define TEST_REGNO(R, TEST, VALUE) \
1900 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1901
1902 /* Don't allow the pc to be used. */
1903 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1904 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1905 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1906 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1907
1908 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1909 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1910 || (GET_MODE_SIZE (MODE) >= 4 \
1911 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1912
1913 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1914 (TARGET_THUMB1 \
1915 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1916 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1917
1918 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1919 For Thumb, we can not use SP + reg, so reject SP. */
1920 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1921 REGNO_MODE_OK_FOR_BASE_P (X, QImode)
1922
1923 /* For ARM code, we don't care about the mode, but for Thumb, the index
1924 must be suitable for use in a QImode load. */
1925 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1926 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \
1927 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))
1928
1929 /* Maximum number of registers that can appear in a valid memory address.
1930 Shifts in addresses can't be by a register. */
1931 #define MAX_REGS_PER_ADDRESS 2
1932
1933 /* Recognize any constant value that is a valid address. */
1934 /* XXX We can address any constant, eventually... */
1935 /* ??? Should the TARGET_ARM here also apply to thumb2? */
1936 #define CONSTANT_ADDRESS_P(X) \
1937 (GET_CODE (X) == SYMBOL_REF \
1938 && (CONSTANT_POOL_ADDRESS_P (X) \
1939 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1940
1941 /* True if SYMBOL + OFFSET constants must refer to something within
1942 SYMBOL's section. */
1943 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0
1944
1945 /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */
1946 #ifndef TARGET_DEFAULT_WORD_RELOCATIONS
1947 #define TARGET_DEFAULT_WORD_RELOCATIONS 0
1948 #endif
1949
1950 /* Nonzero if the constant value X is a legitimate general operand.
1951 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1952
1953 On the ARM, allow any integer (invalid ones are removed later by insn
1954 patterns), nice doubles and symbol_refs which refer to the function's
1955 constant pool XXX.
1956
1957 When generating pic allow anything. */
1958 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1959
1960 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
1961 ( GET_CODE (X) == CONST_INT \
1962 || GET_CODE (X) == CONST_DOUBLE \
1963 || CONSTANT_ADDRESS_P (X) \
1964 || flag_pic)
1965
1966 #define LEGITIMATE_CONSTANT_P(X) \
1967 (!arm_cannot_force_const_mem (X) \
1968 && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X) \
1969 : THUMB_LEGITIMATE_CONSTANT_P (X)))
1970
1971 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1972 #define SUBTARGET_NAME_ENCODING_LENGTHS
1973 #endif
1974
1975 /* This is a C fragment for the inside of a switch statement.
1976 Each case label should return the number of characters to
1977 be stripped from the start of a function's name, if that
1978 name starts with the indicated character. */
1979 #define ARM_NAME_ENCODING_LENGTHS \
1980 case '*': return 1; \
1981 SUBTARGET_NAME_ENCODING_LENGTHS
1982
1983 /* This is how to output a reference to a user-level label named NAME.
1984 `assemble_name' uses this. */
1985 #undef ASM_OUTPUT_LABELREF
1986 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1987 arm_asm_output_labelref (FILE, NAME)
1988
1989 /* Output IT instructions for conditionally executed Thumb-2 instructions. */
1990 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
1991 if (TARGET_THUMB2) \
1992 thumb2_asm_output_opcode (STREAM);
1993
1994 /* The EABI specifies that constructors should go in .init_array.
1995 Other targets use .ctors for compatibility. */
1996 #ifndef ARM_EABI_CTORS_SECTION_OP
1997 #define ARM_EABI_CTORS_SECTION_OP \
1998 "\t.section\t.init_array,\"aw\",%init_array"
1999 #endif
2000 #ifndef ARM_EABI_DTORS_SECTION_OP
2001 #define ARM_EABI_DTORS_SECTION_OP \
2002 "\t.section\t.fini_array,\"aw\",%fini_array"
2003 #endif
2004 #define ARM_CTORS_SECTION_OP \
2005 "\t.section\t.ctors,\"aw\",%progbits"
2006 #define ARM_DTORS_SECTION_OP \
2007 "\t.section\t.dtors,\"aw\",%progbits"
2008
2009 /* Define CTORS_SECTION_ASM_OP. */
2010 #undef CTORS_SECTION_ASM_OP
2011 #undef DTORS_SECTION_ASM_OP
2012 #ifndef IN_LIBGCC2
2013 # define CTORS_SECTION_ASM_OP \
2014 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
2015 # define DTORS_SECTION_ASM_OP \
2016 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
2017 #else /* !defined (IN_LIBGCC2) */
2018 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
2019 so we cannot use the definition above. */
2020 # ifdef __ARM_EABI__
2021 /* The .ctors section is not part of the EABI, so we do not define
2022 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
2023 from trying to use it. We do define it when doing normal
2024 compilation, as .init_array can be used instead of .ctors. */
2025 /* There is no need to emit begin or end markers when using
2026 init_array; the dynamic linker will compute the size of the
2027 array itself based on special symbols created by the static
2028 linker. However, we do need to arrange to set up
2029 exception-handling here. */
2030 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
2031 # define CTOR_LIST_END /* empty */
2032 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
2033 # define DTOR_LIST_END /* empty */
2034 # else /* !defined (__ARM_EABI__) */
2035 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
2036 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
2037 # endif /* !defined (__ARM_EABI__) */
2038 #endif /* !defined (IN_LIBCC2) */
2039
2040 /* True if the operating system can merge entities with vague linkage
2041 (e.g., symbols in COMDAT group) during dynamic linking. */
2042 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
2043 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
2044 #endif
2045
2046 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
2047
2048 #ifdef TARGET_UNWIND_INFO
2049 #define ARM_EABI_UNWIND_TABLES \
2050 ((!USING_SJLJ_EXCEPTIONS && flag_exceptions) || flag_unwind_tables)
2051 #else
2052 #define ARM_EABI_UNWIND_TABLES 0
2053 #endif
2054
2055 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2056 and check its validity for a certain class.
2057 We have two alternate definitions for each of them.
2058 The usual definition accepts all pseudo regs; the other rejects
2059 them unless they have been allocated suitable hard regs.
2060 The symbol REG_OK_STRICT causes the latter definition to be used.
2061 Thumb-2 has the same restrictions as arm. */
2062 #ifndef REG_OK_STRICT
2063
2064 #define ARM_REG_OK_FOR_BASE_P(X) \
2065 (REGNO (X) <= LAST_ARM_REGNUM \
2066 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2067 || REGNO (X) == FRAME_POINTER_REGNUM \
2068 || REGNO (X) == ARG_POINTER_REGNUM)
2069
2070 #define ARM_REG_OK_FOR_INDEX_P(X) \
2071 ((REGNO (X) <= LAST_ARM_REGNUM \
2072 && REGNO (X) != STACK_POINTER_REGNUM) \
2073 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2074 || REGNO (X) == FRAME_POINTER_REGNUM \
2075 || REGNO (X) == ARG_POINTER_REGNUM)
2076
2077 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2078 (REGNO (X) <= LAST_LO_REGNUM \
2079 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2080 || (GET_MODE_SIZE (MODE) >= 4 \
2081 && (REGNO (X) == STACK_POINTER_REGNUM \
2082 || (X) == hard_frame_pointer_rtx \
2083 || (X) == arg_pointer_rtx)))
2084
2085 #define REG_STRICT_P 0
2086
2087 #else /* REG_OK_STRICT */
2088
2089 #define ARM_REG_OK_FOR_BASE_P(X) \
2090 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2091
2092 #define ARM_REG_OK_FOR_INDEX_P(X) \
2093 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X))
2094
2095 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2096 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2097
2098 #define REG_STRICT_P 1
2099
2100 #endif /* REG_OK_STRICT */
2101
2102 /* Now define some helpers in terms of the above. */
2103
2104 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2105 (TARGET_THUMB1 \
2106 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2107 : ARM_REG_OK_FOR_BASE_P (X))
2108
2109 /* For 16-bit Thumb, a valid index register is anything that can be used in
2110 a byte load instruction. */
2111 #define THUMB1_REG_OK_FOR_INDEX_P(X) \
2112 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode)
2113
2114 /* Nonzero if X is a hard reg that can be used as an index
2115 or if it is a pseudo reg. On the Thumb, the stack pointer
2116 is not suitable. */
2117 #define REG_OK_FOR_INDEX_P(X) \
2118 (TARGET_THUMB1 \
2119 ? THUMB1_REG_OK_FOR_INDEX_P (X) \
2120 : ARM_REG_OK_FOR_INDEX_P (X))
2121
2122 /* Nonzero if X can be the base register in a reg+reg addressing mode.
2123 For Thumb, we can not use SP + reg, so reject SP. */
2124 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2125 REG_OK_FOR_INDEX_P (X)
2126 \f
2127 #define ARM_BASE_REGISTER_RTX_P(X) \
2128 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2129
2130 #define ARM_INDEX_REGISTER_RTX_P(X) \
2131 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2132 \f
2133 /* Define this for compatibility reasons. */
2134 #define HANDLE_PRAGMA_PACK_PUSH_POP
2135
2136 /* Specify the machine mode that this machine uses
2137 for the index in the tablejump instruction. */
2138 #define CASE_VECTOR_MODE Pmode
2139
2140 #define CASE_VECTOR_PC_RELATIVE (TARGET_THUMB2 \
2141 || (TARGET_THUMB1 \
2142 && (optimize_size || flag_pic)))
2143
2144 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \
2145 (TARGET_THUMB1 \
2146 ? (min >= 0 && max < 512 \
2147 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \
2148 : min >= -256 && max < 256 \
2149 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \
2150 : min >= 0 && max < 8192 \
2151 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \
2152 : min >= -4096 && max < 4096 \
2153 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \
2154 : SImode) \
2155 : ((min < 0 || max >= 0x2000 || !TARGET_THUMB2) ? SImode \
2156 : (max >= 0x200) ? HImode \
2157 : QImode))
2158
2159 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2160 unsigned is probably best, but may break some code. */
2161 #ifndef DEFAULT_SIGNED_CHAR
2162 #define DEFAULT_SIGNED_CHAR 0
2163 #endif
2164
2165 /* Max number of bytes we can move from memory to memory
2166 in one reasonably fast instruction. */
2167 #define MOVE_MAX 4
2168
2169 #undef MOVE_RATIO
2170 #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2)
2171
2172 /* Define if operations between registers always perform the operation
2173 on the full register even if a narrower mode is specified. */
2174 #define WORD_REGISTER_OPERATIONS
2175
2176 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2177 will either zero-extend or sign-extend. The value of this macro should
2178 be the code that says which one of the two operations is implicitly
2179 done, UNKNOWN if none. */
2180 #define LOAD_EXTEND_OP(MODE) \
2181 (TARGET_THUMB ? ZERO_EXTEND : \
2182 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2183 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
2184
2185 /* Nonzero if access to memory by bytes is slow and undesirable. */
2186 #define SLOW_BYTE_ACCESS 0
2187
2188 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2189
2190 /* Immediate shift counts are truncated by the output routines (or was it
2191 the assembler?). Shift counts in a register are truncated by ARM. Note
2192 that the native compiler puts too large (> 32) immediate shift counts
2193 into a register and shifts by the register, letting the ARM decide what
2194 to do instead of doing that itself. */
2195 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2196 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2197 On the arm, Y in a register is used modulo 256 for the shift. Only for
2198 rotates is modulo 32 used. */
2199 /* #define SHIFT_COUNT_TRUNCATED 1 */
2200
2201 /* All integers have the same format so truncation is easy. */
2202 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2203
2204 /* Calling from registers is a massive pain. */
2205 #define NO_FUNCTION_CSE 1
2206
2207 /* The machine modes of pointers and functions */
2208 #define Pmode SImode
2209 #define FUNCTION_MODE Pmode
2210
2211 #define ARM_FRAME_RTX(X) \
2212 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2213 || (X) == arg_pointer_rtx)
2214
2215 /* Moves to and from memory are quite expensive */
2216 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2217 (TARGET_32BIT ? 10 : \
2218 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2219 * (CLASS == LO_REGS ? 1 : 2)))
2220
2221 /* Try to generate sequences that don't involve branches, we can then use
2222 conditional instructions */
2223 #define BRANCH_COST(speed_p, predictable_p) \
2224 (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0))
2225 \f
2226 /* Position Independent Code. */
2227 /* We decide which register to use based on the compilation options and
2228 the assembler in use; this is more general than the APCS restriction of
2229 using sb (r9) all the time. */
2230 extern unsigned arm_pic_register;
2231
2232 /* The register number of the register used to address a table of static
2233 data addresses in memory. */
2234 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2235
2236 /* We can't directly access anything that contains a symbol,
2237 nor can we indirect via the constant pool. One exception is
2238 UNSPEC_TLS, which is always PIC. */
2239 #define LEGITIMATE_PIC_OPERAND_P(X) \
2240 (!(symbol_mentioned_p (X) \
2241 || label_mentioned_p (X) \
2242 || (GET_CODE (X) == SYMBOL_REF \
2243 && CONSTANT_POOL_ADDRESS_P (X) \
2244 && (symbol_mentioned_p (get_pool_constant (X)) \
2245 || label_mentioned_p (get_pool_constant (X))))) \
2246 || tls_mentioned_p (X))
2247
2248 /* We need to know when we are making a constant pool; this determines
2249 whether data needs to be in the GOT or can be referenced via a GOT
2250 offset. */
2251 extern int making_const_table;
2252 \f
2253 /* Handle pragmas for compatibility with Intel's compilers. */
2254 /* Also abuse this to register additional C specific EABI attributes. */
2255 #define REGISTER_TARGET_PRAGMAS() do { \
2256 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2257 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2258 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2259 arm_lang_object_attributes_init(); \
2260 } while (0)
2261
2262 /* Condition code information. */
2263 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2264 return the mode to be used for the comparison. */
2265
2266 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2267
2268 #define REVERSIBLE_CC_MODE(MODE) 1
2269
2270 #define REVERSE_CONDITION(CODE,MODE) \
2271 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2272 ? reverse_condition_maybe_unordered (code) \
2273 : reverse_condition (code))
2274
2275 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2276 (CODE) = arm_canonicalize_comparison (CODE, &(OP0), &(OP1))
2277
2278 /* The arm5 clz instruction returns 32. */
2279 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2280 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2281 \f
2282 #define CC_STATUS_INIT \
2283 do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0)
2284
2285 #undef ASM_APP_OFF
2286 #define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \
2287 TARGET_THUMB2 ? "\t.thumb\n" : "")
2288
2289 /* Output a push or a pop instruction (only used when profiling).
2290 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know
2291 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and
2292 that r7 isn't used by the function profiler, so we can use it as a
2293 scratch reg. WARNING: This isn't safe in the general case! It may be
2294 sensitive to future changes in final.c:profile_function. */
2295 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2296 do \
2297 { \
2298 if (TARGET_ARM) \
2299 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2300 STACK_POINTER_REGNUM, REGNO); \
2301 else if (TARGET_THUMB1 \
2302 && (REGNO) == STATIC_CHAIN_REGNUM) \
2303 { \
2304 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \
2305 asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\
2306 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \
2307 } \
2308 else \
2309 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2310 } while (0)
2311
2312
2313 /* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */
2314 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2315 do \
2316 { \
2317 if (TARGET_ARM) \
2318 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2319 STACK_POINTER_REGNUM, REGNO); \
2320 else if (TARGET_THUMB1 \
2321 && (REGNO) == STATIC_CHAIN_REGNUM) \
2322 { \
2323 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \
2324 asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\
2325 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \
2326 } \
2327 else \
2328 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2329 } while (0)
2330
2331 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */
2332 #define ADDR_VEC_ALIGN(JUMPTABLE) 0
2333
2334 /* This is how to output a label which precedes a jumptable. Since
2335 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2336 #undef ASM_OUTPUT_CASE_LABEL
2337 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2338 do \
2339 { \
2340 if (TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) \
2341 ASM_OUTPUT_ALIGN (FILE, 2); \
2342 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2343 } \
2344 while (0)
2345
2346 /* Make sure subsequent insns are aligned after a TBB. */
2347 #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \
2348 do \
2349 { \
2350 if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \
2351 ASM_OUTPUT_ALIGN (FILE, 1); \
2352 } \
2353 while (0)
2354
2355 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2356 do \
2357 { \
2358 if (TARGET_THUMB) \
2359 { \
2360 if (is_called_in_ARM_mode (DECL) \
2361 || (TARGET_THUMB1 && !TARGET_THUMB1_ONLY \
2362 && cfun->is_thunk)) \
2363 fprintf (STREAM, "\t.code 32\n") ; \
2364 else if (TARGET_THUMB1) \
2365 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \
2366 else \
2367 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \
2368 } \
2369 if (TARGET_POKE_FUNCTION_NAME) \
2370 arm_poke_function_name (STREAM, (const char *) NAME); \
2371 } \
2372 while (0)
2373
2374 /* For aliases of functions we use .thumb_set instead. */
2375 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2376 do \
2377 { \
2378 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2379 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2380 \
2381 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2382 { \
2383 fprintf (FILE, "\t.thumb_set "); \
2384 assemble_name (FILE, LABEL1); \
2385 fprintf (FILE, ","); \
2386 assemble_name (FILE, LABEL2); \
2387 fprintf (FILE, "\n"); \
2388 } \
2389 else \
2390 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2391 } \
2392 while (0)
2393
2394 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2395 /* To support -falign-* switches we need to use .p2align so
2396 that alignment directives in code sections will be padded
2397 with no-op instructions, rather than zeroes. */
2398 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2399 if ((LOG) != 0) \
2400 { \
2401 if ((MAX_SKIP) == 0) \
2402 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2403 else \
2404 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2405 (int) (LOG), (int) (MAX_SKIP)); \
2406 }
2407 #endif
2408 \f
2409 /* Add two bytes to the length of conditionally executed Thumb-2
2410 instructions for the IT instruction. */
2411 #define ADJUST_INSN_LENGTH(insn, length) \
2412 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \
2413 length += 2;
2414
2415 /* Only perform branch elimination (by making instructions conditional) if
2416 we're optimizing. For Thumb-2 check if any IT instructions need
2417 outputting. */
2418 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2419 if (TARGET_ARM && optimize) \
2420 arm_final_prescan_insn (INSN); \
2421 else if (TARGET_THUMB2) \
2422 thumb2_final_prescan_insn (INSN); \
2423 else if (TARGET_THUMB1) \
2424 thumb1_final_prescan_insn (INSN)
2425
2426 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2427 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2428 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2429 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2430 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2431 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2432 : 0))))
2433
2434 #define OUTPUT_ADDR_CONST_EXTRA(file, x, fail) \
2435 if (arm_output_addr_const_extra (file, x) == FALSE) \
2436 goto fail
2437
2438 /* A C expression whose value is RTL representing the value of the return
2439 address for the frame COUNT steps up from the current frame. */
2440
2441 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2442 arm_return_addr (COUNT, FRAME)
2443
2444 /* Mask of the bits in the PC that contain the real return address
2445 when running in 26-bit mode. */
2446 #define RETURN_ADDR_MASK26 (0x03fffffc)
2447
2448 /* Pick up the return address upon entry to a procedure. Used for
2449 dwarf2 unwind information. This also enables the table driven
2450 mechanism. */
2451 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2452 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2453
2454 /* Used to mask out junk bits from the return address, such as
2455 processor state, interrupt status, condition codes and the like. */
2456 #define MASK_RETURN_ADDR \
2457 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2458 in 26 bit mode, the condition codes must be masked out of the \
2459 return address. This does not apply to ARM6 and later processors \
2460 when running in 32 bit mode. */ \
2461 ((arm_arch4 || TARGET_THUMB) \
2462 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2463 : arm_gen_return_addr_mask ())
2464
2465 \f
2466 /* Neon defines builtins from ARM_BUILTIN_MAX upwards, though they don't have
2467 symbolic names defined here (which would require too much duplication).
2468 FIXME? */
2469 enum arm_builtins
2470 {
2471 ARM_BUILTIN_GETWCX,
2472 ARM_BUILTIN_SETWCX,
2473
2474 ARM_BUILTIN_WZERO,
2475
2476 ARM_BUILTIN_WAVG2BR,
2477 ARM_BUILTIN_WAVG2HR,
2478 ARM_BUILTIN_WAVG2B,
2479 ARM_BUILTIN_WAVG2H,
2480
2481 ARM_BUILTIN_WACCB,
2482 ARM_BUILTIN_WACCH,
2483 ARM_BUILTIN_WACCW,
2484
2485 ARM_BUILTIN_WMACS,
2486 ARM_BUILTIN_WMACSZ,
2487 ARM_BUILTIN_WMACU,
2488 ARM_BUILTIN_WMACUZ,
2489
2490 ARM_BUILTIN_WSADB,
2491 ARM_BUILTIN_WSADBZ,
2492 ARM_BUILTIN_WSADH,
2493 ARM_BUILTIN_WSADHZ,
2494
2495 ARM_BUILTIN_WALIGN,
2496
2497 ARM_BUILTIN_TMIA,
2498 ARM_BUILTIN_TMIAPH,
2499 ARM_BUILTIN_TMIABB,
2500 ARM_BUILTIN_TMIABT,
2501 ARM_BUILTIN_TMIATB,
2502 ARM_BUILTIN_TMIATT,
2503
2504 ARM_BUILTIN_TMOVMSKB,
2505 ARM_BUILTIN_TMOVMSKH,
2506 ARM_BUILTIN_TMOVMSKW,
2507
2508 ARM_BUILTIN_TBCSTB,
2509 ARM_BUILTIN_TBCSTH,
2510 ARM_BUILTIN_TBCSTW,
2511
2512 ARM_BUILTIN_WMADDS,
2513 ARM_BUILTIN_WMADDU,
2514
2515 ARM_BUILTIN_WPACKHSS,
2516 ARM_BUILTIN_WPACKWSS,
2517 ARM_BUILTIN_WPACKDSS,
2518 ARM_BUILTIN_WPACKHUS,
2519 ARM_BUILTIN_WPACKWUS,
2520 ARM_BUILTIN_WPACKDUS,
2521
2522 ARM_BUILTIN_WADDB,
2523 ARM_BUILTIN_WADDH,
2524 ARM_BUILTIN_WADDW,
2525 ARM_BUILTIN_WADDSSB,
2526 ARM_BUILTIN_WADDSSH,
2527 ARM_BUILTIN_WADDSSW,
2528 ARM_BUILTIN_WADDUSB,
2529 ARM_BUILTIN_WADDUSH,
2530 ARM_BUILTIN_WADDUSW,
2531 ARM_BUILTIN_WSUBB,
2532 ARM_BUILTIN_WSUBH,
2533 ARM_BUILTIN_WSUBW,
2534 ARM_BUILTIN_WSUBSSB,
2535 ARM_BUILTIN_WSUBSSH,
2536 ARM_BUILTIN_WSUBSSW,
2537 ARM_BUILTIN_WSUBUSB,
2538 ARM_BUILTIN_WSUBUSH,
2539 ARM_BUILTIN_WSUBUSW,
2540
2541 ARM_BUILTIN_WAND,
2542 ARM_BUILTIN_WANDN,
2543 ARM_BUILTIN_WOR,
2544 ARM_BUILTIN_WXOR,
2545
2546 ARM_BUILTIN_WCMPEQB,
2547 ARM_BUILTIN_WCMPEQH,
2548 ARM_BUILTIN_WCMPEQW,
2549 ARM_BUILTIN_WCMPGTUB,
2550 ARM_BUILTIN_WCMPGTUH,
2551 ARM_BUILTIN_WCMPGTUW,
2552 ARM_BUILTIN_WCMPGTSB,
2553 ARM_BUILTIN_WCMPGTSH,
2554 ARM_BUILTIN_WCMPGTSW,
2555
2556 ARM_BUILTIN_TEXTRMSB,
2557 ARM_BUILTIN_TEXTRMSH,
2558 ARM_BUILTIN_TEXTRMSW,
2559 ARM_BUILTIN_TEXTRMUB,
2560 ARM_BUILTIN_TEXTRMUH,
2561 ARM_BUILTIN_TEXTRMUW,
2562 ARM_BUILTIN_TINSRB,
2563 ARM_BUILTIN_TINSRH,
2564 ARM_BUILTIN_TINSRW,
2565
2566 ARM_BUILTIN_WMAXSW,
2567 ARM_BUILTIN_WMAXSH,
2568 ARM_BUILTIN_WMAXSB,
2569 ARM_BUILTIN_WMAXUW,
2570 ARM_BUILTIN_WMAXUH,
2571 ARM_BUILTIN_WMAXUB,
2572 ARM_BUILTIN_WMINSW,
2573 ARM_BUILTIN_WMINSH,
2574 ARM_BUILTIN_WMINSB,
2575 ARM_BUILTIN_WMINUW,
2576 ARM_BUILTIN_WMINUH,
2577 ARM_BUILTIN_WMINUB,
2578
2579 ARM_BUILTIN_WMULUM,
2580 ARM_BUILTIN_WMULSM,
2581 ARM_BUILTIN_WMULUL,
2582
2583 ARM_BUILTIN_PSADBH,
2584 ARM_BUILTIN_WSHUFH,
2585
2586 ARM_BUILTIN_WSLLH,
2587 ARM_BUILTIN_WSLLW,
2588 ARM_BUILTIN_WSLLD,
2589 ARM_BUILTIN_WSRAH,
2590 ARM_BUILTIN_WSRAW,
2591 ARM_BUILTIN_WSRAD,
2592 ARM_BUILTIN_WSRLH,
2593 ARM_BUILTIN_WSRLW,
2594 ARM_BUILTIN_WSRLD,
2595 ARM_BUILTIN_WRORH,
2596 ARM_BUILTIN_WRORW,
2597 ARM_BUILTIN_WRORD,
2598 ARM_BUILTIN_WSLLHI,
2599 ARM_BUILTIN_WSLLWI,
2600 ARM_BUILTIN_WSLLDI,
2601 ARM_BUILTIN_WSRAHI,
2602 ARM_BUILTIN_WSRAWI,
2603 ARM_BUILTIN_WSRADI,
2604 ARM_BUILTIN_WSRLHI,
2605 ARM_BUILTIN_WSRLWI,
2606 ARM_BUILTIN_WSRLDI,
2607 ARM_BUILTIN_WRORHI,
2608 ARM_BUILTIN_WRORWI,
2609 ARM_BUILTIN_WRORDI,
2610
2611 ARM_BUILTIN_WUNPCKIHB,
2612 ARM_BUILTIN_WUNPCKIHH,
2613 ARM_BUILTIN_WUNPCKIHW,
2614 ARM_BUILTIN_WUNPCKILB,
2615 ARM_BUILTIN_WUNPCKILH,
2616 ARM_BUILTIN_WUNPCKILW,
2617
2618 ARM_BUILTIN_WUNPCKEHSB,
2619 ARM_BUILTIN_WUNPCKEHSH,
2620 ARM_BUILTIN_WUNPCKEHSW,
2621 ARM_BUILTIN_WUNPCKEHUB,
2622 ARM_BUILTIN_WUNPCKEHUH,
2623 ARM_BUILTIN_WUNPCKEHUW,
2624 ARM_BUILTIN_WUNPCKELSB,
2625 ARM_BUILTIN_WUNPCKELSH,
2626 ARM_BUILTIN_WUNPCKELSW,
2627 ARM_BUILTIN_WUNPCKELUB,
2628 ARM_BUILTIN_WUNPCKELUH,
2629 ARM_BUILTIN_WUNPCKELUW,
2630
2631 ARM_BUILTIN_THREAD_POINTER,
2632
2633 ARM_BUILTIN_NEON_BASE,
2634
2635 ARM_BUILTIN_MAX = ARM_BUILTIN_NEON_BASE /* FIXME: Wrong! */
2636 };
2637
2638 /* Do not emit .note.GNU-stack by default. */
2639 #ifndef NEED_INDICATE_EXEC_STACK
2640 #define NEED_INDICATE_EXEC_STACK 0
2641 #endif
2642
2643 /* The maximum number of parallel loads or stores we support in an ldm/stm
2644 instruction. */
2645 #define MAX_LDM_STM_OPS 4
2646
2647 #endif /* ! GCC_ARM_H */
Mirror of https://gcc.gnu.org/git/gcc.git