]> git.ipfire.org Git - thirdparty/gcc.git/blob - gcc/config/arm/arm.h
projects / thirdparty / gcc.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
target.def (target_option.optimization): New hook.
[thirdparty/gcc.git] / gcc / config / arm / arm.h
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
6 and Martin Simmons (@harleqn.co.uk).
7 More major hacks by Richard Earnshaw (rearnsha@arm.com)
8 Minor hacks by Nick Clifton (nickc@cygnus.com)
9
10 This file is part of GCC.
11
12 GCC is free software; you can redistribute it and/or modify it
13 under the terms of the GNU General Public License as published
14 by the Free Software Foundation; either version 3, or (at your
15 option) any later version.
16
17 GCC is distributed in the hope that it will be useful, but WITHOUT
18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
19 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
25
26 #ifndef GCC_ARM_H
27 #define GCC_ARM_H
28
29 /* We can't use enum machine_mode inside a generator file because it
30 hasn't been created yet; we shouldn't be using any code that
31 needs the real definition though, so this ought to be safe. */
32 #ifdef GENERATOR_FILE
33 #define MACHMODE int
34 #else
35 #include "insn-modes.h"
36 #define MACHMODE enum machine_mode
37 #endif
38
39 #include "config/vxworks-dummy.h"
40
41 /* The architecture define. */
42 extern char arm_arch_name[];
43
44 /* Target CPU builtins. */
45 #define TARGET_CPU_CPP_BUILTINS() \
46 do \
47 { \
48 /* Define __arm__ even when in thumb mode, for \
49 consistency with armcc. */ \
50 builtin_define ("__arm__"); \
51 builtin_define ("__APCS_32__"); \
52 if (TARGET_THUMB) \
53 builtin_define ("__thumb__"); \
54 if (TARGET_THUMB2) \
55 builtin_define ("__thumb2__"); \
56 \
57 if (TARGET_BIG_END) \
58 { \
59 builtin_define ("__ARMEB__"); \
60 if (TARGET_THUMB) \
61 builtin_define ("__THUMBEB__"); \
62 if (TARGET_LITTLE_WORDS) \
63 builtin_define ("__ARMWEL__"); \
64 } \
65 else \
66 { \
67 builtin_define ("__ARMEL__"); \
68 if (TARGET_THUMB) \
69 builtin_define ("__THUMBEL__"); \
70 } \
71 \
72 if (TARGET_SOFT_FLOAT) \
73 builtin_define ("__SOFTFP__"); \
74 \
75 if (TARGET_VFP) \
76 builtin_define ("__VFP_FP__"); \
77 \
78 if (TARGET_NEON) \
79 builtin_define ("__ARM_NEON__"); \
80 \
81 /* Add a define for interworking. \
82 Needed when building libgcc.a. */ \
83 if (arm_cpp_interwork) \
84 builtin_define ("__THUMB_INTERWORK__"); \
85 \
86 builtin_assert ("cpu=arm"); \
87 builtin_assert ("machine=arm"); \
88 \
89 builtin_define (arm_arch_name); \
90 if (arm_arch_cirrus) \
91 builtin_define ("__MAVERICK__"); \
92 if (arm_arch_xscale) \
93 builtin_define ("__XSCALE__"); \
94 if (arm_arch_iwmmxt) \
95 builtin_define ("__IWMMXT__"); \
96 if (TARGET_AAPCS_BASED) \
97 { \
98 if (arm_pcs_default == ARM_PCS_AAPCS_VFP) \
99 builtin_define ("__ARM_PCS_VFP"); \
100 else if (arm_pcs_default == ARM_PCS_AAPCS) \
101 builtin_define ("__ARM_PCS"); \
102 builtin_define ("__ARM_EABI__"); \
103 } \
104 } while (0)
105
106 /* The various ARM cores. */
107 enum processor_type
108 {
109 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
110 IDENT,
111 #include "arm-cores.def"
112 #undef ARM_CORE
113 /* Used to indicate that no processor has been specified. */
114 arm_none
115 };
116
117 enum target_cpus
118 {
119 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
120 TARGET_CPU_##IDENT,
121 #include "arm-cores.def"
122 #undef ARM_CORE
123 TARGET_CPU_generic
124 };
125
126 /* The processor for which instructions should be scheduled. */
127 extern enum processor_type arm_tune;
128
129 enum arm_sync_generator_tag
130 {
131 arm_sync_generator_omn,
132 arm_sync_generator_omrn
133 };
134
135 /* Wrapper to pass around a polymorphic pointer to a sync instruction
136 generator and. */
137 struct arm_sync_generator
138 {
139 enum arm_sync_generator_tag op;
140 union
141 {
142 rtx (* omn) (rtx, rtx, rtx);
143 rtx (* omrn) (rtx, rtx, rtx, rtx);
144 } u;
145 };
146
147 typedef enum arm_cond_code
148 {
149 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
150 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
151 }
152 arm_cc;
153
154 extern arm_cc arm_current_cc;
155
156 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
157
158 extern int arm_target_label;
159 extern int arm_ccfsm_state;
160 extern GTY(()) rtx arm_target_insn;
161 /* The label of the current constant pool. */
162 extern rtx pool_vector_label;
163 /* Set to 1 when a return insn is output, this means that the epilogue
164 is not needed. */
165 extern int return_used_this_function;
166 /* Callback to output language specific object attributes. */
167 extern void (*arm_lang_output_object_attributes_hook)(void);
168 \f
169 /* Just in case configure has failed to define anything. */
170 #ifndef TARGET_CPU_DEFAULT
171 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
172 #endif
173
174
175 #undef CPP_SPEC
176 #define CPP_SPEC "%(subtarget_cpp_spec) \
177 %{msoft-float:%{mhard-float: \
178 %e-msoft-float and -mhard_float may not be used together}} \
179 %{mbig-endian:%{mlittle-endian: \
180 %e-mbig-endian and -mlittle-endian may not be used together}}"
181
182 #ifndef CC1_SPEC
183 #define CC1_SPEC ""
184 #endif
185
186 /* This macro defines names of additional specifications to put in the specs
187 that can be used in various specifications like CC1_SPEC. Its definition
188 is an initializer with a subgrouping for each command option.
189
190 Each subgrouping contains a string constant, that defines the
191 specification name, and a string constant that used by the GCC driver
192 program.
193
194 Do not define this macro if it does not need to do anything. */
195 #define EXTRA_SPECS \
196 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
197 SUBTARGET_EXTRA_SPECS
198
199 #ifndef SUBTARGET_EXTRA_SPECS
200 #define SUBTARGET_EXTRA_SPECS
201 #endif
202
203 #ifndef SUBTARGET_CPP_SPEC
204 #define SUBTARGET_CPP_SPEC ""
205 #endif
206 \f
207 /* Run-time Target Specification. */
208 #ifndef TARGET_VERSION
209 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
210 #endif
211
212 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
213 /* Use hardware floating point instructions. */
214 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
215 /* Use hardware floating point calling convention. */
216 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
217 #define TARGET_FPA (arm_fpu_desc->model == ARM_FP_MODEL_FPA)
218 #define TARGET_MAVERICK (arm_fpu_desc->model == ARM_FP_MODEL_MAVERICK)
219 #define TARGET_VFP (arm_fpu_desc->model == ARM_FP_MODEL_VFP)
220 #define TARGET_IWMMXT (arm_arch_iwmmxt)
221 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT)
222 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT)
223 #define TARGET_ARM (! TARGET_THUMB)
224 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
225 #define TARGET_BACKTRACE (leaf_function_p () \
226 ? TARGET_TPCS_LEAF_FRAME \
227 : TARGET_TPCS_FRAME)
228 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
229 #define TARGET_AAPCS_BASED \
230 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
231
232 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
233 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
234
235 /* Only 16-bit thumb code. */
236 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2)
237 /* Arm or Thumb-2 32-bit code. */
238 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2)
239 /* 32-bit Thumb-2 code. */
240 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2)
241 /* Thumb-1 only. */
242 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm)
243 /* FPA emulator without LFM. */
244 #define TARGET_FPA_EMU2 (TARGET_FPA && arm_fpu_desc->rev == 2)
245
246 /* The following two macros concern the ability to execute coprocessor
247 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently
248 only ever tested when we know we are generating for VFP hardware; we need
249 to be more careful with TARGET_NEON as noted below. */
250
251 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */
252 #define TARGET_VFPD32 (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_D32)
253
254 /* FPU supports VFPv3 instructions. */
255 #define TARGET_VFP3 (TARGET_VFP && arm_fpu_desc->rev >= 3)
256
257 /* FPU only supports VFP single-precision instructions. */
258 #define TARGET_VFP_SINGLE (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_SINGLE)
259
260 /* FPU supports VFP double-precision instructions. */
261 #define TARGET_VFP_DOUBLE (TARGET_VFP && arm_fpu_desc->regs != VFP_REG_SINGLE)
262
263 /* FPU supports half-precision floating-point with NEON element load/store. */
264 #define TARGET_NEON_FP16 \
265 (TARGET_VFP && arm_fpu_desc->neon && arm_fpu_desc->fp16)
266
267 /* FPU supports VFP half-precision floating-point. */
268 #define TARGET_FP16 (TARGET_VFP && arm_fpu_desc->fp16)
269
270 /* FPU supports Neon instructions. The setting of this macro gets
271 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT
272 and TARGET_HARD_FLOAT to ensure that NEON instructions are
273 available. */
274 #define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \
275 && TARGET_VFP && arm_fpu_desc->neon)
276
277 /* "DSP" multiply instructions, eg. SMULxy. */
278 #define TARGET_DSP_MULTIPLY \
279 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7em))
280 /* Integer SIMD instructions, and extend-accumulate instructions. */
281 #define TARGET_INT_SIMD \
282 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em))
283
284 /* Should MOVW/MOVT be used in preference to a constant pool. */
285 #define TARGET_USE_MOVT (arm_arch_thumb2 && !optimize_size)
286
287 /* We could use unified syntax for arm mode, but for now we just use it
288 for Thumb-2. */
289 #define TARGET_UNIFIED_ASM TARGET_THUMB2
290
291 /* Nonzero if this chip provides the DMB instruction. */
292 #define TARGET_HAVE_DMB (arm_arch7)
293
294 /* Nonzero if this chip implements a memory barrier via CP15. */
295 #define TARGET_HAVE_DMB_MCR (arm_arch6k && ! TARGET_HAVE_DMB)
296
297 /* Nonzero if this chip implements a memory barrier instruction. */
298 #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR)
299
300 /* Nonzero if this chip supports ldrex and strex */
301 #define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7)
302
303 /* Nonzero if this chip supports ldrex{bhd} and strex{bhd}. */
304 #define TARGET_HAVE_LDREXBHD ((arm_arch6k && TARGET_ARM) || arm_arch7)
305
306 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
307 then TARGET_AAPCS_BASED must be true -- but the converse does not
308 hold. TARGET_BPABI implies the use of the BPABI runtime library,
309 etc., in addition to just the AAPCS calling conventions. */
310 #ifndef TARGET_BPABI
311 #define TARGET_BPABI false
312 #endif
313
314 /* Support for a compile-time default CPU, et cetera. The rules are:
315 --with-arch is ignored if -march or -mcpu are specified.
316 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
317 by --with-arch.
318 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
319 by -march).
320 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
321 specified.
322 --with-fpu is ignored if -mfpu is specified.
323 --with-abi is ignored is -mabi is specified. */
324 #define OPTION_DEFAULT_SPECS \
325 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
326 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
327 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
328 {"float", \
329 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
330 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
331 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \
332 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"},
333
334 /* Which floating point model to use. */
335 enum arm_fp_model
336 {
337 ARM_FP_MODEL_UNKNOWN,
338 /* FPA model (Hardware or software). */
339 ARM_FP_MODEL_FPA,
340 /* Cirrus Maverick floating point model. */
341 ARM_FP_MODEL_MAVERICK,
342 /* VFP floating point model. */
343 ARM_FP_MODEL_VFP
344 };
345
346 enum vfp_reg_type
347 {
348 VFP_NONE = 0,
349 VFP_REG_D16,
350 VFP_REG_D32,
351 VFP_REG_SINGLE
352 };
353
354 extern const struct arm_fpu_desc
355 {
356 const char *name;
357 enum arm_fp_model model;
358 int rev;
359 enum vfp_reg_type regs;
360 int neon;
361 int fp16;
362 } *arm_fpu_desc;
363
364 /* Which floating point hardware to schedule for. */
365 extern int arm_fpu_attr;
366
367 enum float_abi_type
368 {
369 ARM_FLOAT_ABI_SOFT,
370 ARM_FLOAT_ABI_SOFTFP,
371 ARM_FLOAT_ABI_HARD
372 };
373
374 extern enum float_abi_type arm_float_abi;
375
376 #ifndef TARGET_DEFAULT_FLOAT_ABI
377 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
378 #endif
379
380 /* Which __fp16 format to use.
381 The enumeration values correspond to the numbering for the
382 Tag_ABI_FP_16bit_format attribute.
383 */
384 enum arm_fp16_format_type
385 {
386 ARM_FP16_FORMAT_NONE = 0,
387 ARM_FP16_FORMAT_IEEE = 1,
388 ARM_FP16_FORMAT_ALTERNATIVE = 2
389 };
390
391 extern enum arm_fp16_format_type arm_fp16_format;
392 #define LARGEST_EXPONENT_IS_NORMAL(bits) \
393 ((bits) == 16 && arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE)
394
395 /* Which ABI to use. */
396 enum arm_abi_type
397 {
398 ARM_ABI_APCS,
399 ARM_ABI_ATPCS,
400 ARM_ABI_AAPCS,
401 ARM_ABI_IWMMXT,
402 ARM_ABI_AAPCS_LINUX
403 };
404
405 extern enum arm_abi_type arm_abi;
406
407 #ifndef ARM_DEFAULT_ABI
408 #define ARM_DEFAULT_ABI ARM_ABI_APCS
409 #endif
410
411 /* Which thread pointer access sequence to use. */
412 enum arm_tp_type {
413 TP_AUTO,
414 TP_SOFT,
415 TP_CP15
416 };
417
418 extern enum arm_tp_type target_thread_pointer;
419
420 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
421 extern int arm_arch3m;
422
423 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
424 extern int arm_arch4;
425
426 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
427 extern int arm_arch4t;
428
429 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
430 extern int arm_arch5;
431
432 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
433 extern int arm_arch5e;
434
435 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
436 extern int arm_arch6;
437
438 /* Nonzero if this chip supports the ARM Architecture 6k extensions. */
439 extern int arm_arch6k;
440
441 /* Nonzero if this chip supports the ARM Architecture 7 extensions. */
442 extern int arm_arch7;
443
444 /* Nonzero if instructions not present in the 'M' profile can be used. */
445 extern int arm_arch_notm;
446
447 /* Nonzero if instructions present in ARMv7E-M can be used. */
448 extern int arm_arch7em;
449
450 /* Nonzero if this chip can benefit from load scheduling. */
451 extern int arm_ld_sched;
452
453 /* Nonzero if generating Thumb code, either Thumb-1 or Thumb-2. */
454 extern int thumb_code;
455
456 /* Nonzero if generating Thumb-1 code. */
457 extern int thumb1_code;
458
459 /* Nonzero if this chip is a StrongARM. */
460 extern int arm_tune_strongarm;
461
462 /* Nonzero if this chip is a Cirrus variant. */
463 extern int arm_arch_cirrus;
464
465 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
466 extern int arm_arch_iwmmxt;
467
468 /* Nonzero if this chip is an XScale. */
469 extern int arm_arch_xscale;
470
471 /* Nonzero if tuning for XScale. */
472 extern int arm_tune_xscale;
473
474 /* Nonzero if tuning for stores via the write buffer. */
475 extern int arm_tune_wbuf;
476
477 /* Nonzero if tuning for Cortex-A9. */
478 extern int arm_tune_cortex_a9;
479
480 /* Nonzero if we should define __THUMB_INTERWORK__ in the
481 preprocessor.
482 XXX This is a bit of a hack, it's intended to help work around
483 problems in GLD which doesn't understand that armv5t code is
484 interworking clean. */
485 extern int arm_cpp_interwork;
486
487 /* Nonzero if chip supports Thumb 2. */
488 extern int arm_arch_thumb2;
489
490 /* Nonzero if chip supports integer division instruction. */
491 extern int arm_arch_hwdiv;
492
493 #ifndef TARGET_DEFAULT
494 #define TARGET_DEFAULT (MASK_APCS_FRAME)
495 #endif
496
497 /* The frame pointer register used in gcc has nothing to do with debugging;
498 that is controlled by the APCS-FRAME option. */
499 #define CAN_DEBUG_WITHOUT_FP
500
501 /* Nonzero if PIC code requires explicit qualifiers to generate
502 PLT and GOT relocs rather than the assembler doing so implicitly.
503 Subtargets can override these if required. */
504 #ifndef NEED_GOT_RELOC
505 #define NEED_GOT_RELOC 0
506 #endif
507 #ifndef NEED_PLT_RELOC
508 #define NEED_PLT_RELOC 0
509 #endif
510
511 /* Nonzero if we need to refer to the GOT with a PC-relative
512 offset. In other words, generate
513
514 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
515
516 rather than
517
518 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
519
520 The default is true, which matches NetBSD. Subtargets can
521 override this if required. */
522 #ifndef GOT_PCREL
523 #define GOT_PCREL 1
524 #endif
525 \f
526 /* Target machine storage Layout. */
527
528
529 /* Define this macro if it is advisable to hold scalars in registers
530 in a wider mode than that declared by the program. In such cases,
531 the value is constrained to be within the bounds of the declared
532 type, but kept valid in the wider mode. The signedness of the
533 extension may differ from that of the type. */
534
535 /* It is far faster to zero extend chars than to sign extend them */
536
537 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
538 if (GET_MODE_CLASS (MODE) == MODE_INT \
539 && GET_MODE_SIZE (MODE) < 4) \
540 { \
541 if (MODE == QImode) \
542 UNSIGNEDP = 1; \
543 else if (MODE == HImode) \
544 UNSIGNEDP = 1; \
545 (MODE) = SImode; \
546 }
547
548 /* Define this if most significant bit is lowest numbered
549 in instructions that operate on numbered bit-fields. */
550 #define BITS_BIG_ENDIAN 0
551
552 /* Define this if most significant byte of a word is the lowest numbered.
553 Most ARM processors are run in little endian mode, so that is the default.
554 If you want to have it run-time selectable, change the definition in a
555 cover file to be TARGET_BIG_ENDIAN. */
556 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
557
558 /* Define this if most significant word of a multiword number is the lowest
559 numbered.
560 This is always false, even when in big-endian mode. */
561 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
562
563 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
564 on processor pre-defineds when compiling libgcc2.c. */
565 #if defined(__ARMEB__) && !defined(__ARMWEL__)
566 #define LIBGCC2_WORDS_BIG_ENDIAN 1
567 #else
568 #define LIBGCC2_WORDS_BIG_ENDIAN 0
569 #endif
570
571 /* Define this if most significant word of doubles is the lowest numbered.
572 The rules are different based on whether or not we use FPA-format,
573 VFP-format or some other floating point co-processor's format doubles. */
574 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
575
576 #define UNITS_PER_WORD 4
577
578 /* True if natural alignment is used for doubleword types. */
579 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
580
581 #define DOUBLEWORD_ALIGNMENT 64
582
583 #define PARM_BOUNDARY 32
584
585 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
586
587 #define PREFERRED_STACK_BOUNDARY \
588 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
589
590 #define FUNCTION_BOUNDARY ((TARGET_THUMB && optimize_size) ? 16 : 32)
591
592 /* The lowest bit is used to indicate Thumb-mode functions, so the
593 vbit must go into the delta field of pointers to member
594 functions. */
595 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
596
597 #define EMPTY_FIELD_BOUNDARY 32
598
599 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
600
601 /* XXX Blah -- this macro is used directly by libobjc. Since it
602 supports no vector modes, cut out the complexity and fall back
603 on BIGGEST_FIELD_ALIGNMENT. */
604 #ifdef IN_TARGET_LIBS
605 #define BIGGEST_FIELD_ALIGNMENT 64
606 #endif
607
608 /* Make strings word-aligned so strcpy from constants will be faster. */
609 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
610
611 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
612 ((TREE_CODE (EXP) == STRING_CST \
613 && !optimize_size \
614 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
615 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
616
617 /* Align definitions of arrays, unions and structures so that
618 initializations and copies can be made more efficient. This is not
619 ABI-changing, so it only affects places where we can see the
620 definition. */
621 #define DATA_ALIGNMENT(EXP, ALIGN) \
622 ((((ALIGN) < BITS_PER_WORD) \
623 && (TREE_CODE (EXP) == ARRAY_TYPE \
624 || TREE_CODE (EXP) == UNION_TYPE \
625 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
626
627 /* Similarly, make sure that objects on the stack are sensibly aligned. */
628 #define LOCAL_ALIGNMENT(EXP, ALIGN) DATA_ALIGNMENT(EXP, ALIGN)
629
630 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
631 value set in previous versions of this toolchain was 8, which produces more
632 compact structures. The command line option -mstructure_size_boundary=<n>
633 can be used to change this value. For compatibility with the ARM SDK
634 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
635 0020D) page 2-20 says "Structures are aligned on word boundaries".
636 The AAPCS specifies a value of 8. */
637 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
638 extern int arm_structure_size_boundary;
639
640 /* This is the value used to initialize arm_structure_size_boundary. If a
641 particular arm target wants to change the default value it should change
642 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
643 for an example of this. */
644 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
645 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
646 #endif
647
648 /* Nonzero if move instructions will actually fail to work
649 when given unaligned data. */
650 #define STRICT_ALIGNMENT 1
651
652 /* wchar_t is unsigned under the AAPCS. */
653 #ifndef WCHAR_TYPE
654 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
655
656 #define WCHAR_TYPE_SIZE BITS_PER_WORD
657 #endif
658
659 #ifndef SIZE_TYPE
660 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
661 #endif
662
663 #ifndef PTRDIFF_TYPE
664 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int")
665 #endif
666
667 /* AAPCS requires that structure alignment is affected by bitfields. */
668 #ifndef PCC_BITFIELD_TYPE_MATTERS
669 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
670 #endif
671
672 \f
673 /* Standard register usage. */
674
675 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
676 (S - saved over call).
677
678 r0 * argument word/integer result
679 r1-r3 argument word
680
681 r4-r8 S register variable
682 r9 S (rfp) register variable (real frame pointer)
683
684 r10 F S (sl) stack limit (used by -mapcs-stack-check)
685 r11 F S (fp) argument pointer
686 r12 (ip) temp workspace
687 r13 F S (sp) lower end of current stack frame
688 r14 (lr) link address/workspace
689 r15 F (pc) program counter
690
691 f0 floating point result
692 f1-f3 floating point scratch
693
694 f4-f7 S floating point variable
695
696 cc This is NOT a real register, but is used internally
697 to represent things that use or set the condition
698 codes.
699 sfp This isn't either. It is used during rtl generation
700 since the offset between the frame pointer and the
701 auto's isn't known until after register allocation.
702 afp Nor this, we only need this because of non-local
703 goto. Without it fp appears to be used and the
704 elimination code won't get rid of sfp. It tracks
705 fp exactly at all times.
706
707 *: See CONDITIONAL_REGISTER_USAGE */
708
709 /*
710 mvf0 Cirrus floating point result
711 mvf1-mvf3 Cirrus floating point scratch
712 mvf4-mvf15 S Cirrus floating point variable. */
713
714 /* s0-s15 VFP scratch (aka d0-d7).
715 s16-s31 S VFP variable (aka d8-d15).
716 vfpcc Not a real register. Represents the VFP condition
717 code flags. */
718
719 /* The stack backtrace structure is as follows:
720 fp points to here: | save code pointer | [fp]
721 | return link value | [fp, #-4]
722 | return sp value | [fp, #-8]
723 | return fp value | [fp, #-12]
724 [| saved r10 value |]
725 [| saved r9 value |]
726 [| saved r8 value |]
727 [| saved r7 value |]
728 [| saved r6 value |]
729 [| saved r5 value |]
730 [| saved r4 value |]
731 [| saved r3 value |]
732 [| saved r2 value |]
733 [| saved r1 value |]
734 [| saved r0 value |]
735 [| saved f7 value |] three words
736 [| saved f6 value |] three words
737 [| saved f5 value |] three words
738 [| saved f4 value |] three words
739 r0-r3 are not normally saved in a C function. */
740
741 /* 1 for registers that have pervasive standard uses
742 and are not available for the register allocator. */
743 #define FIXED_REGISTERS \
744 { \
745 0,0,0,0,0,0,0,0, \
746 0,0,0,0,0,1,0,1, \
747 0,0,0,0,0,0,0,0, \
748 1,1,1, \
749 1,1,1,1,1,1,1,1, \
750 1,1,1,1,1,1,1,1, \
751 1,1,1,1,1,1,1,1, \
752 1,1,1,1,1,1,1,1, \
753 1,1,1,1, \
754 1,1,1,1,1,1,1,1, \
755 1,1,1,1,1,1,1,1, \
756 1,1,1,1,1,1,1,1, \
757 1,1,1,1,1,1,1,1, \
758 1,1,1,1,1,1,1,1, \
759 1,1,1,1,1,1,1,1, \
760 1,1,1,1,1,1,1,1, \
761 1,1,1,1,1,1,1,1, \
762 1 \
763 }
764
765 /* 1 for registers not available across function calls.
766 These must include the FIXED_REGISTERS and also any
767 registers that can be used without being saved.
768 The latter must include the registers where values are returned
769 and the register where structure-value addresses are passed.
770 Aside from that, you can include as many other registers as you like.
771 The CC is not preserved over function calls on the ARM 6, so it is
772 easier to assume this for all. SFP is preserved, since FP is. */
773 #define CALL_USED_REGISTERS \
774 { \
775 1,1,1,1,0,0,0,0, \
776 0,0,0,0,1,1,1,1, \
777 1,1,1,1,0,0,0,0, \
778 1,1,1, \
779 1,1,1,1,1,1,1,1, \
780 1,1,1,1,1,1,1,1, \
781 1,1,1,1,1,1,1,1, \
782 1,1,1,1,1,1,1,1, \
783 1,1,1,1, \
784 1,1,1,1,1,1,1,1, \
785 1,1,1,1,1,1,1,1, \
786 1,1,1,1,1,1,1,1, \
787 1,1,1,1,1,1,1,1, \
788 1,1,1,1,1,1,1,1, \
789 1,1,1,1,1,1,1,1, \
790 1,1,1,1,1,1,1,1, \
791 1,1,1,1,1,1,1,1, \
792 1 \
793 }
794
795 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
796 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
797 #endif
798
799 #define CONDITIONAL_REGISTER_USAGE \
800 { \
801 int regno; \
802 \
803 if (TARGET_SOFT_FLOAT || TARGET_THUMB1 || !TARGET_FPA) \
804 { \
805 for (regno = FIRST_FPA_REGNUM; \
806 regno <= LAST_FPA_REGNUM; ++regno) \
807 fixed_regs[regno] = call_used_regs[regno] = 1; \
808 } \
809 \
810 if (TARGET_THUMB1 && optimize_size) \
811 { \
812 /* When optimizing for size on Thumb-1, it's better not \
813 to use the HI regs, because of the overhead of \
814 stacking them. */ \
815 for (regno = FIRST_HI_REGNUM; \
816 regno <= LAST_HI_REGNUM; ++regno) \
817 fixed_regs[regno] = call_used_regs[regno] = 1; \
818 } \
819 \
820 /* The link register can be clobbered by any branch insn, \
821 but we have no way to track that at present, so mark \
822 it as unavailable. */ \
823 if (TARGET_THUMB1) \
824 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
825 \
826 if (TARGET_32BIT && TARGET_HARD_FLOAT) \
827 { \
828 if (TARGET_MAVERICK) \
829 { \
830 for (regno = FIRST_FPA_REGNUM; \
831 regno <= LAST_FPA_REGNUM; ++ regno) \
832 fixed_regs[regno] = call_used_regs[regno] = 1; \
833 for (regno = FIRST_CIRRUS_FP_REGNUM; \
834 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
835 { \
836 fixed_regs[regno] = 0; \
837 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
838 } \
839 } \
840 if (TARGET_VFP) \
841 { \
842 /* VFPv3 registers are disabled when earlier VFP \
843 versions are selected due to the definition of \
844 LAST_VFP_REGNUM. */ \
845 for (regno = FIRST_VFP_REGNUM; \
846 regno <= LAST_VFP_REGNUM; ++ regno) \
847 { \
848 fixed_regs[regno] = 0; \
849 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16 \
850 || regno >= FIRST_VFP_REGNUM + 32; \
851 } \
852 } \
853 } \
854 \
855 if (TARGET_REALLY_IWMMXT) \
856 { \
857 regno = FIRST_IWMMXT_GR_REGNUM; \
858 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
859 and wCG1 as call-preserved registers. The 2002/11/21 \
860 revision changed this so that all wCG registers are \
861 scratch registers. */ \
862 for (regno = FIRST_IWMMXT_GR_REGNUM; \
863 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
864 fixed_regs[regno] = 0; \
865 /* The XScale ABI has wR0 - wR9 as scratch registers, \
866 the rest as call-preserved registers. */ \
867 for (regno = FIRST_IWMMXT_REGNUM; \
868 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
869 { \
870 fixed_regs[regno] = 0; \
871 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
872 } \
873 } \
874 \
875 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
876 { \
877 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
878 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
879 } \
880 else if (TARGET_APCS_STACK) \
881 { \
882 fixed_regs[10] = 1; \
883 call_used_regs[10] = 1; \
884 } \
885 /* -mcaller-super-interworking reserves r11 for calls to \
886 _interwork_r11_call_via_rN(). Making the register global \
887 is an easy way of ensuring that it remains valid for all \
888 calls. */ \
889 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \
890 || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \
891 { \
892 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
893 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
894 if (TARGET_CALLER_INTERWORKING) \
895 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
896 } \
897 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
898 }
899
900 /* These are a couple of extensions to the formats accepted
901 by asm_fprintf:
902 %@ prints out ASM_COMMENT_START
903 %r prints out REGISTER_PREFIX reg_names[arg] */
904 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
905 case '@': \
906 fputs (ASM_COMMENT_START, FILE); \
907 break; \
908 \
909 case 'r': \
910 fputs (REGISTER_PREFIX, FILE); \
911 fputs (reg_names [va_arg (ARGS, int)], FILE); \
912 break;
913
914 /* Round X up to the nearest word. */
915 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
916
917 /* Convert fron bytes to ints. */
918 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
919
920 /* The number of (integer) registers required to hold a quantity of type MODE.
921 Also used for VFP registers. */
922 #define ARM_NUM_REGS(MODE) \
923 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
924
925 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
926 #define ARM_NUM_REGS2(MODE, TYPE) \
927 ARM_NUM_INTS ((MODE) == BLKmode ? \
928 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
929
930 /* The number of (integer) argument register available. */
931 #define NUM_ARG_REGS 4
932
933 /* And similarly for the VFP. */
934 #define NUM_VFP_ARG_REGS 16
935
936 /* Return the register number of the N'th (integer) argument. */
937 #define ARG_REGISTER(N) (N - 1)
938
939 /* Specify the registers used for certain standard purposes.
940 The values of these macros are register numbers. */
941
942 /* The number of the last argument register. */
943 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
944
945 /* The numbers of the Thumb register ranges. */
946 #define FIRST_LO_REGNUM 0
947 #define LAST_LO_REGNUM 7
948 #define FIRST_HI_REGNUM 8
949 #define LAST_HI_REGNUM 11
950
951 #ifndef TARGET_UNWIND_INFO
952 /* We use sjlj exceptions for backwards compatibility. */
953 #define MUST_USE_SJLJ_EXCEPTIONS 1
954 #endif
955
956 /* We can generate DWARF2 Unwind info, even though we don't use it. */
957 #define DWARF2_UNWIND_INFO 1
958
959 /* Use r0 and r1 to pass exception handling information. */
960 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
961
962 /* The register that holds the return address in exception handlers. */
963 #define ARM_EH_STACKADJ_REGNUM 2
964 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
965
966 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
967 as an invisible last argument (possible since varargs don't exist in
968 Pascal), so the following is not true. */
969 #define STATIC_CHAIN_REGNUM 12
970
971 /* Define this to be where the real frame pointer is if it is not possible to
972 work out the offset between the frame pointer and the automatic variables
973 until after register allocation has taken place. FRAME_POINTER_REGNUM
974 should point to a special register that we will make sure is eliminated.
975
976 For the Thumb we have another problem. The TPCS defines the frame pointer
977 as r11, and GCC believes that it is always possible to use the frame pointer
978 as base register for addressing purposes. (See comments in
979 find_reloads_address()). But - the Thumb does not allow high registers,
980 including r11, to be used as base address registers. Hence our problem.
981
982 The solution used here, and in the old thumb port is to use r7 instead of
983 r11 as the hard frame pointer and to have special code to generate
984 backtrace structures on the stack (if required to do so via a command line
985 option) using r11. This is the only 'user visible' use of r11 as a frame
986 pointer. */
987 #define ARM_HARD_FRAME_POINTER_REGNUM 11
988 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
989
990 #define HARD_FRAME_POINTER_REGNUM \
991 (TARGET_ARM \
992 ? ARM_HARD_FRAME_POINTER_REGNUM \
993 : THUMB_HARD_FRAME_POINTER_REGNUM)
994
995 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
996
997 /* Register to use for pushing function arguments. */
998 #define STACK_POINTER_REGNUM SP_REGNUM
999
1000 /* ARM floating pointer registers. */
1001 #define FIRST_FPA_REGNUM 16
1002 #define LAST_FPA_REGNUM 23
1003 #define IS_FPA_REGNUM(REGNUM) \
1004 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
1005
1006 #define FIRST_IWMMXT_GR_REGNUM 43
1007 #define LAST_IWMMXT_GR_REGNUM 46
1008 #define FIRST_IWMMXT_REGNUM 47
1009 #define LAST_IWMMXT_REGNUM 62
1010 #define IS_IWMMXT_REGNUM(REGNUM) \
1011 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
1012 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
1013 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
1014
1015 /* Base register for access to local variables of the function. */
1016 #define FRAME_POINTER_REGNUM 25
1017
1018 /* Base register for access to arguments of the function. */
1019 #define ARG_POINTER_REGNUM 26
1020
1021 #define FIRST_CIRRUS_FP_REGNUM 27
1022 #define LAST_CIRRUS_FP_REGNUM 42
1023 #define IS_CIRRUS_REGNUM(REGNUM) \
1024 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
1025
1026 #define FIRST_VFP_REGNUM 63
1027 #define D7_VFP_REGNUM 78 /* Registers 77 and 78 == VFP reg D7. */
1028 #define LAST_VFP_REGNUM \
1029 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM)
1030
1031 #define IS_VFP_REGNUM(REGNUM) \
1032 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
1033
1034 /* VFP registers are split into two types: those defined by VFP versions < 3
1035 have D registers overlaid on consecutive pairs of S registers. VFP version 3
1036 defines 16 new D registers (d16-d31) which, for simplicity and correctness
1037 in various parts of the backend, we implement as "fake" single-precision
1038 registers (which would be S32-S63, but cannot be used in that way). The
1039 following macros define these ranges of registers. */
1040 #define LAST_LO_VFP_REGNUM 94
1041 #define FIRST_HI_VFP_REGNUM 95
1042 #define LAST_HI_VFP_REGNUM 126
1043
1044 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \
1045 ((REGNUM) <= LAST_LO_VFP_REGNUM)
1046
1047 /* DFmode values are only valid in even register pairs. */
1048 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \
1049 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0)
1050
1051 /* Neon Quad values must start at a multiple of four registers. */
1052 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \
1053 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0)
1054
1055 /* Neon structures of vectors must be in even register pairs and there
1056 must be enough registers available. Because of various patterns
1057 requiring quad registers, we require them to start at a multiple of
1058 four. */
1059 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \
1060 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \
1061 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
1062
1063 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
1064 /* + 16 Cirrus registers take us up to 43. */
1065 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
1066 /* VFP (VFP3) adds 32 (64) + 1 more. */
1067 #define FIRST_PSEUDO_REGISTER 128
1068
1069 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
1070
1071 /* Value should be nonzero if functions must have frame pointers.
1072 Zero means the frame pointer need not be set up (and parms may be accessed
1073 via the stack pointer) in functions that seem suitable.
1074 If we have to have a frame pointer we might as well make use of it.
1075 APCS says that the frame pointer does not need to be pushed in leaf
1076 functions, or simple tail call functions. */
1077
1078 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1079 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1080 #endif
1081
1082 /* Return number of consecutive hard regs needed starting at reg REGNO
1083 to hold something of mode MODE.
1084 This is ordinarily the length in words of a value of mode MODE
1085 but can be less for certain modes in special long registers.
1086
1087 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
1088 mode. */
1089 #define HARD_REGNO_NREGS(REGNO, MODE) \
1090 ((TARGET_32BIT \
1091 && REGNO >= FIRST_FPA_REGNUM \
1092 && REGNO != FRAME_POINTER_REGNUM \
1093 && REGNO != ARG_POINTER_REGNUM) \
1094 && !IS_VFP_REGNUM (REGNO) \
1095 ? 1 : ARM_NUM_REGS (MODE))
1096
1097 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1098 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1099 arm_hard_regno_mode_ok ((REGNO), (MODE))
1100
1101 /* Value is 1 if it is a good idea to tie two pseudo registers
1102 when one has mode MODE1 and one has mode MODE2.
1103 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1104 for any hard reg, then this must be 0 for correct output. */
1105 #define MODES_TIEABLE_P(MODE1, MODE2) \
1106 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1107
1108 #define VALID_IWMMXT_REG_MODE(MODE) \
1109 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
1110
1111 /* Modes valid for Neon D registers. */
1112 #define VALID_NEON_DREG_MODE(MODE) \
1113 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
1114 || (MODE) == V2SFmode || (MODE) == DImode)
1115
1116 /* Modes valid for Neon Q registers. */
1117 #define VALID_NEON_QREG_MODE(MODE) \
1118 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
1119 || (MODE) == V4SFmode || (MODE) == V2DImode)
1120
1121 /* Structure modes valid for Neon registers. */
1122 #define VALID_NEON_STRUCT_MODE(MODE) \
1123 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \
1124 || (MODE) == CImode || (MODE) == XImode)
1125
1126 /* The register numbers in sequence, for passing to arm_gen_load_multiple. */
1127 extern int arm_regs_in_sequence[];
1128
1129 /* The order in which register should be allocated. It is good to use ip
1130 since no saving is required (though calls clobber it) and it never contains
1131 function parameters. It is quite good to use lr since other calls may
1132 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1133 least likely to contain a function parameter; in addition results are
1134 returned in r0.
1135 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7),
1136 then D8-D15. The reason for doing this is to attempt to reduce register
1137 pressure when both single- and double-precision registers are used in a
1138 function. */
1139
1140 #define REG_ALLOC_ORDER \
1141 { \
1142 3, 2, 1, 0, 12, 14, 4, 5, \
1143 6, 7, 8, 10, 9, 11, 13, 15, \
1144 16, 17, 18, 19, 20, 21, 22, 23, \
1145 27, 28, 29, 30, 31, 32, 33, 34, \
1146 35, 36, 37, 38, 39, 40, 41, 42, \
1147 43, 44, 45, 46, 47, 48, 49, 50, \
1148 51, 52, 53, 54, 55, 56, 57, 58, \
1149 59, 60, 61, 62, \
1150 24, 25, 26, \
1151 95, 96, 97, 98, 99, 100, 101, 102, \
1152 103, 104, 105, 106, 107, 108, 109, 110, \
1153 111, 112, 113, 114, 115, 116, 117, 118, \
1154 119, 120, 121, 122, 123, 124, 125, 126, \
1155 78, 77, 76, 75, 74, 73, 72, 71, \
1156 70, 69, 68, 67, 66, 65, 64, 63, \
1157 79, 80, 81, 82, 83, 84, 85, 86, \
1158 87, 88, 89, 90, 91, 92, 93, 94, \
1159 127 \
1160 }
1161
1162 /* Use different register alloc ordering for Thumb. */
1163 #define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc ()
1164
1165 /* Tell IRA to use the order we define rather than messing it up with its
1166 own cost calculations. */
1167 #define HONOR_REG_ALLOC_ORDER
1168
1169 /* Interrupt functions can only use registers that have already been
1170 saved by the prologue, even if they would normally be
1171 call-clobbered. */
1172 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1173 (! IS_INTERRUPT (cfun->machine->func_type) || \
1174 df_regs_ever_live_p (DST))
1175 \f
1176 /* Register and constant classes. */
1177
1178 /* Register classes: used to be simple, just all ARM regs or all FPA regs
1179 Now that the Thumb is involved it has become more complicated. */
1180 enum reg_class
1181 {
1182 NO_REGS,
1183 FPA_REGS,
1184 CIRRUS_REGS,
1185 VFP_D0_D7_REGS,
1186 VFP_LO_REGS,
1187 VFP_HI_REGS,
1188 VFP_REGS,
1189 IWMMXT_GR_REGS,
1190 IWMMXT_REGS,
1191 LO_REGS,
1192 STACK_REG,
1193 BASE_REGS,
1194 HI_REGS,
1195 CC_REG,
1196 VFPCC_REG,
1197 GENERAL_REGS,
1198 CORE_REGS,
1199 ALL_REGS,
1200 LIM_REG_CLASSES
1201 };
1202
1203 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1204
1205 /* Give names of register classes as strings for dump file. */
1206 #define REG_CLASS_NAMES \
1207 { \
1208 "NO_REGS", \
1209 "FPA_REGS", \
1210 "CIRRUS_REGS", \
1211 "VFP_D0_D7_REGS", \
1212 "VFP_LO_REGS", \
1213 "VFP_HI_REGS", \
1214 "VFP_REGS", \
1215 "IWMMXT_GR_REGS", \
1216 "IWMMXT_REGS", \
1217 "LO_REGS", \
1218 "STACK_REG", \
1219 "BASE_REGS", \
1220 "HI_REGS", \
1221 "CC_REG", \
1222 "VFPCC_REG", \
1223 "GENERAL_REGS", \
1224 "CORE_REGS", \
1225 "ALL_REGS", \
1226 }
1227
1228 /* Define which registers fit in which classes.
1229 This is an initializer for a vector of HARD_REG_SET
1230 of length N_REG_CLASSES. */
1231 #define REG_CLASS_CONTENTS \
1232 { \
1233 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1234 { 0x00FF0000, 0x00000000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
1235 { 0xF8000000, 0x000007FF, 0x00000000, 0x00000000 }, /* CIRRUS_REGS */ \
1236 { 0x00000000, 0x80000000, 0x00007FFF, 0x00000000 }, /* VFP_D0_D7_REGS */ \
1237 { 0x00000000, 0x80000000, 0x7FFFFFFF, 0x00000000 }, /* VFP_LO_REGS */ \
1238 { 0x00000000, 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_HI_REGS */ \
1239 { 0x00000000, 0x80000000, 0xFFFFFFFF, 0x7FFFFFFF }, /* VFP_REGS */ \
1240 { 0x00000000, 0x00007800, 0x00000000, 0x00000000 }, /* IWMMXT_GR_REGS */ \
1241 { 0x00000000, 0x7FFF8000, 0x00000000, 0x00000000 }, /* IWMMXT_REGS */ \
1242 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1243 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1244 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1245 { 0x0000DF00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1246 { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1247 { 0x00000000, 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
1248 { 0x0200DFFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1249 { 0x0200FFFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \
1250 { 0xFAFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
1251 }
1252
1253 /* Any of the VFP register classes. */
1254 #define IS_VFP_CLASS(X) \
1255 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \
1256 || (X) == VFP_HI_REGS || (X) == VFP_REGS)
1257
1258 /* The same information, inverted:
1259 Return the class number of the smallest class containing
1260 reg number REGNO. This could be a conditional expression
1261 or could index an array. */
1262 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1263
1264 /* The following macro defines cover classes for Integrated Register
1265 Allocator. Cover classes is a set of non-intersected register
1266 classes covering all hard registers used for register allocation
1267 purpose. Any move between two registers of a cover class should be
1268 cheaper than load or store of the registers. The macro value is
1269 array of register classes with LIM_REG_CLASSES used as the end
1270 marker. */
1271
1272 #define IRA_COVER_CLASSES \
1273 { \
1274 GENERAL_REGS, FPA_REGS, CIRRUS_REGS, VFP_REGS, IWMMXT_GR_REGS, IWMMXT_REGS,\
1275 LIM_REG_CLASSES \
1276 }
1277
1278 /* FPA registers can't do subreg as all values are reformatted to internal
1279 precision. VFP registers may only be accessed in the mode they
1280 were set. */
1281 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1282 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1283 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1284 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1285 : 0)
1286
1287 /* We need to define this for LO_REGS on thumb. Otherwise we can end up
1288 using r0-r4 for function arguments, r7 for the stack frame and don't
1289 have enough left over to do doubleword arithmetic. */
1290 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1291 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1292 || (CLASS) == CC_REG)
1293
1294 /* The class value for index registers, and the one for base regs. */
1295 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
1296 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS)
1297
1298 /* For the Thumb the high registers cannot be used as base registers
1299 when addressing quantities in QI or HI mode; if we don't know the
1300 mode, then we must be conservative. */
1301 #define MODE_BASE_REG_CLASS(MODE) \
1302 (TARGET_32BIT ? CORE_REGS : \
1303 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1304
1305 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1306 instead of BASE_REGS. */
1307 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
1308
1309 /* When this hook returns true for MODE, the compiler allows
1310 registers explicitly used in the rtl to be used as spill registers
1311 but prevents the compiler from extending the lifetime of these
1312 registers. */
1313 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
1314 arm_small_register_classes_for_mode_p
1315
1316 /* Given an rtx X being reloaded into a reg required to be
1317 in class CLASS, return the class of reg to actually use.
1318 In general this is just CLASS, but for the Thumb core registers and
1319 immediate constants we prefer a LO_REGS class or a subset. */
1320 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1321 (TARGET_32BIT ? (CLASS) : \
1322 ((CLASS) == GENERAL_REGS || (CLASS) == HI_REGS \
1323 || (CLASS) == NO_REGS || (CLASS) == STACK_REG \
1324 ? LO_REGS : (CLASS)))
1325
1326 /* Must leave BASE_REGS reloads alone */
1327 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1328 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1329 ? ((true_regnum (X) == -1 ? LO_REGS \
1330 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1331 : NO_REGS)) \
1332 : NO_REGS)
1333
1334 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1335 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1336 ? ((true_regnum (X) == -1 ? LO_REGS \
1337 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1338 : NO_REGS)) \
1339 : NO_REGS)
1340
1341 /* Return the register class of a scratch register needed to copy IN into
1342 or out of a register in CLASS in MODE. If it can be done directly,
1343 NO_REGS is returned. */
1344 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1345 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1346 ((TARGET_VFP && TARGET_HARD_FLOAT \
1347 && IS_VFP_CLASS (CLASS)) \
1348 ? coproc_secondary_reload_class (MODE, X, FALSE) \
1349 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \
1350 ? coproc_secondary_reload_class (MODE, X, TRUE) \
1351 : TARGET_32BIT \
1352 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1353 ? GENERAL_REGS : NO_REGS) \
1354 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1355
1356 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1357 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1358 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1359 ((TARGET_VFP && TARGET_HARD_FLOAT \
1360 && IS_VFP_CLASS (CLASS)) \
1361 ? coproc_secondary_reload_class (MODE, X, FALSE) : \
1362 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \
1363 coproc_secondary_reload_class (MODE, X, TRUE) : \
1364 /* Cannot load constants into Cirrus registers. */ \
1365 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1366 && (CLASS) == CIRRUS_REGS \
1367 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1368 ? GENERAL_REGS : \
1369 (TARGET_32BIT ? \
1370 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1371 && CONSTANT_P (X)) \
1372 ? GENERAL_REGS : \
1373 (((MODE) == HImode && ! arm_arch4 \
1374 && (GET_CODE (X) == MEM \
1375 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1376 && true_regnum (X) == -1))) \
1377 ? GENERAL_REGS : NO_REGS) \
1378 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1379
1380 /* Try a machine-dependent way of reloading an illegitimate address
1381 operand. If we find one, push the reload and jump to WIN. This
1382 macro is used in only one place: `find_reloads_address' in reload.c.
1383
1384 For the ARM, we wish to handle large displacements off a base
1385 register by splitting the addend across a MOV and the mem insn.
1386 This can cut the number of reloads needed. */
1387 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1388 do \
1389 { \
1390 if (GET_CODE (X) == PLUS \
1391 && GET_CODE (XEXP (X, 0)) == REG \
1392 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1393 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1394 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1395 { \
1396 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1397 HOST_WIDE_INT low, high; \
1398 \
1399 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
1400 low = ((val & 0xf) ^ 0x8) - 0x8; \
1401 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
1402 /* Need to be careful, -256 is not a valid offset. */ \
1403 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1404 else if (MODE == SImode \
1405 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1406 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1407 /* Need to be careful, -4096 is not a valid offset. */ \
1408 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1409 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1410 /* Need to be careful, -256 is not a valid offset. */ \
1411 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1412 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1413 && TARGET_HARD_FLOAT && TARGET_FPA) \
1414 /* Need to be careful, -1024 is not a valid offset. */ \
1415 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1416 else \
1417 break; \
1418 \
1419 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1420 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1421 - (unsigned HOST_WIDE_INT) 0x80000000); \
1422 /* Check for overflow or zero */ \
1423 if (low == 0 || high == 0 || (high + low != val)) \
1424 break; \
1425 \
1426 /* Reload the high part into a base reg; leave the low part \
1427 in the mem. */ \
1428 X = gen_rtx_PLUS (GET_MODE (X), \
1429 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1430 GEN_INT (high)), \
1431 GEN_INT (low)); \
1432 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1433 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1434 VOIDmode, 0, 0, OPNUM, TYPE); \
1435 goto WIN; \
1436 } \
1437 } \
1438 while (0)
1439
1440 /* XXX If an HImode FP+large_offset address is converted to an HImode
1441 SP+large_offset address, then reload won't know how to fix it. It sees
1442 only that SP isn't valid for HImode, and so reloads the SP into an index
1443 register, but the resulting address is still invalid because the offset
1444 is too big. We fix it here instead by reloading the entire address. */
1445 /* We could probably achieve better results by defining PROMOTE_MODE to help
1446 cope with the variances between the Thumb's signed and unsigned byte and
1447 halfword load instructions. */
1448 /* ??? This should be safe for thumb2, but we may be able to do better. */
1449 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
1450 do { \
1451 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
1452 if (new_x) \
1453 { \
1454 X = new_x; \
1455 goto WIN; \
1456 } \
1457 } while (0)
1458
1459 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1460 if (TARGET_ARM) \
1461 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1462 else \
1463 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1464
1465 /* Return the maximum number of consecutive registers
1466 needed to represent mode MODE in a register of class CLASS.
1467 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1468 #define CLASS_MAX_NREGS(CLASS, MODE) \
1469 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1470
1471 /* If defined, gives a class of registers that cannot be used as the
1472 operand of a SUBREG that changes the mode of the object illegally. */
1473
1474 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns.
1475 Moves between VFP_REGS and GENERAL_REGS are a single insn, but
1476 it is typically more expensive than a single memory access. We set
1477 the cost to less than two memory accesses so that floating
1478 point to integer conversion does not go through memory. */
1479 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1480 (TARGET_32BIT ? \
1481 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1482 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1483 IS_VFP_CLASS (FROM) && !IS_VFP_CLASS (TO) ? 15 : \
1484 !IS_VFP_CLASS (FROM) && IS_VFP_CLASS (TO) ? 15 : \
1485 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1486 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1487 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1488 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1489 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1490 2) \
1491 : \
1492 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1493 \f
1494 /* Stack layout; function entry, exit and calling. */
1495
1496 /* Define this if pushing a word on the stack
1497 makes the stack pointer a smaller address. */
1498 #define STACK_GROWS_DOWNWARD 1
1499
1500 /* Define this to nonzero if the nominal address of the stack frame
1501 is at the high-address end of the local variables;
1502 that is, each additional local variable allocated
1503 goes at a more negative offset in the frame. */
1504 #define FRAME_GROWS_DOWNWARD 1
1505
1506 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1507 When present, it is one word in size, and sits at the top of the frame,
1508 between the soft frame pointer and either r7 or r11.
1509
1510 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1511 and only then if some outgoing arguments are passed on the stack. It would
1512 be tempting to also check whether the stack arguments are passed by indirect
1513 calls, but there seems to be no reason in principle why a post-reload pass
1514 couldn't convert a direct call into an indirect one. */
1515 #define CALLER_INTERWORKING_SLOT_SIZE \
1516 (TARGET_CALLER_INTERWORKING \
1517 && crtl->outgoing_args_size != 0 \
1518 ? UNITS_PER_WORD : 0)
1519
1520 /* Offset within stack frame to start allocating local variables at.
1521 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1522 first local allocated. Otherwise, it is the offset to the BEGINNING
1523 of the first local allocated. */
1524 #define STARTING_FRAME_OFFSET 0
1525
1526 /* If we generate an insn to push BYTES bytes,
1527 this says how many the stack pointer really advances by. */
1528 /* The push insns do not do this rounding implicitly.
1529 So don't define this. */
1530 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1531
1532 /* Define this if the maximum size of all the outgoing args is to be
1533 accumulated and pushed during the prologue. The amount can be
1534 found in the variable crtl->outgoing_args_size. */
1535 #define ACCUMULATE_OUTGOING_ARGS 1
1536
1537 /* Offset of first parameter from the argument pointer register value. */
1538 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1539
1540 /* Define how to find the value returned by a library function
1541 assuming the value has mode MODE. */
1542 #define LIBCALL_VALUE(MODE) \
1543 (TARGET_AAPCS_BASED ? aapcs_libcall_value (MODE) \
1544 : (TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
1545 && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
1546 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1547 : TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
1548 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1549 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1550 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
1551 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1552 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1553
1554 /* 1 if REGNO is a possible register number for a function value. */
1555 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1556 ((REGNO) == ARG_REGISTER (1) \
1557 || (TARGET_AAPCS_BASED && TARGET_32BIT \
1558 && TARGET_VFP && TARGET_HARD_FLOAT \
1559 && (REGNO) == FIRST_VFP_REGNUM) \
1560 || (TARGET_32BIT && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1561 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
1562 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
1563 || (TARGET_32BIT && ((REGNO) == FIRST_FPA_REGNUM) \
1564 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
1565
1566 /* Amount of memory needed for an untyped call to save all possible return
1567 registers. */
1568 #define APPLY_RESULT_SIZE arm_apply_result_size()
1569
1570 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1571 values must be in memory. On the ARM, they need only do so if larger
1572 than a word, or if they contain elements offset from zero in the struct. */
1573 #define DEFAULT_PCC_STRUCT_RETURN 0
1574
1575 /* These bits describe the different types of function supported
1576 by the ARM backend. They are exclusive. i.e. a function cannot be both a
1577 normal function and an interworked function, for example. Knowing the
1578 type of a function is important for determining its prologue and
1579 epilogue sequences.
1580 Note value 7 is currently unassigned. Also note that the interrupt
1581 function types all have bit 2 set, so that they can be tested for easily.
1582 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1583 machine_function structure is initialized (to zero) func_type will
1584 default to unknown. This will force the first use of arm_current_func_type
1585 to call arm_compute_func_type. */
1586 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1587 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1588 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1589 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1590 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1591 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1592
1593 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1594
1595 /* In addition functions can have several type modifiers,
1596 outlined by these bit masks: */
1597 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1598 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1599 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1600 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1601 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */
1602
1603 /* Some macros to test these flags. */
1604 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1605 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1606 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1607 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1608 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1609 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN)
1610
1611
1612 /* Structure used to hold the function stack frame layout. Offsets are
1613 relative to the stack pointer on function entry. Positive offsets are
1614 in the direction of stack growth.
1615 Only soft_frame is used in thumb mode. */
1616
1617 typedef struct GTY(()) arm_stack_offsets
1618 {
1619 int saved_args; /* ARG_POINTER_REGNUM. */
1620 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1621 int saved_regs;
1622 int soft_frame; /* FRAME_POINTER_REGNUM. */
1623 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */
1624 int outgoing_args; /* STACK_POINTER_REGNUM. */
1625 unsigned int saved_regs_mask;
1626 }
1627 arm_stack_offsets;
1628
1629 #ifndef GENERATOR_FILE
1630 /* A C structure for machine-specific, per-function data.
1631 This is added to the cfun structure. */
1632 typedef struct GTY(()) machine_function
1633 {
1634 /* Additional stack adjustment in __builtin_eh_throw. */
1635 rtx eh_epilogue_sp_ofs;
1636 /* Records if LR has to be saved for far jumps. */
1637 int far_jump_used;
1638 /* Records if ARG_POINTER was ever live. */
1639 int arg_pointer_live;
1640 /* Records if the save of LR has been eliminated. */
1641 int lr_save_eliminated;
1642 /* The size of the stack frame. Only valid after reload. */
1643 arm_stack_offsets stack_offsets;
1644 /* Records the type of the current function. */
1645 unsigned long func_type;
1646 /* Record if the function has a variable argument list. */
1647 int uses_anonymous_args;
1648 /* Records if sibcalls are blocked because an argument
1649 register is needed to preserve stack alignment. */
1650 int sibcall_blocked;
1651 /* The PIC register for this function. This might be a pseudo. */
1652 rtx pic_reg;
1653 /* Labels for per-function Thumb call-via stubs. One per potential calling
1654 register. We can never call via LR or PC. We can call via SP if a
1655 trampoline happens to be on the top of the stack. */
1656 rtx call_via[14];
1657 /* Set to 1 when a return insn is output, this means that the epilogue
1658 is not needed. */
1659 int return_used_this_function;
1660 /* When outputting Thumb-1 code, record the last insn that provides
1661 information about condition codes, and the comparison operands. */
1662 rtx thumb1_cc_insn;
1663 rtx thumb1_cc_op0;
1664 rtx thumb1_cc_op1;
1665 /* Also record the CC mode that is supported. */
1666 enum machine_mode thumb1_cc_mode;
1667 }
1668 machine_function;
1669 #endif
1670
1671 /* As in the machine_function, a global set of call-via labels, for code
1672 that is in text_section. */
1673 extern GTY(()) rtx thumb_call_via_label[14];
1674
1675 /* The number of potential ways of assigning to a co-processor. */
1676 #define ARM_NUM_COPROC_SLOTS 1
1677
1678 /* Enumeration of procedure calling standard variants. We don't really
1679 support all of these yet. */
1680 enum arm_pcs
1681 {
1682 ARM_PCS_AAPCS, /* Base standard AAPCS. */
1683 ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */
1684 ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */
1685 /* This must be the last AAPCS variant. */
1686 ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */
1687 ARM_PCS_ATPCS, /* ATPCS. */
1688 ARM_PCS_APCS, /* APCS (legacy Linux etc). */
1689 ARM_PCS_UNKNOWN
1690 };
1691
1692 /* Default procedure calling standard of current compilation unit. */
1693 extern enum arm_pcs arm_pcs_default;
1694
1695 /* A C type for declaring a variable that is used as the first argument of
1696 `FUNCTION_ARG' and other related values. */
1697 typedef struct
1698 {
1699 /* This is the number of registers of arguments scanned so far. */
1700 int nregs;
1701 /* This is the number of iWMMXt register arguments scanned so far. */
1702 int iwmmxt_nregs;
1703 int named_count;
1704 int nargs;
1705 /* Which procedure call variant to use for this call. */
1706 enum arm_pcs pcs_variant;
1707
1708 /* AAPCS related state tracking. */
1709 int aapcs_arg_processed; /* No need to lay out this argument again. */
1710 int aapcs_cprc_slot; /* Index of co-processor rules to handle
1711 this argument, or -1 if using core
1712 registers. */
1713 int aapcs_ncrn;
1714 int aapcs_next_ncrn;
1715 rtx aapcs_reg; /* Register assigned to this argument. */
1716 int aapcs_partial; /* How many bytes are passed in regs (if
1717 split between core regs and stack.
1718 Zero otherwise. */
1719 int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS];
1720 int can_split; /* Argument can be split between core regs
1721 and the stack. */
1722 /* Private data for tracking VFP register allocation */
1723 unsigned aapcs_vfp_regs_free;
1724 unsigned aapcs_vfp_reg_alloc;
1725 int aapcs_vfp_rcount;
1726 MACHMODE aapcs_vfp_rmode;
1727 } CUMULATIVE_ARGS;
1728
1729 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1730 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1731
1732 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1733 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1734
1735 /* For AAPCS, padding should never be below the argument. For other ABIs,
1736 * mimic the default. */
1737 #define PAD_VARARGS_DOWN \
1738 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1739
1740 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1741 for a call to a function whose data type is FNTYPE.
1742 For a library call, FNTYPE is 0.
1743 On the ARM, the offset starts at 0. */
1744 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1745 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1746
1747 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1748 argument with the specified mode and type. If it is not defined,
1749 `PARM_BOUNDARY' is used for all arguments. */
1750 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1751 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1752 ? DOUBLEWORD_ALIGNMENT \
1753 : PARM_BOUNDARY )
1754
1755 /* 1 if N is a possible register number for function argument passing.
1756 On the ARM, r0-r3 are used to pass args. */
1757 #define FUNCTION_ARG_REGNO_P(REGNO) \
1758 (IN_RANGE ((REGNO), 0, 3) \
1759 || (TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT \
1760 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \
1761 || (TARGET_IWMMXT_ABI \
1762 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1763
1764 \f
1765 /* If your target environment doesn't prefix user functions with an
1766 underscore, you may wish to re-define this to prevent any conflicts. */
1767 #ifndef ARM_MCOUNT_NAME
1768 #define ARM_MCOUNT_NAME "*mcount"
1769 #endif
1770
1771 /* Call the function profiler with a given profile label. The Acorn
1772 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1773 On the ARM the full profile code will look like:
1774 .data
1775 LP1
1776 .word 0
1777 .text
1778 mov ip, lr
1779 bl mcount
1780 .word LP1
1781
1782 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1783 will output the .text section.
1784
1785 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1786 ``prof'' doesn't seem to mind about this!
1787
1788 Note - this version of the code is designed to work in both ARM and
1789 Thumb modes. */
1790 #ifndef ARM_FUNCTION_PROFILER
1791 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1792 { \
1793 char temp[20]; \
1794 rtx sym; \
1795 \
1796 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1797 IP_REGNUM, LR_REGNUM); \
1798 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1799 fputc ('\n', STREAM); \
1800 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1801 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1802 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1803 }
1804 #endif
1805
1806 #ifdef THUMB_FUNCTION_PROFILER
1807 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1808 if (TARGET_ARM) \
1809 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1810 else \
1811 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1812 #else
1813 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1814 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1815 #endif
1816
1817 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1818 the stack pointer does not matter. The value is tested only in
1819 functions that have frame pointers.
1820 No definition is equivalent to always zero.
1821
1822 On the ARM, the function epilogue recovers the stack pointer from the
1823 frame. */
1824 #define EXIT_IGNORE_STACK 1
1825
1826 #define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNUM)
1827
1828 /* Determine if the epilogue should be output as RTL.
1829 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1830 #define USE_RETURN_INSN(ISCOND) \
1831 (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0)
1832
1833 /* Definitions for register eliminations.
1834
1835 This is an array of structures. Each structure initializes one pair
1836 of eliminable registers. The "from" register number is given first,
1837 followed by "to". Eliminations of the same "from" register are listed
1838 in order of preference.
1839
1840 We have two registers that can be eliminated on the ARM. First, the
1841 arg pointer register can often be eliminated in favor of the stack
1842 pointer register. Secondly, the pseudo frame pointer register can always
1843 be eliminated; it is replaced with either the stack or the real frame
1844 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1845 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1846
1847 #define ELIMINABLE_REGS \
1848 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1849 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1850 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1851 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1852 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1853 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1854 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1855
1856 /* Define the offset between two registers, one to be eliminated, and the
1857 other its replacement, at the start of a routine. */
1858 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1859 if (TARGET_ARM) \
1860 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1861 else \
1862 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1863
1864 /* Special case handling of the location of arguments passed on the stack. */
1865 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1866
1867 /* Initialize data used by insn expanders. This is called from insn_emit,
1868 once for every function before code is generated. */
1869 #define INIT_EXPANDERS arm_init_expanders ()
1870
1871 /* Length in units of the trampoline for entering a nested function. */
1872 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20)
1873
1874 /* Alignment required for a trampoline in bits. */
1875 #define TRAMPOLINE_ALIGNMENT 32
1876 \f
1877 /* Addressing modes, and classification of registers for them. */
1878 #define HAVE_POST_INCREMENT 1
1879 #define HAVE_PRE_INCREMENT TARGET_32BIT
1880 #define HAVE_POST_DECREMENT TARGET_32BIT
1881 #define HAVE_PRE_DECREMENT TARGET_32BIT
1882 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT
1883 #define HAVE_POST_MODIFY_DISP TARGET_32BIT
1884 #define HAVE_PRE_MODIFY_REG TARGET_32BIT
1885 #define HAVE_POST_MODIFY_REG TARGET_32BIT
1886
1887 /* Macros to check register numbers against specific register classes. */
1888
1889 /* These assume that REGNO is a hard or pseudo reg number.
1890 They give nonzero only if REGNO is a hard reg of the suitable class
1891 or a pseudo reg currently allocated to a suitable hard reg.
1892 Since they use reg_renumber, they are safe only once reg_renumber
1893 has been allocated, which happens in local-alloc.c. */
1894 #define TEST_REGNO(R, TEST, VALUE) \
1895 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1896
1897 /* Don't allow the pc to be used. */
1898 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1899 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1900 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1901 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1902
1903 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1904 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1905 || (GET_MODE_SIZE (MODE) >= 4 \
1906 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1907
1908 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1909 (TARGET_THUMB1 \
1910 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1911 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1912
1913 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1914 For Thumb, we can not use SP + reg, so reject SP. */
1915 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1916 REGNO_MODE_OK_FOR_BASE_P (X, QImode)
1917
1918 /* For ARM code, we don't care about the mode, but for Thumb, the index
1919 must be suitable for use in a QImode load. */
1920 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1921 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \
1922 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))
1923
1924 /* Maximum number of registers that can appear in a valid memory address.
1925 Shifts in addresses can't be by a register. */
1926 #define MAX_REGS_PER_ADDRESS 2
1927
1928 /* Recognize any constant value that is a valid address. */
1929 /* XXX We can address any constant, eventually... */
1930 /* ??? Should the TARGET_ARM here also apply to thumb2? */
1931 #define CONSTANT_ADDRESS_P(X) \
1932 (GET_CODE (X) == SYMBOL_REF \
1933 && (CONSTANT_POOL_ADDRESS_P (X) \
1934 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1935
1936 /* True if SYMBOL + OFFSET constants must refer to something within
1937 SYMBOL's section. */
1938 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0
1939
1940 /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */
1941 #ifndef TARGET_DEFAULT_WORD_RELOCATIONS
1942 #define TARGET_DEFAULT_WORD_RELOCATIONS 0
1943 #endif
1944
1945 /* Nonzero if the constant value X is a legitimate general operand.
1946 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1947
1948 On the ARM, allow any integer (invalid ones are removed later by insn
1949 patterns), nice doubles and symbol_refs which refer to the function's
1950 constant pool XXX.
1951
1952 When generating pic allow anything. */
1953 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1954
1955 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
1956 ( GET_CODE (X) == CONST_INT \
1957 || GET_CODE (X) == CONST_DOUBLE \
1958 || CONSTANT_ADDRESS_P (X) \
1959 || flag_pic)
1960
1961 #define LEGITIMATE_CONSTANT_P(X) \
1962 (!arm_cannot_force_const_mem (X) \
1963 && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X) \
1964 : THUMB_LEGITIMATE_CONSTANT_P (X)))
1965
1966 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1967 #define SUBTARGET_NAME_ENCODING_LENGTHS
1968 #endif
1969
1970 /* This is a C fragment for the inside of a switch statement.
1971 Each case label should return the number of characters to
1972 be stripped from the start of a function's name, if that
1973 name starts with the indicated character. */
1974 #define ARM_NAME_ENCODING_LENGTHS \
1975 case '*': return 1; \
1976 SUBTARGET_NAME_ENCODING_LENGTHS
1977
1978 /* This is how to output a reference to a user-level label named NAME.
1979 `assemble_name' uses this. */
1980 #undef ASM_OUTPUT_LABELREF
1981 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1982 arm_asm_output_labelref (FILE, NAME)
1983
1984 /* Output IT instructions for conditionally executed Thumb-2 instructions. */
1985 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
1986 if (TARGET_THUMB2) \
1987 thumb2_asm_output_opcode (STREAM);
1988
1989 /* The EABI specifies that constructors should go in .init_array.
1990 Other targets use .ctors for compatibility. */
1991 #ifndef ARM_EABI_CTORS_SECTION_OP
1992 #define ARM_EABI_CTORS_SECTION_OP \
1993 "\t.section\t.init_array,\"aw\",%init_array"
1994 #endif
1995 #ifndef ARM_EABI_DTORS_SECTION_OP
1996 #define ARM_EABI_DTORS_SECTION_OP \
1997 "\t.section\t.fini_array,\"aw\",%fini_array"
1998 #endif
1999 #define ARM_CTORS_SECTION_OP \
2000 "\t.section\t.ctors,\"aw\",%progbits"
2001 #define ARM_DTORS_SECTION_OP \
2002 "\t.section\t.dtors,\"aw\",%progbits"
2003
2004 /* Define CTORS_SECTION_ASM_OP. */
2005 #undef CTORS_SECTION_ASM_OP
2006 #undef DTORS_SECTION_ASM_OP
2007 #ifndef IN_LIBGCC2
2008 # define CTORS_SECTION_ASM_OP \
2009 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
2010 # define DTORS_SECTION_ASM_OP \
2011 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
2012 #else /* !defined (IN_LIBGCC2) */
2013 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
2014 so we cannot use the definition above. */
2015 # ifdef __ARM_EABI__
2016 /* The .ctors section is not part of the EABI, so we do not define
2017 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
2018 from trying to use it. We do define it when doing normal
2019 compilation, as .init_array can be used instead of .ctors. */
2020 /* There is no need to emit begin or end markers when using
2021 init_array; the dynamic linker will compute the size of the
2022 array itself based on special symbols created by the static
2023 linker. However, we do need to arrange to set up
2024 exception-handling here. */
2025 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
2026 # define CTOR_LIST_END /* empty */
2027 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
2028 # define DTOR_LIST_END /* empty */
2029 # else /* !defined (__ARM_EABI__) */
2030 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
2031 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
2032 # endif /* !defined (__ARM_EABI__) */
2033 #endif /* !defined (IN_LIBCC2) */
2034
2035 /* True if the operating system can merge entities with vague linkage
2036 (e.g., symbols in COMDAT group) during dynamic linking. */
2037 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
2038 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
2039 #endif
2040
2041 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
2042
2043 #ifdef TARGET_UNWIND_INFO
2044 #define ARM_EABI_UNWIND_TABLES \
2045 ((!USING_SJLJ_EXCEPTIONS && flag_exceptions) || flag_unwind_tables)
2046 #else
2047 #define ARM_EABI_UNWIND_TABLES 0
2048 #endif
2049
2050 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2051 and check its validity for a certain class.
2052 We have two alternate definitions for each of them.
2053 The usual definition accepts all pseudo regs; the other rejects
2054 them unless they have been allocated suitable hard regs.
2055 The symbol REG_OK_STRICT causes the latter definition to be used.
2056 Thumb-2 has the same restrictions as arm. */
2057 #ifndef REG_OK_STRICT
2058
2059 #define ARM_REG_OK_FOR_BASE_P(X) \
2060 (REGNO (X) <= LAST_ARM_REGNUM \
2061 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2062 || REGNO (X) == FRAME_POINTER_REGNUM \
2063 || REGNO (X) == ARG_POINTER_REGNUM)
2064
2065 #define ARM_REG_OK_FOR_INDEX_P(X) \
2066 ((REGNO (X) <= LAST_ARM_REGNUM \
2067 && REGNO (X) != STACK_POINTER_REGNUM) \
2068 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2069 || REGNO (X) == FRAME_POINTER_REGNUM \
2070 || REGNO (X) == ARG_POINTER_REGNUM)
2071
2072 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2073 (REGNO (X) <= LAST_LO_REGNUM \
2074 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2075 || (GET_MODE_SIZE (MODE) >= 4 \
2076 && (REGNO (X) == STACK_POINTER_REGNUM \
2077 || (X) == hard_frame_pointer_rtx \
2078 || (X) == arg_pointer_rtx)))
2079
2080 #define REG_STRICT_P 0
2081
2082 #else /* REG_OK_STRICT */
2083
2084 #define ARM_REG_OK_FOR_BASE_P(X) \
2085 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2086
2087 #define ARM_REG_OK_FOR_INDEX_P(X) \
2088 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X))
2089
2090 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2091 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2092
2093 #define REG_STRICT_P 1
2094
2095 #endif /* REG_OK_STRICT */
2096
2097 /* Now define some helpers in terms of the above. */
2098
2099 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2100 (TARGET_THUMB1 \
2101 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2102 : ARM_REG_OK_FOR_BASE_P (X))
2103
2104 /* For 16-bit Thumb, a valid index register is anything that can be used in
2105 a byte load instruction. */
2106 #define THUMB1_REG_OK_FOR_INDEX_P(X) \
2107 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode)
2108
2109 /* Nonzero if X is a hard reg that can be used as an index
2110 or if it is a pseudo reg. On the Thumb, the stack pointer
2111 is not suitable. */
2112 #define REG_OK_FOR_INDEX_P(X) \
2113 (TARGET_THUMB1 \
2114 ? THUMB1_REG_OK_FOR_INDEX_P (X) \
2115 : ARM_REG_OK_FOR_INDEX_P (X))
2116
2117 /* Nonzero if X can be the base register in a reg+reg addressing mode.
2118 For Thumb, we can not use SP + reg, so reject SP. */
2119 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2120 REG_OK_FOR_INDEX_P (X)
2121 \f
2122 #define ARM_BASE_REGISTER_RTX_P(X) \
2123 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2124
2125 #define ARM_INDEX_REGISTER_RTX_P(X) \
2126 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2127 \f
2128 /* Define this for compatibility reasons. */
2129 #define HANDLE_PRAGMA_PACK_PUSH_POP
2130
2131 /* Specify the machine mode that this machine uses
2132 for the index in the tablejump instruction. */
2133 #define CASE_VECTOR_MODE Pmode
2134
2135 #define CASE_VECTOR_PC_RELATIVE (TARGET_THUMB2 \
2136 || (TARGET_THUMB1 \
2137 && (optimize_size || flag_pic)))
2138
2139 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \
2140 (TARGET_THUMB1 \
2141 ? (min >= 0 && max < 512 \
2142 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \
2143 : min >= -256 && max < 256 \
2144 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \
2145 : min >= 0 && max < 8192 \
2146 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \
2147 : min >= -4096 && max < 4096 \
2148 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \
2149 : SImode) \
2150 : ((min < 0 || max >= 0x2000 || !TARGET_THUMB2) ? SImode \
2151 : (max >= 0x200) ? HImode \
2152 : QImode))
2153
2154 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2155 unsigned is probably best, but may break some code. */
2156 #ifndef DEFAULT_SIGNED_CHAR
2157 #define DEFAULT_SIGNED_CHAR 0
2158 #endif
2159
2160 /* Max number of bytes we can move from memory to memory
2161 in one reasonably fast instruction. */
2162 #define MOVE_MAX 4
2163
2164 #undef MOVE_RATIO
2165 #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2)
2166
2167 /* Define if operations between registers always perform the operation
2168 on the full register even if a narrower mode is specified. */
2169 #define WORD_REGISTER_OPERATIONS
2170
2171 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2172 will either zero-extend or sign-extend. The value of this macro should
2173 be the code that says which one of the two operations is implicitly
2174 done, UNKNOWN if none. */
2175 #define LOAD_EXTEND_OP(MODE) \
2176 (TARGET_THUMB ? ZERO_EXTEND : \
2177 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2178 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
2179
2180 /* Nonzero if access to memory by bytes is slow and undesirable. */
2181 #define SLOW_BYTE_ACCESS 0
2182
2183 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2184
2185 /* Immediate shift counts are truncated by the output routines (or was it
2186 the assembler?). Shift counts in a register are truncated by ARM. Note
2187 that the native compiler puts too large (> 32) immediate shift counts
2188 into a register and shifts by the register, letting the ARM decide what
2189 to do instead of doing that itself. */
2190 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2191 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2192 On the arm, Y in a register is used modulo 256 for the shift. Only for
2193 rotates is modulo 32 used. */
2194 /* #define SHIFT_COUNT_TRUNCATED 1 */
2195
2196 /* All integers have the same format so truncation is easy. */
2197 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2198
2199 /* Calling from registers is a massive pain. */
2200 #define NO_FUNCTION_CSE 1
2201
2202 /* The machine modes of pointers and functions */
2203 #define Pmode SImode
2204 #define FUNCTION_MODE Pmode
2205
2206 #define ARM_FRAME_RTX(X) \
2207 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2208 || (X) == arg_pointer_rtx)
2209
2210 /* Moves to and from memory are quite expensive */
2211 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2212 (TARGET_32BIT ? 10 : \
2213 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2214 * (CLASS == LO_REGS ? 1 : 2)))
2215
2216 /* Try to generate sequences that don't involve branches, we can then use
2217 conditional instructions */
2218 #define BRANCH_COST(speed_p, predictable_p) \
2219 (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0))
2220 \f
2221 /* Position Independent Code. */
2222 /* We decide which register to use based on the compilation options and
2223 the assembler in use; this is more general than the APCS restriction of
2224 using sb (r9) all the time. */
2225 extern unsigned arm_pic_register;
2226
2227 /* The register number of the register used to address a table of static
2228 data addresses in memory. */
2229 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2230
2231 /* We can't directly access anything that contains a symbol,
2232 nor can we indirect via the constant pool. One exception is
2233 UNSPEC_TLS, which is always PIC. */
2234 #define LEGITIMATE_PIC_OPERAND_P(X) \
2235 (!(symbol_mentioned_p (X) \
2236 || label_mentioned_p (X) \
2237 || (GET_CODE (X) == SYMBOL_REF \
2238 && CONSTANT_POOL_ADDRESS_P (X) \
2239 && (symbol_mentioned_p (get_pool_constant (X)) \
2240 || label_mentioned_p (get_pool_constant (X))))) \
2241 || tls_mentioned_p (X))
2242
2243 /* We need to know when we are making a constant pool; this determines
2244 whether data needs to be in the GOT or can be referenced via a GOT
2245 offset. */
2246 extern int making_const_table;
2247 \f
2248 /* Handle pragmas for compatibility with Intel's compilers. */
2249 /* Also abuse this to register additional C specific EABI attributes. */
2250 #define REGISTER_TARGET_PRAGMAS() do { \
2251 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2252 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2253 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2254 arm_lang_object_attributes_init(); \
2255 } while (0)
2256
2257 /* Condition code information. */
2258 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2259 return the mode to be used for the comparison. */
2260
2261 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2262
2263 #define REVERSIBLE_CC_MODE(MODE) 1
2264
2265 #define REVERSE_CONDITION(CODE,MODE) \
2266 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2267 ? reverse_condition_maybe_unordered (code) \
2268 : reverse_condition (code))
2269
2270 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2271 (CODE) = arm_canonicalize_comparison (CODE, &(OP0), &(OP1))
2272
2273 /* The arm5 clz instruction returns 32. */
2274 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2275 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2276 \f
2277 #define CC_STATUS_INIT \
2278 do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0)
2279
2280 #undef ASM_APP_OFF
2281 #define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \
2282 TARGET_THUMB2 ? "\t.thumb\n" : "")
2283
2284 /* Output a push or a pop instruction (only used when profiling).
2285 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know
2286 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and
2287 that r7 isn't used by the function profiler, so we can use it as a
2288 scratch reg. WARNING: This isn't safe in the general case! It may be
2289 sensitive to future changes in final.c:profile_function. */
2290 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2291 do \
2292 { \
2293 if (TARGET_ARM) \
2294 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2295 STACK_POINTER_REGNUM, REGNO); \
2296 else if (TARGET_THUMB1 \
2297 && (REGNO) == STATIC_CHAIN_REGNUM) \
2298 { \
2299 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \
2300 asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\
2301 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \
2302 } \
2303 else \
2304 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2305 } while (0)
2306
2307
2308 /* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */
2309 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2310 do \
2311 { \
2312 if (TARGET_ARM) \
2313 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2314 STACK_POINTER_REGNUM, REGNO); \
2315 else if (TARGET_THUMB1 \
2316 && (REGNO) == STATIC_CHAIN_REGNUM) \
2317 { \
2318 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \
2319 asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\
2320 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \
2321 } \
2322 else \
2323 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2324 } while (0)
2325
2326 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */
2327 #define ADDR_VEC_ALIGN(JUMPTABLE) 0
2328
2329 /* This is how to output a label which precedes a jumptable. Since
2330 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2331 #undef ASM_OUTPUT_CASE_LABEL
2332 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2333 do \
2334 { \
2335 if (TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) \
2336 ASM_OUTPUT_ALIGN (FILE, 2); \
2337 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2338 } \
2339 while (0)
2340
2341 /* Make sure subsequent insns are aligned after a TBB. */
2342 #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \
2343 do \
2344 { \
2345 if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \
2346 ASM_OUTPUT_ALIGN (FILE, 1); \
2347 } \
2348 while (0)
2349
2350 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2351 do \
2352 { \
2353 if (TARGET_THUMB) \
2354 { \
2355 if (is_called_in_ARM_mode (DECL) \
2356 || (TARGET_THUMB1 && !TARGET_THUMB1_ONLY \
2357 && cfun->is_thunk)) \
2358 fprintf (STREAM, "\t.code 32\n") ; \
2359 else if (TARGET_THUMB1) \
2360 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \
2361 else \
2362 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \
2363 } \
2364 if (TARGET_POKE_FUNCTION_NAME) \
2365 arm_poke_function_name (STREAM, (const char *) NAME); \
2366 } \
2367 while (0)
2368
2369 /* For aliases of functions we use .thumb_set instead. */
2370 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2371 do \
2372 { \
2373 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2374 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2375 \
2376 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2377 { \
2378 fprintf (FILE, "\t.thumb_set "); \
2379 assemble_name (FILE, LABEL1); \
2380 fprintf (FILE, ","); \
2381 assemble_name (FILE, LABEL2); \
2382 fprintf (FILE, "\n"); \
2383 } \
2384 else \
2385 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2386 } \
2387 while (0)
2388
2389 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2390 /* To support -falign-* switches we need to use .p2align so
2391 that alignment directives in code sections will be padded
2392 with no-op instructions, rather than zeroes. */
2393 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2394 if ((LOG) != 0) \
2395 { \
2396 if ((MAX_SKIP) == 0) \
2397 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2398 else \
2399 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2400 (int) (LOG), (int) (MAX_SKIP)); \
2401 }
2402 #endif
2403 \f
2404 /* Add two bytes to the length of conditionally executed Thumb-2
2405 instructions for the IT instruction. */
2406 #define ADJUST_INSN_LENGTH(insn, length) \
2407 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \
2408 length += 2;
2409
2410 /* Only perform branch elimination (by making instructions conditional) if
2411 we're optimizing. For Thumb-2 check if any IT instructions need
2412 outputting. */
2413 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2414 if (TARGET_ARM && optimize) \
2415 arm_final_prescan_insn (INSN); \
2416 else if (TARGET_THUMB2) \
2417 thumb2_final_prescan_insn (INSN); \
2418 else if (TARGET_THUMB1) \
2419 thumb1_final_prescan_insn (INSN)
2420
2421 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2422 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2423 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2424 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2425 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2426 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2427 : 0))))
2428
2429 #define OUTPUT_ADDR_CONST_EXTRA(file, x, fail) \
2430 if (arm_output_addr_const_extra (file, x) == FALSE) \
2431 goto fail
2432
2433 /* A C expression whose value is RTL representing the value of the return
2434 address for the frame COUNT steps up from the current frame. */
2435
2436 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2437 arm_return_addr (COUNT, FRAME)
2438
2439 /* Mask of the bits in the PC that contain the real return address
2440 when running in 26-bit mode. */
2441 #define RETURN_ADDR_MASK26 (0x03fffffc)
2442
2443 /* Pick up the return address upon entry to a procedure. Used for
2444 dwarf2 unwind information. This also enables the table driven
2445 mechanism. */
2446 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2447 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2448
2449 /* Used to mask out junk bits from the return address, such as
2450 processor state, interrupt status, condition codes and the like. */
2451 #define MASK_RETURN_ADDR \
2452 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2453 in 26 bit mode, the condition codes must be masked out of the \
2454 return address. This does not apply to ARM6 and later processors \
2455 when running in 32 bit mode. */ \
2456 ((arm_arch4 || TARGET_THUMB) \
2457 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2458 : arm_gen_return_addr_mask ())
2459
2460 \f
2461 /* Neon defines builtins from ARM_BUILTIN_MAX upwards, though they don't have
2462 symbolic names defined here (which would require too much duplication).
2463 FIXME? */
2464 enum arm_builtins
2465 {
2466 ARM_BUILTIN_GETWCX,
2467 ARM_BUILTIN_SETWCX,
2468
2469 ARM_BUILTIN_WZERO,
2470
2471 ARM_BUILTIN_WAVG2BR,
2472 ARM_BUILTIN_WAVG2HR,
2473 ARM_BUILTIN_WAVG2B,
2474 ARM_BUILTIN_WAVG2H,
2475
2476 ARM_BUILTIN_WACCB,
2477 ARM_BUILTIN_WACCH,
2478 ARM_BUILTIN_WACCW,
2479
2480 ARM_BUILTIN_WMACS,
2481 ARM_BUILTIN_WMACSZ,
2482 ARM_BUILTIN_WMACU,
2483 ARM_BUILTIN_WMACUZ,
2484
2485 ARM_BUILTIN_WSADB,
2486 ARM_BUILTIN_WSADBZ,
2487 ARM_BUILTIN_WSADH,
2488 ARM_BUILTIN_WSADHZ,
2489
2490 ARM_BUILTIN_WALIGN,
2491
2492 ARM_BUILTIN_TMIA,
2493 ARM_BUILTIN_TMIAPH,
2494 ARM_BUILTIN_TMIABB,
2495 ARM_BUILTIN_TMIABT,
2496 ARM_BUILTIN_TMIATB,
2497 ARM_BUILTIN_TMIATT,
2498
2499 ARM_BUILTIN_TMOVMSKB,
2500 ARM_BUILTIN_TMOVMSKH,
2501 ARM_BUILTIN_TMOVMSKW,
2502
2503 ARM_BUILTIN_TBCSTB,
2504 ARM_BUILTIN_TBCSTH,
2505 ARM_BUILTIN_TBCSTW,
2506
2507 ARM_BUILTIN_WMADDS,
2508 ARM_BUILTIN_WMADDU,
2509
2510 ARM_BUILTIN_WPACKHSS,
2511 ARM_BUILTIN_WPACKWSS,
2512 ARM_BUILTIN_WPACKDSS,
2513 ARM_BUILTIN_WPACKHUS,
2514 ARM_BUILTIN_WPACKWUS,
2515 ARM_BUILTIN_WPACKDUS,
2516
2517 ARM_BUILTIN_WADDB,
2518 ARM_BUILTIN_WADDH,
2519 ARM_BUILTIN_WADDW,
2520 ARM_BUILTIN_WADDSSB,
2521 ARM_BUILTIN_WADDSSH,
2522 ARM_BUILTIN_WADDSSW,
2523 ARM_BUILTIN_WADDUSB,
2524 ARM_BUILTIN_WADDUSH,
2525 ARM_BUILTIN_WADDUSW,
2526 ARM_BUILTIN_WSUBB,
2527 ARM_BUILTIN_WSUBH,
2528 ARM_BUILTIN_WSUBW,
2529 ARM_BUILTIN_WSUBSSB,
2530 ARM_BUILTIN_WSUBSSH,
2531 ARM_BUILTIN_WSUBSSW,
2532 ARM_BUILTIN_WSUBUSB,
2533 ARM_BUILTIN_WSUBUSH,
2534 ARM_BUILTIN_WSUBUSW,
2535
2536 ARM_BUILTIN_WAND,
2537 ARM_BUILTIN_WANDN,
2538 ARM_BUILTIN_WOR,
2539 ARM_BUILTIN_WXOR,
2540
2541 ARM_BUILTIN_WCMPEQB,
2542 ARM_BUILTIN_WCMPEQH,
2543 ARM_BUILTIN_WCMPEQW,
2544 ARM_BUILTIN_WCMPGTUB,
2545 ARM_BUILTIN_WCMPGTUH,
2546 ARM_BUILTIN_WCMPGTUW,
2547 ARM_BUILTIN_WCMPGTSB,
2548 ARM_BUILTIN_WCMPGTSH,
2549 ARM_BUILTIN_WCMPGTSW,
2550
2551 ARM_BUILTIN_TEXTRMSB,
2552 ARM_BUILTIN_TEXTRMSH,
2553 ARM_BUILTIN_TEXTRMSW,
2554 ARM_BUILTIN_TEXTRMUB,
2555 ARM_BUILTIN_TEXTRMUH,
2556 ARM_BUILTIN_TEXTRMUW,
2557 ARM_BUILTIN_TINSRB,
2558 ARM_BUILTIN_TINSRH,
2559 ARM_BUILTIN_TINSRW,
2560
2561 ARM_BUILTIN_WMAXSW,
2562 ARM_BUILTIN_WMAXSH,
2563 ARM_BUILTIN_WMAXSB,
2564 ARM_BUILTIN_WMAXUW,
2565 ARM_BUILTIN_WMAXUH,
2566 ARM_BUILTIN_WMAXUB,
2567 ARM_BUILTIN_WMINSW,
2568 ARM_BUILTIN_WMINSH,
2569 ARM_BUILTIN_WMINSB,
2570 ARM_BUILTIN_WMINUW,
2571 ARM_BUILTIN_WMINUH,
2572 ARM_BUILTIN_WMINUB,
2573
2574 ARM_BUILTIN_WMULUM,
2575 ARM_BUILTIN_WMULSM,
2576 ARM_BUILTIN_WMULUL,
2577
2578 ARM_BUILTIN_PSADBH,
2579 ARM_BUILTIN_WSHUFH,
2580
2581 ARM_BUILTIN_WSLLH,
2582 ARM_BUILTIN_WSLLW,
2583 ARM_BUILTIN_WSLLD,
2584 ARM_BUILTIN_WSRAH,
2585 ARM_BUILTIN_WSRAW,
2586 ARM_BUILTIN_WSRAD,
2587 ARM_BUILTIN_WSRLH,
2588 ARM_BUILTIN_WSRLW,
2589 ARM_BUILTIN_WSRLD,
2590 ARM_BUILTIN_WRORH,
2591 ARM_BUILTIN_WRORW,
2592 ARM_BUILTIN_WRORD,
2593 ARM_BUILTIN_WSLLHI,
2594 ARM_BUILTIN_WSLLWI,
2595 ARM_BUILTIN_WSLLDI,
2596 ARM_BUILTIN_WSRAHI,
2597 ARM_BUILTIN_WSRAWI,
2598 ARM_BUILTIN_WSRADI,
2599 ARM_BUILTIN_WSRLHI,
2600 ARM_BUILTIN_WSRLWI,
2601 ARM_BUILTIN_WSRLDI,
2602 ARM_BUILTIN_WRORHI,
2603 ARM_BUILTIN_WRORWI,
2604 ARM_BUILTIN_WRORDI,
2605
2606 ARM_BUILTIN_WUNPCKIHB,
2607 ARM_BUILTIN_WUNPCKIHH,
2608 ARM_BUILTIN_WUNPCKIHW,
2609 ARM_BUILTIN_WUNPCKILB,
2610 ARM_BUILTIN_WUNPCKILH,
2611 ARM_BUILTIN_WUNPCKILW,
2612
2613 ARM_BUILTIN_WUNPCKEHSB,
2614 ARM_BUILTIN_WUNPCKEHSH,
2615 ARM_BUILTIN_WUNPCKEHSW,
2616 ARM_BUILTIN_WUNPCKEHUB,
2617 ARM_BUILTIN_WUNPCKEHUH,
2618 ARM_BUILTIN_WUNPCKEHUW,
2619 ARM_BUILTIN_WUNPCKELSB,
2620 ARM_BUILTIN_WUNPCKELSH,
2621 ARM_BUILTIN_WUNPCKELSW,
2622 ARM_BUILTIN_WUNPCKELUB,
2623 ARM_BUILTIN_WUNPCKELUH,
2624 ARM_BUILTIN_WUNPCKELUW,
2625
2626 ARM_BUILTIN_THREAD_POINTER,
2627
2628 ARM_BUILTIN_NEON_BASE,
2629
2630 ARM_BUILTIN_MAX = ARM_BUILTIN_NEON_BASE /* FIXME: Wrong! */
2631 };
2632
2633 /* Do not emit .note.GNU-stack by default. */
2634 #ifndef NEED_INDICATE_EXEC_STACK
2635 #define NEED_INDICATE_EXEC_STACK 0
2636 #endif
2637
2638 /* The maximum number of parallel loads or stores we support in an ldm/stm
2639 instruction. */
2640 #define MAX_LDM_STM_OPS 4
2641
2642 #endif /* ! GCC_ARM_H */
Mirror of https://gcc.gnu.org/git/gcc.git