1 ;;- Machine description for ARM for GNU compiler
2 ;; Copyright (C) 1991-2019 Free Software Foundation, Inc.
3 ;; Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 ;; and Martin Simmons (@harleqn.co.uk).
5 ;; More major hacks by Richard Earnshaw (rearnsha@arm.com).
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it
10 ;; under the terms of the GNU General Public License as published
11 ;; by the Free Software Foundation; either version 3, or (at your
12 ;; option) any later version.
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
15 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 ;; License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
26 ;;---------------------------------------------------------------------------
29 ;; Register numbers -- All machine registers should be defined here
31 [(R0_REGNUM 0) ; First CORE register
32 (R1_REGNUM 1) ; Second CORE register
33 (R4_REGNUM 4) ; Fifth CORE register
34 (FDPIC_REGNUM 9) ; FDPIC register
35 (IP_REGNUM 12) ; Scratch register
36 (SP_REGNUM 13) ; Stack pointer
37 (LR_REGNUM 14) ; Return address register
38 (PC_REGNUM 15) ; Program counter
39 (LAST_ARM_REGNUM 15) ;
40 (CC_REGNUM 100) ; Condition code pseudo register
41 (VFPCC_REGNUM 101) ; VFP Condition code pseudo register
44 ;; 3rd operand to select_dominance_cc_mode
51 ;; conditional compare combination
62 ;;---------------------------------------------------------------------------
65 ;; Processor type. This is created automatically from arm-cores.def.
66 (include "arm-tune.md")
68 ;; Instruction classification types
71 ; IS_THUMB is set to 'yes' when we are generating Thumb code, and 'no' when
72 ; generating ARM code. This is used to control the length of some insn
73 ; patterns that share the same RTL in both ARM and Thumb code.
74 (define_attr "is_thumb" "yes,no"
75 (const (if_then_else (symbol_ref "TARGET_THUMB")
76 (const_string "yes") (const_string "no"))))
78 ; IS_ARCH6 is set to 'yes' when we are generating code form ARMv6.
79 (define_attr "is_arch6" "no,yes" (const (symbol_ref "arm_arch6")))
81 ; IS_THUMB1 is set to 'yes' iff we are generating Thumb-1 code.
82 (define_attr "is_thumb1" "yes,no"
83 (const (if_then_else (symbol_ref "TARGET_THUMB1")
84 (const_string "yes") (const_string "no"))))
86 ; Mark an instruction as suitable for "short IT" blocks in Thumb-2.
87 ; The arm_restrict_it flag enables the "short IT" feature which
88 ; restricts IT blocks to a single 16-bit instruction.
89 ; This attribute should only be used on 16-bit Thumb-2 instructions
90 ; which may be predicated (the "predicable" attribute must be set).
91 (define_attr "predicable_short_it" "no,yes" (const_string "no"))
93 ; Mark an instruction as suitable for "short IT" blocks in Thumb-2.
94 ; This attribute should only be used on instructions which may emit
95 ; an IT block in their expansion which is not a short IT.
96 (define_attr "enabled_for_short_it" "no,yes" (const_string "yes"))
98 ;; Operand number of an input operand that is shifted. Zero if the
99 ;; given instruction does not shift one of its input operands.
100 (define_attr "shift" "" (const_int 0))
102 ;; [For compatibility with AArch64 in pipeline models]
103 ;; Attribute that specifies whether or not the instruction touches fp
105 (define_attr "fp" "no,yes" (const_string "no"))
107 ; Floating Point Unit. If we only have floating point emulation, then there
108 ; is no point in scheduling the floating point insns. (Well, for best
109 ; performance we should try and group them together).
110 (define_attr "fpu" "none,vfp"
111 (const (symbol_ref "arm_fpu_attr")))
113 ; Predicated means that the insn form is conditionally executed based on a
114 ; predicate. We default to 'no' because no Thumb patterns match this rule
115 ; and not all ARM insns do.
116 (define_attr "predicated" "yes,no" (const_string "no"))
118 ; LENGTH of an instruction (in bytes)
119 (define_attr "length" ""
122 ; The architecture which supports the instruction (or alternative).
123 ; This can be "a" for ARM, "t" for either of the Thumbs, "32" for
124 ; TARGET_32BIT, "t1" or "t2" to specify a specific Thumb mode. "v6"
125 ; for ARM or Thumb-2 with arm_arch6, and nov6 for ARM without
126 ; arm_arch6. "v6t2" for Thumb-2 with arm_arch6 and "v8mb" for ARMv8-M
127 ; Baseline. This attribute is used to compute attribute "enabled",
128 ; use type "any" to enable an alternative in all cases.
129 (define_attr "arch" "any,a,t,32,t1,t2,v6,nov6,v6t2,v8mb,iwmmxt,iwmmxt2,armv6_or_vfpv3,neon"
130 (const_string "any"))
132 (define_attr "arch_enabled" "no,yes"
133 (cond [(eq_attr "arch" "any")
136 (and (eq_attr "arch" "a")
137 (match_test "TARGET_ARM"))
140 (and (eq_attr "arch" "t")
141 (match_test "TARGET_THUMB"))
144 (and (eq_attr "arch" "t1")
145 (match_test "TARGET_THUMB1"))
148 (and (eq_attr "arch" "t2")
149 (match_test "TARGET_THUMB2"))
152 (and (eq_attr "arch" "32")
153 (match_test "TARGET_32BIT"))
156 (and (eq_attr "arch" "v6")
157 (match_test "TARGET_32BIT && arm_arch6"))
160 (and (eq_attr "arch" "nov6")
161 (match_test "TARGET_32BIT && !arm_arch6"))
164 (and (eq_attr "arch" "v6t2")
165 (match_test "TARGET_32BIT && arm_arch6 && arm_arch_thumb2"))
168 (and (eq_attr "arch" "v8mb")
169 (match_test "TARGET_THUMB1 && arm_arch8"))
172 (and (eq_attr "arch" "iwmmxt2")
173 (match_test "TARGET_REALLY_IWMMXT2"))
176 (and (eq_attr "arch" "armv6_or_vfpv3")
177 (match_test "arm_arch6 || TARGET_VFP3"))
180 (and (eq_attr "arch" "neon")
181 (match_test "TARGET_NEON"))
185 (const_string "no")))
187 (define_attr "opt" "any,speed,size"
188 (const_string "any"))
190 (define_attr "opt_enabled" "no,yes"
191 (cond [(eq_attr "opt" "any")
194 (and (eq_attr "opt" "speed")
195 (match_test "optimize_function_for_speed_p (cfun)"))
198 (and (eq_attr "opt" "size")
199 (match_test "optimize_function_for_size_p (cfun)"))
200 (const_string "yes")]
201 (const_string "no")))
203 (define_attr "use_literal_pool" "no,yes"
204 (cond [(and (eq_attr "type" "f_loads,f_loadd")
205 (match_test "CONSTANT_P (operands[1])"))
206 (const_string "yes")]
207 (const_string "no")))
209 ; Enable all alternatives that are both arch_enabled and insn_enabled.
210 ; FIXME:: opt_enabled has been temporarily removed till the time we have
211 ; an attribute that allows the use of such alternatives.
212 ; This depends on caching of speed_p, size_p on a per
213 ; alternative basis. The problem is that the enabled attribute
214 ; cannot depend on any state that is not cached or is not constant
215 ; for a compilation unit. We probably need a generic "hot/cold"
216 ; alternative which if implemented can help with this. We disable this
217 ; until such a time as this is implemented and / or the improvements or
218 ; regressions with removing this attribute are double checked.
219 ; See ashldi3_neon and <shift>di3_neon in neon.md.
221 (define_attr "enabled" "no,yes"
222 (cond [(and (eq_attr "predicable_short_it" "no")
223 (and (eq_attr "predicated" "yes")
224 (match_test "arm_restrict_it")))
227 (and (eq_attr "enabled_for_short_it" "no")
228 (match_test "arm_restrict_it"))
231 (eq_attr "arch_enabled" "no")
233 (const_string "yes")))
235 ; POOL_RANGE is how far away from a constant pool entry that this insn
236 ; can be placed. If the distance is zero, then this insn will never
237 ; reference the pool.
238 ; Note that for Thumb constant pools the PC value is rounded down to the
239 ; nearest multiple of four. Therefore, THUMB2_POOL_RANGE (and POOL_RANGE for
240 ; Thumb insns) should be set to <max_range> - 2.
241 ; NEG_POOL_RANGE is nonzero for insns that can reference a constant pool entry
242 ; before its address. It is set to <max_range> - (8 + <data_size>).
243 (define_attr "arm_pool_range" "" (const_int 0))
244 (define_attr "thumb2_pool_range" "" (const_int 0))
245 (define_attr "arm_neg_pool_range" "" (const_int 0))
246 (define_attr "thumb2_neg_pool_range" "" (const_int 0))
248 (define_attr "pool_range" ""
249 (cond [(eq_attr "is_thumb" "yes") (attr "thumb2_pool_range")]
250 (attr "arm_pool_range")))
251 (define_attr "neg_pool_range" ""
252 (cond [(eq_attr "is_thumb" "yes") (attr "thumb2_neg_pool_range")]
253 (attr "arm_neg_pool_range")))
255 ; An assembler sequence may clobber the condition codes without us knowing.
256 ; If such an insn references the pool, then we have no way of knowing how,
257 ; so use the most conservative value for pool_range.
258 (define_asm_attributes
259 [(set_attr "conds" "clob")
260 (set_attr "length" "4")
261 (set_attr "pool_range" "250")])
263 ; Load scheduling, set from the arm_ld_sched variable
264 ; initialized by arm_option_override()
265 (define_attr "ldsched" "no,yes" (const (symbol_ref "arm_ld_sched")))
267 ; condition codes: this one is used by final_prescan_insn to speed up
268 ; conditionalizing instructions. It saves having to scan the rtl to see if
269 ; it uses or alters the condition codes.
271 ; USE means that the condition codes are used by the insn in the process of
272 ; outputting code, this means (at present) that we can't use the insn in
275 ; SET means that the purpose of the insn is to set the condition codes in a
276 ; well defined manner.
278 ; CLOB means that the condition codes are altered in an undefined manner, if
279 ; they are altered at all
281 ; UNCONDITIONAL means the instruction cannot be conditionally executed and
282 ; that the instruction does not use or alter the condition codes.
284 ; NOCOND means that the instruction does not use or alter the condition
285 ; codes but can be converted into a conditionally exectuted instruction.
287 (define_attr "conds" "use,set,clob,unconditional,nocond"
289 (ior (eq_attr "is_thumb1" "yes")
290 (eq_attr "type" "call"))
291 (const_string "clob")
292 (if_then_else (eq_attr "is_neon_type" "no")
293 (const_string "nocond")
294 (const_string "unconditional"))))
296 ; Predicable means that the insn can be conditionally executed based on
297 ; an automatically added predicate (additional patterns are generated by
298 ; gen...). We default to 'no' because no Thumb patterns match this rule
299 ; and not all ARM patterns do.
300 (define_attr "predicable" "no,yes" (const_string "no"))
302 ; Only model the write buffer for ARM6 and ARM7. Earlier processors don't
303 ; have one. Later ones, such as StrongARM, have write-back caches, so don't
304 ; suffer blockages enough to warrant modelling this (and it can adversely
305 ; affect the schedule).
306 (define_attr "model_wbuf" "no,yes" (const (symbol_ref "arm_tune_wbuf")))
308 ; WRITE_CONFLICT implies that a read following an unrelated write is likely
309 ; to stall the processor. Used with model_wbuf above.
310 (define_attr "write_conflict" "no,yes"
311 (if_then_else (eq_attr "type"
314 (const_string "no")))
316 ; Classify the insns into those that take one cycle and those that take more
317 ; than one on the main cpu execution unit.
318 (define_attr "core_cycles" "single,multi"
319 (if_then_else (eq_attr "type"
320 "adc_imm, adc_reg, adcs_imm, adcs_reg, adr, alu_ext, alu_imm, alu_sreg,\
321 alu_shift_imm, alu_shift_reg, alu_dsp_reg, alus_ext, alus_imm, alus_sreg,\
322 alus_shift_imm, alus_shift_reg, bfm, csel, rev, logic_imm, logic_reg,\
323 logic_shift_imm, logic_shift_reg, logics_imm, logics_reg,\
324 logics_shift_imm, logics_shift_reg, extend, shift_imm, float, fcsel,\
325 wmmx_wor, wmmx_wxor, wmmx_wand, wmmx_wandn, wmmx_wmov, wmmx_tmcrr,\
326 wmmx_tmrrc, wmmx_wldr, wmmx_wstr, wmmx_tmcr, wmmx_tmrc, wmmx_wadd,\
327 wmmx_wsub, wmmx_wmul, wmmx_wmac, wmmx_wavg2, wmmx_tinsr, wmmx_textrm,\
328 wmmx_wshufh, wmmx_wcmpeq, wmmx_wcmpgt, wmmx_wmax, wmmx_wmin, wmmx_wpack,\
329 wmmx_wunpckih, wmmx_wunpckil, wmmx_wunpckeh, wmmx_wunpckel, wmmx_wror,\
330 wmmx_wsra, wmmx_wsrl, wmmx_wsll, wmmx_wmadd, wmmx_tmia, wmmx_tmiaph,\
331 wmmx_tmiaxy, wmmx_tbcst, wmmx_tmovmsk, wmmx_wacc, wmmx_waligni,\
332 wmmx_walignr, wmmx_tandc, wmmx_textrc, wmmx_torc, wmmx_torvsc, wmmx_wsad,\
333 wmmx_wabs, wmmx_wabsdiff, wmmx_waddsubhx, wmmx_wsubaddhx, wmmx_wavg4,\
334 wmmx_wmulw, wmmx_wqmulm, wmmx_wqmulwm, wmmx_waddbhus, wmmx_wqmiaxy,\
335 wmmx_wmiaxy, wmmx_wmiawxy, wmmx_wmerge")
336 (const_string "single")
337 (const_string "multi")))
339 ;; FAR_JUMP is "yes" if a BL instruction is used to generate a branch to a
340 ;; distant label. Only applicable to Thumb code.
341 (define_attr "far_jump" "yes,no" (const_string "no"))
344 ;; The number of machine instructions this pattern expands to.
345 ;; Used for Thumb-2 conditional execution.
346 (define_attr "ce_count" "" (const_int 1))
348 ;;---------------------------------------------------------------------------
351 (include "unspecs.md")
353 ;;---------------------------------------------------------------------------
356 (include "iterators.md")
358 ;;---------------------------------------------------------------------------
361 (include "predicates.md")
362 (include "constraints.md")
364 ;;---------------------------------------------------------------------------
365 ;; Pipeline descriptions
367 (define_attr "tune_cortexr4" "yes,no"
369 (eq_attr "tune" "cortexr4,cortexr4f,cortexr5")
371 (const_string "no"))))
373 ;; True if the generic scheduling description should be used.
375 (define_attr "generic_sched" "yes,no"
377 (ior (eq_attr "tune" "fa526,fa626,fa606te,fa626te,fmp626,fa726te,\
378 arm926ejs,arm10e,arm1026ejs,arm1136js,\
379 arm1136jfs,cortexa5,cortexa7,cortexa8,\
380 cortexa9,cortexa12,cortexa15,cortexa17,\
381 cortexa53,cortexa57,cortexm4,cortexm7,\
382 exynosm1,marvell_pj4,xgene1")
383 (eq_attr "tune_cortexr4" "yes"))
385 (const_string "yes"))))
387 (define_attr "generic_vfp" "yes,no"
389 (and (eq_attr "fpu" "vfp")
390 (eq_attr "tune" "!arm10e,cortexa5,cortexa7,\
391 cortexa8,cortexa9,cortexa53,cortexm4,\
392 cortexm7,marvell_pj4,xgene1")
393 (eq_attr "tune_cortexr4" "no"))
395 (const_string "no"))))
397 (include "marvell-f-iwmmxt.md")
398 (include "arm-generic.md")
399 (include "arm926ejs.md")
400 (include "arm1020e.md")
401 (include "arm1026ejs.md")
402 (include "arm1136jfs.md")
404 (include "fa606te.md")
405 (include "fa626te.md")
406 (include "fmp626.md")
407 (include "fa726te.md")
408 (include "cortex-a5.md")
409 (include "cortex-a7.md")
410 (include "cortex-a8.md")
411 (include "cortex-a9.md")
412 (include "cortex-a15.md")
413 (include "cortex-a17.md")
414 (include "cortex-a53.md")
415 (include "cortex-a57.md")
416 (include "cortex-r4.md")
417 (include "cortex-r4f.md")
418 (include "cortex-m7.md")
419 (include "cortex-m4.md")
420 (include "cortex-m4-fpu.md")
421 (include "exynos-m1.md")
423 (include "marvell-pj4.md")
424 (include "xgene1.md")
427 ;;---------------------------------------------------------------------------
432 ;; Note: For DImode insns, there is normally no reason why operands should
433 ;; not be in the same register, what we don't want is for something being
434 ;; written to partially overlap something that is an input.
436 (define_expand "adddi3"
438 [(set (match_operand:DI 0 "s_register_operand")
439 (plus:DI (match_operand:DI 1 "s_register_operand")
440 (match_operand:DI 2 "arm_adddi_operand")))
441 (clobber (reg:CC CC_REGNUM))])]
444 if (TARGET_THUMB1 && !REG_P (operands[2]))
445 operands[2] = force_reg (DImode, operands[2]);
449 (define_insn_and_split "*arm_adddi3"
450 [(set (match_operand:DI 0 "arm_general_register_operand" "=&r,&r,&r,&r,&r")
451 (plus:DI (match_operand:DI 1 "arm_general_register_operand" "%0, 0, r, 0, r")
452 (match_operand:DI 2 "arm_general_adddi_operand" "r, 0, r, Dd, Dd")))
453 (clobber (reg:CC CC_REGNUM))]
457 [(parallel [(set (reg:CC_C CC_REGNUM)
458 (compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
460 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
461 (set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))
462 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
465 operands[3] = gen_highpart (SImode, operands[0]);
466 operands[0] = gen_lowpart (SImode, operands[0]);
467 operands[4] = gen_highpart (SImode, operands[1]);
468 operands[1] = gen_lowpart (SImode, operands[1]);
469 operands[5] = gen_highpart_mode (SImode, DImode, operands[2]);
470 operands[2] = gen_lowpart (SImode, operands[2]);
472 [(set_attr "conds" "clob")
473 (set_attr "length" "8")
474 (set_attr "type" "multiple")]
477 (define_insn_and_split "*adddi_sesidi_di"
478 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
479 (plus:DI (sign_extend:DI
480 (match_operand:SI 2 "s_register_operand" "r,r"))
481 (match_operand:DI 1 "s_register_operand" "0,r")))
482 (clobber (reg:CC CC_REGNUM))]
485 "TARGET_32BIT && reload_completed"
486 [(parallel [(set (reg:CC_C CC_REGNUM)
487 (compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
489 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
490 (set (match_dup 3) (plus:SI (plus:SI (ashiftrt:SI (match_dup 2)
493 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
496 operands[3] = gen_highpart (SImode, operands[0]);
497 operands[0] = gen_lowpart (SImode, operands[0]);
498 operands[4] = gen_highpart (SImode, operands[1]);
499 operands[1] = gen_lowpart (SImode, operands[1]);
500 operands[2] = gen_lowpart (SImode, operands[2]);
502 [(set_attr "conds" "clob")
503 (set_attr "length" "8")
504 (set_attr "type" "multiple")]
507 (define_insn_and_split "*adddi_zesidi_di"
508 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
509 (plus:DI (zero_extend:DI
510 (match_operand:SI 2 "s_register_operand" "r,r"))
511 (match_operand:DI 1 "s_register_operand" "0,r")))
512 (clobber (reg:CC CC_REGNUM))]
515 "TARGET_32BIT && reload_completed"
516 [(parallel [(set (reg:CC_C CC_REGNUM)
517 (compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
519 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
520 (set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (const_int 0))
521 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
524 operands[3] = gen_highpart (SImode, operands[0]);
525 operands[0] = gen_lowpart (SImode, operands[0]);
526 operands[4] = gen_highpart (SImode, operands[1]);
527 operands[1] = gen_lowpart (SImode, operands[1]);
528 operands[2] = gen_lowpart (SImode, operands[2]);
530 [(set_attr "conds" "clob")
531 (set_attr "length" "8")
532 (set_attr "type" "multiple")]
535 (define_expand "addv<mode>4"
536 [(match_operand:SIDI 0 "register_operand")
537 (match_operand:SIDI 1 "register_operand")
538 (match_operand:SIDI 2 "register_operand")
539 (match_operand 3 "")]
542 emit_insn (gen_add<mode>3_compareV (operands[0], operands[1], operands[2]));
543 arm_gen_unlikely_cbranch (NE, CC_Vmode, operands[3]);
548 (define_expand "uaddv<mode>4"
549 [(match_operand:SIDI 0 "register_operand")
550 (match_operand:SIDI 1 "register_operand")
551 (match_operand:SIDI 2 "register_operand")
552 (match_operand 3 "")]
555 emit_insn (gen_add<mode>3_compareC (operands[0], operands[1], operands[2]));
556 arm_gen_unlikely_cbranch (NE, CC_Cmode, operands[3]);
561 (define_expand "addsi3"
562 [(set (match_operand:SI 0 "s_register_operand")
563 (plus:SI (match_operand:SI 1 "s_register_operand")
564 (match_operand:SI 2 "reg_or_int_operand")))]
567 if (TARGET_32BIT && CONST_INT_P (operands[2]))
569 arm_split_constant (PLUS, SImode, NULL_RTX,
570 INTVAL (operands[2]), operands[0], operands[1],
571 optimize && can_create_pseudo_p ());
577 ; If there is a scratch available, this will be faster than synthesizing the
580 [(match_scratch:SI 3 "r")
581 (set (match_operand:SI 0 "arm_general_register_operand" "")
582 (plus:SI (match_operand:SI 1 "arm_general_register_operand" "")
583 (match_operand:SI 2 "const_int_operand" "")))]
585 !(const_ok_for_arm (INTVAL (operands[2]))
586 || const_ok_for_arm (-INTVAL (operands[2])))
587 && const_ok_for_arm (~INTVAL (operands[2]))"
588 [(set (match_dup 3) (match_dup 2))
589 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))]
593 ;; The r/r/k alternative is required when reloading the address
594 ;; (plus (reg rN) (reg sp)) into (reg rN). In this case reload will
595 ;; put the duplicated register first, and not try the commutative version.
596 (define_insn_and_split "*arm_addsi3"
597 [(set (match_operand:SI 0 "s_register_operand" "=rk,l,l ,l ,r ,k ,r,k ,r ,k ,r ,k,k,r ,k ,r")
598 (plus:SI (match_operand:SI 1 "s_register_operand" "%0 ,l,0 ,l ,rk,k ,r,r ,rk,k ,rk,k,r,rk,k ,rk")
599 (match_operand:SI 2 "reg_or_int_operand" "rk ,l,Py,Pd,rI,rI,k,rI,Pj,Pj,L ,L,L,PJ,PJ,?n")))]
615 subw%?\\t%0, %1, #%n2
616 subw%?\\t%0, %1, #%n2
619 && CONST_INT_P (operands[2])
620 && !const_ok_for_op (INTVAL (operands[2]), PLUS)
621 && (reload_completed || !arm_eliminable_register (operands[1]))"
622 [(clobber (const_int 0))]
624 arm_split_constant (PLUS, SImode, curr_insn,
625 INTVAL (operands[2]), operands[0],
629 [(set_attr "length" "2,4,4,4,4,4,4,4,4,4,4,4,4,4,4,16")
630 (set_attr "predicable" "yes")
631 (set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no,no,no,no,no,no,no,no")
632 (set_attr "arch" "t2,t2,t2,t2,*,*,*,a,t2,t2,*,*,a,t2,t2,*")
633 (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
634 (const_string "alu_imm")
635 (const_string "alu_sreg")))
639 (define_insn_and_split "adddi3_compareV"
640 [(set (reg:CC_V CC_REGNUM)
643 (sign_extend:TI (match_operand:DI 1 "register_operand" "r"))
644 (sign_extend:TI (match_operand:DI 2 "register_operand" "r")))
645 (sign_extend:TI (plus:DI (match_dup 1) (match_dup 2)))))
646 (set (match_operand:DI 0 "register_operand" "=&r")
647 (plus:DI (match_dup 1) (match_dup 2)))]
650 "&& reload_completed"
651 [(parallel [(set (reg:CC_C CC_REGNUM)
652 (compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
654 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
655 (parallel [(set (reg:CC_V CC_REGNUM)
658 (sign_extend:DI (match_dup 4))
659 (sign_extend:DI (match_dup 5)))
660 (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))
661 (plus:DI (sign_extend:DI
662 (plus:SI (match_dup 4) (match_dup 5)))
663 (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))))
664 (set (match_dup 3) (plus:SI (plus:SI
665 (match_dup 4) (match_dup 5))
666 (ltu:SI (reg:CC_C CC_REGNUM)
670 operands[3] = gen_highpart (SImode, operands[0]);
671 operands[0] = gen_lowpart (SImode, operands[0]);
672 operands[4] = gen_highpart (SImode, operands[1]);
673 operands[1] = gen_lowpart (SImode, operands[1]);
674 operands[5] = gen_highpart (SImode, operands[2]);
675 operands[2] = gen_lowpart (SImode, operands[2]);
677 [(set_attr "conds" "set")
678 (set_attr "length" "8")
679 (set_attr "type" "multiple")]
682 (define_insn "addsi3_compareV"
683 [(set (reg:CC_V CC_REGNUM)
686 (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
687 (sign_extend:DI (match_operand:SI 2 "register_operand" "r")))
688 (sign_extend:DI (plus:SI (match_dup 1) (match_dup 2)))))
689 (set (match_operand:SI 0 "register_operand" "=r")
690 (plus:SI (match_dup 1) (match_dup 2)))]
692 "adds%?\\t%0, %1, %2"
693 [(set_attr "conds" "set")
694 (set_attr "type" "alus_sreg")]
697 (define_insn "*addsi3_compareV_upper"
698 [(set (reg:CC_V CC_REGNUM)
702 (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
703 (sign_extend:DI (match_operand:SI 2 "register_operand" "r")))
704 (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))
705 (plus:DI (sign_extend:DI
706 (plus:SI (match_dup 1) (match_dup 2)))
707 (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))))
708 (set (match_operand:SI 0 "register_operand" "=r")
710 (plus:SI (match_dup 1) (match_dup 2))
711 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
713 "adcs%?\\t%0, %1, %2"
714 [(set_attr "conds" "set")
715 (set_attr "type" "adcs_reg")]
718 (define_insn_and_split "adddi3_compareC"
719 [(set (reg:CC_C CC_REGNUM)
722 (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
723 (zero_extend:TI (match_operand:DI 2 "register_operand" "r")))
724 (zero_extend:TI (plus:DI (match_dup 1) (match_dup 2)))))
725 (set (match_operand:DI 0 "register_operand" "=&r")
726 (plus:DI (match_dup 1) (match_dup 2)))]
729 "&& reload_completed"
730 [(parallel [(set (reg:CC_C CC_REGNUM)
731 (compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
733 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
734 (parallel [(set (reg:CC_C CC_REGNUM)
737 (zero_extend:DI (match_dup 4))
738 (zero_extend:DI (match_dup 5)))
739 (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))
740 (plus:DI (zero_extend:DI
741 (plus:SI (match_dup 4) (match_dup 5)))
742 (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))))
743 (set (match_dup 3) (plus:SI
744 (plus:SI (match_dup 4) (match_dup 5))
745 (ltu:SI (reg:CC_C CC_REGNUM)
749 operands[3] = gen_highpart (SImode, operands[0]);
750 operands[0] = gen_lowpart (SImode, operands[0]);
751 operands[4] = gen_highpart (SImode, operands[1]);
752 operands[5] = gen_highpart (SImode, operands[2]);
753 operands[1] = gen_lowpart (SImode, operands[1]);
754 operands[2] = gen_lowpart (SImode, operands[2]);
756 [(set_attr "conds" "set")
757 (set_attr "length" "8")
758 (set_attr "type" "multiple")]
761 (define_insn "*addsi3_compareC_upper"
762 [(set (reg:CC_C CC_REGNUM)
766 (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
767 (zero_extend:DI (match_operand:SI 2 "register_operand" "r")))
768 (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))
769 (plus:DI (zero_extend:DI
770 (plus:SI (match_dup 1) (match_dup 2)))
771 (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))))
772 (set (match_operand:SI 0 "register_operand" "=r")
774 (plus:SI (match_dup 1) (match_dup 2))
775 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
777 "adcs%?\\t%0, %1, %2"
778 [(set_attr "conds" "set")
779 (set_attr "type" "adcs_reg")]
782 (define_insn "addsi3_compareC"
783 [(set (reg:CC_C CC_REGNUM)
786 (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
787 (zero_extend:DI (match_operand:SI 2 "register_operand" "r")))
789 (plus:SI (match_dup 1) (match_dup 2)))))
790 (set (match_operand:SI 0 "register_operand" "=r")
791 (plus:SI (match_dup 1) (match_dup 2)))]
793 "adds%?\\t%0, %1, %2"
794 [(set_attr "conds" "set")
795 (set_attr "type" "alus_sreg")]
798 (define_insn "addsi3_compare0"
799 [(set (reg:CC_NOOV CC_REGNUM)
801 (plus:SI (match_operand:SI 1 "s_register_operand" "r, r,r")
802 (match_operand:SI 2 "arm_add_operand" "I,L,r"))
804 (set (match_operand:SI 0 "s_register_operand" "=r,r,r")
805 (plus:SI (match_dup 1) (match_dup 2)))]
809 subs%?\\t%0, %1, #%n2
811 [(set_attr "conds" "set")
812 (set_attr "type" "alus_imm,alus_imm,alus_sreg")]
815 (define_insn "*addsi3_compare0_scratch"
816 [(set (reg:CC_NOOV CC_REGNUM)
818 (plus:SI (match_operand:SI 0 "s_register_operand" "r, r, r")
819 (match_operand:SI 1 "arm_add_operand" "I,L, r"))
826 [(set_attr "conds" "set")
827 (set_attr "predicable" "yes")
828 (set_attr "type" "alus_imm,alus_imm,alus_sreg")]
831 (define_insn "*compare_negsi_si"
832 [(set (reg:CC_Z CC_REGNUM)
834 (neg:SI (match_operand:SI 0 "s_register_operand" "l,r"))
835 (match_operand:SI 1 "s_register_operand" "l,r")))]
838 [(set_attr "conds" "set")
839 (set_attr "predicable" "yes")
840 (set_attr "arch" "t2,*")
841 (set_attr "length" "2,4")
842 (set_attr "predicable_short_it" "yes,no")
843 (set_attr "type" "alus_sreg")]
846 ;; This is the canonicalization of subsi3_compare when the
847 ;; addend is a constant.
848 (define_insn "cmpsi2_addneg"
849 [(set (reg:CC CC_REGNUM)
851 (match_operand:SI 1 "s_register_operand" "r,r")
852 (match_operand:SI 2 "arm_addimm_operand" "I,L")))
853 (set (match_operand:SI 0 "s_register_operand" "=r,r")
854 (plus:SI (match_dup 1)
855 (match_operand:SI 3 "arm_addimm_operand" "L,I")))]
857 && (INTVAL (operands[2])
858 == trunc_int_for_mode (-INTVAL (operands[3]), SImode))"
860 /* For 0 and INT_MIN it is essential that we use subs, as adds will result
861 in different condition codes (like cmn rather than like cmp), so that
862 alternative comes first. Both alternatives can match for any 0x??000000
863 where except for 0 and INT_MIN it doesn't matter what we choose, and also
864 for -1 and 1 with TARGET_THUMB2, in that case prefer instruction with #1
866 if (which_alternative == 0 && operands[3] != const1_rtx)
867 return "subs%?\\t%0, %1, #%n3";
869 return "adds%?\\t%0, %1, %3";
871 [(set_attr "conds" "set")
872 (set_attr "type" "alus_sreg")]
875 ;; Convert the sequence
877 ;; cmn rd, #1 (equivalent to cmp rd, #-1)
881 ;; bcs dest ((unsigned)rn >= 1)
882 ;; similarly for the beq variant using bcc.
883 ;; This is a common looping idiom (while (n--))
885 [(set (match_operand:SI 0 "arm_general_register_operand" "")
886 (plus:SI (match_operand:SI 1 "arm_general_register_operand" "")
888 (set (match_operand 2 "cc_register" "")
889 (compare (match_dup 0) (const_int -1)))
891 (if_then_else (match_operator 3 "equality_operator"
892 [(match_dup 2) (const_int 0)])
893 (match_operand 4 "" "")
894 (match_operand 5 "" "")))]
895 "TARGET_32BIT && peep2_reg_dead_p (3, operands[2])"
899 (match_dup 1) (const_int 1)))
900 (set (match_dup 0) (plus:SI (match_dup 1) (const_int -1)))])
902 (if_then_else (match_op_dup 3 [(match_dup 2) (const_int 0)])
905 "operands[2] = gen_rtx_REG (CCmode, CC_REGNUM);
906 operands[3] = gen_rtx_fmt_ee ((GET_CODE (operands[3]) == NE
909 operands[2], const0_rtx);"
912 ;; The next four insns work because they compare the result with one of
913 ;; the operands, and we know that the use of the condition code is
914 ;; either GEU or LTU, so we can use the carry flag from the addition
915 ;; instead of doing the compare a second time.
916 (define_insn "*addsi3_compare_op1"
917 [(set (reg:CC_C CC_REGNUM)
919 (plus:SI (match_operand:SI 1 "s_register_operand" "l,0,l,0,r,r,r")
920 (match_operand:SI 2 "arm_add_operand" "lPd,Py,lPx,Pw,I,L,r"))
922 (set (match_operand:SI 0 "s_register_operand" "=l,l,l,l,r,r,r")
923 (plus:SI (match_dup 1) (match_dup 2)))]
928 subs%?\\t%0, %1, #%n2
929 subs%?\\t%0, %0, #%n2
931 subs%?\\t%0, %1, #%n2
933 [(set_attr "conds" "set")
934 (set_attr "arch" "t2,t2,t2,t2,*,*,*")
935 (set_attr "length" "2,2,2,2,4,4,4")
937 "alus_sreg,alus_imm,alus_sreg,alus_imm,alus_imm,alus_imm,alus_sreg")]
940 (define_insn "*addsi3_compare_op2"
941 [(set (reg:CC_C CC_REGNUM)
943 (plus:SI (match_operand:SI 1 "s_register_operand" "l,0,l,0,r,r,r")
944 (match_operand:SI 2 "arm_add_operand" "lPd,Py,lPx,Pw,I,L,r"))
946 (set (match_operand:SI 0 "s_register_operand" "=l,l,l,l,r,r,r")
947 (plus:SI (match_dup 1) (match_dup 2)))]
952 subs%?\\t%0, %1, #%n2
953 subs%?\\t%0, %0, #%n2
955 subs%?\\t%0, %1, #%n2
957 [(set_attr "conds" "set")
958 (set_attr "arch" "t2,t2,t2,t2,*,*,*")
959 (set_attr "length" "2,2,2,2,4,4,4")
961 "alus_sreg,alus_imm,alus_sreg,alus_imm,alus_imm,alus_imm,alus_sreg")]
964 (define_insn "*compare_addsi2_op0"
965 [(set (reg:CC_C CC_REGNUM)
967 (plus:SI (match_operand:SI 0 "s_register_operand" "l,l,r,r,r")
968 (match_operand:SI 1 "arm_add_operand" "Pv,l,I,L,r"))
977 [(set_attr "conds" "set")
978 (set_attr "predicable" "yes")
979 (set_attr "arch" "t2,t2,*,*,*")
980 (set_attr "predicable_short_it" "yes,yes,no,no,no")
981 (set_attr "length" "2,2,4,4,4")
982 (set_attr "type" "alus_imm,alus_sreg,alus_imm,alus_imm,alus_sreg")]
985 (define_insn "*compare_addsi2_op1"
986 [(set (reg:CC_C CC_REGNUM)
988 (plus:SI (match_operand:SI 0 "s_register_operand" "l,l,r,r,r")
989 (match_operand:SI 1 "arm_add_operand" "Pv,l,I,L,r"))
998 [(set_attr "conds" "set")
999 (set_attr "predicable" "yes")
1000 (set_attr "arch" "t2,t2,*,*,*")
1001 (set_attr "predicable_short_it" "yes,yes,no,no,no")
1002 (set_attr "length" "2,2,4,4,4")
1003 (set_attr "type" "alus_imm,alus_sreg,alus_imm,alus_imm,alus_sreg")]
1006 (define_insn "*addsi3_carryin_<optab>"
1007 [(set (match_operand:SI 0 "s_register_operand" "=l,r,r")
1008 (plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%l,r,r")
1009 (match_operand:SI 2 "arm_not_operand" "0,rI,K"))
1010 (LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))))]
1015 sbc%?\\t%0, %1, #%B2"
1016 [(set_attr "conds" "use")
1017 (set_attr "predicable" "yes")
1018 (set_attr "arch" "t2,*,*")
1019 (set_attr "length" "4")
1020 (set_attr "predicable_short_it" "yes,no,no")
1021 (set_attr "type" "adc_reg,adc_reg,adc_imm")]
1024 (define_insn "*addsi3_carryin_alt2_<optab>"
1025 [(set (match_operand:SI 0 "s_register_operand" "=l,r,r")
1026 (plus:SI (plus:SI (LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))
1027 (match_operand:SI 1 "s_register_operand" "%l,r,r"))
1028 (match_operand:SI 2 "arm_rhs_operand" "l,rI,K")))]
1033 sbc%?\\t%0, %1, #%B2"
1034 [(set_attr "conds" "use")
1035 (set_attr "predicable" "yes")
1036 (set_attr "arch" "t2,*,*")
1037 (set_attr "length" "4")
1038 (set_attr "predicable_short_it" "yes,no,no")
1039 (set_attr "type" "adc_reg,adc_reg,adc_imm")]
1042 (define_insn "*addsi3_carryin_shift_<optab>"
1043 [(set (match_operand:SI 0 "s_register_operand" "=r")
1045 (match_operator:SI 2 "shift_operator"
1046 [(match_operand:SI 3 "s_register_operand" "r")
1047 (match_operand:SI 4 "reg_or_int_operand" "rM")])
1048 (match_operand:SI 1 "s_register_operand" "r"))
1049 (LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))))]
1051 "adc%?\\t%0, %1, %3%S2"
1052 [(set_attr "conds" "use")
1053 (set_attr "predicable" "yes")
1054 (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
1055 (const_string "alu_shift_imm")
1056 (const_string "alu_shift_reg")))]
1059 (define_insn "*addsi3_carryin_clobercc_<optab>"
1060 [(set (match_operand:SI 0 "s_register_operand" "=r")
1061 (plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%r")
1062 (match_operand:SI 2 "arm_rhs_operand" "rI"))
1063 (LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))))
1064 (clobber (reg:CC CC_REGNUM))]
1066 "adcs%?\\t%0, %1, %2"
1067 [(set_attr "conds" "set")
1068 (set_attr "type" "adcs_reg")]
1071 (define_expand "subv<mode>4"
1072 [(match_operand:SIDI 0 "register_operand")
1073 (match_operand:SIDI 1 "register_operand")
1074 (match_operand:SIDI 2 "register_operand")
1075 (match_operand 3 "")]
1078 emit_insn (gen_sub<mode>3_compare1 (operands[0], operands[1], operands[2]));
1079 arm_gen_unlikely_cbranch (NE, CC_Vmode, operands[3]);
1084 (define_expand "usubv<mode>4"
1085 [(match_operand:SIDI 0 "register_operand")
1086 (match_operand:SIDI 1 "register_operand")
1087 (match_operand:SIDI 2 "register_operand")
1088 (match_operand 3 "")]
1091 emit_insn (gen_sub<mode>3_compare1 (operands[0], operands[1], operands[2]));
1092 arm_gen_unlikely_cbranch (LTU, CCmode, operands[3]);
1097 (define_insn_and_split "subdi3_compare1"
1098 [(set (reg:CC CC_REGNUM)
1100 (match_operand:DI 1 "register_operand" "r")
1101 (match_operand:DI 2 "register_operand" "r")))
1102 (set (match_operand:DI 0 "register_operand" "=&r")
1103 (minus:DI (match_dup 1) (match_dup 2)))]
1106 "&& reload_completed"
1107 [(parallel [(set (reg:CC CC_REGNUM)
1108 (compare:CC (match_dup 1) (match_dup 2)))
1109 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
1110 (parallel [(set (reg:CC CC_REGNUM)
1111 (compare:CC (match_dup 4) (match_dup 5)))
1112 (set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
1113 (ltu:SI (reg:CC CC_REGNUM) (const_int 0))))])]
1115 operands[3] = gen_highpart (SImode, operands[0]);
1116 operands[0] = gen_lowpart (SImode, operands[0]);
1117 operands[4] = gen_highpart (SImode, operands[1]);
1118 operands[1] = gen_lowpart (SImode, operands[1]);
1119 operands[5] = gen_highpart (SImode, operands[2]);
1120 operands[2] = gen_lowpart (SImode, operands[2]);
1122 [(set_attr "conds" "set")
1123 (set_attr "length" "8")
1124 (set_attr "type" "multiple")]
1127 (define_insn "subsi3_compare1"
1128 [(set (reg:CC CC_REGNUM)
1130 (match_operand:SI 1 "register_operand" "r")
1131 (match_operand:SI 2 "register_operand" "r")))
1132 (set (match_operand:SI 0 "register_operand" "=r")
1133 (minus:SI (match_dup 1) (match_dup 2)))]
1135 "subs%?\\t%0, %1, %2"
1136 [(set_attr "conds" "set")
1137 (set_attr "type" "alus_sreg")]
1140 (define_insn "*subsi3_carryin"
1141 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
1142 (minus:SI (minus:SI (match_operand:SI 1 "reg_or_int_operand" "r,I,Pz")
1143 (match_operand:SI 2 "s_register_operand" "r,r,r"))
1144 (match_operand:SI 3 "arm_borrow_operation" "")))]
1149 sbc%?\\t%0, %2, %2, lsl #1"
1150 [(set_attr "conds" "use")
1151 (set_attr "arch" "*,a,t2")
1152 (set_attr "predicable" "yes")
1153 (set_attr "type" "adc_reg,adc_imm,alu_shift_imm")]
1156 (define_insn "*subsi3_carryin_const"
1157 [(set (match_operand:SI 0 "s_register_operand" "=r")
1159 (match_operand:SI 1 "s_register_operand" "r")
1160 (match_operand:SI 2 "arm_neg_immediate_operand" "L"))
1161 (match_operand:SI 3 "arm_borrow_operation" "")))]
1163 "sbc\\t%0, %1, #%n2"
1164 [(set_attr "conds" "use")
1165 (set_attr "type" "adc_imm")]
1168 (define_insn "*subsi3_carryin_const0"
1169 [(set (match_operand:SI 0 "s_register_operand" "=r")
1170 (minus:SI (match_operand:SI 1 "s_register_operand" "r")
1171 (match_operand:SI 2 "arm_borrow_operation" "")))]
1174 [(set_attr "conds" "use")
1175 (set_attr "type" "adc_imm")]
1178 (define_insn "*subsi3_carryin_compare"
1179 [(set (reg:CC CC_REGNUM)
1180 (compare:CC (match_operand:SI 1 "s_register_operand" "r")
1181 (match_operand:SI 2 "s_register_operand" "r")))
1182 (set (match_operand:SI 0 "s_register_operand" "=r")
1183 (minus:SI (minus:SI (match_dup 1) (match_dup 2))
1184 (match_operand:SI 3 "arm_borrow_operation" "")))]
1187 [(set_attr "conds" "set")
1188 (set_attr "type" "adcs_reg")]
1191 (define_insn "*subsi3_carryin_compare_const"
1192 [(set (reg:CC CC_REGNUM)
1193 (compare:CC (match_operand:SI 1 "reg_or_int_operand" "r")
1194 (match_operand:SI 2 "const_int_I_operand" "I")))
1195 (set (match_operand:SI 0 "s_register_operand" "=r")
1198 (match_operand:SI 3 "arm_neg_immediate_operand" "L"))
1199 (match_operand:SI 4 "arm_borrow_operation" "")))]
1201 && (INTVAL (operands[2])
1202 == trunc_int_for_mode (-INTVAL (operands[3]), SImode))"
1203 "sbcs\\t%0, %1, #%n3"
1204 [(set_attr "conds" "set")
1205 (set_attr "type" "adcs_imm")]
1208 (define_insn "*subsi3_carryin_compare_const0"
1209 [(set (reg:CC CC_REGNUM)
1210 (compare:CC (match_operand:SI 1 "reg_or_int_operand" "r")
1212 (set (match_operand:SI 0 "s_register_operand" "=r")
1213 (minus:SI (match_dup 1)
1214 (match_operand:SI 2 "arm_borrow_operation" "")))]
1217 [(set_attr "conds" "set")
1218 (set_attr "type" "adcs_imm")]
1221 (define_insn "*subsi3_carryin_shift"
1222 [(set (match_operand:SI 0 "s_register_operand" "=r")
1224 (match_operand:SI 1 "s_register_operand" "r")
1225 (match_operator:SI 2 "shift_operator"
1226 [(match_operand:SI 3 "s_register_operand" "r")
1227 (match_operand:SI 4 "reg_or_int_operand" "rM")]))
1228 (match_operand:SI 5 "arm_borrow_operation" "")))]
1230 "sbc%?\\t%0, %1, %3%S2"
1231 [(set_attr "conds" "use")
1232 (set_attr "predicable" "yes")
1233 (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
1234 (const_string "alu_shift_imm")
1235 (const_string "alu_shift_reg")))]
1238 (define_insn "*rsbsi3_carryin_shift"
1239 [(set (match_operand:SI 0 "s_register_operand" "=r")
1241 (match_operator:SI 2 "shift_operator"
1242 [(match_operand:SI 3 "s_register_operand" "r")
1243 (match_operand:SI 4 "reg_or_int_operand" "rM")])
1244 (match_operand:SI 1 "s_register_operand" "r"))
1245 (match_operand:SI 5 "arm_borrow_operation" "")))]
1247 "rsc%?\\t%0, %1, %3%S2"
1248 [(set_attr "conds" "use")
1249 (set_attr "predicable" "yes")
1250 (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
1251 (const_string "alu_shift_imm")
1252 (const_string "alu_shift_reg")))]
1255 ; transform ((x << y) - 1) to ~(~(x-1) << y) Where X is a constant.
1257 [(set (match_operand:SI 0 "s_register_operand" "")
1258 (plus:SI (ashift:SI (match_operand:SI 1 "const_int_operand" "")
1259 (match_operand:SI 2 "s_register_operand" ""))
1261 (clobber (match_operand:SI 3 "s_register_operand" ""))]
1263 [(set (match_dup 3) (match_dup 1))
1264 (set (match_dup 0) (not:SI (ashift:SI (match_dup 3) (match_dup 2))))]
1266 operands[1] = GEN_INT (~(INTVAL (operands[1]) - 1));
1269 (define_expand "addsf3"
1270 [(set (match_operand:SF 0 "s_register_operand")
1271 (plus:SF (match_operand:SF 1 "s_register_operand")
1272 (match_operand:SF 2 "s_register_operand")))]
1273 "TARGET_32BIT && TARGET_HARD_FLOAT"
1277 (define_expand "adddf3"
1278 [(set (match_operand:DF 0 "s_register_operand")
1279 (plus:DF (match_operand:DF 1 "s_register_operand")
1280 (match_operand:DF 2 "s_register_operand")))]
1281 "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
1285 (define_expand "subdi3"
1287 [(set (match_operand:DI 0 "s_register_operand")
1288 (minus:DI (match_operand:DI 1 "s_register_operand")
1289 (match_operand:DI 2 "s_register_operand")))
1290 (clobber (reg:CC CC_REGNUM))])]
1295 (define_insn_and_split "*arm_subdi3"
1296 [(set (match_operand:DI 0 "arm_general_register_operand" "=&r,&r,&r")
1297 (minus:DI (match_operand:DI 1 "arm_general_register_operand" "0,r,0")
1298 (match_operand:DI 2 "arm_general_register_operand" "r,0,0")))
1299 (clobber (reg:CC CC_REGNUM))]
1301 "#" ; "subs\\t%Q0, %Q1, %Q2\;sbc\\t%R0, %R1, %R2"
1303 [(parallel [(set (reg:CC CC_REGNUM)
1304 (compare:CC (match_dup 1) (match_dup 2)))
1305 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
1306 (set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
1307 (ltu:SI (reg:CC CC_REGNUM) (const_int 0))))]
1309 operands[3] = gen_highpart (SImode, operands[0]);
1310 operands[0] = gen_lowpart (SImode, operands[0]);
1311 operands[4] = gen_highpart (SImode, operands[1]);
1312 operands[1] = gen_lowpart (SImode, operands[1]);
1313 operands[5] = gen_highpart (SImode, operands[2]);
1314 operands[2] = gen_lowpart (SImode, operands[2]);
1316 [(set_attr "conds" "clob")
1317 (set_attr "length" "8")
1318 (set_attr "type" "multiple")]
1321 (define_insn_and_split "*subdi_di_zesidi"
1322 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
1323 (minus:DI (match_operand:DI 1 "s_register_operand" "0,r")
1325 (match_operand:SI 2 "s_register_operand" "r,r"))))
1326 (clobber (reg:CC CC_REGNUM))]
1328 "#" ; "subs\\t%Q0, %Q1, %2\;sbc\\t%R0, %R1, #0"
1329 "&& reload_completed"
1330 [(parallel [(set (reg:CC CC_REGNUM)
1331 (compare:CC (match_dup 1) (match_dup 2)))
1332 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
1333 (set (match_dup 3) (minus:SI (match_dup 4)
1334 (ltu:SI (reg:CC CC_REGNUM) (const_int 0))))]
1336 operands[3] = gen_highpart (SImode, operands[0]);
1337 operands[0] = gen_lowpart (SImode, operands[0]);
1338 operands[4] = gen_highpart (SImode, operands[1]);
1339 operands[1] = gen_lowpart (SImode, operands[1]);
1341 [(set_attr "conds" "clob")
1342 (set_attr "length" "8")
1343 (set_attr "type" "multiple")]
1346 (define_insn_and_split "*subdi_di_sesidi"
1347 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
1348 (minus:DI (match_operand:DI 1 "s_register_operand" "0,r")
1350 (match_operand:SI 2 "s_register_operand" "r,r"))))
1351 (clobber (reg:CC CC_REGNUM))]
1353 "#" ; "subs\\t%Q0, %Q1, %2\;sbc\\t%R0, %R1, %2, asr #31"
1354 "&& reload_completed"
1355 [(parallel [(set (reg:CC CC_REGNUM)
1356 (compare:CC (match_dup 1) (match_dup 2)))
1357 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
1358 (set (match_dup 3) (minus:SI (minus:SI (match_dup 4)
1359 (ashiftrt:SI (match_dup 2)
1361 (ltu:SI (reg:CC CC_REGNUM) (const_int 0))))]
1363 operands[3] = gen_highpart (SImode, operands[0]);
1364 operands[0] = gen_lowpart (SImode, operands[0]);
1365 operands[4] = gen_highpart (SImode, operands[1]);
1366 operands[1] = gen_lowpart (SImode, operands[1]);
1368 [(set_attr "conds" "clob")
1369 (set_attr "length" "8")
1370 (set_attr "type" "multiple")]
1373 (define_insn_and_split "*subdi_zesidi_di"
1374 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
1375 (minus:DI (zero_extend:DI
1376 (match_operand:SI 2 "s_register_operand" "r,r"))
1377 (match_operand:DI 1 "s_register_operand" "0,r")))
1378 (clobber (reg:CC CC_REGNUM))]
1380 "#" ; "rsbs\\t%Q0, %Q1, %2\;rsc\\t%R0, %R1, #0"
1382 ; "subs\\t%Q0, %2, %Q1\;rsc\\t%R0, %R1, #0"
1383 "&& reload_completed"
1384 [(parallel [(set (reg:CC CC_REGNUM)
1385 (compare:CC (match_dup 2) (match_dup 1)))
1386 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 1)))])
1387 (set (match_dup 3) (minus:SI (minus:SI (const_int 0) (match_dup 4))
1388 (ltu:SI (reg:CC CC_REGNUM) (const_int 0))))]
1390 operands[3] = gen_highpart (SImode, operands[0]);
1391 operands[0] = gen_lowpart (SImode, operands[0]);
1392 operands[4] = gen_highpart (SImode, operands[1]);
1393 operands[1] = gen_lowpart (SImode, operands[1]);
1395 [(set_attr "conds" "clob")
1396 (set_attr "length" "8")
1397 (set_attr "type" "multiple")]
1400 (define_insn_and_split "*subdi_sesidi_di"
1401 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
1402 (minus:DI (sign_extend:DI
1403 (match_operand:SI 2 "s_register_operand" "r,r"))
1404 (match_operand:DI 1 "s_register_operand" "0,r")))
1405 (clobber (reg:CC CC_REGNUM))]
1407 "#" ; "rsbs\\t%Q0, %Q1, %2\;rsc\\t%R0, %R1, %2, asr #31"
1409 ; "subs\\t%Q0, %2, %Q1\;rsc\\t%R0, %R1, %2, asr #31"
1410 "&& reload_completed"
1411 [(parallel [(set (reg:CC CC_REGNUM)
1412 (compare:CC (match_dup 2) (match_dup 1)))
1413 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 1)))])
1414 (set (match_dup 3) (minus:SI (minus:SI
1415 (ashiftrt:SI (match_dup 2)
1418 (ltu:SI (reg:CC CC_REGNUM) (const_int 0))))]
1420 operands[3] = gen_highpart (SImode, operands[0]);
1421 operands[0] = gen_lowpart (SImode, operands[0]);
1422 operands[4] = gen_highpart (SImode, operands[1]);
1423 operands[1] = gen_lowpart (SImode, operands[1]);
1425 [(set_attr "conds" "clob")
1426 (set_attr "length" "8")
1427 (set_attr "type" "multiple")]
1430 (define_insn_and_split "*subdi_zesidi_zesidi"
1431 [(set (match_operand:DI 0 "s_register_operand" "=r")
1432 (minus:DI (zero_extend:DI
1433 (match_operand:SI 1 "s_register_operand" "r"))
1435 (match_operand:SI 2 "s_register_operand" "r"))))
1436 (clobber (reg:CC CC_REGNUM))]
1438 "#" ; "subs\\t%Q0, %1, %2\;sbc\\t%R0, %1, %1"
1439 "&& reload_completed"
1440 [(parallel [(set (reg:CC CC_REGNUM)
1441 (compare:CC (match_dup 1) (match_dup 2)))
1442 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
1443 (set (match_dup 3) (minus:SI (minus:SI (match_dup 1) (match_dup 1))
1444 (ltu:SI (reg:CC CC_REGNUM) (const_int 0))))]
1446 operands[3] = gen_highpart (SImode, operands[0]);
1447 operands[0] = gen_lowpart (SImode, operands[0]);
1449 [(set_attr "conds" "clob")
1450 (set_attr "length" "8")
1451 (set_attr "type" "multiple")]
1454 (define_expand "subsi3"
1455 [(set (match_operand:SI 0 "s_register_operand")
1456 (minus:SI (match_operand:SI 1 "reg_or_int_operand")
1457 (match_operand:SI 2 "s_register_operand")))]
1460 if (CONST_INT_P (operands[1]))
1464 if (DONT_EARLY_SPLIT_CONSTANT (INTVAL (operands[1]), MINUS))
1465 operands[1] = force_reg (SImode, operands[1]);
1468 arm_split_constant (MINUS, SImode, NULL_RTX,
1469 INTVAL (operands[1]), operands[0],
1471 optimize && can_create_pseudo_p ());
1475 else /* TARGET_THUMB1 */
1476 operands[1] = force_reg (SImode, operands[1]);
1481 ; ??? Check Thumb-2 split length
1482 (define_insn_and_split "*arm_subsi3_insn"
1483 [(set (match_operand:SI 0 "s_register_operand" "=l,l ,l ,l ,r,r,r,rk,r")
1484 (minus:SI (match_operand:SI 1 "reg_or_int_operand" "l ,0 ,l ,Pz,I,r,r,k ,?n")
1485 (match_operand:SI 2 "reg_or_int_operand" "l ,Py,Pd,l ,r,I,r,r ,r")))]
1497 "&& (CONST_INT_P (operands[1])
1498 && !const_ok_for_arm (INTVAL (operands[1])))"
1499 [(clobber (const_int 0))]
1501 arm_split_constant (MINUS, SImode, curr_insn,
1502 INTVAL (operands[1]), operands[0], operands[2], 0);
1505 [(set_attr "length" "4,4,4,4,4,4,4,4,16")
1506 (set_attr "arch" "t2,t2,t2,t2,*,*,*,*,*")
1507 (set_attr "predicable" "yes")
1508 (set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no")
1509 (set_attr "type" "alu_sreg,alu_sreg,alu_sreg,alu_sreg,alu_imm,alu_imm,alu_sreg,alu_sreg,multiple")]
1513 [(match_scratch:SI 3 "r")
1514 (set (match_operand:SI 0 "arm_general_register_operand" "")
1515 (minus:SI (match_operand:SI 1 "const_int_operand" "")
1516 (match_operand:SI 2 "arm_general_register_operand" "")))]
1518 && !const_ok_for_arm (INTVAL (operands[1]))
1519 && const_ok_for_arm (~INTVAL (operands[1]))"
1520 [(set (match_dup 3) (match_dup 1))
1521 (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 2)))]
1525 (define_insn "subsi3_compare0"
1526 [(set (reg:CC_NOOV CC_REGNUM)
1528 (minus:SI (match_operand:SI 1 "arm_rhs_operand" "r,r,I")
1529 (match_operand:SI 2 "arm_rhs_operand" "I,r,r"))
1531 (set (match_operand:SI 0 "s_register_operand" "=r,r,r")
1532 (minus:SI (match_dup 1) (match_dup 2)))]
1537 rsbs%?\\t%0, %2, %1"
1538 [(set_attr "conds" "set")
1539 (set_attr "type" "alus_imm,alus_sreg,alus_sreg")]
1542 (define_insn "subsi3_compare"
1543 [(set (reg:CC CC_REGNUM)
1544 (compare:CC (match_operand:SI 1 "arm_rhs_operand" "r,r,I")
1545 (match_operand:SI 2 "arm_rhs_operand" "I,r,r")))
1546 (set (match_operand:SI 0 "s_register_operand" "=r,r,r")
1547 (minus:SI (match_dup 1) (match_dup 2)))]
1552 rsbs%?\\t%0, %2, %1"
1553 [(set_attr "conds" "set")
1554 (set_attr "type" "alus_imm,alus_sreg,alus_sreg")]
1557 (define_expand "subsf3"
1558 [(set (match_operand:SF 0 "s_register_operand")
1559 (minus:SF (match_operand:SF 1 "s_register_operand")
1560 (match_operand:SF 2 "s_register_operand")))]
1561 "TARGET_32BIT && TARGET_HARD_FLOAT"
1565 (define_expand "subdf3"
1566 [(set (match_operand:DF 0 "s_register_operand")
1567 (minus:DF (match_operand:DF 1 "s_register_operand")
1568 (match_operand:DF 2 "s_register_operand")))]
1569 "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
1574 ;; Multiplication insns
1576 (define_expand "mulhi3"
1577 [(set (match_operand:HI 0 "s_register_operand")
1578 (mult:HI (match_operand:HI 1 "s_register_operand")
1579 (match_operand:HI 2 "s_register_operand")))]
1580 "TARGET_DSP_MULTIPLY"
1583 rtx result = gen_reg_rtx (SImode);
1584 emit_insn (gen_mulhisi3 (result, operands[1], operands[2]));
1585 emit_move_insn (operands[0], gen_lowpart (HImode, result));
1590 (define_expand "mulsi3"
1591 [(set (match_operand:SI 0 "s_register_operand")
1592 (mult:SI (match_operand:SI 2 "s_register_operand")
1593 (match_operand:SI 1 "s_register_operand")))]
1598 ;; Use `&' and then `0' to prevent operands 0 and 2 being the same
1600 [(set (match_operand:SI 0 "s_register_operand" "=l,r,&r,&r")
1601 (mult:SI (match_operand:SI 2 "s_register_operand" "l,r,r,r")
1602 (match_operand:SI 1 "s_register_operand" "%0,r,0,r")))]
1604 "mul%?\\t%0, %2, %1"
1605 [(set_attr "type" "mul")
1606 (set_attr "predicable" "yes")
1607 (set_attr "arch" "t2,v6,nov6,nov6")
1608 (set_attr "length" "4")
1609 (set_attr "predicable_short_it" "yes,no,*,*")]
1612 ;; MLA and MLS instruction. Use operand 1 for the accumulator to prefer
1613 ;; reusing the same register.
1616 [(set (match_operand:SI 0 "s_register_operand" "=r,&r,&r,&r")
1618 (mult:SI (match_operand:SI 3 "s_register_operand" "r,r,r,r")
1619 (match_operand:SI 2 "s_register_operand" "%r,r,0,r"))
1620 (match_operand:SI 1 "s_register_operand" "r,0,r,r")))]
1622 "mla%?\\t%0, %3, %2, %1"
1623 [(set_attr "type" "mla")
1624 (set_attr "predicable" "yes")
1625 (set_attr "arch" "v6,nov6,nov6,nov6")]
1629 [(set (match_operand:SI 0 "s_register_operand" "=r")
1631 (match_operand:SI 1 "s_register_operand" "r")
1632 (mult:SI (match_operand:SI 3 "s_register_operand" "r")
1633 (match_operand:SI 2 "s_register_operand" "r"))))]
1634 "TARGET_32BIT && arm_arch_thumb2"
1635 "mls%?\\t%0, %3, %2, %1"
1636 [(set_attr "type" "mla")
1637 (set_attr "predicable" "yes")]
1640 (define_insn "*mulsi3_compare0"
1641 [(set (reg:CC_NOOV CC_REGNUM)
1642 (compare:CC_NOOV (mult:SI
1643 (match_operand:SI 2 "s_register_operand" "r,r")
1644 (match_operand:SI 1 "s_register_operand" "%0,r"))
1646 (set (match_operand:SI 0 "s_register_operand" "=&r,&r")
1647 (mult:SI (match_dup 2) (match_dup 1)))]
1648 "TARGET_ARM && !arm_arch6"
1649 "muls%?\\t%0, %2, %1"
1650 [(set_attr "conds" "set")
1651 (set_attr "type" "muls")]
1654 (define_insn "*mulsi3_compare0_v6"
1655 [(set (reg:CC_NOOV CC_REGNUM)
1656 (compare:CC_NOOV (mult:SI
1657 (match_operand:SI 2 "s_register_operand" "r")
1658 (match_operand:SI 1 "s_register_operand" "r"))
1660 (set (match_operand:SI 0 "s_register_operand" "=r")
1661 (mult:SI (match_dup 2) (match_dup 1)))]
1662 "TARGET_ARM && arm_arch6 && optimize_size"
1663 "muls%?\\t%0, %2, %1"
1664 [(set_attr "conds" "set")
1665 (set_attr "type" "muls")]
1668 (define_insn "*mulsi_compare0_scratch"
1669 [(set (reg:CC_NOOV CC_REGNUM)
1670 (compare:CC_NOOV (mult:SI
1671 (match_operand:SI 2 "s_register_operand" "r,r")
1672 (match_operand:SI 1 "s_register_operand" "%0,r"))
1674 (clobber (match_scratch:SI 0 "=&r,&r"))]
1675 "TARGET_ARM && !arm_arch6"
1676 "muls%?\\t%0, %2, %1"
1677 [(set_attr "conds" "set")
1678 (set_attr "type" "muls")]
1681 (define_insn "*mulsi_compare0_scratch_v6"
1682 [(set (reg:CC_NOOV CC_REGNUM)
1683 (compare:CC_NOOV (mult:SI
1684 (match_operand:SI 2 "s_register_operand" "r")
1685 (match_operand:SI 1 "s_register_operand" "r"))
1687 (clobber (match_scratch:SI 0 "=r"))]
1688 "TARGET_ARM && arm_arch6 && optimize_size"
1689 "muls%?\\t%0, %2, %1"
1690 [(set_attr "conds" "set")
1691 (set_attr "type" "muls")]
1694 (define_insn "*mulsi3addsi_compare0"
1695 [(set (reg:CC_NOOV CC_REGNUM)
1698 (match_operand:SI 2 "s_register_operand" "r,r,r,r")
1699 (match_operand:SI 1 "s_register_operand" "%0,r,0,r"))
1700 (match_operand:SI 3 "s_register_operand" "r,r,0,0"))
1702 (set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r,&r")
1703 (plus:SI (mult:SI (match_dup 2) (match_dup 1))
1705 "TARGET_ARM && arm_arch6"
1706 "mlas%?\\t%0, %2, %1, %3"
1707 [(set_attr "conds" "set")
1708 (set_attr "type" "mlas")]
1711 (define_insn "*mulsi3addsi_compare0_v6"
1712 [(set (reg:CC_NOOV CC_REGNUM)
1715 (match_operand:SI 2 "s_register_operand" "r")
1716 (match_operand:SI 1 "s_register_operand" "r"))
1717 (match_operand:SI 3 "s_register_operand" "r"))
1719 (set (match_operand:SI 0 "s_register_operand" "=r")
1720 (plus:SI (mult:SI (match_dup 2) (match_dup 1))
1722 "TARGET_ARM && arm_arch6 && optimize_size"
1723 "mlas%?\\t%0, %2, %1, %3"
1724 [(set_attr "conds" "set")
1725 (set_attr "type" "mlas")]
1728 (define_insn "*mulsi3addsi_compare0_scratch"
1729 [(set (reg:CC_NOOV CC_REGNUM)
1732 (match_operand:SI 2 "s_register_operand" "r,r,r,r")
1733 (match_operand:SI 1 "s_register_operand" "%0,r,0,r"))
1734 (match_operand:SI 3 "s_register_operand" "?r,r,0,0"))
1736 (clobber (match_scratch:SI 0 "=&r,&r,&r,&r"))]
1737 "TARGET_ARM && !arm_arch6"
1738 "mlas%?\\t%0, %2, %1, %3"
1739 [(set_attr "conds" "set")
1740 (set_attr "type" "mlas")]
1743 (define_insn "*mulsi3addsi_compare0_scratch_v6"
1744 [(set (reg:CC_NOOV CC_REGNUM)
1747 (match_operand:SI 2 "s_register_operand" "r")
1748 (match_operand:SI 1 "s_register_operand" "r"))
1749 (match_operand:SI 3 "s_register_operand" "r"))
1751 (clobber (match_scratch:SI 0 "=r"))]
1752 "TARGET_ARM && arm_arch6 && optimize_size"
1753 "mlas%?\\t%0, %2, %1, %3"
1754 [(set_attr "conds" "set")
1755 (set_attr "type" "mlas")]
1758 (define_expand "maddsidi4"
1759 [(set (match_operand:DI 0 "s_register_operand")
1762 (sign_extend:DI (match_operand:SI 1 "s_register_operand"))
1763 (sign_extend:DI (match_operand:SI 2 "s_register_operand")))
1764 (match_operand:DI 3 "s_register_operand")))]
1768 (define_insn "*mulsidi3adddi"
1769 [(set (match_operand:DI 0 "s_register_operand" "=&r")
1772 (sign_extend:DI (match_operand:SI 2 "s_register_operand" "%r"))
1773 (sign_extend:DI (match_operand:SI 3 "s_register_operand" "r")))
1774 (match_operand:DI 1 "s_register_operand" "0")))]
1775 "TARGET_32BIT && !arm_arch6"
1776 "smlal%?\\t%Q0, %R0, %3, %2"
1777 [(set_attr "type" "smlal")
1778 (set_attr "predicable" "yes")]
1781 (define_insn "*mulsidi3adddi_v6"
1782 [(set (match_operand:DI 0 "s_register_operand" "=r")
1785 (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r"))
1786 (sign_extend:DI (match_operand:SI 3 "s_register_operand" "r")))
1787 (match_operand:DI 1 "s_register_operand" "0")))]
1788 "TARGET_32BIT && arm_arch6"
1789 "smlal%?\\t%Q0, %R0, %3, %2"
1790 [(set_attr "type" "smlal")
1791 (set_attr "predicable" "yes")]
1794 ;; 32x32->64 widening multiply.
1795 ;; As with mulsi3, the only difference between the v3-5 and v6+
1796 ;; versions of these patterns is the requirement that the output not
1797 ;; overlap the inputs, but that still means we have to have a named
1798 ;; expander and two different starred insns.
1800 (define_expand "mulsidi3"
1801 [(set (match_operand:DI 0 "s_register_operand")
1803 (sign_extend:DI (match_operand:SI 1 "s_register_operand"))
1804 (sign_extend:DI (match_operand:SI 2 "s_register_operand"))))]
1809 (define_insn "*mulsidi3_nov6"
1810 [(set (match_operand:DI 0 "s_register_operand" "=&r")
1812 (sign_extend:DI (match_operand:SI 1 "s_register_operand" "%r"))
1813 (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r"))))]
1814 "TARGET_32BIT && !arm_arch6"
1815 "smull%?\\t%Q0, %R0, %1, %2"
1816 [(set_attr "type" "smull")
1817 (set_attr "predicable" "yes")]
1820 (define_insn "*mulsidi3_v6"
1821 [(set (match_operand:DI 0 "s_register_operand" "=r")
1823 (sign_extend:DI (match_operand:SI 1 "s_register_operand" "r"))
1824 (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r"))))]
1825 "TARGET_32BIT && arm_arch6"
1826 "smull%?\\t%Q0, %R0, %1, %2"
1827 [(set_attr "type" "smull")
1828 (set_attr "predicable" "yes")]
1831 (define_expand "umulsidi3"
1832 [(set (match_operand:DI 0 "s_register_operand")
1834 (zero_extend:DI (match_operand:SI 1 "s_register_operand"))
1835 (zero_extend:DI (match_operand:SI 2 "s_register_operand"))))]
1840 (define_insn "*umulsidi3_nov6"
1841 [(set (match_operand:DI 0 "s_register_operand" "=&r")
1843 (zero_extend:DI (match_operand:SI 1 "s_register_operand" "%r"))
1844 (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r"))))]
1845 "TARGET_32BIT && !arm_arch6"
1846 "umull%?\\t%Q0, %R0, %1, %2"
1847 [(set_attr "type" "umull")
1848 (set_attr "predicable" "yes")]
1851 (define_insn "*umulsidi3_v6"
1852 [(set (match_operand:DI 0 "s_register_operand" "=r")
1854 (zero_extend:DI (match_operand:SI 1 "s_register_operand" "r"))
1855 (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r"))))]
1856 "TARGET_32BIT && arm_arch6"
1857 "umull%?\\t%Q0, %R0, %1, %2"
1858 [(set_attr "type" "umull")
1859 (set_attr "predicable" "yes")]
1862 (define_expand "umaddsidi4"
1863 [(set (match_operand:DI 0 "s_register_operand")
1866 (zero_extend:DI (match_operand:SI 1 "s_register_operand"))
1867 (zero_extend:DI (match_operand:SI 2 "s_register_operand")))
1868 (match_operand:DI 3 "s_register_operand")))]
1872 (define_insn "*umulsidi3adddi"
1873 [(set (match_operand:DI 0 "s_register_operand" "=&r")
1876 (zero_extend:DI (match_operand:SI 2 "s_register_operand" "%r"))
1877 (zero_extend:DI (match_operand:SI 3 "s_register_operand" "r")))
1878 (match_operand:DI 1 "s_register_operand" "0")))]
1879 "TARGET_32BIT && !arm_arch6"
1880 "umlal%?\\t%Q0, %R0, %3, %2"
1881 [(set_attr "type" "umlal")
1882 (set_attr "predicable" "yes")]
1885 (define_insn "*umulsidi3adddi_v6"
1886 [(set (match_operand:DI 0 "s_register_operand" "=r")
1889 (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r"))
1890 (zero_extend:DI (match_operand:SI 3 "s_register_operand" "r")))
1891 (match_operand:DI 1 "s_register_operand" "0")))]
1892 "TARGET_32BIT && arm_arch6"
1893 "umlal%?\\t%Q0, %R0, %3, %2"
1894 [(set_attr "type" "umlal")
1895 (set_attr "predicable" "yes")]
1898 (define_expand "<US>mulsi3_highpart"
1900 [(set (match_operand:SI 0 "s_register_operand")
1904 (SE:DI (match_operand:SI 1 "s_register_operand"))
1905 (SE:DI (match_operand:SI 2 "s_register_operand")))
1907 (clobber (match_scratch:SI 3 ""))])]
1912 (define_insn "*<US>mull_high"
1913 [(set (match_operand:SI 0 "s_register_operand" "=r,&r,&r")
1917 (SE:DI (match_operand:SI 1 "s_register_operand" "%r,0,r"))
1918 (SE:DI (match_operand:SI 2 "s_register_operand" "r,r,r")))
1920 (clobber (match_scratch:SI 3 "=r,&r,&r"))]
1922 "<US>mull%?\\t%3, %0, %2, %1"
1923 [(set_attr "type" "umull")
1924 (set_attr "predicable" "yes")
1925 (set_attr "arch" "v6,nov6,nov6")]
1928 (define_insn "mulhisi3"
1929 [(set (match_operand:SI 0 "s_register_operand" "=r")
1930 (mult:SI (sign_extend:SI
1931 (match_operand:HI 1 "s_register_operand" "%r"))
1933 (match_operand:HI 2 "s_register_operand" "r"))))]
1934 "TARGET_DSP_MULTIPLY"
1935 "smulbb%?\\t%0, %1, %2"
1936 [(set_attr "type" "smulxy")
1937 (set_attr "predicable" "yes")]
1940 (define_insn "*mulhisi3tb"
1941 [(set (match_operand:SI 0 "s_register_operand" "=r")
1942 (mult:SI (ashiftrt:SI
1943 (match_operand:SI 1 "s_register_operand" "r")
1946 (match_operand:HI 2 "s_register_operand" "r"))))]
1947 "TARGET_DSP_MULTIPLY"
1948 "smultb%?\\t%0, %1, %2"
1949 [(set_attr "type" "smulxy")
1950 (set_attr "predicable" "yes")]
1953 (define_insn "*mulhisi3bt"
1954 [(set (match_operand:SI 0 "s_register_operand" "=r")
1955 (mult:SI (sign_extend:SI
1956 (match_operand:HI 1 "s_register_operand" "r"))
1958 (match_operand:SI 2 "s_register_operand" "r")
1960 "TARGET_DSP_MULTIPLY"
1961 "smulbt%?\\t%0, %1, %2"
1962 [(set_attr "type" "smulxy")
1963 (set_attr "predicable" "yes")]
1966 (define_insn "*mulhisi3tt"
1967 [(set (match_operand:SI 0 "s_register_operand" "=r")
1968 (mult:SI (ashiftrt:SI
1969 (match_operand:SI 1 "s_register_operand" "r")
1972 (match_operand:SI 2 "s_register_operand" "r")
1974 "TARGET_DSP_MULTIPLY"
1975 "smultt%?\\t%0, %1, %2"
1976 [(set_attr "type" "smulxy")
1977 (set_attr "predicable" "yes")]
1980 (define_insn "maddhisi4"
1981 [(set (match_operand:SI 0 "s_register_operand" "=r")
1982 (plus:SI (mult:SI (sign_extend:SI
1983 (match_operand:HI 1 "s_register_operand" "r"))
1985 (match_operand:HI 2 "s_register_operand" "r")))
1986 (match_operand:SI 3 "s_register_operand" "r")))]
1987 "TARGET_DSP_MULTIPLY"
1988 "smlabb%?\\t%0, %1, %2, %3"
1989 [(set_attr "type" "smlaxy")
1990 (set_attr "predicable" "yes")]
1993 ;; Note: there is no maddhisi4ibt because this one is canonical form
1994 (define_insn "*maddhisi4tb"
1995 [(set (match_operand:SI 0 "s_register_operand" "=r")
1996 (plus:SI (mult:SI (ashiftrt:SI
1997 (match_operand:SI 1 "s_register_operand" "r")
2000 (match_operand:HI 2 "s_register_operand" "r")))
2001 (match_operand:SI 3 "s_register_operand" "r")))]
2002 "TARGET_DSP_MULTIPLY"
2003 "smlatb%?\\t%0, %1, %2, %3"
2004 [(set_attr "type" "smlaxy")
2005 (set_attr "predicable" "yes")]
2008 (define_insn "*maddhisi4tt"
2009 [(set (match_operand:SI 0 "s_register_operand" "=r")
2010 (plus:SI (mult:SI (ashiftrt:SI
2011 (match_operand:SI 1 "s_register_operand" "r")
2014 (match_operand:SI 2 "s_register_operand" "r")
2016 (match_operand:SI 3 "s_register_operand" "r")))]
2017 "TARGET_DSP_MULTIPLY"
2018 "smlatt%?\\t%0, %1, %2, %3"
2019 [(set_attr "type" "smlaxy")
2020 (set_attr "predicable" "yes")]
2023 (define_insn "maddhidi4"
2024 [(set (match_operand:DI 0 "s_register_operand" "=r")
2026 (mult:DI (sign_extend:DI
2027 (match_operand:HI 1 "s_register_operand" "r"))
2029 (match_operand:HI 2 "s_register_operand" "r")))
2030 (match_operand:DI 3 "s_register_operand" "0")))]
2031 "TARGET_DSP_MULTIPLY"
2032 "smlalbb%?\\t%Q0, %R0, %1, %2"
2033 [(set_attr "type" "smlalxy")
2034 (set_attr "predicable" "yes")])
2036 ;; Note: there is no maddhidi4ibt because this one is canonical form
2037 (define_insn "*maddhidi4tb"
2038 [(set (match_operand:DI 0 "s_register_operand" "=r")
2040 (mult:DI (sign_extend:DI
2042 (match_operand:SI 1 "s_register_operand" "r")
2045 (match_operand:HI 2 "s_register_operand" "r")))
2046 (match_operand:DI 3 "s_register_operand" "0")))]
2047 "TARGET_DSP_MULTIPLY"
2048 "smlaltb%?\\t%Q0, %R0, %1, %2"
2049 [(set_attr "type" "smlalxy")
2050 (set_attr "predicable" "yes")])
2052 (define_insn "*maddhidi4tt"
2053 [(set (match_operand:DI 0 "s_register_operand" "=r")
2055 (mult:DI (sign_extend:DI
2057 (match_operand:SI 1 "s_register_operand" "r")
2061 (match_operand:SI 2 "s_register_operand" "r")
2063 (match_operand:DI 3 "s_register_operand" "0")))]
2064 "TARGET_DSP_MULTIPLY"
2065 "smlaltt%?\\t%Q0, %R0, %1, %2"
2066 [(set_attr "type" "smlalxy")
2067 (set_attr "predicable" "yes")])
2069 (define_expand "mulsf3"
2070 [(set (match_operand:SF 0 "s_register_operand")
2071 (mult:SF (match_operand:SF 1 "s_register_operand")
2072 (match_operand:SF 2 "s_register_operand")))]
2073 "TARGET_32BIT && TARGET_HARD_FLOAT"
2077 (define_expand "muldf3"
2078 [(set (match_operand:DF 0 "s_register_operand")
2079 (mult:DF (match_operand:DF 1 "s_register_operand")
2080 (match_operand:DF 2 "s_register_operand")))]
2081 "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
2087 (define_expand "divsf3"
2088 [(set (match_operand:SF 0 "s_register_operand")
2089 (div:SF (match_operand:SF 1 "s_register_operand")
2090 (match_operand:SF 2 "s_register_operand")))]
2091 "TARGET_32BIT && TARGET_HARD_FLOAT"
2094 (define_expand "divdf3"
2095 [(set (match_operand:DF 0 "s_register_operand")
2096 (div:DF (match_operand:DF 1 "s_register_operand")
2097 (match_operand:DF 2 "s_register_operand")))]
2098 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
2102 ;; Split DImode and, ior, xor operations. Simply perform the logical
2103 ;; operation on the upper and lower halves of the registers.
2104 ;; This is needed for atomic operations in arm_split_atomic_op.
2105 ;; Avoid splitting IWMMXT instructions.
2107 [(set (match_operand:DI 0 "s_register_operand" "")
2108 (match_operator:DI 6 "logical_binary_operator"
2109 [(match_operand:DI 1 "s_register_operand" "")
2110 (match_operand:DI 2 "s_register_operand" "")]))]
2111 "TARGET_32BIT && reload_completed
2112 && ! IS_IWMMXT_REGNUM (REGNO (operands[0]))"
2113 [(set (match_dup 0) (match_op_dup:SI 6 [(match_dup 1) (match_dup 2)]))
2114 (set (match_dup 3) (match_op_dup:SI 6 [(match_dup 4) (match_dup 5)]))]
2117 operands[3] = gen_highpart (SImode, operands[0]);
2118 operands[0] = gen_lowpart (SImode, operands[0]);
2119 operands[4] = gen_highpart (SImode, operands[1]);
2120 operands[1] = gen_lowpart (SImode, operands[1]);
2121 operands[5] = gen_highpart (SImode, operands[2]);
2122 operands[2] = gen_lowpart (SImode, operands[2]);
2126 ;; Split DImode not (needed for atomic operations in arm_split_atomic_op).
2127 ;; Unconditionally split since there is no SIMD DImode NOT pattern.
2129 [(set (match_operand:DI 0 "s_register_operand")
2130 (not:DI (match_operand:DI 1 "s_register_operand")))]
2132 [(set (match_dup 0) (not:SI (match_dup 1)))
2133 (set (match_dup 2) (not:SI (match_dup 3)))]
2136 operands[2] = gen_highpart (SImode, operands[0]);
2137 operands[0] = gen_lowpart (SImode, operands[0]);
2138 operands[3] = gen_highpart (SImode, operands[1]);
2139 operands[1] = gen_lowpart (SImode, operands[1]);
2143 (define_expand "andsi3"
2144 [(set (match_operand:SI 0 "s_register_operand")
2145 (and:SI (match_operand:SI 1 "s_register_operand")
2146 (match_operand:SI 2 "reg_or_int_operand")))]
2151 if (CONST_INT_P (operands[2]))
2153 if (INTVAL (operands[2]) == 255 && arm_arch6)
2155 operands[1] = convert_to_mode (QImode, operands[1], 1);
2156 emit_insn (gen_thumb2_zero_extendqisi2_v6 (operands[0],
2160 else if (DONT_EARLY_SPLIT_CONSTANT (INTVAL (operands[2]), AND))
2161 operands[2] = force_reg (SImode, operands[2]);
2164 arm_split_constant (AND, SImode, NULL_RTX,
2165 INTVAL (operands[2]), operands[0],
2167 optimize && can_create_pseudo_p ());
2173 else /* TARGET_THUMB1 */
2175 if (!CONST_INT_P (operands[2]))
2177 rtx tmp = force_reg (SImode, operands[2]);
2178 if (rtx_equal_p (operands[0], operands[1]))
2182 operands[2] = operands[1];
2190 if (((unsigned HOST_WIDE_INT) ~INTVAL (operands[2])) < 256)
2192 operands[2] = force_reg (SImode,
2193 GEN_INT (~INTVAL (operands[2])));
2195 emit_insn (gen_thumb1_bicsi3 (operands[0], operands[2], operands[1]));
2200 for (i = 9; i <= 31; i++)
2202 if ((HOST_WIDE_INT_1 << i) - 1 == INTVAL (operands[2]))
2204 emit_insn (gen_extzv (operands[0], operands[1], GEN_INT (i),
2208 else if ((HOST_WIDE_INT_1 << i) - 1
2209 == ~INTVAL (operands[2]))
2211 rtx shift = GEN_INT (i);
2212 rtx reg = gen_reg_rtx (SImode);
2214 emit_insn (gen_lshrsi3 (reg, operands[1], shift));
2215 emit_insn (gen_ashlsi3 (operands[0], reg, shift));
2221 operands[2] = force_reg (SImode, operands[2]);
2227 ; ??? Check split length for Thumb-2
2228 (define_insn_and_split "*arm_andsi3_insn"
2229 [(set (match_operand:SI 0 "s_register_operand" "=r,l,r,r,r")
2230 (and:SI (match_operand:SI 1 "s_register_operand" "%r,0,r,r,r")
2231 (match_operand:SI 2 "reg_or_int_operand" "I,l,K,r,?n")))]
2236 bic%?\\t%0, %1, #%B2
2240 && CONST_INT_P (operands[2])
2241 && !(const_ok_for_arm (INTVAL (operands[2]))
2242 || const_ok_for_arm (~INTVAL (operands[2])))"
2243 [(clobber (const_int 0))]
2245 arm_split_constant (AND, SImode, curr_insn,
2246 INTVAL (operands[2]), operands[0], operands[1], 0);
2249 [(set_attr "length" "4,4,4,4,16")
2250 (set_attr "predicable" "yes")
2251 (set_attr "predicable_short_it" "no,yes,no,no,no")
2252 (set_attr "type" "logic_imm,logic_imm,logic_reg,logic_reg,logic_imm")]
2255 (define_insn "*andsi3_compare0"
2256 [(set (reg:CC_NOOV CC_REGNUM)
2258 (and:SI (match_operand:SI 1 "s_register_operand" "r,r,r")
2259 (match_operand:SI 2 "arm_not_operand" "I,K,r"))
2261 (set (match_operand:SI 0 "s_register_operand" "=r,r,r")
2262 (and:SI (match_dup 1) (match_dup 2)))]
2266 bics%?\\t%0, %1, #%B2
2267 ands%?\\t%0, %1, %2"
2268 [(set_attr "conds" "set")
2269 (set_attr "type" "logics_imm,logics_imm,logics_reg")]
2272 (define_insn "*andsi3_compare0_scratch"
2273 [(set (reg:CC_NOOV CC_REGNUM)
2275 (and:SI (match_operand:SI 0 "s_register_operand" "r,r,r")
2276 (match_operand:SI 1 "arm_not_operand" "I,K,r"))
2278 (clobber (match_scratch:SI 2 "=X,r,X"))]
2282 bics%?\\t%2, %0, #%B1
2284 [(set_attr "conds" "set")
2285 (set_attr "type" "logics_imm,logics_imm,logics_reg")]
2288 (define_insn "*zeroextractsi_compare0_scratch"
2289 [(set (reg:CC_NOOV CC_REGNUM)
2290 (compare:CC_NOOV (zero_extract:SI
2291 (match_operand:SI 0 "s_register_operand" "r")
2292 (match_operand 1 "const_int_operand" "n")
2293 (match_operand 2 "const_int_operand" "n"))
2296 && (INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) < 32
2297 && INTVAL (operands[1]) > 0
2298 && INTVAL (operands[1]) + (INTVAL (operands[2]) & 1) <= 8
2299 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32)"
2301 operands[1] = GEN_INT (((1 << INTVAL (operands[1])) - 1)
2302 << INTVAL (operands[2]));
2303 output_asm_insn (\"tst%?\\t%0, %1\", operands);
2306 [(set_attr "conds" "set")
2307 (set_attr "predicable" "yes")
2308 (set_attr "type" "logics_imm")]
2311 (define_insn_and_split "*ne_zeroextractsi"
2312 [(set (match_operand:SI 0 "s_register_operand" "=r")
2313 (ne:SI (zero_extract:SI
2314 (match_operand:SI 1 "s_register_operand" "r")
2315 (match_operand:SI 2 "const_int_operand" "n")
2316 (match_operand:SI 3 "const_int_operand" "n"))
2318 (clobber (reg:CC CC_REGNUM))]
2320 && (INTVAL (operands[3]) >= 0 && INTVAL (operands[3]) < 32
2321 && INTVAL (operands[2]) > 0
2322 && INTVAL (operands[2]) + (INTVAL (operands[3]) & 1) <= 8
2323 && INTVAL (operands[2]) + INTVAL (operands[3]) <= 32)"
2326 && (INTVAL (operands[3]) >= 0 && INTVAL (operands[3]) < 32
2327 && INTVAL (operands[2]) > 0
2328 && INTVAL (operands[2]) + (INTVAL (operands[3]) & 1) <= 8
2329 && INTVAL (operands[2]) + INTVAL (operands[3]) <= 32)"
2330 [(parallel [(set (reg:CC_NOOV CC_REGNUM)
2331 (compare:CC_NOOV (and:SI (match_dup 1) (match_dup 2))
2333 (set (match_dup 0) (and:SI (match_dup 1) (match_dup 2)))])
2335 (if_then_else:SI (eq (reg:CC_NOOV CC_REGNUM) (const_int 0))
2336 (match_dup 0) (const_int 1)))]
2338 operands[2] = GEN_INT (((1 << INTVAL (operands[2])) - 1)
2339 << INTVAL (operands[3]));
2341 [(set_attr "conds" "clob")
2342 (set (attr "length")
2343 (if_then_else (eq_attr "is_thumb" "yes")
2346 (set_attr "type" "multiple")]
2349 (define_insn_and_split "*ne_zeroextractsi_shifted"
2350 [(set (match_operand:SI 0 "s_register_operand" "=r")
2351 (ne:SI (zero_extract:SI
2352 (match_operand:SI 1 "s_register_operand" "r")
2353 (match_operand:SI 2 "const_int_operand" "n")
2356 (clobber (reg:CC CC_REGNUM))]
2360 [(parallel [(set (reg:CC_NOOV CC_REGNUM)
2361 (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2))
2363 (set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))])
2365 (if_then_else:SI (eq (reg:CC_NOOV CC_REGNUM) (const_int 0))
2366 (match_dup 0) (const_int 1)))]
2368 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2370 [(set_attr "conds" "clob")
2371 (set_attr "length" "8")
2372 (set_attr "type" "multiple")]
2375 (define_insn_and_split "*ite_ne_zeroextractsi"
2376 [(set (match_operand:SI 0 "s_register_operand" "=r")
2377 (if_then_else:SI (ne (zero_extract:SI
2378 (match_operand:SI 1 "s_register_operand" "r")
2379 (match_operand:SI 2 "const_int_operand" "n")
2380 (match_operand:SI 3 "const_int_operand" "n"))
2382 (match_operand:SI 4 "arm_not_operand" "rIK")
2384 (clobber (reg:CC CC_REGNUM))]
2386 && (INTVAL (operands[3]) >= 0 && INTVAL (operands[3]) < 32
2387 && INTVAL (operands[2]) > 0
2388 && INTVAL (operands[2]) + (INTVAL (operands[3]) & 1) <= 8
2389 && INTVAL (operands[2]) + INTVAL (operands[3]) <= 32)
2390 && !reg_overlap_mentioned_p (operands[0], operands[4])"
2393 && (INTVAL (operands[3]) >= 0 && INTVAL (operands[3]) < 32
2394 && INTVAL (operands[2]) > 0
2395 && INTVAL (operands[2]) + (INTVAL (operands[3]) & 1) <= 8
2396 && INTVAL (operands[2]) + INTVAL (operands[3]) <= 32)
2397 && !reg_overlap_mentioned_p (operands[0], operands[4])"
2398 [(parallel [(set (reg:CC_NOOV CC_REGNUM)
2399 (compare:CC_NOOV (and:SI (match_dup 1) (match_dup 2))
2401 (set (match_dup 0) (and:SI (match_dup 1) (match_dup 2)))])
2403 (if_then_else:SI (eq (reg:CC_NOOV CC_REGNUM) (const_int 0))
2404 (match_dup 0) (match_dup 4)))]
2406 operands[2] = GEN_INT (((1 << INTVAL (operands[2])) - 1)
2407 << INTVAL (operands[3]));
2409 [(set_attr "conds" "clob")
2410 (set_attr "length" "8")
2411 (set_attr "type" "multiple")]
2414 (define_insn_and_split "*ite_ne_zeroextractsi_shifted"
2415 [(set (match_operand:SI 0 "s_register_operand" "=r")
2416 (if_then_else:SI (ne (zero_extract:SI
2417 (match_operand:SI 1 "s_register_operand" "r")
2418 (match_operand:SI 2 "const_int_operand" "n")
2421 (match_operand:SI 3 "arm_not_operand" "rIK")
2423 (clobber (reg:CC CC_REGNUM))]
2424 "TARGET_ARM && !reg_overlap_mentioned_p (operands[0], operands[3])"
2426 "TARGET_ARM && !reg_overlap_mentioned_p (operands[0], operands[3])"
2427 [(parallel [(set (reg:CC_NOOV CC_REGNUM)
2428 (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2))
2430 (set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))])
2432 (if_then_else:SI (eq (reg:CC_NOOV CC_REGNUM) (const_int 0))
2433 (match_dup 0) (match_dup 3)))]
2435 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2437 [(set_attr "conds" "clob")
2438 (set_attr "length" "8")
2439 (set_attr "type" "multiple")]
2442 ;; ??? Use Thumb-2 has bitfield insert/extract instructions.
2444 [(set (match_operand:SI 0 "s_register_operand" "")
2445 (match_operator:SI 1 "shiftable_operator"
2446 [(zero_extract:SI (match_operand:SI 2 "s_register_operand" "")
2447 (match_operand:SI 3 "const_int_operand" "")
2448 (match_operand:SI 4 "const_int_operand" ""))
2449 (match_operand:SI 5 "s_register_operand" "")]))
2450 (clobber (match_operand:SI 6 "s_register_operand" ""))]
2452 [(set (match_dup 6) (ashift:SI (match_dup 2) (match_dup 3)))
2455 [(lshiftrt:SI (match_dup 6) (match_dup 4))
2458 HOST_WIDE_INT temp = INTVAL (operands[3]);
2460 operands[3] = GEN_INT (32 - temp - INTVAL (operands[4]));
2461 operands[4] = GEN_INT (32 - temp);
2466 [(set (match_operand:SI 0 "s_register_operand" "")
2467 (match_operator:SI 1 "shiftable_operator"
2468 [(sign_extract:SI (match_operand:SI 2 "s_register_operand" "")
2469 (match_operand:SI 3 "const_int_operand" "")
2470 (match_operand:SI 4 "const_int_operand" ""))
2471 (match_operand:SI 5 "s_register_operand" "")]))
2472 (clobber (match_operand:SI 6 "s_register_operand" ""))]
2474 [(set (match_dup 6) (ashift:SI (match_dup 2) (match_dup 3)))
2477 [(ashiftrt:SI (match_dup 6) (match_dup 4))
2480 HOST_WIDE_INT temp = INTVAL (operands[3]);
2482 operands[3] = GEN_INT (32 - temp - INTVAL (operands[4]));
2483 operands[4] = GEN_INT (32 - temp);
2487 ;;; ??? This pattern is bogus. If operand3 has bits outside the range
2488 ;;; represented by the bitfield, then this will produce incorrect results.
2489 ;;; Somewhere, the value needs to be truncated. On targets like the m68k,
2490 ;;; which have a real bit-field insert instruction, the truncation happens
2491 ;;; in the bit-field insert instruction itself. Since arm does not have a
2492 ;;; bit-field insert instruction, we would have to emit code here to truncate
2493 ;;; the value before we insert. This loses some of the advantage of having
2494 ;;; this insv pattern, so this pattern needs to be reevalutated.
2496 (define_expand "insv"
2497 [(set (zero_extract (match_operand 0 "nonimmediate_operand")
2498 (match_operand 1 "general_operand")
2499 (match_operand 2 "general_operand"))
2500 (match_operand 3 "reg_or_int_operand"))]
2501 "TARGET_ARM || arm_arch_thumb2"
2504 int start_bit = INTVAL (operands[2]);
2505 int width = INTVAL (operands[1]);
2506 HOST_WIDE_INT mask = (HOST_WIDE_INT_1 << width) - 1;
2507 rtx target, subtarget;
2509 if (arm_arch_thumb2)
2511 if (unaligned_access && MEM_P (operands[0])
2512 && s_register_operand (operands[3], GET_MODE (operands[3]))
2513 && (width == 16 || width == 32) && (start_bit % BITS_PER_UNIT) == 0)
2517 if (BYTES_BIG_ENDIAN)
2518 start_bit = GET_MODE_BITSIZE (GET_MODE (operands[3])) - width
2523 base_addr = adjust_address (operands[0], SImode,
2524 start_bit / BITS_PER_UNIT);
2525 emit_insn (gen_unaligned_storesi (base_addr, operands[3]));
2529 rtx tmp = gen_reg_rtx (HImode);
2531 base_addr = adjust_address (operands[0], HImode,
2532 start_bit / BITS_PER_UNIT);
2533 emit_move_insn (tmp, gen_lowpart (HImode, operands[3]));
2534 emit_insn (gen_unaligned_storehi (base_addr, tmp));
2538 else if (s_register_operand (operands[0], GET_MODE (operands[0])))
2540 bool use_bfi = TRUE;
2542 if (CONST_INT_P (operands[3]))
2544 HOST_WIDE_INT val = INTVAL (operands[3]) & mask;
2548 emit_insn (gen_insv_zero (operands[0], operands[1],
2553 /* See if the set can be done with a single orr instruction. */
2554 if (val == mask && const_ok_for_arm (val << start_bit))
2560 if (!REG_P (operands[3]))
2561 operands[3] = force_reg (SImode, operands[3]);
2563 emit_insn (gen_insv_t2 (operands[0], operands[1], operands[2],
2572 if (!s_register_operand (operands[0], GET_MODE (operands[0])))
2575 target = copy_rtx (operands[0]);
2576 /* Avoid using a subreg as a subtarget, and avoid writing a paradoxical
2577 subreg as the final target. */
2578 if (GET_CODE (target) == SUBREG)
2580 subtarget = gen_reg_rtx (SImode);
2581 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (target)))
2582 < GET_MODE_SIZE (SImode))
2583 target = SUBREG_REG (target);
2588 if (CONST_INT_P (operands[3]))
2590 /* Since we are inserting a known constant, we may be able to
2591 reduce the number of bits that we have to clear so that
2592 the mask becomes simple. */
2593 /* ??? This code does not check to see if the new mask is actually
2594 simpler. It may not be. */
2595 rtx op1 = gen_reg_rtx (SImode);
2596 /* ??? Truncate operand3 to fit in the bitfield. See comment before
2597 start of this pattern. */
2598 HOST_WIDE_INT op3_value = mask & INTVAL (operands[3]);
2599 HOST_WIDE_INT mask2 = ((mask & ~op3_value) << start_bit);
2601 emit_insn (gen_andsi3 (op1, operands[0],
2602 gen_int_mode (~mask2, SImode)));
2603 emit_insn (gen_iorsi3 (subtarget, op1,
2604 gen_int_mode (op3_value << start_bit, SImode)));
2606 else if (start_bit == 0
2607 && !(const_ok_for_arm (mask)
2608 || const_ok_for_arm (~mask)))
2610 /* A Trick, since we are setting the bottom bits in the word,
2611 we can shift operand[3] up, operand[0] down, OR them together
2612 and rotate the result back again. This takes 3 insns, and
2613 the third might be mergeable into another op. */
2614 /* The shift up copes with the possibility that operand[3] is
2615 wider than the bitfield. */
2616 rtx op0 = gen_reg_rtx (SImode);
2617 rtx op1 = gen_reg_rtx (SImode);
2619 emit_insn (gen_ashlsi3 (op0, operands[3], GEN_INT (32 - width)));
2620 emit_insn (gen_lshrsi3 (op1, operands[0], operands[1]));
2621 emit_insn (gen_iorsi3 (op1, op1, op0));
2622 emit_insn (gen_rotlsi3 (subtarget, op1, operands[1]));
2624 else if ((width + start_bit == 32)
2625 && !(const_ok_for_arm (mask)
2626 || const_ok_for_arm (~mask)))
2628 /* Similar trick, but slightly less efficient. */
2630 rtx op0 = gen_reg_rtx (SImode);
2631 rtx op1 = gen_reg_rtx (SImode);
2633 emit_insn (gen_ashlsi3 (op0, operands[3], GEN_INT (32 - width)));
2634 emit_insn (gen_ashlsi3 (op1, operands[0], operands[1]));
2635 emit_insn (gen_lshrsi3 (op1, op1, operands[1]));
2636 emit_insn (gen_iorsi3 (subtarget, op1, op0));
2640 rtx op0 = gen_int_mode (mask, SImode);
2641 rtx op1 = gen_reg_rtx (SImode);
2642 rtx op2 = gen_reg_rtx (SImode);
2644 if (!(const_ok_for_arm (mask) || const_ok_for_arm (~mask)))
2646 rtx tmp = gen_reg_rtx (SImode);
2648 emit_insn (gen_movsi (tmp, op0));
2652 /* Mask out any bits in operand[3] that are not needed. */
2653 emit_insn (gen_andsi3 (op1, operands[3], op0));
2655 if (CONST_INT_P (op0)
2656 && (const_ok_for_arm (mask << start_bit)
2657 || const_ok_for_arm (~(mask << start_bit))))
2659 op0 = gen_int_mode (~(mask << start_bit), SImode);
2660 emit_insn (gen_andsi3 (op2, operands[0], op0));
2664 if (CONST_INT_P (op0))
2666 rtx tmp = gen_reg_rtx (SImode);
2668 emit_insn (gen_movsi (tmp, op0));
2673 emit_insn (gen_ashlsi3 (op0, op0, operands[2]));
2675 emit_insn (gen_andsi_notsi_si (op2, operands[0], op0));
2679 emit_insn (gen_ashlsi3 (op1, op1, operands[2]));
2681 emit_insn (gen_iorsi3 (subtarget, op1, op2));
2684 if (subtarget != target)
2686 /* If TARGET is still a SUBREG, then it must be wider than a word,
2687 so we must be careful only to set the subword we were asked to. */
2688 if (GET_CODE (target) == SUBREG)
2689 emit_move_insn (target, subtarget);
2691 emit_move_insn (target, gen_lowpart (GET_MODE (target), subtarget));
2698 (define_insn "insv_zero"
2699 [(set (zero_extract:SI (match_operand:SI 0 "s_register_operand" "+r")
2700 (match_operand:SI 1 "const_int_M_operand" "M")
2701 (match_operand:SI 2 "const_int_M_operand" "M"))
2705 [(set_attr "length" "4")
2706 (set_attr "predicable" "yes")
2707 (set_attr "type" "bfm")]
2710 (define_insn "insv_t2"
2711 [(set (zero_extract:SI (match_operand:SI 0 "s_register_operand" "+r")
2712 (match_operand:SI 1 "const_int_M_operand" "M")
2713 (match_operand:SI 2 "const_int_M_operand" "M"))
2714 (match_operand:SI 3 "s_register_operand" "r"))]
2716 "bfi%?\t%0, %3, %2, %1"
2717 [(set_attr "length" "4")
2718 (set_attr "predicable" "yes")
2719 (set_attr "type" "bfm")]
2722 (define_insn "andsi_notsi_si"
2723 [(set (match_operand:SI 0 "s_register_operand" "=r")
2724 (and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
2725 (match_operand:SI 1 "s_register_operand" "r")))]
2727 "bic%?\\t%0, %1, %2"
2728 [(set_attr "predicable" "yes")
2729 (set_attr "type" "logic_reg")]
2732 (define_insn "andsi_not_shiftsi_si"
2733 [(set (match_operand:SI 0 "s_register_operand" "=r")
2734 (and:SI (not:SI (match_operator:SI 4 "shift_operator"
2735 [(match_operand:SI 2 "s_register_operand" "r")
2736 (match_operand:SI 3 "arm_rhs_operand" "rM")]))
2737 (match_operand:SI 1 "s_register_operand" "r")))]
2739 "bic%?\\t%0, %1, %2%S4"
2740 [(set_attr "predicable" "yes")
2741 (set_attr "shift" "2")
2742 (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "")
2743 (const_string "logic_shift_imm")
2744 (const_string "logic_shift_reg")))]
2747 ;; Shifted bics pattern used to set up CC status register and not reusing
2748 ;; bics output. Pattern restricts Thumb2 shift operand as bics for Thumb2
2749 ;; does not support shift by register.
2750 (define_insn "andsi_not_shiftsi_si_scc_no_reuse"
2751 [(set (reg:CC_NOOV CC_REGNUM)
2753 (and:SI (not:SI (match_operator:SI 0 "shift_operator"
2754 [(match_operand:SI 1 "s_register_operand" "r")
2755 (match_operand:SI 2 "arm_rhs_operand" "rM")]))
2756 (match_operand:SI 3 "s_register_operand" "r"))
2758 (clobber (match_scratch:SI 4 "=r"))]
2759 "TARGET_ARM || (TARGET_THUMB2 && CONST_INT_P (operands[2]))"
2760 "bics%?\\t%4, %3, %1%S0"
2761 [(set_attr "predicable" "yes")
2762 (set_attr "conds" "set")
2763 (set_attr "shift" "1")
2764 (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
2765 (const_string "logic_shift_imm")
2766 (const_string "logic_shift_reg")))]
2769 ;; Same as andsi_not_shiftsi_si_scc_no_reuse, but the bics result is also
2770 ;; getting reused later.
2771 (define_insn "andsi_not_shiftsi_si_scc"
2772 [(parallel [(set (reg:CC_NOOV CC_REGNUM)
2774 (and:SI (not:SI (match_operator:SI 0 "shift_operator"
2775 [(match_operand:SI 1 "s_register_operand" "r")
2776 (match_operand:SI 2 "arm_rhs_operand" "rM")]))
2777 (match_operand:SI 3 "s_register_operand" "r"))
2779 (set (match_operand:SI 4 "s_register_operand" "=r")
2780 (and:SI (not:SI (match_op_dup 0
2784 "TARGET_ARM || (TARGET_THUMB2 && CONST_INT_P (operands[2]))"
2785 "bics%?\\t%4, %3, %1%S0"
2786 [(set_attr "predicable" "yes")
2787 (set_attr "conds" "set")
2788 (set_attr "shift" "1")
2789 (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
2790 (const_string "logic_shift_imm")
2791 (const_string "logic_shift_reg")))]
2794 (define_insn "*andsi_notsi_si_compare0"
2795 [(set (reg:CC_NOOV CC_REGNUM)
2797 (and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
2798 (match_operand:SI 1 "s_register_operand" "r"))
2800 (set (match_operand:SI 0 "s_register_operand" "=r")
2801 (and:SI (not:SI (match_dup 2)) (match_dup 1)))]
2804 [(set_attr "conds" "set")
2805 (set_attr "type" "logics_shift_reg")]
2808 (define_insn "*andsi_notsi_si_compare0_scratch"
2809 [(set (reg:CC_NOOV CC_REGNUM)
2811 (and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
2812 (match_operand:SI 1 "s_register_operand" "r"))
2814 (clobber (match_scratch:SI 0 "=r"))]
2817 [(set_attr "conds" "set")
2818 (set_attr "type" "logics_shift_reg")]
2821 (define_expand "iorsi3"
2822 [(set (match_operand:SI 0 "s_register_operand")
2823 (ior:SI (match_operand:SI 1 "s_register_operand")
2824 (match_operand:SI 2 "reg_or_int_operand")))]
2827 if (CONST_INT_P (operands[2]))
2831 if (DONT_EARLY_SPLIT_CONSTANT (INTVAL (operands[2]), IOR))
2832 operands[2] = force_reg (SImode, operands[2]);
2835 arm_split_constant (IOR, SImode, NULL_RTX,
2836 INTVAL (operands[2]), operands[0],
2838 optimize && can_create_pseudo_p ());
2842 else /* TARGET_THUMB1 */
2844 rtx tmp = force_reg (SImode, operands[2]);
2845 if (rtx_equal_p (operands[0], operands[1]))
2849 operands[2] = operands[1];
2857 (define_insn_and_split "*iorsi3_insn"
2858 [(set (match_operand:SI 0 "s_register_operand" "=r,l,r,r,r")
2859 (ior:SI (match_operand:SI 1 "s_register_operand" "%r,0,r,r,r")
2860 (match_operand:SI 2 "reg_or_int_operand" "I,l,K,r,?n")))]
2865 orn%?\\t%0, %1, #%B2
2869 && CONST_INT_P (operands[2])
2870 && !(const_ok_for_arm (INTVAL (operands[2]))
2871 || (TARGET_THUMB2 && const_ok_for_arm (~INTVAL (operands[2]))))"
2872 [(clobber (const_int 0))]
2874 arm_split_constant (IOR, SImode, curr_insn,
2875 INTVAL (operands[2]), operands[0], operands[1], 0);
2878 [(set_attr "length" "4,4,4,4,16")
2879 (set_attr "arch" "32,t2,t2,32,32")
2880 (set_attr "predicable" "yes")
2881 (set_attr "predicable_short_it" "no,yes,no,no,no")
2882 (set_attr "type" "logic_imm,logic_reg,logic_imm,logic_reg,logic_reg")]
2886 [(match_scratch:SI 3 "r")
2887 (set (match_operand:SI 0 "arm_general_register_operand" "")
2888 (ior:SI (match_operand:SI 1 "arm_general_register_operand" "")
2889 (match_operand:SI 2 "const_int_operand" "")))]
2891 && !const_ok_for_arm (INTVAL (operands[2]))
2892 && const_ok_for_arm (~INTVAL (operands[2]))"
2893 [(set (match_dup 3) (match_dup 2))
2894 (set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3)))]
2898 (define_insn "*iorsi3_compare0"
2899 [(set (reg:CC_NOOV CC_REGNUM)
2901 (ior:SI (match_operand:SI 1 "s_register_operand" "%r,0,r")
2902 (match_operand:SI 2 "arm_rhs_operand" "I,l,r"))
2904 (set (match_operand:SI 0 "s_register_operand" "=r,l,r")
2905 (ior:SI (match_dup 1) (match_dup 2)))]
2907 "orrs%?\\t%0, %1, %2"
2908 [(set_attr "conds" "set")
2909 (set_attr "arch" "*,t2,*")
2910 (set_attr "length" "4,2,4")
2911 (set_attr "type" "logics_imm,logics_reg,logics_reg")]
2914 (define_insn "*iorsi3_compare0_scratch"
2915 [(set (reg:CC_NOOV CC_REGNUM)
2917 (ior:SI (match_operand:SI 1 "s_register_operand" "%r,0,r")
2918 (match_operand:SI 2 "arm_rhs_operand" "I,l,r"))
2920 (clobber (match_scratch:SI 0 "=r,l,r"))]
2922 "orrs%?\\t%0, %1, %2"
2923 [(set_attr "conds" "set")
2924 (set_attr "arch" "*,t2,*")
2925 (set_attr "length" "4,2,4")
2926 (set_attr "type" "logics_imm,logics_reg,logics_reg")]
2929 (define_expand "xorsi3"
2930 [(set (match_operand:SI 0 "s_register_operand")
2931 (xor:SI (match_operand:SI 1 "s_register_operand")
2932 (match_operand:SI 2 "reg_or_int_operand")))]
2934 "if (CONST_INT_P (operands[2]))
2938 if (DONT_EARLY_SPLIT_CONSTANT (INTVAL (operands[2]), XOR))
2939 operands[2] = force_reg (SImode, operands[2]);
2942 arm_split_constant (XOR, SImode, NULL_RTX,
2943 INTVAL (operands[2]), operands[0],
2945 optimize && can_create_pseudo_p ());
2949 else /* TARGET_THUMB1 */
2951 rtx tmp = force_reg (SImode, operands[2]);
2952 if (rtx_equal_p (operands[0], operands[1]))
2956 operands[2] = operands[1];
2963 (define_insn_and_split "*arm_xorsi3"
2964 [(set (match_operand:SI 0 "s_register_operand" "=r,l,r,r")
2965 (xor:SI (match_operand:SI 1 "s_register_operand" "%r,0,r,r")
2966 (match_operand:SI 2 "reg_or_int_operand" "I,l,r,?n")))]
2974 && CONST_INT_P (operands[2])
2975 && !const_ok_for_arm (INTVAL (operands[2]))"
2976 [(clobber (const_int 0))]
2978 arm_split_constant (XOR, SImode, curr_insn,
2979 INTVAL (operands[2]), operands[0], operands[1], 0);
2982 [(set_attr "length" "4,4,4,16")
2983 (set_attr "predicable" "yes")
2984 (set_attr "predicable_short_it" "no,yes,no,no")
2985 (set_attr "type" "logic_imm,logic_reg,logic_reg,multiple")]
2988 (define_insn "*xorsi3_compare0"
2989 [(set (reg:CC_NOOV CC_REGNUM)
2990 (compare:CC_NOOV (xor:SI (match_operand:SI 1 "s_register_operand" "r,r")
2991 (match_operand:SI 2 "arm_rhs_operand" "I,r"))
2993 (set (match_operand:SI 0 "s_register_operand" "=r,r")
2994 (xor:SI (match_dup 1) (match_dup 2)))]
2996 "eors%?\\t%0, %1, %2"
2997 [(set_attr "conds" "set")
2998 (set_attr "type" "logics_imm,logics_reg")]
3001 (define_insn "*xorsi3_compare0_scratch"
3002 [(set (reg:CC_NOOV CC_REGNUM)
3003 (compare:CC_NOOV (xor:SI (match_operand:SI 0 "s_register_operand" "r,r")
3004 (match_operand:SI 1 "arm_rhs_operand" "I,r"))
3008 [(set_attr "conds" "set")
3009 (set_attr "type" "logics_imm,logics_reg")]
3012 ; By splitting (IOR (AND (NOT A) (NOT B)) C) as D = AND (IOR A B) (NOT C),
3013 ; (NOT D) we can sometimes merge the final NOT into one of the following
3017 [(set (match_operand:SI 0 "s_register_operand" "")
3018 (ior:SI (and:SI (not:SI (match_operand:SI 1 "s_register_operand" ""))
3019 (not:SI (match_operand:SI 2 "arm_rhs_operand" "")))
3020 (match_operand:SI 3 "arm_rhs_operand" "")))
3021 (clobber (match_operand:SI 4 "s_register_operand" ""))]
3023 [(set (match_dup 4) (and:SI (ior:SI (match_dup 1) (match_dup 2))
3024 (not:SI (match_dup 3))))
3025 (set (match_dup 0) (not:SI (match_dup 4)))]
3029 (define_insn_and_split "*andsi_iorsi3_notsi"
3030 [(set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r")
3031 (and:SI (ior:SI (match_operand:SI 1 "s_register_operand" "%0,r,r")
3032 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))
3033 (not:SI (match_operand:SI 3 "arm_rhs_operand" "rI,rI,rI"))))]
3035 "#" ; "orr%?\\t%0, %1, %2\;bic%?\\t%0, %0, %3"
3036 "&& reload_completed"
3037 [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 2)))
3038 (set (match_dup 0) (and:SI (match_dup 4) (match_dup 5)))]
3040 /* If operands[3] is a constant make sure to fold the NOT into it
3041 to avoid creating a NOT of a CONST_INT. */
3042 rtx not_rtx = simplify_gen_unary (NOT, SImode, operands[3], SImode);
3043 if (CONST_INT_P (not_rtx))
3045 operands[4] = operands[0];
3046 operands[5] = not_rtx;
3050 operands[5] = operands[0];
3051 operands[4] = not_rtx;
3054 [(set_attr "length" "8")
3055 (set_attr "ce_count" "2")
3056 (set_attr "predicable" "yes")
3057 (set_attr "type" "multiple")]
3060 ; ??? Are these four splitters still beneficial when the Thumb-2 bitfield
3061 ; insns are available?
3063 [(set (match_operand:SI 0 "s_register_operand" "")
3064 (match_operator:SI 1 "logical_binary_operator"
3065 [(zero_extract:SI (match_operand:SI 2 "s_register_operand" "")
3066 (match_operand:SI 3 "const_int_operand" "")
3067 (match_operand:SI 4 "const_int_operand" ""))
3068 (match_operator:SI 9 "logical_binary_operator"
3069 [(lshiftrt:SI (match_operand:SI 5 "s_register_operand" "")
3070 (match_operand:SI 6 "const_int_operand" ""))
3071 (match_operand:SI 7 "s_register_operand" "")])]))
3072 (clobber (match_operand:SI 8 "s_register_operand" ""))]
3074 && GET_CODE (operands[1]) == GET_CODE (operands[9])
3075 && INTVAL (operands[3]) == 32 - INTVAL (operands[6])"
3078 [(ashift:SI (match_dup 2) (match_dup 4))
3082 [(lshiftrt:SI (match_dup 8) (match_dup 6))
3085 operands[4] = GEN_INT (32 - (INTVAL (operands[3]) + INTVAL (operands[4])));
3089 [(set (match_operand:SI 0 "s_register_operand" "")
3090 (match_operator:SI 1 "logical_binary_operator"
3091 [(match_operator:SI 9 "logical_binary_operator"
3092 [(lshiftrt:SI (match_operand:SI 5 "s_register_operand" "")
3093 (match_operand:SI 6 "const_int_operand" ""))
3094 (match_operand:SI 7 "s_register_operand" "")])
3095 (zero_extract:SI (match_operand:SI 2 "s_register_operand" "")
3096 (match_operand:SI 3 "const_int_operand" "")
3097 (match_operand:SI 4 "const_int_operand" ""))]))
3098 (clobber (match_operand:SI 8 "s_register_operand" ""))]
3100 && GET_CODE (operands[1]) == GET_CODE (operands[9])
3101 && INTVAL (operands[3]) == 32 - INTVAL (operands[6])"
3104 [(ashift:SI (match_dup 2) (match_dup 4))
3108 [(lshiftrt:SI (match_dup 8) (match_dup 6))
3111 operands[4] = GEN_INT (32 - (INTVAL (operands[3]) + INTVAL (operands[4])));
3115 [(set (match_operand:SI 0 "s_register_operand" "")
3116 (match_operator:SI 1 "logical_binary_operator"
3117 [(sign_extract:SI (match_operand:SI 2 "s_register_operand" "")
3118 (match_operand:SI 3 "const_int_operand" "")
3119 (match_operand:SI 4 "const_int_operand" ""))
3120 (match_operator:SI 9 "logical_binary_operator"
3121 [(ashiftrt:SI (match_operand:SI 5 "s_register_operand" "")
3122 (match_operand:SI 6 "const_int_operand" ""))
3123 (match_operand:SI 7 "s_register_operand" "")])]))
3124 (clobber (match_operand:SI 8 "s_register_operand" ""))]
3126 && GET_CODE (operands[1]) == GET_CODE (operands[9])
3127 && INTVAL (operands[3]) == 32 - INTVAL (operands[6])"
3130 [(ashift:SI (match_dup 2) (match_dup 4))
3134 [(ashiftrt:SI (match_dup 8) (match_dup 6))
3137 operands[4] = GEN_INT (32 - (INTVAL (operands[3]) + INTVAL (operands[4])));
3141 [(set (match_operand:SI 0 "s_register_operand" "")
3142 (match_operator:SI 1 "logical_binary_operator"
3143 [(match_operator:SI 9 "logical_binary_operator"
3144 [(ashiftrt:SI (match_operand:SI 5 "s_register_operand" "")
3145 (match_operand:SI 6 "const_int_operand" ""))
3146 (match_operand:SI 7 "s_register_operand" "")])
3147 (sign_extract:SI (match_operand:SI 2 "s_register_operand" "")
3148 (match_operand:SI 3 "const_int_operand" "")
3149 (match_operand:SI 4 "const_int_operand" ""))]))
3150 (clobber (match_operand:SI 8 "s_register_operand" ""))]
3152 && GET_CODE (operands[1]) == GET_CODE (operands[9])
3153 && INTVAL (operands[3]) == 32 - INTVAL (operands[6])"
3156 [(ashift:SI (match_dup 2) (match_dup 4))
3160 [(ashiftrt:SI (match_dup 8) (match_dup 6))
3163 operands[4] = GEN_INT (32 - (INTVAL (operands[3]) + INTVAL (operands[4])));
3167 ;; Minimum and maximum insns
3169 (define_expand "smaxsi3"
3171 (set (match_operand:SI 0 "s_register_operand")
3172 (smax:SI (match_operand:SI 1 "s_register_operand")
3173 (match_operand:SI 2 "arm_rhs_operand")))
3174 (clobber (reg:CC CC_REGNUM))])]
3177 if (operands[2] == const0_rtx || operands[2] == constm1_rtx)
3179 /* No need for a clobber of the condition code register here. */
3180 emit_insn (gen_rtx_SET (operands[0],
3181 gen_rtx_SMAX (SImode, operands[1],
3187 (define_insn "*smax_0"
3188 [(set (match_operand:SI 0 "s_register_operand" "=r")
3189 (smax:SI (match_operand:SI 1 "s_register_operand" "r")
3192 "bic%?\\t%0, %1, %1, asr #31"
3193 [(set_attr "predicable" "yes")
3194 (set_attr "type" "logic_shift_reg")]
3197 (define_insn "*smax_m1"
3198 [(set (match_operand:SI 0 "s_register_operand" "=r")
3199 (smax:SI (match_operand:SI 1 "s_register_operand" "r")
3202 "orr%?\\t%0, %1, %1, asr #31"
3203 [(set_attr "predicable" "yes")
3204 (set_attr "type" "logic_shift_reg")]
3207 (define_insn_and_split "*arm_smax_insn"
3208 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
3209 (smax:SI (match_operand:SI 1 "s_register_operand" "%0,?r")
3210 (match_operand:SI 2 "arm_rhs_operand" "rI,rI")))
3211 (clobber (reg:CC CC_REGNUM))]
3214 ; cmp\\t%1, %2\;movlt\\t%0, %2
3215 ; cmp\\t%1, %2\;movge\\t%0, %1\;movlt\\t%0, %2"
3217 [(set (reg:CC CC_REGNUM)
3218 (compare:CC (match_dup 1) (match_dup 2)))
3220 (if_then_else:SI (ge:SI (reg:CC CC_REGNUM) (const_int 0))
3224 [(set_attr "conds" "clob")
3225 (set_attr "length" "8,12")
3226 (set_attr "type" "multiple")]
3229 (define_expand "sminsi3"
3231 (set (match_operand:SI 0 "s_register_operand")
3232 (smin:SI (match_operand:SI 1 "s_register_operand")
3233 (match_operand:SI 2 "arm_rhs_operand")))
3234 (clobber (reg:CC CC_REGNUM))])]
3237 if (operands[2] == const0_rtx)
3239 /* No need for a clobber of the condition code register here. */
3240 emit_insn (gen_rtx_SET (operands[0],
3241 gen_rtx_SMIN (SImode, operands[1],
3247 (define_insn "*smin_0"
3248 [(set (match_operand:SI 0 "s_register_operand" "=r")
3249 (smin:SI (match_operand:SI 1 "s_register_operand" "r")
3252 "and%?\\t%0, %1, %1, asr #31"
3253 [(set_attr "predicable" "yes")
3254 (set_attr "type" "logic_shift_reg")]
3257 (define_insn_and_split "*arm_smin_insn"
3258 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
3259 (smin:SI (match_operand:SI 1 "s_register_operand" "%0,?r")
3260 (match_operand:SI 2 "arm_rhs_operand" "rI,rI")))
3261 (clobber (reg:CC CC_REGNUM))]
3264 ; cmp\\t%1, %2\;movge\\t%0, %2
3265 ; cmp\\t%1, %2\;movlt\\t%0, %1\;movge\\t%0, %2"
3267 [(set (reg:CC CC_REGNUM)
3268 (compare:CC (match_dup 1) (match_dup 2)))
3270 (if_then_else:SI (lt:SI (reg:CC CC_REGNUM) (const_int 0))
3274 [(set_attr "conds" "clob")
3275 (set_attr "length" "8,12")
3276 (set_attr "type" "multiple,multiple")]
3279 (define_expand "umaxsi3"
3281 (set (match_operand:SI 0 "s_register_operand")
3282 (umax:SI (match_operand:SI 1 "s_register_operand")
3283 (match_operand:SI 2 "arm_rhs_operand")))
3284 (clobber (reg:CC CC_REGNUM))])]
3289 (define_insn_and_split "*arm_umaxsi3"
3290 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
3291 (umax:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
3292 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
3293 (clobber (reg:CC CC_REGNUM))]
3296 ; cmp\\t%1, %2\;movcc\\t%0, %2
3297 ; cmp\\t%1, %2\;movcs\\t%0, %1
3298 ; cmp\\t%1, %2\;movcs\\t%0, %1\;movcc\\t%0, %2"
3300 [(set (reg:CC CC_REGNUM)
3301 (compare:CC (match_dup 1) (match_dup 2)))
3303 (if_then_else:SI (geu:SI (reg:CC CC_REGNUM) (const_int 0))
3307 [(set_attr "conds" "clob")
3308 (set_attr "length" "8,8,12")
3309 (set_attr "type" "store_4")]
3312 (define_expand "uminsi3"
3314 (set (match_operand:SI 0 "s_register_operand")
3315 (umin:SI (match_operand:SI 1 "s_register_operand")
3316 (match_operand:SI 2 "arm_rhs_operand")))
3317 (clobber (reg:CC CC_REGNUM))])]
3322 (define_insn_and_split "*arm_uminsi3"
3323 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
3324 (umin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
3325 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
3326 (clobber (reg:CC CC_REGNUM))]
3329 ; cmp\\t%1, %2\;movcs\\t%0, %2
3330 ; cmp\\t%1, %2\;movcc\\t%0, %1
3331 ; cmp\\t%1, %2\;movcc\\t%0, %1\;movcs\\t%0, %2"
3333 [(set (reg:CC CC_REGNUM)
3334 (compare:CC (match_dup 1) (match_dup 2)))
3336 (if_then_else:SI (ltu:SI (reg:CC CC_REGNUM) (const_int 0))
3340 [(set_attr "conds" "clob")
3341 (set_attr "length" "8,8,12")
3342 (set_attr "type" "store_4")]
3345 (define_insn "*store_minmaxsi"
3346 [(set (match_operand:SI 0 "memory_operand" "=m")
3347 (match_operator:SI 3 "minmax_operator"
3348 [(match_operand:SI 1 "s_register_operand" "r")
3349 (match_operand:SI 2 "s_register_operand" "r")]))
3350 (clobber (reg:CC CC_REGNUM))]
3351 "TARGET_32BIT && optimize_function_for_size_p (cfun) && !arm_restrict_it"
3353 operands[3] = gen_rtx_fmt_ee (minmax_code (operands[3]), SImode,
3354 operands[1], operands[2]);
3355 output_asm_insn (\"cmp\\t%1, %2\", operands);
3357 output_asm_insn (\"ite\t%d3\", operands);
3358 output_asm_insn (\"str%d3\\t%1, %0\", operands);
3359 output_asm_insn (\"str%D3\\t%2, %0\", operands);
3362 [(set_attr "conds" "clob")
3363 (set (attr "length")
3364 (if_then_else (eq_attr "is_thumb" "yes")
3367 (set_attr "type" "store_4")]
3370 ; Reject the frame pointer in operand[1], since reloading this after
3371 ; it has been eliminated can cause carnage.
3372 (define_insn "*minmax_arithsi"
3373 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
3374 (match_operator:SI 4 "shiftable_operator"
3375 [(match_operator:SI 5 "minmax_operator"
3376 [(match_operand:SI 2 "s_register_operand" "r,r")
3377 (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])
3378 (match_operand:SI 1 "s_register_operand" "0,?r")]))
3379 (clobber (reg:CC CC_REGNUM))]
3380 "TARGET_32BIT && !arm_eliminable_register (operands[1]) && !arm_restrict_it"
3383 enum rtx_code code = GET_CODE (operands[4]);
3386 if (which_alternative != 0 || operands[3] != const0_rtx
3387 || (code != PLUS && code != IOR && code != XOR))
3392 operands[5] = gen_rtx_fmt_ee (minmax_code (operands[5]), SImode,
3393 operands[2], operands[3]);
3394 output_asm_insn (\"cmp\\t%2, %3\", operands);
3398 output_asm_insn (\"ite\\t%d5\", operands);
3400 output_asm_insn (\"it\\t%d5\", operands);
3402 output_asm_insn (\"%i4%d5\\t%0, %1, %2\", operands);
3404 output_asm_insn (\"%i4%D5\\t%0, %1, %3\", operands);
3407 [(set_attr "conds" "clob")
3408 (set (attr "length")
3409 (if_then_else (eq_attr "is_thumb" "yes")
3412 (set_attr "type" "multiple")]
3415 ; Reject the frame pointer in operand[1], since reloading this after
3416 ; it has been eliminated can cause carnage.
3417 (define_insn_and_split "*minmax_arithsi_non_canon"
3418 [(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts")
3420 (match_operand:SI 1 "s_register_operand" "0,?Ts")
3421 (match_operator:SI 4 "minmax_operator"
3422 [(match_operand:SI 2 "s_register_operand" "Ts,Ts")
3423 (match_operand:SI 3 "arm_rhs_operand" "TsI,TsI")])))
3424 (clobber (reg:CC CC_REGNUM))]
3425 "TARGET_32BIT && !arm_eliminable_register (operands[1])
3426 && !(arm_restrict_it && CONST_INT_P (operands[3]))"
3428 "TARGET_32BIT && !arm_eliminable_register (operands[1]) && reload_completed"
3429 [(set (reg:CC CC_REGNUM)
3430 (compare:CC (match_dup 2) (match_dup 3)))
3432 (cond_exec (match_op_dup 4 [(reg:CC CC_REGNUM) (const_int 0)])
3434 (minus:SI (match_dup 1)
3436 (cond_exec (match_op_dup 5 [(reg:CC CC_REGNUM) (const_int 0)])
3440 machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[1]),
3441 operands[2], operands[3]);
3442 enum rtx_code rc = minmax_code (operands[4]);
3443 operands[4] = gen_rtx_fmt_ee (rc, VOIDmode,
3444 operands[2], operands[3]);
3446 if (mode == CCFPmode || mode == CCFPEmode)
3447 rc = reverse_condition_maybe_unordered (rc);
3449 rc = reverse_condition (rc);
3450 operands[5] = gen_rtx_fmt_ee (rc, SImode, operands[2], operands[3]);
3451 if (CONST_INT_P (operands[3]))
3452 operands[6] = plus_constant (SImode, operands[1], -INTVAL (operands[3]));
3454 operands[6] = gen_rtx_MINUS (SImode, operands[1], operands[3]);
3456 [(set_attr "conds" "clob")
3457 (set (attr "length")
3458 (if_then_else (eq_attr "is_thumb" "yes")
3461 (set_attr "type" "multiple")]
3464 (define_code_iterator SAT [smin smax])
3465 (define_code_attr SATrev [(smin "smax") (smax "smin")])
3466 (define_code_attr SATlo [(smin "1") (smax "2")])
3467 (define_code_attr SAThi [(smin "2") (smax "1")])
3469 (define_insn "*satsi_<SAT:code>"
3470 [(set (match_operand:SI 0 "s_register_operand" "=r")
3471 (SAT:SI (<SATrev>:SI (match_operand:SI 3 "s_register_operand" "r")
3472 (match_operand:SI 1 "const_int_operand" "i"))
3473 (match_operand:SI 2 "const_int_operand" "i")))]
3474 "TARGET_32BIT && arm_arch6
3475 && arm_sat_operator_match (operands[<SAT:SATlo>], operands[<SAT:SAThi>], NULL, NULL)"
3479 if (!arm_sat_operator_match (operands[<SAT:SATlo>], operands[<SAT:SAThi>],
3480 &mask, &signed_sat))
3483 operands[1] = GEN_INT (mask);
3485 return "ssat%?\t%0, %1, %3";
3487 return "usat%?\t%0, %1, %3";
3489 [(set_attr "predicable" "yes")
3490 (set_attr "type" "alus_imm")]
3493 (define_insn "*satsi_<SAT:code>_shift"
3494 [(set (match_operand:SI 0 "s_register_operand" "=r")
3495 (SAT:SI (<SATrev>:SI (match_operator:SI 3 "sat_shift_operator"
3496 [(match_operand:SI 4 "s_register_operand" "r")
3497 (match_operand:SI 5 "const_int_operand" "i")])
3498 (match_operand:SI 1 "const_int_operand" "i"))
3499 (match_operand:SI 2 "const_int_operand" "i")))]
3500 "TARGET_32BIT && arm_arch6
3501 && arm_sat_operator_match (operands[<SAT:SATlo>], operands[<SAT:SAThi>], NULL, NULL)"
3505 if (!arm_sat_operator_match (operands[<SAT:SATlo>], operands[<SAT:SAThi>],
3506 &mask, &signed_sat))
3509 operands[1] = GEN_INT (mask);
3511 return "ssat%?\t%0, %1, %4%S3";
3513 return "usat%?\t%0, %1, %4%S3";
3515 [(set_attr "predicable" "yes")
3516 (set_attr "shift" "3")
3517 (set_attr "type" "logic_shift_reg")])
3519 ;; Shift and rotation insns
3521 (define_expand "ashldi3"
3522 [(set (match_operand:DI 0 "s_register_operand")
3523 (ashift:DI (match_operand:DI 1 "s_register_operand")
3524 (match_operand:SI 2 "reg_or_int_operand")))]
3527 arm_emit_coreregs_64bit_shift (ASHIFT, operands[0], operands[1],
3528 operands[2], gen_reg_rtx (SImode),
3529 gen_reg_rtx (SImode));
3533 (define_expand "ashlsi3"
3534 [(set (match_operand:SI 0 "s_register_operand")
3535 (ashift:SI (match_operand:SI 1 "s_register_operand")
3536 (match_operand:SI 2 "arm_rhs_operand")))]
3539 if (CONST_INT_P (operands[2])
3540 && (UINTVAL (operands[2])) > 31)
3542 emit_insn (gen_movsi (operands[0], const0_rtx));
3548 (define_expand "ashrdi3"
3549 [(set (match_operand:DI 0 "s_register_operand")
3550 (ashiftrt:DI (match_operand:DI 1 "s_register_operand")
3551 (match_operand:SI 2 "reg_or_int_operand")))]
3554 arm_emit_coreregs_64bit_shift (ASHIFTRT, operands[0], operands[1],
3555 operands[2], gen_reg_rtx (SImode),
3556 gen_reg_rtx (SImode));
3560 (define_expand "ashrsi3"
3561 [(set (match_operand:SI 0 "s_register_operand")
3562 (ashiftrt:SI (match_operand:SI 1 "s_register_operand")
3563 (match_operand:SI 2 "arm_rhs_operand")))]
3566 if (CONST_INT_P (operands[2])
3567 && UINTVAL (operands[2]) > 31)
3568 operands[2] = GEN_INT (31);
3572 (define_expand "lshrdi3"
3573 [(set (match_operand:DI 0 "s_register_operand")
3574 (lshiftrt:DI (match_operand:DI 1 "s_register_operand")
3575 (match_operand:SI 2 "reg_or_int_operand")))]
3578 arm_emit_coreregs_64bit_shift (LSHIFTRT, operands[0], operands[1],
3579 operands[2], gen_reg_rtx (SImode),
3580 gen_reg_rtx (SImode));
3584 (define_expand "lshrsi3"
3585 [(set (match_operand:SI 0 "s_register_operand")
3586 (lshiftrt:SI (match_operand:SI 1 "s_register_operand")
3587 (match_operand:SI 2 "arm_rhs_operand")))]
3590 if (CONST_INT_P (operands[2])
3591 && (UINTVAL (operands[2])) > 31)
3593 emit_insn (gen_movsi (operands[0], const0_rtx));
3599 (define_expand "rotlsi3"
3600 [(set (match_operand:SI 0 "s_register_operand")
3601 (rotatert:SI (match_operand:SI 1 "s_register_operand")
3602 (match_operand:SI 2 "reg_or_int_operand")))]
3605 if (CONST_INT_P (operands[2]))
3606 operands[2] = GEN_INT ((32 - INTVAL (operands[2])) % 32);
3609 rtx reg = gen_reg_rtx (SImode);
3610 emit_insn (gen_subsi3 (reg, GEN_INT (32), operands[2]));
3616 (define_expand "rotrsi3"
3617 [(set (match_operand:SI 0 "s_register_operand")
3618 (rotatert:SI (match_operand:SI 1 "s_register_operand")
3619 (match_operand:SI 2 "arm_rhs_operand")))]
3624 if (CONST_INT_P (operands[2])
3625 && UINTVAL (operands[2]) > 31)
3626 operands[2] = GEN_INT (INTVAL (operands[2]) % 32);
3628 else /* TARGET_THUMB1 */
3630 if (CONST_INT_P (operands [2]))
3631 operands [2] = force_reg (SImode, operands[2]);
3636 (define_insn "*arm_shiftsi3"
3637 [(set (match_operand:SI 0 "s_register_operand" "=l,l,r,r")
3638 (match_operator:SI 3 "shift_operator"
3639 [(match_operand:SI 1 "s_register_operand" "0,l,r,r")
3640 (match_operand:SI 2 "reg_or_int_operand" "l,M,M,r")]))]
3642 "* return arm_output_shift(operands, 0);"
3643 [(set_attr "predicable" "yes")
3644 (set_attr "arch" "t2,t2,*,*")
3645 (set_attr "predicable_short_it" "yes,yes,no,no")
3646 (set_attr "length" "4")
3647 (set_attr "shift" "1")
3648 (set_attr "type" "alu_shift_reg,alu_shift_imm,alu_shift_imm,alu_shift_reg")]
3651 (define_insn "*shiftsi3_compare0"
3652 [(set (reg:CC_NOOV CC_REGNUM)
3653 (compare:CC_NOOV (match_operator:SI 3 "shift_operator"
3654 [(match_operand:SI 1 "s_register_operand" "r,r")
3655 (match_operand:SI 2 "arm_rhs_operand" "M,r")])
3657 (set (match_operand:SI 0 "s_register_operand" "=r,r")
3658 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))]
3660 "* return arm_output_shift(operands, 1);"
3661 [(set_attr "conds" "set")
3662 (set_attr "shift" "1")
3663 (set_attr "type" "alus_shift_imm,alus_shift_reg")]
3666 (define_insn "*shiftsi3_compare0_scratch"
3667 [(set (reg:CC_NOOV CC_REGNUM)
3668 (compare:CC_NOOV (match_operator:SI 3 "shift_operator"
3669 [(match_operand:SI 1 "s_register_operand" "r,r")
3670 (match_operand:SI 2 "arm_rhs_operand" "M,r")])
3672 (clobber (match_scratch:SI 0 "=r,r"))]
3674 "* return arm_output_shift(operands, 1);"
3675 [(set_attr "conds" "set")
3676 (set_attr "shift" "1")
3677 (set_attr "type" "shift_imm,shift_reg")]
3680 (define_insn "*not_shiftsi"
3681 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
3682 (not:SI (match_operator:SI 3 "shift_operator"
3683 [(match_operand:SI 1 "s_register_operand" "r,r")
3684 (match_operand:SI 2 "shift_amount_operand" "M,rM")])))]
3687 [(set_attr "predicable" "yes")
3688 (set_attr "shift" "1")
3689 (set_attr "arch" "32,a")
3690 (set_attr "type" "mvn_shift,mvn_shift_reg")])
3692 (define_insn "*not_shiftsi_compare0"
3693 [(set (reg:CC_NOOV CC_REGNUM)
3695 (not:SI (match_operator:SI 3 "shift_operator"
3696 [(match_operand:SI 1 "s_register_operand" "r,r")
3697 (match_operand:SI 2 "shift_amount_operand" "M,rM")]))
3699 (set (match_operand:SI 0 "s_register_operand" "=r,r")
3700 (not:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])))]
3702 "mvns%?\\t%0, %1%S3"
3703 [(set_attr "conds" "set")
3704 (set_attr "shift" "1")
3705 (set_attr "arch" "32,a")
3706 (set_attr "type" "mvn_shift,mvn_shift_reg")])
3708 (define_insn "*not_shiftsi_compare0_scratch"
3709 [(set (reg:CC_NOOV CC_REGNUM)
3711 (not:SI (match_operator:SI 3 "shift_operator"
3712 [(match_operand:SI 1 "s_register_operand" "r,r")
3713 (match_operand:SI 2 "shift_amount_operand" "M,rM")]))
3715 (clobber (match_scratch:SI 0 "=r,r"))]
3717 "mvns%?\\t%0, %1%S3"
3718 [(set_attr "conds" "set")
3719 (set_attr "shift" "1")
3720 (set_attr "arch" "32,a")
3721 (set_attr "type" "mvn_shift,mvn_shift_reg")])
3723 ;; We don't really have extzv, but defining this using shifts helps
3724 ;; to reduce register pressure later on.
3726 (define_expand "extzv"
3727 [(set (match_operand 0 "s_register_operand")
3728 (zero_extract (match_operand 1 "nonimmediate_operand")
3729 (match_operand 2 "const_int_operand")
3730 (match_operand 3 "const_int_operand")))]
3731 "TARGET_THUMB1 || arm_arch_thumb2"
3734 HOST_WIDE_INT lshift = 32 - INTVAL (operands[2]) - INTVAL (operands[3]);
3735 HOST_WIDE_INT rshift = 32 - INTVAL (operands[2]);
3737 if (arm_arch_thumb2)
3739 HOST_WIDE_INT width = INTVAL (operands[2]);
3740 HOST_WIDE_INT bitpos = INTVAL (operands[3]);
3742 if (unaligned_access && MEM_P (operands[1])
3743 && (width == 16 || width == 32) && (bitpos % BITS_PER_UNIT) == 0)
3747 if (BYTES_BIG_ENDIAN)
3748 bitpos = GET_MODE_BITSIZE (GET_MODE (operands[0])) - width
3753 base_addr = adjust_address (operands[1], SImode,
3754 bitpos / BITS_PER_UNIT);
3755 emit_insn (gen_unaligned_loadsi (operands[0], base_addr));
3759 rtx dest = operands[0];
3760 rtx tmp = gen_reg_rtx (SImode);
3762 /* We may get a paradoxical subreg here. Strip it off. */
3763 if (GET_CODE (dest) == SUBREG
3764 && GET_MODE (dest) == SImode
3765 && GET_MODE (SUBREG_REG (dest)) == HImode)
3766 dest = SUBREG_REG (dest);
3768 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
3771 base_addr = adjust_address (operands[1], HImode,
3772 bitpos / BITS_PER_UNIT);
3773 emit_insn (gen_unaligned_loadhiu (tmp, base_addr));
3774 emit_move_insn (gen_lowpart (SImode, dest), tmp);
3778 else if (s_register_operand (operands[1], GET_MODE (operands[1])))
3780 emit_insn (gen_extzv_t2 (operands[0], operands[1], operands[2],
3788 if (!s_register_operand (operands[1], GET_MODE (operands[1])))
3791 operands[3] = GEN_INT (rshift);
3795 emit_insn (gen_lshrsi3 (operands[0], operands[1], operands[3]));
3799 emit_insn (gen_extzv_t1 (operands[0], operands[1], GEN_INT (lshift),
3800 operands[3], gen_reg_rtx (SImode)));
3805 ;; Helper for extzv, for the Thumb-1 register-shifts case.
3807 (define_expand "extzv_t1"
3808 [(set (match_operand:SI 4 "s_register_operand")
3809 (ashift:SI (match_operand:SI 1 "nonimmediate_operand")
3810 (match_operand:SI 2 "const_int_operand")))
3811 (set (match_operand:SI 0 "s_register_operand")
3812 (lshiftrt:SI (match_dup 4)
3813 (match_operand:SI 3 "const_int_operand")))]
3817 (define_expand "extv"
3818 [(set (match_operand 0 "s_register_operand")
3819 (sign_extract (match_operand 1 "nonimmediate_operand")
3820 (match_operand 2 "const_int_operand")
3821 (match_operand 3 "const_int_operand")))]
3824 HOST_WIDE_INT width = INTVAL (operands[2]);
3825 HOST_WIDE_INT bitpos = INTVAL (operands[3]);
3827 if (unaligned_access && MEM_P (operands[1]) && (width == 16 || width == 32)
3828 && (bitpos % BITS_PER_UNIT) == 0)
3832 if (BYTES_BIG_ENDIAN)
3833 bitpos = GET_MODE_BITSIZE (GET_MODE (operands[0])) - width - bitpos;
3837 base_addr = adjust_address (operands[1], SImode,
3838 bitpos / BITS_PER_UNIT);
3839 emit_insn (gen_unaligned_loadsi (operands[0], base_addr));
3843 rtx dest = operands[0];
3844 rtx tmp = gen_reg_rtx (SImode);
3846 /* We may get a paradoxical subreg here. Strip it off. */
3847 if (GET_CODE (dest) == SUBREG
3848 && GET_MODE (dest) == SImode
3849 && GET_MODE (SUBREG_REG (dest)) == HImode)
3850 dest = SUBREG_REG (dest);
3852 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
3855 base_addr = adjust_address (operands[1], HImode,
3856 bitpos / BITS_PER_UNIT);
3857 emit_insn (gen_unaligned_loadhis (tmp, base_addr));
3858 emit_move_insn (gen_lowpart (SImode, dest), tmp);
3863 else if (!s_register_operand (operands[1], GET_MODE (operands[1])))
3865 else if (GET_MODE (operands[0]) == SImode
3866 && GET_MODE (operands[1]) == SImode)
3868 emit_insn (gen_extv_regsi (operands[0], operands[1], operands[2],
3876 ; Helper to expand register forms of extv with the proper modes.
3878 (define_expand "extv_regsi"
3879 [(set (match_operand:SI 0 "s_register_operand")
3880 (sign_extract:SI (match_operand:SI 1 "s_register_operand")
3881 (match_operand 2 "const_int_operand")
3882 (match_operand 3 "const_int_operand")))]
3887 ; ARMv6+ unaligned load/store instructions (used for packed structure accesses).
3889 (define_insn "unaligned_loaddi"
3890 [(set (match_operand:DI 0 "s_register_operand" "=r")
3891 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")]
3892 UNSPEC_UNALIGNED_LOAD))]
3893 "TARGET_32BIT && TARGET_LDRD"
3895 return output_move_double (operands, true, NULL);
3897 [(set_attr "length" "8")
3898 (set_attr "type" "load_8")])
3900 (define_insn "unaligned_loadsi"
3901 [(set (match_operand:SI 0 "s_register_operand" "=l,l,r")
3902 (unspec:SI [(match_operand:SI 1 "memory_operand" "m,Uw,m")]
3903 UNSPEC_UNALIGNED_LOAD))]
3906 ldr\t%0, %1\t@ unaligned
3907 ldr%?\t%0, %1\t@ unaligned
3908 ldr%?\t%0, %1\t@ unaligned"
3909 [(set_attr "arch" "t1,t2,32")
3910 (set_attr "length" "2,2,4")
3911 (set_attr "predicable" "no,yes,yes")
3912 (set_attr "predicable_short_it" "no,yes,no")
3913 (set_attr "type" "load_4")])
3915 ;; The 16-bit Thumb1 variant of ldrsh requires two registers in the
3916 ;; address (there's no immediate format). That's tricky to support
3917 ;; here and we don't really need this pattern for that case, so only
3918 ;; enable for 32-bit ISAs.
3919 (define_insn "unaligned_loadhis"
3920 [(set (match_operand:SI 0 "s_register_operand" "=r")
3922 (unspec:HI [(match_operand:HI 1 "memory_operand" "Uh")]
3923 UNSPEC_UNALIGNED_LOAD)))]
3924 "unaligned_access && TARGET_32BIT"
3925 "ldrsh%?\t%0, %1\t@ unaligned"
3926 [(set_attr "predicable" "yes")
3927 (set_attr "type" "load_byte")])
3929 (define_insn "unaligned_loadhiu"
3930 [(set (match_operand:SI 0 "s_register_operand" "=l,l,r")
3932 (unspec:HI [(match_operand:HI 1 "memory_operand" "m,Uw,m")]
3933 UNSPEC_UNALIGNED_LOAD)))]
3936 ldrh\t%0, %1\t@ unaligned
3937 ldrh%?\t%0, %1\t@ unaligned
3938 ldrh%?\t%0, %1\t@ unaligned"
3939 [(set_attr "arch" "t1,t2,32")
3940 (set_attr "length" "2,2,4")
3941 (set_attr "predicable" "no,yes,yes")
3942 (set_attr "predicable_short_it" "no,yes,no")
3943 (set_attr "type" "load_byte")])
3945 (define_insn "unaligned_storedi"
3946 [(set (match_operand:DI 0 "memory_operand" "=m")
3947 (unspec:DI [(match_operand:DI 1 "s_register_operand" "r")]
3948 UNSPEC_UNALIGNED_STORE))]
3949 "TARGET_32BIT && TARGET_LDRD"
3951 return output_move_double (operands, true, NULL);
3953 [(set_attr "length" "8")
3954 (set_attr "type" "store_8")])
3956 (define_insn "unaligned_storesi"
3957 [(set (match_operand:SI 0 "memory_operand" "=m,Uw,m")
3958 (unspec:SI [(match_operand:SI 1 "s_register_operand" "l,l,r")]
3959 UNSPEC_UNALIGNED_STORE))]
3962 str\t%1, %0\t@ unaligned
3963 str%?\t%1, %0\t@ unaligned
3964 str%?\t%1, %0\t@ unaligned"
3965 [(set_attr "arch" "t1,t2,32")
3966 (set_attr "length" "2,2,4")
3967 (set_attr "predicable" "no,yes,yes")
3968 (set_attr "predicable_short_it" "no,yes,no")
3969 (set_attr "type" "store_4")])
3971 (define_insn "unaligned_storehi"
3972 [(set (match_operand:HI 0 "memory_operand" "=m,Uw,m")
3973 (unspec:HI [(match_operand:HI 1 "s_register_operand" "l,l,r")]
3974 UNSPEC_UNALIGNED_STORE))]
3977 strh\t%1, %0\t@ unaligned
3978 strh%?\t%1, %0\t@ unaligned
3979 strh%?\t%1, %0\t@ unaligned"
3980 [(set_attr "arch" "t1,t2,32")
3981 (set_attr "length" "2,2,4")
3982 (set_attr "predicable" "no,yes,yes")
3983 (set_attr "predicable_short_it" "no,yes,no")
3984 (set_attr "type" "store_4")])
3987 (define_insn "*extv_reg"
3988 [(set (match_operand:SI 0 "s_register_operand" "=r")
3989 (sign_extract:SI (match_operand:SI 1 "s_register_operand" "r")
3990 (match_operand:SI 2 "const_int_operand" "n")
3991 (match_operand:SI 3 "const_int_operand" "n")))]
3993 && IN_RANGE (INTVAL (operands[3]), 0, 31)
3994 && IN_RANGE (INTVAL (operands[2]), 1, 32 - INTVAL (operands[3]))"
3995 "sbfx%?\t%0, %1, %3, %2"
3996 [(set_attr "length" "4")
3997 (set_attr "predicable" "yes")
3998 (set_attr "type" "bfm")]
4001 (define_insn "extzv_t2"
4002 [(set (match_operand:SI 0 "s_register_operand" "=r")
4003 (zero_extract:SI (match_operand:SI 1 "s_register_operand" "r")
4004 (match_operand:SI 2 "const_int_operand" "n")
4005 (match_operand:SI 3 "const_int_operand" "n")))]
4007 && IN_RANGE (INTVAL (operands[3]), 0, 31)
4008 && IN_RANGE (INTVAL (operands[2]), 1, 32 - INTVAL (operands[3]))"
4009 "ubfx%?\t%0, %1, %3, %2"
4010 [(set_attr "length" "4")
4011 (set_attr "predicable" "yes")
4012 (set_attr "type" "bfm")]
4016 ;; Division instructions
4017 (define_insn "divsi3"
4018 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
4019 (div:SI (match_operand:SI 1 "s_register_operand" "r,r")
4020 (match_operand:SI 2 "s_register_operand" "r,r")))]
4025 [(set_attr "arch" "32,v8mb")
4026 (set_attr "predicable" "yes")
4027 (set_attr "type" "sdiv")]
4030 (define_insn "udivsi3"
4031 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
4032 (udiv:SI (match_operand:SI 1 "s_register_operand" "r,r")
4033 (match_operand:SI 2 "s_register_operand" "r,r")))]
4038 [(set_attr "arch" "32,v8mb")
4039 (set_attr "predicable" "yes")
4040 (set_attr "type" "udiv")]
4044 ;; Unary arithmetic insns
4046 (define_expand "negvsi3"
4047 [(match_operand:SI 0 "register_operand")
4048 (match_operand:SI 1 "register_operand")
4049 (match_operand 2 "")]
4052 emit_insn (gen_subsi3_compare (operands[0], const0_rtx, operands[1]));
4053 arm_gen_unlikely_cbranch (NE, CC_Vmode, operands[2]);
4058 (define_expand "negvdi3"
4059 [(match_operand:DI 0 "register_operand")
4060 (match_operand:DI 1 "register_operand")
4061 (match_operand 2 "")]
4064 emit_insn (gen_negdi2_compare (operands[0], operands[1]));
4065 arm_gen_unlikely_cbranch (NE, CC_Vmode, operands[2]);
4071 (define_insn_and_split "negdi2_compare"
4072 [(set (reg:CC CC_REGNUM)
4075 (match_operand:DI 1 "register_operand" "0,r")))
4076 (set (match_operand:DI 0 "register_operand" "=r,&r")
4077 (minus:DI (const_int 0) (match_dup 1)))]
4080 "&& reload_completed"
4081 [(parallel [(set (reg:CC CC_REGNUM)
4082 (compare:CC (const_int 0) (match_dup 1)))
4083 (set (match_dup 0) (minus:SI (const_int 0)
4085 (parallel [(set (reg:CC CC_REGNUM)
4086 (compare:CC (const_int 0) (match_dup 3)))
4089 (minus:SI (const_int 0) (match_dup 3))
4090 (ltu:SI (reg:CC CC_REGNUM)
4093 operands[2] = gen_highpart (SImode, operands[0]);
4094 operands[0] = gen_lowpart (SImode, operands[0]);
4095 operands[3] = gen_highpart (SImode, operands[1]);
4096 operands[1] = gen_lowpart (SImode, operands[1]);
4098 [(set_attr "conds" "set")
4099 (set_attr "length" "8")
4100 (set_attr "type" "multiple")]
4103 (define_expand "negdi2"
4105 [(set (match_operand:DI 0 "s_register_operand")
4106 (neg:DI (match_operand:DI 1 "s_register_operand")))
4107 (clobber (reg:CC CC_REGNUM))])]
4111 ;; The constraints here are to prevent a *partial* overlap (where %Q0 == %R1).
4112 ;; The first alternative allows the common case of a *full* overlap.
4113 (define_insn_and_split "*negdi2_insn"
4114 [(set (match_operand:DI 0 "s_register_operand" "=r,&r")
4115 (neg:DI (match_operand:DI 1 "s_register_operand" "0,r")))
4116 (clobber (reg:CC CC_REGNUM))]
4118 "#" ; rsbs %Q0, %Q1, #0; rsc %R0, %R1, #0 (ARM)
4119 ; negs %Q0, %Q1 ; sbc %R0, %R1, %R1, lsl #1 (Thumb-2)
4121 [(parallel [(set (reg:CC CC_REGNUM)
4122 (compare:CC (const_int 0) (match_dup 1)))
4123 (set (match_dup 0) (minus:SI (const_int 0) (match_dup 1)))])
4124 (set (match_dup 2) (minus:SI (minus:SI (const_int 0) (match_dup 3))
4125 (ltu:SI (reg:CC CC_REGNUM) (const_int 0))))]
4127 operands[2] = gen_highpart (SImode, operands[0]);
4128 operands[0] = gen_lowpart (SImode, operands[0]);
4129 operands[3] = gen_highpart (SImode, operands[1]);
4130 operands[1] = gen_lowpart (SImode, operands[1]);
4132 [(set_attr "conds" "clob")
4133 (set_attr "length" "8")
4134 (set_attr "type" "multiple")]
4137 (define_insn "*negsi2_carryin_compare"
4138 [(set (reg:CC CC_REGNUM)
4139 (compare:CC (const_int 0)
4140 (match_operand:SI 1 "s_register_operand" "r")))
4141 (set (match_operand:SI 0 "s_register_operand" "=r")
4142 (minus:SI (minus:SI (const_int 0)
4144 (match_operand:SI 2 "arm_borrow_operation" "")))]
4147 [(set_attr "conds" "set")
4148 (set_attr "type" "alus_imm")]
4151 (define_expand "negsi2"
4152 [(set (match_operand:SI 0 "s_register_operand")
4153 (neg:SI (match_operand:SI 1 "s_register_operand")))]
4158 (define_insn "*arm_negsi2"
4159 [(set (match_operand:SI 0 "s_register_operand" "=l,r")
4160 (neg:SI (match_operand:SI 1 "s_register_operand" "l,r")))]
4162 "rsb%?\\t%0, %1, #0"
4163 [(set_attr "predicable" "yes")
4164 (set_attr "predicable_short_it" "yes,no")
4165 (set_attr "arch" "t2,*")
4166 (set_attr "length" "4")
4167 (set_attr "type" "alu_sreg")]
4170 (define_expand "negsf2"
4171 [(set (match_operand:SF 0 "s_register_operand")
4172 (neg:SF (match_operand:SF 1 "s_register_operand")))]
4173 "TARGET_32BIT && TARGET_HARD_FLOAT"
4177 (define_expand "negdf2"
4178 [(set (match_operand:DF 0 "s_register_operand")
4179 (neg:DF (match_operand:DF 1 "s_register_operand")))]
4180 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
4183 (define_insn_and_split "*zextendsidi_negsi"
4184 [(set (match_operand:DI 0 "s_register_operand" "=r")
4185 (zero_extend:DI (neg:SI (match_operand:SI 1 "s_register_operand" "r"))))]
4190 (neg:SI (match_dup 1)))
4194 operands[2] = gen_lowpart (SImode, operands[0]);
4195 operands[3] = gen_highpart (SImode, operands[0]);
4197 [(set_attr "length" "8")
4198 (set_attr "type" "multiple")]
4201 ;; Negate an extended 32-bit value.
4202 (define_insn_and_split "*negdi_extendsidi"
4203 [(set (match_operand:DI 0 "s_register_operand" "=l,r")
4204 (neg:DI (sign_extend:DI
4205 (match_operand:SI 1 "s_register_operand" "l,r"))))
4206 (clobber (reg:CC CC_REGNUM))]
4209 "&& reload_completed"
4212 rtx low = gen_lowpart (SImode, operands[0]);
4213 rtx high = gen_highpart (SImode, operands[0]);
4215 if (reg_overlap_mentioned_p (low, operands[1]))
4217 /* Input overlaps the low word of the output. Use:
4220 rsc Rhi, Rhi, #0 (thumb2: sbc Rhi, Rhi, Rhi, lsl #1). */
4221 rtx cc_reg = gen_rtx_REG (CCmode, CC_REGNUM);
4223 emit_insn (gen_rtx_SET (high,
4224 gen_rtx_ASHIFTRT (SImode, operands[1],
4227 emit_insn (gen_subsi3_compare (low, const0_rtx, operands[1]));
4229 emit_insn (gen_rtx_SET (high,
4230 gen_rtx_MINUS (SImode,
4231 gen_rtx_MINUS (SImode,
4234 gen_rtx_LTU (SImode,
4239 rtx two_x = gen_rtx_ASHIFT (SImode, high, GEN_INT (1));
4240 emit_insn (gen_rtx_SET (high,
4241 gen_rtx_MINUS (SImode,
4242 gen_rtx_MINUS (SImode,
4245 gen_rtx_LTU (SImode,
4252 /* No overlap, or overlap on high word. Use:
4256 Flags not needed for this sequence. */
4257 emit_insn (gen_rtx_SET (low, gen_rtx_NEG (SImode, operands[1])));
4258 emit_insn (gen_rtx_SET (high,
4259 gen_rtx_AND (SImode,
4260 gen_rtx_NOT (SImode, operands[1]),
4262 emit_insn (gen_rtx_SET (high,
4263 gen_rtx_ASHIFTRT (SImode, high,
4268 [(set_attr "length" "12")
4269 (set_attr "arch" "t2,*")
4270 (set_attr "type" "multiple")]
4273 (define_insn_and_split "*negdi_zero_extendsidi"
4274 [(set (match_operand:DI 0 "s_register_operand" "=r,&r")
4275 (neg:DI (zero_extend:DI (match_operand:SI 1 "s_register_operand" "0,r"))))
4276 (clobber (reg:CC CC_REGNUM))]
4278 "#" ; "rsbs\\t%Q0, %1, #0\;sbc\\t%R0,%R0,%R0"
4279 ;; Don't care what register is input to sbc,
4280 ;; since we just need to propagate the carry.
4281 "&& reload_completed"
4282 [(parallel [(set (reg:CC CC_REGNUM)
4283 (compare:CC (const_int 0) (match_dup 1)))
4284 (set (match_dup 0) (minus:SI (const_int 0) (match_dup 1)))])
4285 (set (match_dup 2) (minus:SI (minus:SI (match_dup 2) (match_dup 2))
4286 (ltu:SI (reg:CC CC_REGNUM) (const_int 0))))]
4288 operands[2] = gen_highpart (SImode, operands[0]);
4289 operands[0] = gen_lowpart (SImode, operands[0]);
4291 [(set_attr "conds" "clob")
4292 (set_attr "length" "8")
4293 (set_attr "type" "multiple")] ;; length in thumb is 4
4296 ;; abssi2 doesn't really clobber the condition codes if a different register
4297 ;; is being set. To keep things simple, assume during rtl manipulations that
4298 ;; it does, but tell the final scan operator the truth. Similarly for
4301 (define_expand "abssi2"
4303 [(set (match_operand:SI 0 "s_register_operand")
4304 (abs:SI (match_operand:SI 1 "s_register_operand")))
4305 (clobber (match_dup 2))])]
4309 operands[2] = gen_rtx_SCRATCH (SImode);
4311 operands[2] = gen_rtx_REG (CCmode, CC_REGNUM);
4314 (define_insn_and_split "*arm_abssi2"
4315 [(set (match_operand:SI 0 "s_register_operand" "=r,&r")
4316 (abs:SI (match_operand:SI 1 "s_register_operand" "0,r")))
4317 (clobber (reg:CC CC_REGNUM))]
4320 "&& reload_completed"
4323 /* if (which_alternative == 0) */
4324 if (REGNO(operands[0]) == REGNO(operands[1]))
4326 /* Emit the pattern:
4327 cmp\\t%0, #0\;rsblt\\t%0, %0, #0
4328 [(set (reg:CC CC_REGNUM)
4329 (compare:CC (match_dup 0) (const_int 0)))
4330 (cond_exec (lt:CC (reg:CC CC_REGNUM) (const_int 0))
4331 (set (match_dup 0) (minus:SI (const_int 0) (match_dup 1))))]
4333 emit_insn (gen_rtx_SET (gen_rtx_REG (CCmode, CC_REGNUM),
4334 gen_rtx_COMPARE (CCmode, operands[0], const0_rtx)));
4335 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4336 (gen_rtx_LT (SImode,
4337 gen_rtx_REG (CCmode, CC_REGNUM),
4339 (gen_rtx_SET (operands[0],
4340 (gen_rtx_MINUS (SImode,
4347 /* Emit the pattern:
4348 alt1: eor%?\\t%0, %1, %1, asr #31\;sub%?\\t%0, %0, %1, asr #31
4350 (xor:SI (match_dup 1)
4351 (ashiftrt:SI (match_dup 1) (const_int 31))))
4353 (minus:SI (match_dup 0)
4354 (ashiftrt:SI (match_dup 1) (const_int 31))))]
4356 emit_insn (gen_rtx_SET (operands[0],
4357 gen_rtx_XOR (SImode,
4358 gen_rtx_ASHIFTRT (SImode,
4362 emit_insn (gen_rtx_SET (operands[0],
4363 gen_rtx_MINUS (SImode,
4365 gen_rtx_ASHIFTRT (SImode,
4371 [(set_attr "conds" "clob,*")
4372 (set_attr "shift" "1")
4373 (set_attr "predicable" "no, yes")
4374 (set_attr "length" "8")
4375 (set_attr "type" "multiple")]
4378 (define_insn_and_split "*arm_neg_abssi2"
4379 [(set (match_operand:SI 0 "s_register_operand" "=r,&r")
4380 (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "0,r"))))
4381 (clobber (reg:CC CC_REGNUM))]
4384 "&& reload_completed"
4387 /* if (which_alternative == 0) */
4388 if (REGNO (operands[0]) == REGNO (operands[1]))
4390 /* Emit the pattern:
4391 cmp\\t%0, #0\;rsbgt\\t%0, %0, #0
4393 emit_insn (gen_rtx_SET (gen_rtx_REG (CCmode, CC_REGNUM),
4394 gen_rtx_COMPARE (CCmode, operands[0], const0_rtx)));
4395 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4397 gen_rtx_REG (CCmode, CC_REGNUM),
4399 gen_rtx_SET (operands[0],
4400 (gen_rtx_MINUS (SImode,
4406 /* Emit the pattern:
4407 eor%?\\t%0, %1, %1, asr #31\;rsb%?\\t%0, %0, %1, asr #31
4409 emit_insn (gen_rtx_SET (operands[0],
4410 gen_rtx_XOR (SImode,
4411 gen_rtx_ASHIFTRT (SImode,
4415 emit_insn (gen_rtx_SET (operands[0],
4416 gen_rtx_MINUS (SImode,
4417 gen_rtx_ASHIFTRT (SImode,
4424 [(set_attr "conds" "clob,*")
4425 (set_attr "shift" "1")
4426 (set_attr "predicable" "no, yes")
4427 (set_attr "length" "8")
4428 (set_attr "type" "multiple")]
4431 (define_expand "abssf2"
4432 [(set (match_operand:SF 0 "s_register_operand")
4433 (abs:SF (match_operand:SF 1 "s_register_operand")))]
4434 "TARGET_32BIT && TARGET_HARD_FLOAT"
4437 (define_expand "absdf2"
4438 [(set (match_operand:DF 0 "s_register_operand")
4439 (abs:DF (match_operand:DF 1 "s_register_operand")))]
4440 "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
4443 (define_expand "sqrtsf2"
4444 [(set (match_operand:SF 0 "s_register_operand")
4445 (sqrt:SF (match_operand:SF 1 "s_register_operand")))]
4446 "TARGET_32BIT && TARGET_HARD_FLOAT"
4449 (define_expand "sqrtdf2"
4450 [(set (match_operand:DF 0 "s_register_operand")
4451 (sqrt:DF (match_operand:DF 1 "s_register_operand")))]
4452 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
4455 (define_expand "one_cmplsi2"
4456 [(set (match_operand:SI 0 "s_register_operand")
4457 (not:SI (match_operand:SI 1 "s_register_operand")))]
4462 (define_insn "*arm_one_cmplsi2"
4463 [(set (match_operand:SI 0 "s_register_operand" "=l,r")
4464 (not:SI (match_operand:SI 1 "s_register_operand" "l,r")))]
4467 [(set_attr "predicable" "yes")
4468 (set_attr "predicable_short_it" "yes,no")
4469 (set_attr "arch" "t2,*")
4470 (set_attr "length" "4")
4471 (set_attr "type" "mvn_reg")]
4474 (define_insn "*notsi_compare0"
4475 [(set (reg:CC_NOOV CC_REGNUM)
4476 (compare:CC_NOOV (not:SI (match_operand:SI 1 "s_register_operand" "r"))
4478 (set (match_operand:SI 0 "s_register_operand" "=r")
4479 (not:SI (match_dup 1)))]
4482 [(set_attr "conds" "set")
4483 (set_attr "type" "mvn_reg")]
4486 (define_insn "*notsi_compare0_scratch"
4487 [(set (reg:CC_NOOV CC_REGNUM)
4488 (compare:CC_NOOV (not:SI (match_operand:SI 1 "s_register_operand" "r"))
4490 (clobber (match_scratch:SI 0 "=r"))]
4493 [(set_attr "conds" "set")
4494 (set_attr "type" "mvn_reg")]
4497 ;; Fixed <--> Floating conversion insns
4499 (define_expand "floatsihf2"
4500 [(set (match_operand:HF 0 "general_operand")
4501 (float:HF (match_operand:SI 1 "general_operand")))]
4505 rtx op1 = gen_reg_rtx (SFmode);
4506 expand_float (op1, operands[1], 0);
4507 op1 = convert_to_mode (HFmode, op1, 0);
4508 emit_move_insn (operands[0], op1);
4513 (define_expand "floatdihf2"
4514 [(set (match_operand:HF 0 "general_operand")
4515 (float:HF (match_operand:DI 1 "general_operand")))]
4519 rtx op1 = gen_reg_rtx (SFmode);
4520 expand_float (op1, operands[1], 0);
4521 op1 = convert_to_mode (HFmode, op1, 0);
4522 emit_move_insn (operands[0], op1);
4527 (define_expand "floatsisf2"
4528 [(set (match_operand:SF 0 "s_register_operand")
4529 (float:SF (match_operand:SI 1 "s_register_operand")))]
4530 "TARGET_32BIT && TARGET_HARD_FLOAT"
4534 (define_expand "floatsidf2"
4535 [(set (match_operand:DF 0 "s_register_operand")
4536 (float:DF (match_operand:SI 1 "s_register_operand")))]
4537 "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
4541 (define_expand "fix_trunchfsi2"
4542 [(set (match_operand:SI 0 "general_operand")
4543 (fix:SI (fix:HF (match_operand:HF 1 "general_operand"))))]
4547 rtx op1 = convert_to_mode (SFmode, operands[1], 0);
4548 expand_fix (operands[0], op1, 0);
4553 (define_expand "fix_trunchfdi2"
4554 [(set (match_operand:DI 0 "general_operand")
4555 (fix:DI (fix:HF (match_operand:HF 1 "general_operand"))))]
4559 rtx op1 = convert_to_mode (SFmode, operands[1], 0);
4560 expand_fix (operands[0], op1, 0);
4565 (define_expand "fix_truncsfsi2"
4566 [(set (match_operand:SI 0 "s_register_operand")
4567 (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand"))))]
4568 "TARGET_32BIT && TARGET_HARD_FLOAT"
4572 (define_expand "fix_truncdfsi2"
4573 [(set (match_operand:SI 0 "s_register_operand")
4574 (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand"))))]
4575 "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
4581 (define_expand "truncdfsf2"
4582 [(set (match_operand:SF 0 "s_register_operand")
4584 (match_operand:DF 1 "s_register_operand")))]
4585 "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
4589 ;; DFmode to HFmode conversions on targets without a single-step hardware
4590 ;; instruction for it would have to go through SFmode. This is dangerous
4591 ;; as it introduces double rounding.
4593 ;; Disable this pattern unless we are in an unsafe math mode, or we have
4594 ;; a single-step instruction.
4596 (define_expand "truncdfhf2"
4597 [(set (match_operand:HF 0 "s_register_operand")
4599 (match_operand:DF 1 "s_register_operand")))]
4600 "(TARGET_EITHER && flag_unsafe_math_optimizations)
4601 || (TARGET_32BIT && TARGET_FP16_TO_DOUBLE)"
4603 /* We don't have a direct instruction for this, so we must be in
4604 an unsafe math mode, and going via SFmode. */
4606 if (!(TARGET_32BIT && TARGET_FP16_TO_DOUBLE))
4609 op1 = convert_to_mode (SFmode, operands[1], 0);
4610 op1 = convert_to_mode (HFmode, op1, 0);
4611 emit_move_insn (operands[0], op1);
4614 /* Otherwise, we will pick this up as a single instruction with
4615 no intermediary rounding. */
4619 ;; Zero and sign extension instructions.
4621 (define_insn "zero_extend<mode>di2"
4622 [(set (match_operand:DI 0 "s_register_operand" "=r,?r")
4623 (zero_extend:DI (match_operand:QHSI 1 "<qhs_zextenddi_op>"
4624 "<qhs_zextenddi_cstr>")))]
4625 "TARGET_32BIT <qhs_zextenddi_cond>"
4627 [(set_attr "length" "4,8")
4628 (set_attr "arch" "*,*")
4629 (set_attr "ce_count" "2")
4630 (set_attr "predicable" "yes")
4631 (set_attr "type" "mov_reg,multiple")]
4634 (define_insn "extend<mode>di2"
4635 [(set (match_operand:DI 0 "s_register_operand" "=r,?r,?r")
4636 (sign_extend:DI (match_operand:QHSI 1 "<qhs_extenddi_op>"
4637 "<qhs_extenddi_cstr>")))]
4638 "TARGET_32BIT <qhs_sextenddi_cond>"
4640 [(set_attr "length" "4,8,8")
4641 (set_attr "ce_count" "2")
4642 (set_attr "shift" "1")
4643 (set_attr "predicable" "yes")
4644 (set_attr "arch" "*,a,t")
4645 (set_attr "type" "mov_reg,multiple,multiple")]
4648 ;; Splits for all extensions to DImode
4650 [(set (match_operand:DI 0 "s_register_operand" "")
4651 (zero_extend:DI (match_operand 1 "nonimmediate_operand" "")))]
4653 [(set (match_dup 0) (match_dup 1))]
4655 rtx lo_part = gen_lowpart (SImode, operands[0]);
4656 machine_mode src_mode = GET_MODE (operands[1]);
4658 if (src_mode == SImode)
4659 emit_move_insn (lo_part, operands[1]);
4661 emit_insn (gen_rtx_SET (lo_part,
4662 gen_rtx_ZERO_EXTEND (SImode, operands[1])));
4663 operands[0] = gen_highpart (SImode, operands[0]);
4664 operands[1] = const0_rtx;
4668 [(set (match_operand:DI 0 "s_register_operand" "")
4669 (sign_extend:DI (match_operand 1 "nonimmediate_operand" "")))]
4671 [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (const_int 31)))]
4673 rtx lo_part = gen_lowpart (SImode, operands[0]);
4674 machine_mode src_mode = GET_MODE (operands[1]);
4676 if (src_mode == SImode)
4677 emit_move_insn (lo_part, operands[1]);
4679 emit_insn (gen_rtx_SET (lo_part,
4680 gen_rtx_SIGN_EXTEND (SImode, operands[1])));
4681 operands[1] = lo_part;
4682 operands[0] = gen_highpart (SImode, operands[0]);
4685 (define_expand "zero_extendhisi2"
4686 [(set (match_operand:SI 0 "s_register_operand")
4687 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand")))]
4690 if (TARGET_ARM && !arm_arch4 && MEM_P (operands[1]))
4692 emit_insn (gen_movhi_bytes (operands[0], operands[1]));
4695 if (!arm_arch6 && !MEM_P (operands[1]))
4697 rtx t = gen_lowpart (SImode, operands[1]);
4698 rtx tmp = gen_reg_rtx (SImode);
4699 emit_insn (gen_ashlsi3 (tmp, t, GEN_INT (16)));
4700 emit_insn (gen_lshrsi3 (operands[0], tmp, GEN_INT (16)));
4706 [(set (match_operand:SI 0 "s_register_operand" "")
4707 (zero_extend:SI (match_operand:HI 1 "s_register_operand" "")))]
4708 "!TARGET_THUMB2 && !arm_arch6"
4709 [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16)))
4710 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 16)))]
4712 operands[2] = gen_lowpart (SImode, operands[1]);
4715 (define_insn "*arm_zero_extendhisi2"
4716 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
4717 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
4718 "TARGET_ARM && arm_arch4 && !arm_arch6"
4722 [(set_attr "type" "alu_shift_reg,load_byte")
4723 (set_attr "predicable" "yes")]
4726 (define_insn "*arm_zero_extendhisi2_v6"
4727 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
4728 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,Uh")))]
4729 "TARGET_ARM && arm_arch6"
4733 [(set_attr "predicable" "yes")
4734 (set_attr "type" "extend,load_byte")]
4737 (define_insn "*arm_zero_extendhisi2addsi"
4738 [(set (match_operand:SI 0 "s_register_operand" "=r")
4739 (plus:SI (zero_extend:SI (match_operand:HI 1 "s_register_operand" "r"))
4740 (match_operand:SI 2 "s_register_operand" "r")))]
4742 "uxtah%?\\t%0, %2, %1"
4743 [(set_attr "type" "alu_shift_reg")
4744 (set_attr "predicable" "yes")]
4747 (define_expand "zero_extendqisi2"
4748 [(set (match_operand:SI 0 "s_register_operand")
4749 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand")))]
4752 if (TARGET_ARM && !arm_arch6 && !MEM_P (operands[1]))
4754 emit_insn (gen_andsi3 (operands[0],
4755 gen_lowpart (SImode, operands[1]),
4759 if (!arm_arch6 && !MEM_P (operands[1]))
4761 rtx t = gen_lowpart (SImode, operands[1]);
4762 rtx tmp = gen_reg_rtx (SImode);
4763 emit_insn (gen_ashlsi3 (tmp, t, GEN_INT (24)));
4764 emit_insn (gen_lshrsi3 (operands[0], tmp, GEN_INT (24)));
4770 [(set (match_operand:SI 0 "s_register_operand" "")
4771 (zero_extend:SI (match_operand:QI 1 "s_register_operand" "")))]
4773 [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 24)))
4774 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))]
4776 operands[2] = simplify_gen_subreg (SImode, operands[1], QImode, 0);
4779 emit_insn (gen_andsi3 (operands[0], operands[2], GEN_INT (255)));
4784 (define_insn "*arm_zero_extendqisi2"
4785 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
4786 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
4787 "TARGET_ARM && !arm_arch6"
4790 ldrb%?\\t%0, %1\\t%@ zero_extendqisi2"
4791 [(set_attr "length" "8,4")
4792 (set_attr "type" "alu_shift_reg,load_byte")
4793 (set_attr "predicable" "yes")]
4796 (define_insn "*arm_zero_extendqisi2_v6"
4797 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
4798 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,Uh")))]
4799 "TARGET_ARM && arm_arch6"
4802 ldrb%?\\t%0, %1\\t%@ zero_extendqisi2"
4803 [(set_attr "type" "extend,load_byte")
4804 (set_attr "predicable" "yes")]
4807 (define_insn "*arm_zero_extendqisi2addsi"
4808 [(set (match_operand:SI 0 "s_register_operand" "=r")
4809 (plus:SI (zero_extend:SI (match_operand:QI 1 "s_register_operand" "r"))
4810 (match_operand:SI 2 "s_register_operand" "r")))]
4812 "uxtab%?\\t%0, %2, %1"
4813 [(set_attr "predicable" "yes")
4814 (set_attr "type" "alu_shift_reg")]
4818 [(set (match_operand:SI 0 "s_register_operand" "")
4819 (zero_extend:SI (subreg:QI (match_operand:SI 1 "" "") 0)))
4820 (clobber (match_operand:SI 2 "s_register_operand" ""))]
4821 "TARGET_32BIT && (!MEM_P (operands[1])) && ! BYTES_BIG_ENDIAN"
4822 [(set (match_dup 2) (match_dup 1))
4823 (set (match_dup 0) (and:SI (match_dup 2) (const_int 255)))]
4828 [(set (match_operand:SI 0 "s_register_operand" "")
4829 (zero_extend:SI (subreg:QI (match_operand:SI 1 "" "") 3)))
4830 (clobber (match_operand:SI 2 "s_register_operand" ""))]
4831 "TARGET_32BIT && (!MEM_P (operands[1])) && BYTES_BIG_ENDIAN"
4832 [(set (match_dup 2) (match_dup 1))
4833 (set (match_dup 0) (and:SI (match_dup 2) (const_int 255)))]
4839 [(set (match_operand:SI 0 "s_register_operand" "")
4840 (IOR_XOR:SI (and:SI (ashift:SI
4841 (match_operand:SI 1 "s_register_operand" "")
4842 (match_operand:SI 2 "const_int_operand" ""))
4843 (match_operand:SI 3 "const_int_operand" ""))
4845 (match_operator 5 "subreg_lowpart_operator"
4846 [(match_operand:SI 4 "s_register_operand" "")]))))]
4848 && (UINTVAL (operands[3])
4849 == (GET_MODE_MASK (GET_MODE (operands[5]))
4850 & (GET_MODE_MASK (GET_MODE (operands[5]))
4851 << (INTVAL (operands[2])))))"
4852 [(set (match_dup 0) (IOR_XOR:SI (ashift:SI (match_dup 1) (match_dup 2))
4854 (set (match_dup 0) (zero_extend:SI (match_dup 5)))]
4855 "operands[5] = gen_lowpart (GET_MODE (operands[5]), operands[0]);"
4858 (define_insn "*compareqi_eq0"
4859 [(set (reg:CC_Z CC_REGNUM)
4860 (compare:CC_Z (match_operand:QI 0 "s_register_operand" "r")
4864 [(set_attr "conds" "set")
4865 (set_attr "predicable" "yes")
4866 (set_attr "type" "logic_imm")]
4869 (define_expand "extendhisi2"
4870 [(set (match_operand:SI 0 "s_register_operand")
4871 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand")))]
4876 emit_insn (gen_thumb1_extendhisi2 (operands[0], operands[1]));
4879 if (MEM_P (operands[1]) && TARGET_ARM && !arm_arch4)
4881 emit_insn (gen_extendhisi2_mem (operands[0], operands[1]));
4885 if (!arm_arch6 && !MEM_P (operands[1]))
4887 rtx t = gen_lowpart (SImode, operands[1]);
4888 rtx tmp = gen_reg_rtx (SImode);
4889 emit_insn (gen_ashlsi3 (tmp, t, GEN_INT (16)));
4890 emit_insn (gen_ashrsi3 (operands[0], tmp, GEN_INT (16)));
4897 [(set (match_operand:SI 0 "register_operand" "")
4898 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))
4899 (clobber (match_scratch:SI 2 ""))])]
4901 [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16)))
4902 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 16)))]
4904 operands[2] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
4907 ;; This pattern will only be used when ldsh is not available
4908 (define_expand "extendhisi2_mem"
4909 [(set (match_dup 2) (zero_extend:SI (match_operand:HI 1 "" "")))
4911 (zero_extend:SI (match_dup 7)))
4912 (set (match_dup 6) (ashift:SI (match_dup 4) (const_int 24)))
4913 (set (match_operand:SI 0 "" "")
4914 (ior:SI (ashiftrt:SI (match_dup 6) (const_int 16)) (match_dup 5)))]
4919 rtx addr = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
4921 mem1 = change_address (operands[1], QImode, addr);
4922 mem2 = change_address (operands[1], QImode,
4923 plus_constant (Pmode, addr, 1));
4924 operands[0] = gen_lowpart (SImode, operands[0]);
4926 operands[2] = gen_reg_rtx (SImode);
4927 operands[3] = gen_reg_rtx (SImode);
4928 operands[6] = gen_reg_rtx (SImode);
4931 if (BYTES_BIG_ENDIAN)
4933 operands[4] = operands[2];
4934 operands[5] = operands[3];
4938 operands[4] = operands[3];
4939 operands[5] = operands[2];
4945 [(set (match_operand:SI 0 "register_operand" "")
4946 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
4948 [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16)))
4949 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 16)))]
4951 operands[2] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
4954 (define_insn "*arm_extendhisi2"
4955 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
4956 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,Uh")))]
4957 "TARGET_ARM && arm_arch4 && !arm_arch6"
4961 [(set_attr "length" "8,4")
4962 (set_attr "type" "alu_shift_reg,load_byte")
4963 (set_attr "predicable" "yes")]
4966 ;; ??? Check Thumb-2 pool range
4967 (define_insn "*arm_extendhisi2_v6"
4968 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
4969 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,Uh")))]
4970 "TARGET_32BIT && arm_arch6"
4974 [(set_attr "type" "extend,load_byte")
4975 (set_attr "predicable" "yes")]
4978 (define_insn "*arm_extendhisi2addsi"
4979 [(set (match_operand:SI 0 "s_register_operand" "=r")
4980 (plus:SI (sign_extend:SI (match_operand:HI 1 "s_register_operand" "r"))
4981 (match_operand:SI 2 "s_register_operand" "r")))]
4983 "sxtah%?\\t%0, %2, %1"
4984 [(set_attr "type" "alu_shift_reg")]
4987 (define_expand "extendqihi2"
4989 (ashift:SI (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op")
4991 (set (match_operand:HI 0 "s_register_operand")
4992 (ashiftrt:SI (match_dup 2)
4997 if (arm_arch4 && MEM_P (operands[1]))
4999 emit_insn (gen_rtx_SET (operands[0],
5000 gen_rtx_SIGN_EXTEND (HImode, operands[1])));
5003 if (!s_register_operand (operands[1], QImode))
5004 operands[1] = copy_to_mode_reg (QImode, operands[1]);
5005 operands[0] = gen_lowpart (SImode, operands[0]);
5006 operands[1] = gen_lowpart (SImode, operands[1]);
5007 operands[2] = gen_reg_rtx (SImode);
5011 (define_insn "*arm_extendqihi_insn"
5012 [(set (match_operand:HI 0 "s_register_operand" "=r")
5013 (sign_extend:HI (match_operand:QI 1 "arm_extendqisi_mem_op" "Uq")))]
5014 "TARGET_ARM && arm_arch4"
5016 [(set_attr "type" "load_byte")
5017 (set_attr "predicable" "yes")]
5020 (define_expand "extendqisi2"
5021 [(set (match_operand:SI 0 "s_register_operand")
5022 (sign_extend:SI (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op")))]
5025 if (!arm_arch4 && MEM_P (operands[1]))
5026 operands[1] = copy_to_mode_reg (QImode, operands[1]);
5028 if (!arm_arch6 && !MEM_P (operands[1]))
5030 rtx t = gen_lowpart (SImode, operands[1]);
5031 rtx tmp = gen_reg_rtx (SImode);
5032 emit_insn (gen_ashlsi3 (tmp, t, GEN_INT (24)));
5033 emit_insn (gen_ashrsi3 (operands[0], tmp, GEN_INT (24)));
5039 [(set (match_operand:SI 0 "register_operand" "")
5040 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
5042 [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 24)))
5043 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))]
5045 operands[2] = simplify_gen_subreg (SImode, operands[1], QImode, 0);
5048 (define_insn "*arm_extendqisi"
5049 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
5050 (sign_extend:SI (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "r,Uq")))]
5051 "TARGET_ARM && arm_arch4 && !arm_arch6"
5055 [(set_attr "length" "8,4")
5056 (set_attr "type" "alu_shift_reg,load_byte")
5057 (set_attr "predicable" "yes")]
5060 (define_insn "*arm_extendqisi_v6"
5061 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
5063 (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "r,Uq")))]
5064 "TARGET_ARM && arm_arch6"
5068 [(set_attr "type" "extend,load_byte")
5069 (set_attr "predicable" "yes")]
5072 (define_insn "*arm_extendqisi2addsi"
5073 [(set (match_operand:SI 0 "s_register_operand" "=r")
5074 (plus:SI (sign_extend:SI (match_operand:QI 1 "s_register_operand" "r"))
5075 (match_operand:SI 2 "s_register_operand" "r")))]
5077 "sxtab%?\\t%0, %2, %1"
5078 [(set_attr "type" "alu_shift_reg")
5079 (set_attr "predicable" "yes")]
5082 (define_expand "extendsfdf2"
5083 [(set (match_operand:DF 0 "s_register_operand")
5084 (float_extend:DF (match_operand:SF 1 "s_register_operand")))]
5085 "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
5089 ;; HFmode -> DFmode conversions where we don't have an instruction for it
5090 ;; must go through SFmode.
5092 ;; This is always safe for an extend.
5094 (define_expand "extendhfdf2"
5095 [(set (match_operand:DF 0 "s_register_operand")
5096 (float_extend:DF (match_operand:HF 1 "s_register_operand")))]
5099 /* We don't have a direct instruction for this, so go via SFmode. */
5100 if (!(TARGET_32BIT && TARGET_FP16_TO_DOUBLE))
5103 op1 = convert_to_mode (SFmode, operands[1], 0);
5104 op1 = convert_to_mode (DFmode, op1, 0);
5105 emit_insn (gen_movdf (operands[0], op1));
5108 /* Otherwise, we're done producing RTL and will pick up the correct
5109 pattern to do this with one rounding-step in a single instruction. */
5113 ;; Move insns (including loads and stores)
5115 ;; XXX Just some ideas about movti.
5116 ;; I don't think these are a good idea on the arm, there just aren't enough
5118 ;;(define_expand "loadti"
5119 ;; [(set (match_operand:TI 0 "s_register_operand")
5120 ;; (mem:TI (match_operand:SI 1 "address_operand")))]
5123 ;;(define_expand "storeti"
5124 ;; [(set (mem:TI (match_operand:TI 0 "address_operand"))
5125 ;; (match_operand:TI 1 "s_register_operand"))]
5128 ;;(define_expand "movti"
5129 ;; [(set (match_operand:TI 0 "general_operand")
5130 ;; (match_operand:TI 1 "general_operand"))]
5136 ;; if (MEM_P (operands[0]) && MEM_P (operands[1]))
5137 ;; operands[1] = copy_to_reg (operands[1]);
5138 ;; if (MEM_P (operands[0]))
5139 ;; insn = gen_storeti (XEXP (operands[0], 0), operands[1]);
5140 ;; else if (MEM_P (operands[1]))
5141 ;; insn = gen_loadti (operands[0], XEXP (operands[1], 0));
5145 ;; emit_insn (insn);
5149 ;; Recognize garbage generated above.
5152 ;; [(set (match_operand:TI 0 "general_operand" "=r,r,r,<,>,m")
5153 ;; (match_operand:TI 1 "general_operand" "<,>,m,r,r,r"))]
5157 ;; register mem = (which_alternative < 3);
5158 ;; register const char *template;
5160 ;; operands[mem] = XEXP (operands[mem], 0);
5161 ;; switch (which_alternative)
5163 ;; case 0: template = \"ldmdb\\t%1!, %M0\"; break;
5164 ;; case 1: template = \"ldmia\\t%1!, %M0\"; break;
5165 ;; case 2: template = \"ldmia\\t%1, %M0\"; break;
5166 ;; case 3: template = \"stmdb\\t%0!, %M1\"; break;
5167 ;; case 4: template = \"stmia\\t%0!, %M1\"; break;
5168 ;; case 5: template = \"stmia\\t%0, %M1\"; break;
5170 ;; output_asm_insn (template, operands);
5174 (define_expand "movdi"
5175 [(set (match_operand:DI 0 "general_operand")
5176 (match_operand:DI 1 "general_operand"))]
5179 gcc_checking_assert (aligned_operand (operands[0], DImode));
5180 gcc_checking_assert (aligned_operand (operands[1], DImode));
5181 if (can_create_pseudo_p ())
5183 if (!REG_P (operands[0]))
5184 operands[1] = force_reg (DImode, operands[1]);
5186 if (REG_P (operands[0]) && REGNO (operands[0]) <= LAST_ARM_REGNUM
5187 && !targetm.hard_regno_mode_ok (REGNO (operands[0]), DImode))
5189 /* Avoid LDRD's into an odd-numbered register pair in ARM state
5190 when expanding function calls. */
5191 gcc_assert (can_create_pseudo_p ());
5192 if (MEM_P (operands[1]) && MEM_VOLATILE_P (operands[1]))
5194 /* Perform load into legal reg pair first, then move. */
5195 rtx reg = gen_reg_rtx (DImode);
5196 emit_insn (gen_movdi (reg, operands[1]));
5199 emit_move_insn (gen_lowpart (SImode, operands[0]),
5200 gen_lowpart (SImode, operands[1]));
5201 emit_move_insn (gen_highpart (SImode, operands[0]),
5202 gen_highpart (SImode, operands[1]));
5205 else if (REG_P (operands[1]) && REGNO (operands[1]) <= LAST_ARM_REGNUM
5206 && !targetm.hard_regno_mode_ok (REGNO (operands[1]), DImode))
5208 /* Avoid STRD's from an odd-numbered register pair in ARM state
5209 when expanding function prologue. */
5210 gcc_assert (can_create_pseudo_p ());
5211 rtx split_dest = (MEM_P (operands[0]) && MEM_VOLATILE_P (operands[0]))
5212 ? gen_reg_rtx (DImode)
5214 emit_move_insn (gen_lowpart (SImode, split_dest),
5215 gen_lowpart (SImode, operands[1]));
5216 emit_move_insn (gen_highpart (SImode, split_dest),
5217 gen_highpart (SImode, operands[1]));
5218 if (split_dest != operands[0])
5219 emit_insn (gen_movdi (operands[0], split_dest));
5225 (define_insn "*arm_movdi"
5226 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, r, m")
5227 (match_operand:DI 1 "di_operand" "rDa,Db,Dc,mi,r"))]
5229 && !(TARGET_HARD_FLOAT)
5231 && ( register_operand (operands[0], DImode)
5232 || register_operand (operands[1], DImode))"
5234 switch (which_alternative)
5241 /* Cannot load it directly, split to load it via MOV / MOVT. */
5242 if (!MEM_P (operands[1]) && arm_disable_literal_pool)
5246 return output_move_double (operands, true, NULL);
5249 [(set_attr "length" "8,12,16,8,8")
5250 (set_attr "type" "multiple,multiple,multiple,load_8,store_8")
5251 (set_attr "arm_pool_range" "*,*,*,1020,*")
5252 (set_attr "arm_neg_pool_range" "*,*,*,1004,*")
5253 (set_attr "thumb2_pool_range" "*,*,*,4094,*")
5254 (set_attr "thumb2_neg_pool_range" "*,*,*,0,*")]
5258 [(set (match_operand:ANY64 0 "arm_general_register_operand" "")
5259 (match_operand:ANY64 1 "immediate_operand" ""))]
5262 && (arm_disable_literal_pool
5263 || (arm_const_double_inline_cost (operands[1])
5264 <= arm_max_const_double_inline_cost ()))"
5267 arm_split_constant (SET, SImode, curr_insn,
5268 INTVAL (gen_lowpart (SImode, operands[1])),
5269 gen_lowpart (SImode, operands[0]), NULL_RTX, 0);
5270 arm_split_constant (SET, SImode, curr_insn,
5271 INTVAL (gen_highpart_mode (SImode,
5272 GET_MODE (operands[0]),
5274 gen_highpart (SImode, operands[0]), NULL_RTX, 0);
5279 ; If optimizing for size, or if we have load delay slots, then
5280 ; we want to split the constant into two separate operations.
5281 ; In both cases this may split a trivial part into a single data op
5282 ; leaving a single complex constant to load. We can also get longer
5283 ; offsets in a LDR which means we get better chances of sharing the pool
5284 ; entries. Finally, we can normally do a better job of scheduling
5285 ; LDR instructions than we can with LDM.
5286 ; This pattern will only match if the one above did not.
5288 [(set (match_operand:ANY64 0 "arm_general_register_operand" "")
5289 (match_operand:ANY64 1 "const_double_operand" ""))]
5290 "TARGET_ARM && reload_completed
5291 && arm_const_double_by_parts (operands[1])"
5292 [(set (match_dup 0) (match_dup 1))
5293 (set (match_dup 2) (match_dup 3))]
5295 operands[2] = gen_highpart (SImode, operands[0]);
5296 operands[3] = gen_highpart_mode (SImode, GET_MODE (operands[0]),
5298 operands[0] = gen_lowpart (SImode, operands[0]);
5299 operands[1] = gen_lowpart (SImode, operands[1]);
5304 [(set (match_operand:ANY64 0 "arm_general_register_operand" "")
5305 (match_operand:ANY64 1 "arm_general_register_operand" ""))]
5306 "TARGET_EITHER && reload_completed"
5307 [(set (match_dup 0) (match_dup 1))
5308 (set (match_dup 2) (match_dup 3))]
5310 operands[2] = gen_highpart (SImode, operands[0]);
5311 operands[3] = gen_highpart (SImode, operands[1]);
5312 operands[0] = gen_lowpart (SImode, operands[0]);
5313 operands[1] = gen_lowpart (SImode, operands[1]);
5315 /* Handle a partial overlap. */
5316 if (rtx_equal_p (operands[0], operands[3]))
5318 rtx tmp0 = operands[0];
5319 rtx tmp1 = operands[1];
5321 operands[0] = operands[2];
5322 operands[1] = operands[3];
5329 ;; We can't actually do base+index doubleword loads if the index and
5330 ;; destination overlap. Split here so that we at least have chance to
5333 [(set (match_operand:DI 0 "s_register_operand" "")
5334 (mem:DI (plus:SI (match_operand:SI 1 "s_register_operand" "")
5335 (match_operand:SI 2 "s_register_operand" ""))))]
5337 && reg_overlap_mentioned_p (operands[0], operands[1])
5338 && reg_overlap_mentioned_p (operands[0], operands[2])"
5340 (plus:SI (match_dup 1)
5343 (mem:DI (match_dup 4)))]
5345 operands[4] = gen_rtx_REG (SImode, REGNO(operands[0]));
5349 (define_expand "movsi"
5350 [(set (match_operand:SI 0 "general_operand")
5351 (match_operand:SI 1 "general_operand"))]
5355 rtx base, offset, tmp;
5357 gcc_checking_assert (aligned_operand (operands[0], SImode));
5358 gcc_checking_assert (aligned_operand (operands[1], SImode));
5359 if (TARGET_32BIT || TARGET_HAVE_MOVT)
5361 /* Everything except mem = const or mem = mem can be done easily. */
5362 if (MEM_P (operands[0]))
5363 operands[1] = force_reg (SImode, operands[1]);
5364 if (arm_general_register_operand (operands[0], SImode)
5365 && CONST_INT_P (operands[1])
5366 && !(const_ok_for_arm (INTVAL (operands[1]))
5367 || const_ok_for_arm (~INTVAL (operands[1]))))
5369 if (DONT_EARLY_SPLIT_CONSTANT (INTVAL (operands[1]), SET))
5371 emit_insn (gen_rtx_SET (operands[0], operands[1]));
5376 arm_split_constant (SET, SImode, NULL_RTX,
5377 INTVAL (operands[1]), operands[0], NULL_RTX,
5378 optimize && can_create_pseudo_p ());
5383 else /* Target doesn't have MOVT... */
5385 if (can_create_pseudo_p ())
5387 if (!REG_P (operands[0]))
5388 operands[1] = force_reg (SImode, operands[1]);
5392 split_const (operands[1], &base, &offset);
5393 if (INTVAL (offset) != 0
5394 && targetm.cannot_force_const_mem (SImode, operands[1]))
5396 tmp = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0];
5397 emit_move_insn (tmp, base);
5398 emit_insn (gen_addsi3 (operands[0], tmp, offset));
5402 tmp = can_create_pseudo_p () ? NULL_RTX : operands[0];
5404 /* Recognize the case where operand[1] is a reference to thread-local
5405 data and load its address to a register. Offsets have been split off
5407 if (arm_tls_referenced_p (operands[1]))
5408 operands[1] = legitimize_tls_address (operands[1], tmp);
5410 && (CONSTANT_P (operands[1])
5411 || symbol_mentioned_p (operands[1])
5412 || label_mentioned_p (operands[1])))
5414 legitimize_pic_address (operands[1], SImode, tmp, NULL_RTX, false);
5419 ;; The ARM LO_SUM and HIGH are backwards - HIGH sets the low bits, and
5420 ;; LO_SUM adds in the high bits. Fortunately these are opaque operations
5421 ;; so this does not matter.
5422 (define_insn "*arm_movt"
5423 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r")
5424 (lo_sum:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
5425 (match_operand:SI 2 "general_operand" "i,i")))]
5426 "TARGET_HAVE_MOVT && arm_valid_symbolic_address_p (operands[2])"
5428 movt%?\t%0, #:upper16:%c2
5429 movt\t%0, #:upper16:%c2"
5430 [(set_attr "arch" "32,v8mb")
5431 (set_attr "predicable" "yes")
5432 (set_attr "length" "4")
5433 (set_attr "type" "alu_sreg")]
5436 (define_insn "*arm_movsi_insn"
5437 [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m")
5438 (match_operand:SI 1 "general_operand" "rk, I,K,j,mi,rk"))]
5439 "TARGET_ARM && !TARGET_IWMMXT && !TARGET_HARD_FLOAT
5440 && ( register_operand (operands[0], SImode)
5441 || register_operand (operands[1], SImode))"
5449 [(set_attr "type" "mov_reg,mov_imm,mvn_imm,mov_imm,load_4,store_4")
5450 (set_attr "predicable" "yes")
5451 (set_attr "arch" "*,*,*,v6t2,*,*")
5452 (set_attr "pool_range" "*,*,*,*,4096,*")
5453 (set_attr "neg_pool_range" "*,*,*,*,4084,*")]
5457 [(set (match_operand:SI 0 "arm_general_register_operand" "")
5458 (match_operand:SI 1 "const_int_operand" ""))]
5459 "(TARGET_32BIT || TARGET_HAVE_MOVT)
5460 && (!(const_ok_for_arm (INTVAL (operands[1]))
5461 || const_ok_for_arm (~INTVAL (operands[1]))))"
5462 [(clobber (const_int 0))]
5464 arm_split_constant (SET, SImode, NULL_RTX,
5465 INTVAL (operands[1]), operands[0], NULL_RTX, 0);
5470 ;; A normal way to do (symbol + offset) requires three instructions at least
5471 ;; (depends on how big the offset is) as below:
5472 ;; movw r0, #:lower16:g
5473 ;; movw r0, #:upper16:g
5476 ;; A better way would be:
5477 ;; movw r0, #:lower16:g+4
5478 ;; movw r0, #:upper16:g+4
5480 ;; The limitation of this way is that the length of offset should be a 16-bit
5481 ;; signed value, because current assembler only supports REL type relocation for
5482 ;; such case. If the more powerful RELA type is supported in future, we should
5483 ;; update this pattern to go with better way.
5485 [(set (match_operand:SI 0 "arm_general_register_operand" "")
5486 (const:SI (plus:SI (match_operand:SI 1 "general_operand" "")
5487 (match_operand:SI 2 "const_int_operand" ""))))]
5490 && arm_disable_literal_pool
5492 && GET_CODE (operands[1]) == SYMBOL_REF"
5493 [(clobber (const_int 0))]
5495 int offset = INTVAL (operands[2]);
5497 if (offset < -0x8000 || offset > 0x7fff)
5499 arm_emit_movpair (operands[0], operands[1]);
5500 emit_insn (gen_rtx_SET (operands[0],
5501 gen_rtx_PLUS (SImode, operands[0], operands[2])));
5505 rtx op = gen_rtx_CONST (SImode,
5506 gen_rtx_PLUS (SImode, operands[1], operands[2]));
5507 arm_emit_movpair (operands[0], op);
5512 ;; Split symbol_refs at the later stage (after cprop), instead of generating
5513 ;; movt/movw pair directly at expand. Otherwise corresponding high_sum
5514 ;; and lo_sum would be merged back into memory load at cprop. However,
5515 ;; if the default is to prefer movt/movw rather than a load from the constant
5516 ;; pool, the performance is better.
5518 [(set (match_operand:SI 0 "arm_general_register_operand" "")
5519 (match_operand:SI 1 "general_operand" ""))]
5520 "TARGET_USE_MOVT && GET_CODE (operands[1]) == SYMBOL_REF
5521 && !target_word_relocations
5522 && !arm_tls_referenced_p (operands[1])"
5523 [(clobber (const_int 0))]
5525 arm_emit_movpair (operands[0], operands[1]);
5529 ;; When generating pic, we need to load the symbol offset into a register.
5530 ;; So that the optimizer does not confuse this with a normal symbol load
5531 ;; we use an unspec. The offset will be loaded from a constant pool entry,
5532 ;; since that is the only type of relocation we can use.
5534 ;; Wrap calculation of the whole PIC address in a single pattern for the
5535 ;; benefit of optimizers, particularly, PRE and HOIST. Calculation of
5536 ;; a PIC address involves two loads from memory, so we want to CSE it
5537 ;; as often as possible.
5538 ;; This pattern will be split into one of the pic_load_addr_* patterns
5539 ;; and a move after GCSE optimizations.
5541 ;; Note: Update arm.c: legitimize_pic_address() when changing this pattern.
5542 (define_expand "calculate_pic_address"
5543 [(set (match_operand:SI 0 "register_operand")
5544 (mem:SI (plus:SI (match_operand:SI 1 "register_operand")
5545 (unspec:SI [(match_operand:SI 2 "" "")]
5550 ;; Split calculate_pic_address into pic_load_addr_* and a move.
5552 [(set (match_operand:SI 0 "register_operand" "")
5553 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "")
5554 (unspec:SI [(match_operand:SI 2 "" "")]
5557 [(set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_PIC_SYM))
5558 (set (match_dup 0) (mem:SI (plus:SI (match_dup 1) (match_dup 3))))]
5559 "operands[3] = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0];"
5562 ;; operand1 is the memory address to go into
5563 ;; pic_load_addr_32bit.
5564 ;; operand2 is the PIC label to be emitted
5565 ;; from pic_add_dot_plus_eight.
5566 ;; We do this to allow hoisting of the entire insn.
5567 (define_insn_and_split "pic_load_addr_unified"
5568 [(set (match_operand:SI 0 "s_register_operand" "=r,r,l")
5569 (unspec:SI [(match_operand:SI 1 "" "mX,mX,mX")
5570 (match_operand:SI 2 "" "")]
5571 UNSPEC_PIC_UNIFIED))]
5574 "&& reload_completed"
5575 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_PIC_SYM))
5576 (set (match_dup 0) (unspec:SI [(match_dup 0) (match_dup 3)
5577 (match_dup 2)] UNSPEC_PIC_BASE))]
5578 "operands[3] = TARGET_THUMB ? GEN_INT (4) : GEN_INT (8);"
5579 [(set_attr "type" "load_4,load_4,load_4")
5580 (set_attr "pool_range" "4096,4094,1022")
5581 (set_attr "neg_pool_range" "4084,0,0")
5582 (set_attr "arch" "a,t2,t1")
5583 (set_attr "length" "8,6,4")]
5586 ;; The rather odd constraints on the following are to force reload to leave
5587 ;; the insn alone, and to force the minipool generation pass to then move
5588 ;; the GOT symbol to memory.
5590 (define_insn "pic_load_addr_32bit"
5591 [(set (match_operand:SI 0 "s_register_operand" "=r")
5592 (unspec:SI [(match_operand:SI 1 "" "mX")] UNSPEC_PIC_SYM))]
5593 "TARGET_32BIT && flag_pic"
5595 [(set_attr "type" "load_4")
5596 (set (attr "pool_range")
5597 (if_then_else (eq_attr "is_thumb" "no")
5600 (set (attr "neg_pool_range")
5601 (if_then_else (eq_attr "is_thumb" "no")
5606 (define_insn "pic_load_addr_thumb1"
5607 [(set (match_operand:SI 0 "s_register_operand" "=l")
5608 (unspec:SI [(match_operand:SI 1 "" "mX")] UNSPEC_PIC_SYM))]
5609 "TARGET_THUMB1 && flag_pic"
5611 [(set_attr "type" "load_4")
5612 (set (attr "pool_range") (const_int 1018))]
5615 (define_insn "pic_add_dot_plus_four"
5616 [(set (match_operand:SI 0 "register_operand" "=r")
5617 (unspec:SI [(match_operand:SI 1 "register_operand" "0")
5619 (match_operand 2 "" "")]
5623 (*targetm.asm_out.internal_label) (asm_out_file, \"LPIC\",
5624 INTVAL (operands[2]));
5625 return \"add\\t%0, %|pc\";
5627 [(set_attr "length" "2")
5628 (set_attr "type" "alu_sreg")]
5631 (define_insn "pic_add_dot_plus_eight"
5632 [(set (match_operand:SI 0 "register_operand" "=r")
5633 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
5635 (match_operand 2 "" "")]
5639 (*targetm.asm_out.internal_label) (asm_out_file, \"LPIC\",
5640 INTVAL (operands[2]));
5641 return \"add%?\\t%0, %|pc, %1\";
5643 [(set_attr "predicable" "yes")
5644 (set_attr "type" "alu_sreg")]
5647 (define_insn "tls_load_dot_plus_eight"
5648 [(set (match_operand:SI 0 "register_operand" "=r")
5649 (mem:SI (unspec:SI [(match_operand:SI 1 "register_operand" "r")
5651 (match_operand 2 "" "")]
5655 (*targetm.asm_out.internal_label) (asm_out_file, \"LPIC\",
5656 INTVAL (operands[2]));
5657 return \"ldr%?\\t%0, [%|pc, %1]\t\t@ tls_load_dot_plus_eight\";
5659 [(set_attr "predicable" "yes")
5660 (set_attr "type" "load_4")]
5663 ;; PIC references to local variables can generate pic_add_dot_plus_eight
5664 ;; followed by a load. These sequences can be crunched down to
5665 ;; tls_load_dot_plus_eight by a peephole.
5668 [(set (match_operand:SI 0 "register_operand" "")
5669 (unspec:SI [(match_operand:SI 3 "register_operand" "")
5671 (match_operand 1 "" "")]
5673 (set (match_operand:SI 2 "arm_general_register_operand" "")
5674 (mem:SI (match_dup 0)))]
5675 "TARGET_ARM && peep2_reg_dead_p (2, operands[0])"
5677 (mem:SI (unspec:SI [(match_dup 3)
5684 (define_insn "pic_offset_arm"
5685 [(set (match_operand:SI 0 "register_operand" "=r")
5686 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
5687 (unspec:SI [(match_operand:SI 2 "" "X")]
5688 UNSPEC_PIC_OFFSET))))]
5689 "TARGET_VXWORKS_RTP && TARGET_ARM && flag_pic"
5690 "ldr%?\\t%0, [%1,%2]"
5691 [(set_attr "type" "load_4")]
5694 (define_expand "builtin_setjmp_receiver"
5695 [(label_ref (match_operand 0 "" ""))]
5699 /* r3 is clobbered by set/longjmp, so we can use it as a scratch
5701 if (arm_pic_register != INVALID_REGNUM)
5702 arm_load_pic_register (1UL << 3, NULL_RTX);
5706 ;; If copying one reg to another we can set the condition codes according to
5707 ;; its value. Such a move is common after a return from subroutine and the
5708 ;; result is being tested against zero.
5710 (define_insn "*movsi_compare0"
5711 [(set (reg:CC CC_REGNUM)
5712 (compare:CC (match_operand:SI 1 "s_register_operand" "0,r")
5714 (set (match_operand:SI 0 "s_register_operand" "=r,r")
5719 subs%?\\t%0, %1, #0"
5720 [(set_attr "conds" "set")
5721 (set_attr "type" "alus_imm,alus_imm")]
5724 ;; Subroutine to store a half word from a register into memory.
5725 ;; Operand 0 is the source register (HImode)
5726 ;; Operand 1 is the destination address in a register (SImode)
5728 ;; In both this routine and the next, we must be careful not to spill
5729 ;; a memory address of reg+large_const into a separate PLUS insn, since this
5730 ;; can generate unrecognizable rtl.
5732 (define_expand "storehi"
5733 [;; store the low byte
5734 (set (match_operand 1 "" "") (match_dup 3))
5735 ;; extract the high byte
5737 (ashiftrt:SI (match_operand 0 "" "") (const_int 8)))
5738 ;; store the high byte
5739 (set (match_dup 4) (match_dup 5))]
5743 rtx op1 = operands[1];
5744 rtx addr = XEXP (op1, 0);
5745 enum rtx_code code = GET_CODE (addr);
5747 if ((code == PLUS && !CONST_INT_P (XEXP (addr, 1)))
5749 op1 = replace_equiv_address (operands[1], force_reg (SImode, addr));
5751 operands[4] = adjust_address (op1, QImode, 1);
5752 operands[1] = adjust_address (operands[1], QImode, 0);
5753 operands[3] = gen_lowpart (QImode, operands[0]);
5754 operands[0] = gen_lowpart (SImode, operands[0]);
5755 operands[2] = gen_reg_rtx (SImode);
5756 operands[5] = gen_lowpart (QImode, operands[2]);
5760 (define_expand "storehi_bigend"
5761 [(set (match_dup 4) (match_dup 3))
5763 (ashiftrt:SI (match_operand 0 "" "") (const_int 8)))
5764 (set (match_operand 1 "" "") (match_dup 5))]
5768 rtx op1 = operands[1];
5769 rtx addr = XEXP (op1, 0);
5770 enum rtx_code code = GET_CODE (addr);
5772 if ((code == PLUS && !CONST_INT_P (XEXP (addr, 1)))
5774 op1 = replace_equiv_address (op1, force_reg (SImode, addr));
5776 operands[4] = adjust_address (op1, QImode, 1);
5777 operands[1] = adjust_address (operands[1], QImode, 0);
5778 operands[3] = gen_lowpart (QImode, operands[0]);
5779 operands[0] = gen_lowpart (SImode, operands[0]);
5780 operands[2] = gen_reg_rtx (SImode);
5781 operands[5] = gen_lowpart (QImode, operands[2]);
5785 ;; Subroutine to store a half word integer constant into memory.
5786 (define_expand "storeinthi"
5787 [(set (match_operand 0 "" "")
5788 (match_operand 1 "" ""))
5789 (set (match_dup 3) (match_dup 2))]
5793 HOST_WIDE_INT value = INTVAL (operands[1]);
5794 rtx addr = XEXP (operands[0], 0);
5795 rtx op0 = operands[0];
5796 enum rtx_code code = GET_CODE (addr);
5798 if ((code == PLUS && !CONST_INT_P (XEXP (addr, 1)))
5800 op0 = replace_equiv_address (op0, force_reg (SImode, addr));
5802 operands[1] = gen_reg_rtx (SImode);
5803 if (BYTES_BIG_ENDIAN)
5805 emit_insn (gen_movsi (operands[1], GEN_INT ((value >> 8) & 255)));
5806 if ((value & 255) == ((value >> 8) & 255))
5807 operands[2] = operands[1];
5810 operands[2] = gen_reg_rtx (SImode);
5811 emit_insn (gen_movsi (operands[2], GEN_INT (value & 255)));
5816 emit_insn (gen_movsi (operands[1], GEN_INT (value & 255)));
5817 if ((value & 255) == ((value >> 8) & 255))
5818 operands[2] = operands[1];
5821 operands[2] = gen_reg_rtx (SImode);
5822 emit_insn (gen_movsi (operands[2], GEN_INT ((value >> 8) & 255)));
5826 operands[3] = adjust_address (op0, QImode, 1);
5827 operands[0] = adjust_address (operands[0], QImode, 0);
5828 operands[2] = gen_lowpart (QImode, operands[2]);
5829 operands[1] = gen_lowpart (QImode, operands[1]);
5833 (define_expand "storehi_single_op"
5834 [(set (match_operand:HI 0 "memory_operand")
5835 (match_operand:HI 1 "general_operand"))]
5836 "TARGET_32BIT && arm_arch4"
5838 if (!s_register_operand (operands[1], HImode))
5839 operands[1] = copy_to_mode_reg (HImode, operands[1]);
5843 (define_expand "movhi"
5844 [(set (match_operand:HI 0 "general_operand")
5845 (match_operand:HI 1 "general_operand"))]
5848 gcc_checking_assert (aligned_operand (operands[0], HImode));
5849 gcc_checking_assert (aligned_operand (operands[1], HImode));
5852 if (can_create_pseudo_p ())
5854 if (MEM_P (operands[0]))
5858 emit_insn (gen_storehi_single_op (operands[0], operands[1]));
5861 if (CONST_INT_P (operands[1]))
5862 emit_insn (gen_storeinthi (operands[0], operands[1]));
5865 if (MEM_P (operands[1]))
5866 operands[1] = force_reg (HImode, operands[1]);
5867 if (BYTES_BIG_ENDIAN)
5868 emit_insn (gen_storehi_bigend (operands[1], operands[0]));
5870 emit_insn (gen_storehi (operands[1], operands[0]));
5874 /* Sign extend a constant, and keep it in an SImode reg. */
5875 else if (CONST_INT_P (operands[1]))
5877 rtx reg = gen_reg_rtx (SImode);
5878 HOST_WIDE_INT val = INTVAL (operands[1]) & 0xffff;
5880 /* If the constant is already valid, leave it alone. */
5881 if (!const_ok_for_arm (val))
5883 /* If setting all the top bits will make the constant
5884 loadable in a single instruction, then set them.
5885 Otherwise, sign extend the number. */
5887 if (const_ok_for_arm (~(val | ~0xffff)))
5889 else if (val & 0x8000)
5893 emit_insn (gen_movsi (reg, GEN_INT (val)));
5894 operands[1] = gen_lowpart (HImode, reg);
5896 else if (arm_arch4 && optimize && can_create_pseudo_p ()
5897 && MEM_P (operands[1]))
5899 rtx reg = gen_reg_rtx (SImode);
5901 emit_insn (gen_zero_extendhisi2 (reg, operands[1]));
5902 operands[1] = gen_lowpart (HImode, reg);
5904 else if (!arm_arch4)
5906 if (MEM_P (operands[1]))
5909 rtx offset = const0_rtx;
5910 rtx reg = gen_reg_rtx (SImode);
5912 if ((REG_P (base = XEXP (operands[1], 0))
5913 || (GET_CODE (base) == PLUS
5914 && (CONST_INT_P (offset = XEXP (base, 1)))
5915 && ((INTVAL(offset) & 1) != 1)
5916 && REG_P (base = XEXP (base, 0))))
5917 && REGNO_POINTER_ALIGN (REGNO (base)) >= 32)
5921 new_rtx = widen_memory_access (operands[1], SImode,
5922 ((INTVAL (offset) & ~3)
5923 - INTVAL (offset)));
5924 emit_insn (gen_movsi (reg, new_rtx));
5925 if (((INTVAL (offset) & 2) != 0)
5926 ^ (BYTES_BIG_ENDIAN ? 1 : 0))
5928 rtx reg2 = gen_reg_rtx (SImode);
5930 emit_insn (gen_lshrsi3 (reg2, reg, GEN_INT (16)));
5935 emit_insn (gen_movhi_bytes (reg, operands[1]));
5937 operands[1] = gen_lowpart (HImode, reg);
5941 /* Handle loading a large integer during reload. */
5942 else if (CONST_INT_P (operands[1])
5943 && !const_ok_for_arm (INTVAL (operands[1]))
5944 && !const_ok_for_arm (~INTVAL (operands[1])))
5946 /* Writing a constant to memory needs a scratch, which should
5947 be handled with SECONDARY_RELOADs. */
5948 gcc_assert (REG_P (operands[0]));
5950 operands[0] = gen_rtx_SUBREG (SImode, operands[0], 0);
5951 emit_insn (gen_movsi (operands[0], operands[1]));
5955 else if (TARGET_THUMB2)
5957 /* Thumb-2 can do everything except mem=mem and mem=const easily. */
5958 if (can_create_pseudo_p ())
5960 if (!REG_P (operands[0]))
5961 operands[1] = force_reg (HImode, operands[1]);
5962 /* Zero extend a constant, and keep it in an SImode reg. */
5963 else if (CONST_INT_P (operands[1]))
5965 rtx reg = gen_reg_rtx (SImode);
5966 HOST_WIDE_INT val = INTVAL (operands[1]) & 0xffff;
5968 emit_insn (gen_movsi (reg, GEN_INT (val)));
5969 operands[1] = gen_lowpart (HImode, reg);
5973 else /* TARGET_THUMB1 */
5975 if (can_create_pseudo_p ())
5977 if (CONST_INT_P (operands[1]))
5979 rtx reg = gen_reg_rtx (SImode);
5981 emit_insn (gen_movsi (reg, operands[1]));
5982 operands[1] = gen_lowpart (HImode, reg);
5985 /* ??? We shouldn't really get invalid addresses here, but this can
5986 happen if we are passed a SP (never OK for HImode/QImode) or
5987 virtual register (also rejected as illegitimate for HImode/QImode)
5988 relative address. */
5989 /* ??? This should perhaps be fixed elsewhere, for instance, in
5990 fixup_stack_1, by checking for other kinds of invalid addresses,
5991 e.g. a bare reference to a virtual register. This may confuse the
5992 alpha though, which must handle this case differently. */
5993 if (MEM_P (operands[0])
5994 && !memory_address_p (GET_MODE (operands[0]),
5995 XEXP (operands[0], 0)))
5997 = replace_equiv_address (operands[0],
5998 copy_to_reg (XEXP (operands[0], 0)));
6000 if (MEM_P (operands[1])
6001 && !memory_address_p (GET_MODE (operands[1]),
6002 XEXP (operands[1], 0)))
6004 = replace_equiv_address (operands[1],
6005 copy_to_reg (XEXP (operands[1], 0)));
6007 if (MEM_P (operands[1]) && optimize > 0)
6009 rtx reg = gen_reg_rtx (SImode);
6011 emit_insn (gen_zero_extendhisi2 (reg, operands[1]));
6012 operands[1] = gen_lowpart (HImode, reg);
6015 if (MEM_P (operands[0]))
6016 operands[1] = force_reg (HImode, operands[1]);
6018 else if (CONST_INT_P (operands[1])
6019 && !satisfies_constraint_I (operands[1]))
6021 /* Handle loading a large integer during reload. */
6023 /* Writing a constant to memory needs a scratch, which should
6024 be handled with SECONDARY_RELOADs. */
6025 gcc_assert (REG_P (operands[0]));
6027 operands[0] = gen_rtx_SUBREG (SImode, operands[0], 0);
6028 emit_insn (gen_movsi (operands[0], operands[1]));
6035 (define_expand "movhi_bytes"
6036 [(set (match_dup 2) (zero_extend:SI (match_operand:HI 1 "" "")))
6038 (zero_extend:SI (match_dup 6)))
6039 (set (match_operand:SI 0 "" "")
6040 (ior:SI (ashift:SI (match_dup 4) (const_int 8)) (match_dup 5)))]
6045 rtx addr = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
6047 mem1 = change_address (operands[1], QImode, addr);
6048 mem2 = change_address (operands[1], QImode,
6049 plus_constant (Pmode, addr, 1));
6050 operands[0] = gen_lowpart (SImode, operands[0]);
6052 operands[2] = gen_reg_rtx (SImode);
6053 operands[3] = gen_reg_rtx (SImode);
6056 if (BYTES_BIG_ENDIAN)
6058 operands[4] = operands[2];
6059 operands[5] = operands[3];
6063 operands[4] = operands[3];
6064 operands[5] = operands[2];
6069 (define_expand "movhi_bigend"
6071 (rotate:SI (subreg:SI (match_operand:HI 1 "memory_operand") 0)
6074 (ashiftrt:SI (match_dup 2) (const_int 16)))
6075 (set (match_operand:HI 0 "s_register_operand")
6079 operands[2] = gen_reg_rtx (SImode);
6080 operands[3] = gen_reg_rtx (SImode);
6081 operands[4] = gen_lowpart (HImode, operands[3]);
6085 ;; Pattern to recognize insn generated default case above
6086 (define_insn "*movhi_insn_arch4"
6087 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m,r")
6088 (match_operand:HI 1 "general_operand" "rIk,K,n,r,mi"))]
6090 && arm_arch4 && !TARGET_HARD_FLOAT
6091 && (register_operand (operands[0], HImode)
6092 || register_operand (operands[1], HImode))"
6094 mov%?\\t%0, %1\\t%@ movhi
6095 mvn%?\\t%0, #%B1\\t%@ movhi
6096 movw%?\\t%0, %L1\\t%@ movhi
6097 strh%?\\t%1, %0\\t%@ movhi
6098 ldrh%?\\t%0, %1\\t%@ movhi"
6099 [(set_attr "predicable" "yes")
6100 (set_attr "pool_range" "*,*,*,*,256")
6101 (set_attr "neg_pool_range" "*,*,*,*,244")
6102 (set_attr "arch" "*,*,v6t2,*,*")
6103 (set_attr_alternative "type"
6104 [(if_then_else (match_operand 1 "const_int_operand" "")
6105 (const_string "mov_imm" )
6106 (const_string "mov_reg"))
6107 (const_string "mvn_imm")
6108 (const_string "mov_imm")
6109 (const_string "store_4")
6110 (const_string "load_4")])]
6113 (define_insn "*movhi_bytes"
6114 [(set (match_operand:HI 0 "s_register_operand" "=r,r,r")
6115 (match_operand:HI 1 "arm_rhs_operand" "I,rk,K"))]
6116 "TARGET_ARM && !TARGET_HARD_FLOAT"
6118 mov%?\\t%0, %1\\t%@ movhi
6119 mov%?\\t%0, %1\\t%@ movhi
6120 mvn%?\\t%0, #%B1\\t%@ movhi"
6121 [(set_attr "predicable" "yes")
6122 (set_attr "type" "mov_imm,mov_reg,mvn_imm")]
6125 ;; We use a DImode scratch because we may occasionally need an additional
6126 ;; temporary if the address isn't offsettable -- push_reload doesn't seem
6127 ;; to take any notice of the "o" constraints on reload_memory_operand operand.
6128 ;; The reload_in<m> and reload_out<m> patterns require special constraints
6129 ;; to be correctly handled in default_secondary_reload function.
6130 (define_expand "reload_outhi"
6131 [(parallel [(match_operand:HI 0 "arm_reload_memory_operand" "=o")
6132 (match_operand:HI 1 "s_register_operand" "r")
6133 (match_operand:DI 2 "s_register_operand" "=&l")])]
6136 arm_reload_out_hi (operands);
6138 thumb_reload_out_hi (operands);
6143 (define_expand "reload_inhi"
6144 [(parallel [(match_operand:HI 0 "s_register_operand" "=r")
6145 (match_operand:HI 1 "arm_reload_memory_operand" "o")
6146 (match_operand:DI 2 "s_register_operand" "=&r")])]
6150 arm_reload_in_hi (operands);
6152 thumb_reload_out_hi (operands);
6156 (define_expand "movqi"
6157 [(set (match_operand:QI 0 "general_operand")
6158 (match_operand:QI 1 "general_operand"))]
6161 /* Everything except mem = const or mem = mem can be done easily */
6163 if (can_create_pseudo_p ())
6165 if (CONST_INT_P (operands[1]))
6167 rtx reg = gen_reg_rtx (SImode);
6169 /* For thumb we want an unsigned immediate, then we are more likely
6170 to be able to use a movs insn. */
6172 operands[1] = GEN_INT (INTVAL (operands[1]) & 255);
6174 emit_insn (gen_movsi (reg, operands[1]));
6175 operands[1] = gen_lowpart (QImode, reg);
6180 /* ??? We shouldn't really get invalid addresses here, but this can
6181 happen if we are passed a SP (never OK for HImode/QImode) or
6182 virtual register (also rejected as illegitimate for HImode/QImode)
6183 relative address. */
6184 /* ??? This should perhaps be fixed elsewhere, for instance, in
6185 fixup_stack_1, by checking for other kinds of invalid addresses,
6186 e.g. a bare reference to a virtual register. This may confuse the
6187 alpha though, which must handle this case differently. */
6188 if (MEM_P (operands[0])
6189 && !memory_address_p (GET_MODE (operands[0]),
6190 XEXP (operands[0], 0)))
6192 = replace_equiv_address (operands[0],
6193 copy_to_reg (XEXP (operands[0], 0)));
6194 if (MEM_P (operands[1])
6195 && !memory_address_p (GET_MODE (operands[1]),
6196 XEXP (operands[1], 0)))
6198 = replace_equiv_address (operands[1],
6199 copy_to_reg (XEXP (operands[1], 0)));
6202 if (MEM_P (operands[1]) && optimize > 0)
6204 rtx reg = gen_reg_rtx (SImode);
6206 emit_insn (gen_zero_extendqisi2 (reg, operands[1]));
6207 operands[1] = gen_lowpart (QImode, reg);
6210 if (MEM_P (operands[0]))
6211 operands[1] = force_reg (QImode, operands[1]);
6213 else if (TARGET_THUMB
6214 && CONST_INT_P (operands[1])
6215 && !satisfies_constraint_I (operands[1]))
6217 /* Handle loading a large integer during reload. */
6219 /* Writing a constant to memory needs a scratch, which should
6220 be handled with SECONDARY_RELOADs. */
6221 gcc_assert (REG_P (operands[0]));
6223 operands[0] = gen_rtx_SUBREG (SImode, operands[0], 0);
6224 emit_insn (gen_movsi (operands[0], operands[1]));
6230 (define_insn "*arm_movqi_insn"
6231 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,l,r,l,Uu,r,m")
6232 (match_operand:QI 1 "general_operand" "rk,rk,I,Py,K,Uu,l,Uh,r"))]
6234 && ( register_operand (operands[0], QImode)
6235 || register_operand (operands[1], QImode))"
6246 [(set_attr "type" "mov_reg,mov_reg,mov_imm,mov_imm,mvn_imm,load_4,store_4,load_4,store_4")
6247 (set_attr "predicable" "yes")
6248 (set_attr "predicable_short_it" "yes,yes,no,yes,no,no,no,no,no")
6249 (set_attr "arch" "t2,any,any,t2,any,t2,t2,any,any")
6250 (set_attr "length" "2,4,4,2,4,2,2,4,4")]
6254 (define_expand "movhf"
6255 [(set (match_operand:HF 0 "general_operand")
6256 (match_operand:HF 1 "general_operand"))]
6259 gcc_checking_assert (aligned_operand (operands[0], HFmode));
6260 gcc_checking_assert (aligned_operand (operands[1], HFmode));
6263 if (MEM_P (operands[0]))
6264 operands[1] = force_reg (HFmode, operands[1]);
6266 else /* TARGET_THUMB1 */
6268 if (can_create_pseudo_p ())
6270 if (!REG_P (operands[0]))
6271 operands[1] = force_reg (HFmode, operands[1]);
6277 (define_insn "*arm32_movhf"
6278 [(set (match_operand:HF 0 "nonimmediate_operand" "=r,m,r,r")
6279 (match_operand:HF 1 "general_operand" " m,r,r,F"))]
6280 "TARGET_32BIT && !TARGET_HARD_FLOAT
6281 && ( s_register_operand (operands[0], HFmode)
6282 || s_register_operand (operands[1], HFmode))"
6284 switch (which_alternative)
6286 case 0: /* ARM register from memory */
6287 return \"ldrh%?\\t%0, %1\\t%@ __fp16\";
6288 case 1: /* memory from ARM register */
6289 return \"strh%?\\t%1, %0\\t%@ __fp16\";
6290 case 2: /* ARM register from ARM register */
6291 return \"mov%?\\t%0, %1\\t%@ __fp16\";
6292 case 3: /* ARM register from constant */
6297 bits = real_to_target (NULL, CONST_DOUBLE_REAL_VALUE (operands[1]),
6299 ops[0] = operands[0];
6300 ops[1] = GEN_INT (bits);
6301 ops[2] = GEN_INT (bits & 0xff00);
6302 ops[3] = GEN_INT (bits & 0x00ff);
6304 if (arm_arch_thumb2)
6305 output_asm_insn (\"movw%?\\t%0, %1\", ops);
6307 output_asm_insn (\"mov%?\\t%0, %2\;orr%?\\t%0, %0, %3\", ops);
6314 [(set_attr "conds" "unconditional")
6315 (set_attr "type" "load_4,store_4,mov_reg,multiple")
6316 (set_attr "length" "4,4,4,8")
6317 (set_attr "predicable" "yes")]
6320 (define_expand "movsf"
6321 [(set (match_operand:SF 0 "general_operand")
6322 (match_operand:SF 1 "general_operand"))]
6325 gcc_checking_assert (aligned_operand (operands[0], SFmode));
6326 gcc_checking_assert (aligned_operand (operands[1], SFmode));
6329 if (MEM_P (operands[0]))
6330 operands[1] = force_reg (SFmode, operands[1]);
6332 else /* TARGET_THUMB1 */
6334 if (can_create_pseudo_p ())
6336 if (!REG_P (operands[0]))
6337 operands[1] = force_reg (SFmode, operands[1]);
6341 /* Cannot load it directly, generate a load with clobber so that it can be
6342 loaded via GPR with MOV / MOVT. */
6343 if (arm_disable_literal_pool
6344 && (REG_P (operands[0]) || SUBREG_P (operands[0]))
6345 && CONST_DOUBLE_P (operands[1])
6346 && TARGET_HARD_FLOAT
6347 && !vfp3_const_double_rtx (operands[1]))
6349 rtx clobreg = gen_reg_rtx (SFmode);
6350 emit_insn (gen_no_literal_pool_sf_immediate (operands[0], operands[1],
6357 ;; Transform a floating-point move of a constant into a core register into
6358 ;; an SImode operation.
6360 [(set (match_operand:SF 0 "arm_general_register_operand" "")
6361 (match_operand:SF 1 "immediate_operand" ""))]
6364 && CONST_DOUBLE_P (operands[1])"
6365 [(set (match_dup 2) (match_dup 3))]
6367 operands[2] = gen_lowpart (SImode, operands[0]);
6368 operands[3] = gen_lowpart (SImode, operands[1]);
6369 if (operands[2] == 0 || operands[3] == 0)
6374 (define_insn "*arm_movsf_soft_insn"
6375 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
6376 (match_operand:SF 1 "general_operand" "r,mE,r"))]
6378 && TARGET_SOFT_FLOAT
6379 && (!MEM_P (operands[0])
6380 || register_operand (operands[1], SFmode))"
6382 switch (which_alternative)
6384 case 0: return \"mov%?\\t%0, %1\";
6386 /* Cannot load it directly, split to load it via MOV / MOVT. */
6387 if (!MEM_P (operands[1]) && arm_disable_literal_pool)
6389 return \"ldr%?\\t%0, %1\\t%@ float\";
6390 case 2: return \"str%?\\t%1, %0\\t%@ float\";
6391 default: gcc_unreachable ();
6394 [(set_attr "predicable" "yes")
6395 (set_attr "type" "mov_reg,load_4,store_4")
6396 (set_attr "arm_pool_range" "*,4096,*")
6397 (set_attr "thumb2_pool_range" "*,4094,*")
6398 (set_attr "arm_neg_pool_range" "*,4084,*")
6399 (set_attr "thumb2_neg_pool_range" "*,0,*")]
6402 ;; Splitter for the above.
6404 [(set (match_operand:SF 0 "s_register_operand")
6405 (match_operand:SF 1 "const_double_operand"))]
6406 "arm_disable_literal_pool && TARGET_SOFT_FLOAT"
6410 real_to_target (&buf, CONST_DOUBLE_REAL_VALUE (operands[1]), SFmode);
6411 rtx cst = gen_int_mode (buf, SImode);
6412 emit_move_insn (simplify_gen_subreg (SImode, operands[0], SFmode, 0), cst);
6417 (define_expand "movdf"
6418 [(set (match_operand:DF 0 "general_operand")
6419 (match_operand:DF 1 "general_operand"))]
6422 gcc_checking_assert (aligned_operand (operands[0], DFmode));
6423 gcc_checking_assert (aligned_operand (operands[1], DFmode));
6426 if (MEM_P (operands[0]))
6427 operands[1] = force_reg (DFmode, operands[1]);
6429 else /* TARGET_THUMB */
6431 if (can_create_pseudo_p ())
6433 if (!REG_P (operands[0]))
6434 operands[1] = force_reg (DFmode, operands[1]);
6438 /* Cannot load it directly, generate a load with clobber so that it can be
6439 loaded via GPR with MOV / MOVT. */
6440 if (arm_disable_literal_pool
6441 && (REG_P (operands[0]) || SUBREG_P (operands[0]))
6442 && CONSTANT_P (operands[1])
6443 && TARGET_HARD_FLOAT
6444 && !arm_const_double_rtx (operands[1])
6445 && !(TARGET_VFP_DOUBLE && vfp3_const_double_rtx (operands[1])))
6447 rtx clobreg = gen_reg_rtx (DFmode);
6448 emit_insn (gen_no_literal_pool_df_immediate (operands[0], operands[1],
6455 ;; Reloading a df mode value stored in integer regs to memory can require a
6457 ;; Another reload_out<m> pattern that requires special constraints.
6458 (define_expand "reload_outdf"
6459 [(match_operand:DF 0 "arm_reload_memory_operand" "=o")
6460 (match_operand:DF 1 "s_register_operand" "r")
6461 (match_operand:SI 2 "s_register_operand" "=&r")]
6465 enum rtx_code code = GET_CODE (XEXP (operands[0], 0));
6468 operands[2] = XEXP (operands[0], 0);
6469 else if (code == POST_INC || code == PRE_DEC)
6471 operands[0] = gen_rtx_SUBREG (DImode, operands[0], 0);
6472 operands[1] = gen_rtx_SUBREG (DImode, operands[1], 0);
6473 emit_insn (gen_movdi (operands[0], operands[1]));
6476 else if (code == PRE_INC)
6478 rtx reg = XEXP (XEXP (operands[0], 0), 0);
6480 emit_insn (gen_addsi3 (reg, reg, GEN_INT (8)));
6483 else if (code == POST_DEC)
6484 operands[2] = XEXP (XEXP (operands[0], 0), 0);
6486 emit_insn (gen_addsi3 (operands[2], XEXP (XEXP (operands[0], 0), 0),
6487 XEXP (XEXP (operands[0], 0), 1)));
6489 emit_insn (gen_rtx_SET (replace_equiv_address (operands[0], operands[2]),
6492 if (code == POST_DEC)
6493 emit_insn (gen_addsi3 (operands[2], operands[2], GEN_INT (-8)));
6499 (define_insn "*movdf_soft_insn"
6500 [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=r,r,r,r,m")
6501 (match_operand:DF 1 "soft_df_operand" "rDa,Db,Dc,mF,r"))]
6502 "TARGET_32BIT && TARGET_SOFT_FLOAT
6503 && ( register_operand (operands[0], DFmode)
6504 || register_operand (operands[1], DFmode))"
6506 switch (which_alternative)
6513 /* Cannot load it directly, split to load it via MOV / MOVT. */
6514 if (!MEM_P (operands[1]) && arm_disable_literal_pool)
6518 return output_move_double (operands, true, NULL);
6521 [(set_attr "length" "8,12,16,8,8")
6522 (set_attr "type" "multiple,multiple,multiple,load_8,store_8")
6523 (set_attr "arm_pool_range" "*,*,*,1020,*")
6524 (set_attr "thumb2_pool_range" "*,*,*,1018,*")
6525 (set_attr "arm_neg_pool_range" "*,*,*,1004,*")
6526 (set_attr "thumb2_neg_pool_range" "*,*,*,0,*")]
6529 ;; Splitter for the above.
6531 [(set (match_operand:DF 0 "s_register_operand")
6532 (match_operand:DF 1 "const_double_operand"))]
6533 "arm_disable_literal_pool && TARGET_SOFT_FLOAT"
6537 int order = BYTES_BIG_ENDIAN ? 1 : 0;
6538 real_to_target (buf, CONST_DOUBLE_REAL_VALUE (operands[1]), DFmode);
6539 unsigned HOST_WIDE_INT ival = zext_hwi (buf[order], 32);
6540 ival |= (zext_hwi (buf[1 - order], 32) << 32);
6541 rtx cst = gen_int_mode (ival, DImode);
6542 emit_move_insn (simplify_gen_subreg (DImode, operands[0], DFmode, 0), cst);
6548 ;; load- and store-multiple insns
6549 ;; The arm can load/store any set of registers, provided that they are in
6550 ;; ascending order, but these expanders assume a contiguous set.
6552 (define_expand "load_multiple"
6553 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
6554 (match_operand:SI 1 "" ""))
6555 (use (match_operand:SI 2 "" ""))])]
6558 HOST_WIDE_INT offset = 0;
6560 /* Support only fixed point registers. */
6561 if (!CONST_INT_P (operands[2])
6562 || INTVAL (operands[2]) > MAX_LDM_STM_OPS
6563 || INTVAL (operands[2]) < 2
6564 || !MEM_P (operands[1])
6565 || !REG_P (operands[0])
6566 || REGNO (operands[0]) > (LAST_ARM_REGNUM - 1)
6567 || REGNO (operands[0]) + INTVAL (operands[2]) > LAST_ARM_REGNUM)
6571 = arm_gen_load_multiple (arm_regs_in_sequence + REGNO (operands[0]),
6572 INTVAL (operands[2]),
6573 force_reg (SImode, XEXP (operands[1], 0)),
6574 FALSE, operands[1], &offset);
6577 (define_expand "store_multiple"
6578 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
6579 (match_operand:SI 1 "" ""))
6580 (use (match_operand:SI 2 "" ""))])]
6583 HOST_WIDE_INT offset = 0;
6585 /* Support only fixed point registers. */
6586 if (!CONST_INT_P (operands[2])
6587 || INTVAL (operands[2]) > MAX_LDM_STM_OPS
6588 || INTVAL (operands[2]) < 2
6589 || !REG_P (operands[1])
6590 || !MEM_P (operands[0])
6591 || REGNO (operands[1]) > (LAST_ARM_REGNUM - 1)
6592 || REGNO (operands[1]) + INTVAL (operands[2]) > LAST_ARM_REGNUM)
6596 = arm_gen_store_multiple (arm_regs_in_sequence + REGNO (operands[1]),
6597 INTVAL (operands[2]),
6598 force_reg (SImode, XEXP (operands[0], 0)),
6599 FALSE, operands[0], &offset);
6603 (define_expand "setmemsi"
6604 [(match_operand:BLK 0 "general_operand")
6605 (match_operand:SI 1 "const_int_operand")
6606 (match_operand:SI 2 "const_int_operand")
6607 (match_operand:SI 3 "const_int_operand")]
6610 if (arm_gen_setmem (operands))
6617 ;; Move a block of memory if it is word aligned and MORE than 2 words long.
6618 ;; We could let this apply for blocks of less than this, but it clobbers so
6619 ;; many registers that there is then probably a better way.
6621 (define_expand "cpymemqi"
6622 [(match_operand:BLK 0 "general_operand")
6623 (match_operand:BLK 1 "general_operand")
6624 (match_operand:SI 2 "const_int_operand")
6625 (match_operand:SI 3 "const_int_operand")]
6630 if (TARGET_LDRD && current_tune->prefer_ldrd_strd
6631 && !optimize_function_for_size_p (cfun))
6633 if (gen_cpymem_ldrd_strd (operands))
6638 if (arm_gen_cpymemqi (operands))
6642 else /* TARGET_THUMB1 */
6644 if ( INTVAL (operands[3]) != 4
6645 || INTVAL (operands[2]) > 48)
6648 thumb_expand_cpymemqi (operands);
6655 ;; Compare & branch insns
6656 ;; The range calculations are based as follows:
6657 ;; For forward branches, the address calculation returns the address of
6658 ;; the next instruction. This is 2 beyond the branch instruction.
6659 ;; For backward branches, the address calculation returns the address of
6660 ;; the first instruction in this pattern (cmp). This is 2 before the branch
6661 ;; instruction for the shortest sequence, and 4 before the branch instruction
6662 ;; if we have to jump around an unconditional branch.
6663 ;; To the basic branch range the PC offset must be added (this is +4).
6664 ;; So for forward branches we have
6665 ;; (pos_range - pos_base_offs + pc_offs) = (pos_range - 2 + 4).
6666 ;; And for backward branches we have
6667 ;; (neg_range - neg_base_offs + pc_offs) = (neg_range - (-2 or -4) + 4).
6669 ;; For a 'b' pos_range = 2046, neg_range = -2048 giving (-2040->2048).
6670 ;; For a 'b<cond>' pos_range = 254, neg_range = -256 giving (-250 ->256).
6672 (define_expand "cbranchsi4"
6673 [(set (pc) (if_then_else
6674 (match_operator 0 "expandable_comparison_operator"
6675 [(match_operand:SI 1 "s_register_operand")
6676 (match_operand:SI 2 "nonmemory_operand")])
6677 (label_ref (match_operand 3 "" ""))
6683 if (!arm_validize_comparison (&operands[0], &operands[1], &operands[2]))
6685 emit_jump_insn (gen_cbranch_cc (operands[0], operands[1], operands[2],
6689 if (thumb1_cmpneg_operand (operands[2], SImode))
6691 emit_jump_insn (gen_cbranchsi4_scratch (NULL, operands[1], operands[2],
6692 operands[3], operands[0]));
6695 if (!thumb1_cmp_operand (operands[2], SImode))
6696 operands[2] = force_reg (SImode, operands[2]);
6699 (define_expand "cbranchsf4"
6700 [(set (pc) (if_then_else
6701 (match_operator 0 "expandable_comparison_operator"
6702 [(match_operand:SF 1 "s_register_operand")
6703 (match_operand:SF 2 "vfp_compare_operand")])
6704 (label_ref (match_operand 3 "" ""))
6706 "TARGET_32BIT && TARGET_HARD_FLOAT"
6707 "emit_jump_insn (gen_cbranch_cc (operands[0], operands[1], operands[2],
6708 operands[3])); DONE;"
6711 (define_expand "cbranchdf4"
6712 [(set (pc) (if_then_else
6713 (match_operator 0 "expandable_comparison_operator"
6714 [(match_operand:DF 1 "s_register_operand")
6715 (match_operand:DF 2 "vfp_compare_operand")])
6716 (label_ref (match_operand 3 "" ""))
6718 "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
6719 "emit_jump_insn (gen_cbranch_cc (operands[0], operands[1], operands[2],
6720 operands[3])); DONE;"
6723 (define_expand "cbranchdi4"
6724 [(set (pc) (if_then_else
6725 (match_operator 0 "expandable_comparison_operator"
6726 [(match_operand:DI 1 "s_register_operand")
6727 (match_operand:DI 2 "cmpdi_operand")])
6728 (label_ref (match_operand 3 "" ""))
6732 if (!arm_validize_comparison (&operands[0], &operands[1], &operands[2]))
6734 emit_jump_insn (gen_cbranch_cc (operands[0], operands[1], operands[2],
6740 ;; Comparison and test insns
6742 (define_insn "*arm_cmpsi_insn"
6743 [(set (reg:CC CC_REGNUM)
6744 (compare:CC (match_operand:SI 0 "s_register_operand" "l,r,r,r,r")
6745 (match_operand:SI 1 "arm_add_operand" "Py,r,r,I,L")))]
6753 [(set_attr "conds" "set")
6754 (set_attr "arch" "t2,t2,any,any,any")
6755 (set_attr "length" "2,2,4,4,4")
6756 (set_attr "predicable" "yes")
6757 (set_attr "predicable_short_it" "yes,yes,yes,no,no")
6758 (set_attr "type" "alus_imm,alus_sreg,alus_sreg,alus_imm,alus_imm")]
6761 (define_insn "*cmpsi_shiftsi"
6762 [(set (reg:CC CC_REGNUM)
6763 (compare:CC (match_operand:SI 0 "s_register_operand" "r,r,r")
6764 (match_operator:SI 3 "shift_operator"
6765 [(match_operand:SI 1 "s_register_operand" "r,r,r")
6766 (match_operand:SI 2 "shift_amount_operand" "M,r,M")])))]
6769 [(set_attr "conds" "set")
6770 (set_attr "shift" "1")
6771 (set_attr "arch" "32,a,a")
6772 (set_attr "type" "alus_shift_imm,alus_shift_reg,alus_shift_imm")])
6774 (define_insn "*cmpsi_shiftsi_swp"
6775 [(set (reg:CC_SWP CC_REGNUM)
6776 (compare:CC_SWP (match_operator:SI 3 "shift_operator"
6777 [(match_operand:SI 1 "s_register_operand" "r,r,r")
6778 (match_operand:SI 2 "shift_amount_operand" "M,r,M")])
6779 (match_operand:SI 0 "s_register_operand" "r,r,r")))]
6782 [(set_attr "conds" "set")
6783 (set_attr "shift" "1")
6784 (set_attr "arch" "32,a,a")
6785 (set_attr "type" "alus_shift_imm,alus_shift_reg,alus_shift_imm")])
6787 (define_insn "*arm_cmpsi_negshiftsi_si"
6788 [(set (reg:CC_Z CC_REGNUM)
6790 (neg:SI (match_operator:SI 1 "shift_operator"
6791 [(match_operand:SI 2 "s_register_operand" "r")
6792 (match_operand:SI 3 "reg_or_int_operand" "rM")]))
6793 (match_operand:SI 0 "s_register_operand" "r")))]
6796 [(set_attr "conds" "set")
6797 (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "")
6798 (const_string "alus_shift_imm")
6799 (const_string "alus_shift_reg")))
6800 (set_attr "predicable" "yes")]
6803 ;; DImode comparisons. The generic code generates branches that
6804 ;; if-conversion cannot reduce to a conditional compare, so we do
6807 (define_insn_and_split "*arm_cmpdi_insn"
6808 [(set (reg:CC_NCV CC_REGNUM)
6809 (compare:CC_NCV (match_operand:DI 0 "s_register_operand" "r")
6810 (match_operand:DI 1 "arm_di_operand" "rDi")))
6811 (clobber (match_scratch:SI 2 "=r"))]
6813 "#" ; "cmp\\t%Q0, %Q1\;sbcs\\t%2, %R0, %R1"
6814 "&& reload_completed"
6815 [(set (reg:CC CC_REGNUM)
6816 (compare:CC (match_dup 0) (match_dup 1)))
6817 (parallel [(set (reg:CC CC_REGNUM)
6818 (compare:CC (match_dup 3) (match_dup 4)))
6820 (minus:SI (match_dup 5)
6821 (ltu:SI (reg:CC CC_REGNUM) (const_int 0))))])]
6823 operands[3] = gen_highpart (SImode, operands[0]);
6824 operands[0] = gen_lowpart (SImode, operands[0]);
6825 if (CONST_INT_P (operands[1]))
6827 operands[4] = gen_highpart_mode (SImode, DImode, operands[1]);
6828 if (operands[4] == const0_rtx)
6829 operands[5] = operands[3];
6831 operands[5] = gen_rtx_PLUS (SImode, operands[3],
6832 gen_int_mode (-UINTVAL (operands[4]),
6837 operands[4] = gen_highpart (SImode, operands[1]);
6838 operands[5] = gen_rtx_MINUS (SImode, operands[3], operands[4]);
6840 operands[1] = gen_lowpart (SImode, operands[1]);
6841 operands[2] = gen_lowpart (SImode, operands[2]);
6843 [(set_attr "conds" "set")
6844 (set_attr "length" "8")
6845 (set_attr "type" "multiple")]
6848 (define_insn_and_split "*arm_cmpdi_unsigned"
6849 [(set (reg:CC_CZ CC_REGNUM)
6850 (compare:CC_CZ (match_operand:DI 0 "s_register_operand" "l,r,r,r")
6851 (match_operand:DI 1 "arm_di_operand" "Py,r,Di,rDi")))]
6854 "#" ; "cmp\\t%R0, %R1\;it eq\;cmpeq\\t%Q0, %Q1"
6855 "&& reload_completed"
6856 [(set (reg:CC CC_REGNUM)
6857 (compare:CC (match_dup 2) (match_dup 3)))
6858 (cond_exec (eq:SI (reg:CC CC_REGNUM) (const_int 0))
6859 (set (reg:CC CC_REGNUM)
6860 (compare:CC (match_dup 0) (match_dup 1))))]
6862 operands[2] = gen_highpart (SImode, operands[0]);
6863 operands[0] = gen_lowpart (SImode, operands[0]);
6864 if (CONST_INT_P (operands[1]))
6865 operands[3] = gen_highpart_mode (SImode, DImode, operands[1]);
6867 operands[3] = gen_highpart (SImode, operands[1]);
6868 operands[1] = gen_lowpart (SImode, operands[1]);
6870 [(set_attr "conds" "set")
6871 (set_attr "enabled_for_short_it" "yes,yes,no,*")
6872 (set_attr "arch" "t2,t2,t2,a")
6873 (set_attr "length" "6,6,10,8")
6874 (set_attr "type" "multiple")]
6877 (define_insn "*arm_cmpdi_zero"
6878 [(set (reg:CC_Z CC_REGNUM)
6879 (compare:CC_Z (match_operand:DI 0 "s_register_operand" "r")
6881 (clobber (match_scratch:SI 1 "=r"))]
6883 "orrs%?\\t%1, %Q0, %R0"
6884 [(set_attr "conds" "set")
6885 (set_attr "type" "logics_reg")]
6888 ; This insn allows redundant compares to be removed by cse, nothing should
6889 ; ever appear in the output file since (set (reg x) (reg x)) is a no-op that
6890 ; is deleted later on. The match_dup will match the mode here, so that
6891 ; mode changes of the condition codes aren't lost by this even though we don't
6892 ; specify what they are.
6894 (define_insn "*deleted_compare"
6895 [(set (match_operand 0 "cc_register" "") (match_dup 0))]
6897 "\\t%@ deleted compare"
6898 [(set_attr "conds" "set")
6899 (set_attr "length" "0")
6900 (set_attr "type" "no_insn")]
6904 ;; Conditional branch insns
6906 (define_expand "cbranch_cc"
6908 (if_then_else (match_operator 0 "" [(match_operand 1 "" "")
6909 (match_operand 2 "" "")])
6910 (label_ref (match_operand 3 "" ""))
6913 "operands[1] = arm_gen_compare_reg (GET_CODE (operands[0]),
6914 operands[1], operands[2], NULL_RTX);
6915 operands[2] = const0_rtx;"
6919 ;; Patterns to match conditional branch insns.
6922 (define_insn "arm_cond_branch"
6924 (if_then_else (match_operator 1 "arm_comparison_operator"
6925 [(match_operand 2 "cc_register" "") (const_int 0)])
6926 (label_ref (match_operand 0 "" ""))
6930 if (arm_ccfsm_state == 1 || arm_ccfsm_state == 2)
6932 arm_ccfsm_state += 2;
6935 return \"b%d1\\t%l0\";
6937 [(set_attr "conds" "use")
6938 (set_attr "type" "branch")
6939 (set (attr "length")
6941 (and (match_test "TARGET_THUMB2")
6942 (and (ge (minus (match_dup 0) (pc)) (const_int -250))
6943 (le (minus (match_dup 0) (pc)) (const_int 256))))
6948 (define_insn "*arm_cond_branch_reversed"
6950 (if_then_else (match_operator 1 "arm_comparison_operator"
6951 [(match_operand 2 "cc_register" "") (const_int 0)])
6953 (label_ref (match_operand 0 "" ""))))]
6956 if (arm_ccfsm_state == 1 || arm_ccfsm_state == 2)
6958 arm_ccfsm_state += 2;
6961 return \"b%D1\\t%l0\";
6963 [(set_attr "conds" "use")
6964 (set_attr "type" "branch")
6965 (set (attr "length")
6967 (and (match_test "TARGET_THUMB2")
6968 (and (ge (minus (match_dup 0) (pc)) (const_int -250))
6969 (le (minus (match_dup 0) (pc)) (const_int 256))))
6978 (define_expand "cstore_cc"
6979 [(set (match_operand:SI 0 "s_register_operand")
6980 (match_operator:SI 1 "" [(match_operand 2 "" "")
6981 (match_operand 3 "" "")]))]
6983 "operands[2] = arm_gen_compare_reg (GET_CODE (operands[1]),
6984 operands[2], operands[3], NULL_RTX);
6985 operands[3] = const0_rtx;"
6988 (define_insn_and_split "*mov_scc"
6989 [(set (match_operand:SI 0 "s_register_operand" "=r")
6990 (match_operator:SI 1 "arm_comparison_operator_mode"
6991 [(match_operand 2 "cc_register" "") (const_int 0)]))]
6993 "#" ; "mov%D1\\t%0, #0\;mov%d1\\t%0, #1"
6996 (if_then_else:SI (match_dup 1)
7000 [(set_attr "conds" "use")
7001 (set_attr "length" "8")
7002 (set_attr "type" "multiple")]
7005 (define_insn_and_split "*mov_negscc"
7006 [(set (match_operand:SI 0 "s_register_operand" "=r")
7007 (neg:SI (match_operator:SI 1 "arm_comparison_operator_mode"
7008 [(match_operand 2 "cc_register" "") (const_int 0)])))]
7010 "#" ; "mov%D1\\t%0, #0\;mvn%d1\\t%0, #0"
7013 (if_then_else:SI (match_dup 1)
7017 operands[3] = GEN_INT (~0);
7019 [(set_attr "conds" "use")
7020 (set_attr "length" "8")
7021 (set_attr "type" "multiple")]
7024 (define_insn_and_split "*mov_notscc"
7025 [(set (match_operand:SI 0 "s_register_operand" "=r")
7026 (not:SI (match_operator:SI 1 "arm_comparison_operator"
7027 [(match_operand 2 "cc_register" "") (const_int 0)])))]
7029 "#" ; "mvn%D1\\t%0, #0\;mvn%d1\\t%0, #1"
7032 (if_then_else:SI (match_dup 1)
7036 operands[3] = GEN_INT (~1);
7037 operands[4] = GEN_INT (~0);
7039 [(set_attr "conds" "use")
7040 (set_attr "length" "8")
7041 (set_attr "type" "multiple")]
7044 (define_expand "cstoresi4"
7045 [(set (match_operand:SI 0 "s_register_operand")
7046 (match_operator:SI 1 "expandable_comparison_operator"
7047 [(match_operand:SI 2 "s_register_operand")
7048 (match_operand:SI 3 "reg_or_int_operand")]))]
7049 "TARGET_32BIT || TARGET_THUMB1"
7051 rtx op3, scratch, scratch2;
7055 if (!arm_add_operand (operands[3], SImode))
7056 operands[3] = force_reg (SImode, operands[3]);
7057 emit_insn (gen_cstore_cc (operands[0], operands[1],
7058 operands[2], operands[3]));
7062 if (operands[3] == const0_rtx)
7064 switch (GET_CODE (operands[1]))
7067 emit_insn (gen_cstoresi_eq0_thumb1 (operands[0], operands[2]));
7071 emit_insn (gen_cstoresi_ne0_thumb1 (operands[0], operands[2]));
7075 scratch = expand_binop (SImode, add_optab, operands[2], constm1_rtx,
7076 NULL_RTX, 0, OPTAB_WIDEN);
7077 scratch = expand_binop (SImode, ior_optab, operands[2], scratch,
7078 NULL_RTX, 0, OPTAB_WIDEN);
7079 expand_binop (SImode, lshr_optab, scratch, GEN_INT (31),
7080 operands[0], 1, OPTAB_WIDEN);
7084 scratch = expand_unop (SImode, one_cmpl_optab, operands[2],
7086 expand_binop (SImode, lshr_optab, scratch, GEN_INT (31),
7087 NULL_RTX, 1, OPTAB_WIDEN);
7091 scratch = expand_binop (SImode, ashr_optab, operands[2],
7092 GEN_INT (31), NULL_RTX, 0, OPTAB_WIDEN);
7093 scratch = expand_binop (SImode, sub_optab, scratch, operands[2],
7094 NULL_RTX, 0, OPTAB_WIDEN);
7095 expand_binop (SImode, lshr_optab, scratch, GEN_INT (31), operands[0],
7099 /* LT is handled by generic code. No need for unsigned with 0. */
7106 switch (GET_CODE (operands[1]))
7109 scratch = expand_binop (SImode, sub_optab, operands[2], operands[3],
7110 NULL_RTX, 0, OPTAB_WIDEN);
7111 emit_insn (gen_cstoresi_eq0_thumb1 (operands[0], scratch));
7115 scratch = expand_binop (SImode, sub_optab, operands[2], operands[3],
7116 NULL_RTX, 0, OPTAB_WIDEN);
7117 emit_insn (gen_cstoresi_ne0_thumb1 (operands[0], scratch));
7121 op3 = force_reg (SImode, operands[3]);
7123 scratch = expand_binop (SImode, lshr_optab, operands[2], GEN_INT (31),
7124 NULL_RTX, 1, OPTAB_WIDEN);
7125 scratch2 = expand_binop (SImode, ashr_optab, op3, GEN_INT (31),
7126 NULL_RTX, 0, OPTAB_WIDEN);
7127 emit_insn (gen_thumb1_addsi3_addgeu (operands[0], scratch, scratch2,
7133 if (!thumb1_cmp_operand (op3, SImode))
7134 op3 = force_reg (SImode, op3);
7135 scratch = expand_binop (SImode, ashr_optab, operands[2], GEN_INT (31),
7136 NULL_RTX, 0, OPTAB_WIDEN);
7137 scratch2 = expand_binop (SImode, lshr_optab, op3, GEN_INT (31),
7138 NULL_RTX, 1, OPTAB_WIDEN);
7139 emit_insn (gen_thumb1_addsi3_addgeu (operands[0], scratch, scratch2,
7144 op3 = force_reg (SImode, operands[3]);
7145 scratch = force_reg (SImode, const0_rtx);
7146 emit_insn (gen_thumb1_addsi3_addgeu (operands[0], scratch, scratch,
7152 if (!thumb1_cmp_operand (op3, SImode))
7153 op3 = force_reg (SImode, op3);
7154 scratch = force_reg (SImode, const0_rtx);
7155 emit_insn (gen_thumb1_addsi3_addgeu (operands[0], scratch, scratch,
7161 if (!thumb1_cmp_operand (op3, SImode))
7162 op3 = force_reg (SImode, op3);
7163 scratch = gen_reg_rtx (SImode);
7164 emit_insn (gen_cstoresi_ltu_thumb1 (operands[0], operands[2], op3));
7168 op3 = force_reg (SImode, operands[3]);
7169 scratch = gen_reg_rtx (SImode);
7170 emit_insn (gen_cstoresi_ltu_thumb1 (operands[0], op3, operands[2]));
7173 /* No good sequences for GT, LT. */
7180 (define_expand "cstorehf4"
7181 [(set (match_operand:SI 0 "s_register_operand")
7182 (match_operator:SI 1 "expandable_comparison_operator"
7183 [(match_operand:HF 2 "s_register_operand")
7184 (match_operand:HF 3 "vfp_compare_operand")]))]
7185 "TARGET_VFP_FP16INST"
7187 if (!arm_validize_comparison (&operands[1],
7192 emit_insn (gen_cstore_cc (operands[0], operands[1],
7193 operands[2], operands[3]));
7198 (define_expand "cstoresf4"
7199 [(set (match_operand:SI 0 "s_register_operand")
7200 (match_operator:SI 1 "expandable_comparison_operator"
7201 [(match_operand:SF 2 "s_register_operand")
7202 (match_operand:SF 3 "vfp_compare_operand")]))]
7203 "TARGET_32BIT && TARGET_HARD_FLOAT"
7204 "emit_insn (gen_cstore_cc (operands[0], operands[1],
7205 operands[2], operands[3])); DONE;"
7208 (define_expand "cstoredf4"
7209 [(set (match_operand:SI 0 "s_register_operand")
7210 (match_operator:SI 1 "expandable_comparison_operator"
7211 [(match_operand:DF 2 "s_register_operand")
7212 (match_operand:DF 3 "vfp_compare_operand")]))]
7213 "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
7214 "emit_insn (gen_cstore_cc (operands[0], operands[1],
7215 operands[2], operands[3])); DONE;"
7218 (define_expand "cstoredi4"
7219 [(set (match_operand:SI 0 "s_register_operand")
7220 (match_operator:SI 1 "expandable_comparison_operator"
7221 [(match_operand:DI 2 "s_register_operand")
7222 (match_operand:DI 3 "cmpdi_operand")]))]
7225 if (!arm_validize_comparison (&operands[1],
7229 emit_insn (gen_cstore_cc (operands[0], operands[1], operands[2],
7236 ;; Conditional move insns
7238 (define_expand "movsicc"
7239 [(set (match_operand:SI 0 "s_register_operand")
7240 (if_then_else:SI (match_operand 1 "expandable_comparison_operator")
7241 (match_operand:SI 2 "arm_not_operand")
7242 (match_operand:SI 3 "arm_not_operand")))]
7249 if (!arm_validize_comparison (&operands[1], &XEXP (operands[1], 0),
7250 &XEXP (operands[1], 1)))
7253 code = GET_CODE (operands[1]);
7254 ccreg = arm_gen_compare_reg (code, XEXP (operands[1], 0),
7255 XEXP (operands[1], 1), NULL_RTX);
7256 operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
7260 (define_expand "movhfcc"
7261 [(set (match_operand:HF 0 "s_register_operand")
7262 (if_then_else:HF (match_operand 1 "arm_cond_move_operator")
7263 (match_operand:HF 2 "s_register_operand")
7264 (match_operand:HF 3 "s_register_operand")))]
7265 "TARGET_VFP_FP16INST"
7268 enum rtx_code code = GET_CODE (operands[1]);
7271 if (!arm_validize_comparison (&operands[1], &XEXP (operands[1], 0),
7272 &XEXP (operands[1], 1)))
7275 code = GET_CODE (operands[1]);
7276 ccreg = arm_gen_compare_reg (code, XEXP (operands[1], 0),
7277 XEXP (operands[1], 1), NULL_RTX);
7278 operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
7282 (define_expand "movsfcc"
7283 [(set (match_operand:SF 0 "s_register_operand")
7284 (if_then_else:SF (match_operand 1 "arm_cond_move_operator")
7285 (match_operand:SF 2 "s_register_operand")
7286 (match_operand:SF 3 "s_register_operand")))]
7287 "TARGET_32BIT && TARGET_HARD_FLOAT"
7290 enum rtx_code code = GET_CODE (operands[1]);
7293 if (!arm_validize_comparison (&operands[1], &XEXP (operands[1], 0),
7294 &XEXP (operands[1], 1)))
7297 code = GET_CODE (operands[1]);
7298 ccreg = arm_gen_compare_reg (code, XEXP (operands[1], 0),
7299 XEXP (operands[1], 1), NULL_RTX);
7300 operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
7304 (define_expand "movdfcc"
7305 [(set (match_operand:DF 0 "s_register_operand")
7306 (if_then_else:DF (match_operand 1 "arm_cond_move_operator")
7307 (match_operand:DF 2 "s_register_operand")
7308 (match_operand:DF 3 "s_register_operand")))]
7309 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
7312 enum rtx_code code = GET_CODE (operands[1]);
7315 if (!arm_validize_comparison (&operands[1], &XEXP (operands[1], 0),
7316 &XEXP (operands[1], 1)))
7318 code = GET_CODE (operands[1]);
7319 ccreg = arm_gen_compare_reg (code, XEXP (operands[1], 0),
7320 XEXP (operands[1], 1), NULL_RTX);
7321 operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
7325 (define_insn "*cmov<mode>"
7326 [(set (match_operand:SDF 0 "s_register_operand" "=<F_constraint>")
7327 (if_then_else:SDF (match_operator 1 "arm_vsel_comparison_operator"
7328 [(match_operand 2 "cc_register" "") (const_int 0)])
7329 (match_operand:SDF 3 "s_register_operand"
7331 (match_operand:SDF 4 "s_register_operand"
7332 "<F_constraint>")))]
7333 "TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>"
7336 enum arm_cond_code code = maybe_get_arm_condition_code (operands[1]);
7343 return \"vsel%d1.<V_if_elem>\\t%<V_reg>0, %<V_reg>3, %<V_reg>4\";
7348 return \"vsel%D1.<V_if_elem>\\t%<V_reg>0, %<V_reg>4, %<V_reg>3\";
7354 [(set_attr "conds" "use")
7355 (set_attr "type" "fcsel")]
7358 (define_insn "*cmovhf"
7359 [(set (match_operand:HF 0 "s_register_operand" "=t")
7360 (if_then_else:HF (match_operator 1 "arm_vsel_comparison_operator"
7361 [(match_operand 2 "cc_register" "") (const_int 0)])
7362 (match_operand:HF 3 "s_register_operand" "t")
7363 (match_operand:HF 4 "s_register_operand" "t")))]
7364 "TARGET_VFP_FP16INST"
7367 enum arm_cond_code code = maybe_get_arm_condition_code (operands[1]);
7374 return \"vsel%d1.f16\\t%0, %3, %4\";
7379 return \"vsel%D1.f16\\t%0, %4, %3\";
7385 [(set_attr "conds" "use")
7386 (set_attr "type" "fcsel")]
7389 (define_insn_and_split "*movsicc_insn"
7390 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r,r,r,r,r")
7392 (match_operator 3 "arm_comparison_operator"
7393 [(match_operand 4 "cc_register" "") (const_int 0)])
7394 (match_operand:SI 1 "arm_not_operand" "0,0,rI,K,rI,rI,K,K")
7395 (match_operand:SI 2 "arm_not_operand" "rI,K,0,0,rI,K,rI,K")))]
7406 ; alt4: mov%d3\\t%0, %1\;mov%D3\\t%0, %2
7407 ; alt5: mov%d3\\t%0, %1\;mvn%D3\\t%0, #%B2
7408 ; alt6: mvn%d3\\t%0, #%B1\;mov%D3\\t%0, %2
7409 ; alt7: mvn%d3\\t%0, #%B1\;mvn%D3\\t%0, #%B2"
7410 "&& reload_completed"
7413 enum rtx_code rev_code;
7417 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
7419 gen_rtx_SET (operands[0], operands[1])));
7421 rev_code = GET_CODE (operands[3]);
7422 mode = GET_MODE (operands[4]);
7423 if (mode == CCFPmode || mode == CCFPEmode)
7424 rev_code = reverse_condition_maybe_unordered (rev_code);
7426 rev_code = reverse_condition (rev_code);
7428 rev_cond = gen_rtx_fmt_ee (rev_code,
7432 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
7434 gen_rtx_SET (operands[0], operands[2])));
7437 [(set_attr "length" "4,4,4,4,8,8,8,8")
7438 (set_attr "conds" "use")
7439 (set_attr_alternative "type"
7440 [(if_then_else (match_operand 2 "const_int_operand" "")
7441 (const_string "mov_imm")
7442 (const_string "mov_reg"))
7443 (const_string "mvn_imm")
7444 (if_then_else (match_operand 1 "const_int_operand" "")
7445 (const_string "mov_imm")
7446 (const_string "mov_reg"))
7447 (const_string "mvn_imm")
7448 (const_string "multiple")
7449 (const_string "multiple")
7450 (const_string "multiple")
7451 (const_string "multiple")])]
7454 (define_insn "*movsfcc_soft_insn"
7455 [(set (match_operand:SF 0 "s_register_operand" "=r,r")
7456 (if_then_else:SF (match_operator 3 "arm_comparison_operator"
7457 [(match_operand 4 "cc_register" "") (const_int 0)])
7458 (match_operand:SF 1 "s_register_operand" "0,r")
7459 (match_operand:SF 2 "s_register_operand" "r,0")))]
7460 "TARGET_ARM && TARGET_SOFT_FLOAT"
7464 [(set_attr "conds" "use")
7465 (set_attr "type" "mov_reg")]
7469 ;; Jump and linkage insns
7471 (define_expand "jump"
7473 (label_ref (match_operand 0 "" "")))]
7478 (define_insn "*arm_jump"
7480 (label_ref (match_operand 0 "" "")))]
7484 if (arm_ccfsm_state == 1 || arm_ccfsm_state == 2)
7486 arm_ccfsm_state += 2;
7489 return \"b%?\\t%l0\";
7492 [(set_attr "predicable" "yes")
7493 (set (attr "length")
7495 (and (match_test "TARGET_THUMB2")
7496 (and (ge (minus (match_dup 0) (pc)) (const_int -2044))
7497 (le (minus (match_dup 0) (pc)) (const_int 2048))))
7500 (set_attr "type" "branch")]
7503 (define_expand "call"
7504 [(parallel [(call (match_operand 0 "memory_operand")
7505 (match_operand 1 "general_operand"))
7506 (use (match_operand 2 "" ""))
7507 (clobber (reg:SI LR_REGNUM))])]
7512 tree addr = MEM_EXPR (operands[0]);
7514 /* In an untyped call, we can get NULL for operand 2. */
7515 if (operands[2] == NULL_RTX)
7516 operands[2] = const0_rtx;
7518 /* Decide if we should generate indirect calls by loading the
7519 32-bit address of the callee into a register before performing the
7521 callee = XEXP (operands[0], 0);
7522 if (GET_CODE (callee) == SYMBOL_REF
7523 ? arm_is_long_call_p (SYMBOL_REF_DECL (callee))
7525 XEXP (operands[0], 0) = force_reg (Pmode, callee);
7527 if (TARGET_FDPIC && !SYMBOL_REF_P (XEXP (operands[0], 0)))
7528 /* Indirect call: set r9 with FDPIC value of callee. */
7529 XEXP (operands[0], 0)
7530 = arm_load_function_descriptor (XEXP (operands[0], 0));
7532 if (detect_cmse_nonsecure_call (addr))
7534 pat = gen_nonsecure_call_internal (operands[0], operands[1],
7536 emit_call_insn (pat);
7540 pat = gen_call_internal (operands[0], operands[1], operands[2]);
7541 arm_emit_call_insn (pat, XEXP (operands[0], 0), false);
7544 /* Restore FDPIC register (r9) after call. */
7547 rtx fdpic_reg = gen_rtx_REG (Pmode, FDPIC_REGNUM);
7548 rtx initial_fdpic_reg
7549 = get_hard_reg_initial_val (Pmode, FDPIC_REGNUM);
7551 emit_insn (gen_restore_pic_register_after_call (fdpic_reg,
7552 initial_fdpic_reg));
7559 (define_insn "restore_pic_register_after_call"
7560 [(set (match_operand:SI 0 "s_register_operand" "+r,r")
7561 (unspec:SI [(match_dup 0)
7562 (match_operand:SI 1 "nonimmediate_operand" "r,m")]
7563 UNSPEC_PIC_RESTORE))]
7570 (define_expand "call_internal"
7571 [(parallel [(call (match_operand 0 "memory_operand")
7572 (match_operand 1 "general_operand"))
7573 (use (match_operand 2 "" ""))
7574 (clobber (reg:SI LR_REGNUM))])])
7576 (define_expand "nonsecure_call_internal"
7577 [(parallel [(call (unspec:SI [(match_operand 0 "memory_operand")]
7578 UNSPEC_NONSECURE_MEM)
7579 (match_operand 1 "general_operand"))
7580 (use (match_operand 2 "" ""))
7581 (clobber (reg:SI LR_REGNUM))])]
7586 tmp = copy_to_suggested_reg (XEXP (operands[0], 0),
7587 gen_rtx_REG (SImode, R4_REGNUM),
7590 operands[0] = replace_equiv_address (operands[0], tmp);
7593 (define_insn "*call_reg_armv5"
7594 [(call (mem:SI (match_operand:SI 0 "s_register_operand" "r"))
7595 (match_operand 1 "" ""))
7596 (use (match_operand 2 "" ""))
7597 (clobber (reg:SI LR_REGNUM))]
7598 "TARGET_ARM && arm_arch5t && !SIBLING_CALL_P (insn)"
7600 [(set_attr "type" "call")]
7603 (define_insn "*call_reg_arm"
7604 [(call (mem:SI (match_operand:SI 0 "s_register_operand" "r"))
7605 (match_operand 1 "" ""))
7606 (use (match_operand 2 "" ""))
7607 (clobber (reg:SI LR_REGNUM))]
7608 "TARGET_ARM && !arm_arch5t && !SIBLING_CALL_P (insn)"
7610 return output_call (operands);
7612 ;; length is worst case, normally it is only two
7613 [(set_attr "length" "12")
7614 (set_attr "type" "call")]
7618 (define_expand "call_value"
7619 [(parallel [(set (match_operand 0 "" "")
7620 (call (match_operand 1 "memory_operand")
7621 (match_operand 2 "general_operand")))
7622 (use (match_operand 3 "" ""))
7623 (clobber (reg:SI LR_REGNUM))])]
7628 tree addr = MEM_EXPR (operands[1]);
7630 /* In an untyped call, we can get NULL for operand 2. */
7631 if (operands[3] == 0)
7632 operands[3] = const0_rtx;
7634 /* Decide if we should generate indirect calls by loading the
7635 32-bit address of the callee into a register before performing the
7637 callee = XEXP (operands[1], 0);
7638 if (GET_CODE (callee) == SYMBOL_REF
7639 ? arm_is_long_call_p (SYMBOL_REF_DECL (callee))
7641 XEXP (operands[1], 0) = force_reg (Pmode, callee);
7643 if (TARGET_FDPIC && !SYMBOL_REF_P (XEXP (operands[1], 0)))
7644 /* Indirect call: set r9 with FDPIC value of callee. */
7645 XEXP (operands[1], 0)
7646 = arm_load_function_descriptor (XEXP (operands[1], 0));
7648 if (detect_cmse_nonsecure_call (addr))
7650 pat = gen_nonsecure_call_value_internal (operands[0], operands[1],
7651 operands[2], operands[3]);
7652 emit_call_insn (pat);
7656 pat = gen_call_value_internal (operands[0], operands[1],
7657 operands[2], operands[3]);
7658 arm_emit_call_insn (pat, XEXP (operands[1], 0), false);
7661 /* Restore FDPIC register (r9) after call. */
7664 rtx fdpic_reg = gen_rtx_REG (Pmode, FDPIC_REGNUM);
7665 rtx initial_fdpic_reg
7666 = get_hard_reg_initial_val (Pmode, FDPIC_REGNUM);
7668 emit_insn (gen_restore_pic_register_after_call (fdpic_reg,
7669 initial_fdpic_reg));
7676 (define_expand "call_value_internal"
7677 [(parallel [(set (match_operand 0 "" "")
7678 (call (match_operand 1 "memory_operand")
7679 (match_operand 2 "general_operand")))
7680 (use (match_operand 3 "" ""))
7681 (clobber (reg:SI LR_REGNUM))])])
7683 (define_expand "nonsecure_call_value_internal"
7684 [(parallel [(set (match_operand 0 "" "")
7685 (call (unspec:SI [(match_operand 1 "memory_operand")]
7686 UNSPEC_NONSECURE_MEM)
7687 (match_operand 2 "general_operand")))
7688 (use (match_operand 3 "" ""))
7689 (clobber (reg:SI LR_REGNUM))])]
7694 tmp = copy_to_suggested_reg (XEXP (operands[1], 0),
7695 gen_rtx_REG (SImode, R4_REGNUM),
7698 operands[1] = replace_equiv_address (operands[1], tmp);
7701 (define_insn "*call_value_reg_armv5"
7702 [(set (match_operand 0 "" "")
7703 (call (mem:SI (match_operand:SI 1 "s_register_operand" "r"))
7704 (match_operand 2 "" "")))
7705 (use (match_operand 3 "" ""))
7706 (clobber (reg:SI LR_REGNUM))]
7707 "TARGET_ARM && arm_arch5t && !SIBLING_CALL_P (insn)"
7709 [(set_attr "type" "call")]
7712 (define_insn "*call_value_reg_arm"
7713 [(set (match_operand 0 "" "")
7714 (call (mem:SI (match_operand:SI 1 "s_register_operand" "r"))
7715 (match_operand 2 "" "")))
7716 (use (match_operand 3 "" ""))
7717 (clobber (reg:SI LR_REGNUM))]
7718 "TARGET_ARM && !arm_arch5t && !SIBLING_CALL_P (insn)"
7720 return output_call (&operands[1]);
7722 [(set_attr "length" "12")
7723 (set_attr "type" "call")]
7726 ;; Allow calls to SYMBOL_REFs specially as they are not valid general addresses
7727 ;; The 'a' causes the operand to be treated as an address, i.e. no '#' output.
7729 (define_insn "*call_symbol"
7730 [(call (mem:SI (match_operand:SI 0 "" ""))
7731 (match_operand 1 "" ""))
7732 (use (match_operand 2 "" ""))
7733 (clobber (reg:SI LR_REGNUM))]
7735 && !SIBLING_CALL_P (insn)
7736 && (GET_CODE (operands[0]) == SYMBOL_REF)
7737 && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[0]))"
7740 rtx op = operands[0];
7742 /* Switch mode now when possible. */
7743 if (SYMBOL_REF_DECL (op) && !TREE_PUBLIC (SYMBOL_REF_DECL (op))
7744 && arm_arch5t && arm_change_mode_p (SYMBOL_REF_DECL (op)))
7745 return NEED_PLT_RELOC ? \"blx%?\\t%a0(PLT)\" : \"blx%?\\t(%a0)\";
7747 return NEED_PLT_RELOC ? \"bl%?\\t%a0(PLT)\" : \"bl%?\\t%a0\";
7749 [(set_attr "type" "call")]
7752 (define_insn "*call_value_symbol"
7753 [(set (match_operand 0 "" "")
7754 (call (mem:SI (match_operand:SI 1 "" ""))
7755 (match_operand:SI 2 "" "")))
7756 (use (match_operand 3 "" ""))
7757 (clobber (reg:SI LR_REGNUM))]
7759 && !SIBLING_CALL_P (insn)
7760 && (GET_CODE (operands[1]) == SYMBOL_REF)
7761 && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[1]))"
7764 rtx op = operands[1];
7766 /* Switch mode now when possible. */
7767 if (SYMBOL_REF_DECL (op) && !TREE_PUBLIC (SYMBOL_REF_DECL (op))
7768 && arm_arch5t && arm_change_mode_p (SYMBOL_REF_DECL (op)))
7769 return NEED_PLT_RELOC ? \"blx%?\\t%a1(PLT)\" : \"blx%?\\t(%a1)\";
7771 return NEED_PLT_RELOC ? \"bl%?\\t%a1(PLT)\" : \"bl%?\\t%a1\";
7773 [(set_attr "type" "call")]
7776 (define_expand "sibcall_internal"
7777 [(parallel [(call (match_operand 0 "memory_operand")
7778 (match_operand 1 "general_operand"))
7780 (use (match_operand 2 "" ""))])])
7782 ;; We may also be able to do sibcalls for Thumb, but it's much harder...
7783 (define_expand "sibcall"
7784 [(parallel [(call (match_operand 0 "memory_operand")
7785 (match_operand 1 "general_operand"))
7787 (use (match_operand 2 "" ""))])]
7793 if ((!REG_P (XEXP (operands[0], 0))
7794 && GET_CODE (XEXP (operands[0], 0)) != SYMBOL_REF)
7795 || (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
7796 && arm_is_long_call_p (SYMBOL_REF_DECL (XEXP (operands[0], 0)))))
7797 XEXP (operands[0], 0) = force_reg (SImode, XEXP (operands[0], 0));
7799 if (operands[2] == NULL_RTX)
7800 operands[2] = const0_rtx;
7802 pat = gen_sibcall_internal (operands[0], operands[1], operands[2]);
7803 arm_emit_call_insn (pat, operands[0], true);
7808 (define_expand "sibcall_value_internal"
7809 [(parallel [(set (match_operand 0 "" "")
7810 (call (match_operand 1 "memory_operand")
7811 (match_operand 2 "general_operand")))
7813 (use (match_operand 3 "" ""))])])
7815 (define_expand "sibcall_value"
7816 [(parallel [(set (match_operand 0 "" "")
7817 (call (match_operand 1 "memory_operand")
7818 (match_operand 2 "general_operand")))
7820 (use (match_operand 3 "" ""))])]
7826 if ((!REG_P (XEXP (operands[1], 0))
7827 && GET_CODE (XEXP (operands[1], 0)) != SYMBOL_REF)
7828 || (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
7829 && arm_is_long_call_p (SYMBOL_REF_DECL (XEXP (operands[1], 0)))))
7830 XEXP (operands[1], 0) = force_reg (SImode, XEXP (operands[1], 0));
7832 if (operands[3] == NULL_RTX)
7833 operands[3] = const0_rtx;
7835 pat = gen_sibcall_value_internal (operands[0], operands[1],
7836 operands[2], operands[3]);
7837 arm_emit_call_insn (pat, operands[1], true);
7842 (define_insn "*sibcall_insn"
7843 [(call (mem:SI (match_operand:SI 0 "call_insn_operand" "Cs, US"))
7844 (match_operand 1 "" ""))
7846 (use (match_operand 2 "" ""))]
7847 "TARGET_32BIT && SIBLING_CALL_P (insn)"
7849 if (which_alternative == 1)
7850 return NEED_PLT_RELOC ? \"b%?\\t%a0(PLT)\" : \"b%?\\t%a0\";
7853 if (arm_arch5t || arm_arch4t)
7854 return \"bx%?\\t%0\\t%@ indirect register sibling call\";
7856 return \"mov%?\\t%|pc, %0\\t%@ indirect register sibling call\";
7859 [(set_attr "type" "call")]
7862 (define_insn "*sibcall_value_insn"
7863 [(set (match_operand 0 "" "")
7864 (call (mem:SI (match_operand:SI 1 "call_insn_operand" "Cs,US"))
7865 (match_operand 2 "" "")))
7867 (use (match_operand 3 "" ""))]
7868 "TARGET_32BIT && SIBLING_CALL_P (insn)"
7870 if (which_alternative == 1)
7871 return NEED_PLT_RELOC ? \"b%?\\t%a1(PLT)\" : \"b%?\\t%a1\";
7874 if (arm_arch5t || arm_arch4t)
7875 return \"bx%?\\t%1\";
7877 return \"mov%?\\t%|pc, %1\\t@ indirect sibling call \";
7880 [(set_attr "type" "call")]
7883 (define_expand "<return_str>return"
7885 "(TARGET_ARM || (TARGET_THUMB2
7886 && ARM_FUNC_TYPE (arm_current_func_type ()) == ARM_FT_NORMAL
7887 && !IS_STACKALIGN (arm_current_func_type ())))
7888 <return_cond_false>"
7893 thumb2_expand_return (<return_simple_p>);
7900 ;; Often the return insn will be the same as loading from memory, so set attr
7901 (define_insn "*arm_return"
7903 "TARGET_ARM && USE_RETURN_INSN (FALSE)"
7906 if (arm_ccfsm_state == 2)
7908 arm_ccfsm_state += 2;
7911 return output_return_instruction (const_true_rtx, true, false, false);
7913 [(set_attr "type" "load_4")
7914 (set_attr "length" "12")
7915 (set_attr "predicable" "yes")]
7918 (define_insn "*cond_<return_str>return"
7920 (if_then_else (match_operator 0 "arm_comparison_operator"
7921 [(match_operand 1 "cc_register" "") (const_int 0)])
7924 "TARGET_ARM <return_cond_true>"
7927 if (arm_ccfsm_state == 2)
7929 arm_ccfsm_state += 2;
7932 return output_return_instruction (operands[0], true, false,
7935 [(set_attr "conds" "use")
7936 (set_attr "length" "12")
7937 (set_attr "type" "load_4")]
7940 (define_insn "*cond_<return_str>return_inverted"
7942 (if_then_else (match_operator 0 "arm_comparison_operator"
7943 [(match_operand 1 "cc_register" "") (const_int 0)])
7946 "TARGET_ARM <return_cond_true>"
7949 if (arm_ccfsm_state == 2)
7951 arm_ccfsm_state += 2;
7954 return output_return_instruction (operands[0], true, true,
7957 [(set_attr "conds" "use")
7958 (set_attr "length" "12")
7959 (set_attr "type" "load_4")]
7962 (define_insn "*arm_simple_return"
7967 if (arm_ccfsm_state == 2)
7969 arm_ccfsm_state += 2;
7972 return output_return_instruction (const_true_rtx, true, false, true);
7974 [(set_attr "type" "branch")
7975 (set_attr "length" "4")
7976 (set_attr "predicable" "yes")]
7979 ;; Generate a sequence of instructions to determine if the processor is
7980 ;; in 26-bit or 32-bit mode, and return the appropriate return address
7983 (define_expand "return_addr_mask"
7985 (compare:CC_NOOV (unspec [(const_int 0)] UNSPEC_CHECK_ARCH)
7987 (set (match_operand:SI 0 "s_register_operand")
7988 (if_then_else:SI (eq (match_dup 1) (const_int 0))
7990 (const_int 67108860)))] ; 0x03fffffc
7993 operands[1] = gen_rtx_REG (CC_NOOVmode, CC_REGNUM);
7996 (define_insn "*check_arch2"
7997 [(set (match_operand:CC_NOOV 0 "cc_register" "")
7998 (compare:CC_NOOV (unspec [(const_int 0)] UNSPEC_CHECK_ARCH)
8001 "teq\\t%|r0, %|r0\;teq\\t%|pc, %|pc"
8002 [(set_attr "length" "8")
8003 (set_attr "conds" "set")
8004 (set_attr "type" "multiple")]
8007 ;; Call subroutine returning any type.
8009 (define_expand "untyped_call"
8010 [(parallel [(call (match_operand 0 "" "")
8012 (match_operand 1 "" "")
8013 (match_operand 2 "" "")])]
8014 "TARGET_EITHER && !TARGET_FDPIC"
8018 rtx par = gen_rtx_PARALLEL (VOIDmode,
8019 rtvec_alloc (XVECLEN (operands[2], 0)));
8020 rtx addr = gen_reg_rtx (Pmode);
8024 emit_move_insn (addr, XEXP (operands[1], 0));
8025 mem = change_address (operands[1], BLKmode, addr);
8027 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8029 rtx src = SET_SRC (XVECEXP (operands[2], 0, i));
8031 /* Default code only uses r0 as a return value, but we could
8032 be using anything up to 4 registers. */
8033 if (REGNO (src) == R0_REGNUM)
8034 src = gen_rtx_REG (TImode, R0_REGNUM);
8036 XVECEXP (par, 0, i) = gen_rtx_EXPR_LIST (VOIDmode, src,
8038 size += GET_MODE_SIZE (GET_MODE (src));
8041 emit_call_insn (gen_call_value (par, operands[0], const0_rtx, NULL));
8045 for (i = 0; i < XVECLEN (par, 0); i++)
8047 HOST_WIDE_INT offset = 0;
8048 rtx reg = XEXP (XVECEXP (par, 0, i), 0);
8051 emit_move_insn (addr, plus_constant (Pmode, addr, size));
8053 mem = change_address (mem, GET_MODE (reg), NULL);
8054 if (REGNO (reg) == R0_REGNUM)
8056 /* On thumb we have to use a write-back instruction. */
8057 emit_insn (arm_gen_store_multiple (arm_regs_in_sequence, 4, addr,
8058 TARGET_THUMB ? TRUE : FALSE, mem, &offset));
8059 size = TARGET_ARM ? 16 : 0;
8063 emit_move_insn (mem, reg);
8064 size = GET_MODE_SIZE (GET_MODE (reg));
8068 /* The optimizer does not know that the call sets the function value
8069 registers we stored in the result block. We avoid problems by
8070 claiming that all hard registers are used and clobbered at this
8072 emit_insn (gen_blockage ());
8078 (define_expand "untyped_return"
8079 [(match_operand:BLK 0 "memory_operand")
8080 (match_operand 1 "" "")]
8081 "TARGET_EITHER && !TARGET_FDPIC"
8085 rtx addr = gen_reg_rtx (Pmode);
8089 emit_move_insn (addr, XEXP (operands[0], 0));
8090 mem = change_address (operands[0], BLKmode, addr);
8092 for (i = 0; i < XVECLEN (operands[1], 0); i++)
8094 HOST_WIDE_INT offset = 0;
8095 rtx reg = SET_DEST (XVECEXP (operands[1], 0, i));
8098 emit_move_insn (addr, plus_constant (Pmode, addr, size));
8100 mem = change_address (mem, GET_MODE (reg), NULL);
8101 if (REGNO (reg) == R0_REGNUM)
8103 /* On thumb we have to use a write-back instruction. */
8104 emit_insn (arm_gen_load_multiple (arm_regs_in_sequence, 4, addr,
8105 TARGET_THUMB ? TRUE : FALSE, mem, &offset));
8106 size = TARGET_ARM ? 16 : 0;
8110 emit_move_insn (reg, mem);
8111 size = GET_MODE_SIZE (GET_MODE (reg));
8115 /* Emit USE insns before the return. */
8116 for (i = 0; i < XVECLEN (operands[1], 0); i++)
8117 emit_use (SET_DEST (XVECEXP (operands[1], 0, i)));
8119 /* Construct the return. */
8120 expand_naked_return ();
8126 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
8127 ;; all of memory. This blocks insns from being moved across this point.
8129 (define_insn "blockage"
8130 [(unspec_volatile [(const_int 0)] VUNSPEC_BLOCKAGE)]
8133 [(set_attr "length" "0")
8134 (set_attr "type" "block")]
8137 ;; Since we hard code r0 here use the 'o' constraint to prevent
8138 ;; provoking undefined behaviour in the hardware with putting out
8139 ;; auto-increment operations with potentially r0 as the base register.
8140 (define_insn "probe_stack"
8141 [(set (match_operand:SI 0 "memory_operand" "=o")
8142 (unspec:SI [(const_int 0)] UNSPEC_PROBE_STACK))]
8145 [(set_attr "type" "store_4")
8146 (set_attr "predicable" "yes")]
8149 (define_insn "probe_stack_range"
8150 [(set (match_operand:SI 0 "register_operand" "=r")
8151 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "0")
8152 (match_operand:SI 2 "register_operand" "r")]
8153 VUNSPEC_PROBE_STACK_RANGE))]
8156 return output_probe_stack_range (operands[0], operands[2]);
8158 [(set_attr "type" "multiple")
8159 (set_attr "conds" "clob")]
8162 ;; Named patterns for stack smashing protection.
8163 (define_expand "stack_protect_combined_set"
8165 [(set (match_operand:SI 0 "memory_operand")
8166 (unspec:SI [(match_operand:SI 1 "guard_operand")]
8168 (clobber (match_scratch:SI 2 ""))
8169 (clobber (match_scratch:SI 3 ""))])]
8174 ;; Use a separate insn from the above expand to be able to have the mem outside
8175 ;; the operand #1 when register allocation comes. This is needed to avoid LRA
8176 ;; try to reload the guard since we need to control how PIC access is done in
8177 ;; the -fpic/-fPIC case (see COMPUTE_NOW parameter when calling
8178 ;; legitimize_pic_address ()).
8179 (define_insn_and_split "*stack_protect_combined_set_insn"
8180 [(set (match_operand:SI 0 "memory_operand" "=m,m")
8181 (unspec:SI [(mem:SI (match_operand:SI 1 "guard_addr_operand" "X,X"))]
8183 (clobber (match_scratch:SI 2 "=&l,&r"))
8184 (clobber (match_scratch:SI 3 "=&l,&r"))]
8188 [(parallel [(set (match_dup 0) (unspec:SI [(mem:SI (match_dup 2))]
8190 (clobber (match_dup 2))])]
8198 pic_reg = gen_rtx_REG (Pmode, FDPIC_REGNUM);
8200 pic_reg = operands[3];
8202 /* Forces recomputing of GOT base now. */
8203 legitimize_pic_address (operands[1], SImode, operands[2], pic_reg,
8204 true /*compute_now*/);
8208 if (address_operand (operands[1], SImode))
8209 operands[2] = operands[1];
8212 rtx mem = XEXP (force_const_mem (SImode, operands[1]), 0);
8213 emit_move_insn (operands[2], mem);
8217 [(set_attr "arch" "t1,32")]
8220 ;; DO NOT SPLIT THIS INSN. It's important for security reasons that the
8221 ;; canary value does not live beyond the life of this sequence.
8222 (define_insn "*stack_protect_set_insn"
8223 [(set (match_operand:SI 0 "memory_operand" "=m,m")
8224 (unspec:SI [(mem:SI (match_operand:SI 1 "register_operand" "+&l,&r"))]
8226 (clobber (match_dup 1))]
8229 ldr\\t%1, [%1]\;str\\t%1, %0\;movs\t%1, #0
8230 ldr\\t%1, [%1]\;str\\t%1, %0\;mov\t%1, #0"
8231 [(set_attr "length" "8,12")
8232 (set_attr "conds" "clob,nocond")
8233 (set_attr "type" "multiple")
8234 (set_attr "arch" "t1,32")]
8237 (define_expand "stack_protect_combined_test"
8241 (eq (match_operand:SI 0 "memory_operand")
8242 (unspec:SI [(match_operand:SI 1 "guard_operand")]
8244 (label_ref (match_operand 2))
8246 (clobber (match_scratch:SI 3 ""))
8247 (clobber (match_scratch:SI 4 ""))
8248 (clobber (reg:CC CC_REGNUM))])]
8253 ;; Use a separate insn from the above expand to be able to have the mem outside
8254 ;; the operand #1 when register allocation comes. This is needed to avoid LRA
8255 ;; try to reload the guard since we need to control how PIC access is done in
8256 ;; the -fpic/-fPIC case (see COMPUTE_NOW parameter when calling
8257 ;; legitimize_pic_address ()).
8258 (define_insn_and_split "*stack_protect_combined_test_insn"
8261 (eq (match_operand:SI 0 "memory_operand" "m,m")
8262 (unspec:SI [(mem:SI (match_operand:SI 1 "guard_addr_operand" "X,X"))]
8264 (label_ref (match_operand 2))
8266 (clobber (match_scratch:SI 3 "=&l,&r"))
8267 (clobber (match_scratch:SI 4 "=&l,&r"))
8268 (clobber (reg:CC CC_REGNUM))]
8281 pic_reg = gen_rtx_REG (Pmode, FDPIC_REGNUM);
8283 pic_reg = operands[4];
8285 /* Forces recomputing of GOT base now. */
8286 legitimize_pic_address (operands[1], SImode, operands[3], pic_reg,
8287 true /*compute_now*/);
8291 if (address_operand (operands[1], SImode))
8292 operands[3] = operands[1];
8295 rtx mem = XEXP (force_const_mem (SImode, operands[1]), 0);
8296 emit_move_insn (operands[3], mem);
8301 emit_insn (gen_arm_stack_protect_test_insn (operands[4], operands[0],
8303 rtx cc_reg = gen_rtx_REG (CC_Zmode, CC_REGNUM);
8304 eq = gen_rtx_EQ (CC_Zmode, cc_reg, const0_rtx);
8305 emit_jump_insn (gen_arm_cond_branch (operands[2], eq, cc_reg));
8309 emit_insn (gen_thumb1_stack_protect_test_insn (operands[4], operands[0],
8311 eq = gen_rtx_EQ (VOIDmode, operands[4], const0_rtx);
8312 emit_jump_insn (gen_cbranchsi4 (eq, operands[4], const0_rtx,
8317 [(set_attr "arch" "t1,32")]
8320 (define_insn "arm_stack_protect_test_insn"
8321 [(set (reg:CC_Z CC_REGNUM)
8322 (compare:CC_Z (unspec:SI [(match_operand:SI 1 "memory_operand" "m,m")
8323 (mem:SI (match_operand:SI 2 "register_operand" "+l,r"))]
8326 (clobber (match_operand:SI 0 "register_operand" "=&l,&r"))
8327 (clobber (match_dup 2))]
8329 "ldr\t%0, [%2]\;ldr\t%2, %1\;eors\t%0, %2, %0"
8330 [(set_attr "length" "8,12")
8331 (set_attr "conds" "set")
8332 (set_attr "type" "multiple")
8333 (set_attr "arch" "t,32")]
8336 (define_expand "casesi"
8337 [(match_operand:SI 0 "s_register_operand") ; index to jump on
8338 (match_operand:SI 1 "const_int_operand") ; lower bound
8339 (match_operand:SI 2 "const_int_operand") ; total range
8340 (match_operand:SI 3 "" "") ; table label
8341 (match_operand:SI 4 "" "")] ; Out of range label
8342 "(TARGET_32BIT || optimize_size || flag_pic) && !target_pure_code"
8345 enum insn_code code;
8346 if (operands[1] != const0_rtx)
8348 rtx reg = gen_reg_rtx (SImode);
8350 emit_insn (gen_addsi3 (reg, operands[0],
8351 gen_int_mode (-INTVAL (operands[1]),
8357 code = CODE_FOR_arm_casesi_internal;
8358 else if (TARGET_THUMB1)
8359 code = CODE_FOR_thumb1_casesi_internal_pic;
8361 code = CODE_FOR_thumb2_casesi_internal_pic;
8363 code = CODE_FOR_thumb2_casesi_internal;
8365 if (!insn_data[(int) code].operand[1].predicate(operands[2], SImode))
8366 operands[2] = force_reg (SImode, operands[2]);
8368 emit_jump_insn (GEN_FCN ((int) code) (operands[0], operands[2],
8369 operands[3], operands[4]));
8374 ;; The USE in this pattern is needed to tell flow analysis that this is
8375 ;; a CASESI insn. It has no other purpose.
8376 (define_expand "arm_casesi_internal"
8377 [(parallel [(set (pc)
8379 (leu (match_operand:SI 0 "s_register_operand")
8380 (match_operand:SI 1 "arm_rhs_operand"))
8382 (label_ref:SI (match_operand 3 ""))))
8383 (clobber (reg:CC CC_REGNUM))
8384 (use (label_ref:SI (match_operand 2 "")))])]
8387 operands[4] = gen_rtx_MULT (SImode, operands[0], GEN_INT (4));
8388 operands[4] = gen_rtx_PLUS (SImode, operands[4],
8389 gen_rtx_LABEL_REF (SImode, operands[2]));
8390 operands[4] = gen_rtx_MEM (SImode, operands[4]);
8391 MEM_READONLY_P (operands[4]) = 1;
8392 MEM_NOTRAP_P (operands[4]) = 1;
8395 (define_insn "*arm_casesi_internal"
8396 [(parallel [(set (pc)
8398 (leu (match_operand:SI 0 "s_register_operand" "r")
8399 (match_operand:SI 1 "arm_rhs_operand" "rI"))
8400 (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
8401 (label_ref:SI (match_operand 2 "" ""))))
8402 (label_ref:SI (match_operand 3 "" ""))))
8403 (clobber (reg:CC CC_REGNUM))
8404 (use (label_ref:SI (match_dup 2)))])]
8408 return \"cmp\\t%0, %1\;addls\\t%|pc, %|pc, %0, asl #2\;b\\t%l3\";
8409 return \"cmp\\t%0, %1\;ldrls\\t%|pc, [%|pc, %0, asl #2]\;b\\t%l3\";
8411 [(set_attr "conds" "clob")
8412 (set_attr "length" "12")
8413 (set_attr "type" "multiple")]
8416 (define_expand "indirect_jump"
8418 (match_operand:SI 0 "s_register_operand"))]
8421 /* Thumb-2 doesn't have mov pc, reg. Explicitly set the low bit of the
8422 address and use bx. */
8426 tmp = gen_reg_rtx (SImode);
8427 emit_insn (gen_iorsi3 (tmp, operands[0], GEN_INT(1)));
8433 ;; NB Never uses BX.
8434 (define_insn "*arm_indirect_jump"
8436 (match_operand:SI 0 "s_register_operand" "r"))]
8438 "mov%?\\t%|pc, %0\\t%@ indirect register jump"
8439 [(set_attr "predicable" "yes")
8440 (set_attr "type" "branch")]
8443 (define_insn "*load_indirect_jump"
8445 (match_operand:SI 0 "memory_operand" "m"))]
8447 "ldr%?\\t%|pc, %0\\t%@ indirect memory jump"
8448 [(set_attr "type" "load_4")
8449 (set_attr "pool_range" "4096")
8450 (set_attr "neg_pool_range" "4084")
8451 (set_attr "predicable" "yes")]
8461 [(set (attr "length")
8462 (if_then_else (eq_attr "is_thumb" "yes")
8465 (set_attr "type" "mov_reg")]
8469 [(trap_if (const_int 1) (const_int 0))]
8473 return \".inst\\t0xe7f000f0\";
8475 return \".inst\\t0xdeff\";
8477 [(set (attr "length")
8478 (if_then_else (eq_attr "is_thumb" "yes")
8481 (set_attr "type" "trap")
8482 (set_attr "conds" "unconditional")]
8486 ;; Patterns to allow combination of arithmetic, cond code and shifts
8488 (define_insn "*<arith_shift_insn>_multsi"
8489 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
8491 (mult:SI (match_operand:SI 2 "s_register_operand" "r,r")
8492 (match_operand:SI 3 "power_of_two_operand" ""))
8493 (match_operand:SI 1 "s_register_operand" "rk,<t2_binop0>")))]
8495 "<arith_shift_insn>%?\\t%0, %1, %2, lsl %b3"
8496 [(set_attr "predicable" "yes")
8497 (set_attr "shift" "2")
8498 (set_attr "arch" "a,t2")
8499 (set_attr "type" "alu_shift_imm")])
8501 (define_insn "*<arith_shift_insn>_shiftsi"
8502 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
8504 (match_operator:SI 2 "shift_nomul_operator"
8505 [(match_operand:SI 3 "s_register_operand" "r,r,r")
8506 (match_operand:SI 4 "shift_amount_operand" "M,M,r")])
8507 (match_operand:SI 1 "s_register_operand" "rk,<t2_binop0>,rk")))]
8508 "TARGET_32BIT && GET_CODE (operands[2]) != MULT"
8509 "<arith_shift_insn>%?\\t%0, %1, %3%S2"
8510 [(set_attr "predicable" "yes")
8511 (set_attr "shift" "3")
8512 (set_attr "arch" "a,t2,a")
8513 (set_attr "type" "alu_shift_imm,alu_shift_imm,alu_shift_reg")])
8516 [(set (match_operand:SI 0 "s_register_operand" "")
8517 (match_operator:SI 1 "shiftable_operator"
8518 [(match_operator:SI 2 "shiftable_operator"
8519 [(match_operator:SI 3 "shift_operator"
8520 [(match_operand:SI 4 "s_register_operand" "")
8521 (match_operand:SI 5 "reg_or_int_operand" "")])
8522 (match_operand:SI 6 "s_register_operand" "")])
8523 (match_operand:SI 7 "arm_rhs_operand" "")]))
8524 (clobber (match_operand:SI 8 "s_register_operand" ""))]
8527 (match_op_dup 2 [(match_op_dup 3 [(match_dup 4) (match_dup 5)])
8530 (match_op_dup 1 [(match_dup 8) (match_dup 7)]))]
8533 (define_insn "*arith_shiftsi_compare0"
8534 [(set (reg:CC_NOOV CC_REGNUM)
8536 (match_operator:SI 1 "shiftable_operator"
8537 [(match_operator:SI 3 "shift_operator"
8538 [(match_operand:SI 4 "s_register_operand" "r,r")
8539 (match_operand:SI 5 "shift_amount_operand" "M,r")])
8540 (match_operand:SI 2 "s_register_operand" "r,r")])
8542 (set (match_operand:SI 0 "s_register_operand" "=r,r")
8543 (match_op_dup 1 [(match_op_dup 3 [(match_dup 4) (match_dup 5)])
8546 "%i1s%?\\t%0, %2, %4%S3"
8547 [(set_attr "conds" "set")
8548 (set_attr "shift" "4")
8549 (set_attr "arch" "32,a")
8550 (set_attr "type" "alus_shift_imm,alus_shift_reg")])
8552 (define_insn "*arith_shiftsi_compare0_scratch"
8553 [(set (reg:CC_NOOV CC_REGNUM)
8555 (match_operator:SI 1 "shiftable_operator"
8556 [(match_operator:SI 3 "shift_operator"
8557 [(match_operand:SI 4 "s_register_operand" "r,r")
8558 (match_operand:SI 5 "shift_amount_operand" "M,r")])
8559 (match_operand:SI 2 "s_register_operand" "r,r")])
8561 (clobber (match_scratch:SI 0 "=r,r"))]
8563 "%i1s%?\\t%0, %2, %4%S3"
8564 [(set_attr "conds" "set")
8565 (set_attr "shift" "4")
8566 (set_attr "arch" "32,a")
8567 (set_attr "type" "alus_shift_imm,alus_shift_reg")])
8569 (define_insn "*sub_shiftsi"
8570 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
8571 (minus:SI (match_operand:SI 1 "s_register_operand" "r,r")
8572 (match_operator:SI 2 "shift_operator"
8573 [(match_operand:SI 3 "s_register_operand" "r,r")
8574 (match_operand:SI 4 "shift_amount_operand" "M,r")])))]
8576 "sub%?\\t%0, %1, %3%S2"
8577 [(set_attr "predicable" "yes")
8578 (set_attr "predicable_short_it" "no")
8579 (set_attr "shift" "3")
8580 (set_attr "arch" "32,a")
8581 (set_attr "type" "alus_shift_imm,alus_shift_reg")])
8583 (define_insn "*sub_shiftsi_compare0"
8584 [(set (reg:CC_NOOV CC_REGNUM)
8586 (minus:SI (match_operand:SI 1 "s_register_operand" "r,r,r")
8587 (match_operator:SI 2 "shift_operator"
8588 [(match_operand:SI 3 "s_register_operand" "r,r,r")
8589 (match_operand:SI 4 "shift_amount_operand" "M,r,M")]))
8591 (set (match_operand:SI 0 "s_register_operand" "=r,r,r")
8592 (minus:SI (match_dup 1)
8593 (match_op_dup 2 [(match_dup 3) (match_dup 4)])))]
8595 "subs%?\\t%0, %1, %3%S2"
8596 [(set_attr "conds" "set")
8597 (set_attr "shift" "3")
8598 (set_attr "arch" "32,a,a")
8599 (set_attr "type" "alus_shift_imm,alus_shift_reg,alus_shift_imm")])
8601 (define_insn "*sub_shiftsi_compare0_scratch"
8602 [(set (reg:CC_NOOV CC_REGNUM)
8604 (minus:SI (match_operand:SI 1 "s_register_operand" "r,r,r")
8605 (match_operator:SI 2 "shift_operator"
8606 [(match_operand:SI 3 "s_register_operand" "r,r,r")
8607 (match_operand:SI 4 "shift_amount_operand" "M,r,M")]))
8609 (clobber (match_scratch:SI 0 "=r,r,r"))]
8611 "subs%?\\t%0, %1, %3%S2"
8612 [(set_attr "conds" "set")
8613 (set_attr "shift" "3")
8614 (set_attr "arch" "32,a,a")
8615 (set_attr "type" "alus_shift_imm,alus_shift_reg,alus_shift_imm")])
8618 (define_insn_and_split "*and_scc"
8619 [(set (match_operand:SI 0 "s_register_operand" "=r")
8620 (and:SI (match_operator:SI 1 "arm_comparison_operator"
8621 [(match_operand 2 "cc_register" "") (const_int 0)])
8622 (match_operand:SI 3 "s_register_operand" "r")))]
8624 "#" ; "mov%D1\\t%0, #0\;and%d1\\t%0, %3, #1"
8625 "&& reload_completed"
8626 [(cond_exec (match_dup 5) (set (match_dup 0) (const_int 0)))
8627 (cond_exec (match_dup 4) (set (match_dup 0)
8628 (and:SI (match_dup 3) (const_int 1))))]
8630 machine_mode mode = GET_MODE (operands[2]);
8631 enum rtx_code rc = GET_CODE (operands[1]);
8633 /* Note that operands[4] is the same as operands[1],
8634 but with VOIDmode as the result. */
8635 operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
8636 if (mode == CCFPmode || mode == CCFPEmode)
8637 rc = reverse_condition_maybe_unordered (rc);
8639 rc = reverse_condition (rc);
8640 operands[5] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
8642 [(set_attr "conds" "use")
8643 (set_attr "type" "multiple")
8644 (set_attr "length" "8")]
8647 (define_insn_and_split "*ior_scc"
8648 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
8649 (ior:SI (match_operator:SI 1 "arm_comparison_operator"
8650 [(match_operand 2 "cc_register" "") (const_int 0)])
8651 (match_operand:SI 3 "s_register_operand" "0,?r")))]
8656 "&& reload_completed
8657 && REGNO (operands [0]) != REGNO (operands[3])"
8658 ;; && which_alternative == 1
8659 ; mov%D1\\t%0, %3\;orr%d1\\t%0, %3, #1
8660 [(cond_exec (match_dup 5) (set (match_dup 0) (match_dup 3)))
8661 (cond_exec (match_dup 4) (set (match_dup 0)
8662 (ior:SI (match_dup 3) (const_int 1))))]
8664 machine_mode mode = GET_MODE (operands[2]);
8665 enum rtx_code rc = GET_CODE (operands[1]);
8667 /* Note that operands[4] is the same as operands[1],
8668 but with VOIDmode as the result. */
8669 operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
8670 if (mode == CCFPmode || mode == CCFPEmode)
8671 rc = reverse_condition_maybe_unordered (rc);
8673 rc = reverse_condition (rc);
8674 operands[5] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
8676 [(set_attr "conds" "use")
8677 (set_attr "length" "4,8")
8678 (set_attr "type" "logic_imm,multiple")]
8681 ; A series of splitters for the compare_scc pattern below. Note that
8682 ; order is important.
8684 [(set (match_operand:SI 0 "s_register_operand" "")
8685 (lt:SI (match_operand:SI 1 "s_register_operand" "")
8687 (clobber (reg:CC CC_REGNUM))]
8688 "TARGET_32BIT && reload_completed"
8689 [(set (match_dup 0) (lshiftrt:SI (match_dup 1) (const_int 31)))])
8692 [(set (match_operand:SI 0 "s_register_operand" "")
8693 (ge:SI (match_operand:SI 1 "s_register_operand" "")
8695 (clobber (reg:CC CC_REGNUM))]
8696 "TARGET_32BIT && reload_completed"
8697 [(set (match_dup 0) (not:SI (match_dup 1)))
8698 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 31)))])
8701 [(set (match_operand:SI 0 "s_register_operand" "")
8702 (eq:SI (match_operand:SI 1 "s_register_operand" "")
8704 (clobber (reg:CC CC_REGNUM))]
8705 "arm_arch5t && TARGET_32BIT"
8706 [(set (match_dup 0) (clz:SI (match_dup 1)))
8707 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 5)))]
8711 [(set (match_operand:SI 0 "s_register_operand" "")
8712 (eq:SI (match_operand:SI 1 "s_register_operand" "")
8714 (clobber (reg:CC CC_REGNUM))]
8715 "TARGET_32BIT && reload_completed"
8717 [(set (reg:CC CC_REGNUM)
8718 (compare:CC (const_int 1) (match_dup 1)))
8720 (minus:SI (const_int 1) (match_dup 1)))])
8721 (cond_exec (ltu:CC (reg:CC CC_REGNUM) (const_int 0))
8722 (set (match_dup 0) (const_int 0)))])
8725 [(set (match_operand:SI 0 "s_register_operand" "")
8726 (ne:SI (match_operand:SI 1 "s_register_operand" "")
8727 (match_operand:SI 2 "const_int_operand" "")))
8728 (clobber (reg:CC CC_REGNUM))]
8729 "TARGET_32BIT && reload_completed"
8731 [(set (reg:CC CC_REGNUM)
8732 (compare:CC (match_dup 1) (match_dup 2)))
8733 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))])
8734 (cond_exec (ne:CC (reg:CC CC_REGNUM) (const_int 0))
8735 (set (match_dup 0) (const_int 1)))]
8737 operands[3] = gen_int_mode (-INTVAL (operands[2]), SImode);
8741 [(set (match_operand:SI 0 "s_register_operand" "")
8742 (ne:SI (match_operand:SI 1 "s_register_operand" "")
8743 (match_operand:SI 2 "arm_add_operand" "")))
8744 (clobber (reg:CC CC_REGNUM))]
8745 "TARGET_32BIT && reload_completed"
8747 [(set (reg:CC_NOOV CC_REGNUM)
8748 (compare:CC_NOOV (minus:SI (match_dup 1) (match_dup 2))
8750 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
8751 (cond_exec (ne:CC_NOOV (reg:CC_NOOV CC_REGNUM) (const_int 0))
8752 (set (match_dup 0) (const_int 1)))])
8754 (define_insn_and_split "*compare_scc"
8755 [(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts")
8756 (match_operator:SI 1 "arm_comparison_operator"
8757 [(match_operand:SI 2 "s_register_operand" "r,r")
8758 (match_operand:SI 3 "arm_add_operand" "rI,L")]))
8759 (clobber (reg:CC CC_REGNUM))]
8762 "&& reload_completed"
8763 [(set (reg:CC CC_REGNUM) (compare:CC (match_dup 2) (match_dup 3)))
8764 (cond_exec (match_dup 4) (set (match_dup 0) (const_int 0)))
8765 (cond_exec (match_dup 5) (set (match_dup 0) (const_int 1)))]
8768 machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[1]),
8769 operands[2], operands[3]);
8770 enum rtx_code rc = GET_CODE (operands[1]);
8772 tmp1 = gen_rtx_REG (mode, CC_REGNUM);
8774 operands[5] = gen_rtx_fmt_ee (rc, VOIDmode, tmp1, const0_rtx);
8775 if (mode == CCFPmode || mode == CCFPEmode)
8776 rc = reverse_condition_maybe_unordered (rc);
8778 rc = reverse_condition (rc);
8779 operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, tmp1, const0_rtx);
8781 [(set_attr "type" "multiple")]
8784 ;; Attempt to improve the sequence generated by the compare_scc splitters
8785 ;; not to use conditional execution.
8787 ;; Rd = (eq (reg1) (const_int0)) // ARMv5
8791 [(set (reg:CC CC_REGNUM)
8792 (compare:CC (match_operand:SI 1 "register_operand" "")
8794 (cond_exec (ne (reg:CC CC_REGNUM) (const_int 0))
8795 (set (match_operand:SI 0 "register_operand" "") (const_int 0)))
8796 (cond_exec (eq (reg:CC CC_REGNUM) (const_int 0))
8797 (set (match_dup 0) (const_int 1)))]
8798 "arm_arch5t && TARGET_32BIT && peep2_regno_dead_p (3, CC_REGNUM)"
8799 [(set (match_dup 0) (clz:SI (match_dup 1)))
8800 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 5)))]
8803 ;; Rd = (eq (reg1) (const_int0)) // !ARMv5
8807 [(set (reg:CC CC_REGNUM)
8808 (compare:CC (match_operand:SI 1 "register_operand" "")
8810 (cond_exec (ne (reg:CC CC_REGNUM) (const_int 0))
8811 (set (match_operand:SI 0 "register_operand" "") (const_int 0)))
8812 (cond_exec (eq (reg:CC CC_REGNUM) (const_int 0))
8813 (set (match_dup 0) (const_int 1)))
8814 (match_scratch:SI 2 "r")]
8815 "TARGET_32BIT && peep2_regno_dead_p (3, CC_REGNUM)"
8817 [(set (reg:CC CC_REGNUM)
8818 (compare:CC (const_int 0) (match_dup 1)))
8819 (set (match_dup 2) (minus:SI (const_int 0) (match_dup 1)))])
8821 (plus:SI (plus:SI (match_dup 1) (match_dup 2))
8822 (geu:SI (reg:CC CC_REGNUM) (const_int 0))))]
8825 ;; Rd = (eq (reg1) (reg2/imm)) // ARMv5 and optimising for speed.
8826 ;; sub Rd, Reg1, reg2
8830 [(set (reg:CC CC_REGNUM)
8831 (compare:CC (match_operand:SI 1 "register_operand" "")
8832 (match_operand:SI 2 "arm_rhs_operand" "")))
8833 (cond_exec (ne (reg:CC CC_REGNUM) (const_int 0))
8834 (set (match_operand:SI 0 "register_operand" "") (const_int 0)))
8835 (cond_exec (eq (reg:CC CC_REGNUM) (const_int 0))
8836 (set (match_dup 0) (const_int 1)))]
8837 "arm_arch5t && TARGET_32BIT && peep2_regno_dead_p (3, CC_REGNUM)
8838 && !(TARGET_THUMB2 && optimize_insn_for_size_p ())"
8839 [(set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))
8840 (set (match_dup 0) (clz:SI (match_dup 0)))
8841 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 5)))]
8845 ;; Rd = (eq (reg1) (reg2)) // ! ARMv5 or optimising for size.
8846 ;; sub T1, Reg1, reg2
8850 [(set (reg:CC CC_REGNUM)
8851 (compare:CC (match_operand:SI 1 "register_operand" "")
8852 (match_operand:SI 2 "arm_rhs_operand" "")))
8853 (cond_exec (ne (reg:CC CC_REGNUM) (const_int 0))
8854 (set (match_operand:SI 0 "register_operand" "") (const_int 0)))
8855 (cond_exec (eq (reg:CC CC_REGNUM) (const_int 0))
8856 (set (match_dup 0) (const_int 1)))
8857 (match_scratch:SI 3 "r")]
8858 "TARGET_32BIT && peep2_regno_dead_p (3, CC_REGNUM)"
8859 [(set (match_dup 3) (match_dup 4))
8861 [(set (reg:CC CC_REGNUM)
8862 (compare:CC (const_int 0) (match_dup 3)))
8863 (set (match_dup 0) (minus:SI (const_int 0) (match_dup 3)))])
8865 (plus:SI (plus:SI (match_dup 0) (match_dup 3))
8866 (geu:SI (reg:CC CC_REGNUM) (const_int 0))))]
8868 if (CONST_INT_P (operands[2]))
8869 operands[4] = plus_constant (SImode, operands[1], -INTVAL (operands[2]));
8871 operands[4] = gen_rtx_MINUS (SImode, operands[1], operands[2]);
8874 (define_insn "*cond_move"
8875 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
8876 (if_then_else:SI (match_operator 3 "equality_operator"
8877 [(match_operator 4 "arm_comparison_operator"
8878 [(match_operand 5 "cc_register" "") (const_int 0)])
8880 (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI")
8881 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))]
8884 if (GET_CODE (operands[3]) == NE)
8886 if (which_alternative != 1)
8887 output_asm_insn (\"mov%D4\\t%0, %2\", operands);
8888 if (which_alternative != 0)
8889 output_asm_insn (\"mov%d4\\t%0, %1\", operands);
8892 if (which_alternative != 0)
8893 output_asm_insn (\"mov%D4\\t%0, %1\", operands);
8894 if (which_alternative != 1)
8895 output_asm_insn (\"mov%d4\\t%0, %2\", operands);
8898 [(set_attr "conds" "use")
8899 (set_attr_alternative "type"
8900 [(if_then_else (match_operand 2 "const_int_operand" "")
8901 (const_string "mov_imm")
8902 (const_string "mov_reg"))
8903 (if_then_else (match_operand 1 "const_int_operand" "")
8904 (const_string "mov_imm")
8905 (const_string "mov_reg"))
8906 (const_string "multiple")])
8907 (set_attr "length" "4,4,8")]
8910 (define_insn "*cond_arith"
8911 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
8912 (match_operator:SI 5 "shiftable_operator"
8913 [(match_operator:SI 4 "arm_comparison_operator"
8914 [(match_operand:SI 2 "s_register_operand" "r,r")
8915 (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])
8916 (match_operand:SI 1 "s_register_operand" "0,?r")]))
8917 (clobber (reg:CC CC_REGNUM))]
8920 if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx)
8921 return \"%i5\\t%0, %1, %2, lsr #31\";
8923 output_asm_insn (\"cmp\\t%2, %3\", operands);
8924 if (GET_CODE (operands[5]) == AND)
8925 output_asm_insn (\"mov%D4\\t%0, #0\", operands);
8926 else if (GET_CODE (operands[5]) == MINUS)
8927 output_asm_insn (\"rsb%D4\\t%0, %1, #0\", operands);
8928 else if (which_alternative != 0)
8929 output_asm_insn (\"mov%D4\\t%0, %1\", operands);
8930 return \"%i5%d4\\t%0, %1, #1\";
8932 [(set_attr "conds" "clob")
8933 (set_attr "length" "12")
8934 (set_attr "type" "multiple")]
8937 (define_insn "*cond_sub"
8938 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
8939 (minus:SI (match_operand:SI 1 "s_register_operand" "0,?r")
8940 (match_operator:SI 4 "arm_comparison_operator"
8941 [(match_operand:SI 2 "s_register_operand" "r,r")
8942 (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))
8943 (clobber (reg:CC CC_REGNUM))]
8946 output_asm_insn (\"cmp\\t%2, %3\", operands);
8947 if (which_alternative != 0)
8948 output_asm_insn (\"mov%D4\\t%0, %1\", operands);
8949 return \"sub%d4\\t%0, %1, #1\";
8951 [(set_attr "conds" "clob")
8952 (set_attr "length" "8,12")
8953 (set_attr "type" "multiple")]
8956 (define_insn "*cmp_ite0"
8957 [(set (match_operand 6 "dominant_cc_register" "")
8960 (match_operator 4 "arm_comparison_operator"
8961 [(match_operand:SI 0 "s_register_operand"
8962 "l,l,l,r,r,r,r,r,r")
8963 (match_operand:SI 1 "arm_add_operand"
8964 "lPy,lPy,lPy,rI,L,rI,L,rI,L")])
8965 (match_operator:SI 5 "arm_comparison_operator"
8966 [(match_operand:SI 2 "s_register_operand"
8967 "l,r,r,l,l,r,r,r,r")
8968 (match_operand:SI 3 "arm_add_operand"
8969 "lPy,rI,L,lPy,lPy,rI,rI,L,L")])
8975 static const char * const cmp1[NUM_OF_COND_CMP][2] =
8977 {\"cmp%d5\\t%0, %1\",
8978 \"cmp%d4\\t%2, %3\"},
8979 {\"cmn%d5\\t%0, #%n1\",
8980 \"cmp%d4\\t%2, %3\"},
8981 {\"cmp%d5\\t%0, %1\",
8982 \"cmn%d4\\t%2, #%n3\"},
8983 {\"cmn%d5\\t%0, #%n1\",
8984 \"cmn%d4\\t%2, #%n3\"}
8986 static const char * const cmp2[NUM_OF_COND_CMP][2] =
8991 \"cmn\\t%0, #%n1\"},
8992 {\"cmn\\t%2, #%n3\",
8994 {\"cmn\\t%2, #%n3\",
8997 static const char * const ite[2] =
9002 static const int cmp_idx[9] = {CMP_CMP, CMP_CMP, CMP_CMN,
9003 CMP_CMP, CMN_CMP, CMP_CMP,
9004 CMN_CMP, CMP_CMN, CMN_CMN};
9006 comparison_dominates_p (GET_CODE (operands[5]), GET_CODE (operands[4]));
9008 output_asm_insn (cmp2[cmp_idx[which_alternative]][swap], operands);
9009 if (TARGET_THUMB2) {
9010 output_asm_insn (ite[swap], operands);
9012 output_asm_insn (cmp1[cmp_idx[which_alternative]][swap], operands);
9015 [(set_attr "conds" "set")
9016 (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any")
9017 (set_attr "enabled_for_short_it" "yes,no,no,no,no,no,no,no,no")
9018 (set_attr "type" "multiple")
9019 (set_attr_alternative "length"
9025 (if_then_else (eq_attr "is_thumb" "no")
9028 (if_then_else (eq_attr "is_thumb" "no")
9031 (if_then_else (eq_attr "is_thumb" "no")
9034 (if_then_else (eq_attr "is_thumb" "no")
9039 (define_insn "*cmp_ite1"
9040 [(set (match_operand 6 "dominant_cc_register" "")
9043 (match_operator 4 "arm_comparison_operator"
9044 [(match_operand:SI 0 "s_register_operand"
9045 "l,l,l,r,r,r,r,r,r")
9046 (match_operand:SI 1 "arm_add_operand"
9047 "lPy,lPy,lPy,rI,L,rI,L,rI,L")])
9048 (match_operator:SI 5 "arm_comparison_operator"
9049 [(match_operand:SI 2 "s_register_operand"
9050 "l,r,r,l,l,r,r,r,r")
9051 (match_operand:SI 3 "arm_add_operand"
9052 "lPy,rI,L,lPy,lPy,rI,rI,L,L")])
9058 static const char * const cmp1[NUM_OF_COND_CMP][2] =
9062 {\"cmn\\t%0, #%n1\",
9065 \"cmn\\t%2, #%n3\"},
9066 {\"cmn\\t%0, #%n1\",
9069 static const char * const cmp2[NUM_OF_COND_CMP][2] =
9071 {\"cmp%d4\\t%2, %3\",
9072 \"cmp%D5\\t%0, %1\"},
9073 {\"cmp%d4\\t%2, %3\",
9074 \"cmn%D5\\t%0, #%n1\"},
9075 {\"cmn%d4\\t%2, #%n3\",
9076 \"cmp%D5\\t%0, %1\"},
9077 {\"cmn%d4\\t%2, #%n3\",
9078 \"cmn%D5\\t%0, #%n1\"}
9080 static const char * const ite[2] =
9085 static const int cmp_idx[9] = {CMP_CMP, CMP_CMP, CMP_CMN,
9086 CMP_CMP, CMN_CMP, CMP_CMP,
9087 CMN_CMP, CMP_CMN, CMN_CMN};
9089 comparison_dominates_p (GET_CODE (operands[5]),
9090 reverse_condition (GET_CODE (operands[4])));
9092 output_asm_insn (cmp1[cmp_idx[which_alternative]][swap], operands);
9093 if (TARGET_THUMB2) {
9094 output_asm_insn (ite[swap], operands);
9096 output_asm_insn (cmp2[cmp_idx[which_alternative]][swap], operands);
9099 [(set_attr "conds" "set")
9100 (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any")
9101 (set_attr "enabled_for_short_it" "yes,no,no,no,no,no,no,no,no")
9102 (set_attr_alternative "length"
9108 (if_then_else (eq_attr "is_thumb" "no")
9111 (if_then_else (eq_attr "is_thumb" "no")
9114 (if_then_else (eq_attr "is_thumb" "no")
9117 (if_then_else (eq_attr "is_thumb" "no")
9120 (set_attr "type" "multiple")]
9123 (define_insn "*cmp_and"
9124 [(set (match_operand 6 "dominant_cc_register" "")
9127 (match_operator 4 "arm_comparison_operator"
9128 [(match_operand:SI 0 "s_register_operand"
9129 "l,l,l,r,r,r,r,r,r,r")
9130 (match_operand:SI 1 "arm_add_operand"
9131 "lPy,lPy,lPy,rI,L,r,rI,L,rI,L")])
9132 (match_operator:SI 5 "arm_comparison_operator"
9133 [(match_operand:SI 2 "s_register_operand"
9134 "l,r,r,l,l,r,r,r,r,r")
9135 (match_operand:SI 3 "arm_add_operand"
9136 "lPy,rI,L,lPy,lPy,r,rI,rI,L,L")]))
9141 static const char *const cmp1[NUM_OF_COND_CMP][2] =
9143 {\"cmp%d5\\t%0, %1\",
9144 \"cmp%d4\\t%2, %3\"},
9145 {\"cmn%d5\\t%0, #%n1\",
9146 \"cmp%d4\\t%2, %3\"},
9147 {\"cmp%d5\\t%0, %1\",
9148 \"cmn%d4\\t%2, #%n3\"},
9149 {\"cmn%d5\\t%0, #%n1\",
9150 \"cmn%d4\\t%2, #%n3\"}
9152 static const char *const cmp2[NUM_OF_COND_CMP][2] =
9157 \"cmn\\t%0, #%n1\"},
9158 {\"cmn\\t%2, #%n3\",
9160 {\"cmn\\t%2, #%n3\",
9163 static const char *const ite[2] =
9168 static const int cmp_idx[] = {CMP_CMP, CMP_CMP, CMP_CMN,
9169 CMP_CMP, CMN_CMP, CMP_CMP,
9170 CMP_CMP, CMN_CMP, CMP_CMN,
9173 comparison_dominates_p (GET_CODE (operands[5]), GET_CODE (operands[4]));
9175 output_asm_insn (cmp2[cmp_idx[which_alternative]][swap], operands);
9176 if (TARGET_THUMB2) {
9177 output_asm_insn (ite[swap], operands);
9179 output_asm_insn (cmp1[cmp_idx[which_alternative]][swap], operands);
9182 [(set_attr "conds" "set")
9183 (set_attr "predicable" "no")
9184 (set_attr "arch" "t2,t2,t2,t2,t2,t2,any,any,any,any")
9185 (set_attr "enabled_for_short_it" "yes,no,no,no,no,yes,no,no,no,no")
9186 (set_attr_alternative "length"
9193 (if_then_else (eq_attr "is_thumb" "no")
9196 (if_then_else (eq_attr "is_thumb" "no")
9199 (if_then_else (eq_attr "is_thumb" "no")
9202 (if_then_else (eq_attr "is_thumb" "no")
9205 (set_attr "type" "multiple")]
9208 (define_insn "*cmp_ior"
9209 [(set (match_operand 6 "dominant_cc_register" "")
9212 (match_operator 4 "arm_comparison_operator"
9213 [(match_operand:SI 0 "s_register_operand"
9214 "l,l,l,r,r,r,r,r,r,r")
9215 (match_operand:SI 1 "arm_add_operand"
9216 "lPy,lPy,lPy,rI,L,r,rI,L,rI,L")])
9217 (match_operator:SI 5 "arm_comparison_operator"
9218 [(match_operand:SI 2 "s_register_operand"
9219 "l,r,r,l,l,r,r,r,r,r")
9220 (match_operand:SI 3 "arm_add_operand"
9221 "lPy,rI,L,lPy,lPy,r,rI,rI,L,L")]))
9226 static const char *const cmp1[NUM_OF_COND_CMP][2] =
9230 {\"cmn\\t%0, #%n1\",
9233 \"cmn\\t%2, #%n3\"},
9234 {\"cmn\\t%0, #%n1\",
9237 static const char *const cmp2[NUM_OF_COND_CMP][2] =
9239 {\"cmp%D4\\t%2, %3\",
9240 \"cmp%D5\\t%0, %1\"},
9241 {\"cmp%D4\\t%2, %3\",
9242 \"cmn%D5\\t%0, #%n1\"},
9243 {\"cmn%D4\\t%2, #%n3\",
9244 \"cmp%D5\\t%0, %1\"},
9245 {\"cmn%D4\\t%2, #%n3\",
9246 \"cmn%D5\\t%0, #%n1\"}
9248 static const char *const ite[2] =
9253 static const int cmp_idx[] = {CMP_CMP, CMP_CMP, CMP_CMN,
9254 CMP_CMP, CMN_CMP, CMP_CMP,
9255 CMP_CMP, CMN_CMP, CMP_CMN,
9258 comparison_dominates_p (GET_CODE (operands[5]), GET_CODE (operands[4]));
9260 output_asm_insn (cmp1[cmp_idx[which_alternative]][swap], operands);
9261 if (TARGET_THUMB2) {
9262 output_asm_insn (ite[swap], operands);
9264 output_asm_insn (cmp2[cmp_idx[which_alternative]][swap], operands);
9268 [(set_attr "conds" "set")
9269 (set_attr "arch" "t2,t2,t2,t2,t2,t2,any,any,any,any")
9270 (set_attr "enabled_for_short_it" "yes,no,no,no,no,yes,no,no,no,no")
9271 (set_attr_alternative "length"
9278 (if_then_else (eq_attr "is_thumb" "no")
9281 (if_then_else (eq_attr "is_thumb" "no")
9284 (if_then_else (eq_attr "is_thumb" "no")
9287 (if_then_else (eq_attr "is_thumb" "no")
9290 (set_attr "type" "multiple")]
9293 (define_insn_and_split "*ior_scc_scc"
9294 [(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts")
9295 (ior:SI (match_operator:SI 3 "arm_comparison_operator"
9296 [(match_operand:SI 1 "s_register_operand" "l,r")
9297 (match_operand:SI 2 "arm_add_operand" "lPy,rIL")])
9298 (match_operator:SI 6 "arm_comparison_operator"
9299 [(match_operand:SI 4 "s_register_operand" "l,r")
9300 (match_operand:SI 5 "arm_add_operand" "lPy,rIL")])))
9301 (clobber (reg:CC CC_REGNUM))]
9303 && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_OR_Y)
9306 "TARGET_32BIT && reload_completed"
9310 (match_op_dup 3 [(match_dup 1) (match_dup 2)])
9311 (match_op_dup 6 [(match_dup 4) (match_dup 5)]))
9313 (set (match_dup 0) (ne:SI (match_dup 7) (const_int 0)))]
9315 = gen_rtx_REG (arm_select_dominance_cc_mode (operands[3], operands[6],
9318 [(set_attr "conds" "clob")
9319 (set_attr "enabled_for_short_it" "yes,no")
9320 (set_attr "length" "16")
9321 (set_attr "type" "multiple")]
9324 ; If the above pattern is followed by a CMP insn, then the compare is
9325 ; redundant, since we can rework the conditional instruction that follows.
9326 (define_insn_and_split "*ior_scc_scc_cmp"
9327 [(set (match_operand 0 "dominant_cc_register" "")
9328 (compare (ior:SI (match_operator:SI 3 "arm_comparison_operator"
9329 [(match_operand:SI 1 "s_register_operand" "l,r")
9330 (match_operand:SI 2 "arm_add_operand" "lPy,rIL")])
9331 (match_operator:SI 6 "arm_comparison_operator"
9332 [(match_operand:SI 4 "s_register_operand" "l,r")
9333 (match_operand:SI 5 "arm_add_operand" "lPy,rIL")]))
9335 (set (match_operand:SI 7 "s_register_operand" "=Ts,Ts")
9336 (ior:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])
9337 (match_op_dup 6 [(match_dup 4) (match_dup 5)])))]
9340 "TARGET_32BIT && reload_completed"
9344 (match_op_dup 3 [(match_dup 1) (match_dup 2)])
9345 (match_op_dup 6 [(match_dup 4) (match_dup 5)]))
9347 (set (match_dup 7) (ne:SI (match_dup 0) (const_int 0)))]
9349 [(set_attr "conds" "set")
9350 (set_attr "enabled_for_short_it" "yes,no")
9351 (set_attr "length" "16")
9352 (set_attr "type" "multiple")]
9355 (define_insn_and_split "*and_scc_scc"
9356 [(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts")
9357 (and:SI (match_operator:SI 3 "arm_comparison_operator"
9358 [(match_operand:SI 1 "s_register_operand" "l,r")
9359 (match_operand:SI 2 "arm_add_operand" "lPy,rIL")])
9360 (match_operator:SI 6 "arm_comparison_operator"
9361 [(match_operand:SI 4 "s_register_operand" "l,r")
9362 (match_operand:SI 5 "arm_add_operand" "lPy,rIL")])))
9363 (clobber (reg:CC CC_REGNUM))]
9365 && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y)
9368 "TARGET_32BIT && reload_completed
9369 && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y)
9374 (match_op_dup 3 [(match_dup 1) (match_dup 2)])
9375 (match_op_dup 6 [(match_dup 4) (match_dup 5)]))
9377 (set (match_dup 0) (ne:SI (match_dup 7) (const_int 0)))]
9379 = gen_rtx_REG (arm_select_dominance_cc_mode (operands[3], operands[6],
9382 [(set_attr "conds" "clob")
9383 (set_attr "enabled_for_short_it" "yes,no")
9384 (set_attr "length" "16")
9385 (set_attr "type" "multiple")]
9388 ; If the above pattern is followed by a CMP insn, then the compare is
9389 ; redundant, since we can rework the conditional instruction that follows.
9390 (define_insn_and_split "*and_scc_scc_cmp"
9391 [(set (match_operand 0 "dominant_cc_register" "")
9392 (compare (and:SI (match_operator:SI 3 "arm_comparison_operator"
9393 [(match_operand:SI 1 "s_register_operand" "l,r")
9394 (match_operand:SI 2 "arm_add_operand" "lPy,rIL")])
9395 (match_operator:SI 6 "arm_comparison_operator"
9396 [(match_operand:SI 4 "s_register_operand" "l,r")
9397 (match_operand:SI 5 "arm_add_operand" "lPy,rIL")]))
9399 (set (match_operand:SI 7 "s_register_operand" "=Ts,Ts")
9400 (and:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])
9401 (match_op_dup 6 [(match_dup 4) (match_dup 5)])))]
9404 "TARGET_32BIT && reload_completed"
9408 (match_op_dup 3 [(match_dup 1) (match_dup 2)])
9409 (match_op_dup 6 [(match_dup 4) (match_dup 5)]))
9411 (set (match_dup 7) (ne:SI (match_dup 0) (const_int 0)))]
9413 [(set_attr "conds" "set")
9414 (set_attr "enabled_for_short_it" "yes,no")
9415 (set_attr "length" "16")
9416 (set_attr "type" "multiple")]
9419 ;; If there is no dominance in the comparison, then we can still save an
9420 ;; instruction in the AND case, since we can know that the second compare
9421 ;; need only zero the value if false (if true, then the value is already
9423 (define_insn_and_split "*and_scc_scc_nodom"
9424 [(set (match_operand:SI 0 "s_register_operand" "=&Ts,&Ts,&Ts")
9425 (and:SI (match_operator:SI 3 "arm_comparison_operator"
9426 [(match_operand:SI 1 "s_register_operand" "r,r,0")
9427 (match_operand:SI 2 "arm_add_operand" "rIL,0,rIL")])
9428 (match_operator:SI 6 "arm_comparison_operator"
9429 [(match_operand:SI 4 "s_register_operand" "r,r,r")
9430 (match_operand:SI 5 "arm_add_operand" "rIL,rIL,rIL")])))
9431 (clobber (reg:CC CC_REGNUM))]
9433 && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y)
9436 "TARGET_32BIT && reload_completed"
9437 [(parallel [(set (match_dup 0)
9438 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
9439 (clobber (reg:CC CC_REGNUM))])
9440 (set (match_dup 7) (match_op_dup 8 [(match_dup 4) (match_dup 5)]))
9442 (if_then_else:SI (match_op_dup 6 [(match_dup 7) (const_int 0)])
9445 "operands[7] = gen_rtx_REG (SELECT_CC_MODE (GET_CODE (operands[6]),
9446 operands[4], operands[5]),
9448 operands[8] = gen_rtx_COMPARE (GET_MODE (operands[7]), operands[4],
9450 [(set_attr "conds" "clob")
9451 (set_attr "length" "20")
9452 (set_attr "type" "multiple")]
9456 [(set (reg:CC_NOOV CC_REGNUM)
9457 (compare:CC_NOOV (ior:SI
9458 (and:SI (match_operand:SI 0 "s_register_operand" "")
9460 (match_operator:SI 1 "arm_comparison_operator"
9461 [(match_operand:SI 2 "s_register_operand" "")
9462 (match_operand:SI 3 "arm_add_operand" "")]))
9464 (clobber (match_operand:SI 4 "s_register_operand" ""))]
9467 (ior:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
9469 (set (reg:CC_NOOV CC_REGNUM)
9470 (compare:CC_NOOV (and:SI (match_dup 4) (const_int 1))
9475 [(set (reg:CC_NOOV CC_REGNUM)
9476 (compare:CC_NOOV (ior:SI
9477 (match_operator:SI 1 "arm_comparison_operator"
9478 [(match_operand:SI 2 "s_register_operand" "")
9479 (match_operand:SI 3 "arm_add_operand" "")])
9480 (and:SI (match_operand:SI 0 "s_register_operand" "")
9483 (clobber (match_operand:SI 4 "s_register_operand" ""))]
9486 (ior:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
9488 (set (reg:CC_NOOV CC_REGNUM)
9489 (compare:CC_NOOV (and:SI (match_dup 4) (const_int 1))
9492 ;; ??? The conditional patterns above need checking for Thumb-2 usefulness
9494 (define_insn_and_split "*negscc"
9495 [(set (match_operand:SI 0 "s_register_operand" "=r")
9496 (neg:SI (match_operator 3 "arm_comparison_operator"
9497 [(match_operand:SI 1 "s_register_operand" "r")
9498 (match_operand:SI 2 "arm_rhs_operand" "rI")])))
9499 (clobber (reg:CC CC_REGNUM))]
9502 "&& reload_completed"
9505 rtx cc_reg = gen_rtx_REG (CCmode, CC_REGNUM);
9507 if (GET_CODE (operands[3]) == LT && operands[2] == const0_rtx)
9509 /* Emit mov\\t%0, %1, asr #31 */
9510 emit_insn (gen_rtx_SET (operands[0],
9511 gen_rtx_ASHIFTRT (SImode,
9516 else if (GET_CODE (operands[3]) == NE)
9518 /* Emit subs\\t%0, %1, %2\;mvnne\\t%0, #0 */
9519 if (CONST_INT_P (operands[2]))
9520 emit_insn (gen_cmpsi2_addneg (operands[0], operands[1], operands[2],
9521 gen_int_mode (-INTVAL (operands[2]),
9524 emit_insn (gen_subsi3_compare (operands[0], operands[1], operands[2]));
9526 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
9530 gen_rtx_SET (operands[0],
9536 /* Emit: cmp\\t%1, %2\;mov%D3\\t%0, #0\;mvn%d3\\t%0, #0 */
9537 emit_insn (gen_rtx_SET (cc_reg,
9538 gen_rtx_COMPARE (CCmode, operands[1], operands[2])));
9539 enum rtx_code rc = GET_CODE (operands[3]);
9541 rc = reverse_condition (rc);
9542 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
9547 gen_rtx_SET (operands[0], const0_rtx)));
9548 rc = GET_CODE (operands[3]);
9549 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
9554 gen_rtx_SET (operands[0],
9560 [(set_attr "conds" "clob")
9561 (set_attr "length" "12")
9562 (set_attr "type" "multiple")]
9565 (define_insn_and_split "movcond_addsi"
9566 [(set (match_operand:SI 0 "s_register_operand" "=r,l,r")
9568 (match_operator 5 "comparison_operator"
9569 [(plus:SI (match_operand:SI 3 "s_register_operand" "r,r,r")
9570 (match_operand:SI 4 "arm_add_operand" "rIL,rIL,rIL"))
9572 (match_operand:SI 1 "arm_rhs_operand" "rI,rPy,r")
9573 (match_operand:SI 2 "arm_rhs_operand" "rI,rPy,r")))
9574 (clobber (reg:CC CC_REGNUM))]
9577 "&& reload_completed"
9578 [(set (reg:CC_NOOV CC_REGNUM)
9580 (plus:SI (match_dup 3)
9583 (set (match_dup 0) (match_dup 1))
9584 (cond_exec (match_dup 6)
9585 (set (match_dup 0) (match_dup 2)))]
9588 machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[5]),
9589 operands[3], operands[4]);
9590 enum rtx_code rc = GET_CODE (operands[5]);
9591 operands[6] = gen_rtx_REG (mode, CC_REGNUM);
9592 gcc_assert (!(mode == CCFPmode || mode == CCFPEmode));
9593 if (!REG_P (operands[2]) || REGNO (operands[2]) != REGNO (operands[0]))
9594 rc = reverse_condition (rc);
9596 std::swap (operands[1], operands[2]);
9598 operands[6] = gen_rtx_fmt_ee (rc, VOIDmode, operands[6], const0_rtx);
9601 [(set_attr "conds" "clob")
9602 (set_attr "enabled_for_short_it" "no,yes,yes")
9603 (set_attr "type" "multiple")]
9606 (define_insn "movcond"
9607 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
9609 (match_operator 5 "arm_comparison_operator"
9610 [(match_operand:SI 3 "s_register_operand" "r,r,r")
9611 (match_operand:SI 4 "arm_add_operand" "rIL,rIL,rIL")])
9612 (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI")
9613 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
9614 (clobber (reg:CC CC_REGNUM))]
9617 if (GET_CODE (operands[5]) == LT
9618 && (operands[4] == const0_rtx))
9620 if (which_alternative != 1 && REG_P (operands[1]))
9622 if (operands[2] == const0_rtx)
9623 return \"and\\t%0, %1, %3, asr #31\";
9624 return \"ands\\t%0, %1, %3, asr #32\;movcc\\t%0, %2\";
9626 else if (which_alternative != 0 && REG_P (operands[2]))
9628 if (operands[1] == const0_rtx)
9629 return \"bic\\t%0, %2, %3, asr #31\";
9630 return \"bics\\t%0, %2, %3, asr #32\;movcs\\t%0, %1\";
9632 /* The only case that falls through to here is when both ops 1 & 2
9636 if (GET_CODE (operands[5]) == GE
9637 && (operands[4] == const0_rtx))
9639 if (which_alternative != 1 && REG_P (operands[1]))
9641 if (operands[2] == const0_rtx)
9642 return \"bic\\t%0, %1, %3, asr #31\";
9643 return \"bics\\t%0, %1, %3, asr #32\;movcs\\t%0, %2\";
9645 else if (which_alternative != 0 && REG_P (operands[2]))
9647 if (operands[1] == const0_rtx)
9648 return \"and\\t%0, %2, %3, asr #31\";
9649 return \"ands\\t%0, %2, %3, asr #32\;movcc\\t%0, %1\";
9651 /* The only case that falls through to here is when both ops 1 & 2
9654 if (CONST_INT_P (operands[4])
9655 && !const_ok_for_arm (INTVAL (operands[4])))
9656 output_asm_insn (\"cmn\\t%3, #%n4\", operands);
9658 output_asm_insn (\"cmp\\t%3, %4\", operands);
9659 if (which_alternative != 0)
9660 output_asm_insn (\"mov%d5\\t%0, %1\", operands);
9661 if (which_alternative != 1)
9662 output_asm_insn (\"mov%D5\\t%0, %2\", operands);
9665 [(set_attr "conds" "clob")
9666 (set_attr "length" "8,8,12")
9667 (set_attr "type" "multiple")]
9670 ;; ??? The patterns below need checking for Thumb-2 usefulness.
9672 (define_insn "*ifcompare_plus_move"
9673 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
9674 (if_then_else:SI (match_operator 6 "arm_comparison_operator"
9675 [(match_operand:SI 4 "s_register_operand" "r,r")
9676 (match_operand:SI 5 "arm_add_operand" "rIL,rIL")])
9678 (match_operand:SI 2 "s_register_operand" "r,r")
9679 (match_operand:SI 3 "arm_add_operand" "rIL,rIL"))
9680 (match_operand:SI 1 "arm_rhs_operand" "0,?rI")))
9681 (clobber (reg:CC CC_REGNUM))]
9684 [(set_attr "conds" "clob")
9685 (set_attr "length" "8,12")
9686 (set_attr "type" "multiple")]
9689 (define_insn "*if_plus_move"
9690 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r")
9692 (match_operator 4 "arm_comparison_operator"
9693 [(match_operand 5 "cc_register" "") (const_int 0)])
9695 (match_operand:SI 2 "s_register_operand" "r,r,r,r")
9696 (match_operand:SI 3 "arm_add_operand" "rI,L,rI,L"))
9697 (match_operand:SI 1 "arm_rhs_operand" "0,0,?rI,?rI")))]
9701 sub%d4\\t%0, %2, #%n3
9702 add%d4\\t%0, %2, %3\;mov%D4\\t%0, %1
9703 sub%d4\\t%0, %2, #%n3\;mov%D4\\t%0, %1"
9704 [(set_attr "conds" "use")
9705 (set_attr "length" "4,4,8,8")
9706 (set_attr_alternative "type"
9707 [(if_then_else (match_operand 3 "const_int_operand" "")
9708 (const_string "alu_imm" )
9709 (const_string "alu_sreg"))
9710 (const_string "alu_imm")
9711 (const_string "multiple")
9712 (const_string "multiple")])]
9715 (define_insn "*ifcompare_move_plus"
9716 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
9717 (if_then_else:SI (match_operator 6 "arm_comparison_operator"
9718 [(match_operand:SI 4 "s_register_operand" "r,r")
9719 (match_operand:SI 5 "arm_add_operand" "rIL,rIL")])
9720 (match_operand:SI 1 "arm_rhs_operand" "0,?rI")
9722 (match_operand:SI 2 "s_register_operand" "r,r")
9723 (match_operand:SI 3 "arm_add_operand" "rIL,rIL"))))
9724 (clobber (reg:CC CC_REGNUM))]
9727 [(set_attr "conds" "clob")
9728 (set_attr "length" "8,12")
9729 (set_attr "type" "multiple")]
9732 (define_insn "*if_move_plus"
9733 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r")
9735 (match_operator 4 "arm_comparison_operator"
9736 [(match_operand 5 "cc_register" "") (const_int 0)])
9737 (match_operand:SI 1 "arm_rhs_operand" "0,0,?rI,?rI")
9739 (match_operand:SI 2 "s_register_operand" "r,r,r,r")
9740 (match_operand:SI 3 "arm_add_operand" "rI,L,rI,L"))))]
9744 sub%D4\\t%0, %2, #%n3
9745 add%D4\\t%0, %2, %3\;mov%d4\\t%0, %1
9746 sub%D4\\t%0, %2, #%n3\;mov%d4\\t%0, %1"
9747 [(set_attr "conds" "use")
9748 (set_attr "length" "4,4,8,8")
9749 (set_attr_alternative "type"
9750 [(if_then_else (match_operand 3 "const_int_operand" "")
9751 (const_string "alu_imm" )
9752 (const_string "alu_sreg"))
9753 (const_string "alu_imm")
9754 (const_string "multiple")
9755 (const_string "multiple")])]
9758 (define_insn "*ifcompare_arith_arith"
9759 [(set (match_operand:SI 0 "s_register_operand" "=r")
9760 (if_then_else:SI (match_operator 9 "arm_comparison_operator"
9761 [(match_operand:SI 5 "s_register_operand" "r")
9762 (match_operand:SI 6 "arm_add_operand" "rIL")])
9763 (match_operator:SI 8 "shiftable_operator"
9764 [(match_operand:SI 1 "s_register_operand" "r")
9765 (match_operand:SI 2 "arm_rhs_operand" "rI")])
9766 (match_operator:SI 7 "shiftable_operator"
9767 [(match_operand:SI 3 "s_register_operand" "r")
9768 (match_operand:SI 4 "arm_rhs_operand" "rI")])))
9769 (clobber (reg:CC CC_REGNUM))]
9772 [(set_attr "conds" "clob")
9773 (set_attr "length" "12")
9774 (set_attr "type" "multiple")]
9777 (define_insn "*if_arith_arith"
9778 [(set (match_operand:SI 0 "s_register_operand" "=r")
9779 (if_then_else:SI (match_operator 5 "arm_comparison_operator"
9780 [(match_operand 8 "cc_register" "") (const_int 0)])
9781 (match_operator:SI 6 "shiftable_operator"
9782 [(match_operand:SI 1 "s_register_operand" "r")
9783 (match_operand:SI 2 "arm_rhs_operand" "rI")])
9784 (match_operator:SI 7 "shiftable_operator"
9785 [(match_operand:SI 3 "s_register_operand" "r")
9786 (match_operand:SI 4 "arm_rhs_operand" "rI")])))]
9788 "%I6%d5\\t%0, %1, %2\;%I7%D5\\t%0, %3, %4"
9789 [(set_attr "conds" "use")
9790 (set_attr "length" "8")
9791 (set_attr "type" "multiple")]
9794 (define_insn "*ifcompare_arith_move"
9795 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
9796 (if_then_else:SI (match_operator 6 "arm_comparison_operator"
9797 [(match_operand:SI 2 "s_register_operand" "r,r")
9798 (match_operand:SI 3 "arm_add_operand" "rIL,rIL")])
9799 (match_operator:SI 7 "shiftable_operator"
9800 [(match_operand:SI 4 "s_register_operand" "r,r")
9801 (match_operand:SI 5 "arm_rhs_operand" "rI,rI")])
9802 (match_operand:SI 1 "arm_rhs_operand" "0,?rI")))
9803 (clobber (reg:CC CC_REGNUM))]
9806 /* If we have an operation where (op x 0) is the identity operation and
9807 the conditional operator is LT or GE and we are comparing against zero and
9808 everything is in registers then we can do this in two instructions. */
9809 if (operands[3] == const0_rtx
9810 && GET_CODE (operands[7]) != AND
9811 && REG_P (operands[5])
9812 && REG_P (operands[1])
9813 && REGNO (operands[1]) == REGNO (operands[4])
9814 && REGNO (operands[4]) != REGNO (operands[0]))
9816 if (GET_CODE (operands[6]) == LT)
9817 return \"and\\t%0, %5, %2, asr #31\;%I7\\t%0, %4, %0\";
9818 else if (GET_CODE (operands[6]) == GE)
9819 return \"bic\\t%0, %5, %2, asr #31\;%I7\\t%0, %4, %0\";
9821 if (CONST_INT_P (operands[3])
9822 && !const_ok_for_arm (INTVAL (operands[3])))
9823 output_asm_insn (\"cmn\\t%2, #%n3\", operands);
9825 output_asm_insn (\"cmp\\t%2, %3\", operands);
9826 output_asm_insn (\"%I7%d6\\t%0, %4, %5\", operands);
9827 if (which_alternative != 0)
9828 return \"mov%D6\\t%0, %1\";
9831 [(set_attr "conds" "clob")
9832 (set_attr "length" "8,12")
9833 (set_attr "type" "multiple")]
9836 (define_insn "*if_arith_move"
9837 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
9838 (if_then_else:SI (match_operator 4 "arm_comparison_operator"
9839 [(match_operand 6 "cc_register" "") (const_int 0)])
9840 (match_operator:SI 5 "shiftable_operator"
9841 [(match_operand:SI 2 "s_register_operand" "r,r")
9842 (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])
9843 (match_operand:SI 1 "arm_rhs_operand" "0,?rI")))]
9847 %I5%d4\\t%0, %2, %3\;mov%D4\\t%0, %1"
9848 [(set_attr "conds" "use")
9849 (set_attr "length" "4,8")
9850 (set_attr_alternative "type"
9851 [(if_then_else (match_operand 3 "const_int_operand" "")
9852 (const_string "alu_shift_imm" )
9853 (const_string "alu_shift_reg"))
9854 (const_string "multiple")])]
9857 (define_insn "*ifcompare_move_arith"
9858 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
9859 (if_then_else:SI (match_operator 6 "arm_comparison_operator"
9860 [(match_operand:SI 4 "s_register_operand" "r,r")
9861 (match_operand:SI 5 "arm_add_operand" "rIL,rIL")])
9862 (match_operand:SI 1 "arm_rhs_operand" "0,?rI")
9863 (match_operator:SI 7 "shiftable_operator"
9864 [(match_operand:SI 2 "s_register_operand" "r,r")
9865 (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))
9866 (clobber (reg:CC CC_REGNUM))]
9869 /* If we have an operation where (op x 0) is the identity operation and
9870 the conditional operator is LT or GE and we are comparing against zero and
9871 everything is in registers then we can do this in two instructions */
9872 if (operands[5] == const0_rtx
9873 && GET_CODE (operands[7]) != AND
9874 && REG_P (operands[3])
9875 && REG_P (operands[1])
9876 && REGNO (operands[1]) == REGNO (operands[2])
9877 && REGNO (operands[2]) != REGNO (operands[0]))
9879 if (GET_CODE (operands[6]) == GE)
9880 return \"and\\t%0, %3, %4, asr #31\;%I7\\t%0, %2, %0\";
9881 else if (GET_CODE (operands[6]) == LT)
9882 return \"bic\\t%0, %3, %4, asr #31\;%I7\\t%0, %2, %0\";
9885 if (CONST_INT_P (operands[5])
9886 && !const_ok_for_arm (INTVAL (operands[5])))
9887 output_asm_insn (\"cmn\\t%4, #%n5\", operands);
9889 output_asm_insn (\"cmp\\t%4, %5\", operands);
9891 if (which_alternative != 0)
9892 output_asm_insn (\"mov%d6\\t%0, %1\", operands);
9893 return \"%I7%D6\\t%0, %2, %3\";
9895 [(set_attr "conds" "clob")
9896 (set_attr "length" "8,12")
9897 (set_attr "type" "multiple")]
9900 (define_insn "*if_move_arith"
9901 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
9903 (match_operator 4 "arm_comparison_operator"
9904 [(match_operand 6 "cc_register" "") (const_int 0)])
9905 (match_operand:SI 1 "arm_rhs_operand" "0,?rI")
9906 (match_operator:SI 5 "shiftable_operator"
9907 [(match_operand:SI 2 "s_register_operand" "r,r")
9908 (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))]
9912 %I5%D4\\t%0, %2, %3\;mov%d4\\t%0, %1"
9913 [(set_attr "conds" "use")
9914 (set_attr "length" "4,8")
9915 (set_attr_alternative "type"
9916 [(if_then_else (match_operand 3 "const_int_operand" "")
9917 (const_string "alu_shift_imm" )
9918 (const_string "alu_shift_reg"))
9919 (const_string "multiple")])]
9922 (define_insn "*ifcompare_move_not"
9923 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
9925 (match_operator 5 "arm_comparison_operator"
9926 [(match_operand:SI 3 "s_register_operand" "r,r")
9927 (match_operand:SI 4 "arm_add_operand" "rIL,rIL")])
9928 (match_operand:SI 1 "arm_not_operand" "0,?rIK")
9930 (match_operand:SI 2 "s_register_operand" "r,r"))))
9931 (clobber (reg:CC CC_REGNUM))]
9934 [(set_attr "conds" "clob")
9935 (set_attr "length" "8,12")
9936 (set_attr "type" "multiple")]
9939 (define_insn "*if_move_not"
9940 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
9942 (match_operator 4 "arm_comparison_operator"
9943 [(match_operand 3 "cc_register" "") (const_int 0)])
9944 (match_operand:SI 1 "arm_not_operand" "0,?rI,K")
9945 (not:SI (match_operand:SI 2 "s_register_operand" "r,r,r"))))]
9949 mov%d4\\t%0, %1\;mvn%D4\\t%0, %2
9950 mvn%d4\\t%0, #%B1\;mvn%D4\\t%0, %2"
9951 [(set_attr "conds" "use")
9952 (set_attr "type" "mvn_reg")
9953 (set_attr "length" "4,8,8")
9954 (set_attr "type" "mvn_reg,multiple,multiple")]
9957 (define_insn "*ifcompare_not_move"
9958 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
9960 (match_operator 5 "arm_comparison_operator"
9961 [(match_operand:SI 3 "s_register_operand" "r,r")
9962 (match_operand:SI 4 "arm_add_operand" "rIL,rIL")])
9964 (match_operand:SI 2 "s_register_operand" "r,r"))
9965 (match_operand:SI 1 "arm_not_operand" "0,?rIK")))
9966 (clobber (reg:CC CC_REGNUM))]
9969 [(set_attr "conds" "clob")
9970 (set_attr "length" "8,12")
9971 (set_attr "type" "multiple")]
9974 (define_insn "*if_not_move"
9975 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
9977 (match_operator 4 "arm_comparison_operator"
9978 [(match_operand 3 "cc_register" "") (const_int 0)])
9979 (not:SI (match_operand:SI 2 "s_register_operand" "r,r,r"))
9980 (match_operand:SI 1 "arm_not_operand" "0,?rI,K")))]
9984 mov%D4\\t%0, %1\;mvn%d4\\t%0, %2
9985 mvn%D4\\t%0, #%B1\;mvn%d4\\t%0, %2"
9986 [(set_attr "conds" "use")
9987 (set_attr "type" "mvn_reg,multiple,multiple")
9988 (set_attr "length" "4,8,8")]
9991 (define_insn "*ifcompare_shift_move"
9992 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
9994 (match_operator 6 "arm_comparison_operator"
9995 [(match_operand:SI 4 "s_register_operand" "r,r")
9996 (match_operand:SI 5 "arm_add_operand" "rIL,rIL")])
9997 (match_operator:SI 7 "shift_operator"
9998 [(match_operand:SI 2 "s_register_operand" "r,r")
9999 (match_operand:SI 3 "arm_rhs_operand" "rM,rM")])
10000 (match_operand:SI 1 "arm_not_operand" "0,?rIK")))
10001 (clobber (reg:CC CC_REGNUM))]
10004 [(set_attr "conds" "clob")
10005 (set_attr "length" "8,12")
10006 (set_attr "type" "multiple")]
10009 (define_insn "*if_shift_move"
10010 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
10012 (match_operator 5 "arm_comparison_operator"
10013 [(match_operand 6 "cc_register" "") (const_int 0)])
10014 (match_operator:SI 4 "shift_operator"
10015 [(match_operand:SI 2 "s_register_operand" "r,r,r")
10016 (match_operand:SI 3 "arm_rhs_operand" "rM,rM,rM")])
10017 (match_operand:SI 1 "arm_not_operand" "0,?rI,K")))]
10021 mov%D5\\t%0, %1\;mov%d5\\t%0, %2%S4
10022 mvn%D5\\t%0, #%B1\;mov%d5\\t%0, %2%S4"
10023 [(set_attr "conds" "use")
10024 (set_attr "shift" "2")
10025 (set_attr "length" "4,8,8")
10026 (set_attr_alternative "type"
10027 [(if_then_else (match_operand 3 "const_int_operand" "")
10028 (const_string "mov_shift" )
10029 (const_string "mov_shift_reg"))
10030 (const_string "multiple")
10031 (const_string "multiple")])]
10034 (define_insn "*ifcompare_move_shift"
10035 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
10037 (match_operator 6 "arm_comparison_operator"
10038 [(match_operand:SI 4 "s_register_operand" "r,r")
10039 (match_operand:SI 5 "arm_add_operand" "rIL,rIL")])
10040 (match_operand:SI 1 "arm_not_operand" "0,?rIK")
10041 (match_operator:SI 7 "shift_operator"
10042 [(match_operand:SI 2 "s_register_operand" "r,r")
10043 (match_operand:SI 3 "arm_rhs_operand" "rM,rM")])))
10044 (clobber (reg:CC CC_REGNUM))]
10047 [(set_attr "conds" "clob")
10048 (set_attr "length" "8,12")
10049 (set_attr "type" "multiple")]
10052 (define_insn "*if_move_shift"
10053 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
10055 (match_operator 5 "arm_comparison_operator"
10056 [(match_operand 6 "cc_register" "") (const_int 0)])
10057 (match_operand:SI 1 "arm_not_operand" "0,?rI,K")
10058 (match_operator:SI 4 "shift_operator"
10059 [(match_operand:SI 2 "s_register_operand" "r,r,r")
10060 (match_operand:SI 3 "arm_rhs_operand" "rM,rM,rM")])))]
10064 mov%d5\\t%0, %1\;mov%D5\\t%0, %2%S4
10065 mvn%d5\\t%0, #%B1\;mov%D5\\t%0, %2%S4"
10066 [(set_attr "conds" "use")
10067 (set_attr "shift" "2")
10068 (set_attr "length" "4,8,8")
10069 (set_attr_alternative "type"
10070 [(if_then_else (match_operand 3 "const_int_operand" "")
10071 (const_string "mov_shift" )
10072 (const_string "mov_shift_reg"))
10073 (const_string "multiple")
10074 (const_string "multiple")])]
10077 (define_insn "*ifcompare_shift_shift"
10078 [(set (match_operand:SI 0 "s_register_operand" "=r")
10080 (match_operator 7 "arm_comparison_operator"
10081 [(match_operand:SI 5 "s_register_operand" "r")
10082 (match_operand:SI 6 "arm_add_operand" "rIL")])
10083 (match_operator:SI 8 "shift_operator"
10084 [(match_operand:SI 1 "s_register_operand" "r")
10085 (match_operand:SI 2 "arm_rhs_operand" "rM")])
10086 (match_operator:SI 9 "shift_operator"
10087 [(match_operand:SI 3 "s_register_operand" "r")
10088 (match_operand:SI 4 "arm_rhs_operand" "rM")])))
10089 (clobber (reg:CC CC_REGNUM))]
10092 [(set_attr "conds" "clob")
10093 (set_attr "length" "12")
10094 (set_attr "type" "multiple")]
10097 (define_insn "*if_shift_shift"
10098 [(set (match_operand:SI 0 "s_register_operand" "=r")
10100 (match_operator 5 "arm_comparison_operator"
10101 [(match_operand 8 "cc_register" "") (const_int 0)])
10102 (match_operator:SI 6 "shift_operator"
10103 [(match_operand:SI 1 "s_register_operand" "r")
10104 (match_operand:SI 2 "arm_rhs_operand" "rM")])
10105 (match_operator:SI 7 "shift_operator"
10106 [(match_operand:SI 3 "s_register_operand" "r")
10107 (match_operand:SI 4 "arm_rhs_operand" "rM")])))]
10109 "mov%d5\\t%0, %1%S6\;mov%D5\\t%0, %3%S7"
10110 [(set_attr "conds" "use")
10111 (set_attr "shift" "1")
10112 (set_attr "length" "8")
10113 (set (attr "type") (if_then_else
10114 (and (match_operand 2 "const_int_operand" "")
10115 (match_operand 4 "const_int_operand" ""))
10116 (const_string "mov_shift")
10117 (const_string "mov_shift_reg")))]
10120 (define_insn "*ifcompare_not_arith"
10121 [(set (match_operand:SI 0 "s_register_operand" "=r")
10123 (match_operator 6 "arm_comparison_operator"
10124 [(match_operand:SI 4 "s_register_operand" "r")
10125 (match_operand:SI 5 "arm_add_operand" "rIL")])
10126 (not:SI (match_operand:SI 1 "s_register_operand" "r"))
10127 (match_operator:SI 7 "shiftable_operator"
10128 [(match_operand:SI 2 "s_register_operand" "r")
10129 (match_operand:SI 3 "arm_rhs_operand" "rI")])))
10130 (clobber (reg:CC CC_REGNUM))]
10133 [(set_attr "conds" "clob")
10134 (set_attr "length" "12")
10135 (set_attr "type" "multiple")]
10138 (define_insn "*if_not_arith"
10139 [(set (match_operand:SI 0 "s_register_operand" "=r")
10141 (match_operator 5 "arm_comparison_operator"
10142 [(match_operand 4 "cc_register" "") (const_int 0)])
10143 (not:SI (match_operand:SI 1 "s_register_operand" "r"))
10144 (match_operator:SI 6 "shiftable_operator"
10145 [(match_operand:SI 2 "s_register_operand" "r")
10146 (match_operand:SI 3 "arm_rhs_operand" "rI")])))]
10148 "mvn%d5\\t%0, %1\;%I6%D5\\t%0, %2, %3"
10149 [(set_attr "conds" "use")
10150 (set_attr "type" "mvn_reg")
10151 (set_attr "length" "8")]
10154 (define_insn "*ifcompare_arith_not"
10155 [(set (match_operand:SI 0 "s_register_operand" "=r")
10157 (match_operator 6 "arm_comparison_operator"
10158 [(match_operand:SI 4 "s_register_operand" "r")
10159 (match_operand:SI 5 "arm_add_operand" "rIL")])
10160 (match_operator:SI 7 "shiftable_operator"
10161 [(match_operand:SI 2 "s_register_operand" "r")
10162 (match_operand:SI 3 "arm_rhs_operand" "rI")])
10163 (not:SI (match_operand:SI 1 "s_register_operand" "r"))))
10164 (clobber (reg:CC CC_REGNUM))]
10167 [(set_attr "conds" "clob")
10168 (set_attr "length" "12")
10169 (set_attr "type" "multiple")]
10172 (define_insn "*if_arith_not"
10173 [(set (match_operand:SI 0 "s_register_operand" "=r")
10175 (match_operator 5 "arm_comparison_operator"
10176 [(match_operand 4 "cc_register" "") (const_int 0)])
10177 (match_operator:SI 6 "shiftable_operator"
10178 [(match_operand:SI 2 "s_register_operand" "r")
10179 (match_operand:SI 3 "arm_rhs_operand" "rI")])
10180 (not:SI (match_operand:SI 1 "s_register_operand" "r"))))]
10182 "mvn%D5\\t%0, %1\;%I6%d5\\t%0, %2, %3"
10183 [(set_attr "conds" "use")
10184 (set_attr "type" "multiple")
10185 (set_attr "length" "8")]
10188 (define_insn "*ifcompare_neg_move"
10189 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
10191 (match_operator 5 "arm_comparison_operator"
10192 [(match_operand:SI 3 "s_register_operand" "r,r")
10193 (match_operand:SI 4 "arm_add_operand" "rIL,rIL")])
10194 (neg:SI (match_operand:SI 2 "s_register_operand" "r,r"))
10195 (match_operand:SI 1 "arm_not_operand" "0,?rIK")))
10196 (clobber (reg:CC CC_REGNUM))]
10199 [(set_attr "conds" "clob")
10200 (set_attr "length" "8,12")
10201 (set_attr "type" "multiple")]
10204 (define_insn_and_split "*if_neg_move"
10205 [(set (match_operand:SI 0 "s_register_operand" "=l,r")
10207 (match_operator 4 "arm_comparison_operator"
10208 [(match_operand 3 "cc_register" "") (const_int 0)])
10209 (neg:SI (match_operand:SI 2 "s_register_operand" "l,r"))
10210 (match_operand:SI 1 "s_register_operand" "0,0")))]
10213 "&& reload_completed"
10214 [(cond_exec (match_op_dup 4 [(match_dup 3) (const_int 0)])
10215 (set (match_dup 0) (neg:SI (match_dup 2))))]
10217 [(set_attr "conds" "use")
10218 (set_attr "length" "4")
10219 (set_attr "arch" "t2,32")
10220 (set_attr "enabled_for_short_it" "yes,no")
10221 (set_attr "type" "logic_shift_imm")]
10224 (define_insn "*ifcompare_move_neg"
10225 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
10227 (match_operator 5 "arm_comparison_operator"
10228 [(match_operand:SI 3 "s_register_operand" "r,r")
10229 (match_operand:SI 4 "arm_add_operand" "rIL,rIL")])
10230 (match_operand:SI 1 "arm_not_operand" "0,?rIK")
10231 (neg:SI (match_operand:SI 2 "s_register_operand" "r,r"))))
10232 (clobber (reg:CC CC_REGNUM))]
10235 [(set_attr "conds" "clob")
10236 (set_attr "length" "8,12")
10237 (set_attr "type" "multiple")]
10240 (define_insn_and_split "*if_move_neg"
10241 [(set (match_operand:SI 0 "s_register_operand" "=l,r")
10243 (match_operator 4 "arm_comparison_operator"
10244 [(match_operand 3 "cc_register" "") (const_int 0)])
10245 (match_operand:SI 1 "s_register_operand" "0,0")
10246 (neg:SI (match_operand:SI 2 "s_register_operand" "l,r"))))]
10249 "&& reload_completed"
10250 [(cond_exec (match_dup 5)
10251 (set (match_dup 0) (neg:SI (match_dup 2))))]
10253 machine_mode mode = GET_MODE (operands[3]);
10254 rtx_code rc = GET_CODE (operands[4]);
10256 if (mode == CCFPmode || mode == CCFPEmode)
10257 rc = reverse_condition_maybe_unordered (rc);
10259 rc = reverse_condition (rc);
10261 operands[5] = gen_rtx_fmt_ee (rc, VOIDmode, operands[3], const0_rtx);
10263 [(set_attr "conds" "use")
10264 (set_attr "length" "4")
10265 (set_attr "arch" "t2,32")
10266 (set_attr "enabled_for_short_it" "yes,no")
10267 (set_attr "type" "logic_shift_imm")]
10270 (define_insn "*arith_adjacentmem"
10271 [(set (match_operand:SI 0 "s_register_operand" "=r")
10272 (match_operator:SI 1 "shiftable_operator"
10273 [(match_operand:SI 2 "memory_operand" "m")
10274 (match_operand:SI 3 "memory_operand" "m")]))
10275 (clobber (match_scratch:SI 4 "=r"))]
10276 "TARGET_ARM && adjacent_mem_locations (operands[2], operands[3])"
10282 HOST_WIDE_INT val1 = 0, val2 = 0;
10284 if (REGNO (operands[0]) > REGNO (operands[4]))
10286 ldm[1] = operands[4];
10287 ldm[2] = operands[0];
10291 ldm[1] = operands[0];
10292 ldm[2] = operands[4];
10295 base_reg = XEXP (operands[2], 0);
10297 if (!REG_P (base_reg))
10299 val1 = INTVAL (XEXP (base_reg, 1));
10300 base_reg = XEXP (base_reg, 0);
10303 if (!REG_P (XEXP (operands[3], 0)))
10304 val2 = INTVAL (XEXP (XEXP (operands[3], 0), 1));
10306 arith[0] = operands[0];
10307 arith[3] = operands[1];
10321 if (val1 !=0 && val2 != 0)
10325 if (val1 == 4 || val2 == 4)
10326 /* Other val must be 8, since we know they are adjacent and neither
10328 output_asm_insn (\"ldmib%?\\t%0, {%1, %2}\", ldm);
10329 else if (const_ok_for_arm (val1) || const_ok_for_arm (-val1))
10331 ldm[0] = ops[0] = operands[4];
10333 ops[2] = GEN_INT (val1);
10334 output_add_immediate (ops);
10336 output_asm_insn (\"ldmia%?\\t%0, {%1, %2}\", ldm);
10338 output_asm_insn (\"ldmda%?\\t%0, {%1, %2}\", ldm);
10342 /* Offset is out of range for a single add, so use two ldr. */
10345 ops[2] = GEN_INT (val1);
10346 output_asm_insn (\"ldr%?\\t%0, [%1, %2]\", ops);
10348 ops[2] = GEN_INT (val2);
10349 output_asm_insn (\"ldr%?\\t%0, [%1, %2]\", ops);
10352 else if (val1 != 0)
10355 output_asm_insn (\"ldmda%?\\t%0, {%1, %2}\", ldm);
10357 output_asm_insn (\"ldmia%?\\t%0, {%1, %2}\", ldm);
10362 output_asm_insn (\"ldmia%?\\t%0, {%1, %2}\", ldm);
10364 output_asm_insn (\"ldmda%?\\t%0, {%1, %2}\", ldm);
10366 output_asm_insn (\"%I3%?\\t%0, %1, %2\", arith);
10369 [(set_attr "length" "12")
10370 (set_attr "predicable" "yes")
10371 (set_attr "type" "load_4")]
10374 ; This pattern is never tried by combine, so do it as a peephole
10377 [(set (match_operand:SI 0 "arm_general_register_operand" "")
10378 (match_operand:SI 1 "arm_general_register_operand" ""))
10379 (set (reg:CC CC_REGNUM)
10380 (compare:CC (match_dup 1) (const_int 0)))]
10382 [(parallel [(set (reg:CC CC_REGNUM) (compare:CC (match_dup 1) (const_int 0)))
10383 (set (match_dup 0) (match_dup 1))])]
10388 [(set (match_operand:SI 0 "s_register_operand" "")
10389 (and:SI (ge:SI (match_operand:SI 1 "s_register_operand" "")
10391 (neg:SI (match_operator:SI 2 "arm_comparison_operator"
10392 [(match_operand:SI 3 "s_register_operand" "")
10393 (match_operand:SI 4 "arm_rhs_operand" "")]))))
10394 (clobber (match_operand:SI 5 "s_register_operand" ""))]
10396 [(set (match_dup 5) (not:SI (ashiftrt:SI (match_dup 1) (const_int 31))))
10397 (set (match_dup 0) (and:SI (match_op_dup 2 [(match_dup 3) (match_dup 4)])
10402 ;; This split can be used because CC_Z mode implies that the following
10403 ;; branch will be an equality, or an unsigned inequality, so the sign
10404 ;; extension is not needed.
10407 [(set (reg:CC_Z CC_REGNUM)
10409 (ashift:SI (subreg:SI (match_operand:QI 0 "memory_operand" "") 0)
10411 (match_operand 1 "const_int_operand" "")))
10412 (clobber (match_scratch:SI 2 ""))]
10414 && ((UINTVAL (operands[1]))
10415 == ((UINTVAL (operands[1])) >> 24) << 24)"
10416 [(set (match_dup 2) (zero_extend:SI (match_dup 0)))
10417 (set (reg:CC CC_REGNUM) (compare:CC (match_dup 2) (match_dup 1)))]
10419 operands[1] = GEN_INT (((unsigned long) INTVAL (operands[1])) >> 24);
10422 ;; ??? Check the patterns above for Thumb-2 usefulness
10424 (define_expand "prologue"
10425 [(clobber (const_int 0))]
10428 arm_expand_prologue ();
10430 thumb1_expand_prologue ();
10435 (define_expand "epilogue"
10436 [(clobber (const_int 0))]
10439 if (crtl->calls_eh_return)
10440 emit_insn (gen_force_register_use (gen_rtx_REG (Pmode, 2)));
10443 thumb1_expand_epilogue ();
10444 emit_jump_insn (gen_rtx_UNSPEC_VOLATILE (VOIDmode,
10445 gen_rtvec (1, ret_rtx), VUNSPEC_EPILOGUE));
10447 else if (HAVE_return)
10449 /* HAVE_return is testing for USE_RETURN_INSN (FALSE). Hence,
10450 no need for explicit testing again. */
10451 emit_jump_insn (gen_return ());
10453 else if (TARGET_32BIT)
10455 arm_expand_epilogue (true);
10461 ;; Note - although unspec_volatile's USE all hard registers,
10462 ;; USEs are ignored after relaod has completed. Thus we need
10463 ;; to add an unspec of the link register to ensure that flow
10464 ;; does not think that it is unused by the sibcall branch that
10465 ;; will replace the standard function epilogue.
10466 (define_expand "sibcall_epilogue"
10467 [(parallel [(unspec:SI [(reg:SI LR_REGNUM)] UNSPEC_REGISTER_USE)
10468 (unspec_volatile [(return)] VUNSPEC_EPILOGUE)])]
10471 arm_expand_epilogue (false);
10476 (define_expand "eh_epilogue"
10477 [(use (match_operand:SI 0 "register_operand"))
10478 (use (match_operand:SI 1 "register_operand"))
10479 (use (match_operand:SI 2 "register_operand"))]
10483 cfun->machine->eh_epilogue_sp_ofs = operands[1];
10484 if (!REG_P (operands[2]) || REGNO (operands[2]) != 2)
10486 rtx ra = gen_rtx_REG (Pmode, 2);
10488 emit_move_insn (ra, operands[2]);
10491 /* This is a hack -- we may have crystalized the function type too
10493 cfun->machine->func_type = 0;
10497 ;; This split is only used during output to reduce the number of patterns
10498 ;; that need assembler instructions adding to them. We allowed the setting
10499 ;; of the conditions to be implicit during rtl generation so that
10500 ;; the conditional compare patterns would work. However this conflicts to
10501 ;; some extent with the conditional data operations, so we have to split them
10504 ;; ??? Need to audit these splitters for Thumb-2. Why isn't normal
10505 ;; conditional execution sufficient?
10508 [(set (match_operand:SI 0 "s_register_operand" "")
10509 (if_then_else:SI (match_operator 1 "arm_comparison_operator"
10510 [(match_operand 2 "" "") (match_operand 3 "" "")])
10512 (match_operand 4 "" "")))
10513 (clobber (reg:CC CC_REGNUM))]
10514 "TARGET_ARM && reload_completed"
10515 [(set (match_dup 5) (match_dup 6))
10516 (cond_exec (match_dup 7)
10517 (set (match_dup 0) (match_dup 4)))]
10520 machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[1]),
10521 operands[2], operands[3]);
10522 enum rtx_code rc = GET_CODE (operands[1]);
10524 operands[5] = gen_rtx_REG (mode, CC_REGNUM);
10525 operands[6] = gen_rtx_COMPARE (mode, operands[2], operands[3]);
10526 if (mode == CCFPmode || mode == CCFPEmode)
10527 rc = reverse_condition_maybe_unordered (rc);
10529 rc = reverse_condition (rc);
10531 operands[7] = gen_rtx_fmt_ee (rc, VOIDmode, operands[5], const0_rtx);
10536 [(set (match_operand:SI 0 "s_register_operand" "")
10537 (if_then_else:SI (match_operator 1 "arm_comparison_operator"
10538 [(match_operand 2 "" "") (match_operand 3 "" "")])
10539 (match_operand 4 "" "")
10541 (clobber (reg:CC CC_REGNUM))]
10542 "TARGET_ARM && reload_completed"
10543 [(set (match_dup 5) (match_dup 6))
10544 (cond_exec (match_op_dup 1 [(match_dup 5) (const_int 0)])
10545 (set (match_dup 0) (match_dup 4)))]
10548 machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[1]),
10549 operands[2], operands[3]);
10551 operands[5] = gen_rtx_REG (mode, CC_REGNUM);
10552 operands[6] = gen_rtx_COMPARE (mode, operands[2], operands[3]);
10557 [(set (match_operand:SI 0 "s_register_operand" "")
10558 (if_then_else:SI (match_operator 1 "arm_comparison_operator"
10559 [(match_operand 2 "" "") (match_operand 3 "" "")])
10560 (match_operand 4 "" "")
10561 (match_operand 5 "" "")))
10562 (clobber (reg:CC CC_REGNUM))]
10563 "TARGET_ARM && reload_completed"
10564 [(set (match_dup 6) (match_dup 7))
10565 (cond_exec (match_op_dup 1 [(match_dup 6) (const_int 0)])
10566 (set (match_dup 0) (match_dup 4)))
10567 (cond_exec (match_dup 8)
10568 (set (match_dup 0) (match_dup 5)))]
10571 machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[1]),
10572 operands[2], operands[3]);
10573 enum rtx_code rc = GET_CODE (operands[1]);
10575 operands[6] = gen_rtx_REG (mode, CC_REGNUM);
10576 operands[7] = gen_rtx_COMPARE (mode, operands[2], operands[3]);
10577 if (mode == CCFPmode || mode == CCFPEmode)
10578 rc = reverse_condition_maybe_unordered (rc);
10580 rc = reverse_condition (rc);
10582 operands[8] = gen_rtx_fmt_ee (rc, VOIDmode, operands[6], const0_rtx);
10587 [(set (match_operand:SI 0 "s_register_operand" "")
10588 (if_then_else:SI (match_operator 1 "arm_comparison_operator"
10589 [(match_operand:SI 2 "s_register_operand" "")
10590 (match_operand:SI 3 "arm_add_operand" "")])
10591 (match_operand:SI 4 "arm_rhs_operand" "")
10593 (match_operand:SI 5 "s_register_operand" ""))))
10594 (clobber (reg:CC CC_REGNUM))]
10595 "TARGET_ARM && reload_completed"
10596 [(set (match_dup 6) (match_dup 7))
10597 (cond_exec (match_op_dup 1 [(match_dup 6) (const_int 0)])
10598 (set (match_dup 0) (match_dup 4)))
10599 (cond_exec (match_dup 8)
10600 (set (match_dup 0) (not:SI (match_dup 5))))]
10603 machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[1]),
10604 operands[2], operands[3]);
10605 enum rtx_code rc = GET_CODE (operands[1]);
10607 operands[6] = gen_rtx_REG (mode, CC_REGNUM);
10608 operands[7] = gen_rtx_COMPARE (mode, operands[2], operands[3]);
10609 if (mode == CCFPmode || mode == CCFPEmode)
10610 rc = reverse_condition_maybe_unordered (rc);
10612 rc = reverse_condition (rc);
10614 operands[8] = gen_rtx_fmt_ee (rc, VOIDmode, operands[6], const0_rtx);
10618 (define_insn "*cond_move_not"
10619 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
10620 (if_then_else:SI (match_operator 4 "arm_comparison_operator"
10621 [(match_operand 3 "cc_register" "") (const_int 0)])
10622 (match_operand:SI 1 "arm_rhs_operand" "0,?rI")
10624 (match_operand:SI 2 "s_register_operand" "r,r"))))]
10628 mov%d4\\t%0, %1\;mvn%D4\\t%0, %2"
10629 [(set_attr "conds" "use")
10630 (set_attr "type" "mvn_reg,multiple")
10631 (set_attr "length" "4,8")]
10634 ;; The next two patterns occur when an AND operation is followed by a
10635 ;; scc insn sequence
10637 (define_insn "*sign_extract_onebit"
10638 [(set (match_operand:SI 0 "s_register_operand" "=r")
10639 (sign_extract:SI (match_operand:SI 1 "s_register_operand" "r")
10641 (match_operand:SI 2 "const_int_operand" "n")))
10642 (clobber (reg:CC CC_REGNUM))]
10645 operands[2] = GEN_INT (1 << INTVAL (operands[2]));
10646 output_asm_insn (\"ands\\t%0, %1, %2\", operands);
10647 return \"mvnne\\t%0, #0\";
10649 [(set_attr "conds" "clob")
10650 (set_attr "length" "8")
10651 (set_attr "type" "multiple")]
10654 (define_insn "*not_signextract_onebit"
10655 [(set (match_operand:SI 0 "s_register_operand" "=r")
10657 (sign_extract:SI (match_operand:SI 1 "s_register_operand" "r")
10659 (match_operand:SI 2 "const_int_operand" "n"))))
10660 (clobber (reg:CC CC_REGNUM))]
10663 operands[2] = GEN_INT (1 << INTVAL (operands[2]));
10664 output_asm_insn (\"tst\\t%1, %2\", operands);
10665 output_asm_insn (\"mvneq\\t%0, #0\", operands);
10666 return \"movne\\t%0, #0\";
10668 [(set_attr "conds" "clob")
10669 (set_attr "length" "12")
10670 (set_attr "type" "multiple")]
10672 ;; ??? The above patterns need auditing for Thumb-2
10674 ;; Push multiple registers to the stack. Registers are in parallel (use ...)
10675 ;; expressions. For simplicity, the first register is also in the unspec
10677 ;; To avoid the usage of GNU extension, the length attribute is computed
10678 ;; in a C function arm_attr_length_push_multi.
10679 (define_insn "*push_multi"
10680 [(match_parallel 2 "multi_register_push"
10681 [(set (match_operand:BLK 0 "push_mult_memory_operand" "")
10682 (unspec:BLK [(match_operand:SI 1 "s_register_operand" "")]
10683 UNSPEC_PUSH_MULT))])]
10687 int num_saves = XVECLEN (operands[2], 0);
10689 /* For the StrongARM at least it is faster to
10690 use STR to store only a single register.
10691 In Thumb mode always use push, and the assembler will pick
10692 something appropriate. */
10693 if (num_saves == 1 && TARGET_ARM)
10694 output_asm_insn (\"str%?\\t%1, [%m0, #-4]!\", operands);
10701 strcpy (pattern, \"push%?\\t{%1\");
10703 strcpy (pattern, \"push\\t{%1\");
10705 for (i = 1; i < num_saves; i++)
10707 strcat (pattern, \", %|\");
10709 reg_names[REGNO (XEXP (XVECEXP (operands[2], 0, i), 0))]);
10712 strcat (pattern, \"}\");
10713 output_asm_insn (pattern, operands);
10718 [(set_attr "type" "store_16")
10719 (set (attr "length")
10720 (symbol_ref "arm_attr_length_push_multi (operands[2], operands[1])"))]
10723 (define_insn "stack_tie"
10724 [(set (mem:BLK (scratch))
10725 (unspec:BLK [(match_operand:SI 0 "s_register_operand" "rk")
10726 (match_operand:SI 1 "s_register_operand" "rk")]
10730 [(set_attr "length" "0")
10731 (set_attr "type" "block")]
10734 ;; Pop (as used in epilogue RTL)
10736 (define_insn "*load_multiple_with_writeback"
10737 [(match_parallel 0 "load_multiple_operation"
10738 [(set (match_operand:SI 1 "s_register_operand" "+rk")
10739 (plus:SI (match_dup 1)
10740 (match_operand:SI 2 "const_int_I_operand" "I")))
10741 (set (match_operand:SI 3 "s_register_operand" "=rk")
10742 (mem:SI (match_dup 1)))
10744 "TARGET_32BIT && (reload_in_progress || reload_completed)"
10747 arm_output_multireg_pop (operands, /*return_pc=*/false,
10748 /*cond=*/const_true_rtx,
10754 [(set_attr "type" "load_16")
10755 (set_attr "predicable" "yes")
10756 (set (attr "length")
10757 (symbol_ref "arm_attr_length_pop_multi (operands,
10758 /*return_pc=*/false,
10759 /*write_back_p=*/true)"))]
10762 ;; Pop with return (as used in epilogue RTL)
10764 ;; This instruction is generated when the registers are popped at the end of
10765 ;; epilogue. Here, instead of popping the value into LR and then generating
10766 ;; jump to LR, value is popped into PC directly. Hence, the pattern is combined
10768 (define_insn "*pop_multiple_with_writeback_and_return"
10769 [(match_parallel 0 "pop_multiple_return"
10771 (set (match_operand:SI 1 "s_register_operand" "+rk")
10772 (plus:SI (match_dup 1)
10773 (match_operand:SI 2 "const_int_I_operand" "I")))
10774 (set (match_operand:SI 3 "s_register_operand" "=rk")
10775 (mem:SI (match_dup 1)))
10777 "TARGET_32BIT && (reload_in_progress || reload_completed)"
10780 arm_output_multireg_pop (operands, /*return_pc=*/true,
10781 /*cond=*/const_true_rtx,
10787 [(set_attr "type" "load_16")
10788 (set_attr "predicable" "yes")
10789 (set (attr "length")
10790 (symbol_ref "arm_attr_length_pop_multi (operands, /*return_pc=*/true,
10791 /*write_back_p=*/true)"))]
10794 (define_insn "*pop_multiple_with_return"
10795 [(match_parallel 0 "pop_multiple_return"
10797 (set (match_operand:SI 2 "s_register_operand" "=rk")
10798 (mem:SI (match_operand:SI 1 "s_register_operand" "rk")))
10800 "TARGET_32BIT && (reload_in_progress || reload_completed)"
10803 arm_output_multireg_pop (operands, /*return_pc=*/true,
10804 /*cond=*/const_true_rtx,
10810 [(set_attr "type" "load_16")
10811 (set_attr "predicable" "yes")
10812 (set (attr "length")
10813 (symbol_ref "arm_attr_length_pop_multi (operands, /*return_pc=*/true,
10814 /*write_back_p=*/false)"))]
10817 ;; Load into PC and return
10818 (define_insn "*ldr_with_return"
10820 (set (reg:SI PC_REGNUM)
10821 (mem:SI (post_inc:SI (match_operand:SI 0 "s_register_operand" "+rk"))))]
10822 "TARGET_32BIT && (reload_in_progress || reload_completed)"
10823 "ldr%?\t%|pc, [%0], #4"
10824 [(set_attr "type" "load_4")
10825 (set_attr "predicable" "yes")]
10827 ;; Pop for floating point registers (as used in epilogue RTL)
10828 (define_insn "*vfp_pop_multiple_with_writeback"
10829 [(match_parallel 0 "pop_multiple_fp"
10830 [(set (match_operand:SI 1 "s_register_operand" "+rk")
10831 (plus:SI (match_dup 1)
10832 (match_operand:SI 2 "const_int_I_operand" "I")))
10833 (set (match_operand:DF 3 "vfp_hard_register_operand" "")
10834 (mem:DF (match_dup 1)))])]
10835 "TARGET_32BIT && TARGET_HARD_FLOAT"
10838 int num_regs = XVECLEN (operands[0], 0);
10841 strcpy (pattern, \"vldm\\t\");
10842 strcat (pattern, reg_names[REGNO (SET_DEST (XVECEXP (operands[0], 0, 0)))]);
10843 strcat (pattern, \"!, {\");
10844 op_list[0] = XEXP (XVECEXP (operands[0], 0, 1), 0);
10845 strcat (pattern, \"%P0\");
10846 if ((num_regs - 1) > 1)
10848 strcat (pattern, \"-%P1\");
10849 op_list [1] = XEXP (XVECEXP (operands[0], 0, num_regs - 1), 0);
10852 strcat (pattern, \"}\");
10853 output_asm_insn (pattern, op_list);
10857 [(set_attr "type" "load_16")
10858 (set_attr "conds" "unconditional")
10859 (set_attr "predicable" "no")]
10862 ;; Special patterns for dealing with the constant pool
10864 (define_insn "align_4"
10865 [(unspec_volatile [(const_int 0)] VUNSPEC_ALIGN)]
10868 assemble_align (32);
10871 [(set_attr "type" "no_insn")]
10874 (define_insn "align_8"
10875 [(unspec_volatile [(const_int 0)] VUNSPEC_ALIGN8)]
10878 assemble_align (64);
10881 [(set_attr "type" "no_insn")]
10884 (define_insn "consttable_end"
10885 [(unspec_volatile [(const_int 0)] VUNSPEC_POOL_END)]
10888 making_const_table = FALSE;
10891 [(set_attr "type" "no_insn")]
10894 (define_insn "consttable_1"
10895 [(unspec_volatile [(match_operand 0 "" "")] VUNSPEC_POOL_1)]
10898 making_const_table = TRUE;
10899 assemble_integer (operands[0], 1, BITS_PER_WORD, 1);
10900 assemble_zeros (3);
10903 [(set_attr "length" "4")
10904 (set_attr "type" "no_insn")]
10907 (define_insn "consttable_2"
10908 [(unspec_volatile [(match_operand 0 "" "")] VUNSPEC_POOL_2)]
10912 rtx x = operands[0];
10913 making_const_table = TRUE;
10914 switch (GET_MODE_CLASS (GET_MODE (x)))
10917 arm_emit_fp16_const (x);
10920 assemble_integer (operands[0], 2, BITS_PER_WORD, 1);
10921 assemble_zeros (2);
10926 [(set_attr "length" "4")
10927 (set_attr "type" "no_insn")]
10930 (define_insn "consttable_4"
10931 [(unspec_volatile [(match_operand 0 "" "")] VUNSPEC_POOL_4)]
10935 rtx x = operands[0];
10936 making_const_table = TRUE;
10937 scalar_float_mode float_mode;
10938 if (is_a <scalar_float_mode> (GET_MODE (x), &float_mode))
10939 assemble_real (*CONST_DOUBLE_REAL_VALUE (x), float_mode, BITS_PER_WORD);
10942 /* XXX: Sometimes gcc does something really dumb and ends up with
10943 a HIGH in a constant pool entry, usually because it's trying to
10944 load into a VFP register. We know this will always be used in
10945 combination with a LO_SUM which ignores the high bits, so just
10946 strip off the HIGH. */
10947 if (GET_CODE (x) == HIGH)
10949 assemble_integer (x, 4, BITS_PER_WORD, 1);
10950 mark_symbol_refs_as_used (x);
10954 [(set_attr "length" "4")
10955 (set_attr "type" "no_insn")]
10958 (define_insn "consttable_8"
10959 [(unspec_volatile [(match_operand 0 "" "")] VUNSPEC_POOL_8)]
10963 making_const_table = TRUE;
10964 scalar_float_mode float_mode;
10965 if (is_a <scalar_float_mode> (GET_MODE (operands[0]), &float_mode))
10966 assemble_real (*CONST_DOUBLE_REAL_VALUE (operands[0]),
10967 float_mode, BITS_PER_WORD);
10969 assemble_integer (operands[0], 8, BITS_PER_WORD, 1);
10972 [(set_attr "length" "8")
10973 (set_attr "type" "no_insn")]
10976 (define_insn "consttable_16"
10977 [(unspec_volatile [(match_operand 0 "" "")] VUNSPEC_POOL_16)]
10981 making_const_table = TRUE;
10982 scalar_float_mode float_mode;
10983 if (is_a <scalar_float_mode> (GET_MODE (operands[0]), &float_mode))
10984 assemble_real (*CONST_DOUBLE_REAL_VALUE (operands[0]),
10985 float_mode, BITS_PER_WORD);
10987 assemble_integer (operands[0], 16, BITS_PER_WORD, 1);
10990 [(set_attr "length" "16")
10991 (set_attr "type" "no_insn")]
10994 ;; V5 Instructions,
10996 (define_insn "clzsi2"
10997 [(set (match_operand:SI 0 "s_register_operand" "=r")
10998 (clz:SI (match_operand:SI 1 "s_register_operand" "r")))]
10999 "TARGET_32BIT && arm_arch5t"
11001 [(set_attr "predicable" "yes")
11002 (set_attr "type" "clz")])
11004 (define_insn "rbitsi2"
11005 [(set (match_operand:SI 0 "s_register_operand" "=r")
11006 (unspec:SI [(match_operand:SI 1 "s_register_operand" "r")] UNSPEC_RBIT))]
11007 "TARGET_32BIT && arm_arch_thumb2"
11009 [(set_attr "predicable" "yes")
11010 (set_attr "type" "clz")])
11012 ;; Keep this as a CTZ expression until after reload and then split
11013 ;; into RBIT + CLZ. Since RBIT is represented as an UNSPEC it is unlikely
11014 ;; to fold with any other expression.
11016 (define_insn_and_split "ctzsi2"
11017 [(set (match_operand:SI 0 "s_register_operand" "=r")
11018 (ctz:SI (match_operand:SI 1 "s_register_operand" "r")))]
11019 "TARGET_32BIT && arm_arch_thumb2"
11021 "&& reload_completed"
11024 emit_insn (gen_rbitsi2 (operands[0], operands[1]));
11025 emit_insn (gen_clzsi2 (operands[0], operands[0]));
11029 ;; V5E instructions.
11031 (define_insn "prefetch"
11032 [(prefetch (match_operand:SI 0 "address_operand" "p")
11033 (match_operand:SI 1 "" "")
11034 (match_operand:SI 2 "" ""))]
11035 "TARGET_32BIT && arm_arch5te"
11037 [(set_attr "type" "load_4")]
11040 ;; General predication pattern
11043 [(match_operator 0 "arm_comparison_operator"
11044 [(match_operand 1 "cc_register" "")
11047 && (!TARGET_NO_VOLATILE_CE || !volatile_refs_p (PATTERN (insn)))"
11049 [(set_attr "predicated" "yes")]
11052 (define_insn "force_register_use"
11053 [(unspec:SI [(match_operand:SI 0 "register_operand" "")] UNSPEC_REGISTER_USE)]
11056 [(set_attr "length" "0")
11057 (set_attr "type" "no_insn")]
11061 ;; Patterns for exception handling
11063 (define_expand "eh_return"
11064 [(use (match_operand 0 "general_operand"))]
11069 emit_insn (gen_arm_eh_return (operands[0]));
11071 emit_insn (gen_thumb_eh_return (operands[0]));
11076 ;; We can't expand this before we know where the link register is stored.
11077 (define_insn_and_split "arm_eh_return"
11078 [(unspec_volatile [(match_operand:SI 0 "s_register_operand" "r")]
11080 (clobber (match_scratch:SI 1 "=&r"))]
11083 "&& reload_completed"
11087 arm_set_return_address (operands[0], operands[1]);
11095 (define_insn "load_tp_hard"
11096 [(set (match_operand:SI 0 "register_operand" "=r")
11097 (unspec:SI [(const_int 0)] UNSPEC_TLS))]
11099 "mrc%?\\tp15, 0, %0, c13, c0, 3\\t@ load_tp_hard"
11100 [(set_attr "predicable" "yes")
11101 (set_attr "type" "mrs")]
11104 ;; Doesn't clobber R1-R3. Must use r0 for the first operand.
11105 (define_insn "load_tp_soft_fdpic"
11106 [(set (reg:SI 0) (unspec:SI [(const_int 0)] UNSPEC_TLS))
11107 (clobber (reg:SI FDPIC_REGNUM))
11108 (clobber (reg:SI LR_REGNUM))
11109 (clobber (reg:SI IP_REGNUM))
11110 (clobber (reg:CC CC_REGNUM))]
11111 "TARGET_SOFT_TP && TARGET_FDPIC"
11112 "bl\\t__aeabi_read_tp\\t@ load_tp_soft"
11113 [(set_attr "conds" "clob")
11114 (set_attr "type" "branch")]
11117 ;; Doesn't clobber R1-R3. Must use r0 for the first operand.
11118 (define_insn "load_tp_soft"
11119 [(set (reg:SI 0) (unspec:SI [(const_int 0)] UNSPEC_TLS))
11120 (clobber (reg:SI LR_REGNUM))
11121 (clobber (reg:SI IP_REGNUM))
11122 (clobber (reg:CC CC_REGNUM))]
11123 "TARGET_SOFT_TP && !TARGET_FDPIC"
11124 "bl\\t__aeabi_read_tp\\t@ load_tp_soft"
11125 [(set_attr "conds" "clob")
11126 (set_attr "type" "branch")]
11129 ;; tls descriptor call
11130 (define_insn "tlscall"
11131 [(set (reg:SI R0_REGNUM)
11132 (unspec:SI [(reg:SI R0_REGNUM)
11133 (match_operand:SI 0 "" "X")
11134 (match_operand 1 "" "")] UNSPEC_TLS))
11135 (clobber (reg:SI R1_REGNUM))
11136 (clobber (reg:SI LR_REGNUM))
11137 (clobber (reg:SI CC_REGNUM))]
11140 targetm.asm_out.internal_label (asm_out_file, "LPIC",
11141 INTVAL (operands[1]));
11142 return "bl\\t%c0(tlscall)";
11144 [(set_attr "conds" "clob")
11145 (set_attr "length" "4")
11146 (set_attr "type" "branch")]
11149 ;; For thread pointer builtin
11150 (define_expand "get_thread_pointersi"
11151 [(match_operand:SI 0 "s_register_operand")]
11155 arm_load_tp (operands[0]);
11161 ;; We only care about the lower 16 bits of the constant
11162 ;; being inserted into the upper 16 bits of the register.
11163 (define_insn "*arm_movtas_ze"
11164 [(set (zero_extract:SI (match_operand:SI 0 "s_register_operand" "+r,r")
11167 (match_operand:SI 1 "const_int_operand" ""))]
11172 [(set_attr "arch" "32,v8mb")
11173 (set_attr "predicable" "yes")
11174 (set_attr "length" "4")
11175 (set_attr "type" "alu_sreg")]
11178 (define_insn "*arm_rev"
11179 [(set (match_operand:SI 0 "s_register_operand" "=l,l,r")
11180 (bswap:SI (match_operand:SI 1 "s_register_operand" "l,l,r")))]
11186 [(set_attr "arch" "t1,t2,32")
11187 (set_attr "length" "2,2,4")
11188 (set_attr "predicable" "no,yes,yes")
11189 (set_attr "type" "rev")]
11192 (define_expand "arm_legacy_rev"
11193 [(set (match_operand:SI 2 "s_register_operand")
11194 (xor:SI (rotatert:SI (match_operand:SI 1 "s_register_operand")
11198 (lshiftrt:SI (match_dup 2)
11200 (set (match_operand:SI 3 "s_register_operand")
11201 (rotatert:SI (match_dup 1)
11204 (and:SI (match_dup 2)
11205 (const_int -65281)))
11206 (set (match_operand:SI 0 "s_register_operand")
11207 (xor:SI (match_dup 3)
11213 ;; Reuse temporaries to keep register pressure down.
11214 (define_expand "thumb_legacy_rev"
11215 [(set (match_operand:SI 2 "s_register_operand")
11216 (ashift:SI (match_operand:SI 1 "s_register_operand")
11218 (set (match_operand:SI 3 "s_register_operand")
11219 (lshiftrt:SI (match_dup 1)
11222 (ior:SI (match_dup 3)
11224 (set (match_operand:SI 4 "s_register_operand")
11226 (set (match_operand:SI 5 "s_register_operand")
11227 (rotatert:SI (match_dup 1)
11230 (ashift:SI (match_dup 5)
11233 (lshiftrt:SI (match_dup 5)
11236 (ior:SI (match_dup 5)
11239 (rotatert:SI (match_dup 5)
11241 (set (match_operand:SI 0 "s_register_operand")
11242 (ior:SI (match_dup 5)
11248 ;; ARM-specific expansion of signed mod by power of 2
11249 ;; using conditional negate.
11250 ;; For r0 % n where n is a power of 2 produce:
11252 ;; and r0, r0, #(n - 1)
11253 ;; and r1, r1, #(n - 1)
11254 ;; rsbpl r0, r1, #0
11256 (define_expand "modsi3"
11257 [(match_operand:SI 0 "register_operand")
11258 (match_operand:SI 1 "register_operand")
11259 (match_operand:SI 2 "const_int_operand")]
11262 HOST_WIDE_INT val = INTVAL (operands[2]);
11265 || exact_log2 (val) <= 0)
11268 rtx mask = GEN_INT (val - 1);
11270 /* In the special case of x0 % 2 we can do the even shorter:
11273 rsblt r0, r0, #0. */
11277 rtx cc_reg = arm_gen_compare_reg (LT,
11278 operands[1], const0_rtx, NULL_RTX);
11279 rtx cond = gen_rtx_LT (SImode, cc_reg, const0_rtx);
11280 rtx masked = gen_reg_rtx (SImode);
11282 emit_insn (gen_andsi3 (masked, operands[1], mask));
11283 emit_move_insn (operands[0],
11284 gen_rtx_IF_THEN_ELSE (SImode, cond,
11285 gen_rtx_NEG (SImode,
11291 rtx neg_op = gen_reg_rtx (SImode);
11292 rtx_insn *insn = emit_insn (gen_subsi3_compare0 (neg_op, const0_rtx,
11295 /* Extract the condition register and mode. */
11296 rtx cmp = XVECEXP (PATTERN (insn), 0, 0);
11297 rtx cc_reg = SET_DEST (cmp);
11298 rtx cond = gen_rtx_GE (SImode, cc_reg, const0_rtx);
11300 emit_insn (gen_andsi3 (operands[0], operands[1], mask));
11302 rtx masked_neg = gen_reg_rtx (SImode);
11303 emit_insn (gen_andsi3 (masked_neg, neg_op, mask));
11305 /* We want a conditional negate here, but emitting COND_EXEC rtxes
11306 during expand does not always work. Do an IF_THEN_ELSE instead. */
11307 emit_move_insn (operands[0],
11308 gen_rtx_IF_THEN_ELSE (SImode, cond,
11309 gen_rtx_NEG (SImode, masked_neg),
11317 (define_expand "bswapsi2"
11318 [(set (match_operand:SI 0 "s_register_operand")
11319 (bswap:SI (match_operand:SI 1 "s_register_operand")))]
11320 "TARGET_EITHER && (arm_arch6 || !optimize_size)"
11324 rtx op2 = gen_reg_rtx (SImode);
11325 rtx op3 = gen_reg_rtx (SImode);
11329 rtx op4 = gen_reg_rtx (SImode);
11330 rtx op5 = gen_reg_rtx (SImode);
11332 emit_insn (gen_thumb_legacy_rev (operands[0], operands[1],
11333 op2, op3, op4, op5));
11337 emit_insn (gen_arm_legacy_rev (operands[0], operands[1],
11346 ;; bswap16 patterns: use revsh and rev16 instructions for the signed
11347 ;; and unsigned variants, respectively. For rev16, expose
11348 ;; byte-swapping in the lower 16 bits only.
11349 (define_insn "*arm_revsh"
11350 [(set (match_operand:SI 0 "s_register_operand" "=l,l,r")
11351 (sign_extend:SI (bswap:HI (match_operand:HI 1 "s_register_operand" "l,l,r"))))]
11357 [(set_attr "arch" "t1,t2,32")
11358 (set_attr "length" "2,2,4")
11359 (set_attr "type" "rev")]
11362 (define_insn "*arm_rev16"
11363 [(set (match_operand:HI 0 "s_register_operand" "=l,l,r")
11364 (bswap:HI (match_operand:HI 1 "s_register_operand" "l,l,r")))]
11370 [(set_attr "arch" "t1,t2,32")
11371 (set_attr "length" "2,2,4")
11372 (set_attr "type" "rev")]
11375 ;; There are no canonicalisation rules for the position of the lshiftrt, ashift
11376 ;; operations within an IOR/AND RTX, therefore we have two patterns matching
11377 ;; each valid permutation.
11379 (define_insn "arm_rev16si2"
11380 [(set (match_operand:SI 0 "register_operand" "=l,l,r")
11381 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "l,l,r")
11383 (match_operand:SI 3 "const_int_operand" "n,n,n"))
11384 (and:SI (lshiftrt:SI (match_dup 1)
11386 (match_operand:SI 2 "const_int_operand" "n,n,n"))))]
11388 && aarch_rev16_shleft_mask_imm_p (operands[3], SImode)
11389 && aarch_rev16_shright_mask_imm_p (operands[2], SImode)"
11391 [(set_attr "arch" "t1,t2,32")
11392 (set_attr "length" "2,2,4")
11393 (set_attr "type" "rev")]
11396 (define_insn "arm_rev16si2_alt"
11397 [(set (match_operand:SI 0 "register_operand" "=l,l,r")
11398 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "l,l,r")
11400 (match_operand:SI 2 "const_int_operand" "n,n,n"))
11401 (and:SI (ashift:SI (match_dup 1)
11403 (match_operand:SI 3 "const_int_operand" "n,n,n"))))]
11405 && aarch_rev16_shleft_mask_imm_p (operands[3], SImode)
11406 && aarch_rev16_shright_mask_imm_p (operands[2], SImode)"
11408 [(set_attr "arch" "t1,t2,32")
11409 (set_attr "length" "2,2,4")
11410 (set_attr "type" "rev")]
11413 (define_expand "bswaphi2"
11414 [(set (match_operand:HI 0 "s_register_operand")
11415 (bswap:HI (match_operand:HI 1 "s_register_operand")))]
11420 ;; Patterns for LDRD/STRD in Thumb2 mode
11422 (define_insn "*thumb2_ldrd"
11423 [(set (match_operand:SI 0 "s_register_operand" "=r")
11424 (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk")
11425 (match_operand:SI 2 "ldrd_strd_offset_operand" "Do"))))
11426 (set (match_operand:SI 3 "s_register_operand" "=r")
11427 (mem:SI (plus:SI (match_dup 1)
11428 (match_operand:SI 4 "const_int_operand" ""))))]
11429 "TARGET_LDRD && TARGET_THUMB2 && reload_completed
11430 && ((INTVAL (operands[2]) + 4) == INTVAL (operands[4]))
11431 && (operands_ok_ldrd_strd (operands[0], operands[3],
11432 operands[1], INTVAL (operands[2]),
11434 "ldrd%?\t%0, %3, [%1, %2]"
11435 [(set_attr "type" "load_8")
11436 (set_attr "predicable" "yes")])
11438 (define_insn "*thumb2_ldrd_base"
11439 [(set (match_operand:SI 0 "s_register_operand" "=r")
11440 (mem:SI (match_operand:SI 1 "s_register_operand" "rk")))
11441 (set (match_operand:SI 2 "s_register_operand" "=r")
11442 (mem:SI (plus:SI (match_dup 1)
11444 "TARGET_LDRD && TARGET_THUMB2 && reload_completed
11445 && (operands_ok_ldrd_strd (operands[0], operands[2],
11446 operands[1], 0, false, true))"
11447 "ldrd%?\t%0, %2, [%1]"
11448 [(set_attr "type" "load_8")
11449 (set_attr "predicable" "yes")])
11451 (define_insn "*thumb2_ldrd_base_neg"
11452 [(set (match_operand:SI 0 "s_register_operand" "=r")
11453 (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk")
11455 (set (match_operand:SI 2 "s_register_operand" "=r")
11456 (mem:SI (match_dup 1)))]
11457 "TARGET_LDRD && TARGET_THUMB2 && reload_completed
11458 && (operands_ok_ldrd_strd (operands[0], operands[2],
11459 operands[1], -4, false, true))"
11460 "ldrd%?\t%0, %2, [%1, #-4]"
11461 [(set_attr "type" "load_8")
11462 (set_attr "predicable" "yes")])
11464 (define_insn "*thumb2_strd"
11465 [(set (mem:SI (plus:SI (match_operand:SI 0 "s_register_operand" "rk")
11466 (match_operand:SI 1 "ldrd_strd_offset_operand" "Do")))
11467 (match_operand:SI 2 "s_register_operand" "r"))
11468 (set (mem:SI (plus:SI (match_dup 0)
11469 (match_operand:SI 3 "const_int_operand" "")))
11470 (match_operand:SI 4 "s_register_operand" "r"))]
11471 "TARGET_LDRD && TARGET_THUMB2 && reload_completed
11472 && ((INTVAL (operands[1]) + 4) == INTVAL (operands[3]))
11473 && (operands_ok_ldrd_strd (operands[2], operands[4],
11474 operands[0], INTVAL (operands[1]),
11476 "strd%?\t%2, %4, [%0, %1]"
11477 [(set_attr "type" "store_8")
11478 (set_attr "predicable" "yes")])
11480 (define_insn "*thumb2_strd_base"
11481 [(set (mem:SI (match_operand:SI 0 "s_register_operand" "rk"))
11482 (match_operand:SI 1 "s_register_operand" "r"))
11483 (set (mem:SI (plus:SI (match_dup 0)
11485 (match_operand:SI 2 "s_register_operand" "r"))]
11486 "TARGET_LDRD && TARGET_THUMB2 && reload_completed
11487 && (operands_ok_ldrd_strd (operands[1], operands[2],
11488 operands[0], 0, false, false))"
11489 "strd%?\t%1, %2, [%0]"
11490 [(set_attr "type" "store_8")
11491 (set_attr "predicable" "yes")])
11493 (define_insn "*thumb2_strd_base_neg"
11494 [(set (mem:SI (plus:SI (match_operand:SI 0 "s_register_operand" "rk")
11496 (match_operand:SI 1 "s_register_operand" "r"))
11497 (set (mem:SI (match_dup 0))
11498 (match_operand:SI 2 "s_register_operand" "r"))]
11499 "TARGET_LDRD && TARGET_THUMB2 && reload_completed
11500 && (operands_ok_ldrd_strd (operands[1], operands[2],
11501 operands[0], -4, false, false))"
11502 "strd%?\t%1, %2, [%0, #-4]"
11503 [(set_attr "type" "store_8")
11504 (set_attr "predicable" "yes")])
11506 ;; ARMv8 CRC32 instructions.
11507 (define_insn "arm_<crc_variant>"
11508 [(set (match_operand:SI 0 "s_register_operand" "=r")
11509 (unspec:SI [(match_operand:SI 1 "s_register_operand" "r")
11510 (match_operand:<crc_mode> 2 "s_register_operand" "r")]
11513 "<crc_variant>\\t%0, %1, %2"
11514 [(set_attr "type" "crc")
11515 (set_attr "conds" "unconditional")]
11518 ;; Load the load/store double peephole optimizations.
11519 (include "ldrdstrd.md")
11521 ;; Load the load/store multiple patterns
11522 (include "ldmstm.md")
11524 ;; Patterns in ldmstm.md don't cover more than 4 registers. This pattern covers
11525 ;; large lists without explicit writeback generated for APCS_FRAME epilogue.
11526 ;; The operands are validated through the load_multiple_operation
11527 ;; match_parallel predicate rather than through constraints so enable it only
11529 (define_insn "*load_multiple"
11530 [(match_parallel 0 "load_multiple_operation"
11531 [(set (match_operand:SI 2 "s_register_operand" "=rk")
11532 (mem:SI (match_operand:SI 1 "s_register_operand" "rk")))
11534 "TARGET_32BIT && reload_completed"
11537 arm_output_multireg_pop (operands, /*return_pc=*/false,
11538 /*cond=*/const_true_rtx,
11544 [(set_attr "predicable" "yes")]
11547 (define_expand "copysignsf3"
11548 [(match_operand:SF 0 "register_operand")
11549 (match_operand:SF 1 "register_operand")
11550 (match_operand:SF 2 "register_operand")]
11551 "TARGET_SOFT_FLOAT && arm_arch_thumb2"
11553 emit_move_insn (operands[0], operands[2]);
11554 emit_insn (gen_insv_t2 (simplify_gen_subreg (SImode, operands[0], SFmode, 0),
11555 GEN_INT (31), GEN_INT (0),
11556 simplify_gen_subreg (SImode, operands[1], SFmode, 0)));
11561 (define_expand "copysigndf3"
11562 [(match_operand:DF 0 "register_operand")
11563 (match_operand:DF 1 "register_operand")
11564 (match_operand:DF 2 "register_operand")]
11565 "TARGET_SOFT_FLOAT && arm_arch_thumb2"
11567 rtx op0_low = gen_lowpart (SImode, operands[0]);
11568 rtx op0_high = gen_highpart (SImode, operands[0]);
11569 rtx op1_low = gen_lowpart (SImode, operands[1]);
11570 rtx op1_high = gen_highpart (SImode, operands[1]);
11571 rtx op2_high = gen_highpart (SImode, operands[2]);
11573 rtx scratch1 = gen_reg_rtx (SImode);
11574 rtx scratch2 = gen_reg_rtx (SImode);
11575 emit_move_insn (scratch1, op2_high);
11576 emit_move_insn (scratch2, op1_high);
11578 emit_insn(gen_rtx_SET(scratch1,
11579 gen_rtx_LSHIFTRT (SImode, op2_high, GEN_INT(31))));
11580 emit_insn(gen_insv_t2(scratch2, GEN_INT(1), GEN_INT(31), scratch1));
11581 emit_move_insn (op0_low, op1_low);
11582 emit_move_insn (op0_high, scratch2);
11588 ;; movmisalign patterns for HImode and SImode.
11589 (define_expand "movmisalign<mode>"
11590 [(match_operand:HSI 0 "general_operand")
11591 (match_operand:HSI 1 "general_operand")]
11594 /* This pattern is not permitted to fail during expansion: if both arguments
11595 are non-registers (e.g. memory := constant), force operand 1 into a
11597 rtx (* gen_unaligned_load)(rtx, rtx);
11598 rtx tmp_dest = operands[0];
11599 if (!s_register_operand (operands[0], <MODE>mode)
11600 && !s_register_operand (operands[1], <MODE>mode))
11601 operands[1] = force_reg (<MODE>mode, operands[1]);
11603 if (<MODE>mode == HImode)
11605 gen_unaligned_load = gen_unaligned_loadhiu;
11606 tmp_dest = gen_reg_rtx (SImode);
11609 gen_unaligned_load = gen_unaligned_loadsi;
11611 if (MEM_P (operands[1]))
11613 emit_insn (gen_unaligned_load (tmp_dest, operands[1]));
11614 if (<MODE>mode == HImode)
11615 emit_move_insn (operands[0], gen_lowpart (HImode, tmp_dest));
11618 emit_insn (gen_unaligned_store<mode> (operands[0], operands[1]));
11623 (define_insn "arm_<cdp>"
11624 [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "n")
11625 (match_operand:SI 1 "immediate_operand" "n")
11626 (match_operand:SI 2 "immediate_operand" "n")
11627 (match_operand:SI 3 "immediate_operand" "n")
11628 (match_operand:SI 4 "immediate_operand" "n")
11629 (match_operand:SI 5 "immediate_operand" "n")] CDPI)]
11630 "arm_coproc_builtin_available (VUNSPEC_<CDP>)"
11632 arm_const_bounds (operands[0], 0, 16);
11633 arm_const_bounds (operands[1], 0, 16);
11634 arm_const_bounds (operands[2], 0, (1 << 5));
11635 arm_const_bounds (operands[3], 0, (1 << 5));
11636 arm_const_bounds (operands[4], 0, (1 << 5));
11637 arm_const_bounds (operands[5], 0, 8);
11638 return "<cdp>\\tp%c0, %1, CR%c2, CR%c3, CR%c4, %5";
11640 [(set_attr "length" "4")
11641 (set_attr "type" "coproc")])
11643 (define_insn "*ldc"
11644 [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "n")
11645 (match_operand:SI 1 "immediate_operand" "n")
11646 (match_operand:SI 2 "memory_operand" "Uz")] LDCI)]
11647 "arm_coproc_builtin_available (VUNSPEC_<LDC>)"
11649 arm_const_bounds (operands[0], 0, 16);
11650 arm_const_bounds (operands[1], 0, (1 << 5));
11651 return "<ldc>\\tp%c0, CR%c1, %2";
11653 [(set_attr "length" "4")
11654 (set_attr "type" "coproc")])
11656 (define_insn "*stc"
11657 [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "n")
11658 (match_operand:SI 1 "immediate_operand" "n")
11659 (match_operand:SI 2 "memory_operand" "=Uz")] STCI)]
11660 "arm_coproc_builtin_available (VUNSPEC_<STC>)"
11662 arm_const_bounds (operands[0], 0, 16);
11663 arm_const_bounds (operands[1], 0, (1 << 5));
11664 return "<stc>\\tp%c0, CR%c1, %2";
11666 [(set_attr "length" "4")
11667 (set_attr "type" "coproc")])
11669 (define_expand "arm_<ldc>"
11670 [(unspec_volatile [(match_operand:SI 0 "immediate_operand")
11671 (match_operand:SI 1 "immediate_operand")
11672 (mem:SI (match_operand:SI 2 "s_register_operand"))] LDCI)]
11673 "arm_coproc_builtin_available (VUNSPEC_<LDC>)")
11675 (define_expand "arm_<stc>"
11676 [(unspec_volatile [(match_operand:SI 0 "immediate_operand")
11677 (match_operand:SI 1 "immediate_operand")
11678 (mem:SI (match_operand:SI 2 "s_register_operand"))] STCI)]
11679 "arm_coproc_builtin_available (VUNSPEC_<STC>)")
11681 (define_insn "arm_<mcr>"
11682 [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "n")
11683 (match_operand:SI 1 "immediate_operand" "n")
11684 (match_operand:SI 2 "s_register_operand" "r")
11685 (match_operand:SI 3 "immediate_operand" "n")
11686 (match_operand:SI 4 "immediate_operand" "n")
11687 (match_operand:SI 5 "immediate_operand" "n")] MCRI)
11688 (use (match_dup 2))]
11689 "arm_coproc_builtin_available (VUNSPEC_<MCR>)"
11691 arm_const_bounds (operands[0], 0, 16);
11692 arm_const_bounds (operands[1], 0, 8);
11693 arm_const_bounds (operands[3], 0, (1 << 5));
11694 arm_const_bounds (operands[4], 0, (1 << 5));
11695 arm_const_bounds (operands[5], 0, 8);
11696 return "<mcr>\\tp%c0, %1, %2, CR%c3, CR%c4, %5";
11698 [(set_attr "length" "4")
11699 (set_attr "type" "coproc")])
11701 (define_insn "arm_<mrc>"
11702 [(set (match_operand:SI 0 "s_register_operand" "=r")
11703 (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "n")
11704 (match_operand:SI 2 "immediate_operand" "n")
11705 (match_operand:SI 3 "immediate_operand" "n")
11706 (match_operand:SI 4 "immediate_operand" "n")
11707 (match_operand:SI 5 "immediate_operand" "n")] MRCI))]
11708 "arm_coproc_builtin_available (VUNSPEC_<MRC>)"
11710 arm_const_bounds (operands[1], 0, 16);
11711 arm_const_bounds (operands[2], 0, 8);
11712 arm_const_bounds (operands[3], 0, (1 << 5));
11713 arm_const_bounds (operands[4], 0, (1 << 5));
11714 arm_const_bounds (operands[5], 0, 8);
11715 return "<mrc>\\tp%c1, %2, %0, CR%c3, CR%c4, %5";
11717 [(set_attr "length" "4")
11718 (set_attr "type" "coproc")])
11720 (define_insn "arm_<mcrr>"
11721 [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "n")
11722 (match_operand:SI 1 "immediate_operand" "n")
11723 (match_operand:DI 2 "s_register_operand" "r")
11724 (match_operand:SI 3 "immediate_operand" "n")] MCRRI)
11725 (use (match_dup 2))]
11726 "arm_coproc_builtin_available (VUNSPEC_<MCRR>)"
11728 arm_const_bounds (operands[0], 0, 16);
11729 arm_const_bounds (operands[1], 0, 8);
11730 arm_const_bounds (operands[3], 0, (1 << 5));
11731 return "<mcrr>\\tp%c0, %1, %Q2, %R2, CR%c3";
11733 [(set_attr "length" "4")
11734 (set_attr "type" "coproc")])
11736 (define_insn "arm_<mrrc>"
11737 [(set (match_operand:DI 0 "s_register_operand" "=r")
11738 (unspec_volatile:DI [(match_operand:SI 1 "immediate_operand" "n")
11739 (match_operand:SI 2 "immediate_operand" "n")
11740 (match_operand:SI 3 "immediate_operand" "n")] MRRCI))]
11741 "arm_coproc_builtin_available (VUNSPEC_<MRRC>)"
11743 arm_const_bounds (operands[1], 0, 16);
11744 arm_const_bounds (operands[2], 0, 8);
11745 arm_const_bounds (operands[3], 0, (1 << 5));
11746 return "<mrrc>\\tp%c1, %2, %Q0, %R0, CR%c3";
11748 [(set_attr "length" "4")
11749 (set_attr "type" "coproc")])
11751 (define_expand "speculation_barrier"
11752 [(unspec_volatile [(const_int 0)] VUNSPEC_SPECULATION_BARRIER)]
11755 /* For thumb1 (except Armv8 derivatives), and for pre-Armv7 we don't
11756 have a usable barrier (and probably don't need one in practice).
11757 But to be safe if such code is run on later architectures, call a
11758 helper function in libgcc that will do the thing for the active
11760 if (!(arm_arch7 || arm_arch8))
11762 arm_emit_speculation_barrier_function ();
11768 ;; Generate a hard speculation barrier when we have not enabled speculation
11770 (define_insn "*speculation_barrier_insn"
11771 [(unspec_volatile [(const_int 0)] VUNSPEC_SPECULATION_BARRIER)]
11772 "arm_arch7 || arm_arch8"
11774 [(set_attr "type" "block")
11775 (set_attr "length" "8")]
11778 ;; Vector bits common to IWMMXT and Neon
11779 (include "vec-common.md")
11780 ;; Load the Intel Wireless Multimedia Extension patterns
11781 (include "iwmmxt.md")
11782 ;; Load the VFP co-processor patterns
11784 ;; Thumb-1 patterns
11785 (include "thumb1.md")
11786 ;; Thumb-2 patterns
11787 (include "thumb2.md")
11789 (include "neon.md")
11791 (include "crypto.md")
11792 ;; Synchronization Primitives
11793 (include "sync.md")
11794 ;; Fixed-point patterns
11795 (include "arm-fixed.md")