1 ;;- Machine description for ARM for GNU compiler
2 ;; Copyright (C) 1991-2019 Free Software Foundation, Inc.
3 ;; Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 ;; and Martin Simmons (@harleqn.co.uk).
5 ;; More major hacks by Richard Earnshaw (rearnsha@arm.com).
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it
10 ;; under the terms of the GNU General Public License as published
11 ;; by the Free Software Foundation; either version 3, or (at your
12 ;; option) any later version.
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
15 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 ;; License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
26 ;;---------------------------------------------------------------------------
29 ;; Register numbers -- All machine registers should be defined here
31 [(R0_REGNUM 0) ; First CORE register
32 (R1_REGNUM 1) ; Second CORE register
33 (R4_REGNUM 4) ; Fifth CORE register
34 (IP_REGNUM 12) ; Scratch register
35 (SP_REGNUM 13) ; Stack pointer
36 (LR_REGNUM 14) ; Return address register
37 (PC_REGNUM 15) ; Program counter
38 (LAST_ARM_REGNUM 15) ;
39 (CC_REGNUM 100) ; Condition code pseudo register
40 (VFPCC_REGNUM 101) ; VFP Condition code pseudo register
43 ;; 3rd operand to select_dominance_cc_mode
50 ;; conditional compare combination
61 ;;---------------------------------------------------------------------------
64 ;; Processor type. This is created automatically from arm-cores.def.
65 (include "arm-tune.md")
67 ;; Instruction classification types
70 ; IS_THUMB is set to 'yes' when we are generating Thumb code, and 'no' when
71 ; generating ARM code. This is used to control the length of some insn
72 ; patterns that share the same RTL in both ARM and Thumb code.
73 (define_attr "is_thumb" "yes,no"
74 (const (if_then_else (symbol_ref "TARGET_THUMB")
75 (const_string "yes") (const_string "no"))))
77 ; IS_ARCH6 is set to 'yes' when we are generating code form ARMv6.
78 (define_attr "is_arch6" "no,yes" (const (symbol_ref "arm_arch6")))
80 ; IS_THUMB1 is set to 'yes' iff we are generating Thumb-1 code.
81 (define_attr "is_thumb1" "yes,no"
82 (const (if_then_else (symbol_ref "TARGET_THUMB1")
83 (const_string "yes") (const_string "no"))))
85 ; Mark an instruction as suitable for "short IT" blocks in Thumb-2.
86 ; The arm_restrict_it flag enables the "short IT" feature which
87 ; restricts IT blocks to a single 16-bit instruction.
88 ; This attribute should only be used on 16-bit Thumb-2 instructions
89 ; which may be predicated (the "predicable" attribute must be set).
90 (define_attr "predicable_short_it" "no,yes" (const_string "no"))
92 ; Mark an instruction as suitable for "short IT" blocks in Thumb-2.
93 ; This attribute should only be used on instructions which may emit
94 ; an IT block in their expansion which is not a short IT.
95 (define_attr "enabled_for_short_it" "no,yes" (const_string "yes"))
97 ;; Operand number of an input operand that is shifted. Zero if the
98 ;; given instruction does not shift one of its input operands.
99 (define_attr "shift" "" (const_int 0))
101 ;; [For compatibility with AArch64 in pipeline models]
102 ;; Attribute that specifies whether or not the instruction touches fp
104 (define_attr "fp" "no,yes" (const_string "no"))
106 ; Floating Point Unit. If we only have floating point emulation, then there
107 ; is no point in scheduling the floating point insns. (Well, for best
108 ; performance we should try and group them together).
109 (define_attr "fpu" "none,vfp"
110 (const (symbol_ref "arm_fpu_attr")))
112 ; Predicated means that the insn form is conditionally executed based on a
113 ; predicate. We default to 'no' because no Thumb patterns match this rule
114 ; and not all ARM insns do.
115 (define_attr "predicated" "yes,no" (const_string "no"))
117 ; LENGTH of an instruction (in bytes)
118 (define_attr "length" ""
121 ; The architecture which supports the instruction (or alternative).
122 ; This can be "a" for ARM, "t" for either of the Thumbs, "32" for
123 ; TARGET_32BIT, "t1" or "t2" to specify a specific Thumb mode. "v6"
124 ; for ARM or Thumb-2 with arm_arch6, and nov6 for ARM without
125 ; arm_arch6. "v6t2" for Thumb-2 with arm_arch6 and "v8mb" for ARMv8-M
126 ; Baseline. This attribute is used to compute attribute "enabled",
127 ; use type "any" to enable an alternative in all cases.
128 (define_attr "arch" "any,a,t,32,t1,t2,v6,nov6,v6t2,v8mb,neon_for_64bits,avoid_neon_for_64bits,iwmmxt,iwmmxt2,armv6_or_vfpv3,neon"
129 (const_string "any"))
131 (define_attr "arch_enabled" "no,yes"
132 (cond [(eq_attr "arch" "any")
135 (and (eq_attr "arch" "a")
136 (match_test "TARGET_ARM"))
139 (and (eq_attr "arch" "t")
140 (match_test "TARGET_THUMB"))
143 (and (eq_attr "arch" "t1")
144 (match_test "TARGET_THUMB1"))
147 (and (eq_attr "arch" "t2")
148 (match_test "TARGET_THUMB2"))
151 (and (eq_attr "arch" "32")
152 (match_test "TARGET_32BIT"))
155 (and (eq_attr "arch" "v6")
156 (match_test "TARGET_32BIT && arm_arch6"))
159 (and (eq_attr "arch" "nov6")
160 (match_test "TARGET_32BIT && !arm_arch6"))
163 (and (eq_attr "arch" "v6t2")
164 (match_test "TARGET_32BIT && arm_arch6 && arm_arch_thumb2"))
167 (and (eq_attr "arch" "v8mb")
168 (match_test "TARGET_THUMB1 && arm_arch8"))
171 (and (eq_attr "arch" "avoid_neon_for_64bits")
172 (match_test "TARGET_NEON")
173 (not (match_test "TARGET_PREFER_NEON_64BITS")))
176 (and (eq_attr "arch" "neon_for_64bits")
177 (match_test "TARGET_NEON")
178 (match_test "TARGET_PREFER_NEON_64BITS"))
181 (and (eq_attr "arch" "iwmmxt2")
182 (match_test "TARGET_REALLY_IWMMXT2"))
185 (and (eq_attr "arch" "armv6_or_vfpv3")
186 (match_test "arm_arch6 || TARGET_VFP3"))
189 (and (eq_attr "arch" "neon")
190 (match_test "TARGET_NEON"))
194 (const_string "no")))
196 (define_attr "opt" "any,speed,size"
197 (const_string "any"))
199 (define_attr "opt_enabled" "no,yes"
200 (cond [(eq_attr "opt" "any")
203 (and (eq_attr "opt" "speed")
204 (match_test "optimize_function_for_speed_p (cfun)"))
207 (and (eq_attr "opt" "size")
208 (match_test "optimize_function_for_size_p (cfun)"))
209 (const_string "yes")]
210 (const_string "no")))
212 (define_attr "use_literal_pool" "no,yes"
213 (cond [(and (eq_attr "type" "f_loads,f_loadd")
214 (match_test "CONSTANT_P (operands[1])"))
215 (const_string "yes")]
216 (const_string "no")))
218 ; Enable all alternatives that are both arch_enabled and insn_enabled.
219 ; FIXME:: opt_enabled has been temporarily removed till the time we have
220 ; an attribute that allows the use of such alternatives.
221 ; This depends on caching of speed_p, size_p on a per
222 ; alternative basis. The problem is that the enabled attribute
223 ; cannot depend on any state that is not cached or is not constant
224 ; for a compilation unit. We probably need a generic "hot/cold"
225 ; alternative which if implemented can help with this. We disable this
226 ; until such a time as this is implemented and / or the improvements or
227 ; regressions with removing this attribute are double checked.
228 ; See ashldi3_neon and <shift>di3_neon in neon.md.
230 (define_attr "enabled" "no,yes"
231 (cond [(and (eq_attr "predicable_short_it" "no")
232 (and (eq_attr "predicated" "yes")
233 (match_test "arm_restrict_it")))
236 (and (eq_attr "enabled_for_short_it" "no")
237 (match_test "arm_restrict_it"))
240 (eq_attr "arch_enabled" "no")
242 (const_string "yes")))
244 ; POOL_RANGE is how far away from a constant pool entry that this insn
245 ; can be placed. If the distance is zero, then this insn will never
246 ; reference the pool.
247 ; Note that for Thumb constant pools the PC value is rounded down to the
248 ; nearest multiple of four. Therefore, THUMB2_POOL_RANGE (and POOL_RANGE for
249 ; Thumb insns) should be set to <max_range> - 2.
250 ; NEG_POOL_RANGE is nonzero for insns that can reference a constant pool entry
251 ; before its address. It is set to <max_range> - (8 + <data_size>).
252 (define_attr "arm_pool_range" "" (const_int 0))
253 (define_attr "thumb2_pool_range" "" (const_int 0))
254 (define_attr "arm_neg_pool_range" "" (const_int 0))
255 (define_attr "thumb2_neg_pool_range" "" (const_int 0))
257 (define_attr "pool_range" ""
258 (cond [(eq_attr "is_thumb" "yes") (attr "thumb2_pool_range")]
259 (attr "arm_pool_range")))
260 (define_attr "neg_pool_range" ""
261 (cond [(eq_attr "is_thumb" "yes") (attr "thumb2_neg_pool_range")]
262 (attr "arm_neg_pool_range")))
264 ; An assembler sequence may clobber the condition codes without us knowing.
265 ; If such an insn references the pool, then we have no way of knowing how,
266 ; so use the most conservative value for pool_range.
267 (define_asm_attributes
268 [(set_attr "conds" "clob")
269 (set_attr "length" "4")
270 (set_attr "pool_range" "250")])
272 ; Load scheduling, set from the arm_ld_sched variable
273 ; initialized by arm_option_override()
274 (define_attr "ldsched" "no,yes" (const (symbol_ref "arm_ld_sched")))
276 ; condition codes: this one is used by final_prescan_insn to speed up
277 ; conditionalizing instructions. It saves having to scan the rtl to see if
278 ; it uses or alters the condition codes.
280 ; USE means that the condition codes are used by the insn in the process of
281 ; outputting code, this means (at present) that we can't use the insn in
284 ; SET means that the purpose of the insn is to set the condition codes in a
285 ; well defined manner.
287 ; CLOB means that the condition codes are altered in an undefined manner, if
288 ; they are altered at all
290 ; UNCONDITIONAL means the instruction cannot be conditionally executed and
291 ; that the instruction does not use or alter the condition codes.
293 ; NOCOND means that the instruction does not use or alter the condition
294 ; codes but can be converted into a conditionally exectuted instruction.
296 (define_attr "conds" "use,set,clob,unconditional,nocond"
298 (ior (eq_attr "is_thumb1" "yes")
299 (eq_attr "type" "call"))
300 (const_string "clob")
301 (if_then_else (eq_attr "is_neon_type" "no")
302 (const_string "nocond")
303 (const_string "unconditional"))))
305 ; Predicable means that the insn can be conditionally executed based on
306 ; an automatically added predicate (additional patterns are generated by
307 ; gen...). We default to 'no' because no Thumb patterns match this rule
308 ; and not all ARM patterns do.
309 (define_attr "predicable" "no,yes" (const_string "no"))
311 ; Only model the write buffer for ARM6 and ARM7. Earlier processors don't
312 ; have one. Later ones, such as StrongARM, have write-back caches, so don't
313 ; suffer blockages enough to warrant modelling this (and it can adversely
314 ; affect the schedule).
315 (define_attr "model_wbuf" "no,yes" (const (symbol_ref "arm_tune_wbuf")))
317 ; WRITE_CONFLICT implies that a read following an unrelated write is likely
318 ; to stall the processor. Used with model_wbuf above.
319 (define_attr "write_conflict" "no,yes"
320 (if_then_else (eq_attr "type"
323 (const_string "no")))
325 ; Classify the insns into those that take one cycle and those that take more
326 ; than one on the main cpu execution unit.
327 (define_attr "core_cycles" "single,multi"
328 (if_then_else (eq_attr "type"
329 "adc_imm, adc_reg, adcs_imm, adcs_reg, adr, alu_ext, alu_imm, alu_sreg,\
330 alu_shift_imm, alu_shift_reg, alu_dsp_reg, alus_ext, alus_imm, alus_sreg,\
331 alus_shift_imm, alus_shift_reg, bfm, csel, rev, logic_imm, logic_reg,\
332 logic_shift_imm, logic_shift_reg, logics_imm, logics_reg,\
333 logics_shift_imm, logics_shift_reg, extend, shift_imm, float, fcsel,\
334 wmmx_wor, wmmx_wxor, wmmx_wand, wmmx_wandn, wmmx_wmov, wmmx_tmcrr,\
335 wmmx_tmrrc, wmmx_wldr, wmmx_wstr, wmmx_tmcr, wmmx_tmrc, wmmx_wadd,\
336 wmmx_wsub, wmmx_wmul, wmmx_wmac, wmmx_wavg2, wmmx_tinsr, wmmx_textrm,\
337 wmmx_wshufh, wmmx_wcmpeq, wmmx_wcmpgt, wmmx_wmax, wmmx_wmin, wmmx_wpack,\
338 wmmx_wunpckih, wmmx_wunpckil, wmmx_wunpckeh, wmmx_wunpckel, wmmx_wror,\
339 wmmx_wsra, wmmx_wsrl, wmmx_wsll, wmmx_wmadd, wmmx_tmia, wmmx_tmiaph,\
340 wmmx_tmiaxy, wmmx_tbcst, wmmx_tmovmsk, wmmx_wacc, wmmx_waligni,\
341 wmmx_walignr, wmmx_tandc, wmmx_textrc, wmmx_torc, wmmx_torvsc, wmmx_wsad,\
342 wmmx_wabs, wmmx_wabsdiff, wmmx_waddsubhx, wmmx_wsubaddhx, wmmx_wavg4,\
343 wmmx_wmulw, wmmx_wqmulm, wmmx_wqmulwm, wmmx_waddbhus, wmmx_wqmiaxy,\
344 wmmx_wmiaxy, wmmx_wmiawxy, wmmx_wmerge")
345 (const_string "single")
346 (const_string "multi")))
348 ;; FAR_JUMP is "yes" if a BL instruction is used to generate a branch to a
349 ;; distant label. Only applicable to Thumb code.
350 (define_attr "far_jump" "yes,no" (const_string "no"))
353 ;; The number of machine instructions this pattern expands to.
354 ;; Used for Thumb-2 conditional execution.
355 (define_attr "ce_count" "" (const_int 1))
357 ;;---------------------------------------------------------------------------
360 (include "unspecs.md")
362 ;;---------------------------------------------------------------------------
365 (include "iterators.md")
367 ;;---------------------------------------------------------------------------
370 (include "predicates.md")
371 (include "constraints.md")
373 ;;---------------------------------------------------------------------------
374 ;; Pipeline descriptions
376 (define_attr "tune_cortexr4" "yes,no"
378 (eq_attr "tune" "cortexr4,cortexr4f,cortexr5")
380 (const_string "no"))))
382 ;; True if the generic scheduling description should be used.
384 (define_attr "generic_sched" "yes,no"
386 (ior (eq_attr "tune" "fa526,fa626,fa606te,fa626te,fmp626,fa726te,\
387 arm926ejs,arm10e,arm1026ejs,arm1136js,\
388 arm1136jfs,cortexa5,cortexa7,cortexa8,\
389 cortexa9,cortexa12,cortexa15,cortexa17,\
390 cortexa53,cortexa57,cortexm4,cortexm7,\
391 exynosm1,marvell_pj4,xgene1")
392 (eq_attr "tune_cortexr4" "yes"))
394 (const_string "yes"))))
396 (define_attr "generic_vfp" "yes,no"
398 (and (eq_attr "fpu" "vfp")
399 (eq_attr "tune" "!arm10e,cortexa5,cortexa7,\
400 cortexa8,cortexa9,cortexa53,cortexm4,\
401 cortexm7,marvell_pj4,xgene1")
402 (eq_attr "tune_cortexr4" "no"))
404 (const_string "no"))))
406 (include "marvell-f-iwmmxt.md")
407 (include "arm-generic.md")
408 (include "arm926ejs.md")
409 (include "arm1020e.md")
410 (include "arm1026ejs.md")
411 (include "arm1136jfs.md")
413 (include "fa606te.md")
414 (include "fa626te.md")
415 (include "fmp626.md")
416 (include "fa726te.md")
417 (include "cortex-a5.md")
418 (include "cortex-a7.md")
419 (include "cortex-a8.md")
420 (include "cortex-a9.md")
421 (include "cortex-a15.md")
422 (include "cortex-a17.md")
423 (include "cortex-a53.md")
424 (include "cortex-a57.md")
425 (include "cortex-r4.md")
426 (include "cortex-r4f.md")
427 (include "cortex-m7.md")
428 (include "cortex-m4.md")
429 (include "cortex-m4-fpu.md")
430 (include "exynos-m1.md")
432 (include "marvell-pj4.md")
433 (include "xgene1.md")
436 ;;---------------------------------------------------------------------------
441 ;; Note: For DImode insns, there is normally no reason why operands should
442 ;; not be in the same register, what we don't want is for something being
443 ;; written to partially overlap something that is an input.
445 (define_expand "adddi3"
447 [(set (match_operand:DI 0 "s_register_operand" "")
448 (plus:DI (match_operand:DI 1 "s_register_operand" "")
449 (match_operand:DI 2 "arm_adddi_operand" "")))
450 (clobber (reg:CC CC_REGNUM))])]
455 if (!REG_P (operands[1]))
456 operands[1] = force_reg (DImode, operands[1]);
457 if (!REG_P (operands[2]))
458 operands[2] = force_reg (DImode, operands[2]);
463 (define_insn_and_split "*arm_adddi3"
464 [(set (match_operand:DI 0 "arm_general_register_operand" "=&r,&r,&r,&r,&r")
465 (plus:DI (match_operand:DI 1 "arm_general_register_operand" "%0, 0, r, 0, r")
466 (match_operand:DI 2 "arm_general_adddi_operand" "r, 0, r, Dd, Dd")))
467 (clobber (reg:CC CC_REGNUM))]
468 "TARGET_32BIT && !TARGET_NEON"
470 "TARGET_32BIT && ((!TARGET_NEON && !TARGET_IWMMXT) || reload_completed)"
471 [(parallel [(set (reg:CC_C CC_REGNUM)
472 (compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
474 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
475 (set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))
476 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
479 operands[3] = gen_highpart (SImode, operands[0]);
480 operands[0] = gen_lowpart (SImode, operands[0]);
481 operands[4] = gen_highpart (SImode, operands[1]);
482 operands[1] = gen_lowpart (SImode, operands[1]);
483 operands[5] = gen_highpart_mode (SImode, DImode, operands[2]);
484 operands[2] = gen_lowpart (SImode, operands[2]);
486 [(set_attr "conds" "clob")
487 (set_attr "length" "8")
488 (set_attr "type" "multiple")]
491 (define_insn_and_split "*adddi_sesidi_di"
492 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
493 (plus:DI (sign_extend:DI
494 (match_operand:SI 2 "s_register_operand" "r,r"))
495 (match_operand:DI 1 "s_register_operand" "0,r")))
496 (clobber (reg:CC CC_REGNUM))]
499 "TARGET_32BIT && reload_completed"
500 [(parallel [(set (reg:CC_C CC_REGNUM)
501 (compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
503 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
504 (set (match_dup 3) (plus:SI (plus:SI (ashiftrt:SI (match_dup 2)
507 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
510 operands[3] = gen_highpart (SImode, operands[0]);
511 operands[0] = gen_lowpart (SImode, operands[0]);
512 operands[4] = gen_highpart (SImode, operands[1]);
513 operands[1] = gen_lowpart (SImode, operands[1]);
514 operands[2] = gen_lowpart (SImode, operands[2]);
516 [(set_attr "conds" "clob")
517 (set_attr "length" "8")
518 (set_attr "type" "multiple")]
521 (define_insn_and_split "*adddi_zesidi_di"
522 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
523 (plus:DI (zero_extend:DI
524 (match_operand:SI 2 "s_register_operand" "r,r"))
525 (match_operand:DI 1 "s_register_operand" "0,r")))
526 (clobber (reg:CC CC_REGNUM))]
529 "TARGET_32BIT && reload_completed"
530 [(parallel [(set (reg:CC_C CC_REGNUM)
531 (compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
533 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
534 (set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (const_int 0))
535 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
538 operands[3] = gen_highpart (SImode, operands[0]);
539 operands[0] = gen_lowpart (SImode, operands[0]);
540 operands[4] = gen_highpart (SImode, operands[1]);
541 operands[1] = gen_lowpart (SImode, operands[1]);
542 operands[2] = gen_lowpart (SImode, operands[2]);
544 [(set_attr "conds" "clob")
545 (set_attr "length" "8")
546 (set_attr "type" "multiple")]
549 (define_expand "addv<mode>4"
550 [(match_operand:SIDI 0 "register_operand")
551 (match_operand:SIDI 1 "register_operand")
552 (match_operand:SIDI 2 "register_operand")
553 (match_operand 3 "")]
556 emit_insn (gen_add<mode>3_compareV (operands[0], operands[1], operands[2]));
557 arm_gen_unlikely_cbranch (NE, CC_Vmode, operands[3]);
562 (define_expand "uaddv<mode>4"
563 [(match_operand:SIDI 0 "register_operand")
564 (match_operand:SIDI 1 "register_operand")
565 (match_operand:SIDI 2 "register_operand")
566 (match_operand 3 "")]
569 emit_insn (gen_add<mode>3_compareC (operands[0], operands[1], operands[2]));
570 arm_gen_unlikely_cbranch (NE, CC_Cmode, operands[3]);
575 (define_expand "addsi3"
576 [(set (match_operand:SI 0 "s_register_operand" "")
577 (plus:SI (match_operand:SI 1 "s_register_operand" "")
578 (match_operand:SI 2 "reg_or_int_operand" "")))]
581 if (TARGET_32BIT && CONST_INT_P (operands[2]))
583 arm_split_constant (PLUS, SImode, NULL_RTX,
584 INTVAL (operands[2]), operands[0], operands[1],
585 optimize && can_create_pseudo_p ());
591 ; If there is a scratch available, this will be faster than synthesizing the
594 [(match_scratch:SI 3 "r")
595 (set (match_operand:SI 0 "arm_general_register_operand" "")
596 (plus:SI (match_operand:SI 1 "arm_general_register_operand" "")
597 (match_operand:SI 2 "const_int_operand" "")))]
599 !(const_ok_for_arm (INTVAL (operands[2]))
600 || const_ok_for_arm (-INTVAL (operands[2])))
601 && const_ok_for_arm (~INTVAL (operands[2]))"
602 [(set (match_dup 3) (match_dup 2))
603 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))]
607 ;; The r/r/k alternative is required when reloading the address
608 ;; (plus (reg rN) (reg sp)) into (reg rN). In this case reload will
609 ;; put the duplicated register first, and not try the commutative version.
610 (define_insn_and_split "*arm_addsi3"
611 [(set (match_operand:SI 0 "s_register_operand" "=rk,l,l ,l ,r ,k ,r,k ,r ,k ,r ,k,k,r ,k ,r")
612 (plus:SI (match_operand:SI 1 "s_register_operand" "%0 ,l,0 ,l ,rk,k ,r,r ,rk,k ,rk,k,r,rk,k ,rk")
613 (match_operand:SI 2 "reg_or_int_operand" "rk ,l,Py,Pd,rI,rI,k,rI,Pj,Pj,L ,L,L,PJ,PJ,?n")))]
629 subw%?\\t%0, %1, #%n2
630 subw%?\\t%0, %1, #%n2
633 && CONST_INT_P (operands[2])
634 && !const_ok_for_op (INTVAL (operands[2]), PLUS)
635 && (reload_completed || !arm_eliminable_register (operands[1]))"
636 [(clobber (const_int 0))]
638 arm_split_constant (PLUS, SImode, curr_insn,
639 INTVAL (operands[2]), operands[0],
643 [(set_attr "length" "2,4,4,4,4,4,4,4,4,4,4,4,4,4,4,16")
644 (set_attr "predicable" "yes")
645 (set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no,no,no,no,no,no,no,no")
646 (set_attr "arch" "t2,t2,t2,t2,*,*,*,a,t2,t2,*,*,a,t2,t2,*")
647 (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
648 (const_string "alu_imm")
649 (const_string "alu_sreg")))
653 (define_insn_and_split "adddi3_compareV"
654 [(set (reg:CC_V CC_REGNUM)
657 (sign_extend:TI (match_operand:DI 1 "register_operand" "r"))
658 (sign_extend:TI (match_operand:DI 2 "register_operand" "r")))
659 (sign_extend:TI (plus:DI (match_dup 1) (match_dup 2)))))
660 (set (match_operand:DI 0 "register_operand" "=&r")
661 (plus:DI (match_dup 1) (match_dup 2)))]
664 "&& reload_completed"
665 [(parallel [(set (reg:CC_C CC_REGNUM)
666 (compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
668 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
669 (parallel [(set (reg:CC_V CC_REGNUM)
672 (sign_extend:DI (match_dup 4))
673 (sign_extend:DI (match_dup 5)))
674 (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))
675 (plus:DI (sign_extend:DI
676 (plus:SI (match_dup 4) (match_dup 5)))
677 (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))))
678 (set (match_dup 3) (plus:SI (plus:SI
679 (match_dup 4) (match_dup 5))
680 (ltu:SI (reg:CC_C CC_REGNUM)
684 operands[3] = gen_highpart (SImode, operands[0]);
685 operands[0] = gen_lowpart (SImode, operands[0]);
686 operands[4] = gen_highpart (SImode, operands[1]);
687 operands[1] = gen_lowpart (SImode, operands[1]);
688 operands[5] = gen_highpart (SImode, operands[2]);
689 operands[2] = gen_lowpart (SImode, operands[2]);
691 [(set_attr "conds" "set")
692 (set_attr "length" "8")
693 (set_attr "type" "multiple")]
696 (define_insn "addsi3_compareV"
697 [(set (reg:CC_V CC_REGNUM)
700 (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
701 (sign_extend:DI (match_operand:SI 2 "register_operand" "r")))
702 (sign_extend:DI (plus:SI (match_dup 1) (match_dup 2)))))
703 (set (match_operand:SI 0 "register_operand" "=r")
704 (plus:SI (match_dup 1) (match_dup 2)))]
706 "adds%?\\t%0, %1, %2"
707 [(set_attr "conds" "set")
708 (set_attr "type" "alus_sreg")]
711 (define_insn "*addsi3_compareV_upper"
712 [(set (reg:CC_V CC_REGNUM)
716 (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
717 (sign_extend:DI (match_operand:SI 2 "register_operand" "r")))
718 (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))
719 (plus:DI (sign_extend:DI
720 (plus:SI (match_dup 1) (match_dup 2)))
721 (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))))
722 (set (match_operand:SI 0 "register_operand" "=r")
724 (plus:SI (match_dup 1) (match_dup 2))
725 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
727 "adcs%?\\t%0, %1, %2"
728 [(set_attr "conds" "set")
729 (set_attr "type" "adcs_reg")]
732 (define_insn_and_split "adddi3_compareC"
733 [(set (reg:CC_C CC_REGNUM)
736 (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
737 (zero_extend:TI (match_operand:DI 2 "register_operand" "r")))
738 (zero_extend:TI (plus:DI (match_dup 1) (match_dup 2)))))
739 (set (match_operand:DI 0 "register_operand" "=&r")
740 (plus:DI (match_dup 1) (match_dup 2)))]
743 "&& reload_completed"
744 [(parallel [(set (reg:CC_C CC_REGNUM)
745 (compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
747 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
748 (parallel [(set (reg:CC_C CC_REGNUM)
751 (zero_extend:DI (match_dup 4))
752 (zero_extend:DI (match_dup 5)))
753 (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))
754 (plus:DI (zero_extend:DI
755 (plus:SI (match_dup 4) (match_dup 5)))
756 (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))))
757 (set (match_dup 3) (plus:SI
758 (plus:SI (match_dup 4) (match_dup 5))
759 (ltu:SI (reg:CC_C CC_REGNUM)
763 operands[3] = gen_highpart (SImode, operands[0]);
764 operands[0] = gen_lowpart (SImode, operands[0]);
765 operands[4] = gen_highpart (SImode, operands[1]);
766 operands[5] = gen_highpart (SImode, operands[2]);
767 operands[1] = gen_lowpart (SImode, operands[1]);
768 operands[2] = gen_lowpart (SImode, operands[2]);
770 [(set_attr "conds" "set")
771 (set_attr "length" "8")
772 (set_attr "type" "multiple")]
775 (define_insn "*addsi3_compareC_upper"
776 [(set (reg:CC_C CC_REGNUM)
780 (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
781 (zero_extend:DI (match_operand:SI 2 "register_operand" "r")))
782 (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))
783 (plus:DI (zero_extend:DI
784 (plus:SI (match_dup 1) (match_dup 2)))
785 (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))))
786 (set (match_operand:SI 0 "register_operand" "=r")
788 (plus:SI (match_dup 1) (match_dup 2))
789 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
791 "adcs%?\\t%0, %1, %2"
792 [(set_attr "conds" "set")
793 (set_attr "type" "adcs_reg")]
796 (define_insn "addsi3_compareC"
797 [(set (reg:CC_C CC_REGNUM)
800 (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
801 (zero_extend:DI (match_operand:SI 2 "register_operand" "r")))
803 (plus:SI (match_dup 1) (match_dup 2)))))
804 (set (match_operand:SI 0 "register_operand" "=r")
805 (plus:SI (match_dup 1) (match_dup 2)))]
807 "adds%?\\t%0, %1, %2"
808 [(set_attr "conds" "set")
809 (set_attr "type" "alus_sreg")]
812 (define_insn "addsi3_compare0"
813 [(set (reg:CC_NOOV CC_REGNUM)
815 (plus:SI (match_operand:SI 1 "s_register_operand" "r, r,r")
816 (match_operand:SI 2 "arm_add_operand" "I,L,r"))
818 (set (match_operand:SI 0 "s_register_operand" "=r,r,r")
819 (plus:SI (match_dup 1) (match_dup 2)))]
823 subs%?\\t%0, %1, #%n2
825 [(set_attr "conds" "set")
826 (set_attr "type" "alus_imm,alus_imm,alus_sreg")]
829 (define_insn "*addsi3_compare0_scratch"
830 [(set (reg:CC_NOOV CC_REGNUM)
832 (plus:SI (match_operand:SI 0 "s_register_operand" "r, r, r")
833 (match_operand:SI 1 "arm_add_operand" "I,L, r"))
840 [(set_attr "conds" "set")
841 (set_attr "predicable" "yes")
842 (set_attr "type" "alus_imm,alus_imm,alus_sreg")]
845 (define_insn "*compare_negsi_si"
846 [(set (reg:CC_Z CC_REGNUM)
848 (neg:SI (match_operand:SI 0 "s_register_operand" "l,r"))
849 (match_operand:SI 1 "s_register_operand" "l,r")))]
852 [(set_attr "conds" "set")
853 (set_attr "predicable" "yes")
854 (set_attr "arch" "t2,*")
855 (set_attr "length" "2,4")
856 (set_attr "predicable_short_it" "yes,no")
857 (set_attr "type" "alus_sreg")]
860 ;; This is the canonicalization of subsi3_compare when the
861 ;; addend is a constant.
862 (define_insn "cmpsi2_addneg"
863 [(set (reg:CC CC_REGNUM)
865 (match_operand:SI 1 "s_register_operand" "r,r")
866 (match_operand:SI 2 "arm_addimm_operand" "I,L")))
867 (set (match_operand:SI 0 "s_register_operand" "=r,r")
868 (plus:SI (match_dup 1)
869 (match_operand:SI 3 "arm_addimm_operand" "L,I")))]
871 && (INTVAL (operands[2])
872 == trunc_int_for_mode (-INTVAL (operands[3]), SImode))"
874 /* For 0 and INT_MIN it is essential that we use subs, as adds will result
875 in different condition codes (like cmn rather than like cmp), so that
876 alternative comes first. Both alternatives can match for any 0x??000000
877 where except for 0 and INT_MIN it doesn't matter what we choose, and also
878 for -1 and 1 with TARGET_THUMB2, in that case prefer instruction with #1
880 if (which_alternative == 0 && operands[3] != const1_rtx)
881 return "subs%?\\t%0, %1, #%n3";
883 return "adds%?\\t%0, %1, %3";
885 [(set_attr "conds" "set")
886 (set_attr "type" "alus_sreg")]
889 ;; Convert the sequence
891 ;; cmn rd, #1 (equivalent to cmp rd, #-1)
895 ;; bcs dest ((unsigned)rn >= 1)
896 ;; similarly for the beq variant using bcc.
897 ;; This is a common looping idiom (while (n--))
899 [(set (match_operand:SI 0 "arm_general_register_operand" "")
900 (plus:SI (match_operand:SI 1 "arm_general_register_operand" "")
902 (set (match_operand 2 "cc_register" "")
903 (compare (match_dup 0) (const_int -1)))
905 (if_then_else (match_operator 3 "equality_operator"
906 [(match_dup 2) (const_int 0)])
907 (match_operand 4 "" "")
908 (match_operand 5 "" "")))]
909 "TARGET_32BIT && peep2_reg_dead_p (3, operands[2])"
913 (match_dup 1) (const_int 1)))
914 (set (match_dup 0) (plus:SI (match_dup 1) (const_int -1)))])
916 (if_then_else (match_op_dup 3 [(match_dup 2) (const_int 0)])
919 "operands[2] = gen_rtx_REG (CCmode, CC_REGNUM);
920 operands[3] = gen_rtx_fmt_ee ((GET_CODE (operands[3]) == NE
923 operands[2], const0_rtx);"
926 ;; The next four insns work because they compare the result with one of
927 ;; the operands, and we know that the use of the condition code is
928 ;; either GEU or LTU, so we can use the carry flag from the addition
929 ;; instead of doing the compare a second time.
930 (define_insn "*addsi3_compare_op1"
931 [(set (reg:CC_C CC_REGNUM)
933 (plus:SI (match_operand:SI 1 "s_register_operand" "r,r,r")
934 (match_operand:SI 2 "arm_add_operand" "I,L,r"))
936 (set (match_operand:SI 0 "s_register_operand" "=r,r,r")
937 (plus:SI (match_dup 1) (match_dup 2)))]
941 subs%?\\t%0, %1, #%n2
943 [(set_attr "conds" "set")
944 (set_attr "type" "alus_imm,alus_imm,alus_sreg")]
947 (define_insn "*addsi3_compare_op2"
948 [(set (reg:CC_C CC_REGNUM)
950 (plus:SI (match_operand:SI 1 "s_register_operand" "r,r,r")
951 (match_operand:SI 2 "arm_add_operand" "I,L,r"))
953 (set (match_operand:SI 0 "s_register_operand" "=r,r,r")
954 (plus:SI (match_dup 1) (match_dup 2)))]
958 subs%?\\t%0, %1, #%n2
960 [(set_attr "conds" "set")
961 (set_attr "type" "alus_imm,alus_imm,alus_sreg")]
964 (define_insn "*compare_addsi2_op0"
965 [(set (reg:CC_C CC_REGNUM)
967 (plus:SI (match_operand:SI 0 "s_register_operand" "l,l,r,r,r")
968 (match_operand:SI 1 "arm_add_operand" "Pv,l,I,L,r"))
977 [(set_attr "conds" "set")
978 (set_attr "predicable" "yes")
979 (set_attr "arch" "t2,t2,*,*,*")
980 (set_attr "predicable_short_it" "yes,yes,no,no,no")
981 (set_attr "length" "2,2,4,4,4")
982 (set_attr "type" "alus_imm,alus_sreg,alus_imm,alus_imm,alus_sreg")]
985 (define_insn "*compare_addsi2_op1"
986 [(set (reg:CC_C CC_REGNUM)
988 (plus:SI (match_operand:SI 0 "s_register_operand" "l,l,r,r,r")
989 (match_operand:SI 1 "arm_add_operand" "Pv,l,I,L,r"))
998 [(set_attr "conds" "set")
999 (set_attr "predicable" "yes")
1000 (set_attr "arch" "t2,t2,*,*,*")
1001 (set_attr "predicable_short_it" "yes,yes,no,no,no")
1002 (set_attr "length" "2,2,4,4,4")
1003 (set_attr "type" "alus_imm,alus_sreg,alus_imm,alus_imm,alus_sreg")]
1006 (define_insn "*addsi3_carryin_<optab>"
1007 [(set (match_operand:SI 0 "s_register_operand" "=l,r,r")
1008 (plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%l,r,r")
1009 (match_operand:SI 2 "arm_not_operand" "0,rI,K"))
1010 (LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))))]
1015 sbc%?\\t%0, %1, #%B2"
1016 [(set_attr "conds" "use")
1017 (set_attr "predicable" "yes")
1018 (set_attr "arch" "t2,*,*")
1019 (set_attr "length" "4")
1020 (set_attr "predicable_short_it" "yes,no,no")
1021 (set_attr "type" "adc_reg,adc_reg,adc_imm")]
1024 (define_insn "*addsi3_carryin_alt2_<optab>"
1025 [(set (match_operand:SI 0 "s_register_operand" "=l,r,r")
1026 (plus:SI (plus:SI (LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))
1027 (match_operand:SI 1 "s_register_operand" "%l,r,r"))
1028 (match_operand:SI 2 "arm_rhs_operand" "l,rI,K")))]
1033 sbc%?\\t%0, %1, #%B2"
1034 [(set_attr "conds" "use")
1035 (set_attr "predicable" "yes")
1036 (set_attr "arch" "t2,*,*")
1037 (set_attr "length" "4")
1038 (set_attr "predicable_short_it" "yes,no,no")
1039 (set_attr "type" "adc_reg,adc_reg,adc_imm")]
1042 (define_insn "*addsi3_carryin_shift_<optab>"
1043 [(set (match_operand:SI 0 "s_register_operand" "=r")
1045 (match_operator:SI 2 "shift_operator"
1046 [(match_operand:SI 3 "s_register_operand" "r")
1047 (match_operand:SI 4 "reg_or_int_operand" "rM")])
1048 (match_operand:SI 1 "s_register_operand" "r"))
1049 (LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))))]
1051 "adc%?\\t%0, %1, %3%S2"
1052 [(set_attr "conds" "use")
1053 (set_attr "predicable" "yes")
1054 (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
1055 (const_string "alu_shift_imm")
1056 (const_string "alu_shift_reg")))]
1059 (define_insn "*addsi3_carryin_clobercc_<optab>"
1060 [(set (match_operand:SI 0 "s_register_operand" "=r")
1061 (plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%r")
1062 (match_operand:SI 2 "arm_rhs_operand" "rI"))
1063 (LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))))
1064 (clobber (reg:CC CC_REGNUM))]
1066 "adcs%?\\t%0, %1, %2"
1067 [(set_attr "conds" "set")
1068 (set_attr "type" "adcs_reg")]
1071 (define_expand "subv<mode>4"
1072 [(match_operand:SIDI 0 "register_operand")
1073 (match_operand:SIDI 1 "register_operand")
1074 (match_operand:SIDI 2 "register_operand")
1075 (match_operand 3 "")]
1078 emit_insn (gen_sub<mode>3_compare1 (operands[0], operands[1], operands[2]));
1079 arm_gen_unlikely_cbranch (NE, CC_Vmode, operands[3]);
1084 (define_expand "usubv<mode>4"
1085 [(match_operand:SIDI 0 "register_operand")
1086 (match_operand:SIDI 1 "register_operand")
1087 (match_operand:SIDI 2 "register_operand")
1088 (match_operand 3 "")]
1091 emit_insn (gen_sub<mode>3_compare1 (operands[0], operands[1], operands[2]));
1092 arm_gen_unlikely_cbranch (LTU, CCmode, operands[3]);
1097 (define_insn_and_split "subdi3_compare1"
1098 [(set (reg:CC CC_REGNUM)
1100 (match_operand:DI 1 "register_operand" "r")
1101 (match_operand:DI 2 "register_operand" "r")))
1102 (set (match_operand:DI 0 "register_operand" "=&r")
1103 (minus:DI (match_dup 1) (match_dup 2)))]
1106 "&& reload_completed"
1107 [(parallel [(set (reg:CC CC_REGNUM)
1108 (compare:CC (match_dup 1) (match_dup 2)))
1109 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
1110 (parallel [(set (reg:CC CC_REGNUM)
1111 (compare:CC (match_dup 4) (match_dup 5)))
1112 (set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
1113 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))])]
1115 operands[3] = gen_highpart (SImode, operands[0]);
1116 operands[0] = gen_lowpart (SImode, operands[0]);
1117 operands[4] = gen_highpart (SImode, operands[1]);
1118 operands[1] = gen_lowpart (SImode, operands[1]);
1119 operands[5] = gen_highpart (SImode, operands[2]);
1120 operands[2] = gen_lowpart (SImode, operands[2]);
1122 [(set_attr "conds" "set")
1123 (set_attr "length" "8")
1124 (set_attr "type" "multiple")]
1127 (define_insn "subsi3_compare1"
1128 [(set (reg:CC CC_REGNUM)
1130 (match_operand:SI 1 "register_operand" "r")
1131 (match_operand:SI 2 "register_operand" "r")))
1132 (set (match_operand:SI 0 "register_operand" "=r")
1133 (minus:SI (match_dup 1) (match_dup 2)))]
1135 "subs%?\\t%0, %1, %2"
1136 [(set_attr "conds" "set")
1137 (set_attr "type" "alus_sreg")]
1140 (define_insn "*subsi3_carryin"
1141 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
1142 (minus:SI (minus:SI (match_operand:SI 1 "reg_or_int_operand" "r,I,Pz")
1143 (match_operand:SI 2 "s_register_operand" "r,r,r"))
1144 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
1149 sbc%?\\t%0, %2, %2, lsl #1"
1150 [(set_attr "conds" "use")
1151 (set_attr "arch" "*,a,t2")
1152 (set_attr "predicable" "yes")
1153 (set_attr "type" "adc_reg,adc_imm,alu_shift_imm")]
1156 (define_insn "*subsi3_carryin_const"
1157 [(set (match_operand:SI 0 "s_register_operand" "=r")
1158 (minus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "r")
1159 (match_operand:SI 2 "arm_neg_immediate_operand" "L"))
1160 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
1162 "sbc\\t%0, %1, #%n2"
1163 [(set_attr "conds" "use")
1164 (set_attr "type" "adc_imm")]
1167 (define_insn "*subsi3_carryin_const0"
1168 [(set (match_operand:SI 0 "s_register_operand" "=r")
1169 (minus:SI (match_operand:SI 1 "s_register_operand" "r")
1170 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
1173 [(set_attr "conds" "use")
1174 (set_attr "type" "adc_imm")]
1177 (define_insn "*subsi3_carryin_compare"
1178 [(set (reg:CC CC_REGNUM)
1179 (compare:CC (match_operand:SI 1 "s_register_operand" "r")
1180 (match_operand:SI 2 "s_register_operand" "r")))
1181 (set (match_operand:SI 0 "s_register_operand" "=r")
1182 (minus:SI (minus:SI (match_dup 1)
1184 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
1187 [(set_attr "conds" "set")
1188 (set_attr "type" "adcs_reg")]
1191 (define_insn "*subsi3_carryin_compare_const"
1192 [(set (reg:CC CC_REGNUM)
1193 (compare:CC (match_operand:SI 1 "reg_or_int_operand" "r")
1194 (match_operand:SI 2 "const_int_I_operand" "I")))
1195 (set (match_operand:SI 0 "s_register_operand" "=r")
1196 (minus:SI (plus:SI (match_dup 1)
1197 (match_operand:SI 3 "arm_neg_immediate_operand" "L"))
1198 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
1200 && (INTVAL (operands[2])
1201 == trunc_int_for_mode (-INTVAL (operands[3]), SImode))"
1202 "sbcs\\t%0, %1, #%n3"
1203 [(set_attr "conds" "set")
1204 (set_attr "type" "adcs_imm")]
1207 (define_insn "*subsi3_carryin_compare_const0"
1208 [(set (reg:CC CC_REGNUM)
1209 (compare:CC (match_operand:SI 1 "reg_or_int_operand" "r")
1211 (set (match_operand:SI 0 "s_register_operand" "=r")
1212 (minus:SI (match_dup 1)
1213 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
1216 [(set_attr "conds" "set")
1217 (set_attr "type" "adcs_imm")]
1220 (define_insn "*subsi3_carryin_shift"
1221 [(set (match_operand:SI 0 "s_register_operand" "=r")
1223 (match_operand:SI 1 "s_register_operand" "r")
1224 (match_operator:SI 2 "shift_operator"
1225 [(match_operand:SI 3 "s_register_operand" "r")
1226 (match_operand:SI 4 "reg_or_int_operand" "rM")]))
1227 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
1229 "sbc%?\\t%0, %1, %3%S2"
1230 [(set_attr "conds" "use")
1231 (set_attr "predicable" "yes")
1232 (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
1233 (const_string "alu_shift_imm")
1234 (const_string "alu_shift_reg")))]
1237 (define_insn "*rsbsi3_carryin_shift"
1238 [(set (match_operand:SI 0 "s_register_operand" "=r")
1240 (match_operator:SI 2 "shift_operator"
1241 [(match_operand:SI 3 "s_register_operand" "r")
1242 (match_operand:SI 4 "reg_or_int_operand" "rM")])
1243 (match_operand:SI 1 "s_register_operand" "r"))
1244 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
1246 "rsc%?\\t%0, %1, %3%S2"
1247 [(set_attr "conds" "use")
1248 (set_attr "predicable" "yes")
1249 (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
1250 (const_string "alu_shift_imm")
1251 (const_string "alu_shift_reg")))]
1254 ; transform ((x << y) - 1) to ~(~(x-1) << y) Where X is a constant.
1256 [(set (match_operand:SI 0 "s_register_operand" "")
1257 (plus:SI (ashift:SI (match_operand:SI 1 "const_int_operand" "")
1258 (match_operand:SI 2 "s_register_operand" ""))
1260 (clobber (match_operand:SI 3 "s_register_operand" ""))]
1262 [(set (match_dup 3) (match_dup 1))
1263 (set (match_dup 0) (not:SI (ashift:SI (match_dup 3) (match_dup 2))))]
1265 operands[1] = GEN_INT (~(INTVAL (operands[1]) - 1));
1268 (define_expand "addsf3"
1269 [(set (match_operand:SF 0 "s_register_operand" "")
1270 (plus:SF (match_operand:SF 1 "s_register_operand" "")
1271 (match_operand:SF 2 "s_register_operand" "")))]
1272 "TARGET_32BIT && TARGET_HARD_FLOAT"
1276 (define_expand "adddf3"
1277 [(set (match_operand:DF 0 "s_register_operand" "")
1278 (plus:DF (match_operand:DF 1 "s_register_operand" "")
1279 (match_operand:DF 2 "s_register_operand" "")))]
1280 "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
1284 (define_expand "subdi3"
1286 [(set (match_operand:DI 0 "s_register_operand" "")
1287 (minus:DI (match_operand:DI 1 "s_register_operand" "")
1288 (match_operand:DI 2 "s_register_operand" "")))
1289 (clobber (reg:CC CC_REGNUM))])]
1294 if (!REG_P (operands[1]))
1295 operands[1] = force_reg (DImode, operands[1]);
1296 if (!REG_P (operands[2]))
1297 operands[2] = force_reg (DImode, operands[2]);
1302 (define_insn_and_split "*arm_subdi3"
1303 [(set (match_operand:DI 0 "arm_general_register_operand" "=&r,&r,&r")
1304 (minus:DI (match_operand:DI 1 "arm_general_register_operand" "0,r,0")
1305 (match_operand:DI 2 "arm_general_register_operand" "r,0,0")))
1306 (clobber (reg:CC CC_REGNUM))]
1307 "TARGET_32BIT && !TARGET_NEON"
1308 "#" ; "subs\\t%Q0, %Q1, %Q2\;sbc\\t%R0, %R1, %R2"
1309 "&& (!TARGET_IWMMXT || reload_completed)"
1310 [(parallel [(set (reg:CC CC_REGNUM)
1311 (compare:CC (match_dup 1) (match_dup 2)))
1312 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
1313 (set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
1314 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
1316 operands[3] = gen_highpart (SImode, operands[0]);
1317 operands[0] = gen_lowpart (SImode, operands[0]);
1318 operands[4] = gen_highpart (SImode, operands[1]);
1319 operands[1] = gen_lowpart (SImode, operands[1]);
1320 operands[5] = gen_highpart (SImode, operands[2]);
1321 operands[2] = gen_lowpart (SImode, operands[2]);
1323 [(set_attr "conds" "clob")
1324 (set_attr "length" "8")
1325 (set_attr "type" "multiple")]
1328 (define_insn_and_split "*subdi_di_zesidi"
1329 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
1330 (minus:DI (match_operand:DI 1 "s_register_operand" "0,r")
1332 (match_operand:SI 2 "s_register_operand" "r,r"))))
1333 (clobber (reg:CC CC_REGNUM))]
1335 "#" ; "subs\\t%Q0, %Q1, %2\;sbc\\t%R0, %R1, #0"
1336 "&& reload_completed"
1337 [(parallel [(set (reg:CC CC_REGNUM)
1338 (compare:CC (match_dup 1) (match_dup 2)))
1339 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
1340 (set (match_dup 3) (minus:SI (match_dup 4)
1341 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
1343 operands[3] = gen_highpart (SImode, operands[0]);
1344 operands[0] = gen_lowpart (SImode, operands[0]);
1345 operands[4] = gen_highpart (SImode, operands[1]);
1346 operands[1] = gen_lowpart (SImode, operands[1]);
1348 [(set_attr "conds" "clob")
1349 (set_attr "length" "8")
1350 (set_attr "type" "multiple")]
1353 (define_insn_and_split "*subdi_di_sesidi"
1354 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
1355 (minus:DI (match_operand:DI 1 "s_register_operand" "0,r")
1357 (match_operand:SI 2 "s_register_operand" "r,r"))))
1358 (clobber (reg:CC CC_REGNUM))]
1360 "#" ; "subs\\t%Q0, %Q1, %2\;sbc\\t%R0, %R1, %2, asr #31"
1361 "&& reload_completed"
1362 [(parallel [(set (reg:CC CC_REGNUM)
1363 (compare:CC (match_dup 1) (match_dup 2)))
1364 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
1365 (set (match_dup 3) (minus:SI (minus:SI (match_dup 4)
1366 (ashiftrt:SI (match_dup 2)
1368 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
1370 operands[3] = gen_highpart (SImode, operands[0]);
1371 operands[0] = gen_lowpart (SImode, operands[0]);
1372 operands[4] = gen_highpart (SImode, operands[1]);
1373 operands[1] = gen_lowpart (SImode, operands[1]);
1375 [(set_attr "conds" "clob")
1376 (set_attr "length" "8")
1377 (set_attr "type" "multiple")]
1380 (define_insn_and_split "*subdi_zesidi_di"
1381 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
1382 (minus:DI (zero_extend:DI
1383 (match_operand:SI 2 "s_register_operand" "r,r"))
1384 (match_operand:DI 1 "s_register_operand" "0,r")))
1385 (clobber (reg:CC CC_REGNUM))]
1387 "#" ; "rsbs\\t%Q0, %Q1, %2\;rsc\\t%R0, %R1, #0"
1389 ; "subs\\t%Q0, %2, %Q1\;rsc\\t%R0, %R1, #0"
1390 "&& reload_completed"
1391 [(parallel [(set (reg:CC CC_REGNUM)
1392 (compare:CC (match_dup 2) (match_dup 1)))
1393 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 1)))])
1394 (set (match_dup 3) (minus:SI (minus:SI (const_int 0) (match_dup 4))
1395 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
1397 operands[3] = gen_highpart (SImode, operands[0]);
1398 operands[0] = gen_lowpart (SImode, operands[0]);
1399 operands[4] = gen_highpart (SImode, operands[1]);
1400 operands[1] = gen_lowpart (SImode, operands[1]);
1402 [(set_attr "conds" "clob")
1403 (set_attr "length" "8")
1404 (set_attr "type" "multiple")]
1407 (define_insn_and_split "*subdi_sesidi_di"
1408 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
1409 (minus:DI (sign_extend:DI
1410 (match_operand:SI 2 "s_register_operand" "r,r"))
1411 (match_operand:DI 1 "s_register_operand" "0,r")))
1412 (clobber (reg:CC CC_REGNUM))]
1414 "#" ; "rsbs\\t%Q0, %Q1, %2\;rsc\\t%R0, %R1, %2, asr #31"
1416 ; "subs\\t%Q0, %2, %Q1\;rsc\\t%R0, %R1, %2, asr #31"
1417 "&& reload_completed"
1418 [(parallel [(set (reg:CC CC_REGNUM)
1419 (compare:CC (match_dup 2) (match_dup 1)))
1420 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 1)))])
1421 (set (match_dup 3) (minus:SI (minus:SI
1422 (ashiftrt:SI (match_dup 2)
1425 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
1427 operands[3] = gen_highpart (SImode, operands[0]);
1428 operands[0] = gen_lowpart (SImode, operands[0]);
1429 operands[4] = gen_highpart (SImode, operands[1]);
1430 operands[1] = gen_lowpart (SImode, operands[1]);
1432 [(set_attr "conds" "clob")
1433 (set_attr "length" "8")
1434 (set_attr "type" "multiple")]
1437 (define_insn_and_split "*subdi_zesidi_zesidi"
1438 [(set (match_operand:DI 0 "s_register_operand" "=r")
1439 (minus:DI (zero_extend:DI
1440 (match_operand:SI 1 "s_register_operand" "r"))
1442 (match_operand:SI 2 "s_register_operand" "r"))))
1443 (clobber (reg:CC CC_REGNUM))]
1445 "#" ; "subs\\t%Q0, %1, %2\;sbc\\t%R0, %1, %1"
1446 "&& reload_completed"
1447 [(parallel [(set (reg:CC CC_REGNUM)
1448 (compare:CC (match_dup 1) (match_dup 2)))
1449 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
1450 (set (match_dup 3) (minus:SI (minus:SI (match_dup 1) (match_dup 1))
1451 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
1453 operands[3] = gen_highpart (SImode, operands[0]);
1454 operands[0] = gen_lowpart (SImode, operands[0]);
1456 [(set_attr "conds" "clob")
1457 (set_attr "length" "8")
1458 (set_attr "type" "multiple")]
1461 (define_expand "subsi3"
1462 [(set (match_operand:SI 0 "s_register_operand" "")
1463 (minus:SI (match_operand:SI 1 "reg_or_int_operand" "")
1464 (match_operand:SI 2 "s_register_operand" "")))]
1467 if (CONST_INT_P (operands[1]))
1471 if (DONT_EARLY_SPLIT_CONSTANT (INTVAL (operands[1]), MINUS))
1472 operands[1] = force_reg (SImode, operands[1]);
1475 arm_split_constant (MINUS, SImode, NULL_RTX,
1476 INTVAL (operands[1]), operands[0],
1478 optimize && can_create_pseudo_p ());
1482 else /* TARGET_THUMB1 */
1483 operands[1] = force_reg (SImode, operands[1]);
1488 ; ??? Check Thumb-2 split length
1489 (define_insn_and_split "*arm_subsi3_insn"
1490 [(set (match_operand:SI 0 "s_register_operand" "=l,l ,l ,l ,r,r,r,rk,r")
1491 (minus:SI (match_operand:SI 1 "reg_or_int_operand" "l ,0 ,l ,Pz,I,r,r,k ,?n")
1492 (match_operand:SI 2 "reg_or_int_operand" "l ,Py,Pd,l ,r,I,r,r ,r")))]
1504 "&& (CONST_INT_P (operands[1])
1505 && !const_ok_for_arm (INTVAL (operands[1])))"
1506 [(clobber (const_int 0))]
1508 arm_split_constant (MINUS, SImode, curr_insn,
1509 INTVAL (operands[1]), operands[0], operands[2], 0);
1512 [(set_attr "length" "4,4,4,4,4,4,4,4,16")
1513 (set_attr "arch" "t2,t2,t2,t2,*,*,*,*,*")
1514 (set_attr "predicable" "yes")
1515 (set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no")
1516 (set_attr "type" "alu_sreg,alu_sreg,alu_sreg,alu_sreg,alu_imm,alu_imm,alu_sreg,alu_sreg,multiple")]
1520 [(match_scratch:SI 3 "r")
1521 (set (match_operand:SI 0 "arm_general_register_operand" "")
1522 (minus:SI (match_operand:SI 1 "const_int_operand" "")
1523 (match_operand:SI 2 "arm_general_register_operand" "")))]
1525 && !const_ok_for_arm (INTVAL (operands[1]))
1526 && const_ok_for_arm (~INTVAL (operands[1]))"
1527 [(set (match_dup 3) (match_dup 1))
1528 (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 2)))]
1532 (define_insn "subsi3_compare0"
1533 [(set (reg:CC_NOOV CC_REGNUM)
1535 (minus:SI (match_operand:SI 1 "arm_rhs_operand" "r,r,I")
1536 (match_operand:SI 2 "arm_rhs_operand" "I,r,r"))
1538 (set (match_operand:SI 0 "s_register_operand" "=r,r,r")
1539 (minus:SI (match_dup 1) (match_dup 2)))]
1544 rsbs%?\\t%0, %2, %1"
1545 [(set_attr "conds" "set")
1546 (set_attr "type" "alus_imm,alus_sreg,alus_sreg")]
1549 (define_insn "subsi3_compare"
1550 [(set (reg:CC CC_REGNUM)
1551 (compare:CC (match_operand:SI 1 "arm_rhs_operand" "r,r,I")
1552 (match_operand:SI 2 "arm_rhs_operand" "I,r,r")))
1553 (set (match_operand:SI 0 "s_register_operand" "=r,r,r")
1554 (minus:SI (match_dup 1) (match_dup 2)))]
1559 rsbs%?\\t%0, %2, %1"
1560 [(set_attr "conds" "set")
1561 (set_attr "type" "alus_imm,alus_sreg,alus_sreg")]
1564 (define_expand "subsf3"
1565 [(set (match_operand:SF 0 "s_register_operand" "")
1566 (minus:SF (match_operand:SF 1 "s_register_operand" "")
1567 (match_operand:SF 2 "s_register_operand" "")))]
1568 "TARGET_32BIT && TARGET_HARD_FLOAT"
1572 (define_expand "subdf3"
1573 [(set (match_operand:DF 0 "s_register_operand" "")
1574 (minus:DF (match_operand:DF 1 "s_register_operand" "")
1575 (match_operand:DF 2 "s_register_operand" "")))]
1576 "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
1581 ;; Multiplication insns
1583 (define_expand "mulhi3"
1584 [(set (match_operand:HI 0 "s_register_operand" "")
1585 (mult:HI (match_operand:HI 1 "s_register_operand" "")
1586 (match_operand:HI 2 "s_register_operand" "")))]
1587 "TARGET_DSP_MULTIPLY"
1590 rtx result = gen_reg_rtx (SImode);
1591 emit_insn (gen_mulhisi3 (result, operands[1], operands[2]));
1592 emit_move_insn (operands[0], gen_lowpart (HImode, result));
1597 (define_expand "mulsi3"
1598 [(set (match_operand:SI 0 "s_register_operand" "")
1599 (mult:SI (match_operand:SI 2 "s_register_operand" "")
1600 (match_operand:SI 1 "s_register_operand" "")))]
1605 ;; Use `&' and then `0' to prevent the operands 0 and 1 being the same
1606 (define_insn "*arm_mulsi3"
1607 [(set (match_operand:SI 0 "s_register_operand" "=&r,&r")
1608 (mult:SI (match_operand:SI 2 "s_register_operand" "r,r")
1609 (match_operand:SI 1 "s_register_operand" "%0,r")))]
1610 "TARGET_32BIT && !arm_arch6"
1611 "mul%?\\t%0, %2, %1"
1612 [(set_attr "type" "mul")
1613 (set_attr "predicable" "yes")]
1616 (define_insn "*arm_mulsi3_v6"
1617 [(set (match_operand:SI 0 "s_register_operand" "=l,l,r")
1618 (mult:SI (match_operand:SI 1 "s_register_operand" "0,l,r")
1619 (match_operand:SI 2 "s_register_operand" "l,0,r")))]
1620 "TARGET_32BIT && arm_arch6"
1621 "mul%?\\t%0, %1, %2"
1622 [(set_attr "type" "mul")
1623 (set_attr "predicable" "yes")
1624 (set_attr "arch" "t2,t2,*")
1625 (set_attr "length" "4")
1626 (set_attr "predicable_short_it" "yes,yes,no")]
1629 (define_insn "*mulsi3_compare0"
1630 [(set (reg:CC_NOOV CC_REGNUM)
1631 (compare:CC_NOOV (mult:SI
1632 (match_operand:SI 2 "s_register_operand" "r,r")
1633 (match_operand:SI 1 "s_register_operand" "%0,r"))
1635 (set (match_operand:SI 0 "s_register_operand" "=&r,&r")
1636 (mult:SI (match_dup 2) (match_dup 1)))]
1637 "TARGET_ARM && !arm_arch6"
1638 "muls%?\\t%0, %2, %1"
1639 [(set_attr "conds" "set")
1640 (set_attr "type" "muls")]
1643 (define_insn "*mulsi3_compare0_v6"
1644 [(set (reg:CC_NOOV CC_REGNUM)
1645 (compare:CC_NOOV (mult:SI
1646 (match_operand:SI 2 "s_register_operand" "r")
1647 (match_operand:SI 1 "s_register_operand" "r"))
1649 (set (match_operand:SI 0 "s_register_operand" "=r")
1650 (mult:SI (match_dup 2) (match_dup 1)))]
1651 "TARGET_ARM && arm_arch6 && optimize_size"
1652 "muls%?\\t%0, %2, %1"
1653 [(set_attr "conds" "set")
1654 (set_attr "type" "muls")]
1657 (define_insn "*mulsi_compare0_scratch"
1658 [(set (reg:CC_NOOV CC_REGNUM)
1659 (compare:CC_NOOV (mult:SI
1660 (match_operand:SI 2 "s_register_operand" "r,r")
1661 (match_operand:SI 1 "s_register_operand" "%0,r"))
1663 (clobber (match_scratch:SI 0 "=&r,&r"))]
1664 "TARGET_ARM && !arm_arch6"
1665 "muls%?\\t%0, %2, %1"
1666 [(set_attr "conds" "set")
1667 (set_attr "type" "muls")]
1670 (define_insn "*mulsi_compare0_scratch_v6"
1671 [(set (reg:CC_NOOV CC_REGNUM)
1672 (compare:CC_NOOV (mult:SI
1673 (match_operand:SI 2 "s_register_operand" "r")
1674 (match_operand:SI 1 "s_register_operand" "r"))
1676 (clobber (match_scratch:SI 0 "=r"))]
1677 "TARGET_ARM && arm_arch6 && optimize_size"
1678 "muls%?\\t%0, %2, %1"
1679 [(set_attr "conds" "set")
1680 (set_attr "type" "muls")]
1683 ;; Unnamed templates to match MLA instruction.
1685 (define_insn "*mulsi3addsi"
1686 [(set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r,&r")
1688 (mult:SI (match_operand:SI 2 "s_register_operand" "r,r,r,r")
1689 (match_operand:SI 1 "s_register_operand" "%0,r,0,r"))
1690 (match_operand:SI 3 "s_register_operand" "r,r,0,0")))]
1691 "TARGET_32BIT && !arm_arch6"
1692 "mla%?\\t%0, %2, %1, %3"
1693 [(set_attr "type" "mla")
1694 (set_attr "predicable" "yes")]
1697 (define_insn "*mulsi3addsi_v6"
1698 [(set (match_operand:SI 0 "s_register_operand" "=r")
1700 (mult:SI (match_operand:SI 2 "s_register_operand" "r")
1701 (match_operand:SI 1 "s_register_operand" "r"))
1702 (match_operand:SI 3 "s_register_operand" "r")))]
1703 "TARGET_32BIT && arm_arch6"
1704 "mla%?\\t%0, %2, %1, %3"
1705 [(set_attr "type" "mla")
1706 (set_attr "predicable" "yes")]
1709 (define_insn "*mulsi3addsi_compare0"
1710 [(set (reg:CC_NOOV CC_REGNUM)
1713 (match_operand:SI 2 "s_register_operand" "r,r,r,r")
1714 (match_operand:SI 1 "s_register_operand" "%0,r,0,r"))
1715 (match_operand:SI 3 "s_register_operand" "r,r,0,0"))
1717 (set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r,&r")
1718 (plus:SI (mult:SI (match_dup 2) (match_dup 1))
1720 "TARGET_ARM && arm_arch6"
1721 "mlas%?\\t%0, %2, %1, %3"
1722 [(set_attr "conds" "set")
1723 (set_attr "type" "mlas")]
1726 (define_insn "*mulsi3addsi_compare0_v6"
1727 [(set (reg:CC_NOOV CC_REGNUM)
1730 (match_operand:SI 2 "s_register_operand" "r")
1731 (match_operand:SI 1 "s_register_operand" "r"))
1732 (match_operand:SI 3 "s_register_operand" "r"))
1734 (set (match_operand:SI 0 "s_register_operand" "=r")
1735 (plus:SI (mult:SI (match_dup 2) (match_dup 1))
1737 "TARGET_ARM && arm_arch6 && optimize_size"
1738 "mlas%?\\t%0, %2, %1, %3"
1739 [(set_attr "conds" "set")
1740 (set_attr "type" "mlas")]
1743 (define_insn "*mulsi3addsi_compare0_scratch"
1744 [(set (reg:CC_NOOV CC_REGNUM)
1747 (match_operand:SI 2 "s_register_operand" "r,r,r,r")
1748 (match_operand:SI 1 "s_register_operand" "%0,r,0,r"))
1749 (match_operand:SI 3 "s_register_operand" "?r,r,0,0"))
1751 (clobber (match_scratch:SI 0 "=&r,&r,&r,&r"))]
1752 "TARGET_ARM && !arm_arch6"
1753 "mlas%?\\t%0, %2, %1, %3"
1754 [(set_attr "conds" "set")
1755 (set_attr "type" "mlas")]
1758 (define_insn "*mulsi3addsi_compare0_scratch_v6"
1759 [(set (reg:CC_NOOV CC_REGNUM)
1762 (match_operand:SI 2 "s_register_operand" "r")
1763 (match_operand:SI 1 "s_register_operand" "r"))
1764 (match_operand:SI 3 "s_register_operand" "r"))
1766 (clobber (match_scratch:SI 0 "=r"))]
1767 "TARGET_ARM && arm_arch6 && optimize_size"
1768 "mlas%?\\t%0, %2, %1, %3"
1769 [(set_attr "conds" "set")
1770 (set_attr "type" "mlas")]
1773 (define_insn "*mulsi3subsi"
1774 [(set (match_operand:SI 0 "s_register_operand" "=r")
1776 (match_operand:SI 3 "s_register_operand" "r")
1777 (mult:SI (match_operand:SI 2 "s_register_operand" "r")
1778 (match_operand:SI 1 "s_register_operand" "r"))))]
1779 "TARGET_32BIT && arm_arch_thumb2"
1780 "mls%?\\t%0, %2, %1, %3"
1781 [(set_attr "type" "mla")
1782 (set_attr "predicable" "yes")]
1785 (define_expand "maddsidi4"
1786 [(set (match_operand:DI 0 "s_register_operand" "")
1789 (sign_extend:DI (match_operand:SI 1 "s_register_operand" ""))
1790 (sign_extend:DI (match_operand:SI 2 "s_register_operand" "")))
1791 (match_operand:DI 3 "s_register_operand" "")))]
1795 (define_insn "*mulsidi3adddi"
1796 [(set (match_operand:DI 0 "s_register_operand" "=&r")
1799 (sign_extend:DI (match_operand:SI 2 "s_register_operand" "%r"))
1800 (sign_extend:DI (match_operand:SI 3 "s_register_operand" "r")))
1801 (match_operand:DI 1 "s_register_operand" "0")))]
1802 "TARGET_32BIT && !arm_arch6"
1803 "smlal%?\\t%Q0, %R0, %3, %2"
1804 [(set_attr "type" "smlal")
1805 (set_attr "predicable" "yes")]
1808 (define_insn "*mulsidi3adddi_v6"
1809 [(set (match_operand:DI 0 "s_register_operand" "=r")
1812 (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r"))
1813 (sign_extend:DI (match_operand:SI 3 "s_register_operand" "r")))
1814 (match_operand:DI 1 "s_register_operand" "0")))]
1815 "TARGET_32BIT && arm_arch6"
1816 "smlal%?\\t%Q0, %R0, %3, %2"
1817 [(set_attr "type" "smlal")
1818 (set_attr "predicable" "yes")]
1821 ;; 32x32->64 widening multiply.
1822 ;; As with mulsi3, the only difference between the v3-5 and v6+
1823 ;; versions of these patterns is the requirement that the output not
1824 ;; overlap the inputs, but that still means we have to have a named
1825 ;; expander and two different starred insns.
1827 (define_expand "mulsidi3"
1828 [(set (match_operand:DI 0 "s_register_operand" "")
1830 (sign_extend:DI (match_operand:SI 1 "s_register_operand" ""))
1831 (sign_extend:DI (match_operand:SI 2 "s_register_operand" ""))))]
1836 (define_insn "*mulsidi3_nov6"
1837 [(set (match_operand:DI 0 "s_register_operand" "=&r")
1839 (sign_extend:DI (match_operand:SI 1 "s_register_operand" "%r"))
1840 (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r"))))]
1841 "TARGET_32BIT && !arm_arch6"
1842 "smull%?\\t%Q0, %R0, %1, %2"
1843 [(set_attr "type" "smull")
1844 (set_attr "predicable" "yes")]
1847 (define_insn "*mulsidi3_v6"
1848 [(set (match_operand:DI 0 "s_register_operand" "=r")
1850 (sign_extend:DI (match_operand:SI 1 "s_register_operand" "r"))
1851 (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r"))))]
1852 "TARGET_32BIT && arm_arch6"
1853 "smull%?\\t%Q0, %R0, %1, %2"
1854 [(set_attr "type" "smull")
1855 (set_attr "predicable" "yes")]
1858 (define_expand "umulsidi3"
1859 [(set (match_operand:DI 0 "s_register_operand" "")
1861 (zero_extend:DI (match_operand:SI 1 "s_register_operand" ""))
1862 (zero_extend:DI (match_operand:SI 2 "s_register_operand" ""))))]
1867 (define_insn "*umulsidi3_nov6"
1868 [(set (match_operand:DI 0 "s_register_operand" "=&r")
1870 (zero_extend:DI (match_operand:SI 1 "s_register_operand" "%r"))
1871 (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r"))))]
1872 "TARGET_32BIT && !arm_arch6"
1873 "umull%?\\t%Q0, %R0, %1, %2"
1874 [(set_attr "type" "umull")
1875 (set_attr "predicable" "yes")]
1878 (define_insn "*umulsidi3_v6"
1879 [(set (match_operand:DI 0 "s_register_operand" "=r")
1881 (zero_extend:DI (match_operand:SI 1 "s_register_operand" "r"))
1882 (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r"))))]
1883 "TARGET_32BIT && arm_arch6"
1884 "umull%?\\t%Q0, %R0, %1, %2"
1885 [(set_attr "type" "umull")
1886 (set_attr "predicable" "yes")]
1889 (define_expand "umaddsidi4"
1890 [(set (match_operand:DI 0 "s_register_operand" "")
1893 (zero_extend:DI (match_operand:SI 1 "s_register_operand" ""))
1894 (zero_extend:DI (match_operand:SI 2 "s_register_operand" "")))
1895 (match_operand:DI 3 "s_register_operand" "")))]
1899 (define_insn "*umulsidi3adddi"
1900 [(set (match_operand:DI 0 "s_register_operand" "=&r")
1903 (zero_extend:DI (match_operand:SI 2 "s_register_operand" "%r"))
1904 (zero_extend:DI (match_operand:SI 3 "s_register_operand" "r")))
1905 (match_operand:DI 1 "s_register_operand" "0")))]
1906 "TARGET_32BIT && !arm_arch6"
1907 "umlal%?\\t%Q0, %R0, %3, %2"
1908 [(set_attr "type" "umlal")
1909 (set_attr "predicable" "yes")]
1912 (define_insn "*umulsidi3adddi_v6"
1913 [(set (match_operand:DI 0 "s_register_operand" "=r")
1916 (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r"))
1917 (zero_extend:DI (match_operand:SI 3 "s_register_operand" "r")))
1918 (match_operand:DI 1 "s_register_operand" "0")))]
1919 "TARGET_32BIT && arm_arch6"
1920 "umlal%?\\t%Q0, %R0, %3, %2"
1921 [(set_attr "type" "umlal")
1922 (set_attr "predicable" "yes")]
1925 (define_expand "smulsi3_highpart"
1927 [(set (match_operand:SI 0 "s_register_operand" "")
1931 (sign_extend:DI (match_operand:SI 1 "s_register_operand" ""))
1932 (sign_extend:DI (match_operand:SI 2 "s_register_operand" "")))
1934 (clobber (match_scratch:SI 3 ""))])]
1939 (define_insn "*smulsi3_highpart_nov6"
1940 [(set (match_operand:SI 0 "s_register_operand" "=&r,&r")
1944 (sign_extend:DI (match_operand:SI 1 "s_register_operand" "%0,r"))
1945 (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")))
1947 (clobber (match_scratch:SI 3 "=&r,&r"))]
1948 "TARGET_32BIT && !arm_arch6"
1949 "smull%?\\t%3, %0, %2, %1"
1950 [(set_attr "type" "smull")
1951 (set_attr "predicable" "yes")]
1954 (define_insn "*smulsi3_highpart_v6"
1955 [(set (match_operand:SI 0 "s_register_operand" "=r")
1959 (sign_extend:DI (match_operand:SI 1 "s_register_operand" "r"))
1960 (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r")))
1962 (clobber (match_scratch:SI 3 "=r"))]
1963 "TARGET_32BIT && arm_arch6"
1964 "smull%?\\t%3, %0, %2, %1"
1965 [(set_attr "type" "smull")
1966 (set_attr "predicable" "yes")]
1969 (define_expand "umulsi3_highpart"
1971 [(set (match_operand:SI 0 "s_register_operand" "")
1975 (zero_extend:DI (match_operand:SI 1 "s_register_operand" ""))
1976 (zero_extend:DI (match_operand:SI 2 "s_register_operand" "")))
1978 (clobber (match_scratch:SI 3 ""))])]
1983 (define_insn "*umulsi3_highpart_nov6"
1984 [(set (match_operand:SI 0 "s_register_operand" "=&r,&r")
1988 (zero_extend:DI (match_operand:SI 1 "s_register_operand" "%0,r"))
1989 (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")))
1991 (clobber (match_scratch:SI 3 "=&r,&r"))]
1992 "TARGET_32BIT && !arm_arch6"
1993 "umull%?\\t%3, %0, %2, %1"
1994 [(set_attr "type" "umull")
1995 (set_attr "predicable" "yes")]
1998 (define_insn "*umulsi3_highpart_v6"
1999 [(set (match_operand:SI 0 "s_register_operand" "=r")
2003 (zero_extend:DI (match_operand:SI 1 "s_register_operand" "r"))
2004 (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r")))
2006 (clobber (match_scratch:SI 3 "=r"))]
2007 "TARGET_32BIT && arm_arch6"
2008 "umull%?\\t%3, %0, %2, %1"
2009 [(set_attr "type" "umull")
2010 (set_attr "predicable" "yes")]
2013 (define_insn "mulhisi3"
2014 [(set (match_operand:SI 0 "s_register_operand" "=r")
2015 (mult:SI (sign_extend:SI
2016 (match_operand:HI 1 "s_register_operand" "%r"))
2018 (match_operand:HI 2 "s_register_operand" "r"))))]
2019 "TARGET_DSP_MULTIPLY"
2020 "smulbb%?\\t%0, %1, %2"
2021 [(set_attr "type" "smulxy")
2022 (set_attr "predicable" "yes")]
2025 (define_insn "*mulhisi3tb"
2026 [(set (match_operand:SI 0 "s_register_operand" "=r")
2027 (mult:SI (ashiftrt:SI
2028 (match_operand:SI 1 "s_register_operand" "r")
2031 (match_operand:HI 2 "s_register_operand" "r"))))]
2032 "TARGET_DSP_MULTIPLY"
2033 "smultb%?\\t%0, %1, %2"
2034 [(set_attr "type" "smulxy")
2035 (set_attr "predicable" "yes")]
2038 (define_insn "*mulhisi3bt"
2039 [(set (match_operand:SI 0 "s_register_operand" "=r")
2040 (mult:SI (sign_extend:SI
2041 (match_operand:HI 1 "s_register_operand" "r"))
2043 (match_operand:SI 2 "s_register_operand" "r")
2045 "TARGET_DSP_MULTIPLY"
2046 "smulbt%?\\t%0, %1, %2"
2047 [(set_attr "type" "smulxy")
2048 (set_attr "predicable" "yes")]
2051 (define_insn "*mulhisi3tt"
2052 [(set (match_operand:SI 0 "s_register_operand" "=r")
2053 (mult:SI (ashiftrt:SI
2054 (match_operand:SI 1 "s_register_operand" "r")
2057 (match_operand:SI 2 "s_register_operand" "r")
2059 "TARGET_DSP_MULTIPLY"
2060 "smultt%?\\t%0, %1, %2"
2061 [(set_attr "type" "smulxy")
2062 (set_attr "predicable" "yes")]
2065 (define_insn "maddhisi4"
2066 [(set (match_operand:SI 0 "s_register_operand" "=r")
2067 (plus:SI (mult:SI (sign_extend:SI
2068 (match_operand:HI 1 "s_register_operand" "r"))
2070 (match_operand:HI 2 "s_register_operand" "r")))
2071 (match_operand:SI 3 "s_register_operand" "r")))]
2072 "TARGET_DSP_MULTIPLY"
2073 "smlabb%?\\t%0, %1, %2, %3"
2074 [(set_attr "type" "smlaxy")
2075 (set_attr "predicable" "yes")]
2078 ;; Note: there is no maddhisi4ibt because this one is canonical form
2079 (define_insn "*maddhisi4tb"
2080 [(set (match_operand:SI 0 "s_register_operand" "=r")
2081 (plus:SI (mult:SI (ashiftrt:SI
2082 (match_operand:SI 1 "s_register_operand" "r")
2085 (match_operand:HI 2 "s_register_operand" "r")))
2086 (match_operand:SI 3 "s_register_operand" "r")))]
2087 "TARGET_DSP_MULTIPLY"
2088 "smlatb%?\\t%0, %1, %2, %3"
2089 [(set_attr "type" "smlaxy")
2090 (set_attr "predicable" "yes")]
2093 (define_insn "*maddhisi4tt"
2094 [(set (match_operand:SI 0 "s_register_operand" "=r")
2095 (plus:SI (mult:SI (ashiftrt:SI
2096 (match_operand:SI 1 "s_register_operand" "r")
2099 (match_operand:SI 2 "s_register_operand" "r")
2101 (match_operand:SI 3 "s_register_operand" "r")))]
2102 "TARGET_DSP_MULTIPLY"
2103 "smlatt%?\\t%0, %1, %2, %3"
2104 [(set_attr "type" "smlaxy")
2105 (set_attr "predicable" "yes")]
2108 (define_insn "maddhidi4"
2109 [(set (match_operand:DI 0 "s_register_operand" "=r")
2111 (mult:DI (sign_extend:DI
2112 (match_operand:HI 1 "s_register_operand" "r"))
2114 (match_operand:HI 2 "s_register_operand" "r")))
2115 (match_operand:DI 3 "s_register_operand" "0")))]
2116 "TARGET_DSP_MULTIPLY"
2117 "smlalbb%?\\t%Q0, %R0, %1, %2"
2118 [(set_attr "type" "smlalxy")
2119 (set_attr "predicable" "yes")])
2121 ;; Note: there is no maddhidi4ibt because this one is canonical form
2122 (define_insn "*maddhidi4tb"
2123 [(set (match_operand:DI 0 "s_register_operand" "=r")
2125 (mult:DI (sign_extend:DI
2127 (match_operand:SI 1 "s_register_operand" "r")
2130 (match_operand:HI 2 "s_register_operand" "r")))
2131 (match_operand:DI 3 "s_register_operand" "0")))]
2132 "TARGET_DSP_MULTIPLY"
2133 "smlaltb%?\\t%Q0, %R0, %1, %2"
2134 [(set_attr "type" "smlalxy")
2135 (set_attr "predicable" "yes")])
2137 (define_insn "*maddhidi4tt"
2138 [(set (match_operand:DI 0 "s_register_operand" "=r")
2140 (mult:DI (sign_extend:DI
2142 (match_operand:SI 1 "s_register_operand" "r")
2146 (match_operand:SI 2 "s_register_operand" "r")
2148 (match_operand:DI 3 "s_register_operand" "0")))]
2149 "TARGET_DSP_MULTIPLY"
2150 "smlaltt%?\\t%Q0, %R0, %1, %2"
2151 [(set_attr "type" "smlalxy")
2152 (set_attr "predicable" "yes")])
2154 (define_expand "mulsf3"
2155 [(set (match_operand:SF 0 "s_register_operand" "")
2156 (mult:SF (match_operand:SF 1 "s_register_operand" "")
2157 (match_operand:SF 2 "s_register_operand" "")))]
2158 "TARGET_32BIT && TARGET_HARD_FLOAT"
2162 (define_expand "muldf3"
2163 [(set (match_operand:DF 0 "s_register_operand" "")
2164 (mult:DF (match_operand:DF 1 "s_register_operand" "")
2165 (match_operand:DF 2 "s_register_operand" "")))]
2166 "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
2172 (define_expand "divsf3"
2173 [(set (match_operand:SF 0 "s_register_operand" "")
2174 (div:SF (match_operand:SF 1 "s_register_operand" "")
2175 (match_operand:SF 2 "s_register_operand" "")))]
2176 "TARGET_32BIT && TARGET_HARD_FLOAT"
2179 (define_expand "divdf3"
2180 [(set (match_operand:DF 0 "s_register_operand" "")
2181 (div:DF (match_operand:DF 1 "s_register_operand" "")
2182 (match_operand:DF 2 "s_register_operand" "")))]
2183 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
2186 ;; Boolean and,ior,xor insns
2188 ;; Split up double word logical operations
2190 ;; Split up simple DImode logical operations. Simply perform the logical
2191 ;; operation on the upper and lower halves of the registers.
2193 [(set (match_operand:DI 0 "s_register_operand" "")
2194 (match_operator:DI 6 "logical_binary_operator"
2195 [(match_operand:DI 1 "s_register_operand" "")
2196 (match_operand:DI 2 "s_register_operand" "")]))]
2197 "TARGET_32BIT && reload_completed
2198 && ! (TARGET_NEON && IS_VFP_REGNUM (REGNO (operands[0])))
2199 && ! IS_IWMMXT_REGNUM (REGNO (operands[0]))"
2200 [(set (match_dup 0) (match_op_dup:SI 6 [(match_dup 1) (match_dup 2)]))
2201 (set (match_dup 3) (match_op_dup:SI 6 [(match_dup 4) (match_dup 5)]))]
2204 operands[3] = gen_highpart (SImode, operands[0]);
2205 operands[0] = gen_lowpart (SImode, operands[0]);
2206 operands[4] = gen_highpart (SImode, operands[1]);
2207 operands[1] = gen_lowpart (SImode, operands[1]);
2208 operands[5] = gen_highpart (SImode, operands[2]);
2209 operands[2] = gen_lowpart (SImode, operands[2]);
2214 [(set (match_operand:DI 0 "s_register_operand" "")
2215 (match_operator:DI 6 "logical_binary_operator"
2216 [(sign_extend:DI (match_operand:SI 2 "s_register_operand" ""))
2217 (match_operand:DI 1 "s_register_operand" "")]))]
2218 "TARGET_32BIT && reload_completed"
2219 [(set (match_dup 0) (match_op_dup:SI 6 [(match_dup 1) (match_dup 2)]))
2220 (set (match_dup 3) (match_op_dup:SI 6
2221 [(ashiftrt:SI (match_dup 2) (const_int 31))
2225 operands[3] = gen_highpart (SImode, operands[0]);
2226 operands[0] = gen_lowpart (SImode, operands[0]);
2227 operands[4] = gen_highpart (SImode, operands[1]);
2228 operands[1] = gen_lowpart (SImode, operands[1]);
2229 operands[5] = gen_highpart (SImode, operands[2]);
2230 operands[2] = gen_lowpart (SImode, operands[2]);
2234 ;; The zero extend of operand 2 means we can just copy the high part of
2235 ;; operand1 into operand0.
2237 [(set (match_operand:DI 0 "s_register_operand" "")
2239 (zero_extend:DI (match_operand:SI 2 "s_register_operand" ""))
2240 (match_operand:DI 1 "s_register_operand" "")))]
2241 "TARGET_32BIT && operands[0] != operands[1] && reload_completed"
2242 [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 2)))
2243 (set (match_dup 3) (match_dup 4))]
2246 operands[4] = gen_highpart (SImode, operands[1]);
2247 operands[3] = gen_highpart (SImode, operands[0]);
2248 operands[0] = gen_lowpart (SImode, operands[0]);
2249 operands[1] = gen_lowpart (SImode, operands[1]);
2253 ;; The zero extend of operand 2 means we can just copy the high part of
2254 ;; operand1 into operand0.
2256 [(set (match_operand:DI 0 "s_register_operand" "")
2258 (zero_extend:DI (match_operand:SI 2 "s_register_operand" ""))
2259 (match_operand:DI 1 "s_register_operand" "")))]
2260 "TARGET_32BIT && operands[0] != operands[1] && reload_completed"
2261 [(set (match_dup 0) (xor:SI (match_dup 1) (match_dup 2)))
2262 (set (match_dup 3) (match_dup 4))]
2265 operands[4] = gen_highpart (SImode, operands[1]);
2266 operands[3] = gen_highpart (SImode, operands[0]);
2267 operands[0] = gen_lowpart (SImode, operands[0]);
2268 operands[1] = gen_lowpart (SImode, operands[1]);
2272 (define_expand "anddi3"
2273 [(set (match_operand:DI 0 "s_register_operand" "")
2274 (and:DI (match_operand:DI 1 "s_register_operand" "")
2275 (match_operand:DI 2 "neon_inv_logic_op2" "")))]
2278 if (!TARGET_NEON && !TARGET_IWMMXT)
2280 rtx low = simplify_gen_binary (AND, SImode,
2281 gen_lowpart (SImode, operands[1]),
2282 gen_lowpart (SImode, operands[2]));
2283 rtx high = simplify_gen_binary (AND, SImode,
2284 gen_highpart (SImode, operands[1]),
2285 gen_highpart_mode (SImode, DImode,
2288 emit_insn (gen_rtx_SET (gen_lowpart (SImode, operands[0]), low));
2289 emit_insn (gen_rtx_SET (gen_highpart (SImode, operands[0]), high));
2293 /* Otherwise expand pattern as above. */
2297 (define_insn_and_split "*anddi3_insn"
2298 [(set (match_operand:DI 0 "s_register_operand" "=w,w ,&r,&r,&r,&r,?w,?w")
2299 (and:DI (match_operand:DI 1 "s_register_operand" "%w,0 ,0 ,r ,0 ,r ,w ,0")
2300 (match_operand:DI 2 "arm_anddi_operand_neon" "w ,DL,r ,r ,De,De,w ,DL")))]
2301 "TARGET_32BIT && !TARGET_IWMMXT"
2303 switch (which_alternative)
2305 case 0: /* fall through */
2306 case 6: return "vand\t%P0, %P1, %P2";
2307 case 1: /* fall through */
2308 case 7: return neon_output_logic_immediate ("vand", &operands[2],
2309 DImode, 1, VALID_NEON_QREG_MODE (DImode));
2313 case 5: /* fall through */
2315 default: gcc_unreachable ();
2318 "TARGET_32BIT && !TARGET_IWMMXT && reload_completed
2319 && !(IS_VFP_REGNUM (REGNO (operands[0])))"
2320 [(set (match_dup 3) (match_dup 4))
2321 (set (match_dup 5) (match_dup 6))]
2324 operands[3] = gen_lowpart (SImode, operands[0]);
2325 operands[5] = gen_highpart (SImode, operands[0]);
2327 operands[4] = simplify_gen_binary (AND, SImode,
2328 gen_lowpart (SImode, operands[1]),
2329 gen_lowpart (SImode, operands[2]));
2330 operands[6] = simplify_gen_binary (AND, SImode,
2331 gen_highpart (SImode, operands[1]),
2332 gen_highpart_mode (SImode, DImode, operands[2]));
2335 [(set_attr "type" "neon_logic,neon_logic,multiple,multiple,\
2336 multiple,multiple,neon_logic,neon_logic")
2337 (set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,*,*,
2338 avoid_neon_for_64bits,avoid_neon_for_64bits")
2339 (set_attr "length" "*,*,8,8,8,8,*,*")
2343 (define_insn_and_split "*anddi_zesidi_di"
2344 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
2345 (and:DI (zero_extend:DI
2346 (match_operand:SI 2 "s_register_operand" "r,r"))
2347 (match_operand:DI 1 "s_register_operand" "0,r")))]
2350 "TARGET_32BIT && reload_completed"
2351 ; The zero extend of operand 2 clears the high word of the output
2353 [(set (match_dup 0) (and:SI (match_dup 1) (match_dup 2)))
2354 (set (match_dup 3) (const_int 0))]
2357 operands[3] = gen_highpart (SImode, operands[0]);
2358 operands[0] = gen_lowpart (SImode, operands[0]);
2359 operands[1] = gen_lowpart (SImode, operands[1]);
2361 [(set_attr "length" "8")
2362 (set_attr "type" "multiple")]
2365 (define_insn "*anddi_sesdi_di"
2366 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
2367 (and:DI (sign_extend:DI
2368 (match_operand:SI 2 "s_register_operand" "r,r"))
2369 (match_operand:DI 1 "s_register_operand" "0,r")))]
2372 [(set_attr "length" "8")
2373 (set_attr "type" "multiple")]
2376 (define_expand "andsi3"
2377 [(set (match_operand:SI 0 "s_register_operand" "")
2378 (and:SI (match_operand:SI 1 "s_register_operand" "")
2379 (match_operand:SI 2 "reg_or_int_operand" "")))]
2384 if (CONST_INT_P (operands[2]))
2386 if (INTVAL (operands[2]) == 255 && arm_arch6)
2388 operands[1] = convert_to_mode (QImode, operands[1], 1);
2389 emit_insn (gen_thumb2_zero_extendqisi2_v6 (operands[0],
2393 else if (DONT_EARLY_SPLIT_CONSTANT (INTVAL (operands[2]), AND))
2394 operands[2] = force_reg (SImode, operands[2]);
2397 arm_split_constant (AND, SImode, NULL_RTX,
2398 INTVAL (operands[2]), operands[0],
2400 optimize && can_create_pseudo_p ());
2406 else /* TARGET_THUMB1 */
2408 if (!CONST_INT_P (operands[2]))
2410 rtx tmp = force_reg (SImode, operands[2]);
2411 if (rtx_equal_p (operands[0], operands[1]))
2415 operands[2] = operands[1];
2423 if (((unsigned HOST_WIDE_INT) ~INTVAL (operands[2])) < 256)
2425 operands[2] = force_reg (SImode,
2426 GEN_INT (~INTVAL (operands[2])));
2428 emit_insn (gen_thumb1_bicsi3 (operands[0], operands[2], operands[1]));
2433 for (i = 9; i <= 31; i++)
2435 if ((HOST_WIDE_INT_1 << i) - 1 == INTVAL (operands[2]))
2437 emit_insn (gen_extzv (operands[0], operands[1], GEN_INT (i),
2441 else if ((HOST_WIDE_INT_1 << i) - 1
2442 == ~INTVAL (operands[2]))
2444 rtx shift = GEN_INT (i);
2445 rtx reg = gen_reg_rtx (SImode);
2447 emit_insn (gen_lshrsi3 (reg, operands[1], shift));
2448 emit_insn (gen_ashlsi3 (operands[0], reg, shift));
2454 operands[2] = force_reg (SImode, operands[2]);
2460 ; ??? Check split length for Thumb-2
2461 (define_insn_and_split "*arm_andsi3_insn"
2462 [(set (match_operand:SI 0 "s_register_operand" "=r,l,r,r,r")
2463 (and:SI (match_operand:SI 1 "s_register_operand" "%r,0,r,r,r")
2464 (match_operand:SI 2 "reg_or_int_operand" "I,l,K,r,?n")))]
2469 bic%?\\t%0, %1, #%B2
2473 && CONST_INT_P (operands[2])
2474 && !(const_ok_for_arm (INTVAL (operands[2]))
2475 || const_ok_for_arm (~INTVAL (operands[2])))"
2476 [(clobber (const_int 0))]
2478 arm_split_constant (AND, SImode, curr_insn,
2479 INTVAL (operands[2]), operands[0], operands[1], 0);
2482 [(set_attr "length" "4,4,4,4,16")
2483 (set_attr "predicable" "yes")
2484 (set_attr "predicable_short_it" "no,yes,no,no,no")
2485 (set_attr "type" "logic_imm,logic_imm,logic_reg,logic_reg,logic_imm")]
2488 (define_insn "*andsi3_compare0"
2489 [(set (reg:CC_NOOV CC_REGNUM)
2491 (and:SI (match_operand:SI 1 "s_register_operand" "r,r,r")
2492 (match_operand:SI 2 "arm_not_operand" "I,K,r"))
2494 (set (match_operand:SI 0 "s_register_operand" "=r,r,r")
2495 (and:SI (match_dup 1) (match_dup 2)))]
2499 bics%?\\t%0, %1, #%B2
2500 ands%?\\t%0, %1, %2"
2501 [(set_attr "conds" "set")
2502 (set_attr "type" "logics_imm,logics_imm,logics_reg")]
2505 (define_insn "*andsi3_compare0_scratch"
2506 [(set (reg:CC_NOOV CC_REGNUM)
2508 (and:SI (match_operand:SI 0 "s_register_operand" "r,r,r")
2509 (match_operand:SI 1 "arm_not_operand" "I,K,r"))
2511 (clobber (match_scratch:SI 2 "=X,r,X"))]
2515 bics%?\\t%2, %0, #%B1
2517 [(set_attr "conds" "set")
2518 (set_attr "type" "logics_imm,logics_imm,logics_reg")]
2521 (define_insn "*zeroextractsi_compare0_scratch"
2522 [(set (reg:CC_NOOV CC_REGNUM)
2523 (compare:CC_NOOV (zero_extract:SI
2524 (match_operand:SI 0 "s_register_operand" "r")
2525 (match_operand 1 "const_int_operand" "n")
2526 (match_operand 2 "const_int_operand" "n"))
2529 && (INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) < 32
2530 && INTVAL (operands[1]) > 0
2531 && INTVAL (operands[1]) + (INTVAL (operands[2]) & 1) <= 8
2532 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32)"
2534 operands[1] = GEN_INT (((1 << INTVAL (operands[1])) - 1)
2535 << INTVAL (operands[2]));
2536 output_asm_insn (\"tst%?\\t%0, %1\", operands);
2539 [(set_attr "conds" "set")
2540 (set_attr "predicable" "yes")
2541 (set_attr "type" "logics_imm")]
2544 (define_insn_and_split "*ne_zeroextractsi"
2545 [(set (match_operand:SI 0 "s_register_operand" "=r")
2546 (ne:SI (zero_extract:SI
2547 (match_operand:SI 1 "s_register_operand" "r")
2548 (match_operand:SI 2 "const_int_operand" "n")
2549 (match_operand:SI 3 "const_int_operand" "n"))
2551 (clobber (reg:CC CC_REGNUM))]
2553 && (INTVAL (operands[3]) >= 0 && INTVAL (operands[3]) < 32
2554 && INTVAL (operands[2]) > 0
2555 && INTVAL (operands[2]) + (INTVAL (operands[3]) & 1) <= 8
2556 && INTVAL (operands[2]) + INTVAL (operands[3]) <= 32)"
2559 && (INTVAL (operands[3]) >= 0 && INTVAL (operands[3]) < 32
2560 && INTVAL (operands[2]) > 0
2561 && INTVAL (operands[2]) + (INTVAL (operands[3]) & 1) <= 8
2562 && INTVAL (operands[2]) + INTVAL (operands[3]) <= 32)"
2563 [(parallel [(set (reg:CC_NOOV CC_REGNUM)
2564 (compare:CC_NOOV (and:SI (match_dup 1) (match_dup 2))
2566 (set (match_dup 0) (and:SI (match_dup 1) (match_dup 2)))])
2568 (if_then_else:SI (eq (reg:CC_NOOV CC_REGNUM) (const_int 0))
2569 (match_dup 0) (const_int 1)))]
2571 operands[2] = GEN_INT (((1 << INTVAL (operands[2])) - 1)
2572 << INTVAL (operands[3]));
2574 [(set_attr "conds" "clob")
2575 (set (attr "length")
2576 (if_then_else (eq_attr "is_thumb" "yes")
2579 (set_attr "type" "multiple")]
2582 (define_insn_and_split "*ne_zeroextractsi_shifted"
2583 [(set (match_operand:SI 0 "s_register_operand" "=r")
2584 (ne:SI (zero_extract:SI
2585 (match_operand:SI 1 "s_register_operand" "r")
2586 (match_operand:SI 2 "const_int_operand" "n")
2589 (clobber (reg:CC CC_REGNUM))]
2593 [(parallel [(set (reg:CC_NOOV CC_REGNUM)
2594 (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2))
2596 (set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))])
2598 (if_then_else:SI (eq (reg:CC_NOOV CC_REGNUM) (const_int 0))
2599 (match_dup 0) (const_int 1)))]
2601 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2603 [(set_attr "conds" "clob")
2604 (set_attr "length" "8")
2605 (set_attr "type" "multiple")]
2608 (define_insn_and_split "*ite_ne_zeroextractsi"
2609 [(set (match_operand:SI 0 "s_register_operand" "=r")
2610 (if_then_else:SI (ne (zero_extract:SI
2611 (match_operand:SI 1 "s_register_operand" "r")
2612 (match_operand:SI 2 "const_int_operand" "n")
2613 (match_operand:SI 3 "const_int_operand" "n"))
2615 (match_operand:SI 4 "arm_not_operand" "rIK")
2617 (clobber (reg:CC CC_REGNUM))]
2619 && (INTVAL (operands[3]) >= 0 && INTVAL (operands[3]) < 32
2620 && INTVAL (operands[2]) > 0
2621 && INTVAL (operands[2]) + (INTVAL (operands[3]) & 1) <= 8
2622 && INTVAL (operands[2]) + INTVAL (operands[3]) <= 32)
2623 && !reg_overlap_mentioned_p (operands[0], operands[4])"
2626 && (INTVAL (operands[3]) >= 0 && INTVAL (operands[3]) < 32
2627 && INTVAL (operands[2]) > 0
2628 && INTVAL (operands[2]) + (INTVAL (operands[3]) & 1) <= 8
2629 && INTVAL (operands[2]) + INTVAL (operands[3]) <= 32)
2630 && !reg_overlap_mentioned_p (operands[0], operands[4])"
2631 [(parallel [(set (reg:CC_NOOV CC_REGNUM)
2632 (compare:CC_NOOV (and:SI (match_dup 1) (match_dup 2))
2634 (set (match_dup 0) (and:SI (match_dup 1) (match_dup 2)))])
2636 (if_then_else:SI (eq (reg:CC_NOOV CC_REGNUM) (const_int 0))
2637 (match_dup 0) (match_dup 4)))]
2639 operands[2] = GEN_INT (((1 << INTVAL (operands[2])) - 1)
2640 << INTVAL (operands[3]));
2642 [(set_attr "conds" "clob")
2643 (set_attr "length" "8")
2644 (set_attr "type" "multiple")]
2647 (define_insn_and_split "*ite_ne_zeroextractsi_shifted"
2648 [(set (match_operand:SI 0 "s_register_operand" "=r")
2649 (if_then_else:SI (ne (zero_extract:SI
2650 (match_operand:SI 1 "s_register_operand" "r")
2651 (match_operand:SI 2 "const_int_operand" "n")
2654 (match_operand:SI 3 "arm_not_operand" "rIK")
2656 (clobber (reg:CC CC_REGNUM))]
2657 "TARGET_ARM && !reg_overlap_mentioned_p (operands[0], operands[3])"
2659 "TARGET_ARM && !reg_overlap_mentioned_p (operands[0], operands[3])"
2660 [(parallel [(set (reg:CC_NOOV CC_REGNUM)
2661 (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2))
2663 (set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))])
2665 (if_then_else:SI (eq (reg:CC_NOOV CC_REGNUM) (const_int 0))
2666 (match_dup 0) (match_dup 3)))]
2668 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2670 [(set_attr "conds" "clob")
2671 (set_attr "length" "8")
2672 (set_attr "type" "multiple")]
2675 ;; ??? Use Thumb-2 has bitfield insert/extract instructions.
2677 [(set (match_operand:SI 0 "s_register_operand" "")
2678 (match_operator:SI 1 "shiftable_operator"
2679 [(zero_extract:SI (match_operand:SI 2 "s_register_operand" "")
2680 (match_operand:SI 3 "const_int_operand" "")
2681 (match_operand:SI 4 "const_int_operand" ""))
2682 (match_operand:SI 5 "s_register_operand" "")]))
2683 (clobber (match_operand:SI 6 "s_register_operand" ""))]
2685 [(set (match_dup 6) (ashift:SI (match_dup 2) (match_dup 3)))
2688 [(lshiftrt:SI (match_dup 6) (match_dup 4))
2691 HOST_WIDE_INT temp = INTVAL (operands[3]);
2693 operands[3] = GEN_INT (32 - temp - INTVAL (operands[4]));
2694 operands[4] = GEN_INT (32 - temp);
2699 [(set (match_operand:SI 0 "s_register_operand" "")
2700 (match_operator:SI 1 "shiftable_operator"
2701 [(sign_extract:SI (match_operand:SI 2 "s_register_operand" "")
2702 (match_operand:SI 3 "const_int_operand" "")
2703 (match_operand:SI 4 "const_int_operand" ""))
2704 (match_operand:SI 5 "s_register_operand" "")]))
2705 (clobber (match_operand:SI 6 "s_register_operand" ""))]
2707 [(set (match_dup 6) (ashift:SI (match_dup 2) (match_dup 3)))
2710 [(ashiftrt:SI (match_dup 6) (match_dup 4))
2713 HOST_WIDE_INT temp = INTVAL (operands[3]);
2715 operands[3] = GEN_INT (32 - temp - INTVAL (operands[4]));
2716 operands[4] = GEN_INT (32 - temp);
2720 ;;; ??? This pattern is bogus. If operand3 has bits outside the range
2721 ;;; represented by the bitfield, then this will produce incorrect results.
2722 ;;; Somewhere, the value needs to be truncated. On targets like the m68k,
2723 ;;; which have a real bit-field insert instruction, the truncation happens
2724 ;;; in the bit-field insert instruction itself. Since arm does not have a
2725 ;;; bit-field insert instruction, we would have to emit code here to truncate
2726 ;;; the value before we insert. This loses some of the advantage of having
2727 ;;; this insv pattern, so this pattern needs to be reevalutated.
2729 (define_expand "insv"
2730 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
2731 (match_operand 1 "general_operand" "")
2732 (match_operand 2 "general_operand" ""))
2733 (match_operand 3 "reg_or_int_operand" ""))]
2734 "TARGET_ARM || arm_arch_thumb2"
2737 int start_bit = INTVAL (operands[2]);
2738 int width = INTVAL (operands[1]);
2739 HOST_WIDE_INT mask = (HOST_WIDE_INT_1 << width) - 1;
2740 rtx target, subtarget;
2742 if (arm_arch_thumb2)
2744 if (unaligned_access && MEM_P (operands[0])
2745 && s_register_operand (operands[3], GET_MODE (operands[3]))
2746 && (width == 16 || width == 32) && (start_bit % BITS_PER_UNIT) == 0)
2750 if (BYTES_BIG_ENDIAN)
2751 start_bit = GET_MODE_BITSIZE (GET_MODE (operands[3])) - width
2756 base_addr = adjust_address (operands[0], SImode,
2757 start_bit / BITS_PER_UNIT);
2758 emit_insn (gen_unaligned_storesi (base_addr, operands[3]));
2762 rtx tmp = gen_reg_rtx (HImode);
2764 base_addr = adjust_address (operands[0], HImode,
2765 start_bit / BITS_PER_UNIT);
2766 emit_move_insn (tmp, gen_lowpart (HImode, operands[3]));
2767 emit_insn (gen_unaligned_storehi (base_addr, tmp));
2771 else if (s_register_operand (operands[0], GET_MODE (operands[0])))
2773 bool use_bfi = TRUE;
2775 if (CONST_INT_P (operands[3]))
2777 HOST_WIDE_INT val = INTVAL (operands[3]) & mask;
2781 emit_insn (gen_insv_zero (operands[0], operands[1],
2786 /* See if the set can be done with a single orr instruction. */
2787 if (val == mask && const_ok_for_arm (val << start_bit))
2793 if (!REG_P (operands[3]))
2794 operands[3] = force_reg (SImode, operands[3]);
2796 emit_insn (gen_insv_t2 (operands[0], operands[1], operands[2],
2805 if (!s_register_operand (operands[0], GET_MODE (operands[0])))
2808 target = copy_rtx (operands[0]);
2809 /* Avoid using a subreg as a subtarget, and avoid writing a paradoxical
2810 subreg as the final target. */
2811 if (GET_CODE (target) == SUBREG)
2813 subtarget = gen_reg_rtx (SImode);
2814 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (target)))
2815 < GET_MODE_SIZE (SImode))
2816 target = SUBREG_REG (target);
2821 if (CONST_INT_P (operands[3]))
2823 /* Since we are inserting a known constant, we may be able to
2824 reduce the number of bits that we have to clear so that
2825 the mask becomes simple. */
2826 /* ??? This code does not check to see if the new mask is actually
2827 simpler. It may not be. */
2828 rtx op1 = gen_reg_rtx (SImode);
2829 /* ??? Truncate operand3 to fit in the bitfield. See comment before
2830 start of this pattern. */
2831 HOST_WIDE_INT op3_value = mask & INTVAL (operands[3]);
2832 HOST_WIDE_INT mask2 = ((mask & ~op3_value) << start_bit);
2834 emit_insn (gen_andsi3 (op1, operands[0],
2835 gen_int_mode (~mask2, SImode)));
2836 emit_insn (gen_iorsi3 (subtarget, op1,
2837 gen_int_mode (op3_value << start_bit, SImode)));
2839 else if (start_bit == 0
2840 && !(const_ok_for_arm (mask)
2841 || const_ok_for_arm (~mask)))
2843 /* A Trick, since we are setting the bottom bits in the word,
2844 we can shift operand[3] up, operand[0] down, OR them together
2845 and rotate the result back again. This takes 3 insns, and
2846 the third might be mergeable into another op. */
2847 /* The shift up copes with the possibility that operand[3] is
2848 wider than the bitfield. */
2849 rtx op0 = gen_reg_rtx (SImode);
2850 rtx op1 = gen_reg_rtx (SImode);
2852 emit_insn (gen_ashlsi3 (op0, operands[3], GEN_INT (32 - width)));
2853 emit_insn (gen_lshrsi3 (op1, operands[0], operands[1]));
2854 emit_insn (gen_iorsi3 (op1, op1, op0));
2855 emit_insn (gen_rotlsi3 (subtarget, op1, operands[1]));
2857 else if ((width + start_bit == 32)
2858 && !(const_ok_for_arm (mask)
2859 || const_ok_for_arm (~mask)))
2861 /* Similar trick, but slightly less efficient. */
2863 rtx op0 = gen_reg_rtx (SImode);
2864 rtx op1 = gen_reg_rtx (SImode);
2866 emit_insn (gen_ashlsi3 (op0, operands[3], GEN_INT (32 - width)));
2867 emit_insn (gen_ashlsi3 (op1, operands[0], operands[1]));
2868 emit_insn (gen_lshrsi3 (op1, op1, operands[1]));
2869 emit_insn (gen_iorsi3 (subtarget, op1, op0));
2873 rtx op0 = gen_int_mode (mask, SImode);
2874 rtx op1 = gen_reg_rtx (SImode);
2875 rtx op2 = gen_reg_rtx (SImode);
2877 if (!(const_ok_for_arm (mask) || const_ok_for_arm (~mask)))
2879 rtx tmp = gen_reg_rtx (SImode);
2881 emit_insn (gen_movsi (tmp, op0));
2885 /* Mask out any bits in operand[3] that are not needed. */
2886 emit_insn (gen_andsi3 (op1, operands[3], op0));
2888 if (CONST_INT_P (op0)
2889 && (const_ok_for_arm (mask << start_bit)
2890 || const_ok_for_arm (~(mask << start_bit))))
2892 op0 = gen_int_mode (~(mask << start_bit), SImode);
2893 emit_insn (gen_andsi3 (op2, operands[0], op0));
2897 if (CONST_INT_P (op0))
2899 rtx tmp = gen_reg_rtx (SImode);
2901 emit_insn (gen_movsi (tmp, op0));
2906 emit_insn (gen_ashlsi3 (op0, op0, operands[2]));
2908 emit_insn (gen_andsi_notsi_si (op2, operands[0], op0));
2912 emit_insn (gen_ashlsi3 (op1, op1, operands[2]));
2914 emit_insn (gen_iorsi3 (subtarget, op1, op2));
2917 if (subtarget != target)
2919 /* If TARGET is still a SUBREG, then it must be wider than a word,
2920 so we must be careful only to set the subword we were asked to. */
2921 if (GET_CODE (target) == SUBREG)
2922 emit_move_insn (target, subtarget);
2924 emit_move_insn (target, gen_lowpart (GET_MODE (target), subtarget));
2931 (define_insn "insv_zero"
2932 [(set (zero_extract:SI (match_operand:SI 0 "s_register_operand" "+r")
2933 (match_operand:SI 1 "const_int_M_operand" "M")
2934 (match_operand:SI 2 "const_int_M_operand" "M"))
2938 [(set_attr "length" "4")
2939 (set_attr "predicable" "yes")
2940 (set_attr "type" "bfm")]
2943 (define_insn "insv_t2"
2944 [(set (zero_extract:SI (match_operand:SI 0 "s_register_operand" "+r")
2945 (match_operand:SI 1 "const_int_M_operand" "M")
2946 (match_operand:SI 2 "const_int_M_operand" "M"))
2947 (match_operand:SI 3 "s_register_operand" "r"))]
2949 "bfi%?\t%0, %3, %2, %1"
2950 [(set_attr "length" "4")
2951 (set_attr "predicable" "yes")
2952 (set_attr "type" "bfm")]
2955 ; constants for op 2 will never be given to these patterns.
2956 (define_insn_and_split "*anddi_notdi_di"
2957 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
2958 (and:DI (not:DI (match_operand:DI 1 "s_register_operand" "0,r"))
2959 (match_operand:DI 2 "s_register_operand" "r,0")))]
2962 "TARGET_32BIT && reload_completed
2963 && ! (TARGET_NEON && IS_VFP_REGNUM (REGNO (operands[0])))
2964 && ! IS_IWMMXT_REGNUM (REGNO (operands[0]))"
2965 [(set (match_dup 0) (and:SI (not:SI (match_dup 1)) (match_dup 2)))
2966 (set (match_dup 3) (and:SI (not:SI (match_dup 4)) (match_dup 5)))]
2969 operands[3] = gen_highpart (SImode, operands[0]);
2970 operands[0] = gen_lowpart (SImode, operands[0]);
2971 operands[4] = gen_highpart (SImode, operands[1]);
2972 operands[1] = gen_lowpart (SImode, operands[1]);
2973 operands[5] = gen_highpart (SImode, operands[2]);
2974 operands[2] = gen_lowpart (SImode, operands[2]);
2976 [(set_attr "length" "8")
2977 (set_attr "predicable" "yes")
2978 (set_attr "type" "multiple")]
2981 (define_insn_and_split "*anddi_notzesidi_di"
2982 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
2983 (and:DI (not:DI (zero_extend:DI
2984 (match_operand:SI 2 "s_register_operand" "r,r")))
2985 (match_operand:DI 1 "s_register_operand" "0,?r")))]
2988 bic%?\\t%Q0, %Q1, %2
2990 ; (not (zero_extend ...)) allows us to just copy the high word from
2991 ; operand1 to operand0.
2994 && operands[0] != operands[1]"
2995 [(set (match_dup 0) (and:SI (not:SI (match_dup 2)) (match_dup 1)))
2996 (set (match_dup 3) (match_dup 4))]
2999 operands[3] = gen_highpart (SImode, operands[0]);
3000 operands[0] = gen_lowpart (SImode, operands[0]);
3001 operands[4] = gen_highpart (SImode, operands[1]);
3002 operands[1] = gen_lowpart (SImode, operands[1]);
3004 [(set_attr "length" "4,8")
3005 (set_attr "predicable" "yes")
3006 (set_attr "type" "multiple")]
3009 (define_insn_and_split "*anddi_notdi_zesidi"
3010 [(set (match_operand:DI 0 "s_register_operand" "=r")
3011 (and:DI (not:DI (match_operand:DI 2 "s_register_operand" "r"))
3013 (match_operand:SI 1 "s_register_operand" "r"))))]
3016 "TARGET_32BIT && reload_completed"
3017 [(set (match_dup 0) (and:SI (not:SI (match_dup 2)) (match_dup 1)))
3018 (set (match_dup 3) (const_int 0))]
3021 operands[3] = gen_highpart (SImode, operands[0]);
3022 operands[0] = gen_lowpart (SImode, operands[0]);
3023 operands[2] = gen_lowpart (SImode, operands[2]);
3025 [(set_attr "length" "8")
3026 (set_attr "predicable" "yes")
3027 (set_attr "type" "multiple")]
3030 (define_insn_and_split "*anddi_notsesidi_di"
3031 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
3032 (and:DI (not:DI (sign_extend:DI
3033 (match_operand:SI 2 "s_register_operand" "r,r")))
3034 (match_operand:DI 1 "s_register_operand" "0,r")))]
3037 "TARGET_32BIT && reload_completed"
3038 [(set (match_dup 0) (and:SI (not:SI (match_dup 2)) (match_dup 1)))
3039 (set (match_dup 3) (and:SI (not:SI
3040 (ashiftrt:SI (match_dup 2) (const_int 31)))
3044 operands[3] = gen_highpart (SImode, operands[0]);
3045 operands[0] = gen_lowpart (SImode, operands[0]);
3046 operands[4] = gen_highpart (SImode, operands[1]);
3047 operands[1] = gen_lowpart (SImode, operands[1]);
3049 [(set_attr "length" "8")
3050 (set_attr "predicable" "yes")
3051 (set_attr "type" "multiple")]
3054 (define_insn "andsi_notsi_si"
3055 [(set (match_operand:SI 0 "s_register_operand" "=r")
3056 (and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
3057 (match_operand:SI 1 "s_register_operand" "r")))]
3059 "bic%?\\t%0, %1, %2"
3060 [(set_attr "predicable" "yes")
3061 (set_attr "type" "logic_reg")]
3064 (define_insn "andsi_not_shiftsi_si"
3065 [(set (match_operand:SI 0 "s_register_operand" "=r")
3066 (and:SI (not:SI (match_operator:SI 4 "shift_operator"
3067 [(match_operand:SI 2 "s_register_operand" "r")
3068 (match_operand:SI 3 "arm_rhs_operand" "rM")]))
3069 (match_operand:SI 1 "s_register_operand" "r")))]
3071 "bic%?\\t%0, %1, %2%S4"
3072 [(set_attr "predicable" "yes")
3073 (set_attr "shift" "2")
3074 (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "")
3075 (const_string "logic_shift_imm")
3076 (const_string "logic_shift_reg")))]
3079 ;; Shifted bics pattern used to set up CC status register and not reusing
3080 ;; bics output. Pattern restricts Thumb2 shift operand as bics for Thumb2
3081 ;; does not support shift by register.
3082 (define_insn "andsi_not_shiftsi_si_scc_no_reuse"
3083 [(set (reg:CC_NOOV CC_REGNUM)
3085 (and:SI (not:SI (match_operator:SI 0 "shift_operator"
3086 [(match_operand:SI 1 "s_register_operand" "r")
3087 (match_operand:SI 2 "arm_rhs_operand" "rM")]))
3088 (match_operand:SI 3 "s_register_operand" "r"))
3090 (clobber (match_scratch:SI 4 "=r"))]
3091 "TARGET_ARM || (TARGET_THUMB2 && CONST_INT_P (operands[2]))"
3092 "bics%?\\t%4, %3, %1%S0"
3093 [(set_attr "predicable" "yes")
3094 (set_attr "conds" "set")
3095 (set_attr "shift" "1")
3096 (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
3097 (const_string "logic_shift_imm")
3098 (const_string "logic_shift_reg")))]
3101 ;; Same as andsi_not_shiftsi_si_scc_no_reuse, but the bics result is also
3102 ;; getting reused later.
3103 (define_insn "andsi_not_shiftsi_si_scc"
3104 [(parallel [(set (reg:CC_NOOV CC_REGNUM)
3106 (and:SI (not:SI (match_operator:SI 0 "shift_operator"
3107 [(match_operand:SI 1 "s_register_operand" "r")
3108 (match_operand:SI 2 "arm_rhs_operand" "rM")]))
3109 (match_operand:SI 3 "s_register_operand" "r"))
3111 (set (match_operand:SI 4 "s_register_operand" "=r")
3112 (and:SI (not:SI (match_op_dup 0
3116 "TARGET_ARM || (TARGET_THUMB2 && CONST_INT_P (operands[2]))"
3117 "bics%?\\t%4, %3, %1%S0"
3118 [(set_attr "predicable" "yes")
3119 (set_attr "conds" "set")
3120 (set_attr "shift" "1")
3121 (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
3122 (const_string "logic_shift_imm")
3123 (const_string "logic_shift_reg")))]
3126 (define_insn "*andsi_notsi_si_compare0"
3127 [(set (reg:CC_NOOV CC_REGNUM)
3129 (and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
3130 (match_operand:SI 1 "s_register_operand" "r"))
3132 (set (match_operand:SI 0 "s_register_operand" "=r")
3133 (and:SI (not:SI (match_dup 2)) (match_dup 1)))]
3136 [(set_attr "conds" "set")
3137 (set_attr "type" "logics_shift_reg")]
3140 (define_insn "*andsi_notsi_si_compare0_scratch"
3141 [(set (reg:CC_NOOV CC_REGNUM)
3143 (and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
3144 (match_operand:SI 1 "s_register_operand" "r"))
3146 (clobber (match_scratch:SI 0 "=r"))]
3149 [(set_attr "conds" "set")
3150 (set_attr "type" "logics_shift_reg")]
3153 (define_expand "iordi3"
3154 [(set (match_operand:DI 0 "s_register_operand" "")
3155 (ior:DI (match_operand:DI 1 "s_register_operand" "")
3156 (match_operand:DI 2 "neon_logic_op2" "")))]
3159 if (!TARGET_NEON && !TARGET_IWMMXT)
3161 rtx low = simplify_gen_binary (IOR, SImode,
3162 gen_lowpart (SImode, operands[1]),
3163 gen_lowpart (SImode, operands[2]));
3164 rtx high = simplify_gen_binary (IOR, SImode,
3165 gen_highpart (SImode, operands[1]),
3166 gen_highpart_mode (SImode, DImode,
3169 emit_insn (gen_rtx_SET (gen_lowpart (SImode, operands[0]), low));
3170 emit_insn (gen_rtx_SET (gen_highpart (SImode, operands[0]), high));
3174 /* Otherwise expand pattern as above. */
3178 (define_insn_and_split "*iordi3_insn"
3179 [(set (match_operand:DI 0 "s_register_operand" "=w,w ,&r,&r,&r,&r,?w,?w")
3180 (ior:DI (match_operand:DI 1 "s_register_operand" "%w,0 ,0 ,r ,0 ,r ,w ,0")
3181 (match_operand:DI 2 "arm_iordi_operand_neon" "w ,Dl,r ,r ,Df,Df,w ,Dl")))]
3182 "TARGET_32BIT && !TARGET_IWMMXT"
3184 switch (which_alternative)
3186 case 0: /* fall through */
3187 case 6: return "vorr\t%P0, %P1, %P2";
3188 case 1: /* fall through */
3189 case 7: return neon_output_logic_immediate ("vorr", &operands[2],
3190 DImode, 0, VALID_NEON_QREG_MODE (DImode));
3196 default: gcc_unreachable ();
3199 "TARGET_32BIT && !TARGET_IWMMXT && reload_completed
3200 && !(IS_VFP_REGNUM (REGNO (operands[0])))"
3201 [(set (match_dup 3) (match_dup 4))
3202 (set (match_dup 5) (match_dup 6))]
3205 operands[3] = gen_lowpart (SImode, operands[0]);
3206 operands[5] = gen_highpart (SImode, operands[0]);
3208 operands[4] = simplify_gen_binary (IOR, SImode,
3209 gen_lowpart (SImode, operands[1]),
3210 gen_lowpart (SImode, operands[2]));
3211 operands[6] = simplify_gen_binary (IOR, SImode,
3212 gen_highpart (SImode, operands[1]),
3213 gen_highpart_mode (SImode, DImode, operands[2]));
3216 [(set_attr "type" "neon_logic,neon_logic,multiple,multiple,multiple,\
3217 multiple,neon_logic,neon_logic")
3218 (set_attr "length" "*,*,8,8,8,8,*,*")
3219 (set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,*,*,avoid_neon_for_64bits,avoid_neon_for_64bits")]
3222 (define_insn "*iordi_zesidi_di"
3223 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
3224 (ior:DI (zero_extend:DI
3225 (match_operand:SI 2 "s_register_operand" "r,r"))
3226 (match_operand:DI 1 "s_register_operand" "0,?r")))]
3229 orr%?\\t%Q0, %Q1, %2
3231 [(set_attr "length" "4,8")
3232 (set_attr "predicable" "yes")
3233 (set_attr "type" "logic_reg,multiple")]
3236 (define_insn "*iordi_sesidi_di"
3237 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
3238 (ior:DI (sign_extend:DI
3239 (match_operand:SI 2 "s_register_operand" "r,r"))
3240 (match_operand:DI 1 "s_register_operand" "0,r")))]
3243 [(set_attr "length" "8")
3244 (set_attr "predicable" "yes")
3245 (set_attr "type" "multiple")]
3248 (define_expand "iorsi3"
3249 [(set (match_operand:SI 0 "s_register_operand" "")
3250 (ior:SI (match_operand:SI 1 "s_register_operand" "")
3251 (match_operand:SI 2 "reg_or_int_operand" "")))]
3254 if (CONST_INT_P (operands[2]))
3258 if (DONT_EARLY_SPLIT_CONSTANT (INTVAL (operands[2]), IOR))
3259 operands[2] = force_reg (SImode, operands[2]);
3262 arm_split_constant (IOR, SImode, NULL_RTX,
3263 INTVAL (operands[2]), operands[0],
3265 optimize && can_create_pseudo_p ());
3269 else /* TARGET_THUMB1 */
3271 rtx tmp = force_reg (SImode, operands[2]);
3272 if (rtx_equal_p (operands[0], operands[1]))
3276 operands[2] = operands[1];
3284 (define_insn_and_split "*iorsi3_insn"
3285 [(set (match_operand:SI 0 "s_register_operand" "=r,l,r,r,r")
3286 (ior:SI (match_operand:SI 1 "s_register_operand" "%r,0,r,r,r")
3287 (match_operand:SI 2 "reg_or_int_operand" "I,l,K,r,?n")))]
3292 orn%?\\t%0, %1, #%B2
3296 && CONST_INT_P (operands[2])
3297 && !(const_ok_for_arm (INTVAL (operands[2]))
3298 || (TARGET_THUMB2 && const_ok_for_arm (~INTVAL (operands[2]))))"
3299 [(clobber (const_int 0))]
3301 arm_split_constant (IOR, SImode, curr_insn,
3302 INTVAL (operands[2]), operands[0], operands[1], 0);
3305 [(set_attr "length" "4,4,4,4,16")
3306 (set_attr "arch" "32,t2,t2,32,32")
3307 (set_attr "predicable" "yes")
3308 (set_attr "predicable_short_it" "no,yes,no,no,no")
3309 (set_attr "type" "logic_imm,logic_reg,logic_imm,logic_reg,logic_reg")]
3313 [(match_scratch:SI 3 "r")
3314 (set (match_operand:SI 0 "arm_general_register_operand" "")
3315 (ior:SI (match_operand:SI 1 "arm_general_register_operand" "")
3316 (match_operand:SI 2 "const_int_operand" "")))]
3318 && !const_ok_for_arm (INTVAL (operands[2]))
3319 && const_ok_for_arm (~INTVAL (operands[2]))"
3320 [(set (match_dup 3) (match_dup 2))
3321 (set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3)))]
3325 (define_insn "*iorsi3_compare0"
3326 [(set (reg:CC_NOOV CC_REGNUM)
3327 (compare:CC_NOOV (ior:SI (match_operand:SI 1 "s_register_operand" "%r,r")
3328 (match_operand:SI 2 "arm_rhs_operand" "I,r"))
3330 (set (match_operand:SI 0 "s_register_operand" "=r,r")
3331 (ior:SI (match_dup 1) (match_dup 2)))]
3333 "orrs%?\\t%0, %1, %2"
3334 [(set_attr "conds" "set")
3335 (set_attr "type" "logics_imm,logics_reg")]
3338 (define_insn "*iorsi3_compare0_scratch"
3339 [(set (reg:CC_NOOV CC_REGNUM)
3340 (compare:CC_NOOV (ior:SI (match_operand:SI 1 "s_register_operand" "%r,r")
3341 (match_operand:SI 2 "arm_rhs_operand" "I,r"))
3343 (clobber (match_scratch:SI 0 "=r,r"))]
3345 "orrs%?\\t%0, %1, %2"
3346 [(set_attr "conds" "set")
3347 (set_attr "type" "logics_imm,logics_reg")]
3350 (define_expand "xordi3"
3351 [(set (match_operand:DI 0 "s_register_operand" "")
3352 (xor:DI (match_operand:DI 1 "s_register_operand" "")
3353 (match_operand:DI 2 "arm_xordi_operand" "")))]
3356 /* The iWMMXt pattern for xordi3 accepts only register operands but we want
3357 to reuse this expander for all TARGET_32BIT targets so just force the
3358 constants into a register. Unlike for the anddi3 and iordi3 there are
3359 no NEON instructions that take an immediate. */
3360 if (TARGET_IWMMXT && !REG_P (operands[2]))
3361 operands[2] = force_reg (DImode, operands[2]);
3362 if (!TARGET_NEON && !TARGET_IWMMXT)
3364 rtx low = simplify_gen_binary (XOR, SImode,
3365 gen_lowpart (SImode, operands[1]),
3366 gen_lowpart (SImode, operands[2]));
3367 rtx high = simplify_gen_binary (XOR, SImode,
3368 gen_highpart (SImode, operands[1]),
3369 gen_highpart_mode (SImode, DImode,
3372 emit_insn (gen_rtx_SET (gen_lowpart (SImode, operands[0]), low));
3373 emit_insn (gen_rtx_SET (gen_highpart (SImode, operands[0]), high));
3377 /* Otherwise expand pattern as above. */
3381 (define_insn_and_split "*xordi3_insn"
3382 [(set (match_operand:DI 0 "s_register_operand" "=w,&r,&r,&r,&r,?w")
3383 (xor:DI (match_operand:DI 1 "s_register_operand" "%w ,0,r ,0 ,r ,w")
3384 (match_operand:DI 2 "arm_xordi_operand" "w ,r ,r ,Dg,Dg,w")))]
3385 "TARGET_32BIT && !TARGET_IWMMXT"
3387 switch (which_alternative)
3392 case 4: /* fall through */
3394 case 0: /* fall through */
3395 case 5: return "veor\t%P0, %P1, %P2";
3396 default: gcc_unreachable ();
3399 "TARGET_32BIT && !TARGET_IWMMXT && reload_completed
3400 && !(IS_VFP_REGNUM (REGNO (operands[0])))"
3401 [(set (match_dup 3) (match_dup 4))
3402 (set (match_dup 5) (match_dup 6))]
3405 operands[3] = gen_lowpart (SImode, operands[0]);
3406 operands[5] = gen_highpart (SImode, operands[0]);
3408 operands[4] = simplify_gen_binary (XOR, SImode,
3409 gen_lowpart (SImode, operands[1]),
3410 gen_lowpart (SImode, operands[2]));
3411 operands[6] = simplify_gen_binary (XOR, SImode,
3412 gen_highpart (SImode, operands[1]),
3413 gen_highpart_mode (SImode, DImode, operands[2]));
3416 [(set_attr "length" "*,8,8,8,8,*")
3417 (set_attr "type" "neon_logic,multiple,multiple,multiple,multiple,neon_logic")
3418 (set_attr "arch" "neon_for_64bits,*,*,*,*,avoid_neon_for_64bits")]
3421 (define_insn "*xordi_zesidi_di"
3422 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
3423 (xor:DI (zero_extend:DI
3424 (match_operand:SI 2 "s_register_operand" "r,r"))
3425 (match_operand:DI 1 "s_register_operand" "0,?r")))]
3428 eor%?\\t%Q0, %Q1, %2
3430 [(set_attr "length" "4,8")
3431 (set_attr "predicable" "yes")
3432 (set_attr "type" "logic_reg")]
3435 (define_insn "*xordi_sesidi_di"
3436 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
3437 (xor:DI (sign_extend:DI
3438 (match_operand:SI 2 "s_register_operand" "r,r"))
3439 (match_operand:DI 1 "s_register_operand" "0,r")))]
3442 [(set_attr "length" "8")
3443 (set_attr "predicable" "yes")
3444 (set_attr "type" "multiple")]
3447 (define_expand "xorsi3"
3448 [(set (match_operand:SI 0 "s_register_operand" "")
3449 (xor:SI (match_operand:SI 1 "s_register_operand" "")
3450 (match_operand:SI 2 "reg_or_int_operand" "")))]
3452 "if (CONST_INT_P (operands[2]))
3456 if (DONT_EARLY_SPLIT_CONSTANT (INTVAL (operands[2]), XOR))
3457 operands[2] = force_reg (SImode, operands[2]);
3460 arm_split_constant (XOR, SImode, NULL_RTX,
3461 INTVAL (operands[2]), operands[0],
3463 optimize && can_create_pseudo_p ());
3467 else /* TARGET_THUMB1 */
3469 rtx tmp = force_reg (SImode, operands[2]);
3470 if (rtx_equal_p (operands[0], operands[1]))
3474 operands[2] = operands[1];
3481 (define_insn_and_split "*arm_xorsi3"
3482 [(set (match_operand:SI 0 "s_register_operand" "=r,l,r,r")
3483 (xor:SI (match_operand:SI 1 "s_register_operand" "%r,0,r,r")
3484 (match_operand:SI 2 "reg_or_int_operand" "I,l,r,?n")))]
3492 && CONST_INT_P (operands[2])
3493 && !const_ok_for_arm (INTVAL (operands[2]))"
3494 [(clobber (const_int 0))]
3496 arm_split_constant (XOR, SImode, curr_insn,
3497 INTVAL (operands[2]), operands[0], operands[1], 0);
3500 [(set_attr "length" "4,4,4,16")
3501 (set_attr "predicable" "yes")
3502 (set_attr "predicable_short_it" "no,yes,no,no")
3503 (set_attr "type" "logic_imm,logic_reg,logic_reg,multiple")]
3506 (define_insn "*xorsi3_compare0"
3507 [(set (reg:CC_NOOV CC_REGNUM)
3508 (compare:CC_NOOV (xor:SI (match_operand:SI 1 "s_register_operand" "r,r")
3509 (match_operand:SI 2 "arm_rhs_operand" "I,r"))
3511 (set (match_operand:SI 0 "s_register_operand" "=r,r")
3512 (xor:SI (match_dup 1) (match_dup 2)))]
3514 "eors%?\\t%0, %1, %2"
3515 [(set_attr "conds" "set")
3516 (set_attr "type" "logics_imm,logics_reg")]
3519 (define_insn "*xorsi3_compare0_scratch"
3520 [(set (reg:CC_NOOV CC_REGNUM)
3521 (compare:CC_NOOV (xor:SI (match_operand:SI 0 "s_register_operand" "r,r")
3522 (match_operand:SI 1 "arm_rhs_operand" "I,r"))
3526 [(set_attr "conds" "set")
3527 (set_attr "type" "logics_imm,logics_reg")]
3530 ; By splitting (IOR (AND (NOT A) (NOT B)) C) as D = AND (IOR A B) (NOT C),
3531 ; (NOT D) we can sometimes merge the final NOT into one of the following
3535 [(set (match_operand:SI 0 "s_register_operand" "")
3536 (ior:SI (and:SI (not:SI (match_operand:SI 1 "s_register_operand" ""))
3537 (not:SI (match_operand:SI 2 "arm_rhs_operand" "")))
3538 (match_operand:SI 3 "arm_rhs_operand" "")))
3539 (clobber (match_operand:SI 4 "s_register_operand" ""))]
3541 [(set (match_dup 4) (and:SI (ior:SI (match_dup 1) (match_dup 2))
3542 (not:SI (match_dup 3))))
3543 (set (match_dup 0) (not:SI (match_dup 4)))]
3547 (define_insn_and_split "*andsi_iorsi3_notsi"
3548 [(set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r")
3549 (and:SI (ior:SI (match_operand:SI 1 "s_register_operand" "%0,r,r")
3550 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))
3551 (not:SI (match_operand:SI 3 "arm_rhs_operand" "rI,rI,rI"))))]
3553 "#" ; "orr%?\\t%0, %1, %2\;bic%?\\t%0, %0, %3"
3554 "&& reload_completed"
3555 [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 2)))
3556 (set (match_dup 0) (and:SI (match_dup 4) (match_dup 5)))]
3558 /* If operands[3] is a constant make sure to fold the NOT into it
3559 to avoid creating a NOT of a CONST_INT. */
3560 rtx not_rtx = simplify_gen_unary (NOT, SImode, operands[3], SImode);
3561 if (CONST_INT_P (not_rtx))
3563 operands[4] = operands[0];
3564 operands[5] = not_rtx;
3568 operands[5] = operands[0];
3569 operands[4] = not_rtx;
3572 [(set_attr "length" "8")
3573 (set_attr "ce_count" "2")
3574 (set_attr "predicable" "yes")
3575 (set_attr "type" "multiple")]
3578 ; ??? Are these four splitters still beneficial when the Thumb-2 bitfield
3579 ; insns are available?
3581 [(set (match_operand:SI 0 "s_register_operand" "")
3582 (match_operator:SI 1 "logical_binary_operator"
3583 [(zero_extract:SI (match_operand:SI 2 "s_register_operand" "")
3584 (match_operand:SI 3 "const_int_operand" "")
3585 (match_operand:SI 4 "const_int_operand" ""))
3586 (match_operator:SI 9 "logical_binary_operator"
3587 [(lshiftrt:SI (match_operand:SI 5 "s_register_operand" "")
3588 (match_operand:SI 6 "const_int_operand" ""))
3589 (match_operand:SI 7 "s_register_operand" "")])]))
3590 (clobber (match_operand:SI 8 "s_register_operand" ""))]
3592 && GET_CODE (operands[1]) == GET_CODE (operands[9])
3593 && INTVAL (operands[3]) == 32 - INTVAL (operands[6])"
3596 [(ashift:SI (match_dup 2) (match_dup 4))
3600 [(lshiftrt:SI (match_dup 8) (match_dup 6))
3603 operands[4] = GEN_INT (32 - (INTVAL (operands[3]) + INTVAL (operands[4])));
3607 [(set (match_operand:SI 0 "s_register_operand" "")
3608 (match_operator:SI 1 "logical_binary_operator"
3609 [(match_operator:SI 9 "logical_binary_operator"
3610 [(lshiftrt:SI (match_operand:SI 5 "s_register_operand" "")
3611 (match_operand:SI 6 "const_int_operand" ""))
3612 (match_operand:SI 7 "s_register_operand" "")])
3613 (zero_extract:SI (match_operand:SI 2 "s_register_operand" "")
3614 (match_operand:SI 3 "const_int_operand" "")
3615 (match_operand:SI 4 "const_int_operand" ""))]))
3616 (clobber (match_operand:SI 8 "s_register_operand" ""))]
3618 && GET_CODE (operands[1]) == GET_CODE (operands[9])
3619 && INTVAL (operands[3]) == 32 - INTVAL (operands[6])"
3622 [(ashift:SI (match_dup 2) (match_dup 4))
3626 [(lshiftrt:SI (match_dup 8) (match_dup 6))
3629 operands[4] = GEN_INT (32 - (INTVAL (operands[3]) + INTVAL (operands[4])));
3633 [(set (match_operand:SI 0 "s_register_operand" "")
3634 (match_operator:SI 1 "logical_binary_operator"
3635 [(sign_extract:SI (match_operand:SI 2 "s_register_operand" "")
3636 (match_operand:SI 3 "const_int_operand" "")
3637 (match_operand:SI 4 "const_int_operand" ""))
3638 (match_operator:SI 9 "logical_binary_operator"
3639 [(ashiftrt:SI (match_operand:SI 5 "s_register_operand" "")
3640 (match_operand:SI 6 "const_int_operand" ""))
3641 (match_operand:SI 7 "s_register_operand" "")])]))
3642 (clobber (match_operand:SI 8 "s_register_operand" ""))]
3644 && GET_CODE (operands[1]) == GET_CODE (operands[9])
3645 && INTVAL (operands[3]) == 32 - INTVAL (operands[6])"
3648 [(ashift:SI (match_dup 2) (match_dup 4))
3652 [(ashiftrt:SI (match_dup 8) (match_dup 6))
3655 operands[4] = GEN_INT (32 - (INTVAL (operands[3]) + INTVAL (operands[4])));
3659 [(set (match_operand:SI 0 "s_register_operand" "")
3660 (match_operator:SI 1 "logical_binary_operator"
3661 [(match_operator:SI 9 "logical_binary_operator"
3662 [(ashiftrt:SI (match_operand:SI 5 "s_register_operand" "")
3663 (match_operand:SI 6 "const_int_operand" ""))
3664 (match_operand:SI 7 "s_register_operand" "")])
3665 (sign_extract:SI (match_operand:SI 2 "s_register_operand" "")
3666 (match_operand:SI 3 "const_int_operand" "")
3667 (match_operand:SI 4 "const_int_operand" ""))]))
3668 (clobber (match_operand:SI 8 "s_register_operand" ""))]
3670 && GET_CODE (operands[1]) == GET_CODE (operands[9])
3671 && INTVAL (operands[3]) == 32 - INTVAL (operands[6])"
3674 [(ashift:SI (match_dup 2) (match_dup 4))
3678 [(ashiftrt:SI (match_dup 8) (match_dup 6))
3681 operands[4] = GEN_INT (32 - (INTVAL (operands[3]) + INTVAL (operands[4])));
3685 ;; Minimum and maximum insns
3687 (define_expand "smaxsi3"
3689 (set (match_operand:SI 0 "s_register_operand" "")
3690 (smax:SI (match_operand:SI 1 "s_register_operand" "")
3691 (match_operand:SI 2 "arm_rhs_operand" "")))
3692 (clobber (reg:CC CC_REGNUM))])]
3695 if (operands[2] == const0_rtx || operands[2] == constm1_rtx)
3697 /* No need for a clobber of the condition code register here. */
3698 emit_insn (gen_rtx_SET (operands[0],
3699 gen_rtx_SMAX (SImode, operands[1],
3705 (define_insn "*smax_0"
3706 [(set (match_operand:SI 0 "s_register_operand" "=r")
3707 (smax:SI (match_operand:SI 1 "s_register_operand" "r")
3710 "bic%?\\t%0, %1, %1, asr #31"
3711 [(set_attr "predicable" "yes")
3712 (set_attr "type" "logic_shift_reg")]
3715 (define_insn "*smax_m1"
3716 [(set (match_operand:SI 0 "s_register_operand" "=r")
3717 (smax:SI (match_operand:SI 1 "s_register_operand" "r")
3720 "orr%?\\t%0, %1, %1, asr #31"
3721 [(set_attr "predicable" "yes")
3722 (set_attr "type" "logic_shift_reg")]
3725 (define_insn_and_split "*arm_smax_insn"
3726 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
3727 (smax:SI (match_operand:SI 1 "s_register_operand" "%0,?r")
3728 (match_operand:SI 2 "arm_rhs_operand" "rI,rI")))
3729 (clobber (reg:CC CC_REGNUM))]
3732 ; cmp\\t%1, %2\;movlt\\t%0, %2
3733 ; cmp\\t%1, %2\;movge\\t%0, %1\;movlt\\t%0, %2"
3735 [(set (reg:CC CC_REGNUM)
3736 (compare:CC (match_dup 1) (match_dup 2)))
3738 (if_then_else:SI (ge:SI (reg:CC CC_REGNUM) (const_int 0))
3742 [(set_attr "conds" "clob")
3743 (set_attr "length" "8,12")
3744 (set_attr "type" "multiple")]
3747 (define_expand "sminsi3"
3749 (set (match_operand:SI 0 "s_register_operand" "")
3750 (smin:SI (match_operand:SI 1 "s_register_operand" "")
3751 (match_operand:SI 2 "arm_rhs_operand" "")))
3752 (clobber (reg:CC CC_REGNUM))])]
3755 if (operands[2] == const0_rtx)
3757 /* No need for a clobber of the condition code register here. */
3758 emit_insn (gen_rtx_SET (operands[0],
3759 gen_rtx_SMIN (SImode, operands[1],
3765 (define_insn "*smin_0"
3766 [(set (match_operand:SI 0 "s_register_operand" "=r")
3767 (smin:SI (match_operand:SI 1 "s_register_operand" "r")
3770 "and%?\\t%0, %1, %1, asr #31"
3771 [(set_attr "predicable" "yes")
3772 (set_attr "type" "logic_shift_reg")]
3775 (define_insn_and_split "*arm_smin_insn"
3776 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
3777 (smin:SI (match_operand:SI 1 "s_register_operand" "%0,?r")
3778 (match_operand:SI 2 "arm_rhs_operand" "rI,rI")))
3779 (clobber (reg:CC CC_REGNUM))]
3782 ; cmp\\t%1, %2\;movge\\t%0, %2
3783 ; cmp\\t%1, %2\;movlt\\t%0, %1\;movge\\t%0, %2"
3785 [(set (reg:CC CC_REGNUM)
3786 (compare:CC (match_dup 1) (match_dup 2)))
3788 (if_then_else:SI (lt:SI (reg:CC CC_REGNUM) (const_int 0))
3792 [(set_attr "conds" "clob")
3793 (set_attr "length" "8,12")
3794 (set_attr "type" "multiple,multiple")]
3797 (define_expand "umaxsi3"
3799 (set (match_operand:SI 0 "s_register_operand" "")
3800 (umax:SI (match_operand:SI 1 "s_register_operand" "")
3801 (match_operand:SI 2 "arm_rhs_operand" "")))
3802 (clobber (reg:CC CC_REGNUM))])]
3807 (define_insn_and_split "*arm_umaxsi3"
3808 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
3809 (umax:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
3810 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
3811 (clobber (reg:CC CC_REGNUM))]
3814 ; cmp\\t%1, %2\;movcc\\t%0, %2
3815 ; cmp\\t%1, %2\;movcs\\t%0, %1
3816 ; cmp\\t%1, %2\;movcs\\t%0, %1\;movcc\\t%0, %2"
3818 [(set (reg:CC CC_REGNUM)
3819 (compare:CC (match_dup 1) (match_dup 2)))
3821 (if_then_else:SI (geu:SI (reg:CC CC_REGNUM) (const_int 0))
3825 [(set_attr "conds" "clob")
3826 (set_attr "length" "8,8,12")
3827 (set_attr "type" "store_4")]
3830 (define_expand "uminsi3"
3832 (set (match_operand:SI 0 "s_register_operand" "")
3833 (umin:SI (match_operand:SI 1 "s_register_operand" "")
3834 (match_operand:SI 2 "arm_rhs_operand" "")))
3835 (clobber (reg:CC CC_REGNUM))])]
3840 (define_insn_and_split "*arm_uminsi3"
3841 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
3842 (umin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
3843 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
3844 (clobber (reg:CC CC_REGNUM))]
3847 ; cmp\\t%1, %2\;movcs\\t%0, %2
3848 ; cmp\\t%1, %2\;movcc\\t%0, %1
3849 ; cmp\\t%1, %2\;movcc\\t%0, %1\;movcs\\t%0, %2"
3851 [(set (reg:CC CC_REGNUM)
3852 (compare:CC (match_dup 1) (match_dup 2)))
3854 (if_then_else:SI (ltu:SI (reg:CC CC_REGNUM) (const_int 0))
3858 [(set_attr "conds" "clob")
3859 (set_attr "length" "8,8,12")
3860 (set_attr "type" "store_4")]
3863 (define_insn "*store_minmaxsi"
3864 [(set (match_operand:SI 0 "memory_operand" "=m")
3865 (match_operator:SI 3 "minmax_operator"
3866 [(match_operand:SI 1 "s_register_operand" "r")
3867 (match_operand:SI 2 "s_register_operand" "r")]))
3868 (clobber (reg:CC CC_REGNUM))]
3869 "TARGET_32BIT && optimize_function_for_size_p (cfun) && !arm_restrict_it"
3871 operands[3] = gen_rtx_fmt_ee (minmax_code (operands[3]), SImode,
3872 operands[1], operands[2]);
3873 output_asm_insn (\"cmp\\t%1, %2\", operands);
3875 output_asm_insn (\"ite\t%d3\", operands);
3876 output_asm_insn (\"str%d3\\t%1, %0\", operands);
3877 output_asm_insn (\"str%D3\\t%2, %0\", operands);
3880 [(set_attr "conds" "clob")
3881 (set (attr "length")
3882 (if_then_else (eq_attr "is_thumb" "yes")
3885 (set_attr "type" "store_4")]
3888 ; Reject the frame pointer in operand[1], since reloading this after
3889 ; it has been eliminated can cause carnage.
3890 (define_insn "*minmax_arithsi"
3891 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
3892 (match_operator:SI 4 "shiftable_operator"
3893 [(match_operator:SI 5 "minmax_operator"
3894 [(match_operand:SI 2 "s_register_operand" "r,r")
3895 (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])
3896 (match_operand:SI 1 "s_register_operand" "0,?r")]))
3897 (clobber (reg:CC CC_REGNUM))]
3898 "TARGET_32BIT && !arm_eliminable_register (operands[1]) && !arm_restrict_it"
3901 enum rtx_code code = GET_CODE (operands[4]);
3904 if (which_alternative != 0 || operands[3] != const0_rtx
3905 || (code != PLUS && code != IOR && code != XOR))
3910 operands[5] = gen_rtx_fmt_ee (minmax_code (operands[5]), SImode,
3911 operands[2], operands[3]);
3912 output_asm_insn (\"cmp\\t%2, %3\", operands);
3916 output_asm_insn (\"ite\\t%d5\", operands);
3918 output_asm_insn (\"it\\t%d5\", operands);
3920 output_asm_insn (\"%i4%d5\\t%0, %1, %2\", operands);
3922 output_asm_insn (\"%i4%D5\\t%0, %1, %3\", operands);
3925 [(set_attr "conds" "clob")
3926 (set (attr "length")
3927 (if_then_else (eq_attr "is_thumb" "yes")
3930 (set_attr "type" "multiple")]
3933 ; Reject the frame pointer in operand[1], since reloading this after
3934 ; it has been eliminated can cause carnage.
3935 (define_insn_and_split "*minmax_arithsi_non_canon"
3936 [(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts")
3938 (match_operand:SI 1 "s_register_operand" "0,?Ts")
3939 (match_operator:SI 4 "minmax_operator"
3940 [(match_operand:SI 2 "s_register_operand" "Ts,Ts")
3941 (match_operand:SI 3 "arm_rhs_operand" "TsI,TsI")])))
3942 (clobber (reg:CC CC_REGNUM))]
3943 "TARGET_32BIT && !arm_eliminable_register (operands[1])
3944 && !(arm_restrict_it && CONST_INT_P (operands[3]))"
3946 "TARGET_32BIT && !arm_eliminable_register (operands[1]) && reload_completed"
3947 [(set (reg:CC CC_REGNUM)
3948 (compare:CC (match_dup 2) (match_dup 3)))
3950 (cond_exec (match_op_dup 4 [(reg:CC CC_REGNUM) (const_int 0)])
3952 (minus:SI (match_dup 1)
3954 (cond_exec (match_op_dup 5 [(reg:CC CC_REGNUM) (const_int 0)])
3958 machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[1]),
3959 operands[2], operands[3]);
3960 enum rtx_code rc = minmax_code (operands[4]);
3961 operands[4] = gen_rtx_fmt_ee (rc, VOIDmode,
3962 operands[2], operands[3]);
3964 if (mode == CCFPmode || mode == CCFPEmode)
3965 rc = reverse_condition_maybe_unordered (rc);
3967 rc = reverse_condition (rc);
3968 operands[5] = gen_rtx_fmt_ee (rc, SImode, operands[2], operands[3]);
3969 if (CONST_INT_P (operands[3]))
3970 operands[6] = plus_constant (SImode, operands[1], -INTVAL (operands[3]));
3972 operands[6] = gen_rtx_MINUS (SImode, operands[1], operands[3]);
3974 [(set_attr "conds" "clob")
3975 (set (attr "length")
3976 (if_then_else (eq_attr "is_thumb" "yes")
3979 (set_attr "type" "multiple")]
3982 (define_code_iterator SAT [smin smax])
3983 (define_code_iterator SATrev [smin smax])
3984 (define_code_attr SATlo [(smin "1") (smax "2")])
3985 (define_code_attr SAThi [(smin "2") (smax "1")])
3987 (define_insn "*satsi_<SAT:code>"
3988 [(set (match_operand:SI 0 "s_register_operand" "=r")
3989 (SAT:SI (SATrev:SI (match_operand:SI 3 "s_register_operand" "r")
3990 (match_operand:SI 1 "const_int_operand" "i"))
3991 (match_operand:SI 2 "const_int_operand" "i")))]
3992 "TARGET_32BIT && arm_arch6 && <SAT:CODE> != <SATrev:CODE>
3993 && arm_sat_operator_match (operands[<SAT:SATlo>], operands[<SAT:SAThi>], NULL, NULL)"
3997 if (!arm_sat_operator_match (operands[<SAT:SATlo>], operands[<SAT:SAThi>],
3998 &mask, &signed_sat))
4001 operands[1] = GEN_INT (mask);
4003 return "ssat%?\t%0, %1, %3";
4005 return "usat%?\t%0, %1, %3";
4007 [(set_attr "predicable" "yes")
4008 (set_attr "type" "alus_imm")]
4011 (define_insn "*satsi_<SAT:code>_shift"
4012 [(set (match_operand:SI 0 "s_register_operand" "=r")
4013 (SAT:SI (SATrev:SI (match_operator:SI 3 "sat_shift_operator"
4014 [(match_operand:SI 4 "s_register_operand" "r")
4015 (match_operand:SI 5 "const_int_operand" "i")])
4016 (match_operand:SI 1 "const_int_operand" "i"))
4017 (match_operand:SI 2 "const_int_operand" "i")))]
4018 "TARGET_32BIT && arm_arch6 && <SAT:CODE> != <SATrev:CODE>
4019 && arm_sat_operator_match (operands[<SAT:SATlo>], operands[<SAT:SAThi>], NULL, NULL)"
4023 if (!arm_sat_operator_match (operands[<SAT:SATlo>], operands[<SAT:SAThi>],
4024 &mask, &signed_sat))
4027 operands[1] = GEN_INT (mask);
4029 return "ssat%?\t%0, %1, %4%S3";
4031 return "usat%?\t%0, %1, %4%S3";
4033 [(set_attr "predicable" "yes")
4034 (set_attr "shift" "3")
4035 (set_attr "type" "logic_shift_reg")])
4037 ;; Shift and rotation insns
4039 (define_expand "ashldi3"
4040 [(set (match_operand:DI 0 "s_register_operand" "")
4041 (ashift:DI (match_operand:DI 1 "s_register_operand" "")
4042 (match_operand:SI 2 "general_operand" "")))]
4047 /* Delay the decision whether to use NEON or core-regs until
4048 register allocation. */
4049 emit_insn (gen_ashldi3_neon (operands[0], operands[1], operands[2]));
4054 /* Only the NEON case can handle in-memory shift counts. */
4055 if (!reg_or_int_operand (operands[2], SImode))
4056 operands[2] = force_reg (SImode, operands[2]);
4059 if (!CONST_INT_P (operands[2]) && TARGET_REALLY_IWMMXT)
4060 ; /* No special preparation statements; expand pattern as above. */
4063 rtx scratch1, scratch2;
4065 /* Ideally we should use iwmmxt here if we could know that operands[1]
4066 ends up already living in an iwmmxt register. Otherwise it's
4067 cheaper to have the alternate code being generated than moving
4068 values to iwmmxt regs and back. */
4070 /* Expand operation using core-registers.
4071 'FAIL' would achieve the same thing, but this is a bit smarter. */
4072 scratch1 = gen_reg_rtx (SImode);
4073 scratch2 = gen_reg_rtx (SImode);
4074 arm_emit_coreregs_64bit_shift (ASHIFT, operands[0], operands[1],
4075 operands[2], scratch1, scratch2);
4081 (define_expand "ashlsi3"
4082 [(set (match_operand:SI 0 "s_register_operand" "")
4083 (ashift:SI (match_operand:SI 1 "s_register_operand" "")
4084 (match_operand:SI 2 "arm_rhs_operand" "")))]
4087 if (CONST_INT_P (operands[2])
4088 && (UINTVAL (operands[2])) > 31)
4090 emit_insn (gen_movsi (operands[0], const0_rtx));
4096 (define_expand "ashrdi3"
4097 [(set (match_operand:DI 0 "s_register_operand" "")
4098 (ashiftrt:DI (match_operand:DI 1 "s_register_operand" "")
4099 (match_operand:SI 2 "reg_or_int_operand" "")))]
4104 /* Delay the decision whether to use NEON or core-regs until
4105 register allocation. */
4106 emit_insn (gen_ashrdi3_neon (operands[0], operands[1], operands[2]));
4110 if (!CONST_INT_P (operands[2]) && TARGET_REALLY_IWMMXT)
4111 ; /* No special preparation statements; expand pattern as above. */
4114 rtx scratch1, scratch2;
4116 /* Ideally we should use iwmmxt here if we could know that operands[1]
4117 ends up already living in an iwmmxt register. Otherwise it's
4118 cheaper to have the alternate code being generated than moving
4119 values to iwmmxt regs and back. */
4121 /* Expand operation using core-registers.
4122 'FAIL' would achieve the same thing, but this is a bit smarter. */
4123 scratch1 = gen_reg_rtx (SImode);
4124 scratch2 = gen_reg_rtx (SImode);
4125 arm_emit_coreregs_64bit_shift (ASHIFTRT, operands[0], operands[1],
4126 operands[2], scratch1, scratch2);
4132 (define_expand "ashrsi3"
4133 [(set (match_operand:SI 0 "s_register_operand" "")
4134 (ashiftrt:SI (match_operand:SI 1 "s_register_operand" "")
4135 (match_operand:SI 2 "arm_rhs_operand" "")))]
4138 if (CONST_INT_P (operands[2])
4139 && UINTVAL (operands[2]) > 31)
4140 operands[2] = GEN_INT (31);
4144 (define_expand "lshrdi3"
4145 [(set (match_operand:DI 0 "s_register_operand" "")
4146 (lshiftrt:DI (match_operand:DI 1 "s_register_operand" "")
4147 (match_operand:SI 2 "reg_or_int_operand" "")))]
4152 /* Delay the decision whether to use NEON or core-regs until
4153 register allocation. */
4154 emit_insn (gen_lshrdi3_neon (operands[0], operands[1], operands[2]));
4158 if (!CONST_INT_P (operands[2]) && TARGET_REALLY_IWMMXT)
4159 ; /* No special preparation statements; expand pattern as above. */
4162 rtx scratch1, scratch2;
4164 /* Ideally we should use iwmmxt here if we could know that operands[1]
4165 ends up already living in an iwmmxt register. Otherwise it's
4166 cheaper to have the alternate code being generated than moving
4167 values to iwmmxt regs and back. */
4169 /* Expand operation using core-registers.
4170 'FAIL' would achieve the same thing, but this is a bit smarter. */
4171 scratch1 = gen_reg_rtx (SImode);
4172 scratch2 = gen_reg_rtx (SImode);
4173 arm_emit_coreregs_64bit_shift (LSHIFTRT, operands[0], operands[1],
4174 operands[2], scratch1, scratch2);
4180 (define_expand "lshrsi3"
4181 [(set (match_operand:SI 0 "s_register_operand" "")
4182 (lshiftrt:SI (match_operand:SI 1 "s_register_operand" "")
4183 (match_operand:SI 2 "arm_rhs_operand" "")))]
4186 if (CONST_INT_P (operands[2])
4187 && (UINTVAL (operands[2])) > 31)
4189 emit_insn (gen_movsi (operands[0], const0_rtx));
4195 (define_expand "rotlsi3"
4196 [(set (match_operand:SI 0 "s_register_operand" "")
4197 (rotatert:SI (match_operand:SI 1 "s_register_operand" "")
4198 (match_operand:SI 2 "reg_or_int_operand" "")))]
4201 if (CONST_INT_P (operands[2]))
4202 operands[2] = GEN_INT ((32 - INTVAL (operands[2])) % 32);
4205 rtx reg = gen_reg_rtx (SImode);
4206 emit_insn (gen_subsi3 (reg, GEN_INT (32), operands[2]));
4212 (define_expand "rotrsi3"
4213 [(set (match_operand:SI 0 "s_register_operand" "")
4214 (rotatert:SI (match_operand:SI 1 "s_register_operand" "")
4215 (match_operand:SI 2 "arm_rhs_operand" "")))]
4220 if (CONST_INT_P (operands[2])
4221 && UINTVAL (operands[2]) > 31)
4222 operands[2] = GEN_INT (INTVAL (operands[2]) % 32);
4224 else /* TARGET_THUMB1 */
4226 if (CONST_INT_P (operands [2]))
4227 operands [2] = force_reg (SImode, operands[2]);
4232 (define_insn "*arm_shiftsi3"
4233 [(set (match_operand:SI 0 "s_register_operand" "=l,l,r,r")
4234 (match_operator:SI 3 "shift_operator"
4235 [(match_operand:SI 1 "s_register_operand" "0,l,r,r")
4236 (match_operand:SI 2 "reg_or_int_operand" "l,M,M,r")]))]
4238 "* return arm_output_shift(operands, 0);"
4239 [(set_attr "predicable" "yes")
4240 (set_attr "arch" "t2,t2,*,*")
4241 (set_attr "predicable_short_it" "yes,yes,no,no")
4242 (set_attr "length" "4")
4243 (set_attr "shift" "1")
4244 (set_attr "type" "alu_shift_reg,alu_shift_imm,alu_shift_imm,alu_shift_reg")]
4247 (define_insn "*shiftsi3_compare0"
4248 [(set (reg:CC_NOOV CC_REGNUM)
4249 (compare:CC_NOOV (match_operator:SI 3 "shift_operator"
4250 [(match_operand:SI 1 "s_register_operand" "r,r")
4251 (match_operand:SI 2 "arm_rhs_operand" "M,r")])
4253 (set (match_operand:SI 0 "s_register_operand" "=r,r")
4254 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))]
4256 "* return arm_output_shift(operands, 1);"
4257 [(set_attr "conds" "set")
4258 (set_attr "shift" "1")
4259 (set_attr "type" "alus_shift_imm,alus_shift_reg")]
4262 (define_insn "*shiftsi3_compare0_scratch"
4263 [(set (reg:CC_NOOV CC_REGNUM)
4264 (compare:CC_NOOV (match_operator:SI 3 "shift_operator"
4265 [(match_operand:SI 1 "s_register_operand" "r,r")
4266 (match_operand:SI 2 "arm_rhs_operand" "M,r")])
4268 (clobber (match_scratch:SI 0 "=r,r"))]
4270 "* return arm_output_shift(operands, 1);"
4271 [(set_attr "conds" "set")
4272 (set_attr "shift" "1")
4273 (set_attr "type" "shift_imm,shift_reg")]
4276 (define_insn "*not_shiftsi"
4277 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
4278 (not:SI (match_operator:SI 3 "shift_operator"
4279 [(match_operand:SI 1 "s_register_operand" "r,r")
4280 (match_operand:SI 2 "shift_amount_operand" "M,rM")])))]
4283 [(set_attr "predicable" "yes")
4284 (set_attr "shift" "1")
4285 (set_attr "arch" "32,a")
4286 (set_attr "type" "mvn_shift,mvn_shift_reg")])
4288 (define_insn "*not_shiftsi_compare0"
4289 [(set (reg:CC_NOOV CC_REGNUM)
4291 (not:SI (match_operator:SI 3 "shift_operator"
4292 [(match_operand:SI 1 "s_register_operand" "r,r")
4293 (match_operand:SI 2 "shift_amount_operand" "M,rM")]))
4295 (set (match_operand:SI 0 "s_register_operand" "=r,r")
4296 (not:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])))]
4298 "mvns%?\\t%0, %1%S3"
4299 [(set_attr "conds" "set")
4300 (set_attr "shift" "1")
4301 (set_attr "arch" "32,a")
4302 (set_attr "type" "mvn_shift,mvn_shift_reg")])
4304 (define_insn "*not_shiftsi_compare0_scratch"
4305 [(set (reg:CC_NOOV CC_REGNUM)
4307 (not:SI (match_operator:SI 3 "shift_operator"
4308 [(match_operand:SI 1 "s_register_operand" "r,r")
4309 (match_operand:SI 2 "shift_amount_operand" "M,rM")]))
4311 (clobber (match_scratch:SI 0 "=r,r"))]
4313 "mvns%?\\t%0, %1%S3"
4314 [(set_attr "conds" "set")
4315 (set_attr "shift" "1")
4316 (set_attr "arch" "32,a")
4317 (set_attr "type" "mvn_shift,mvn_shift_reg")])
4319 ;; We don't really have extzv, but defining this using shifts helps
4320 ;; to reduce register pressure later on.
4322 (define_expand "extzv"
4323 [(set (match_operand 0 "s_register_operand" "")
4324 (zero_extract (match_operand 1 "nonimmediate_operand" "")
4325 (match_operand 2 "const_int_operand" "")
4326 (match_operand 3 "const_int_operand" "")))]
4327 "TARGET_THUMB1 || arm_arch_thumb2"
4330 HOST_WIDE_INT lshift = 32 - INTVAL (operands[2]) - INTVAL (operands[3]);
4331 HOST_WIDE_INT rshift = 32 - INTVAL (operands[2]);
4333 if (arm_arch_thumb2)
4335 HOST_WIDE_INT width = INTVAL (operands[2]);
4336 HOST_WIDE_INT bitpos = INTVAL (operands[3]);
4338 if (unaligned_access && MEM_P (operands[1])
4339 && (width == 16 || width == 32) && (bitpos % BITS_PER_UNIT) == 0)
4343 if (BYTES_BIG_ENDIAN)
4344 bitpos = GET_MODE_BITSIZE (GET_MODE (operands[0])) - width
4349 base_addr = adjust_address (operands[1], SImode,
4350 bitpos / BITS_PER_UNIT);
4351 emit_insn (gen_unaligned_loadsi (operands[0], base_addr));
4355 rtx dest = operands[0];
4356 rtx tmp = gen_reg_rtx (SImode);
4358 /* We may get a paradoxical subreg here. Strip it off. */
4359 if (GET_CODE (dest) == SUBREG
4360 && GET_MODE (dest) == SImode
4361 && GET_MODE (SUBREG_REG (dest)) == HImode)
4362 dest = SUBREG_REG (dest);
4364 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
4367 base_addr = adjust_address (operands[1], HImode,
4368 bitpos / BITS_PER_UNIT);
4369 emit_insn (gen_unaligned_loadhiu (tmp, base_addr));
4370 emit_move_insn (gen_lowpart (SImode, dest), tmp);
4374 else if (s_register_operand (operands[1], GET_MODE (operands[1])))
4376 emit_insn (gen_extzv_t2 (operands[0], operands[1], operands[2],
4384 if (!s_register_operand (operands[1], GET_MODE (operands[1])))
4387 operands[3] = GEN_INT (rshift);
4391 emit_insn (gen_lshrsi3 (operands[0], operands[1], operands[3]));
4395 emit_insn (gen_extzv_t1 (operands[0], operands[1], GEN_INT (lshift),
4396 operands[3], gen_reg_rtx (SImode)));
4401 ;; Helper for extzv, for the Thumb-1 register-shifts case.
4403 (define_expand "extzv_t1"
4404 [(set (match_operand:SI 4 "s_register_operand" "")
4405 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "")
4406 (match_operand:SI 2 "const_int_operand" "")))
4407 (set (match_operand:SI 0 "s_register_operand" "")
4408 (lshiftrt:SI (match_dup 4)
4409 (match_operand:SI 3 "const_int_operand" "")))]
4413 (define_expand "extv"
4414 [(set (match_operand 0 "s_register_operand" "")
4415 (sign_extract (match_operand 1 "nonimmediate_operand" "")
4416 (match_operand 2 "const_int_operand" "")
4417 (match_operand 3 "const_int_operand" "")))]
4420 HOST_WIDE_INT width = INTVAL (operands[2]);
4421 HOST_WIDE_INT bitpos = INTVAL (operands[3]);
4423 if (unaligned_access && MEM_P (operands[1]) && (width == 16 || width == 32)
4424 && (bitpos % BITS_PER_UNIT) == 0)
4428 if (BYTES_BIG_ENDIAN)
4429 bitpos = GET_MODE_BITSIZE (GET_MODE (operands[0])) - width - bitpos;
4433 base_addr = adjust_address (operands[1], SImode,
4434 bitpos / BITS_PER_UNIT);
4435 emit_insn (gen_unaligned_loadsi (operands[0], base_addr));
4439 rtx dest = operands[0];
4440 rtx tmp = gen_reg_rtx (SImode);
4442 /* We may get a paradoxical subreg here. Strip it off. */
4443 if (GET_CODE (dest) == SUBREG
4444 && GET_MODE (dest) == SImode
4445 && GET_MODE (SUBREG_REG (dest)) == HImode)
4446 dest = SUBREG_REG (dest);
4448 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
4451 base_addr = adjust_address (operands[1], HImode,
4452 bitpos / BITS_PER_UNIT);
4453 emit_insn (gen_unaligned_loadhis (tmp, base_addr));
4454 emit_move_insn (gen_lowpart (SImode, dest), tmp);
4459 else if (!s_register_operand (operands[1], GET_MODE (operands[1])))
4461 else if (GET_MODE (operands[0]) == SImode
4462 && GET_MODE (operands[1]) == SImode)
4464 emit_insn (gen_extv_regsi (operands[0], operands[1], operands[2],
4472 ; Helper to expand register forms of extv with the proper modes.
4474 (define_expand "extv_regsi"
4475 [(set (match_operand:SI 0 "s_register_operand" "")
4476 (sign_extract:SI (match_operand:SI 1 "s_register_operand" "")
4477 (match_operand 2 "const_int_operand" "")
4478 (match_operand 3 "const_int_operand" "")))]
4483 ; ARMv6+ unaligned load/store instructions (used for packed structure accesses).
4485 (define_insn "unaligned_loadsi"
4486 [(set (match_operand:SI 0 "s_register_operand" "=l,l,r")
4487 (unspec:SI [(match_operand:SI 1 "memory_operand" "m,Uw,m")]
4488 UNSPEC_UNALIGNED_LOAD))]
4491 ldr\t%0, %1\t@ unaligned
4492 ldr%?\t%0, %1\t@ unaligned
4493 ldr%?\t%0, %1\t@ unaligned"
4494 [(set_attr "arch" "t1,t2,32")
4495 (set_attr "length" "2,2,4")
4496 (set_attr "predicable" "no,yes,yes")
4497 (set_attr "predicable_short_it" "no,yes,no")
4498 (set_attr "type" "load_4")])
4500 ;; The 16-bit Thumb1 variant of ldrsh requires two registers in the
4501 ;; address (there's no immediate format). That's tricky to support
4502 ;; here and we don't really need this pattern for that case, so only
4503 ;; enable for 32-bit ISAs.
4504 (define_insn "unaligned_loadhis"
4505 [(set (match_operand:SI 0 "s_register_operand" "=r")
4507 (unspec:HI [(match_operand:HI 1 "memory_operand" "Uh")]
4508 UNSPEC_UNALIGNED_LOAD)))]
4509 "unaligned_access && TARGET_32BIT"
4510 "ldrsh%?\t%0, %1\t@ unaligned"
4511 [(set_attr "predicable" "yes")
4512 (set_attr "type" "load_byte")])
4514 (define_insn "unaligned_loadhiu"
4515 [(set (match_operand:SI 0 "s_register_operand" "=l,l,r")
4517 (unspec:HI [(match_operand:HI 1 "memory_operand" "m,Uw,m")]
4518 UNSPEC_UNALIGNED_LOAD)))]
4521 ldrh\t%0, %1\t@ unaligned
4522 ldrh%?\t%0, %1\t@ unaligned
4523 ldrh%?\t%0, %1\t@ unaligned"
4524 [(set_attr "arch" "t1,t2,32")
4525 (set_attr "length" "2,2,4")
4526 (set_attr "predicable" "no,yes,yes")
4527 (set_attr "predicable_short_it" "no,yes,no")
4528 (set_attr "type" "load_byte")])
4530 (define_insn "unaligned_storesi"
4531 [(set (match_operand:SI 0 "memory_operand" "=m,Uw,m")
4532 (unspec:SI [(match_operand:SI 1 "s_register_operand" "l,l,r")]
4533 UNSPEC_UNALIGNED_STORE))]
4536 str\t%1, %0\t@ unaligned
4537 str%?\t%1, %0\t@ unaligned
4538 str%?\t%1, %0\t@ unaligned"
4539 [(set_attr "arch" "t1,t2,32")
4540 (set_attr "length" "2,2,4")
4541 (set_attr "predicable" "no,yes,yes")
4542 (set_attr "predicable_short_it" "no,yes,no")
4543 (set_attr "type" "store_4")])
4545 (define_insn "unaligned_storehi"
4546 [(set (match_operand:HI 0 "memory_operand" "=m,Uw,m")
4547 (unspec:HI [(match_operand:HI 1 "s_register_operand" "l,l,r")]
4548 UNSPEC_UNALIGNED_STORE))]
4551 strh\t%1, %0\t@ unaligned
4552 strh%?\t%1, %0\t@ unaligned
4553 strh%?\t%1, %0\t@ unaligned"
4554 [(set_attr "arch" "t1,t2,32")
4555 (set_attr "length" "2,2,4")
4556 (set_attr "predicable" "no,yes,yes")
4557 (set_attr "predicable_short_it" "no,yes,no")
4558 (set_attr "type" "store_4")])
4561 (define_insn "*extv_reg"
4562 [(set (match_operand:SI 0 "s_register_operand" "=r")
4563 (sign_extract:SI (match_operand:SI 1 "s_register_operand" "r")
4564 (match_operand:SI 2 "const_int_operand" "n")
4565 (match_operand:SI 3 "const_int_operand" "n")))]
4567 && IN_RANGE (INTVAL (operands[3]), 0, 31)
4568 && IN_RANGE (INTVAL (operands[2]), 1, 32 - INTVAL (operands[3]))"
4569 "sbfx%?\t%0, %1, %3, %2"
4570 [(set_attr "length" "4")
4571 (set_attr "predicable" "yes")
4572 (set_attr "type" "bfm")]
4575 (define_insn "extzv_t2"
4576 [(set (match_operand:SI 0 "s_register_operand" "=r")
4577 (zero_extract:SI (match_operand:SI 1 "s_register_operand" "r")
4578 (match_operand:SI 2 "const_int_operand" "n")
4579 (match_operand:SI 3 "const_int_operand" "n")))]
4581 && IN_RANGE (INTVAL (operands[3]), 0, 31)
4582 && IN_RANGE (INTVAL (operands[2]), 1, 32 - INTVAL (operands[3]))"
4583 "ubfx%?\t%0, %1, %3, %2"
4584 [(set_attr "length" "4")
4585 (set_attr "predicable" "yes")
4586 (set_attr "type" "bfm")]
4590 ;; Division instructions
4591 (define_insn "divsi3"
4592 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
4593 (div:SI (match_operand:SI 1 "s_register_operand" "r,r")
4594 (match_operand:SI 2 "s_register_operand" "r,r")))]
4599 [(set_attr "arch" "32,v8mb")
4600 (set_attr "predicable" "yes")
4601 (set_attr "type" "sdiv")]
4604 (define_insn "udivsi3"
4605 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
4606 (udiv:SI (match_operand:SI 1 "s_register_operand" "r,r")
4607 (match_operand:SI 2 "s_register_operand" "r,r")))]
4612 [(set_attr "arch" "32,v8mb")
4613 (set_attr "predicable" "yes")
4614 (set_attr "type" "udiv")]
4618 ;; Unary arithmetic insns
4620 (define_expand "negvsi3"
4621 [(match_operand:SI 0 "register_operand")
4622 (match_operand:SI 1 "register_operand")
4623 (match_operand 2 "")]
4626 emit_insn (gen_subsi3_compare (operands[0], const0_rtx, operands[1]));
4627 arm_gen_unlikely_cbranch (NE, CC_Vmode, operands[2]);
4632 (define_expand "negvdi3"
4633 [(match_operand:DI 0 "register_operand")
4634 (match_operand:DI 1 "register_operand")
4635 (match_operand 2 "")]
4638 emit_insn (gen_negdi2_compare (operands[0], operands[1]));
4639 arm_gen_unlikely_cbranch (NE, CC_Vmode, operands[2]);
4645 (define_insn_and_split "negdi2_compare"
4646 [(set (reg:CC CC_REGNUM)
4649 (match_operand:DI 1 "register_operand" "0,r")))
4650 (set (match_operand:DI 0 "register_operand" "=r,&r")
4651 (minus:DI (const_int 0) (match_dup 1)))]
4654 "&& reload_completed"
4655 [(parallel [(set (reg:CC CC_REGNUM)
4656 (compare:CC (const_int 0) (match_dup 1)))
4657 (set (match_dup 0) (minus:SI (const_int 0)
4659 (parallel [(set (reg:CC CC_REGNUM)
4660 (compare:CC (const_int 0) (match_dup 3)))
4663 (minus:SI (const_int 0) (match_dup 3))
4664 (ltu:SI (reg:CC_C CC_REGNUM)
4667 operands[2] = gen_highpart (SImode, operands[0]);
4668 operands[0] = gen_lowpart (SImode, operands[0]);
4669 operands[3] = gen_highpart (SImode, operands[1]);
4670 operands[1] = gen_lowpart (SImode, operands[1]);
4672 [(set_attr "conds" "set")
4673 (set_attr "length" "8")
4674 (set_attr "type" "multiple")]
4677 (define_expand "negdi2"
4679 [(set (match_operand:DI 0 "s_register_operand" "")
4680 (neg:DI (match_operand:DI 1 "s_register_operand" "")))
4681 (clobber (reg:CC CC_REGNUM))])]
4686 emit_insn (gen_negdi2_neon (operands[0], operands[1]));
4692 ;; The constraints here are to prevent a *partial* overlap (where %Q0 == %R1).
4693 ;; The first alternative allows the common case of a *full* overlap.
4694 (define_insn_and_split "*negdi2_insn"
4695 [(set (match_operand:DI 0 "s_register_operand" "=r,&r")
4696 (neg:DI (match_operand:DI 1 "s_register_operand" "0,r")))
4697 (clobber (reg:CC CC_REGNUM))]
4699 "#" ; rsbs %Q0, %Q1, #0; rsc %R0, %R1, #0 (ARM)
4700 ; negs %Q0, %Q1 ; sbc %R0, %R1, %R1, lsl #1 (Thumb-2)
4701 "&& reload_completed"
4702 [(parallel [(set (reg:CC CC_REGNUM)
4703 (compare:CC (const_int 0) (match_dup 1)))
4704 (set (match_dup 0) (minus:SI (const_int 0) (match_dup 1)))])
4705 (set (match_dup 2) (minus:SI (minus:SI (const_int 0) (match_dup 3))
4706 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
4708 operands[2] = gen_highpart (SImode, operands[0]);
4709 operands[0] = gen_lowpart (SImode, operands[0]);
4710 operands[3] = gen_highpart (SImode, operands[1]);
4711 operands[1] = gen_lowpart (SImode, operands[1]);
4713 [(set_attr "conds" "clob")
4714 (set_attr "length" "8")
4715 (set_attr "type" "multiple")]
4718 (define_insn "*negsi2_carryin_compare"
4719 [(set (reg:CC CC_REGNUM)
4720 (compare:CC (const_int 0)
4721 (match_operand:SI 1 "s_register_operand" "r")))
4722 (set (match_operand:SI 0 "s_register_operand" "=r")
4723 (minus:SI (minus:SI (const_int 0)
4725 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
4728 [(set_attr "conds" "set")
4729 (set_attr "type" "alus_imm")]
4732 (define_expand "negsi2"
4733 [(set (match_operand:SI 0 "s_register_operand" "")
4734 (neg:SI (match_operand:SI 1 "s_register_operand" "")))]
4739 (define_insn "*arm_negsi2"
4740 [(set (match_operand:SI 0 "s_register_operand" "=l,r")
4741 (neg:SI (match_operand:SI 1 "s_register_operand" "l,r")))]
4743 "rsb%?\\t%0, %1, #0"
4744 [(set_attr "predicable" "yes")
4745 (set_attr "predicable_short_it" "yes,no")
4746 (set_attr "arch" "t2,*")
4747 (set_attr "length" "4")
4748 (set_attr "type" "alu_sreg")]
4751 (define_expand "negsf2"
4752 [(set (match_operand:SF 0 "s_register_operand" "")
4753 (neg:SF (match_operand:SF 1 "s_register_operand" "")))]
4754 "TARGET_32BIT && TARGET_HARD_FLOAT"
4758 (define_expand "negdf2"
4759 [(set (match_operand:DF 0 "s_register_operand" "")
4760 (neg:DF (match_operand:DF 1 "s_register_operand" "")))]
4761 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
4764 (define_insn_and_split "*zextendsidi_negsi"
4765 [(set (match_operand:DI 0 "s_register_operand" "=r")
4766 (zero_extend:DI (neg:SI (match_operand:SI 1 "s_register_operand" "r"))))]
4771 (neg:SI (match_dup 1)))
4775 operands[2] = gen_lowpart (SImode, operands[0]);
4776 operands[3] = gen_highpart (SImode, operands[0]);
4778 [(set_attr "length" "8")
4779 (set_attr "type" "multiple")]
4782 ;; Negate an extended 32-bit value.
4783 (define_insn_and_split "*negdi_extendsidi"
4784 [(set (match_operand:DI 0 "s_register_operand" "=l,r")
4785 (neg:DI (sign_extend:DI
4786 (match_operand:SI 1 "s_register_operand" "l,r"))))
4787 (clobber (reg:CC CC_REGNUM))]
4790 "&& reload_completed"
4793 rtx low = gen_lowpart (SImode, operands[0]);
4794 rtx high = gen_highpart (SImode, operands[0]);
4796 if (reg_overlap_mentioned_p (low, operands[1]))
4798 /* Input overlaps the low word of the output. Use:
4801 rsc Rhi, Rhi, #0 (thumb2: sbc Rhi, Rhi, Rhi, lsl #1). */
4802 rtx cc_reg = gen_rtx_REG (CC_Cmode, CC_REGNUM);
4804 emit_insn (gen_rtx_SET (high,
4805 gen_rtx_ASHIFTRT (SImode, operands[1],
4808 emit_insn (gen_subsi3_compare (low, const0_rtx, operands[1]));
4810 emit_insn (gen_rtx_SET (high,
4811 gen_rtx_MINUS (SImode,
4812 gen_rtx_MINUS (SImode,
4815 gen_rtx_LTU (SImode,
4820 rtx two_x = gen_rtx_ASHIFT (SImode, high, GEN_INT (1));
4821 emit_insn (gen_rtx_SET (high,
4822 gen_rtx_MINUS (SImode,
4823 gen_rtx_MINUS (SImode,
4826 gen_rtx_LTU (SImode,
4833 /* No overlap, or overlap on high word. Use:
4837 Flags not needed for this sequence. */
4838 emit_insn (gen_rtx_SET (low, gen_rtx_NEG (SImode, operands[1])));
4839 emit_insn (gen_rtx_SET (high,
4840 gen_rtx_AND (SImode,
4841 gen_rtx_NOT (SImode, operands[1]),
4843 emit_insn (gen_rtx_SET (high,
4844 gen_rtx_ASHIFTRT (SImode, high,
4849 [(set_attr "length" "12")
4850 (set_attr "arch" "t2,*")
4851 (set_attr "type" "multiple")]
4854 (define_insn_and_split "*negdi_zero_extendsidi"
4855 [(set (match_operand:DI 0 "s_register_operand" "=r,&r")
4856 (neg:DI (zero_extend:DI (match_operand:SI 1 "s_register_operand" "0,r"))))
4857 (clobber (reg:CC CC_REGNUM))]
4859 "#" ; "rsbs\\t%Q0, %1, #0\;sbc\\t%R0,%R0,%R0"
4860 ;; Don't care what register is input to sbc,
4861 ;; since we just need to propagate the carry.
4862 "&& reload_completed"
4863 [(parallel [(set (reg:CC CC_REGNUM)
4864 (compare:CC (const_int 0) (match_dup 1)))
4865 (set (match_dup 0) (minus:SI (const_int 0) (match_dup 1)))])
4866 (set (match_dup 2) (minus:SI (minus:SI (match_dup 2) (match_dup 2))
4867 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
4869 operands[2] = gen_highpart (SImode, operands[0]);
4870 operands[0] = gen_lowpart (SImode, operands[0]);
4872 [(set_attr "conds" "clob")
4873 (set_attr "length" "8")
4874 (set_attr "type" "multiple")] ;; length in thumb is 4
4877 ;; abssi2 doesn't really clobber the condition codes if a different register
4878 ;; is being set. To keep things simple, assume during rtl manipulations that
4879 ;; it does, but tell the final scan operator the truth. Similarly for
4882 (define_expand "abssi2"
4884 [(set (match_operand:SI 0 "s_register_operand" "")
4885 (abs:SI (match_operand:SI 1 "s_register_operand" "")))
4886 (clobber (match_dup 2))])]
4890 operands[2] = gen_rtx_SCRATCH (SImode);
4892 operands[2] = gen_rtx_REG (CCmode, CC_REGNUM);
4895 (define_insn_and_split "*arm_abssi2"
4896 [(set (match_operand:SI 0 "s_register_operand" "=r,&r")
4897 (abs:SI (match_operand:SI 1 "s_register_operand" "0,r")))
4898 (clobber (reg:CC CC_REGNUM))]
4901 "&& reload_completed"
4904 /* if (which_alternative == 0) */
4905 if (REGNO(operands[0]) == REGNO(operands[1]))
4907 /* Emit the pattern:
4908 cmp\\t%0, #0\;rsblt\\t%0, %0, #0
4909 [(set (reg:CC CC_REGNUM)
4910 (compare:CC (match_dup 0) (const_int 0)))
4911 (cond_exec (lt:CC (reg:CC CC_REGNUM) (const_int 0))
4912 (set (match_dup 0) (minus:SI (const_int 0) (match_dup 1))))]
4914 emit_insn (gen_rtx_SET (gen_rtx_REG (CCmode, CC_REGNUM),
4915 gen_rtx_COMPARE (CCmode, operands[0], const0_rtx)));
4916 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4917 (gen_rtx_LT (SImode,
4918 gen_rtx_REG (CCmode, CC_REGNUM),
4920 (gen_rtx_SET (operands[0],
4921 (gen_rtx_MINUS (SImode,
4928 /* Emit the pattern:
4929 alt1: eor%?\\t%0, %1, %1, asr #31\;sub%?\\t%0, %0, %1, asr #31
4931 (xor:SI (match_dup 1)
4932 (ashiftrt:SI (match_dup 1) (const_int 31))))
4934 (minus:SI (match_dup 0)
4935 (ashiftrt:SI (match_dup 1) (const_int 31))))]
4937 emit_insn (gen_rtx_SET (operands[0],
4938 gen_rtx_XOR (SImode,
4939 gen_rtx_ASHIFTRT (SImode,
4943 emit_insn (gen_rtx_SET (operands[0],
4944 gen_rtx_MINUS (SImode,
4946 gen_rtx_ASHIFTRT (SImode,
4952 [(set_attr "conds" "clob,*")
4953 (set_attr "shift" "1")
4954 (set_attr "predicable" "no, yes")
4955 (set_attr "length" "8")
4956 (set_attr "type" "multiple")]
4959 (define_insn_and_split "*arm_neg_abssi2"
4960 [(set (match_operand:SI 0 "s_register_operand" "=r,&r")
4961 (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "0,r"))))
4962 (clobber (reg:CC CC_REGNUM))]
4965 "&& reload_completed"
4968 /* if (which_alternative == 0) */
4969 if (REGNO (operands[0]) == REGNO (operands[1]))
4971 /* Emit the pattern:
4972 cmp\\t%0, #0\;rsbgt\\t%0, %0, #0
4974 emit_insn (gen_rtx_SET (gen_rtx_REG (CCmode, CC_REGNUM),
4975 gen_rtx_COMPARE (CCmode, operands[0], const0_rtx)));
4976 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4978 gen_rtx_REG (CCmode, CC_REGNUM),
4980 gen_rtx_SET (operands[0],
4981 (gen_rtx_MINUS (SImode,
4987 /* Emit the pattern:
4988 eor%?\\t%0, %1, %1, asr #31\;rsb%?\\t%0, %0, %1, asr #31
4990 emit_insn (gen_rtx_SET (operands[0],
4991 gen_rtx_XOR (SImode,
4992 gen_rtx_ASHIFTRT (SImode,
4996 emit_insn (gen_rtx_SET (operands[0],
4997 gen_rtx_MINUS (SImode,
4998 gen_rtx_ASHIFTRT (SImode,
5005 [(set_attr "conds" "clob,*")
5006 (set_attr "shift" "1")
5007 (set_attr "predicable" "no, yes")
5008 (set_attr "length" "8")
5009 (set_attr "type" "multiple")]
5012 (define_expand "abssf2"
5013 [(set (match_operand:SF 0 "s_register_operand" "")
5014 (abs:SF (match_operand:SF 1 "s_register_operand" "")))]
5015 "TARGET_32BIT && TARGET_HARD_FLOAT"
5018 (define_expand "absdf2"
5019 [(set (match_operand:DF 0 "s_register_operand" "")
5020 (abs:DF (match_operand:DF 1 "s_register_operand" "")))]
5021 "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
5024 (define_expand "sqrtsf2"
5025 [(set (match_operand:SF 0 "s_register_operand" "")
5026 (sqrt:SF (match_operand:SF 1 "s_register_operand" "")))]
5027 "TARGET_32BIT && TARGET_HARD_FLOAT"
5030 (define_expand "sqrtdf2"
5031 [(set (match_operand:DF 0 "s_register_operand" "")
5032 (sqrt:DF (match_operand:DF 1 "s_register_operand" "")))]
5033 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
5036 (define_expand "one_cmpldi2"
5037 [(set (match_operand:DI 0 "s_register_operand" "")
5038 (not:DI (match_operand:DI 1 "s_register_operand" "")))]
5041 if (!TARGET_NEON && !TARGET_IWMMXT)
5043 rtx low = simplify_gen_unary (NOT, SImode,
5044 gen_lowpart (SImode, operands[1]),
5046 rtx high = simplify_gen_unary (NOT, SImode,
5047 gen_highpart_mode (SImode, DImode,
5051 emit_insn (gen_rtx_SET (gen_lowpart (SImode, operands[0]), low));
5052 emit_insn (gen_rtx_SET (gen_highpart (SImode, operands[0]), high));
5056 /* Otherwise expand pattern as above. */
5060 (define_insn_and_split "*one_cmpldi2_insn"
5061 [(set (match_operand:DI 0 "s_register_operand" "=w,&r,&r,?w")
5062 (not:DI (match_operand:DI 1 "s_register_operand" " w, 0, r, w")))]
5069 "TARGET_32BIT && reload_completed
5070 && arm_general_register_operand (operands[0], DImode)"
5071 [(set (match_dup 0) (not:SI (match_dup 1)))
5072 (set (match_dup 2) (not:SI (match_dup 3)))]
5075 operands[2] = gen_highpart (SImode, operands[0]);
5076 operands[0] = gen_lowpart (SImode, operands[0]);
5077 operands[3] = gen_highpart (SImode, operands[1]);
5078 operands[1] = gen_lowpart (SImode, operands[1]);
5080 [(set_attr "length" "*,8,8,*")
5081 (set_attr "predicable" "no,yes,yes,no")
5082 (set_attr "type" "neon_move,multiple,multiple,neon_move")
5083 (set_attr "arch" "neon_for_64bits,*,*,avoid_neon_for_64bits")]
5086 (define_expand "one_cmplsi2"
5087 [(set (match_operand:SI 0 "s_register_operand" "")
5088 (not:SI (match_operand:SI 1 "s_register_operand" "")))]
5093 (define_insn "*arm_one_cmplsi2"
5094 [(set (match_operand:SI 0 "s_register_operand" "=l,r")
5095 (not:SI (match_operand:SI 1 "s_register_operand" "l,r")))]
5098 [(set_attr "predicable" "yes")
5099 (set_attr "predicable_short_it" "yes,no")
5100 (set_attr "arch" "t2,*")
5101 (set_attr "length" "4")
5102 (set_attr "type" "mvn_reg")]
5105 (define_insn "*notsi_compare0"
5106 [(set (reg:CC_NOOV CC_REGNUM)
5107 (compare:CC_NOOV (not:SI (match_operand:SI 1 "s_register_operand" "r"))
5109 (set (match_operand:SI 0 "s_register_operand" "=r")
5110 (not:SI (match_dup 1)))]
5113 [(set_attr "conds" "set")
5114 (set_attr "type" "mvn_reg")]
5117 (define_insn "*notsi_compare0_scratch"
5118 [(set (reg:CC_NOOV CC_REGNUM)
5119 (compare:CC_NOOV (not:SI (match_operand:SI 1 "s_register_operand" "r"))
5121 (clobber (match_scratch:SI 0 "=r"))]
5124 [(set_attr "conds" "set")
5125 (set_attr "type" "mvn_reg")]
5128 ;; Fixed <--> Floating conversion insns
5130 (define_expand "floatsihf2"
5131 [(set (match_operand:HF 0 "general_operand" "")
5132 (float:HF (match_operand:SI 1 "general_operand" "")))]
5136 rtx op1 = gen_reg_rtx (SFmode);
5137 expand_float (op1, operands[1], 0);
5138 op1 = convert_to_mode (HFmode, op1, 0);
5139 emit_move_insn (operands[0], op1);
5144 (define_expand "floatdihf2"
5145 [(set (match_operand:HF 0 "general_operand" "")
5146 (float:HF (match_operand:DI 1 "general_operand" "")))]
5150 rtx op1 = gen_reg_rtx (SFmode);
5151 expand_float (op1, operands[1], 0);
5152 op1 = convert_to_mode (HFmode, op1, 0);
5153 emit_move_insn (operands[0], op1);
5158 (define_expand "floatsisf2"
5159 [(set (match_operand:SF 0 "s_register_operand" "")
5160 (float:SF (match_operand:SI 1 "s_register_operand" "")))]
5161 "TARGET_32BIT && TARGET_HARD_FLOAT"
5165 (define_expand "floatsidf2"
5166 [(set (match_operand:DF 0 "s_register_operand" "")
5167 (float:DF (match_operand:SI 1 "s_register_operand" "")))]
5168 "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
5172 (define_expand "fix_trunchfsi2"
5173 [(set (match_operand:SI 0 "general_operand" "")
5174 (fix:SI (fix:HF (match_operand:HF 1 "general_operand" ""))))]
5178 rtx op1 = convert_to_mode (SFmode, operands[1], 0);
5179 expand_fix (operands[0], op1, 0);
5184 (define_expand "fix_trunchfdi2"
5185 [(set (match_operand:DI 0 "general_operand" "")
5186 (fix:DI (fix:HF (match_operand:HF 1 "general_operand" ""))))]
5190 rtx op1 = convert_to_mode (SFmode, operands[1], 0);
5191 expand_fix (operands[0], op1, 0);
5196 (define_expand "fix_truncsfsi2"
5197 [(set (match_operand:SI 0 "s_register_operand" "")
5198 (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" ""))))]
5199 "TARGET_32BIT && TARGET_HARD_FLOAT"
5203 (define_expand "fix_truncdfsi2"
5204 [(set (match_operand:SI 0 "s_register_operand" "")
5205 (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" ""))))]
5206 "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
5212 (define_expand "truncdfsf2"
5213 [(set (match_operand:SF 0 "s_register_operand" "")
5215 (match_operand:DF 1 "s_register_operand" "")))]
5216 "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
5220 ;; DFmode to HFmode conversions on targets without a single-step hardware
5221 ;; instruction for it would have to go through SFmode. This is dangerous
5222 ;; as it introduces double rounding.
5224 ;; Disable this pattern unless we are in an unsafe math mode, or we have
5225 ;; a single-step instruction.
5227 (define_expand "truncdfhf2"
5228 [(set (match_operand:HF 0 "s_register_operand" "")
5230 (match_operand:DF 1 "s_register_operand" "")))]
5231 "(TARGET_EITHER && flag_unsafe_math_optimizations)
5232 || (TARGET_32BIT && TARGET_FP16_TO_DOUBLE)"
5234 /* We don't have a direct instruction for this, so we must be in
5235 an unsafe math mode, and going via SFmode. */
5237 if (!(TARGET_32BIT && TARGET_FP16_TO_DOUBLE))
5240 op1 = convert_to_mode (SFmode, operands[1], 0);
5241 op1 = convert_to_mode (HFmode, op1, 0);
5242 emit_move_insn (operands[0], op1);
5245 /* Otherwise, we will pick this up as a single instruction with
5246 no intermediary rounding. */
5250 ;; Zero and sign extension instructions.
5252 (define_insn "zero_extend<mode>di2"
5253 [(set (match_operand:DI 0 "s_register_operand" "=w,r,?r,w")
5254 (zero_extend:DI (match_operand:QHSI 1 "<qhs_zextenddi_op>"
5255 "<qhs_zextenddi_cstr>")))]
5256 "TARGET_32BIT <qhs_zextenddi_cond>"
5258 [(set_attr "length" "8,4,8,8")
5259 (set_attr "arch" "neon_for_64bits,*,*,avoid_neon_for_64bits")
5260 (set_attr "ce_count" "2")
5261 (set_attr "predicable" "yes")
5262 (set_attr "type" "multiple,mov_reg,multiple,multiple")]
5265 (define_insn "extend<mode>di2"
5266 [(set (match_operand:DI 0 "s_register_operand" "=w,r,?r,?r,w")
5267 (sign_extend:DI (match_operand:QHSI 1 "<qhs_extenddi_op>"
5268 "<qhs_extenddi_cstr>")))]
5269 "TARGET_32BIT <qhs_sextenddi_cond>"
5271 [(set_attr "length" "8,4,8,8,8")
5272 (set_attr "ce_count" "2")
5273 (set_attr "shift" "1")
5274 (set_attr "predicable" "yes")
5275 (set_attr "arch" "neon_for_64bits,*,a,t,avoid_neon_for_64bits")
5276 (set_attr "type" "multiple,mov_reg,multiple,multiple,multiple")]
5279 ;; Splits for all extensions to DImode
5281 [(set (match_operand:DI 0 "s_register_operand" "")
5282 (zero_extend:DI (match_operand 1 "nonimmediate_operand" "")))]
5283 "TARGET_32BIT && reload_completed && !IS_VFP_REGNUM (REGNO (operands[0]))"
5284 [(set (match_dup 0) (match_dup 1))]
5286 rtx lo_part = gen_lowpart (SImode, operands[0]);
5287 machine_mode src_mode = GET_MODE (operands[1]);
5289 if (REG_P (operands[0])
5290 && !reg_overlap_mentioned_p (operands[0], operands[1]))
5291 emit_clobber (operands[0]);
5292 if (!REG_P (lo_part) || src_mode != SImode
5293 || !rtx_equal_p (lo_part, operands[1]))
5295 if (src_mode == SImode)
5296 emit_move_insn (lo_part, operands[1]);
5298 emit_insn (gen_rtx_SET (lo_part,
5299 gen_rtx_ZERO_EXTEND (SImode, operands[1])));
5300 operands[1] = lo_part;
5302 operands[0] = gen_highpart (SImode, operands[0]);
5303 operands[1] = const0_rtx;
5307 [(set (match_operand:DI 0 "s_register_operand" "")
5308 (sign_extend:DI (match_operand 1 "nonimmediate_operand" "")))]
5309 "TARGET_32BIT && reload_completed && !IS_VFP_REGNUM (REGNO (operands[0]))"
5310 [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (const_int 31)))]
5312 rtx lo_part = gen_lowpart (SImode, operands[0]);
5313 machine_mode src_mode = GET_MODE (operands[1]);
5315 if (REG_P (operands[0])
5316 && !reg_overlap_mentioned_p (operands[0], operands[1]))
5317 emit_clobber (operands[0]);
5319 if (!REG_P (lo_part) || src_mode != SImode
5320 || !rtx_equal_p (lo_part, operands[1]))
5322 if (src_mode == SImode)
5323 emit_move_insn (lo_part, operands[1]);
5325 emit_insn (gen_rtx_SET (lo_part,
5326 gen_rtx_SIGN_EXTEND (SImode, operands[1])));
5327 operands[1] = lo_part;
5329 operands[0] = gen_highpart (SImode, operands[0]);
5332 (define_expand "zero_extendhisi2"
5333 [(set (match_operand:SI 0 "s_register_operand" "")
5334 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
5337 if (TARGET_ARM && !arm_arch4 && MEM_P (operands[1]))
5339 emit_insn (gen_movhi_bytes (operands[0], operands[1]));
5342 if (!arm_arch6 && !MEM_P (operands[1]))
5344 rtx t = gen_lowpart (SImode, operands[1]);
5345 rtx tmp = gen_reg_rtx (SImode);
5346 emit_insn (gen_ashlsi3 (tmp, t, GEN_INT (16)));
5347 emit_insn (gen_lshrsi3 (operands[0], tmp, GEN_INT (16)));
5353 [(set (match_operand:SI 0 "s_register_operand" "")
5354 (zero_extend:SI (match_operand:HI 1 "s_register_operand" "")))]
5355 "!TARGET_THUMB2 && !arm_arch6"
5356 [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16)))
5357 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 16)))]
5359 operands[2] = gen_lowpart (SImode, operands[1]);
5362 (define_insn "*arm_zero_extendhisi2"
5363 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
5364 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
5365 "TARGET_ARM && arm_arch4 && !arm_arch6"
5369 [(set_attr "type" "alu_shift_reg,load_byte")
5370 (set_attr "predicable" "yes")]
5373 (define_insn "*arm_zero_extendhisi2_v6"
5374 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
5375 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,Uh")))]
5376 "TARGET_ARM && arm_arch6"
5380 [(set_attr "predicable" "yes")
5381 (set_attr "type" "extend,load_byte")]
5384 (define_insn "*arm_zero_extendhisi2addsi"
5385 [(set (match_operand:SI 0 "s_register_operand" "=r")
5386 (plus:SI (zero_extend:SI (match_operand:HI 1 "s_register_operand" "r"))
5387 (match_operand:SI 2 "s_register_operand" "r")))]
5389 "uxtah%?\\t%0, %2, %1"
5390 [(set_attr "type" "alu_shift_reg")
5391 (set_attr "predicable" "yes")]
5394 (define_expand "zero_extendqisi2"
5395 [(set (match_operand:SI 0 "s_register_operand" "")
5396 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
5399 if (TARGET_ARM && !arm_arch6 && !MEM_P (operands[1]))
5401 emit_insn (gen_andsi3 (operands[0],
5402 gen_lowpart (SImode, operands[1]),
5406 if (!arm_arch6 && !MEM_P (operands[1]))
5408 rtx t = gen_lowpart (SImode, operands[1]);
5409 rtx tmp = gen_reg_rtx (SImode);
5410 emit_insn (gen_ashlsi3 (tmp, t, GEN_INT (24)));
5411 emit_insn (gen_lshrsi3 (operands[0], tmp, GEN_INT (24)));
5417 [(set (match_operand:SI 0 "s_register_operand" "")
5418 (zero_extend:SI (match_operand:QI 1 "s_register_operand" "")))]
5420 [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 24)))
5421 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))]
5423 operands[2] = simplify_gen_subreg (SImode, operands[1], QImode, 0);
5426 emit_insn (gen_andsi3 (operands[0], operands[2], GEN_INT (255)));
5431 (define_insn "*arm_zero_extendqisi2"
5432 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
5433 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
5434 "TARGET_ARM && !arm_arch6"
5437 ldrb%?\\t%0, %1\\t%@ zero_extendqisi2"
5438 [(set_attr "length" "8,4")
5439 (set_attr "type" "alu_shift_reg,load_byte")
5440 (set_attr "predicable" "yes")]
5443 (define_insn "*arm_zero_extendqisi2_v6"
5444 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
5445 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,Uh")))]
5446 "TARGET_ARM && arm_arch6"
5449 ldrb%?\\t%0, %1\\t%@ zero_extendqisi2"
5450 [(set_attr "type" "extend,load_byte")
5451 (set_attr "predicable" "yes")]
5454 (define_insn "*arm_zero_extendqisi2addsi"
5455 [(set (match_operand:SI 0 "s_register_operand" "=r")
5456 (plus:SI (zero_extend:SI (match_operand:QI 1 "s_register_operand" "r"))
5457 (match_operand:SI 2 "s_register_operand" "r")))]
5459 "uxtab%?\\t%0, %2, %1"
5460 [(set_attr "predicable" "yes")
5461 (set_attr "type" "alu_shift_reg")]
5465 [(set (match_operand:SI 0 "s_register_operand" "")
5466 (zero_extend:SI (subreg:QI (match_operand:SI 1 "" "") 0)))
5467 (clobber (match_operand:SI 2 "s_register_operand" ""))]
5468 "TARGET_32BIT && (!MEM_P (operands[1])) && ! BYTES_BIG_ENDIAN"
5469 [(set (match_dup 2) (match_dup 1))
5470 (set (match_dup 0) (and:SI (match_dup 2) (const_int 255)))]
5475 [(set (match_operand:SI 0 "s_register_operand" "")
5476 (zero_extend:SI (subreg:QI (match_operand:SI 1 "" "") 3)))
5477 (clobber (match_operand:SI 2 "s_register_operand" ""))]
5478 "TARGET_32BIT && (!MEM_P (operands[1])) && BYTES_BIG_ENDIAN"
5479 [(set (match_dup 2) (match_dup 1))
5480 (set (match_dup 0) (and:SI (match_dup 2) (const_int 255)))]
5486 [(set (match_operand:SI 0 "s_register_operand" "")
5487 (IOR_XOR:SI (and:SI (ashift:SI
5488 (match_operand:SI 1 "s_register_operand" "")
5489 (match_operand:SI 2 "const_int_operand" ""))
5490 (match_operand:SI 3 "const_int_operand" ""))
5492 (match_operator 5 "subreg_lowpart_operator"
5493 [(match_operand:SI 4 "s_register_operand" "")]))))]
5495 && (UINTVAL (operands[3])
5496 == (GET_MODE_MASK (GET_MODE (operands[5]))
5497 & (GET_MODE_MASK (GET_MODE (operands[5]))
5498 << (INTVAL (operands[2])))))"
5499 [(set (match_dup 0) (IOR_XOR:SI (ashift:SI (match_dup 1) (match_dup 2))
5501 (set (match_dup 0) (zero_extend:SI (match_dup 5)))]
5502 "operands[5] = gen_lowpart (GET_MODE (operands[5]), operands[0]);"
5505 (define_insn "*compareqi_eq0"
5506 [(set (reg:CC_Z CC_REGNUM)
5507 (compare:CC_Z (match_operand:QI 0 "s_register_operand" "r")
5511 [(set_attr "conds" "set")
5512 (set_attr "predicable" "yes")
5513 (set_attr "type" "logic_imm")]
5516 (define_expand "extendhisi2"
5517 [(set (match_operand:SI 0 "s_register_operand" "")
5518 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
5523 emit_insn (gen_thumb1_extendhisi2 (operands[0], operands[1]));
5526 if (MEM_P (operands[1]) && TARGET_ARM && !arm_arch4)
5528 emit_insn (gen_extendhisi2_mem (operands[0], operands[1]));
5532 if (!arm_arch6 && !MEM_P (operands[1]))
5534 rtx t = gen_lowpart (SImode, operands[1]);
5535 rtx tmp = gen_reg_rtx (SImode);
5536 emit_insn (gen_ashlsi3 (tmp, t, GEN_INT (16)));
5537 emit_insn (gen_ashrsi3 (operands[0], tmp, GEN_INT (16)));
5544 [(set (match_operand:SI 0 "register_operand" "")
5545 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))
5546 (clobber (match_scratch:SI 2 ""))])]
5548 [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16)))
5549 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 16)))]
5551 operands[2] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
5554 ;; This pattern will only be used when ldsh is not available
5555 (define_expand "extendhisi2_mem"
5556 [(set (match_dup 2) (zero_extend:SI (match_operand:HI 1 "" "")))
5558 (zero_extend:SI (match_dup 7)))
5559 (set (match_dup 6) (ashift:SI (match_dup 4) (const_int 24)))
5560 (set (match_operand:SI 0 "" "")
5561 (ior:SI (ashiftrt:SI (match_dup 6) (const_int 16)) (match_dup 5)))]
5566 rtx addr = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
5568 mem1 = change_address (operands[1], QImode, addr);
5569 mem2 = change_address (operands[1], QImode,
5570 plus_constant (Pmode, addr, 1));
5571 operands[0] = gen_lowpart (SImode, operands[0]);
5573 operands[2] = gen_reg_rtx (SImode);
5574 operands[3] = gen_reg_rtx (SImode);
5575 operands[6] = gen_reg_rtx (SImode);
5578 if (BYTES_BIG_ENDIAN)
5580 operands[4] = operands[2];
5581 operands[5] = operands[3];
5585 operands[4] = operands[3];
5586 operands[5] = operands[2];
5592 [(set (match_operand:SI 0 "register_operand" "")
5593 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
5595 [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16)))
5596 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 16)))]
5598 operands[2] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
5601 (define_insn "*arm_extendhisi2"
5602 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
5603 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,Uh")))]
5604 "TARGET_ARM && arm_arch4 && !arm_arch6"
5608 [(set_attr "length" "8,4")
5609 (set_attr "type" "alu_shift_reg,load_byte")
5610 (set_attr "predicable" "yes")]
5613 ;; ??? Check Thumb-2 pool range
5614 (define_insn "*arm_extendhisi2_v6"
5615 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
5616 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,Uh")))]
5617 "TARGET_32BIT && arm_arch6"
5621 [(set_attr "type" "extend,load_byte")
5622 (set_attr "predicable" "yes")]
5625 (define_insn "*arm_extendhisi2addsi"
5626 [(set (match_operand:SI 0 "s_register_operand" "=r")
5627 (plus:SI (sign_extend:SI (match_operand:HI 1 "s_register_operand" "r"))
5628 (match_operand:SI 2 "s_register_operand" "r")))]
5630 "sxtah%?\\t%0, %2, %1"
5631 [(set_attr "type" "alu_shift_reg")]
5634 (define_expand "extendqihi2"
5636 (ashift:SI (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "")
5638 (set (match_operand:HI 0 "s_register_operand" "")
5639 (ashiftrt:SI (match_dup 2)
5644 if (arm_arch4 && MEM_P (operands[1]))
5646 emit_insn (gen_rtx_SET (operands[0],
5647 gen_rtx_SIGN_EXTEND (HImode, operands[1])));
5650 if (!s_register_operand (operands[1], QImode))
5651 operands[1] = copy_to_mode_reg (QImode, operands[1]);
5652 operands[0] = gen_lowpart (SImode, operands[0]);
5653 operands[1] = gen_lowpart (SImode, operands[1]);
5654 operands[2] = gen_reg_rtx (SImode);
5658 (define_insn "*arm_extendqihi_insn"
5659 [(set (match_operand:HI 0 "s_register_operand" "=r")
5660 (sign_extend:HI (match_operand:QI 1 "arm_extendqisi_mem_op" "Uq")))]
5661 "TARGET_ARM && arm_arch4"
5663 [(set_attr "type" "load_byte")
5664 (set_attr "predicable" "yes")]
5667 (define_expand "extendqisi2"
5668 [(set (match_operand:SI 0 "s_register_operand" "")
5669 (sign_extend:SI (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "")))]
5672 if (!arm_arch4 && MEM_P (operands[1]))
5673 operands[1] = copy_to_mode_reg (QImode, operands[1]);
5675 if (!arm_arch6 && !MEM_P (operands[1]))
5677 rtx t = gen_lowpart (SImode, operands[1]);
5678 rtx tmp = gen_reg_rtx (SImode);
5679 emit_insn (gen_ashlsi3 (tmp, t, GEN_INT (24)));
5680 emit_insn (gen_ashrsi3 (operands[0], tmp, GEN_INT (24)));
5686 [(set (match_operand:SI 0 "register_operand" "")
5687 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
5689 [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 24)))
5690 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))]
5692 operands[2] = simplify_gen_subreg (SImode, operands[1], QImode, 0);
5695 (define_insn "*arm_extendqisi"
5696 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
5697 (sign_extend:SI (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "r,Uq")))]
5698 "TARGET_ARM && arm_arch4 && !arm_arch6"
5702 [(set_attr "length" "8,4")
5703 (set_attr "type" "alu_shift_reg,load_byte")
5704 (set_attr "predicable" "yes")]
5707 (define_insn "*arm_extendqisi_v6"
5708 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
5710 (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "r,Uq")))]
5711 "TARGET_ARM && arm_arch6"
5715 [(set_attr "type" "extend,load_byte")
5716 (set_attr "predicable" "yes")]
5719 (define_insn "*arm_extendqisi2addsi"
5720 [(set (match_operand:SI 0 "s_register_operand" "=r")
5721 (plus:SI (sign_extend:SI (match_operand:QI 1 "s_register_operand" "r"))
5722 (match_operand:SI 2 "s_register_operand" "r")))]
5724 "sxtab%?\\t%0, %2, %1"
5725 [(set_attr "type" "alu_shift_reg")
5726 (set_attr "predicable" "yes")]
5729 (define_expand "extendsfdf2"
5730 [(set (match_operand:DF 0 "s_register_operand" "")
5731 (float_extend:DF (match_operand:SF 1 "s_register_operand" "")))]
5732 "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
5736 ;; HFmode -> DFmode conversions where we don't have an instruction for it
5737 ;; must go through SFmode.
5739 ;; This is always safe for an extend.
5741 (define_expand "extendhfdf2"
5742 [(set (match_operand:DF 0 "s_register_operand" "")
5743 (float_extend:DF (match_operand:HF 1 "s_register_operand" "")))]
5746 /* We don't have a direct instruction for this, so go via SFmode. */
5747 if (!(TARGET_32BIT && TARGET_FP16_TO_DOUBLE))
5750 op1 = convert_to_mode (SFmode, operands[1], 0);
5751 op1 = convert_to_mode (DFmode, op1, 0);
5752 emit_insn (gen_movdf (operands[0], op1));
5755 /* Otherwise, we're done producing RTL and will pick up the correct
5756 pattern to do this with one rounding-step in a single instruction. */
5760 ;; Move insns (including loads and stores)
5762 ;; XXX Just some ideas about movti.
5763 ;; I don't think these are a good idea on the arm, there just aren't enough
5765 ;;(define_expand "loadti"
5766 ;; [(set (match_operand:TI 0 "s_register_operand" "")
5767 ;; (mem:TI (match_operand:SI 1 "address_operand" "")))]
5770 ;;(define_expand "storeti"
5771 ;; [(set (mem:TI (match_operand:TI 0 "address_operand" ""))
5772 ;; (match_operand:TI 1 "s_register_operand" ""))]
5775 ;;(define_expand "movti"
5776 ;; [(set (match_operand:TI 0 "general_operand" "")
5777 ;; (match_operand:TI 1 "general_operand" ""))]
5783 ;; if (MEM_P (operands[0]) && MEM_P (operands[1]))
5784 ;; operands[1] = copy_to_reg (operands[1]);
5785 ;; if (MEM_P (operands[0]))
5786 ;; insn = gen_storeti (XEXP (operands[0], 0), operands[1]);
5787 ;; else if (MEM_P (operands[1]))
5788 ;; insn = gen_loadti (operands[0], XEXP (operands[1], 0));
5792 ;; emit_insn (insn);
5796 ;; Recognize garbage generated above.
5799 ;; [(set (match_operand:TI 0 "general_operand" "=r,r,r,<,>,m")
5800 ;; (match_operand:TI 1 "general_operand" "<,>,m,r,r,r"))]
5804 ;; register mem = (which_alternative < 3);
5805 ;; register const char *template;
5807 ;; operands[mem] = XEXP (operands[mem], 0);
5808 ;; switch (which_alternative)
5810 ;; case 0: template = \"ldmdb\\t%1!, %M0\"; break;
5811 ;; case 1: template = \"ldmia\\t%1!, %M0\"; break;
5812 ;; case 2: template = \"ldmia\\t%1, %M0\"; break;
5813 ;; case 3: template = \"stmdb\\t%0!, %M1\"; break;
5814 ;; case 4: template = \"stmia\\t%0!, %M1\"; break;
5815 ;; case 5: template = \"stmia\\t%0, %M1\"; break;
5817 ;; output_asm_insn (template, operands);
5821 (define_expand "movdi"
5822 [(set (match_operand:DI 0 "general_operand" "")
5823 (match_operand:DI 1 "general_operand" ""))]
5826 if (can_create_pseudo_p ())
5828 if (!REG_P (operands[0]))
5829 operands[1] = force_reg (DImode, operands[1]);
5831 if (REG_P (operands[0]) && REGNO (operands[0]) <= LAST_ARM_REGNUM
5832 && !targetm.hard_regno_mode_ok (REGNO (operands[0]), DImode))
5834 /* Avoid LDRD's into an odd-numbered register pair in ARM state
5835 when expanding function calls. */
5836 gcc_assert (can_create_pseudo_p ());
5837 if (MEM_P (operands[1]) && MEM_VOLATILE_P (operands[1]))
5839 /* Perform load into legal reg pair first, then move. */
5840 rtx reg = gen_reg_rtx (DImode);
5841 emit_insn (gen_movdi (reg, operands[1]));
5844 emit_move_insn (gen_lowpart (SImode, operands[0]),
5845 gen_lowpart (SImode, operands[1]));
5846 emit_move_insn (gen_highpart (SImode, operands[0]),
5847 gen_highpart (SImode, operands[1]));
5850 else if (REG_P (operands[1]) && REGNO (operands[1]) <= LAST_ARM_REGNUM
5851 && !targetm.hard_regno_mode_ok (REGNO (operands[1]), DImode))
5853 /* Avoid STRD's from an odd-numbered register pair in ARM state
5854 when expanding function prologue. */
5855 gcc_assert (can_create_pseudo_p ());
5856 rtx split_dest = (MEM_P (operands[0]) && MEM_VOLATILE_P (operands[0]))
5857 ? gen_reg_rtx (DImode)
5859 emit_move_insn (gen_lowpart (SImode, split_dest),
5860 gen_lowpart (SImode, operands[1]));
5861 emit_move_insn (gen_highpart (SImode, split_dest),
5862 gen_highpart (SImode, operands[1]));
5863 if (split_dest != operands[0])
5864 emit_insn (gen_movdi (operands[0], split_dest));
5870 (define_insn "*arm_movdi"
5871 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, r, m")
5872 (match_operand:DI 1 "di_operand" "rDa,Db,Dc,mi,r"))]
5874 && !(TARGET_HARD_FLOAT)
5876 && ( register_operand (operands[0], DImode)
5877 || register_operand (operands[1], DImode))"
5879 switch (which_alternative)
5886 /* Cannot load it directly, split to load it via MOV / MOVT. */
5887 if (!MEM_P (operands[1]) && arm_disable_literal_pool)
5891 return output_move_double (operands, true, NULL);
5894 [(set_attr "length" "8,12,16,8,8")
5895 (set_attr "type" "multiple,multiple,multiple,load_8,store_8")
5896 (set_attr "arm_pool_range" "*,*,*,1020,*")
5897 (set_attr "arm_neg_pool_range" "*,*,*,1004,*")
5898 (set_attr "thumb2_pool_range" "*,*,*,4094,*")
5899 (set_attr "thumb2_neg_pool_range" "*,*,*,0,*")]
5903 [(set (match_operand:ANY64 0 "arm_general_register_operand" "")
5904 (match_operand:ANY64 1 "immediate_operand" ""))]
5907 && (arm_disable_literal_pool
5908 || (arm_const_double_inline_cost (operands[1])
5909 <= arm_max_const_double_inline_cost ()))"
5912 arm_split_constant (SET, SImode, curr_insn,
5913 INTVAL (gen_lowpart (SImode, operands[1])),
5914 gen_lowpart (SImode, operands[0]), NULL_RTX, 0);
5915 arm_split_constant (SET, SImode, curr_insn,
5916 INTVAL (gen_highpart_mode (SImode,
5917 GET_MODE (operands[0]),
5919 gen_highpart (SImode, operands[0]), NULL_RTX, 0);
5924 ; If optimizing for size, or if we have load delay slots, then
5925 ; we want to split the constant into two separate operations.
5926 ; In both cases this may split a trivial part into a single data op
5927 ; leaving a single complex constant to load. We can also get longer
5928 ; offsets in a LDR which means we get better chances of sharing the pool
5929 ; entries. Finally, we can normally do a better job of scheduling
5930 ; LDR instructions than we can with LDM.
5931 ; This pattern will only match if the one above did not.
5933 [(set (match_operand:ANY64 0 "arm_general_register_operand" "")
5934 (match_operand:ANY64 1 "const_double_operand" ""))]
5935 "TARGET_ARM && reload_completed
5936 && arm_const_double_by_parts (operands[1])"
5937 [(set (match_dup 0) (match_dup 1))
5938 (set (match_dup 2) (match_dup 3))]
5940 operands[2] = gen_highpart (SImode, operands[0]);
5941 operands[3] = gen_highpart_mode (SImode, GET_MODE (operands[0]),
5943 operands[0] = gen_lowpart (SImode, operands[0]);
5944 operands[1] = gen_lowpart (SImode, operands[1]);
5949 [(set (match_operand:ANY64 0 "arm_general_register_operand" "")
5950 (match_operand:ANY64 1 "arm_general_register_operand" ""))]
5951 "TARGET_EITHER && reload_completed"
5952 [(set (match_dup 0) (match_dup 1))
5953 (set (match_dup 2) (match_dup 3))]
5955 operands[2] = gen_highpart (SImode, operands[0]);
5956 operands[3] = gen_highpart (SImode, operands[1]);
5957 operands[0] = gen_lowpart (SImode, operands[0]);
5958 operands[1] = gen_lowpart (SImode, operands[1]);
5960 /* Handle a partial overlap. */
5961 if (rtx_equal_p (operands[0], operands[3]))
5963 rtx tmp0 = operands[0];
5964 rtx tmp1 = operands[1];
5966 operands[0] = operands[2];
5967 operands[1] = operands[3];
5974 ;; We can't actually do base+index doubleword loads if the index and
5975 ;; destination overlap. Split here so that we at least have chance to
5978 [(set (match_operand:DI 0 "s_register_operand" "")
5979 (mem:DI (plus:SI (match_operand:SI 1 "s_register_operand" "")
5980 (match_operand:SI 2 "s_register_operand" ""))))]
5982 && reg_overlap_mentioned_p (operands[0], operands[1])
5983 && reg_overlap_mentioned_p (operands[0], operands[2])"
5985 (plus:SI (match_dup 1)
5988 (mem:DI (match_dup 4)))]
5990 operands[4] = gen_rtx_REG (SImode, REGNO(operands[0]));
5994 (define_expand "movsi"
5995 [(set (match_operand:SI 0 "general_operand" "")
5996 (match_operand:SI 1 "general_operand" ""))]
6000 rtx base, offset, tmp;
6002 if (TARGET_32BIT || TARGET_HAVE_MOVT)
6004 /* Everything except mem = const or mem = mem can be done easily. */
6005 if (MEM_P (operands[0]))
6006 operands[1] = force_reg (SImode, operands[1]);
6007 if (arm_general_register_operand (operands[0], SImode)
6008 && CONST_INT_P (operands[1])
6009 && !(const_ok_for_arm (INTVAL (operands[1]))
6010 || const_ok_for_arm (~INTVAL (operands[1]))))
6012 if (DONT_EARLY_SPLIT_CONSTANT (INTVAL (operands[1]), SET))
6014 emit_insn (gen_rtx_SET (operands[0], operands[1]));
6019 arm_split_constant (SET, SImode, NULL_RTX,
6020 INTVAL (operands[1]), operands[0], NULL_RTX,
6021 optimize && can_create_pseudo_p ());
6026 else /* Target doesn't have MOVT... */
6028 if (can_create_pseudo_p ())
6030 if (!REG_P (operands[0]))
6031 operands[1] = force_reg (SImode, operands[1]);
6035 split_const (operands[1], &base, &offset);
6036 if (INTVAL (offset) != 0
6037 && targetm.cannot_force_const_mem (SImode, operands[1]))
6039 tmp = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0];
6040 emit_move_insn (tmp, base);
6041 emit_insn (gen_addsi3 (operands[0], tmp, offset));
6045 tmp = can_create_pseudo_p () ? NULL_RTX : operands[0];
6047 /* Recognize the case where operand[1] is a reference to thread-local
6048 data and load its address to a register. Offsets have been split off
6050 if (arm_tls_referenced_p (operands[1]))
6051 operands[1] = legitimize_tls_address (operands[1], tmp);
6053 && (CONSTANT_P (operands[1])
6054 || symbol_mentioned_p (operands[1])
6055 || label_mentioned_p (operands[1])))
6057 legitimize_pic_address (operands[1], SImode, tmp, NULL_RTX, false);
6062 ;; The ARM LO_SUM and HIGH are backwards - HIGH sets the low bits, and
6063 ;; LO_SUM adds in the high bits. Fortunately these are opaque operations
6064 ;; so this does not matter.
6065 (define_insn "*arm_movt"
6066 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r")
6067 (lo_sum:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6068 (match_operand:SI 2 "general_operand" "i,i")))]
6069 "TARGET_HAVE_MOVT && arm_valid_symbolic_address_p (operands[2])"
6071 movt%?\t%0, #:upper16:%c2
6072 movt\t%0, #:upper16:%c2"
6073 [(set_attr "arch" "32,v8mb")
6074 (set_attr "predicable" "yes")
6075 (set_attr "length" "4")
6076 (set_attr "type" "alu_sreg")]
6079 (define_insn "*arm_movsi_insn"
6080 [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m")
6081 (match_operand:SI 1 "general_operand" "rk, I,K,j,mi,rk"))]
6082 "TARGET_ARM && !TARGET_IWMMXT && !TARGET_HARD_FLOAT
6083 && ( register_operand (operands[0], SImode)
6084 || register_operand (operands[1], SImode))"
6092 [(set_attr "type" "mov_reg,mov_imm,mvn_imm,mov_imm,load_4,store_4")
6093 (set_attr "predicable" "yes")
6094 (set_attr "arch" "*,*,*,v6t2,*,*")
6095 (set_attr "pool_range" "*,*,*,*,4096,*")
6096 (set_attr "neg_pool_range" "*,*,*,*,4084,*")]
6100 [(set (match_operand:SI 0 "arm_general_register_operand" "")
6101 (match_operand:SI 1 "const_int_operand" ""))]
6102 "(TARGET_32BIT || TARGET_HAVE_MOVT)
6103 && (!(const_ok_for_arm (INTVAL (operands[1]))
6104 || const_ok_for_arm (~INTVAL (operands[1]))))"
6105 [(clobber (const_int 0))]
6107 arm_split_constant (SET, SImode, NULL_RTX,
6108 INTVAL (operands[1]), operands[0], NULL_RTX, 0);
6113 ;; A normal way to do (symbol + offset) requires three instructions at least
6114 ;; (depends on how big the offset is) as below:
6115 ;; movw r0, #:lower16:g
6116 ;; movw r0, #:upper16:g
6119 ;; A better way would be:
6120 ;; movw r0, #:lower16:g+4
6121 ;; movw r0, #:upper16:g+4
6123 ;; The limitation of this way is that the length of offset should be a 16-bit
6124 ;; signed value, because current assembler only supports REL type relocation for
6125 ;; such case. If the more powerful RELA type is supported in future, we should
6126 ;; update this pattern to go with better way.
6128 [(set (match_operand:SI 0 "arm_general_register_operand" "")
6129 (const:SI (plus:SI (match_operand:SI 1 "general_operand" "")
6130 (match_operand:SI 2 "const_int_operand" ""))))]
6133 && arm_disable_literal_pool
6135 && GET_CODE (operands[1]) == SYMBOL_REF"
6136 [(clobber (const_int 0))]
6138 int offset = INTVAL (operands[2]);
6140 if (offset < -0x8000 || offset > 0x7fff)
6142 arm_emit_movpair (operands[0], operands[1]);
6143 emit_insn (gen_rtx_SET (operands[0],
6144 gen_rtx_PLUS (SImode, operands[0], operands[2])));
6148 rtx op = gen_rtx_CONST (SImode,
6149 gen_rtx_PLUS (SImode, operands[1], operands[2]));
6150 arm_emit_movpair (operands[0], op);
6155 ;; Split symbol_refs at the later stage (after cprop), instead of generating
6156 ;; movt/movw pair directly at expand. Otherwise corresponding high_sum
6157 ;; and lo_sum would be merged back into memory load at cprop. However,
6158 ;; if the default is to prefer movt/movw rather than a load from the constant
6159 ;; pool, the performance is better.
6161 [(set (match_operand:SI 0 "arm_general_register_operand" "")
6162 (match_operand:SI 1 "general_operand" ""))]
6163 "TARGET_USE_MOVT && GET_CODE (operands[1]) == SYMBOL_REF
6164 && !target_word_relocations
6165 && !arm_tls_referenced_p (operands[1])"
6166 [(clobber (const_int 0))]
6168 arm_emit_movpair (operands[0], operands[1]);
6172 ;; When generating pic, we need to load the symbol offset into a register.
6173 ;; So that the optimizer does not confuse this with a normal symbol load
6174 ;; we use an unspec. The offset will be loaded from a constant pool entry,
6175 ;; since that is the only type of relocation we can use.
6177 ;; Wrap calculation of the whole PIC address in a single pattern for the
6178 ;; benefit of optimizers, particularly, PRE and HOIST. Calculation of
6179 ;; a PIC address involves two loads from memory, so we want to CSE it
6180 ;; as often as possible.
6181 ;; This pattern will be split into one of the pic_load_addr_* patterns
6182 ;; and a move after GCSE optimizations.
6184 ;; Note: Update arm.c: legitimize_pic_address() when changing this pattern.
6185 (define_expand "calculate_pic_address"
6186 [(set (match_operand:SI 0 "register_operand" "")
6187 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "")
6188 (unspec:SI [(match_operand:SI 2 "" "")]
6193 ;; Split calculate_pic_address into pic_load_addr_* and a move.
6195 [(set (match_operand:SI 0 "register_operand" "")
6196 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "")
6197 (unspec:SI [(match_operand:SI 2 "" "")]
6200 [(set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_PIC_SYM))
6201 (set (match_dup 0) (mem:SI (plus:SI (match_dup 1) (match_dup 3))))]
6202 "operands[3] = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0];"
6205 ;; operand1 is the memory address to go into
6206 ;; pic_load_addr_32bit.
6207 ;; operand2 is the PIC label to be emitted
6208 ;; from pic_add_dot_plus_eight.
6209 ;; We do this to allow hoisting of the entire insn.
6210 (define_insn_and_split "pic_load_addr_unified"
6211 [(set (match_operand:SI 0 "s_register_operand" "=r,r,l")
6212 (unspec:SI [(match_operand:SI 1 "" "mX,mX,mX")
6213 (match_operand:SI 2 "" "")]
6214 UNSPEC_PIC_UNIFIED))]
6217 "&& reload_completed"
6218 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_PIC_SYM))
6219 (set (match_dup 0) (unspec:SI [(match_dup 0) (match_dup 3)
6220 (match_dup 2)] UNSPEC_PIC_BASE))]
6221 "operands[3] = TARGET_THUMB ? GEN_INT (4) : GEN_INT (8);"
6222 [(set_attr "type" "load_4,load_4,load_4")
6223 (set_attr "pool_range" "4096,4094,1022")
6224 (set_attr "neg_pool_range" "4084,0,0")
6225 (set_attr "arch" "a,t2,t1")
6226 (set_attr "length" "8,6,4")]
6229 ;; The rather odd constraints on the following are to force reload to leave
6230 ;; the insn alone, and to force the minipool generation pass to then move
6231 ;; the GOT symbol to memory.
6233 (define_insn "pic_load_addr_32bit"
6234 [(set (match_operand:SI 0 "s_register_operand" "=r")
6235 (unspec:SI [(match_operand:SI 1 "" "mX")] UNSPEC_PIC_SYM))]
6236 "TARGET_32BIT && flag_pic"
6238 [(set_attr "type" "load_4")
6239 (set (attr "pool_range")
6240 (if_then_else (eq_attr "is_thumb" "no")
6243 (set (attr "neg_pool_range")
6244 (if_then_else (eq_attr "is_thumb" "no")
6249 (define_insn "pic_load_addr_thumb1"
6250 [(set (match_operand:SI 0 "s_register_operand" "=l")
6251 (unspec:SI [(match_operand:SI 1 "" "mX")] UNSPEC_PIC_SYM))]
6252 "TARGET_THUMB1 && flag_pic"
6254 [(set_attr "type" "load_4")
6255 (set (attr "pool_range") (const_int 1018))]
6258 (define_insn "pic_add_dot_plus_four"
6259 [(set (match_operand:SI 0 "register_operand" "=r")
6260 (unspec:SI [(match_operand:SI 1 "register_operand" "0")
6262 (match_operand 2 "" "")]
6266 (*targetm.asm_out.internal_label) (asm_out_file, \"LPIC\",
6267 INTVAL (operands[2]));
6268 return \"add\\t%0, %|pc\";
6270 [(set_attr "length" "2")
6271 (set_attr "type" "alu_sreg")]
6274 (define_insn "pic_add_dot_plus_eight"
6275 [(set (match_operand:SI 0 "register_operand" "=r")
6276 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
6278 (match_operand 2 "" "")]
6282 (*targetm.asm_out.internal_label) (asm_out_file, \"LPIC\",
6283 INTVAL (operands[2]));
6284 return \"add%?\\t%0, %|pc, %1\";
6286 [(set_attr "predicable" "yes")
6287 (set_attr "type" "alu_sreg")]
6290 (define_insn "tls_load_dot_plus_eight"
6291 [(set (match_operand:SI 0 "register_operand" "=r")
6292 (mem:SI (unspec:SI [(match_operand:SI 1 "register_operand" "r")
6294 (match_operand 2 "" "")]
6298 (*targetm.asm_out.internal_label) (asm_out_file, \"LPIC\",
6299 INTVAL (operands[2]));
6300 return \"ldr%?\\t%0, [%|pc, %1]\t\t@ tls_load_dot_plus_eight\";
6302 [(set_attr "predicable" "yes")
6303 (set_attr "type" "load_4")]
6306 ;; PIC references to local variables can generate pic_add_dot_plus_eight
6307 ;; followed by a load. These sequences can be crunched down to
6308 ;; tls_load_dot_plus_eight by a peephole.
6311 [(set (match_operand:SI 0 "register_operand" "")
6312 (unspec:SI [(match_operand:SI 3 "register_operand" "")
6314 (match_operand 1 "" "")]
6316 (set (match_operand:SI 2 "arm_general_register_operand" "")
6317 (mem:SI (match_dup 0)))]
6318 "TARGET_ARM && peep2_reg_dead_p (2, operands[0])"
6320 (mem:SI (unspec:SI [(match_dup 3)
6327 (define_insn "pic_offset_arm"
6328 [(set (match_operand:SI 0 "register_operand" "=r")
6329 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
6330 (unspec:SI [(match_operand:SI 2 "" "X")]
6331 UNSPEC_PIC_OFFSET))))]
6332 "TARGET_VXWORKS_RTP && TARGET_ARM && flag_pic"
6333 "ldr%?\\t%0, [%1,%2]"
6334 [(set_attr "type" "load_4")]
6337 (define_expand "builtin_setjmp_receiver"
6338 [(label_ref (match_operand 0 "" ""))]
6342 /* r3 is clobbered by set/longjmp, so we can use it as a scratch
6344 if (arm_pic_register != INVALID_REGNUM)
6345 arm_load_pic_register (1UL << 3, NULL_RTX);
6349 ;; If copying one reg to another we can set the condition codes according to
6350 ;; its value. Such a move is common after a return from subroutine and the
6351 ;; result is being tested against zero.
6353 (define_insn "*movsi_compare0"
6354 [(set (reg:CC CC_REGNUM)
6355 (compare:CC (match_operand:SI 1 "s_register_operand" "0,r")
6357 (set (match_operand:SI 0 "s_register_operand" "=r,r")
6362 subs%?\\t%0, %1, #0"
6363 [(set_attr "conds" "set")
6364 (set_attr "type" "alus_imm,alus_imm")]
6367 ;; Subroutine to store a half word from a register into memory.
6368 ;; Operand 0 is the source register (HImode)
6369 ;; Operand 1 is the destination address in a register (SImode)
6371 ;; In both this routine and the next, we must be careful not to spill
6372 ;; a memory address of reg+large_const into a separate PLUS insn, since this
6373 ;; can generate unrecognizable rtl.
6375 (define_expand "storehi"
6376 [;; store the low byte
6377 (set (match_operand 1 "" "") (match_dup 3))
6378 ;; extract the high byte
6380 (ashiftrt:SI (match_operand 0 "" "") (const_int 8)))
6381 ;; store the high byte
6382 (set (match_dup 4) (match_dup 5))]
6386 rtx op1 = operands[1];
6387 rtx addr = XEXP (op1, 0);
6388 enum rtx_code code = GET_CODE (addr);
6390 if ((code == PLUS && !CONST_INT_P (XEXP (addr, 1)))
6392 op1 = replace_equiv_address (operands[1], force_reg (SImode, addr));
6394 operands[4] = adjust_address (op1, QImode, 1);
6395 operands[1] = adjust_address (operands[1], QImode, 0);
6396 operands[3] = gen_lowpart (QImode, operands[0]);
6397 operands[0] = gen_lowpart (SImode, operands[0]);
6398 operands[2] = gen_reg_rtx (SImode);
6399 operands[5] = gen_lowpart (QImode, operands[2]);
6403 (define_expand "storehi_bigend"
6404 [(set (match_dup 4) (match_dup 3))
6406 (ashiftrt:SI (match_operand 0 "" "") (const_int 8)))
6407 (set (match_operand 1 "" "") (match_dup 5))]
6411 rtx op1 = operands[1];
6412 rtx addr = XEXP (op1, 0);
6413 enum rtx_code code = GET_CODE (addr);
6415 if ((code == PLUS && !CONST_INT_P (XEXP (addr, 1)))
6417 op1 = replace_equiv_address (op1, force_reg (SImode, addr));
6419 operands[4] = adjust_address (op1, QImode, 1);
6420 operands[1] = adjust_address (operands[1], QImode, 0);
6421 operands[3] = gen_lowpart (QImode, operands[0]);
6422 operands[0] = gen_lowpart (SImode, operands[0]);
6423 operands[2] = gen_reg_rtx (SImode);
6424 operands[5] = gen_lowpart (QImode, operands[2]);
6428 ;; Subroutine to store a half word integer constant into memory.
6429 (define_expand "storeinthi"
6430 [(set (match_operand 0 "" "")
6431 (match_operand 1 "" ""))
6432 (set (match_dup 3) (match_dup 2))]
6436 HOST_WIDE_INT value = INTVAL (operands[1]);
6437 rtx addr = XEXP (operands[0], 0);
6438 rtx op0 = operands[0];
6439 enum rtx_code code = GET_CODE (addr);
6441 if ((code == PLUS && !CONST_INT_P (XEXP (addr, 1)))
6443 op0 = replace_equiv_address (op0, force_reg (SImode, addr));
6445 operands[1] = gen_reg_rtx (SImode);
6446 if (BYTES_BIG_ENDIAN)
6448 emit_insn (gen_movsi (operands[1], GEN_INT ((value >> 8) & 255)));
6449 if ((value & 255) == ((value >> 8) & 255))
6450 operands[2] = operands[1];
6453 operands[2] = gen_reg_rtx (SImode);
6454 emit_insn (gen_movsi (operands[2], GEN_INT (value & 255)));
6459 emit_insn (gen_movsi (operands[1], GEN_INT (value & 255)));
6460 if ((value & 255) == ((value >> 8) & 255))
6461 operands[2] = operands[1];
6464 operands[2] = gen_reg_rtx (SImode);
6465 emit_insn (gen_movsi (operands[2], GEN_INT ((value >> 8) & 255)));
6469 operands[3] = adjust_address (op0, QImode, 1);
6470 operands[0] = adjust_address (operands[0], QImode, 0);
6471 operands[2] = gen_lowpart (QImode, operands[2]);
6472 operands[1] = gen_lowpart (QImode, operands[1]);
6476 (define_expand "storehi_single_op"
6477 [(set (match_operand:HI 0 "memory_operand" "")
6478 (match_operand:HI 1 "general_operand" ""))]
6479 "TARGET_32BIT && arm_arch4"
6481 if (!s_register_operand (operands[1], HImode))
6482 operands[1] = copy_to_mode_reg (HImode, operands[1]);
6486 (define_expand "movhi"
6487 [(set (match_operand:HI 0 "general_operand" "")
6488 (match_operand:HI 1 "general_operand" ""))]
6493 if (can_create_pseudo_p ())
6495 if (MEM_P (operands[0]))
6499 emit_insn (gen_storehi_single_op (operands[0], operands[1]));
6502 if (CONST_INT_P (operands[1]))
6503 emit_insn (gen_storeinthi (operands[0], operands[1]));
6506 if (MEM_P (operands[1]))
6507 operands[1] = force_reg (HImode, operands[1]);
6508 if (BYTES_BIG_ENDIAN)
6509 emit_insn (gen_storehi_bigend (operands[1], operands[0]));
6511 emit_insn (gen_storehi (operands[1], operands[0]));
6515 /* Sign extend a constant, and keep it in an SImode reg. */
6516 else if (CONST_INT_P (operands[1]))
6518 rtx reg = gen_reg_rtx (SImode);
6519 HOST_WIDE_INT val = INTVAL (operands[1]) & 0xffff;
6521 /* If the constant is already valid, leave it alone. */
6522 if (!const_ok_for_arm (val))
6524 /* If setting all the top bits will make the constant
6525 loadable in a single instruction, then set them.
6526 Otherwise, sign extend the number. */
6528 if (const_ok_for_arm (~(val | ~0xffff)))
6530 else if (val & 0x8000)
6534 emit_insn (gen_movsi (reg, GEN_INT (val)));
6535 operands[1] = gen_lowpart (HImode, reg);
6537 else if (arm_arch4 && optimize && can_create_pseudo_p ()
6538 && MEM_P (operands[1]))
6540 rtx reg = gen_reg_rtx (SImode);
6542 emit_insn (gen_zero_extendhisi2 (reg, operands[1]));
6543 operands[1] = gen_lowpart (HImode, reg);
6545 else if (!arm_arch4)
6547 if (MEM_P (operands[1]))
6550 rtx offset = const0_rtx;
6551 rtx reg = gen_reg_rtx (SImode);
6553 if ((REG_P (base = XEXP (operands[1], 0))
6554 || (GET_CODE (base) == PLUS
6555 && (CONST_INT_P (offset = XEXP (base, 1)))
6556 && ((INTVAL(offset) & 1) != 1)
6557 && REG_P (base = XEXP (base, 0))))
6558 && REGNO_POINTER_ALIGN (REGNO (base)) >= 32)
6562 new_rtx = widen_memory_access (operands[1], SImode,
6563 ((INTVAL (offset) & ~3)
6564 - INTVAL (offset)));
6565 emit_insn (gen_movsi (reg, new_rtx));
6566 if (((INTVAL (offset) & 2) != 0)
6567 ^ (BYTES_BIG_ENDIAN ? 1 : 0))
6569 rtx reg2 = gen_reg_rtx (SImode);
6571 emit_insn (gen_lshrsi3 (reg2, reg, GEN_INT (16)));
6576 emit_insn (gen_movhi_bytes (reg, operands[1]));
6578 operands[1] = gen_lowpart (HImode, reg);
6582 /* Handle loading a large integer during reload. */
6583 else if (CONST_INT_P (operands[1])
6584 && !const_ok_for_arm (INTVAL (operands[1]))
6585 && !const_ok_for_arm (~INTVAL (operands[1])))
6587 /* Writing a constant to memory needs a scratch, which should
6588 be handled with SECONDARY_RELOADs. */
6589 gcc_assert (REG_P (operands[0]));
6591 operands[0] = gen_rtx_SUBREG (SImode, operands[0], 0);
6592 emit_insn (gen_movsi (operands[0], operands[1]));
6596 else if (TARGET_THUMB2)
6598 /* Thumb-2 can do everything except mem=mem and mem=const easily. */
6599 if (can_create_pseudo_p ())
6601 if (!REG_P (operands[0]))
6602 operands[1] = force_reg (HImode, operands[1]);
6603 /* Zero extend a constant, and keep it in an SImode reg. */
6604 else if (CONST_INT_P (operands[1]))
6606 rtx reg = gen_reg_rtx (SImode);
6607 HOST_WIDE_INT val = INTVAL (operands[1]) & 0xffff;
6609 emit_insn (gen_movsi (reg, GEN_INT (val)));
6610 operands[1] = gen_lowpart (HImode, reg);
6614 else /* TARGET_THUMB1 */
6616 if (can_create_pseudo_p ())
6618 if (CONST_INT_P (operands[1]))
6620 rtx reg = gen_reg_rtx (SImode);
6622 emit_insn (gen_movsi (reg, operands[1]));
6623 operands[1] = gen_lowpart (HImode, reg);
6626 /* ??? We shouldn't really get invalid addresses here, but this can
6627 happen if we are passed a SP (never OK for HImode/QImode) or
6628 virtual register (also rejected as illegitimate for HImode/QImode)
6629 relative address. */
6630 /* ??? This should perhaps be fixed elsewhere, for instance, in
6631 fixup_stack_1, by checking for other kinds of invalid addresses,
6632 e.g. a bare reference to a virtual register. This may confuse the
6633 alpha though, which must handle this case differently. */
6634 if (MEM_P (operands[0])
6635 && !memory_address_p (GET_MODE (operands[0]),
6636 XEXP (operands[0], 0)))
6638 = replace_equiv_address (operands[0],
6639 copy_to_reg (XEXP (operands[0], 0)));
6641 if (MEM_P (operands[1])
6642 && !memory_address_p (GET_MODE (operands[1]),
6643 XEXP (operands[1], 0)))
6645 = replace_equiv_address (operands[1],
6646 copy_to_reg (XEXP (operands[1], 0)));
6648 if (MEM_P (operands[1]) && optimize > 0)
6650 rtx reg = gen_reg_rtx (SImode);
6652 emit_insn (gen_zero_extendhisi2 (reg, operands[1]));
6653 operands[1] = gen_lowpart (HImode, reg);
6656 if (MEM_P (operands[0]))
6657 operands[1] = force_reg (HImode, operands[1]);
6659 else if (CONST_INT_P (operands[1])
6660 && !satisfies_constraint_I (operands[1]))
6662 /* Handle loading a large integer during reload. */
6664 /* Writing a constant to memory needs a scratch, which should
6665 be handled with SECONDARY_RELOADs. */
6666 gcc_assert (REG_P (operands[0]));
6668 operands[0] = gen_rtx_SUBREG (SImode, operands[0], 0);
6669 emit_insn (gen_movsi (operands[0], operands[1]));
6676 (define_expand "movhi_bytes"
6677 [(set (match_dup 2) (zero_extend:SI (match_operand:HI 1 "" "")))
6679 (zero_extend:SI (match_dup 6)))
6680 (set (match_operand:SI 0 "" "")
6681 (ior:SI (ashift:SI (match_dup 4) (const_int 8)) (match_dup 5)))]
6686 rtx addr = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
6688 mem1 = change_address (operands[1], QImode, addr);
6689 mem2 = change_address (operands[1], QImode,
6690 plus_constant (Pmode, addr, 1));
6691 operands[0] = gen_lowpart (SImode, operands[0]);
6693 operands[2] = gen_reg_rtx (SImode);
6694 operands[3] = gen_reg_rtx (SImode);
6697 if (BYTES_BIG_ENDIAN)
6699 operands[4] = operands[2];
6700 operands[5] = operands[3];
6704 operands[4] = operands[3];
6705 operands[5] = operands[2];
6710 (define_expand "movhi_bigend"
6712 (rotate:SI (subreg:SI (match_operand:HI 1 "memory_operand" "") 0)
6715 (ashiftrt:SI (match_dup 2) (const_int 16)))
6716 (set (match_operand:HI 0 "s_register_operand" "")
6720 operands[2] = gen_reg_rtx (SImode);
6721 operands[3] = gen_reg_rtx (SImode);
6722 operands[4] = gen_lowpart (HImode, operands[3]);
6726 ;; Pattern to recognize insn generated default case above
6727 (define_insn "*movhi_insn_arch4"
6728 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m,r")
6729 (match_operand:HI 1 "general_operand" "rIk,K,n,r,mi"))]
6731 && arm_arch4 && !TARGET_HARD_FLOAT
6732 && (register_operand (operands[0], HImode)
6733 || register_operand (operands[1], HImode))"
6735 mov%?\\t%0, %1\\t%@ movhi
6736 mvn%?\\t%0, #%B1\\t%@ movhi
6737 movw%?\\t%0, %L1\\t%@ movhi
6738 strh%?\\t%1, %0\\t%@ movhi
6739 ldrh%?\\t%0, %1\\t%@ movhi"
6740 [(set_attr "predicable" "yes")
6741 (set_attr "pool_range" "*,*,*,*,256")
6742 (set_attr "neg_pool_range" "*,*,*,*,244")
6743 (set_attr "arch" "*,*,v6t2,*,*")
6744 (set_attr_alternative "type"
6745 [(if_then_else (match_operand 1 "const_int_operand" "")
6746 (const_string "mov_imm" )
6747 (const_string "mov_reg"))
6748 (const_string "mvn_imm")
6749 (const_string "mov_imm")
6750 (const_string "store_4")
6751 (const_string "load_4")])]
6754 (define_insn "*movhi_bytes"
6755 [(set (match_operand:HI 0 "s_register_operand" "=r,r,r")
6756 (match_operand:HI 1 "arm_rhs_operand" "I,rk,K"))]
6757 "TARGET_ARM && !TARGET_HARD_FLOAT"
6759 mov%?\\t%0, %1\\t%@ movhi
6760 mov%?\\t%0, %1\\t%@ movhi
6761 mvn%?\\t%0, #%B1\\t%@ movhi"
6762 [(set_attr "predicable" "yes")
6763 (set_attr "type" "mov_imm,mov_reg,mvn_imm")]
6766 ;; We use a DImode scratch because we may occasionally need an additional
6767 ;; temporary if the address isn't offsettable -- push_reload doesn't seem
6768 ;; to take any notice of the "o" constraints on reload_memory_operand operand.
6769 (define_expand "reload_outhi"
6770 [(parallel [(match_operand:HI 0 "arm_reload_memory_operand" "=o")
6771 (match_operand:HI 1 "s_register_operand" "r")
6772 (match_operand:DI 2 "s_register_operand" "=&l")])]
6775 arm_reload_out_hi (operands);
6777 thumb_reload_out_hi (operands);
6782 (define_expand "reload_inhi"
6783 [(parallel [(match_operand:HI 0 "s_register_operand" "=r")
6784 (match_operand:HI 1 "arm_reload_memory_operand" "o")
6785 (match_operand:DI 2 "s_register_operand" "=&r")])]
6789 arm_reload_in_hi (operands);
6791 thumb_reload_out_hi (operands);
6795 (define_expand "movqi"
6796 [(set (match_operand:QI 0 "general_operand" "")
6797 (match_operand:QI 1 "general_operand" ""))]
6800 /* Everything except mem = const or mem = mem can be done easily */
6802 if (can_create_pseudo_p ())
6804 if (CONST_INT_P (operands[1]))
6806 rtx reg = gen_reg_rtx (SImode);
6808 /* For thumb we want an unsigned immediate, then we are more likely
6809 to be able to use a movs insn. */
6811 operands[1] = GEN_INT (INTVAL (operands[1]) & 255);
6813 emit_insn (gen_movsi (reg, operands[1]));
6814 operands[1] = gen_lowpart (QImode, reg);
6819 /* ??? We shouldn't really get invalid addresses here, but this can
6820 happen if we are passed a SP (never OK for HImode/QImode) or
6821 virtual register (also rejected as illegitimate for HImode/QImode)
6822 relative address. */
6823 /* ??? This should perhaps be fixed elsewhere, for instance, in
6824 fixup_stack_1, by checking for other kinds of invalid addresses,
6825 e.g. a bare reference to a virtual register. This may confuse the
6826 alpha though, which must handle this case differently. */
6827 if (MEM_P (operands[0])
6828 && !memory_address_p (GET_MODE (operands[0]),
6829 XEXP (operands[0], 0)))
6831 = replace_equiv_address (operands[0],
6832 copy_to_reg (XEXP (operands[0], 0)));
6833 if (MEM_P (operands[1])
6834 && !memory_address_p (GET_MODE (operands[1]),
6835 XEXP (operands[1], 0)))
6837 = replace_equiv_address (operands[1],
6838 copy_to_reg (XEXP (operands[1], 0)));
6841 if (MEM_P (operands[1]) && optimize > 0)
6843 rtx reg = gen_reg_rtx (SImode);
6845 emit_insn (gen_zero_extendqisi2 (reg, operands[1]));
6846 operands[1] = gen_lowpart (QImode, reg);
6849 if (MEM_P (operands[0]))
6850 operands[1] = force_reg (QImode, operands[1]);
6852 else if (TARGET_THUMB
6853 && CONST_INT_P (operands[1])
6854 && !satisfies_constraint_I (operands[1]))
6856 /* Handle loading a large integer during reload. */
6858 /* Writing a constant to memory needs a scratch, which should
6859 be handled with SECONDARY_RELOADs. */
6860 gcc_assert (REG_P (operands[0]));
6862 operands[0] = gen_rtx_SUBREG (SImode, operands[0], 0);
6863 emit_insn (gen_movsi (operands[0], operands[1]));
6869 (define_insn "*arm_movqi_insn"
6870 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,l,r,l,Uu,r,m")
6871 (match_operand:QI 1 "general_operand" "rk,rk,I,Py,K,Uu,l,Uh,r"))]
6873 && ( register_operand (operands[0], QImode)
6874 || register_operand (operands[1], QImode))"
6885 [(set_attr "type" "mov_reg,mov_reg,mov_imm,mov_imm,mvn_imm,load_4,store_4,load_4,store_4")
6886 (set_attr "predicable" "yes")
6887 (set_attr "predicable_short_it" "yes,yes,no,yes,no,no,no,no,no")
6888 (set_attr "arch" "t2,any,any,t2,any,t2,t2,any,any")
6889 (set_attr "length" "2,4,4,2,4,2,2,4,4")]
6893 (define_expand "movhf"
6894 [(set (match_operand:HF 0 "general_operand" "")
6895 (match_operand:HF 1 "general_operand" ""))]
6900 if (MEM_P (operands[0]))
6901 operands[1] = force_reg (HFmode, operands[1]);
6903 else /* TARGET_THUMB1 */
6905 if (can_create_pseudo_p ())
6907 if (!REG_P (operands[0]))
6908 operands[1] = force_reg (HFmode, operands[1]);
6914 (define_insn "*arm32_movhf"
6915 [(set (match_operand:HF 0 "nonimmediate_operand" "=r,m,r,r")
6916 (match_operand:HF 1 "general_operand" " m,r,r,F"))]
6917 "TARGET_32BIT && !TARGET_HARD_FLOAT
6918 && ( s_register_operand (operands[0], HFmode)
6919 || s_register_operand (operands[1], HFmode))"
6921 switch (which_alternative)
6923 case 0: /* ARM register from memory */
6924 return \"ldrh%?\\t%0, %1\\t%@ __fp16\";
6925 case 1: /* memory from ARM register */
6926 return \"strh%?\\t%1, %0\\t%@ __fp16\";
6927 case 2: /* ARM register from ARM register */
6928 return \"mov%?\\t%0, %1\\t%@ __fp16\";
6929 case 3: /* ARM register from constant */
6934 bits = real_to_target (NULL, CONST_DOUBLE_REAL_VALUE (operands[1]),
6936 ops[0] = operands[0];
6937 ops[1] = GEN_INT (bits);
6938 ops[2] = GEN_INT (bits & 0xff00);
6939 ops[3] = GEN_INT (bits & 0x00ff);
6941 if (arm_arch_thumb2)
6942 output_asm_insn (\"movw%?\\t%0, %1\", ops);
6944 output_asm_insn (\"mov%?\\t%0, %2\;orr%?\\t%0, %0, %3\", ops);
6951 [(set_attr "conds" "unconditional")
6952 (set_attr "type" "load_4,store_4,mov_reg,multiple")
6953 (set_attr "length" "4,4,4,8")
6954 (set_attr "predicable" "yes")]
6957 (define_expand "movsf"
6958 [(set (match_operand:SF 0 "general_operand" "")
6959 (match_operand:SF 1 "general_operand" ""))]
6964 if (MEM_P (operands[0]))
6965 operands[1] = force_reg (SFmode, operands[1]);
6967 else /* TARGET_THUMB1 */
6969 if (can_create_pseudo_p ())
6971 if (!REG_P (operands[0]))
6972 operands[1] = force_reg (SFmode, operands[1]);
6976 /* Cannot load it directly, generate a load with clobber so that it can be
6977 loaded via GPR with MOV / MOVT. */
6978 if (arm_disable_literal_pool
6979 && (REG_P (operands[0]) || SUBREG_P (operands[0]))
6980 && CONST_DOUBLE_P (operands[1])
6981 && TARGET_HARD_FLOAT
6982 && !vfp3_const_double_rtx (operands[1]))
6984 rtx clobreg = gen_reg_rtx (SFmode);
6985 emit_insn (gen_no_literal_pool_sf_immediate (operands[0], operands[1],
6992 ;; Transform a floating-point move of a constant into a core register into
6993 ;; an SImode operation.
6995 [(set (match_operand:SF 0 "arm_general_register_operand" "")
6996 (match_operand:SF 1 "immediate_operand" ""))]
6999 && CONST_DOUBLE_P (operands[1])"
7000 [(set (match_dup 2) (match_dup 3))]
7002 operands[2] = gen_lowpart (SImode, operands[0]);
7003 operands[3] = gen_lowpart (SImode, operands[1]);
7004 if (operands[2] == 0 || operands[3] == 0)
7009 (define_insn "*arm_movsf_soft_insn"
7010 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
7011 (match_operand:SF 1 "general_operand" "r,mE,r"))]
7013 && TARGET_SOFT_FLOAT
7014 && (!MEM_P (operands[0])
7015 || register_operand (operands[1], SFmode))"
7017 switch (which_alternative)
7019 case 0: return \"mov%?\\t%0, %1\";
7021 /* Cannot load it directly, split to load it via MOV / MOVT. */
7022 if (!MEM_P (operands[1]) && arm_disable_literal_pool)
7024 return \"ldr%?\\t%0, %1\\t%@ float\";
7025 case 2: return \"str%?\\t%1, %0\\t%@ float\";
7026 default: gcc_unreachable ();
7029 [(set_attr "predicable" "yes")
7030 (set_attr "type" "mov_reg,load_4,store_4")
7031 (set_attr "arm_pool_range" "*,4096,*")
7032 (set_attr "thumb2_pool_range" "*,4094,*")
7033 (set_attr "arm_neg_pool_range" "*,4084,*")
7034 (set_attr "thumb2_neg_pool_range" "*,0,*")]
7037 ;; Splitter for the above.
7039 [(set (match_operand:SF 0 "s_register_operand")
7040 (match_operand:SF 1 "const_double_operand"))]
7041 "arm_disable_literal_pool && TARGET_SOFT_FLOAT"
7045 real_to_target (&buf, CONST_DOUBLE_REAL_VALUE (operands[1]), SFmode);
7046 rtx cst = gen_int_mode (buf, SImode);
7047 emit_move_insn (simplify_gen_subreg (SImode, operands[0], SFmode, 0), cst);
7052 (define_expand "movdf"
7053 [(set (match_operand:DF 0 "general_operand" "")
7054 (match_operand:DF 1 "general_operand" ""))]
7059 if (MEM_P (operands[0]))
7060 operands[1] = force_reg (DFmode, operands[1]);
7062 else /* TARGET_THUMB */
7064 if (can_create_pseudo_p ())
7066 if (!REG_P (operands[0]))
7067 operands[1] = force_reg (DFmode, operands[1]);
7071 /* Cannot load it directly, generate a load with clobber so that it can be
7072 loaded via GPR with MOV / MOVT. */
7073 if (arm_disable_literal_pool
7074 && (REG_P (operands[0]) || SUBREG_P (operands[0]))
7075 && CONSTANT_P (operands[1])
7076 && TARGET_HARD_FLOAT
7077 && !arm_const_double_rtx (operands[1])
7078 && !(TARGET_VFP_DOUBLE && vfp3_const_double_rtx (operands[1])))
7080 rtx clobreg = gen_reg_rtx (DFmode);
7081 emit_insn (gen_no_literal_pool_df_immediate (operands[0], operands[1],
7088 ;; Reloading a df mode value stored in integer regs to memory can require a
7090 (define_expand "reload_outdf"
7091 [(match_operand:DF 0 "arm_reload_memory_operand" "=o")
7092 (match_operand:DF 1 "s_register_operand" "r")
7093 (match_operand:SI 2 "s_register_operand" "=&r")]
7097 enum rtx_code code = GET_CODE (XEXP (operands[0], 0));
7100 operands[2] = XEXP (operands[0], 0);
7101 else if (code == POST_INC || code == PRE_DEC)
7103 operands[0] = gen_rtx_SUBREG (DImode, operands[0], 0);
7104 operands[1] = gen_rtx_SUBREG (DImode, operands[1], 0);
7105 emit_insn (gen_movdi (operands[0], operands[1]));
7108 else if (code == PRE_INC)
7110 rtx reg = XEXP (XEXP (operands[0], 0), 0);
7112 emit_insn (gen_addsi3 (reg, reg, GEN_INT (8)));
7115 else if (code == POST_DEC)
7116 operands[2] = XEXP (XEXP (operands[0], 0), 0);
7118 emit_insn (gen_addsi3 (operands[2], XEXP (XEXP (operands[0], 0), 0),
7119 XEXP (XEXP (operands[0], 0), 1)));
7121 emit_insn (gen_rtx_SET (replace_equiv_address (operands[0], operands[2]),
7124 if (code == POST_DEC)
7125 emit_insn (gen_addsi3 (operands[2], operands[2], GEN_INT (-8)));
7131 (define_insn "*movdf_soft_insn"
7132 [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=r,r,r,r,m")
7133 (match_operand:DF 1 "soft_df_operand" "rDa,Db,Dc,mF,r"))]
7134 "TARGET_32BIT && TARGET_SOFT_FLOAT
7135 && ( register_operand (operands[0], DFmode)
7136 || register_operand (operands[1], DFmode))"
7138 switch (which_alternative)
7145 /* Cannot load it directly, split to load it via MOV / MOVT. */
7146 if (!MEM_P (operands[1]) && arm_disable_literal_pool)
7150 return output_move_double (operands, true, NULL);
7153 [(set_attr "length" "8,12,16,8,8")
7154 (set_attr "type" "multiple,multiple,multiple,load_8,store_8")
7155 (set_attr "arm_pool_range" "*,*,*,1020,*")
7156 (set_attr "thumb2_pool_range" "*,*,*,1018,*")
7157 (set_attr "arm_neg_pool_range" "*,*,*,1004,*")
7158 (set_attr "thumb2_neg_pool_range" "*,*,*,0,*")]
7161 ;; Splitter for the above.
7163 [(set (match_operand:DF 0 "s_register_operand")
7164 (match_operand:DF 1 "const_double_operand"))]
7165 "arm_disable_literal_pool && TARGET_SOFT_FLOAT"
7169 int order = BYTES_BIG_ENDIAN ? 1 : 0;
7170 real_to_target (buf, CONST_DOUBLE_REAL_VALUE (operands[1]), DFmode);
7171 unsigned HOST_WIDE_INT ival = zext_hwi (buf[order], 32);
7172 ival |= (zext_hwi (buf[1 - order], 32) << 32);
7173 rtx cst = gen_int_mode (ival, DImode);
7174 emit_move_insn (simplify_gen_subreg (DImode, operands[0], DFmode, 0), cst);
7180 ;; load- and store-multiple insns
7181 ;; The arm can load/store any set of registers, provided that they are in
7182 ;; ascending order, but these expanders assume a contiguous set.
7184 (define_expand "load_multiple"
7185 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
7186 (match_operand:SI 1 "" ""))
7187 (use (match_operand:SI 2 "" ""))])]
7190 HOST_WIDE_INT offset = 0;
7192 /* Support only fixed point registers. */
7193 if (!CONST_INT_P (operands[2])
7194 || INTVAL (operands[2]) > MAX_LDM_STM_OPS
7195 || INTVAL (operands[2]) < 2
7196 || !MEM_P (operands[1])
7197 || !REG_P (operands[0])
7198 || REGNO (operands[0]) > (LAST_ARM_REGNUM - 1)
7199 || REGNO (operands[0]) + INTVAL (operands[2]) > LAST_ARM_REGNUM)
7203 = arm_gen_load_multiple (arm_regs_in_sequence + REGNO (operands[0]),
7204 INTVAL (operands[2]),
7205 force_reg (SImode, XEXP (operands[1], 0)),
7206 FALSE, operands[1], &offset);
7209 (define_expand "store_multiple"
7210 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
7211 (match_operand:SI 1 "" ""))
7212 (use (match_operand:SI 2 "" ""))])]
7215 HOST_WIDE_INT offset = 0;
7217 /* Support only fixed point registers. */
7218 if (!CONST_INT_P (operands[2])
7219 || INTVAL (operands[2]) > MAX_LDM_STM_OPS
7220 || INTVAL (operands[2]) < 2
7221 || !REG_P (operands[1])
7222 || !MEM_P (operands[0])
7223 || REGNO (operands[1]) > (LAST_ARM_REGNUM - 1)
7224 || REGNO (operands[1]) + INTVAL (operands[2]) > LAST_ARM_REGNUM)
7228 = arm_gen_store_multiple (arm_regs_in_sequence + REGNO (operands[1]),
7229 INTVAL (operands[2]),
7230 force_reg (SImode, XEXP (operands[0], 0)),
7231 FALSE, operands[0], &offset);
7235 (define_expand "setmemsi"
7236 [(match_operand:BLK 0 "general_operand" "")
7237 (match_operand:SI 1 "const_int_operand" "")
7238 (match_operand:SI 2 "const_int_operand" "")
7239 (match_operand:SI 3 "const_int_operand" "")]
7242 if (arm_gen_setmem (operands))
7249 ;; Move a block of memory if it is word aligned and MORE than 2 words long.
7250 ;; We could let this apply for blocks of less than this, but it clobbers so
7251 ;; many registers that there is then probably a better way.
7253 (define_expand "cpymemqi"
7254 [(match_operand:BLK 0 "general_operand" "")
7255 (match_operand:BLK 1 "general_operand" "")
7256 (match_operand:SI 2 "const_int_operand" "")
7257 (match_operand:SI 3 "const_int_operand" "")]
7262 if (TARGET_LDRD && current_tune->prefer_ldrd_strd
7263 && !optimize_function_for_size_p (cfun))
7265 if (gen_cpymem_ldrd_strd (operands))
7270 if (arm_gen_cpymemqi (operands))
7274 else /* TARGET_THUMB1 */
7276 if ( INTVAL (operands[3]) != 4
7277 || INTVAL (operands[2]) > 48)
7280 thumb_expand_cpymemqi (operands);
7287 ;; Compare & branch insns
7288 ;; The range calculations are based as follows:
7289 ;; For forward branches, the address calculation returns the address of
7290 ;; the next instruction. This is 2 beyond the branch instruction.
7291 ;; For backward branches, the address calculation returns the address of
7292 ;; the first instruction in this pattern (cmp). This is 2 before the branch
7293 ;; instruction for the shortest sequence, and 4 before the branch instruction
7294 ;; if we have to jump around an unconditional branch.
7295 ;; To the basic branch range the PC offset must be added (this is +4).
7296 ;; So for forward branches we have
7297 ;; (pos_range - pos_base_offs + pc_offs) = (pos_range - 2 + 4).
7298 ;; And for backward branches we have
7299 ;; (neg_range - neg_base_offs + pc_offs) = (neg_range - (-2 or -4) + 4).
7301 ;; For a 'b' pos_range = 2046, neg_range = -2048 giving (-2040->2048).
7302 ;; For a 'b<cond>' pos_range = 254, neg_range = -256 giving (-250 ->256).
7304 (define_expand "cbranchsi4"
7305 [(set (pc) (if_then_else
7306 (match_operator 0 "expandable_comparison_operator"
7307 [(match_operand:SI 1 "s_register_operand" "")
7308 (match_operand:SI 2 "nonmemory_operand" "")])
7309 (label_ref (match_operand 3 "" ""))
7315 if (!arm_validize_comparison (&operands[0], &operands[1], &operands[2]))
7317 emit_jump_insn (gen_cbranch_cc (operands[0], operands[1], operands[2],
7321 if (thumb1_cmpneg_operand (operands[2], SImode))
7323 emit_jump_insn (gen_cbranchsi4_scratch (NULL, operands[1], operands[2],
7324 operands[3], operands[0]));
7327 if (!thumb1_cmp_operand (operands[2], SImode))
7328 operands[2] = force_reg (SImode, operands[2]);
7331 (define_expand "cbranchsf4"
7332 [(set (pc) (if_then_else
7333 (match_operator 0 "expandable_comparison_operator"
7334 [(match_operand:SF 1 "s_register_operand" "")
7335 (match_operand:SF 2 "vfp_compare_operand" "")])
7336 (label_ref (match_operand 3 "" ""))
7338 "TARGET_32BIT && TARGET_HARD_FLOAT"
7339 "emit_jump_insn (gen_cbranch_cc (operands[0], operands[1], operands[2],
7340 operands[3])); DONE;"
7343 (define_expand "cbranchdf4"
7344 [(set (pc) (if_then_else
7345 (match_operator 0 "expandable_comparison_operator"
7346 [(match_operand:DF 1 "s_register_operand" "")
7347 (match_operand:DF 2 "vfp_compare_operand" "")])
7348 (label_ref (match_operand 3 "" ""))
7350 "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
7351 "emit_jump_insn (gen_cbranch_cc (operands[0], operands[1], operands[2],
7352 operands[3])); DONE;"
7355 (define_expand "cbranchdi4"
7356 [(set (pc) (if_then_else
7357 (match_operator 0 "expandable_comparison_operator"
7358 [(match_operand:DI 1 "s_register_operand" "")
7359 (match_operand:DI 2 "cmpdi_operand" "")])
7360 (label_ref (match_operand 3 "" ""))
7364 if (!arm_validize_comparison (&operands[0], &operands[1], &operands[2]))
7366 emit_jump_insn (gen_cbranch_cc (operands[0], operands[1], operands[2],
7372 ;; Comparison and test insns
7374 (define_insn "*arm_cmpsi_insn"
7375 [(set (reg:CC CC_REGNUM)
7376 (compare:CC (match_operand:SI 0 "s_register_operand" "l,r,r,r,r")
7377 (match_operand:SI 1 "arm_add_operand" "Py,r,r,I,L")))]
7385 [(set_attr "conds" "set")
7386 (set_attr "arch" "t2,t2,any,any,any")
7387 (set_attr "length" "2,2,4,4,4")
7388 (set_attr "predicable" "yes")
7389 (set_attr "predicable_short_it" "yes,yes,yes,no,no")
7390 (set_attr "type" "alus_imm,alus_sreg,alus_sreg,alus_imm,alus_imm")]
7393 (define_insn "*cmpsi_shiftsi"
7394 [(set (reg:CC CC_REGNUM)
7395 (compare:CC (match_operand:SI 0 "s_register_operand" "r,r,r")
7396 (match_operator:SI 3 "shift_operator"
7397 [(match_operand:SI 1 "s_register_operand" "r,r,r")
7398 (match_operand:SI 2 "shift_amount_operand" "M,r,M")])))]
7401 [(set_attr "conds" "set")
7402 (set_attr "shift" "1")
7403 (set_attr "arch" "32,a,a")
7404 (set_attr "type" "alus_shift_imm,alus_shift_reg,alus_shift_imm")])
7406 (define_insn "*cmpsi_shiftsi_swp"
7407 [(set (reg:CC_SWP CC_REGNUM)
7408 (compare:CC_SWP (match_operator:SI 3 "shift_operator"
7409 [(match_operand:SI 1 "s_register_operand" "r,r,r")
7410 (match_operand:SI 2 "shift_amount_operand" "M,r,M")])
7411 (match_operand:SI 0 "s_register_operand" "r,r,r")))]
7414 [(set_attr "conds" "set")
7415 (set_attr "shift" "1")
7416 (set_attr "arch" "32,a,a")
7417 (set_attr "type" "alus_shift_imm,alus_shift_reg,alus_shift_imm")])
7419 (define_insn "*arm_cmpsi_negshiftsi_si"
7420 [(set (reg:CC_Z CC_REGNUM)
7422 (neg:SI (match_operator:SI 1 "shift_operator"
7423 [(match_operand:SI 2 "s_register_operand" "r")
7424 (match_operand:SI 3 "reg_or_int_operand" "rM")]))
7425 (match_operand:SI 0 "s_register_operand" "r")))]
7428 [(set_attr "conds" "set")
7429 (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "")
7430 (const_string "alus_shift_imm")
7431 (const_string "alus_shift_reg")))
7432 (set_attr "predicable" "yes")]
7435 ;; DImode comparisons. The generic code generates branches that
7436 ;; if-conversion cannot reduce to a conditional compare, so we do
7439 (define_insn_and_split "*arm_cmpdi_insn"
7440 [(set (reg:CC_NCV CC_REGNUM)
7441 (compare:CC_NCV (match_operand:DI 0 "s_register_operand" "r")
7442 (match_operand:DI 1 "arm_di_operand" "rDi")))
7443 (clobber (match_scratch:SI 2 "=r"))]
7445 "#" ; "cmp\\t%Q0, %Q1\;sbcs\\t%2, %R0, %R1"
7446 "&& reload_completed"
7447 [(set (reg:CC CC_REGNUM)
7448 (compare:CC (match_dup 0) (match_dup 1)))
7449 (parallel [(set (reg:CC CC_REGNUM)
7450 (compare:CC (match_dup 3) (match_dup 4)))
7452 (minus:SI (match_dup 5)
7453 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))])]
7455 operands[3] = gen_highpart (SImode, operands[0]);
7456 operands[0] = gen_lowpart (SImode, operands[0]);
7457 if (CONST_INT_P (operands[1]))
7459 operands[4] = gen_highpart_mode (SImode, DImode, operands[1]);
7460 if (operands[4] == const0_rtx)
7461 operands[5] = operands[3];
7463 operands[5] = gen_rtx_PLUS (SImode, operands[3],
7464 gen_int_mode (-UINTVAL (operands[4]),
7469 operands[4] = gen_highpart (SImode, operands[1]);
7470 operands[5] = gen_rtx_MINUS (SImode, operands[3], operands[4]);
7472 operands[1] = gen_lowpart (SImode, operands[1]);
7473 operands[2] = gen_lowpart (SImode, operands[2]);
7475 [(set_attr "conds" "set")
7476 (set_attr "length" "8")
7477 (set_attr "type" "multiple")]
7480 (define_insn_and_split "*arm_cmpdi_unsigned"
7481 [(set (reg:CC_CZ CC_REGNUM)
7482 (compare:CC_CZ (match_operand:DI 0 "s_register_operand" "l,r,r,r")
7483 (match_operand:DI 1 "arm_di_operand" "Py,r,Di,rDi")))]
7486 "#" ; "cmp\\t%R0, %R1\;it eq\;cmpeq\\t%Q0, %Q1"
7487 "&& reload_completed"
7488 [(set (reg:CC CC_REGNUM)
7489 (compare:CC (match_dup 2) (match_dup 3)))
7490 (cond_exec (eq:SI (reg:CC CC_REGNUM) (const_int 0))
7491 (set (reg:CC CC_REGNUM)
7492 (compare:CC (match_dup 0) (match_dup 1))))]
7494 operands[2] = gen_highpart (SImode, operands[0]);
7495 operands[0] = gen_lowpart (SImode, operands[0]);
7496 if (CONST_INT_P (operands[1]))
7497 operands[3] = gen_highpart_mode (SImode, DImode, operands[1]);
7499 operands[3] = gen_highpart (SImode, operands[1]);
7500 operands[1] = gen_lowpart (SImode, operands[1]);
7502 [(set_attr "conds" "set")
7503 (set_attr "enabled_for_short_it" "yes,yes,no,*")
7504 (set_attr "arch" "t2,t2,t2,a")
7505 (set_attr "length" "6,6,10,8")
7506 (set_attr "type" "multiple")]
7509 (define_insn "*arm_cmpdi_zero"
7510 [(set (reg:CC_Z CC_REGNUM)
7511 (compare:CC_Z (match_operand:DI 0 "s_register_operand" "r")
7513 (clobber (match_scratch:SI 1 "=r"))]
7515 "orrs%?\\t%1, %Q0, %R0"
7516 [(set_attr "conds" "set")
7517 (set_attr "type" "logics_reg")]
7520 ; This insn allows redundant compares to be removed by cse, nothing should
7521 ; ever appear in the output file since (set (reg x) (reg x)) is a no-op that
7522 ; is deleted later on. The match_dup will match the mode here, so that
7523 ; mode changes of the condition codes aren't lost by this even though we don't
7524 ; specify what they are.
7526 (define_insn "*deleted_compare"
7527 [(set (match_operand 0 "cc_register" "") (match_dup 0))]
7529 "\\t%@ deleted compare"
7530 [(set_attr "conds" "set")
7531 (set_attr "length" "0")
7532 (set_attr "type" "no_insn")]
7536 ;; Conditional branch insns
7538 (define_expand "cbranch_cc"
7540 (if_then_else (match_operator 0 "" [(match_operand 1 "" "")
7541 (match_operand 2 "" "")])
7542 (label_ref (match_operand 3 "" ""))
7545 "operands[1] = arm_gen_compare_reg (GET_CODE (operands[0]),
7546 operands[1], operands[2], NULL_RTX);
7547 operands[2] = const0_rtx;"
7551 ;; Patterns to match conditional branch insns.
7554 (define_insn "arm_cond_branch"
7556 (if_then_else (match_operator 1 "arm_comparison_operator"
7557 [(match_operand 2 "cc_register" "") (const_int 0)])
7558 (label_ref (match_operand 0 "" ""))
7562 if (arm_ccfsm_state == 1 || arm_ccfsm_state == 2)
7564 arm_ccfsm_state += 2;
7567 return \"b%d1\\t%l0\";
7569 [(set_attr "conds" "use")
7570 (set_attr "type" "branch")
7571 (set (attr "length")
7573 (and (match_test "TARGET_THUMB2")
7574 (and (ge (minus (match_dup 0) (pc)) (const_int -250))
7575 (le (minus (match_dup 0) (pc)) (const_int 256))))
7580 (define_insn "*arm_cond_branch_reversed"
7582 (if_then_else (match_operator 1 "arm_comparison_operator"
7583 [(match_operand 2 "cc_register" "") (const_int 0)])
7585 (label_ref (match_operand 0 "" ""))))]
7588 if (arm_ccfsm_state == 1 || arm_ccfsm_state == 2)
7590 arm_ccfsm_state += 2;
7593 return \"b%D1\\t%l0\";
7595 [(set_attr "conds" "use")
7596 (set_attr "type" "branch")
7597 (set (attr "length")
7599 (and (match_test "TARGET_THUMB2")
7600 (and (ge (minus (match_dup 0) (pc)) (const_int -250))
7601 (le (minus (match_dup 0) (pc)) (const_int 256))))
7610 (define_expand "cstore_cc"
7611 [(set (match_operand:SI 0 "s_register_operand" "")
7612 (match_operator:SI 1 "" [(match_operand 2 "" "")
7613 (match_operand 3 "" "")]))]
7615 "operands[2] = arm_gen_compare_reg (GET_CODE (operands[1]),
7616 operands[2], operands[3], NULL_RTX);
7617 operands[3] = const0_rtx;"
7620 (define_insn_and_split "*mov_scc"
7621 [(set (match_operand:SI 0 "s_register_operand" "=r")
7622 (match_operator:SI 1 "arm_comparison_operator_mode"
7623 [(match_operand 2 "cc_register" "") (const_int 0)]))]
7625 "#" ; "mov%D1\\t%0, #0\;mov%d1\\t%0, #1"
7628 (if_then_else:SI (match_dup 1)
7632 [(set_attr "conds" "use")
7633 (set_attr "length" "8")
7634 (set_attr "type" "multiple")]
7637 (define_insn_and_split "*mov_negscc"
7638 [(set (match_operand:SI 0 "s_register_operand" "=r")
7639 (neg:SI (match_operator:SI 1 "arm_comparison_operator_mode"
7640 [(match_operand 2 "cc_register" "") (const_int 0)])))]
7642 "#" ; "mov%D1\\t%0, #0\;mvn%d1\\t%0, #0"
7645 (if_then_else:SI (match_dup 1)
7649 operands[3] = GEN_INT (~0);
7651 [(set_attr "conds" "use")
7652 (set_attr "length" "8")
7653 (set_attr "type" "multiple")]
7656 (define_insn_and_split "*mov_notscc"
7657 [(set (match_operand:SI 0 "s_register_operand" "=r")
7658 (not:SI (match_operator:SI 1 "arm_comparison_operator"
7659 [(match_operand 2 "cc_register" "") (const_int 0)])))]
7661 "#" ; "mvn%D1\\t%0, #0\;mvn%d1\\t%0, #1"
7664 (if_then_else:SI (match_dup 1)
7668 operands[3] = GEN_INT (~1);
7669 operands[4] = GEN_INT (~0);
7671 [(set_attr "conds" "use")
7672 (set_attr "length" "8")
7673 (set_attr "type" "multiple")]
7676 (define_expand "cstoresi4"
7677 [(set (match_operand:SI 0 "s_register_operand" "")
7678 (match_operator:SI 1 "expandable_comparison_operator"
7679 [(match_operand:SI 2 "s_register_operand" "")
7680 (match_operand:SI 3 "reg_or_int_operand" "")]))]
7681 "TARGET_32BIT || TARGET_THUMB1"
7683 rtx op3, scratch, scratch2;
7687 if (!arm_add_operand (operands[3], SImode))
7688 operands[3] = force_reg (SImode, operands[3]);
7689 emit_insn (gen_cstore_cc (operands[0], operands[1],
7690 operands[2], operands[3]));
7694 if (operands[3] == const0_rtx)
7696 switch (GET_CODE (operands[1]))
7699 emit_insn (gen_cstoresi_eq0_thumb1 (operands[0], operands[2]));
7703 emit_insn (gen_cstoresi_ne0_thumb1 (operands[0], operands[2]));
7707 scratch = expand_binop (SImode, add_optab, operands[2], constm1_rtx,
7708 NULL_RTX, 0, OPTAB_WIDEN);
7709 scratch = expand_binop (SImode, ior_optab, operands[2], scratch,
7710 NULL_RTX, 0, OPTAB_WIDEN);
7711 expand_binop (SImode, lshr_optab, scratch, GEN_INT (31),
7712 operands[0], 1, OPTAB_WIDEN);
7716 scratch = expand_unop (SImode, one_cmpl_optab, operands[2],
7718 expand_binop (SImode, lshr_optab, scratch, GEN_INT (31),
7719 NULL_RTX, 1, OPTAB_WIDEN);
7723 scratch = expand_binop (SImode, ashr_optab, operands[2],
7724 GEN_INT (31), NULL_RTX, 0, OPTAB_WIDEN);
7725 scratch = expand_binop (SImode, sub_optab, scratch, operands[2],
7726 NULL_RTX, 0, OPTAB_WIDEN);
7727 expand_binop (SImode, lshr_optab, scratch, GEN_INT (31), operands[0],
7731 /* LT is handled by generic code. No need for unsigned with 0. */
7738 switch (GET_CODE (operands[1]))
7741 scratch = expand_binop (SImode, sub_optab, operands[2], operands[3],
7742 NULL_RTX, 0, OPTAB_WIDEN);
7743 emit_insn (gen_cstoresi_eq0_thumb1 (operands[0], scratch));
7747 scratch = expand_binop (SImode, sub_optab, operands[2], operands[3],
7748 NULL_RTX, 0, OPTAB_WIDEN);
7749 emit_insn (gen_cstoresi_ne0_thumb1 (operands[0], scratch));
7753 op3 = force_reg (SImode, operands[3]);
7755 scratch = expand_binop (SImode, lshr_optab, operands[2], GEN_INT (31),
7756 NULL_RTX, 1, OPTAB_WIDEN);
7757 scratch2 = expand_binop (SImode, ashr_optab, op3, GEN_INT (31),
7758 NULL_RTX, 0, OPTAB_WIDEN);
7759 emit_insn (gen_thumb1_addsi3_addgeu (operands[0], scratch, scratch2,
7765 if (!thumb1_cmp_operand (op3, SImode))
7766 op3 = force_reg (SImode, op3);
7767 scratch = expand_binop (SImode, ashr_optab, operands[2], GEN_INT (31),
7768 NULL_RTX, 0, OPTAB_WIDEN);
7769 scratch2 = expand_binop (SImode, lshr_optab, op3, GEN_INT (31),
7770 NULL_RTX, 1, OPTAB_WIDEN);
7771 emit_insn (gen_thumb1_addsi3_addgeu (operands[0], scratch, scratch2,
7776 op3 = force_reg (SImode, operands[3]);
7777 scratch = force_reg (SImode, const0_rtx);
7778 emit_insn (gen_thumb1_addsi3_addgeu (operands[0], scratch, scratch,
7784 if (!thumb1_cmp_operand (op3, SImode))
7785 op3 = force_reg (SImode, op3);
7786 scratch = force_reg (SImode, const0_rtx);
7787 emit_insn (gen_thumb1_addsi3_addgeu (operands[0], scratch, scratch,
7793 if (!thumb1_cmp_operand (op3, SImode))
7794 op3 = force_reg (SImode, op3);
7795 scratch = gen_reg_rtx (SImode);
7796 emit_insn (gen_cstoresi_ltu_thumb1 (operands[0], operands[2], op3));
7800 op3 = force_reg (SImode, operands[3]);
7801 scratch = gen_reg_rtx (SImode);
7802 emit_insn (gen_cstoresi_ltu_thumb1 (operands[0], op3, operands[2]));
7805 /* No good sequences for GT, LT. */
7812 (define_expand "cstorehf4"
7813 [(set (match_operand:SI 0 "s_register_operand")
7814 (match_operator:SI 1 "expandable_comparison_operator"
7815 [(match_operand:HF 2 "s_register_operand")
7816 (match_operand:HF 3 "vfp_compare_operand")]))]
7817 "TARGET_VFP_FP16INST"
7819 if (!arm_validize_comparison (&operands[1],
7824 emit_insn (gen_cstore_cc (operands[0], operands[1],
7825 operands[2], operands[3]));
7830 (define_expand "cstoresf4"
7831 [(set (match_operand:SI 0 "s_register_operand" "")
7832 (match_operator:SI 1 "expandable_comparison_operator"
7833 [(match_operand:SF 2 "s_register_operand" "")
7834 (match_operand:SF 3 "vfp_compare_operand" "")]))]
7835 "TARGET_32BIT && TARGET_HARD_FLOAT"
7836 "emit_insn (gen_cstore_cc (operands[0], operands[1],
7837 operands[2], operands[3])); DONE;"
7840 (define_expand "cstoredf4"
7841 [(set (match_operand:SI 0 "s_register_operand" "")
7842 (match_operator:SI 1 "expandable_comparison_operator"
7843 [(match_operand:DF 2 "s_register_operand" "")
7844 (match_operand:DF 3 "vfp_compare_operand" "")]))]
7845 "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
7846 "emit_insn (gen_cstore_cc (operands[0], operands[1],
7847 operands[2], operands[3])); DONE;"
7850 (define_expand "cstoredi4"
7851 [(set (match_operand:SI 0 "s_register_operand" "")
7852 (match_operator:SI 1 "expandable_comparison_operator"
7853 [(match_operand:DI 2 "s_register_operand" "")
7854 (match_operand:DI 3 "cmpdi_operand" "")]))]
7857 if (!arm_validize_comparison (&operands[1],
7861 emit_insn (gen_cstore_cc (operands[0], operands[1], operands[2],
7868 ;; Conditional move insns
7870 (define_expand "movsicc"
7871 [(set (match_operand:SI 0 "s_register_operand" "")
7872 (if_then_else:SI (match_operand 1 "expandable_comparison_operator" "")
7873 (match_operand:SI 2 "arm_not_operand" "")
7874 (match_operand:SI 3 "arm_not_operand" "")))]
7881 if (!arm_validize_comparison (&operands[1], &XEXP (operands[1], 0),
7882 &XEXP (operands[1], 1)))
7885 code = GET_CODE (operands[1]);
7886 ccreg = arm_gen_compare_reg (code, XEXP (operands[1], 0),
7887 XEXP (operands[1], 1), NULL_RTX);
7888 operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
7892 (define_expand "movhfcc"
7893 [(set (match_operand:HF 0 "s_register_operand")
7894 (if_then_else:HF (match_operand 1 "arm_cond_move_operator")
7895 (match_operand:HF 2 "s_register_operand")
7896 (match_operand:HF 3 "s_register_operand")))]
7897 "TARGET_VFP_FP16INST"
7900 enum rtx_code code = GET_CODE (operands[1]);
7903 if (!arm_validize_comparison (&operands[1], &XEXP (operands[1], 0),
7904 &XEXP (operands[1], 1)))
7907 code = GET_CODE (operands[1]);
7908 ccreg = arm_gen_compare_reg (code, XEXP (operands[1], 0),
7909 XEXP (operands[1], 1), NULL_RTX);
7910 operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
7914 (define_expand "movsfcc"
7915 [(set (match_operand:SF 0 "s_register_operand" "")
7916 (if_then_else:SF (match_operand 1 "arm_cond_move_operator" "")
7917 (match_operand:SF 2 "s_register_operand" "")
7918 (match_operand:SF 3 "s_register_operand" "")))]
7919 "TARGET_32BIT && TARGET_HARD_FLOAT"
7922 enum rtx_code code = GET_CODE (operands[1]);
7925 if (!arm_validize_comparison (&operands[1], &XEXP (operands[1], 0),
7926 &XEXP (operands[1], 1)))
7929 code = GET_CODE (operands[1]);
7930 ccreg = arm_gen_compare_reg (code, XEXP (operands[1], 0),
7931 XEXP (operands[1], 1), NULL_RTX);
7932 operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
7936 (define_expand "movdfcc"
7937 [(set (match_operand:DF 0 "s_register_operand" "")
7938 (if_then_else:DF (match_operand 1 "arm_cond_move_operator" "")
7939 (match_operand:DF 2 "s_register_operand" "")
7940 (match_operand:DF 3 "s_register_operand" "")))]
7941 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
7944 enum rtx_code code = GET_CODE (operands[1]);
7947 if (!arm_validize_comparison (&operands[1], &XEXP (operands[1], 0),
7948 &XEXP (operands[1], 1)))
7950 code = GET_CODE (operands[1]);
7951 ccreg = arm_gen_compare_reg (code, XEXP (operands[1], 0),
7952 XEXP (operands[1], 1), NULL_RTX);
7953 operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
7957 (define_insn "*cmov<mode>"
7958 [(set (match_operand:SDF 0 "s_register_operand" "=<F_constraint>")
7959 (if_then_else:SDF (match_operator 1 "arm_vsel_comparison_operator"
7960 [(match_operand 2 "cc_register" "") (const_int 0)])
7961 (match_operand:SDF 3 "s_register_operand"
7963 (match_operand:SDF 4 "s_register_operand"
7964 "<F_constraint>")))]
7965 "TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>"
7968 enum arm_cond_code code = maybe_get_arm_condition_code (operands[1]);
7975 return \"vsel%d1.<V_if_elem>\\t%<V_reg>0, %<V_reg>3, %<V_reg>4\";
7980 return \"vsel%D1.<V_if_elem>\\t%<V_reg>0, %<V_reg>4, %<V_reg>3\";
7986 [(set_attr "conds" "use")
7987 (set_attr "type" "fcsel")]
7990 (define_insn "*cmovhf"
7991 [(set (match_operand:HF 0 "s_register_operand" "=t")
7992 (if_then_else:HF (match_operator 1 "arm_vsel_comparison_operator"
7993 [(match_operand 2 "cc_register" "") (const_int 0)])
7994 (match_operand:HF 3 "s_register_operand" "t")
7995 (match_operand:HF 4 "s_register_operand" "t")))]
7996 "TARGET_VFP_FP16INST"
7999 enum arm_cond_code code = maybe_get_arm_condition_code (operands[1]);
8006 return \"vsel%d1.f16\\t%0, %3, %4\";
8011 return \"vsel%D1.f16\\t%0, %4, %3\";
8017 [(set_attr "conds" "use")
8018 (set_attr "type" "fcsel")]
8021 (define_insn_and_split "*movsicc_insn"
8022 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r,r,r,r,r")
8024 (match_operator 3 "arm_comparison_operator"
8025 [(match_operand 4 "cc_register" "") (const_int 0)])
8026 (match_operand:SI 1 "arm_not_operand" "0,0,rI,K,rI,rI,K,K")
8027 (match_operand:SI 2 "arm_not_operand" "rI,K,0,0,rI,K,rI,K")))]
8038 ; alt4: mov%d3\\t%0, %1\;mov%D3\\t%0, %2
8039 ; alt5: mov%d3\\t%0, %1\;mvn%D3\\t%0, #%B2
8040 ; alt6: mvn%d3\\t%0, #%B1\;mov%D3\\t%0, %2
8041 ; alt7: mvn%d3\\t%0, #%B1\;mvn%D3\\t%0, #%B2"
8042 "&& reload_completed"
8045 enum rtx_code rev_code;
8049 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
8051 gen_rtx_SET (operands[0], operands[1])));
8053 rev_code = GET_CODE (operands[3]);
8054 mode = GET_MODE (operands[4]);
8055 if (mode == CCFPmode || mode == CCFPEmode)
8056 rev_code = reverse_condition_maybe_unordered (rev_code);
8058 rev_code = reverse_condition (rev_code);
8060 rev_cond = gen_rtx_fmt_ee (rev_code,
8064 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
8066 gen_rtx_SET (operands[0], operands[2])));
8069 [(set_attr "length" "4,4,4,4,8,8,8,8")
8070 (set_attr "conds" "use")
8071 (set_attr_alternative "type"
8072 [(if_then_else (match_operand 2 "const_int_operand" "")
8073 (const_string "mov_imm")
8074 (const_string "mov_reg"))
8075 (const_string "mvn_imm")
8076 (if_then_else (match_operand 1 "const_int_operand" "")
8077 (const_string "mov_imm")
8078 (const_string "mov_reg"))
8079 (const_string "mvn_imm")
8080 (const_string "multiple")
8081 (const_string "multiple")
8082 (const_string "multiple")
8083 (const_string "multiple")])]
8086 (define_insn "*movsfcc_soft_insn"
8087 [(set (match_operand:SF 0 "s_register_operand" "=r,r")
8088 (if_then_else:SF (match_operator 3 "arm_comparison_operator"
8089 [(match_operand 4 "cc_register" "") (const_int 0)])
8090 (match_operand:SF 1 "s_register_operand" "0,r")
8091 (match_operand:SF 2 "s_register_operand" "r,0")))]
8092 "TARGET_ARM && TARGET_SOFT_FLOAT"
8096 [(set_attr "conds" "use")
8097 (set_attr "type" "mov_reg")]
8101 ;; Jump and linkage insns
8103 (define_expand "jump"
8105 (label_ref (match_operand 0 "" "")))]
8110 (define_insn "*arm_jump"
8112 (label_ref (match_operand 0 "" "")))]
8116 if (arm_ccfsm_state == 1 || arm_ccfsm_state == 2)
8118 arm_ccfsm_state += 2;
8121 return \"b%?\\t%l0\";
8124 [(set_attr "predicable" "yes")
8125 (set (attr "length")
8127 (and (match_test "TARGET_THUMB2")
8128 (and (ge (minus (match_dup 0) (pc)) (const_int -2044))
8129 (le (minus (match_dup 0) (pc)) (const_int 2048))))
8132 (set_attr "type" "branch")]
8135 (define_expand "call"
8136 [(parallel [(call (match_operand 0 "memory_operand" "")
8137 (match_operand 1 "general_operand" ""))
8138 (use (match_operand 2 "" ""))
8139 (clobber (reg:SI LR_REGNUM))])]
8144 tree addr = MEM_EXPR (operands[0]);
8146 /* In an untyped call, we can get NULL for operand 2. */
8147 if (operands[2] == NULL_RTX)
8148 operands[2] = const0_rtx;
8150 /* Decide if we should generate indirect calls by loading the
8151 32-bit address of the callee into a register before performing the
8153 callee = XEXP (operands[0], 0);
8154 if (GET_CODE (callee) == SYMBOL_REF
8155 ? arm_is_long_call_p (SYMBOL_REF_DECL (callee))
8157 XEXP (operands[0], 0) = force_reg (Pmode, callee);
8159 if (detect_cmse_nonsecure_call (addr))
8161 pat = gen_nonsecure_call_internal (operands[0], operands[1],
8163 emit_call_insn (pat);
8167 pat = gen_call_internal (operands[0], operands[1], operands[2]);
8168 arm_emit_call_insn (pat, XEXP (operands[0], 0), false);
8174 (define_expand "call_internal"
8175 [(parallel [(call (match_operand 0 "memory_operand" "")
8176 (match_operand 1 "general_operand" ""))
8177 (use (match_operand 2 "" ""))
8178 (clobber (reg:SI LR_REGNUM))])])
8180 (define_expand "nonsecure_call_internal"
8181 [(parallel [(call (unspec:SI [(match_operand 0 "memory_operand" "")]
8182 UNSPEC_NONSECURE_MEM)
8183 (match_operand 1 "general_operand" ""))
8184 (use (match_operand 2 "" ""))
8185 (clobber (reg:SI LR_REGNUM))])]
8190 tmp = copy_to_suggested_reg (XEXP (operands[0], 0),
8191 gen_rtx_REG (SImode, R4_REGNUM),
8194 operands[0] = replace_equiv_address (operands[0], tmp);
8197 (define_insn "*call_reg_armv5"
8198 [(call (mem:SI (match_operand:SI 0 "s_register_operand" "r"))
8199 (match_operand 1 "" ""))
8200 (use (match_operand 2 "" ""))
8201 (clobber (reg:SI LR_REGNUM))]
8202 "TARGET_ARM && arm_arch5t && !SIBLING_CALL_P (insn)"
8204 [(set_attr "type" "call")]
8207 (define_insn "*call_reg_arm"
8208 [(call (mem:SI (match_operand:SI 0 "s_register_operand" "r"))
8209 (match_operand 1 "" ""))
8210 (use (match_operand 2 "" ""))
8211 (clobber (reg:SI LR_REGNUM))]
8212 "TARGET_ARM && !arm_arch5t && !SIBLING_CALL_P (insn)"
8214 return output_call (operands);
8216 ;; length is worst case, normally it is only two
8217 [(set_attr "length" "12")
8218 (set_attr "type" "call")]
8222 (define_expand "call_value"
8223 [(parallel [(set (match_operand 0 "" "")
8224 (call (match_operand 1 "memory_operand" "")
8225 (match_operand 2 "general_operand" "")))
8226 (use (match_operand 3 "" ""))
8227 (clobber (reg:SI LR_REGNUM))])]
8232 tree addr = MEM_EXPR (operands[1]);
8234 /* In an untyped call, we can get NULL for operand 2. */
8235 if (operands[3] == 0)
8236 operands[3] = const0_rtx;
8238 /* Decide if we should generate indirect calls by loading the
8239 32-bit address of the callee into a register before performing the
8241 callee = XEXP (operands[1], 0);
8242 if (GET_CODE (callee) == SYMBOL_REF
8243 ? arm_is_long_call_p (SYMBOL_REF_DECL (callee))
8245 XEXP (operands[1], 0) = force_reg (Pmode, callee);
8247 if (detect_cmse_nonsecure_call (addr))
8249 pat = gen_nonsecure_call_value_internal (operands[0], operands[1],
8250 operands[2], operands[3]);
8251 emit_call_insn (pat);
8255 pat = gen_call_value_internal (operands[0], operands[1],
8256 operands[2], operands[3]);
8257 arm_emit_call_insn (pat, XEXP (operands[1], 0), false);
8263 (define_expand "call_value_internal"
8264 [(parallel [(set (match_operand 0 "" "")
8265 (call (match_operand 1 "memory_operand" "")
8266 (match_operand 2 "general_operand" "")))
8267 (use (match_operand 3 "" ""))
8268 (clobber (reg:SI LR_REGNUM))])])
8270 (define_expand "nonsecure_call_value_internal"
8271 [(parallel [(set (match_operand 0 "" "")
8272 (call (unspec:SI [(match_operand 1 "memory_operand" "")]
8273 UNSPEC_NONSECURE_MEM)
8274 (match_operand 2 "general_operand" "")))
8275 (use (match_operand 3 "" ""))
8276 (clobber (reg:SI LR_REGNUM))])]
8281 tmp = copy_to_suggested_reg (XEXP (operands[1], 0),
8282 gen_rtx_REG (SImode, R4_REGNUM),
8285 operands[1] = replace_equiv_address (operands[1], tmp);
8288 (define_insn "*call_value_reg_armv5"
8289 [(set (match_operand 0 "" "")
8290 (call (mem:SI (match_operand:SI 1 "s_register_operand" "r"))
8291 (match_operand 2 "" "")))
8292 (use (match_operand 3 "" ""))
8293 (clobber (reg:SI LR_REGNUM))]
8294 "TARGET_ARM && arm_arch5t && !SIBLING_CALL_P (insn)"
8296 [(set_attr "type" "call")]
8299 (define_insn "*call_value_reg_arm"
8300 [(set (match_operand 0 "" "")
8301 (call (mem:SI (match_operand:SI 1 "s_register_operand" "r"))
8302 (match_operand 2 "" "")))
8303 (use (match_operand 3 "" ""))
8304 (clobber (reg:SI LR_REGNUM))]
8305 "TARGET_ARM && !arm_arch5t && !SIBLING_CALL_P (insn)"
8307 return output_call (&operands[1]);
8309 [(set_attr "length" "12")
8310 (set_attr "type" "call")]
8313 ;; Allow calls to SYMBOL_REFs specially as they are not valid general addresses
8314 ;; The 'a' causes the operand to be treated as an address, i.e. no '#' output.
8316 (define_insn "*call_symbol"
8317 [(call (mem:SI (match_operand:SI 0 "" ""))
8318 (match_operand 1 "" ""))
8319 (use (match_operand 2 "" ""))
8320 (clobber (reg:SI LR_REGNUM))]
8322 && !SIBLING_CALL_P (insn)
8323 && (GET_CODE (operands[0]) == SYMBOL_REF)
8324 && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[0]))"
8327 rtx op = operands[0];
8329 /* Switch mode now when possible. */
8330 if (SYMBOL_REF_DECL (op) && !TREE_PUBLIC (SYMBOL_REF_DECL (op))
8331 && arm_arch5t && arm_change_mode_p (SYMBOL_REF_DECL (op)))
8332 return NEED_PLT_RELOC ? \"blx%?\\t%a0(PLT)\" : \"blx%?\\t(%a0)\";
8334 return NEED_PLT_RELOC ? \"bl%?\\t%a0(PLT)\" : \"bl%?\\t%a0\";
8336 [(set_attr "type" "call")]
8339 (define_insn "*call_value_symbol"
8340 [(set (match_operand 0 "" "")
8341 (call (mem:SI (match_operand:SI 1 "" ""))
8342 (match_operand:SI 2 "" "")))
8343 (use (match_operand 3 "" ""))
8344 (clobber (reg:SI LR_REGNUM))]
8346 && !SIBLING_CALL_P (insn)
8347 && (GET_CODE (operands[1]) == SYMBOL_REF)
8348 && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[1]))"
8351 rtx op = operands[1];
8353 /* Switch mode now when possible. */
8354 if (SYMBOL_REF_DECL (op) && !TREE_PUBLIC (SYMBOL_REF_DECL (op))
8355 && arm_arch5t && arm_change_mode_p (SYMBOL_REF_DECL (op)))
8356 return NEED_PLT_RELOC ? \"blx%?\\t%a1(PLT)\" : \"blx%?\\t(%a1)\";
8358 return NEED_PLT_RELOC ? \"bl%?\\t%a1(PLT)\" : \"bl%?\\t%a1\";
8360 [(set_attr "type" "call")]
8363 (define_expand "sibcall_internal"
8364 [(parallel [(call (match_operand 0 "memory_operand" "")
8365 (match_operand 1 "general_operand" ""))
8367 (use (match_operand 2 "" ""))])])
8369 ;; We may also be able to do sibcalls for Thumb, but it's much harder...
8370 (define_expand "sibcall"
8371 [(parallel [(call (match_operand 0 "memory_operand" "")
8372 (match_operand 1 "general_operand" ""))
8374 (use (match_operand 2 "" ""))])]
8380 if ((!REG_P (XEXP (operands[0], 0))
8381 && GET_CODE (XEXP (operands[0], 0)) != SYMBOL_REF)
8382 || (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
8383 && arm_is_long_call_p (SYMBOL_REF_DECL (XEXP (operands[0], 0)))))
8384 XEXP (operands[0], 0) = force_reg (SImode, XEXP (operands[0], 0));
8386 if (operands[2] == NULL_RTX)
8387 operands[2] = const0_rtx;
8389 pat = gen_sibcall_internal (operands[0], operands[1], operands[2]);
8390 arm_emit_call_insn (pat, operands[0], true);
8395 (define_expand "sibcall_value_internal"
8396 [(parallel [(set (match_operand 0 "" "")
8397 (call (match_operand 1 "memory_operand" "")
8398 (match_operand 2 "general_operand" "")))
8400 (use (match_operand 3 "" ""))])])
8402 (define_expand "sibcall_value"
8403 [(parallel [(set (match_operand 0 "" "")
8404 (call (match_operand 1 "memory_operand" "")
8405 (match_operand 2 "general_operand" "")))
8407 (use (match_operand 3 "" ""))])]
8413 if ((!REG_P (XEXP (operands[1], 0))
8414 && GET_CODE (XEXP (operands[1], 0)) != SYMBOL_REF)
8415 || (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
8416 && arm_is_long_call_p (SYMBOL_REF_DECL (XEXP (operands[1], 0)))))
8417 XEXP (operands[1], 0) = force_reg (SImode, XEXP (operands[1], 0));
8419 if (operands[3] == NULL_RTX)
8420 operands[3] = const0_rtx;
8422 pat = gen_sibcall_value_internal (operands[0], operands[1],
8423 operands[2], operands[3]);
8424 arm_emit_call_insn (pat, operands[1], true);
8429 (define_insn "*sibcall_insn"
8430 [(call (mem:SI (match_operand:SI 0 "call_insn_operand" "Cs, US"))
8431 (match_operand 1 "" ""))
8433 (use (match_operand 2 "" ""))]
8434 "TARGET_32BIT && SIBLING_CALL_P (insn)"
8436 if (which_alternative == 1)
8437 return NEED_PLT_RELOC ? \"b%?\\t%a0(PLT)\" : \"b%?\\t%a0\";
8440 if (arm_arch5t || arm_arch4t)
8441 return \"bx%?\\t%0\\t%@ indirect register sibling call\";
8443 return \"mov%?\\t%|pc, %0\\t%@ indirect register sibling call\";
8446 [(set_attr "type" "call")]
8449 (define_insn "*sibcall_value_insn"
8450 [(set (match_operand 0 "" "")
8451 (call (mem:SI (match_operand:SI 1 "call_insn_operand" "Cs,US"))
8452 (match_operand 2 "" "")))
8454 (use (match_operand 3 "" ""))]
8455 "TARGET_32BIT && SIBLING_CALL_P (insn)"
8457 if (which_alternative == 1)
8458 return NEED_PLT_RELOC ? \"b%?\\t%a1(PLT)\" : \"b%?\\t%a1\";
8461 if (arm_arch5t || arm_arch4t)
8462 return \"bx%?\\t%1\";
8464 return \"mov%?\\t%|pc, %1\\t@ indirect sibling call \";
8467 [(set_attr "type" "call")]
8470 (define_expand "<return_str>return"
8472 "(TARGET_ARM || (TARGET_THUMB2
8473 && ARM_FUNC_TYPE (arm_current_func_type ()) == ARM_FT_NORMAL
8474 && !IS_STACKALIGN (arm_current_func_type ())))
8475 <return_cond_false>"
8480 thumb2_expand_return (<return_simple_p>);
8487 ;; Often the return insn will be the same as loading from memory, so set attr
8488 (define_insn "*arm_return"
8490 "TARGET_ARM && USE_RETURN_INSN (FALSE)"
8493 if (arm_ccfsm_state == 2)
8495 arm_ccfsm_state += 2;
8498 return output_return_instruction (const_true_rtx, true, false, false);
8500 [(set_attr "type" "load_4")
8501 (set_attr "length" "12")
8502 (set_attr "predicable" "yes")]
8505 (define_insn "*cond_<return_str>return"
8507 (if_then_else (match_operator 0 "arm_comparison_operator"
8508 [(match_operand 1 "cc_register" "") (const_int 0)])
8511 "TARGET_ARM <return_cond_true>"
8514 if (arm_ccfsm_state == 2)
8516 arm_ccfsm_state += 2;
8519 return output_return_instruction (operands[0], true, false,
8522 [(set_attr "conds" "use")
8523 (set_attr "length" "12")
8524 (set_attr "type" "load_4")]
8527 (define_insn "*cond_<return_str>return_inverted"
8529 (if_then_else (match_operator 0 "arm_comparison_operator"
8530 [(match_operand 1 "cc_register" "") (const_int 0)])
8533 "TARGET_ARM <return_cond_true>"
8536 if (arm_ccfsm_state == 2)
8538 arm_ccfsm_state += 2;
8541 return output_return_instruction (operands[0], true, true,
8544 [(set_attr "conds" "use")
8545 (set_attr "length" "12")
8546 (set_attr "type" "load_4")]
8549 (define_insn "*arm_simple_return"
8554 if (arm_ccfsm_state == 2)
8556 arm_ccfsm_state += 2;
8559 return output_return_instruction (const_true_rtx, true, false, true);
8561 [(set_attr "type" "branch")
8562 (set_attr "length" "4")
8563 (set_attr "predicable" "yes")]
8566 ;; Generate a sequence of instructions to determine if the processor is
8567 ;; in 26-bit or 32-bit mode, and return the appropriate return address
8570 (define_expand "return_addr_mask"
8572 (compare:CC_NOOV (unspec [(const_int 0)] UNSPEC_CHECK_ARCH)
8574 (set (match_operand:SI 0 "s_register_operand" "")
8575 (if_then_else:SI (eq (match_dup 1) (const_int 0))
8577 (const_int 67108860)))] ; 0x03fffffc
8580 operands[1] = gen_rtx_REG (CC_NOOVmode, CC_REGNUM);
8583 (define_insn "*check_arch2"
8584 [(set (match_operand:CC_NOOV 0 "cc_register" "")
8585 (compare:CC_NOOV (unspec [(const_int 0)] UNSPEC_CHECK_ARCH)
8588 "teq\\t%|r0, %|r0\;teq\\t%|pc, %|pc"
8589 [(set_attr "length" "8")
8590 (set_attr "conds" "set")
8591 (set_attr "type" "multiple")]
8594 ;; Call subroutine returning any type.
8596 (define_expand "untyped_call"
8597 [(parallel [(call (match_operand 0 "" "")
8599 (match_operand 1 "" "")
8600 (match_operand 2 "" "")])]
8605 rtx par = gen_rtx_PARALLEL (VOIDmode,
8606 rtvec_alloc (XVECLEN (operands[2], 0)));
8607 rtx addr = gen_reg_rtx (Pmode);
8611 emit_move_insn (addr, XEXP (operands[1], 0));
8612 mem = change_address (operands[1], BLKmode, addr);
8614 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8616 rtx src = SET_SRC (XVECEXP (operands[2], 0, i));
8618 /* Default code only uses r0 as a return value, but we could
8619 be using anything up to 4 registers. */
8620 if (REGNO (src) == R0_REGNUM)
8621 src = gen_rtx_REG (TImode, R0_REGNUM);
8623 XVECEXP (par, 0, i) = gen_rtx_EXPR_LIST (VOIDmode, src,
8625 size += GET_MODE_SIZE (GET_MODE (src));
8628 emit_call_insn (gen_call_value (par, operands[0], const0_rtx, NULL));
8632 for (i = 0; i < XVECLEN (par, 0); i++)
8634 HOST_WIDE_INT offset = 0;
8635 rtx reg = XEXP (XVECEXP (par, 0, i), 0);
8638 emit_move_insn (addr, plus_constant (Pmode, addr, size));
8640 mem = change_address (mem, GET_MODE (reg), NULL);
8641 if (REGNO (reg) == R0_REGNUM)
8643 /* On thumb we have to use a write-back instruction. */
8644 emit_insn (arm_gen_store_multiple (arm_regs_in_sequence, 4, addr,
8645 TARGET_THUMB ? TRUE : FALSE, mem, &offset));
8646 size = TARGET_ARM ? 16 : 0;
8650 emit_move_insn (mem, reg);
8651 size = GET_MODE_SIZE (GET_MODE (reg));
8655 /* The optimizer does not know that the call sets the function value
8656 registers we stored in the result block. We avoid problems by
8657 claiming that all hard registers are used and clobbered at this
8659 emit_insn (gen_blockage ());
8665 (define_expand "untyped_return"
8666 [(match_operand:BLK 0 "memory_operand" "")
8667 (match_operand 1 "" "")]
8672 rtx addr = gen_reg_rtx (Pmode);
8676 emit_move_insn (addr, XEXP (operands[0], 0));
8677 mem = change_address (operands[0], BLKmode, addr);
8679 for (i = 0; i < XVECLEN (operands[1], 0); i++)
8681 HOST_WIDE_INT offset = 0;
8682 rtx reg = SET_DEST (XVECEXP (operands[1], 0, i));
8685 emit_move_insn (addr, plus_constant (Pmode, addr, size));
8687 mem = change_address (mem, GET_MODE (reg), NULL);
8688 if (REGNO (reg) == R0_REGNUM)
8690 /* On thumb we have to use a write-back instruction. */
8691 emit_insn (arm_gen_load_multiple (arm_regs_in_sequence, 4, addr,
8692 TARGET_THUMB ? TRUE : FALSE, mem, &offset));
8693 size = TARGET_ARM ? 16 : 0;
8697 emit_move_insn (reg, mem);
8698 size = GET_MODE_SIZE (GET_MODE (reg));
8702 /* Emit USE insns before the return. */
8703 for (i = 0; i < XVECLEN (operands[1], 0); i++)
8704 emit_use (SET_DEST (XVECEXP (operands[1], 0, i)));
8706 /* Construct the return. */
8707 expand_naked_return ();
8713 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
8714 ;; all of memory. This blocks insns from being moved across this point.
8716 (define_insn "blockage"
8717 [(unspec_volatile [(const_int 0)] VUNSPEC_BLOCKAGE)]
8720 [(set_attr "length" "0")
8721 (set_attr "type" "block")]
8724 ;; Since we hard code r0 here use the 'o' constraint to prevent
8725 ;; provoking undefined behaviour in the hardware with putting out
8726 ;; auto-increment operations with potentially r0 as the base register.
8727 (define_insn "probe_stack"
8728 [(set (match_operand:SI 0 "memory_operand" "=o")
8729 (unspec:SI [(const_int 0)] UNSPEC_PROBE_STACK))]
8732 [(set_attr "type" "store_4")
8733 (set_attr "predicable" "yes")]
8736 (define_insn "probe_stack_range"
8737 [(set (match_operand:SI 0 "register_operand" "=r")
8738 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "0")
8739 (match_operand:SI 2 "register_operand" "r")]
8740 VUNSPEC_PROBE_STACK_RANGE))]
8743 return output_probe_stack_range (operands[0], operands[2]);
8745 [(set_attr "type" "multiple")
8746 (set_attr "conds" "clob")]
8749 ;; Named patterns for stack smashing protection.
8750 (define_expand "stack_protect_combined_set"
8752 [(set (match_operand:SI 0 "memory_operand" "")
8753 (unspec:SI [(match_operand:SI 1 "guard_operand" "")]
8755 (clobber (match_scratch:SI 2 ""))
8756 (clobber (match_scratch:SI 3 ""))])]
8761 ;; Use a separate insn from the above expand to be able to have the mem outside
8762 ;; the operand #1 when register allocation comes. This is needed to avoid LRA
8763 ;; try to reload the guard since we need to control how PIC access is done in
8764 ;; the -fpic/-fPIC case (see COMPUTE_NOW parameter when calling
8765 ;; legitimize_pic_address ()).
8766 (define_insn_and_split "*stack_protect_combined_set_insn"
8767 [(set (match_operand:SI 0 "memory_operand" "=m,m")
8768 (unspec:SI [(mem:SI (match_operand:SI 1 "guard_addr_operand" "X,X"))]
8770 (clobber (match_scratch:SI 2 "=&l,&r"))
8771 (clobber (match_scratch:SI 3 "=&l,&r"))]
8775 [(parallel [(set (match_dup 0) (unspec:SI [(mem:SI (match_dup 2))]
8777 (clobber (match_dup 2))])]
8782 /* Forces recomputing of GOT base now. */
8783 legitimize_pic_address (operands[1], SImode, operands[2], operands[3],
8784 true /*compute_now*/);
8788 if (address_operand (operands[1], SImode))
8789 operands[2] = operands[1];
8792 rtx mem = XEXP (force_const_mem (SImode, operands[1]), 0);
8793 emit_move_insn (operands[2], mem);
8797 [(set_attr "arch" "t1,32")]
8800 (define_insn "*stack_protect_set_insn"
8801 [(set (match_operand:SI 0 "memory_operand" "=m,m")
8802 (unspec:SI [(mem:SI (match_operand:SI 1 "register_operand" "+&l,&r"))]
8804 (clobber (match_dup 1))]
8807 ldr\\t%1, [%1]\;str\\t%1, %0\;movs\t%1,#0
8808 ldr\\t%1, [%1]\;str\\t%1, %0\;mov\t%1,#0"
8809 [(set_attr "length" "8,12")
8810 (set_attr "conds" "clob,nocond")
8811 (set_attr "type" "multiple")
8812 (set_attr "arch" "t1,32")]
8815 (define_expand "stack_protect_combined_test"
8819 (eq (match_operand:SI 0 "memory_operand" "")
8820 (unspec:SI [(match_operand:SI 1 "guard_operand" "")]
8822 (label_ref (match_operand 2))
8824 (clobber (match_scratch:SI 3 ""))
8825 (clobber (match_scratch:SI 4 ""))
8826 (clobber (reg:CC CC_REGNUM))])]
8831 ;; Use a separate insn from the above expand to be able to have the mem outside
8832 ;; the operand #1 when register allocation comes. This is needed to avoid LRA
8833 ;; try to reload the guard since we need to control how PIC access is done in
8834 ;; the -fpic/-fPIC case (see COMPUTE_NOW parameter when calling
8835 ;; legitimize_pic_address ()).
8836 (define_insn_and_split "*stack_protect_combined_test_insn"
8839 (eq (match_operand:SI 0 "memory_operand" "m,m")
8840 (unspec:SI [(mem:SI (match_operand:SI 1 "guard_addr_operand" "X,X"))]
8842 (label_ref (match_operand 2))
8844 (clobber (match_scratch:SI 3 "=&l,&r"))
8845 (clobber (match_scratch:SI 4 "=&l,&r"))
8846 (clobber (reg:CC CC_REGNUM))]
8856 /* Forces recomputing of GOT base now. */
8857 legitimize_pic_address (operands[1], SImode, operands[3], operands[4],
8858 true /*compute_now*/);
8862 if (address_operand (operands[1], SImode))
8863 operands[3] = operands[1];
8866 rtx mem = XEXP (force_const_mem (SImode, operands[1]), 0);
8867 emit_move_insn (operands[3], mem);
8872 emit_insn (gen_arm_stack_protect_test_insn (operands[4], operands[0],
8874 rtx cc_reg = gen_rtx_REG (CC_Zmode, CC_REGNUM);
8875 eq = gen_rtx_EQ (CC_Zmode, cc_reg, const0_rtx);
8876 emit_jump_insn (gen_arm_cond_branch (operands[2], eq, cc_reg));
8880 emit_insn (gen_thumb1_stack_protect_test_insn (operands[4], operands[0],
8882 eq = gen_rtx_EQ (VOIDmode, operands[4], const0_rtx);
8883 emit_jump_insn (gen_cbranchsi4 (eq, operands[4], const0_rtx,
8888 [(set_attr "arch" "t1,32")]
8891 (define_insn "arm_stack_protect_test_insn"
8892 [(set (reg:CC_Z CC_REGNUM)
8893 (compare:CC_Z (unspec:SI [(match_operand:SI 1 "memory_operand" "m,m")
8894 (mem:SI (match_operand:SI 2 "register_operand" "+l,r"))]
8897 (clobber (match_operand:SI 0 "register_operand" "=&l,&r"))
8898 (clobber (match_dup 2))]
8900 "ldr\t%0, [%2]\;ldr\t%2, %1\;eors\t%0, %2, %0"
8901 [(set_attr "length" "8,12")
8902 (set_attr "conds" "set")
8903 (set_attr "type" "multiple")
8904 (set_attr "arch" "t,32")]
8907 (define_expand "casesi"
8908 [(match_operand:SI 0 "s_register_operand" "") ; index to jump on
8909 (match_operand:SI 1 "const_int_operand" "") ; lower bound
8910 (match_operand:SI 2 "const_int_operand" "") ; total range
8911 (match_operand:SI 3 "" "") ; table label
8912 (match_operand:SI 4 "" "")] ; Out of range label
8913 "(TARGET_32BIT || optimize_size || flag_pic) && !target_pure_code"
8916 enum insn_code code;
8917 if (operands[1] != const0_rtx)
8919 rtx reg = gen_reg_rtx (SImode);
8921 emit_insn (gen_addsi3 (reg, operands[0],
8922 gen_int_mode (-INTVAL (operands[1]),
8928 code = CODE_FOR_arm_casesi_internal;
8929 else if (TARGET_THUMB1)
8930 code = CODE_FOR_thumb1_casesi_internal_pic;
8932 code = CODE_FOR_thumb2_casesi_internal_pic;
8934 code = CODE_FOR_thumb2_casesi_internal;
8936 if (!insn_data[(int) code].operand[1].predicate(operands[2], SImode))
8937 operands[2] = force_reg (SImode, operands[2]);
8939 emit_jump_insn (GEN_FCN ((int) code) (operands[0], operands[2],
8940 operands[3], operands[4]));
8945 ;; The USE in this pattern is needed to tell flow analysis that this is
8946 ;; a CASESI insn. It has no other purpose.
8947 (define_expand "arm_casesi_internal"
8948 [(parallel [(set (pc)
8950 (leu (match_operand:SI 0 "s_register_operand")
8951 (match_operand:SI 1 "arm_rhs_operand"))
8953 (label_ref:SI (match_operand 3 ""))))
8954 (clobber (reg:CC CC_REGNUM))
8955 (use (label_ref:SI (match_operand 2 "")))])]
8958 operands[4] = gen_rtx_MULT (SImode, operands[0], GEN_INT (4));
8959 operands[4] = gen_rtx_PLUS (SImode, operands[4],
8960 gen_rtx_LABEL_REF (SImode, operands[2]));
8961 operands[4] = gen_rtx_MEM (SImode, operands[4]);
8962 MEM_READONLY_P (operands[4]) = 1;
8963 MEM_NOTRAP_P (operands[4]) = 1;
8966 (define_insn "*arm_casesi_internal"
8967 [(parallel [(set (pc)
8969 (leu (match_operand:SI 0 "s_register_operand" "r")
8970 (match_operand:SI 1 "arm_rhs_operand" "rI"))
8971 (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
8972 (label_ref:SI (match_operand 2 "" ""))))
8973 (label_ref:SI (match_operand 3 "" ""))))
8974 (clobber (reg:CC CC_REGNUM))
8975 (use (label_ref:SI (match_dup 2)))])]
8979 return \"cmp\\t%0, %1\;addls\\t%|pc, %|pc, %0, asl #2\;b\\t%l3\";
8980 return \"cmp\\t%0, %1\;ldrls\\t%|pc, [%|pc, %0, asl #2]\;b\\t%l3\";
8982 [(set_attr "conds" "clob")
8983 (set_attr "length" "12")
8984 (set_attr "type" "multiple")]
8987 (define_expand "indirect_jump"
8989 (match_operand:SI 0 "s_register_operand" ""))]
8992 /* Thumb-2 doesn't have mov pc, reg. Explicitly set the low bit of the
8993 address and use bx. */
8997 tmp = gen_reg_rtx (SImode);
8998 emit_insn (gen_iorsi3 (tmp, operands[0], GEN_INT(1)));
9004 ;; NB Never uses BX.
9005 (define_insn "*arm_indirect_jump"
9007 (match_operand:SI 0 "s_register_operand" "r"))]
9009 "mov%?\\t%|pc, %0\\t%@ indirect register jump"
9010 [(set_attr "predicable" "yes")
9011 (set_attr "type" "branch")]
9014 (define_insn "*load_indirect_jump"
9016 (match_operand:SI 0 "memory_operand" "m"))]
9018 "ldr%?\\t%|pc, %0\\t%@ indirect memory jump"
9019 [(set_attr "type" "load_4")
9020 (set_attr "pool_range" "4096")
9021 (set_attr "neg_pool_range" "4084")
9022 (set_attr "predicable" "yes")]
9032 [(set (attr "length")
9033 (if_then_else (eq_attr "is_thumb" "yes")
9036 (set_attr "type" "mov_reg")]
9040 [(trap_if (const_int 1) (const_int 0))]
9044 return \".inst\\t0xe7f000f0\";
9046 return \".inst\\t0xdeff\";
9048 [(set (attr "length")
9049 (if_then_else (eq_attr "is_thumb" "yes")
9052 (set_attr "type" "trap")
9053 (set_attr "conds" "unconditional")]
9057 ;; Patterns to allow combination of arithmetic, cond code and shifts
9059 (define_insn "*<arith_shift_insn>_multsi"
9060 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
9062 (mult:SI (match_operand:SI 2 "s_register_operand" "r,r")
9063 (match_operand:SI 3 "power_of_two_operand" ""))
9064 (match_operand:SI 1 "s_register_operand" "rk,<t2_binop0>")))]
9066 "<arith_shift_insn>%?\\t%0, %1, %2, lsl %b3"
9067 [(set_attr "predicable" "yes")
9068 (set_attr "shift" "2")
9069 (set_attr "arch" "a,t2")
9070 (set_attr "type" "alu_shift_imm")])
9072 (define_insn "*<arith_shift_insn>_shiftsi"
9073 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
9075 (match_operator:SI 2 "shift_nomul_operator"
9076 [(match_operand:SI 3 "s_register_operand" "r,r,r")
9077 (match_operand:SI 4 "shift_amount_operand" "M,M,r")])
9078 (match_operand:SI 1 "s_register_operand" "rk,<t2_binop0>,rk")))]
9079 "TARGET_32BIT && GET_CODE (operands[2]) != MULT"
9080 "<arith_shift_insn>%?\\t%0, %1, %3%S2"
9081 [(set_attr "predicable" "yes")
9082 (set_attr "shift" "3")
9083 (set_attr "arch" "a,t2,a")
9084 (set_attr "type" "alu_shift_imm,alu_shift_imm,alu_shift_reg")])
9087 [(set (match_operand:SI 0 "s_register_operand" "")
9088 (match_operator:SI 1 "shiftable_operator"
9089 [(match_operator:SI 2 "shiftable_operator"
9090 [(match_operator:SI 3 "shift_operator"
9091 [(match_operand:SI 4 "s_register_operand" "")
9092 (match_operand:SI 5 "reg_or_int_operand" "")])
9093 (match_operand:SI 6 "s_register_operand" "")])
9094 (match_operand:SI 7 "arm_rhs_operand" "")]))
9095 (clobber (match_operand:SI 8 "s_register_operand" ""))]
9098 (match_op_dup 2 [(match_op_dup 3 [(match_dup 4) (match_dup 5)])
9101 (match_op_dup 1 [(match_dup 8) (match_dup 7)]))]
9104 (define_insn "*arith_shiftsi_compare0"
9105 [(set (reg:CC_NOOV CC_REGNUM)
9107 (match_operator:SI 1 "shiftable_operator"
9108 [(match_operator:SI 3 "shift_operator"
9109 [(match_operand:SI 4 "s_register_operand" "r,r")
9110 (match_operand:SI 5 "shift_amount_operand" "M,r")])
9111 (match_operand:SI 2 "s_register_operand" "r,r")])
9113 (set (match_operand:SI 0 "s_register_operand" "=r,r")
9114 (match_op_dup 1 [(match_op_dup 3 [(match_dup 4) (match_dup 5)])
9117 "%i1s%?\\t%0, %2, %4%S3"
9118 [(set_attr "conds" "set")
9119 (set_attr "shift" "4")
9120 (set_attr "arch" "32,a")
9121 (set_attr "type" "alus_shift_imm,alus_shift_reg")])
9123 (define_insn "*arith_shiftsi_compare0_scratch"
9124 [(set (reg:CC_NOOV CC_REGNUM)
9126 (match_operator:SI 1 "shiftable_operator"
9127 [(match_operator:SI 3 "shift_operator"
9128 [(match_operand:SI 4 "s_register_operand" "r,r")
9129 (match_operand:SI 5 "shift_amount_operand" "M,r")])
9130 (match_operand:SI 2 "s_register_operand" "r,r")])
9132 (clobber (match_scratch:SI 0 "=r,r"))]
9134 "%i1s%?\\t%0, %2, %4%S3"
9135 [(set_attr "conds" "set")
9136 (set_attr "shift" "4")
9137 (set_attr "arch" "32,a")
9138 (set_attr "type" "alus_shift_imm,alus_shift_reg")])
9140 (define_insn "*sub_shiftsi"
9141 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
9142 (minus:SI (match_operand:SI 1 "s_register_operand" "r,r")
9143 (match_operator:SI 2 "shift_operator"
9144 [(match_operand:SI 3 "s_register_operand" "r,r")
9145 (match_operand:SI 4 "shift_amount_operand" "M,r")])))]
9147 "sub%?\\t%0, %1, %3%S2"
9148 [(set_attr "predicable" "yes")
9149 (set_attr "predicable_short_it" "no")
9150 (set_attr "shift" "3")
9151 (set_attr "arch" "32,a")
9152 (set_attr "type" "alus_shift_imm,alus_shift_reg")])
9154 (define_insn "*sub_shiftsi_compare0"
9155 [(set (reg:CC_NOOV CC_REGNUM)
9157 (minus:SI (match_operand:SI 1 "s_register_operand" "r,r,r")
9158 (match_operator:SI 2 "shift_operator"
9159 [(match_operand:SI 3 "s_register_operand" "r,r,r")
9160 (match_operand:SI 4 "shift_amount_operand" "M,r,M")]))
9162 (set (match_operand:SI 0 "s_register_operand" "=r,r,r")
9163 (minus:SI (match_dup 1)
9164 (match_op_dup 2 [(match_dup 3) (match_dup 4)])))]
9166 "subs%?\\t%0, %1, %3%S2"
9167 [(set_attr "conds" "set")
9168 (set_attr "shift" "3")
9169 (set_attr "arch" "32,a,a")
9170 (set_attr "type" "alus_shift_imm,alus_shift_reg,alus_shift_imm")])
9172 (define_insn "*sub_shiftsi_compare0_scratch"
9173 [(set (reg:CC_NOOV CC_REGNUM)
9175 (minus:SI (match_operand:SI 1 "s_register_operand" "r,r,r")
9176 (match_operator:SI 2 "shift_operator"
9177 [(match_operand:SI 3 "s_register_operand" "r,r,r")
9178 (match_operand:SI 4 "shift_amount_operand" "M,r,M")]))
9180 (clobber (match_scratch:SI 0 "=r,r,r"))]
9182 "subs%?\\t%0, %1, %3%S2"
9183 [(set_attr "conds" "set")
9184 (set_attr "shift" "3")
9185 (set_attr "arch" "32,a,a")
9186 (set_attr "type" "alus_shift_imm,alus_shift_reg,alus_shift_imm")])
9189 (define_insn_and_split "*and_scc"
9190 [(set (match_operand:SI 0 "s_register_operand" "=r")
9191 (and:SI (match_operator:SI 1 "arm_comparison_operator"
9192 [(match_operand 2 "cc_register" "") (const_int 0)])
9193 (match_operand:SI 3 "s_register_operand" "r")))]
9195 "#" ; "mov%D1\\t%0, #0\;and%d1\\t%0, %3, #1"
9196 "&& reload_completed"
9197 [(cond_exec (match_dup 5) (set (match_dup 0) (const_int 0)))
9198 (cond_exec (match_dup 4) (set (match_dup 0)
9199 (and:SI (match_dup 3) (const_int 1))))]
9201 machine_mode mode = GET_MODE (operands[2]);
9202 enum rtx_code rc = GET_CODE (operands[1]);
9204 /* Note that operands[4] is the same as operands[1],
9205 but with VOIDmode as the result. */
9206 operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
9207 if (mode == CCFPmode || mode == CCFPEmode)
9208 rc = reverse_condition_maybe_unordered (rc);
9210 rc = reverse_condition (rc);
9211 operands[5] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
9213 [(set_attr "conds" "use")
9214 (set_attr "type" "multiple")
9215 (set_attr "length" "8")]
9218 (define_insn_and_split "*ior_scc"
9219 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
9220 (ior:SI (match_operator:SI 1 "arm_comparison_operator"
9221 [(match_operand 2 "cc_register" "") (const_int 0)])
9222 (match_operand:SI 3 "s_register_operand" "0,?r")))]
9227 "&& reload_completed
9228 && REGNO (operands [0]) != REGNO (operands[3])"
9229 ;; && which_alternative == 1
9230 ; mov%D1\\t%0, %3\;orr%d1\\t%0, %3, #1
9231 [(cond_exec (match_dup 5) (set (match_dup 0) (match_dup 3)))
9232 (cond_exec (match_dup 4) (set (match_dup 0)
9233 (ior:SI (match_dup 3) (const_int 1))))]
9235 machine_mode mode = GET_MODE (operands[2]);
9236 enum rtx_code rc = GET_CODE (operands[1]);
9238 /* Note that operands[4] is the same as operands[1],
9239 but with VOIDmode as the result. */
9240 operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
9241 if (mode == CCFPmode || mode == CCFPEmode)
9242 rc = reverse_condition_maybe_unordered (rc);
9244 rc = reverse_condition (rc);
9245 operands[5] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
9247 [(set_attr "conds" "use")
9248 (set_attr "length" "4,8")
9249 (set_attr "type" "logic_imm,multiple")]
9252 ; A series of splitters for the compare_scc pattern below. Note that
9253 ; order is important.
9255 [(set (match_operand:SI 0 "s_register_operand" "")
9256 (lt:SI (match_operand:SI 1 "s_register_operand" "")
9258 (clobber (reg:CC CC_REGNUM))]
9259 "TARGET_32BIT && reload_completed"
9260 [(set (match_dup 0) (lshiftrt:SI (match_dup 1) (const_int 31)))])
9263 [(set (match_operand:SI 0 "s_register_operand" "")
9264 (ge:SI (match_operand:SI 1 "s_register_operand" "")
9266 (clobber (reg:CC CC_REGNUM))]
9267 "TARGET_32BIT && reload_completed"
9268 [(set (match_dup 0) (not:SI (match_dup 1)))
9269 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 31)))])
9272 [(set (match_operand:SI 0 "s_register_operand" "")
9273 (eq:SI (match_operand:SI 1 "s_register_operand" "")
9275 (clobber (reg:CC CC_REGNUM))]
9276 "arm_arch5t && TARGET_32BIT"
9277 [(set (match_dup 0) (clz:SI (match_dup 1)))
9278 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 5)))]
9282 [(set (match_operand:SI 0 "s_register_operand" "")
9283 (eq:SI (match_operand:SI 1 "s_register_operand" "")
9285 (clobber (reg:CC CC_REGNUM))]
9286 "TARGET_32BIT && reload_completed"
9288 [(set (reg:CC CC_REGNUM)
9289 (compare:CC (const_int 1) (match_dup 1)))
9291 (minus:SI (const_int 1) (match_dup 1)))])
9292 (cond_exec (ltu:CC (reg:CC CC_REGNUM) (const_int 0))
9293 (set (match_dup 0) (const_int 0)))])
9296 [(set (match_operand:SI 0 "s_register_operand" "")
9297 (ne:SI (match_operand:SI 1 "s_register_operand" "")
9298 (match_operand:SI 2 "const_int_operand" "")))
9299 (clobber (reg:CC CC_REGNUM))]
9300 "TARGET_32BIT && reload_completed"
9302 [(set (reg:CC CC_REGNUM)
9303 (compare:CC (match_dup 1) (match_dup 2)))
9304 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))])
9305 (cond_exec (ne:CC (reg:CC CC_REGNUM) (const_int 0))
9306 (set (match_dup 0) (const_int 1)))]
9308 operands[3] = gen_int_mode (-INTVAL (operands[2]), SImode);
9312 [(set (match_operand:SI 0 "s_register_operand" "")
9313 (ne:SI (match_operand:SI 1 "s_register_operand" "")
9314 (match_operand:SI 2 "arm_add_operand" "")))
9315 (clobber (reg:CC CC_REGNUM))]
9316 "TARGET_32BIT && reload_completed"
9318 [(set (reg:CC_NOOV CC_REGNUM)
9319 (compare:CC_NOOV (minus:SI (match_dup 1) (match_dup 2))
9321 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
9322 (cond_exec (ne:CC_NOOV (reg:CC_NOOV CC_REGNUM) (const_int 0))
9323 (set (match_dup 0) (const_int 1)))])
9325 (define_insn_and_split "*compare_scc"
9326 [(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts")
9327 (match_operator:SI 1 "arm_comparison_operator"
9328 [(match_operand:SI 2 "s_register_operand" "r,r")
9329 (match_operand:SI 3 "arm_add_operand" "rI,L")]))
9330 (clobber (reg:CC CC_REGNUM))]
9333 "&& reload_completed"
9334 [(set (reg:CC CC_REGNUM) (compare:CC (match_dup 2) (match_dup 3)))
9335 (cond_exec (match_dup 4) (set (match_dup 0) (const_int 0)))
9336 (cond_exec (match_dup 5) (set (match_dup 0) (const_int 1)))]
9339 machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[1]),
9340 operands[2], operands[3]);
9341 enum rtx_code rc = GET_CODE (operands[1]);
9343 tmp1 = gen_rtx_REG (mode, CC_REGNUM);
9345 operands[5] = gen_rtx_fmt_ee (rc, VOIDmode, tmp1, const0_rtx);
9346 if (mode == CCFPmode || mode == CCFPEmode)
9347 rc = reverse_condition_maybe_unordered (rc);
9349 rc = reverse_condition (rc);
9350 operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, tmp1, const0_rtx);
9352 [(set_attr "type" "multiple")]
9355 ;; Attempt to improve the sequence generated by the compare_scc splitters
9356 ;; not to use conditional execution.
9358 ;; Rd = (eq (reg1) (const_int0)) // ARMv5
9362 [(set (reg:CC CC_REGNUM)
9363 (compare:CC (match_operand:SI 1 "register_operand" "")
9365 (cond_exec (ne (reg:CC CC_REGNUM) (const_int 0))
9366 (set (match_operand:SI 0 "register_operand" "") (const_int 0)))
9367 (cond_exec (eq (reg:CC CC_REGNUM) (const_int 0))
9368 (set (match_dup 0) (const_int 1)))]
9369 "arm_arch5t && TARGET_32BIT && peep2_regno_dead_p (3, CC_REGNUM)"
9370 [(set (match_dup 0) (clz:SI (match_dup 1)))
9371 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 5)))]
9374 ;; Rd = (eq (reg1) (const_int0)) // !ARMv5
9378 [(set (reg:CC CC_REGNUM)
9379 (compare:CC (match_operand:SI 1 "register_operand" "")
9381 (cond_exec (ne (reg:CC CC_REGNUM) (const_int 0))
9382 (set (match_operand:SI 0 "register_operand" "") (const_int 0)))
9383 (cond_exec (eq (reg:CC CC_REGNUM) (const_int 0))
9384 (set (match_dup 0) (const_int 1)))
9385 (match_scratch:SI 2 "r")]
9386 "TARGET_32BIT && peep2_regno_dead_p (3, CC_REGNUM)"
9388 [(set (reg:CC CC_REGNUM)
9389 (compare:CC (const_int 0) (match_dup 1)))
9390 (set (match_dup 2) (minus:SI (const_int 0) (match_dup 1)))])
9392 (plus:SI (plus:SI (match_dup 1) (match_dup 2))
9393 (geu:SI (reg:CC CC_REGNUM) (const_int 0))))]
9396 ;; Rd = (eq (reg1) (reg2/imm)) // ARMv5 and optimising for speed.
9397 ;; sub Rd, Reg1, reg2
9401 [(set (reg:CC CC_REGNUM)
9402 (compare:CC (match_operand:SI 1 "register_operand" "")
9403 (match_operand:SI 2 "arm_rhs_operand" "")))
9404 (cond_exec (ne (reg:CC CC_REGNUM) (const_int 0))
9405 (set (match_operand:SI 0 "register_operand" "") (const_int 0)))
9406 (cond_exec (eq (reg:CC CC_REGNUM) (const_int 0))
9407 (set (match_dup 0) (const_int 1)))]
9408 "arm_arch5t && TARGET_32BIT && peep2_regno_dead_p (3, CC_REGNUM)
9409 && !(TARGET_THUMB2 && optimize_insn_for_size_p ())"
9410 [(set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))
9411 (set (match_dup 0) (clz:SI (match_dup 0)))
9412 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 5)))]
9416 ;; Rd = (eq (reg1) (reg2)) // ! ARMv5 or optimising for size.
9417 ;; sub T1, Reg1, reg2
9421 [(set (reg:CC CC_REGNUM)
9422 (compare:CC (match_operand:SI 1 "register_operand" "")
9423 (match_operand:SI 2 "arm_rhs_operand" "")))
9424 (cond_exec (ne (reg:CC CC_REGNUM) (const_int 0))
9425 (set (match_operand:SI 0 "register_operand" "") (const_int 0)))
9426 (cond_exec (eq (reg:CC CC_REGNUM) (const_int 0))
9427 (set (match_dup 0) (const_int 1)))
9428 (match_scratch:SI 3 "r")]
9429 "TARGET_32BIT && peep2_regno_dead_p (3, CC_REGNUM)"
9430 [(set (match_dup 3) (match_dup 4))
9432 [(set (reg:CC CC_REGNUM)
9433 (compare:CC (const_int 0) (match_dup 3)))
9434 (set (match_dup 0) (minus:SI (const_int 0) (match_dup 3)))])
9436 (plus:SI (plus:SI (match_dup 0) (match_dup 3))
9437 (geu:SI (reg:CC CC_REGNUM) (const_int 0))))]
9439 if (CONST_INT_P (operands[2]))
9440 operands[4] = plus_constant (SImode, operands[1], -INTVAL (operands[2]));
9442 operands[4] = gen_rtx_MINUS (SImode, operands[1], operands[2]);
9445 (define_insn "*cond_move"
9446 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
9447 (if_then_else:SI (match_operator 3 "equality_operator"
9448 [(match_operator 4 "arm_comparison_operator"
9449 [(match_operand 5 "cc_register" "") (const_int 0)])
9451 (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI")
9452 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))]
9455 if (GET_CODE (operands[3]) == NE)
9457 if (which_alternative != 1)
9458 output_asm_insn (\"mov%D4\\t%0, %2\", operands);
9459 if (which_alternative != 0)
9460 output_asm_insn (\"mov%d4\\t%0, %1\", operands);
9463 if (which_alternative != 0)
9464 output_asm_insn (\"mov%D4\\t%0, %1\", operands);
9465 if (which_alternative != 1)
9466 output_asm_insn (\"mov%d4\\t%0, %2\", operands);
9469 [(set_attr "conds" "use")
9470 (set_attr_alternative "type"
9471 [(if_then_else (match_operand 2 "const_int_operand" "")
9472 (const_string "mov_imm")
9473 (const_string "mov_reg"))
9474 (if_then_else (match_operand 1 "const_int_operand" "")
9475 (const_string "mov_imm")
9476 (const_string "mov_reg"))
9477 (const_string "multiple")])
9478 (set_attr "length" "4,4,8")]
9481 (define_insn "*cond_arith"
9482 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
9483 (match_operator:SI 5 "shiftable_operator"
9484 [(match_operator:SI 4 "arm_comparison_operator"
9485 [(match_operand:SI 2 "s_register_operand" "r,r")
9486 (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])
9487 (match_operand:SI 1 "s_register_operand" "0,?r")]))
9488 (clobber (reg:CC CC_REGNUM))]
9491 if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx)
9492 return \"%i5\\t%0, %1, %2, lsr #31\";
9494 output_asm_insn (\"cmp\\t%2, %3\", operands);
9495 if (GET_CODE (operands[5]) == AND)
9496 output_asm_insn (\"mov%D4\\t%0, #0\", operands);
9497 else if (GET_CODE (operands[5]) == MINUS)
9498 output_asm_insn (\"rsb%D4\\t%0, %1, #0\", operands);
9499 else if (which_alternative != 0)
9500 output_asm_insn (\"mov%D4\\t%0, %1\", operands);
9501 return \"%i5%d4\\t%0, %1, #1\";
9503 [(set_attr "conds" "clob")
9504 (set_attr "length" "12")
9505 (set_attr "type" "multiple")]
9508 (define_insn "*cond_sub"
9509 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
9510 (minus:SI (match_operand:SI 1 "s_register_operand" "0,?r")
9511 (match_operator:SI 4 "arm_comparison_operator"
9512 [(match_operand:SI 2 "s_register_operand" "r,r")
9513 (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))
9514 (clobber (reg:CC CC_REGNUM))]
9517 output_asm_insn (\"cmp\\t%2, %3\", operands);
9518 if (which_alternative != 0)
9519 output_asm_insn (\"mov%D4\\t%0, %1\", operands);
9520 return \"sub%d4\\t%0, %1, #1\";
9522 [(set_attr "conds" "clob")
9523 (set_attr "length" "8,12")
9524 (set_attr "type" "multiple")]
9527 (define_insn "*cmp_ite0"
9528 [(set (match_operand 6 "dominant_cc_register" "")
9531 (match_operator 4 "arm_comparison_operator"
9532 [(match_operand:SI 0 "s_register_operand"
9533 "l,l,l,r,r,r,r,r,r")
9534 (match_operand:SI 1 "arm_add_operand"
9535 "lPy,lPy,lPy,rI,L,rI,L,rI,L")])
9536 (match_operator:SI 5 "arm_comparison_operator"
9537 [(match_operand:SI 2 "s_register_operand"
9538 "l,r,r,l,l,r,r,r,r")
9539 (match_operand:SI 3 "arm_add_operand"
9540 "lPy,rI,L,lPy,lPy,rI,rI,L,L")])
9546 static const char * const cmp1[NUM_OF_COND_CMP][2] =
9548 {\"cmp%d5\\t%0, %1\",
9549 \"cmp%d4\\t%2, %3\"},
9550 {\"cmn%d5\\t%0, #%n1\",
9551 \"cmp%d4\\t%2, %3\"},
9552 {\"cmp%d5\\t%0, %1\",
9553 \"cmn%d4\\t%2, #%n3\"},
9554 {\"cmn%d5\\t%0, #%n1\",
9555 \"cmn%d4\\t%2, #%n3\"}
9557 static const char * const cmp2[NUM_OF_COND_CMP][2] =
9562 \"cmn\\t%0, #%n1\"},
9563 {\"cmn\\t%2, #%n3\",
9565 {\"cmn\\t%2, #%n3\",
9568 static const char * const ite[2] =
9573 static const int cmp_idx[9] = {CMP_CMP, CMP_CMP, CMP_CMN,
9574 CMP_CMP, CMN_CMP, CMP_CMP,
9575 CMN_CMP, CMP_CMN, CMN_CMN};
9577 comparison_dominates_p (GET_CODE (operands[5]), GET_CODE (operands[4]));
9579 output_asm_insn (cmp2[cmp_idx[which_alternative]][swap], operands);
9580 if (TARGET_THUMB2) {
9581 output_asm_insn (ite[swap], operands);
9583 output_asm_insn (cmp1[cmp_idx[which_alternative]][swap], operands);
9586 [(set_attr "conds" "set")
9587 (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any")
9588 (set_attr "enabled_for_short_it" "yes,no,no,no,no,no,no,no,no")
9589 (set_attr "type" "multiple")
9590 (set_attr_alternative "length"
9596 (if_then_else (eq_attr "is_thumb" "no")
9599 (if_then_else (eq_attr "is_thumb" "no")
9602 (if_then_else (eq_attr "is_thumb" "no")
9605 (if_then_else (eq_attr "is_thumb" "no")
9610 (define_insn "*cmp_ite1"
9611 [(set (match_operand 6 "dominant_cc_register" "")
9614 (match_operator 4 "arm_comparison_operator"
9615 [(match_operand:SI 0 "s_register_operand"
9616 "l,l,l,r,r,r,r,r,r")
9617 (match_operand:SI 1 "arm_add_operand"
9618 "lPy,lPy,lPy,rI,L,rI,L,rI,L")])
9619 (match_operator:SI 5 "arm_comparison_operator"
9620 [(match_operand:SI 2 "s_register_operand"
9621 "l,r,r,l,l,r,r,r,r")
9622 (match_operand:SI 3 "arm_add_operand"
9623 "lPy,rI,L,lPy,lPy,rI,rI,L,L")])
9629 static const char * const cmp1[NUM_OF_COND_CMP][2] =
9633 {\"cmn\\t%0, #%n1\",
9636 \"cmn\\t%2, #%n3\"},
9637 {\"cmn\\t%0, #%n1\",
9640 static const char * const cmp2[NUM_OF_COND_CMP][2] =
9642 {\"cmp%d4\\t%2, %3\",
9643 \"cmp%D5\\t%0, %1\"},
9644 {\"cmp%d4\\t%2, %3\",
9645 \"cmn%D5\\t%0, #%n1\"},
9646 {\"cmn%d4\\t%2, #%n3\",
9647 \"cmp%D5\\t%0, %1\"},
9648 {\"cmn%d4\\t%2, #%n3\",
9649 \"cmn%D5\\t%0, #%n1\"}
9651 static const char * const ite[2] =
9656 static const int cmp_idx[9] = {CMP_CMP, CMP_CMP, CMP_CMN,
9657 CMP_CMP, CMN_CMP, CMP_CMP,
9658 CMN_CMP, CMP_CMN, CMN_CMN};
9660 comparison_dominates_p (GET_CODE (operands[5]),
9661 reverse_condition (GET_CODE (operands[4])));
9663 output_asm_insn (cmp1[cmp_idx[which_alternative]][swap], operands);
9664 if (TARGET_THUMB2) {
9665 output_asm_insn (ite[swap], operands);
9667 output_asm_insn (cmp2[cmp_idx[which_alternative]][swap], operands);
9670 [(set_attr "conds" "set")
9671 (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any")
9672 (set_attr "enabled_for_short_it" "yes,no,no,no,no,no,no,no,no")
9673 (set_attr_alternative "length"
9679 (if_then_else (eq_attr "is_thumb" "no")
9682 (if_then_else (eq_attr "is_thumb" "no")
9685 (if_then_else (eq_attr "is_thumb" "no")
9688 (if_then_else (eq_attr "is_thumb" "no")
9691 (set_attr "type" "multiple")]
9694 (define_insn "*cmp_and"
9695 [(set (match_operand 6 "dominant_cc_register" "")
9698 (match_operator 4 "arm_comparison_operator"
9699 [(match_operand:SI 0 "s_register_operand"
9700 "l,l,l,r,r,r,r,r,r")
9701 (match_operand:SI 1 "arm_add_operand"
9702 "lPy,lPy,lPy,rI,L,rI,L,rI,L")])
9703 (match_operator:SI 5 "arm_comparison_operator"
9704 [(match_operand:SI 2 "s_register_operand"
9705 "l,r,r,l,l,r,r,r,r")
9706 (match_operand:SI 3 "arm_add_operand"
9707 "lPy,rI,L,lPy,lPy,rI,rI,L,L")]))
9712 static const char *const cmp1[NUM_OF_COND_CMP][2] =
9714 {\"cmp%d5\\t%0, %1\",
9715 \"cmp%d4\\t%2, %3\"},
9716 {\"cmn%d5\\t%0, #%n1\",
9717 \"cmp%d4\\t%2, %3\"},
9718 {\"cmp%d5\\t%0, %1\",
9719 \"cmn%d4\\t%2, #%n3\"},
9720 {\"cmn%d5\\t%0, #%n1\",
9721 \"cmn%d4\\t%2, #%n3\"}
9723 static const char *const cmp2[NUM_OF_COND_CMP][2] =
9728 \"cmn\\t%0, #%n1\"},
9729 {\"cmn\\t%2, #%n3\",
9731 {\"cmn\\t%2, #%n3\",
9734 static const char *const ite[2] =
9739 static const int cmp_idx[9] = {CMP_CMP, CMP_CMP, CMP_CMN,
9740 CMP_CMP, CMN_CMP, CMP_CMP,
9741 CMN_CMP, CMP_CMN, CMN_CMN};
9743 comparison_dominates_p (GET_CODE (operands[5]), GET_CODE (operands[4]));
9745 output_asm_insn (cmp2[cmp_idx[which_alternative]][swap], operands);
9746 if (TARGET_THUMB2) {
9747 output_asm_insn (ite[swap], operands);
9749 output_asm_insn (cmp1[cmp_idx[which_alternative]][swap], operands);
9752 [(set_attr "conds" "set")
9753 (set_attr "predicable" "no")
9754 (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any")
9755 (set_attr "enabled_for_short_it" "yes,no,no,no,no,no,no,no,no")
9756 (set_attr_alternative "length"
9762 (if_then_else (eq_attr "is_thumb" "no")
9765 (if_then_else (eq_attr "is_thumb" "no")
9768 (if_then_else (eq_attr "is_thumb" "no")
9771 (if_then_else (eq_attr "is_thumb" "no")
9774 (set_attr "type" "multiple")]
9777 (define_insn "*cmp_ior"
9778 [(set (match_operand 6 "dominant_cc_register" "")
9781 (match_operator 4 "arm_comparison_operator"
9782 [(match_operand:SI 0 "s_register_operand"
9783 "l,l,l,r,r,r,r,r,r")
9784 (match_operand:SI 1 "arm_add_operand"
9785 "lPy,lPy,lPy,rI,L,rI,L,rI,L")])
9786 (match_operator:SI 5 "arm_comparison_operator"
9787 [(match_operand:SI 2 "s_register_operand"
9788 "l,r,r,l,l,r,r,r,r")
9789 (match_operand:SI 3 "arm_add_operand"
9790 "lPy,rI,L,lPy,lPy,rI,rI,L,L")]))
9795 static const char *const cmp1[NUM_OF_COND_CMP][2] =
9799 {\"cmn\\t%0, #%n1\",
9802 \"cmn\\t%2, #%n3\"},
9803 {\"cmn\\t%0, #%n1\",
9806 static const char *const cmp2[NUM_OF_COND_CMP][2] =
9808 {\"cmp%D4\\t%2, %3\",
9809 \"cmp%D5\\t%0, %1\"},
9810 {\"cmp%D4\\t%2, %3\",
9811 \"cmn%D5\\t%0, #%n1\"},
9812 {\"cmn%D4\\t%2, #%n3\",
9813 \"cmp%D5\\t%0, %1\"},
9814 {\"cmn%D4\\t%2, #%n3\",
9815 \"cmn%D5\\t%0, #%n1\"}
9817 static const char *const ite[2] =
9822 static const int cmp_idx[9] = {CMP_CMP, CMP_CMP, CMP_CMN,
9823 CMP_CMP, CMN_CMP, CMP_CMP,
9824 CMN_CMP, CMP_CMN, CMN_CMN};
9826 comparison_dominates_p (GET_CODE (operands[5]), GET_CODE (operands[4]));
9828 output_asm_insn (cmp1[cmp_idx[which_alternative]][swap], operands);
9829 if (TARGET_THUMB2) {
9830 output_asm_insn (ite[swap], operands);
9832 output_asm_insn (cmp2[cmp_idx[which_alternative]][swap], operands);
9836 [(set_attr "conds" "set")
9837 (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any")
9838 (set_attr "enabled_for_short_it" "yes,no,no,no,no,no,no,no,no")
9839 (set_attr_alternative "length"
9845 (if_then_else (eq_attr "is_thumb" "no")
9848 (if_then_else (eq_attr "is_thumb" "no")
9851 (if_then_else (eq_attr "is_thumb" "no")
9854 (if_then_else (eq_attr "is_thumb" "no")
9857 (set_attr "type" "multiple")]
9860 (define_insn_and_split "*ior_scc_scc"
9861 [(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts")
9862 (ior:SI (match_operator:SI 3 "arm_comparison_operator"
9863 [(match_operand:SI 1 "s_register_operand" "l,r")
9864 (match_operand:SI 2 "arm_add_operand" "lPy,rIL")])
9865 (match_operator:SI 6 "arm_comparison_operator"
9866 [(match_operand:SI 4 "s_register_operand" "l,r")
9867 (match_operand:SI 5 "arm_add_operand" "lPy,rIL")])))
9868 (clobber (reg:CC CC_REGNUM))]
9870 && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_OR_Y)
9873 "TARGET_32BIT && reload_completed"
9877 (match_op_dup 3 [(match_dup 1) (match_dup 2)])
9878 (match_op_dup 6 [(match_dup 4) (match_dup 5)]))
9880 (set (match_dup 0) (ne:SI (match_dup 7) (const_int 0)))]
9882 = gen_rtx_REG (arm_select_dominance_cc_mode (operands[3], operands[6],
9885 [(set_attr "conds" "clob")
9886 (set_attr "enabled_for_short_it" "yes,no")
9887 (set_attr "length" "16")
9888 (set_attr "type" "multiple")]
9891 ; If the above pattern is followed by a CMP insn, then the compare is
9892 ; redundant, since we can rework the conditional instruction that follows.
9893 (define_insn_and_split "*ior_scc_scc_cmp"
9894 [(set (match_operand 0 "dominant_cc_register" "")
9895 (compare (ior:SI (match_operator:SI 3 "arm_comparison_operator"
9896 [(match_operand:SI 1 "s_register_operand" "l,r")
9897 (match_operand:SI 2 "arm_add_operand" "lPy,rIL")])
9898 (match_operator:SI 6 "arm_comparison_operator"
9899 [(match_operand:SI 4 "s_register_operand" "l,r")
9900 (match_operand:SI 5 "arm_add_operand" "lPy,rIL")]))
9902 (set (match_operand:SI 7 "s_register_operand" "=Ts,Ts")
9903 (ior:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])
9904 (match_op_dup 6 [(match_dup 4) (match_dup 5)])))]
9907 "TARGET_32BIT && reload_completed"
9911 (match_op_dup 3 [(match_dup 1) (match_dup 2)])
9912 (match_op_dup 6 [(match_dup 4) (match_dup 5)]))
9914 (set (match_dup 7) (ne:SI (match_dup 0) (const_int 0)))]
9916 [(set_attr "conds" "set")
9917 (set_attr "enabled_for_short_it" "yes,no")
9918 (set_attr "length" "16")
9919 (set_attr "type" "multiple")]
9922 (define_insn_and_split "*and_scc_scc"
9923 [(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts")
9924 (and:SI (match_operator:SI 3 "arm_comparison_operator"
9925 [(match_operand:SI 1 "s_register_operand" "l,r")
9926 (match_operand:SI 2 "arm_add_operand" "lPy,rIL")])
9927 (match_operator:SI 6 "arm_comparison_operator"
9928 [(match_operand:SI 4 "s_register_operand" "l,r")
9929 (match_operand:SI 5 "arm_add_operand" "lPy,rIL")])))
9930 (clobber (reg:CC CC_REGNUM))]
9932 && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y)
9935 "TARGET_32BIT && reload_completed
9936 && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y)
9941 (match_op_dup 3 [(match_dup 1) (match_dup 2)])
9942 (match_op_dup 6 [(match_dup 4) (match_dup 5)]))
9944 (set (match_dup 0) (ne:SI (match_dup 7) (const_int 0)))]
9946 = gen_rtx_REG (arm_select_dominance_cc_mode (operands[3], operands[6],
9949 [(set_attr "conds" "clob")
9950 (set_attr "enabled_for_short_it" "yes,no")
9951 (set_attr "length" "16")
9952 (set_attr "type" "multiple")]
9955 ; If the above pattern is followed by a CMP insn, then the compare is
9956 ; redundant, since we can rework the conditional instruction that follows.
9957 (define_insn_and_split "*and_scc_scc_cmp"
9958 [(set (match_operand 0 "dominant_cc_register" "")
9959 (compare (and:SI (match_operator:SI 3 "arm_comparison_operator"
9960 [(match_operand:SI 1 "s_register_operand" "l,r")
9961 (match_operand:SI 2 "arm_add_operand" "lPy,rIL")])
9962 (match_operator:SI 6 "arm_comparison_operator"
9963 [(match_operand:SI 4 "s_register_operand" "l,r")
9964 (match_operand:SI 5 "arm_add_operand" "lPy,rIL")]))
9966 (set (match_operand:SI 7 "s_register_operand" "=Ts,Ts")
9967 (and:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])
9968 (match_op_dup 6 [(match_dup 4) (match_dup 5)])))]
9971 "TARGET_32BIT && reload_completed"
9975 (match_op_dup 3 [(match_dup 1) (match_dup 2)])
9976 (match_op_dup 6 [(match_dup 4) (match_dup 5)]))
9978 (set (match_dup 7) (ne:SI (match_dup 0) (const_int 0)))]
9980 [(set_attr "conds" "set")
9981 (set_attr "enabled_for_short_it" "yes,no")
9982 (set_attr "length" "16")
9983 (set_attr "type" "multiple")]
9986 ;; If there is no dominance in the comparison, then we can still save an
9987 ;; instruction in the AND case, since we can know that the second compare
9988 ;; need only zero the value if false (if true, then the value is already
9990 (define_insn_and_split "*and_scc_scc_nodom"
9991 [(set (match_operand:SI 0 "s_register_operand" "=&Ts,&Ts,&Ts")
9992 (and:SI (match_operator:SI 3 "arm_comparison_operator"
9993 [(match_operand:SI 1 "s_register_operand" "r,r,0")
9994 (match_operand:SI 2 "arm_add_operand" "rIL,0,rIL")])
9995 (match_operator:SI 6 "arm_comparison_operator"
9996 [(match_operand:SI 4 "s_register_operand" "r,r,r")
9997 (match_operand:SI 5 "arm_add_operand" "rIL,rIL,rIL")])))
9998 (clobber (reg:CC CC_REGNUM))]
10000 && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y)
10003 "TARGET_32BIT && reload_completed"
10004 [(parallel [(set (match_dup 0)
10005 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
10006 (clobber (reg:CC CC_REGNUM))])
10007 (set (match_dup 7) (match_op_dup 8 [(match_dup 4) (match_dup 5)]))
10009 (if_then_else:SI (match_op_dup 6 [(match_dup 7) (const_int 0)])
10012 "operands[7] = gen_rtx_REG (SELECT_CC_MODE (GET_CODE (operands[6]),
10013 operands[4], operands[5]),
10015 operands[8] = gen_rtx_COMPARE (GET_MODE (operands[7]), operands[4],
10017 [(set_attr "conds" "clob")
10018 (set_attr "length" "20")
10019 (set_attr "type" "multiple")]
10023 [(set (reg:CC_NOOV CC_REGNUM)
10024 (compare:CC_NOOV (ior:SI
10025 (and:SI (match_operand:SI 0 "s_register_operand" "")
10027 (match_operator:SI 1 "arm_comparison_operator"
10028 [(match_operand:SI 2 "s_register_operand" "")
10029 (match_operand:SI 3 "arm_add_operand" "")]))
10031 (clobber (match_operand:SI 4 "s_register_operand" ""))]
10033 [(set (match_dup 4)
10034 (ior:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
10036 (set (reg:CC_NOOV CC_REGNUM)
10037 (compare:CC_NOOV (and:SI (match_dup 4) (const_int 1))
10042 [(set (reg:CC_NOOV CC_REGNUM)
10043 (compare:CC_NOOV (ior:SI
10044 (match_operator:SI 1 "arm_comparison_operator"
10045 [(match_operand:SI 2 "s_register_operand" "")
10046 (match_operand:SI 3 "arm_add_operand" "")])
10047 (and:SI (match_operand:SI 0 "s_register_operand" "")
10050 (clobber (match_operand:SI 4 "s_register_operand" ""))]
10052 [(set (match_dup 4)
10053 (ior:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
10055 (set (reg:CC_NOOV CC_REGNUM)
10056 (compare:CC_NOOV (and:SI (match_dup 4) (const_int 1))
10059 ;; ??? The conditional patterns above need checking for Thumb-2 usefulness
10061 (define_insn_and_split "*negscc"
10062 [(set (match_operand:SI 0 "s_register_operand" "=r")
10063 (neg:SI (match_operator 3 "arm_comparison_operator"
10064 [(match_operand:SI 1 "s_register_operand" "r")
10065 (match_operand:SI 2 "arm_rhs_operand" "rI")])))
10066 (clobber (reg:CC CC_REGNUM))]
10069 "&& reload_completed"
10072 rtx cc_reg = gen_rtx_REG (CCmode, CC_REGNUM);
10074 if (GET_CODE (operands[3]) == LT && operands[2] == const0_rtx)
10076 /* Emit mov\\t%0, %1, asr #31 */
10077 emit_insn (gen_rtx_SET (operands[0],
10078 gen_rtx_ASHIFTRT (SImode,
10083 else if (GET_CODE (operands[3]) == NE)
10085 /* Emit subs\\t%0, %1, %2\;mvnne\\t%0, #0 */
10086 if (CONST_INT_P (operands[2]))
10087 emit_insn (gen_cmpsi2_addneg (operands[0], operands[1], operands[2],
10088 gen_int_mode (-INTVAL (operands[2]),
10091 emit_insn (gen_subsi3_compare (operands[0], operands[1], operands[2]));
10093 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
10094 gen_rtx_NE (SImode,
10097 gen_rtx_SET (operands[0],
10103 /* Emit: cmp\\t%1, %2\;mov%D3\\t%0, #0\;mvn%d3\\t%0, #0 */
10104 emit_insn (gen_rtx_SET (cc_reg,
10105 gen_rtx_COMPARE (CCmode, operands[1], operands[2])));
10106 enum rtx_code rc = GET_CODE (operands[3]);
10108 rc = reverse_condition (rc);
10109 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
10110 gen_rtx_fmt_ee (rc,
10114 gen_rtx_SET (operands[0], const0_rtx)));
10115 rc = GET_CODE (operands[3]);
10116 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
10117 gen_rtx_fmt_ee (rc,
10121 gen_rtx_SET (operands[0],
10127 [(set_attr "conds" "clob")
10128 (set_attr "length" "12")
10129 (set_attr "type" "multiple")]
10132 (define_insn_and_split "movcond_addsi"
10133 [(set (match_operand:SI 0 "s_register_operand" "=r,l,r")
10135 (match_operator 5 "comparison_operator"
10136 [(plus:SI (match_operand:SI 3 "s_register_operand" "r,r,r")
10137 (match_operand:SI 4 "arm_add_operand" "rIL,rIL,rIL"))
10139 (match_operand:SI 1 "arm_rhs_operand" "rI,rPy,r")
10140 (match_operand:SI 2 "arm_rhs_operand" "rI,rPy,r")))
10141 (clobber (reg:CC CC_REGNUM))]
10144 "&& reload_completed"
10145 [(set (reg:CC_NOOV CC_REGNUM)
10147 (plus:SI (match_dup 3)
10150 (set (match_dup 0) (match_dup 1))
10151 (cond_exec (match_dup 6)
10152 (set (match_dup 0) (match_dup 2)))]
10155 machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[5]),
10156 operands[3], operands[4]);
10157 enum rtx_code rc = GET_CODE (operands[5]);
10158 operands[6] = gen_rtx_REG (mode, CC_REGNUM);
10159 gcc_assert (!(mode == CCFPmode || mode == CCFPEmode));
10160 if (!REG_P (operands[2]) || REGNO (operands[2]) != REGNO (operands[0]))
10161 rc = reverse_condition (rc);
10163 std::swap (operands[1], operands[2]);
10165 operands[6] = gen_rtx_fmt_ee (rc, VOIDmode, operands[6], const0_rtx);
10168 [(set_attr "conds" "clob")
10169 (set_attr "enabled_for_short_it" "no,yes,yes")
10170 (set_attr "type" "multiple")]
10173 (define_insn "movcond"
10174 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
10176 (match_operator 5 "arm_comparison_operator"
10177 [(match_operand:SI 3 "s_register_operand" "r,r,r")
10178 (match_operand:SI 4 "arm_add_operand" "rIL,rIL,rIL")])
10179 (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI")
10180 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
10181 (clobber (reg:CC CC_REGNUM))]
10184 if (GET_CODE (operands[5]) == LT
10185 && (operands[4] == const0_rtx))
10187 if (which_alternative != 1 && REG_P (operands[1]))
10189 if (operands[2] == const0_rtx)
10190 return \"and\\t%0, %1, %3, asr #31\";
10191 return \"ands\\t%0, %1, %3, asr #32\;movcc\\t%0, %2\";
10193 else if (which_alternative != 0 && REG_P (operands[2]))
10195 if (operands[1] == const0_rtx)
10196 return \"bic\\t%0, %2, %3, asr #31\";
10197 return \"bics\\t%0, %2, %3, asr #32\;movcs\\t%0, %1\";
10199 /* The only case that falls through to here is when both ops 1 & 2
10203 if (GET_CODE (operands[5]) == GE
10204 && (operands[4] == const0_rtx))
10206 if (which_alternative != 1 && REG_P (operands[1]))
10208 if (operands[2] == const0_rtx)
10209 return \"bic\\t%0, %1, %3, asr #31\";
10210 return \"bics\\t%0, %1, %3, asr #32\;movcs\\t%0, %2\";
10212 else if (which_alternative != 0 && REG_P (operands[2]))
10214 if (operands[1] == const0_rtx)
10215 return \"and\\t%0, %2, %3, asr #31\";
10216 return \"ands\\t%0, %2, %3, asr #32\;movcc\\t%0, %1\";
10218 /* The only case that falls through to here is when both ops 1 & 2
10221 if (CONST_INT_P (operands[4])
10222 && !const_ok_for_arm (INTVAL (operands[4])))
10223 output_asm_insn (\"cmn\\t%3, #%n4\", operands);
10225 output_asm_insn (\"cmp\\t%3, %4\", operands);
10226 if (which_alternative != 0)
10227 output_asm_insn (\"mov%d5\\t%0, %1\", operands);
10228 if (which_alternative != 1)
10229 output_asm_insn (\"mov%D5\\t%0, %2\", operands);
10232 [(set_attr "conds" "clob")
10233 (set_attr "length" "8,8,12")
10234 (set_attr "type" "multiple")]
10237 ;; ??? The patterns below need checking for Thumb-2 usefulness.
10239 (define_insn "*ifcompare_plus_move"
10240 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
10241 (if_then_else:SI (match_operator 6 "arm_comparison_operator"
10242 [(match_operand:SI 4 "s_register_operand" "r,r")
10243 (match_operand:SI 5 "arm_add_operand" "rIL,rIL")])
10245 (match_operand:SI 2 "s_register_operand" "r,r")
10246 (match_operand:SI 3 "arm_add_operand" "rIL,rIL"))
10247 (match_operand:SI 1 "arm_rhs_operand" "0,?rI")))
10248 (clobber (reg:CC CC_REGNUM))]
10251 [(set_attr "conds" "clob")
10252 (set_attr "length" "8,12")
10253 (set_attr "type" "multiple")]
10256 (define_insn "*if_plus_move"
10257 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r")
10259 (match_operator 4 "arm_comparison_operator"
10260 [(match_operand 5 "cc_register" "") (const_int 0)])
10262 (match_operand:SI 2 "s_register_operand" "r,r,r,r")
10263 (match_operand:SI 3 "arm_add_operand" "rI,L,rI,L"))
10264 (match_operand:SI 1 "arm_rhs_operand" "0,0,?rI,?rI")))]
10267 add%d4\\t%0, %2, %3
10268 sub%d4\\t%0, %2, #%n3
10269 add%d4\\t%0, %2, %3\;mov%D4\\t%0, %1
10270 sub%d4\\t%0, %2, #%n3\;mov%D4\\t%0, %1"
10271 [(set_attr "conds" "use")
10272 (set_attr "length" "4,4,8,8")
10273 (set_attr_alternative "type"
10274 [(if_then_else (match_operand 3 "const_int_operand" "")
10275 (const_string "alu_imm" )
10276 (const_string "alu_sreg"))
10277 (const_string "alu_imm")
10278 (const_string "multiple")
10279 (const_string "multiple")])]
10282 (define_insn "*ifcompare_move_plus"
10283 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
10284 (if_then_else:SI (match_operator 6 "arm_comparison_operator"
10285 [(match_operand:SI 4 "s_register_operand" "r,r")
10286 (match_operand:SI 5 "arm_add_operand" "rIL,rIL")])
10287 (match_operand:SI 1 "arm_rhs_operand" "0,?rI")
10289 (match_operand:SI 2 "s_register_operand" "r,r")
10290 (match_operand:SI 3 "arm_add_operand" "rIL,rIL"))))
10291 (clobber (reg:CC CC_REGNUM))]
10294 [(set_attr "conds" "clob")
10295 (set_attr "length" "8,12")
10296 (set_attr "type" "multiple")]
10299 (define_insn "*if_move_plus"
10300 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r")
10302 (match_operator 4 "arm_comparison_operator"
10303 [(match_operand 5 "cc_register" "") (const_int 0)])
10304 (match_operand:SI 1 "arm_rhs_operand" "0,0,?rI,?rI")
10306 (match_operand:SI 2 "s_register_operand" "r,r,r,r")
10307 (match_operand:SI 3 "arm_add_operand" "rI,L,rI,L"))))]
10310 add%D4\\t%0, %2, %3
10311 sub%D4\\t%0, %2, #%n3
10312 add%D4\\t%0, %2, %3\;mov%d4\\t%0, %1
10313 sub%D4\\t%0, %2, #%n3\;mov%d4\\t%0, %1"
10314 [(set_attr "conds" "use")
10315 (set_attr "length" "4,4,8,8")
10316 (set_attr_alternative "type"
10317 [(if_then_else (match_operand 3 "const_int_operand" "")
10318 (const_string "alu_imm" )
10319 (const_string "alu_sreg"))
10320 (const_string "alu_imm")
10321 (const_string "multiple")
10322 (const_string "multiple")])]
10325 (define_insn "*ifcompare_arith_arith"
10326 [(set (match_operand:SI 0 "s_register_operand" "=r")
10327 (if_then_else:SI (match_operator 9 "arm_comparison_operator"
10328 [(match_operand:SI 5 "s_register_operand" "r")
10329 (match_operand:SI 6 "arm_add_operand" "rIL")])
10330 (match_operator:SI 8 "shiftable_operator"
10331 [(match_operand:SI 1 "s_register_operand" "r")
10332 (match_operand:SI 2 "arm_rhs_operand" "rI")])
10333 (match_operator:SI 7 "shiftable_operator"
10334 [(match_operand:SI 3 "s_register_operand" "r")
10335 (match_operand:SI 4 "arm_rhs_operand" "rI")])))
10336 (clobber (reg:CC CC_REGNUM))]
10339 [(set_attr "conds" "clob")
10340 (set_attr "length" "12")
10341 (set_attr "type" "multiple")]
10344 (define_insn "*if_arith_arith"
10345 [(set (match_operand:SI 0 "s_register_operand" "=r")
10346 (if_then_else:SI (match_operator 5 "arm_comparison_operator"
10347 [(match_operand 8 "cc_register" "") (const_int 0)])
10348 (match_operator:SI 6 "shiftable_operator"
10349 [(match_operand:SI 1 "s_register_operand" "r")
10350 (match_operand:SI 2 "arm_rhs_operand" "rI")])
10351 (match_operator:SI 7 "shiftable_operator"
10352 [(match_operand:SI 3 "s_register_operand" "r")
10353 (match_operand:SI 4 "arm_rhs_operand" "rI")])))]
10355 "%I6%d5\\t%0, %1, %2\;%I7%D5\\t%0, %3, %4"
10356 [(set_attr "conds" "use")
10357 (set_attr "length" "8")
10358 (set_attr "type" "multiple")]
10361 (define_insn "*ifcompare_arith_move"
10362 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
10363 (if_then_else:SI (match_operator 6 "arm_comparison_operator"
10364 [(match_operand:SI 2 "s_register_operand" "r,r")
10365 (match_operand:SI 3 "arm_add_operand" "rIL,rIL")])
10366 (match_operator:SI 7 "shiftable_operator"
10367 [(match_operand:SI 4 "s_register_operand" "r,r")
10368 (match_operand:SI 5 "arm_rhs_operand" "rI,rI")])
10369 (match_operand:SI 1 "arm_rhs_operand" "0,?rI")))
10370 (clobber (reg:CC CC_REGNUM))]
10373 /* If we have an operation where (op x 0) is the identity operation and
10374 the conditional operator is LT or GE and we are comparing against zero and
10375 everything is in registers then we can do this in two instructions. */
10376 if (operands[3] == const0_rtx
10377 && GET_CODE (operands[7]) != AND
10378 && REG_P (operands[5])
10379 && REG_P (operands[1])
10380 && REGNO (operands[1]) == REGNO (operands[4])
10381 && REGNO (operands[4]) != REGNO (operands[0]))
10383 if (GET_CODE (operands[6]) == LT)
10384 return \"and\\t%0, %5, %2, asr #31\;%I7\\t%0, %4, %0\";
10385 else if (GET_CODE (operands[6]) == GE)
10386 return \"bic\\t%0, %5, %2, asr #31\;%I7\\t%0, %4, %0\";
10388 if (CONST_INT_P (operands[3])
10389 && !const_ok_for_arm (INTVAL (operands[3])))
10390 output_asm_insn (\"cmn\\t%2, #%n3\", operands);
10392 output_asm_insn (\"cmp\\t%2, %3\", operands);
10393 output_asm_insn (\"%I7%d6\\t%0, %4, %5\", operands);
10394 if (which_alternative != 0)
10395 return \"mov%D6\\t%0, %1\";
10398 [(set_attr "conds" "clob")
10399 (set_attr "length" "8,12")
10400 (set_attr "type" "multiple")]
10403 (define_insn "*if_arith_move"
10404 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
10405 (if_then_else:SI (match_operator 4 "arm_comparison_operator"
10406 [(match_operand 6 "cc_register" "") (const_int 0)])
10407 (match_operator:SI 5 "shiftable_operator"
10408 [(match_operand:SI 2 "s_register_operand" "r,r")
10409 (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])
10410 (match_operand:SI 1 "arm_rhs_operand" "0,?rI")))]
10413 %I5%d4\\t%0, %2, %3
10414 %I5%d4\\t%0, %2, %3\;mov%D4\\t%0, %1"
10415 [(set_attr "conds" "use")
10416 (set_attr "length" "4,8")
10417 (set_attr_alternative "type"
10418 [(if_then_else (match_operand 3 "const_int_operand" "")
10419 (const_string "alu_shift_imm" )
10420 (const_string "alu_shift_reg"))
10421 (const_string "multiple")])]
10424 (define_insn "*ifcompare_move_arith"
10425 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
10426 (if_then_else:SI (match_operator 6 "arm_comparison_operator"
10427 [(match_operand:SI 4 "s_register_operand" "r,r")
10428 (match_operand:SI 5 "arm_add_operand" "rIL,rIL")])
10429 (match_operand:SI 1 "arm_rhs_operand" "0,?rI")
10430 (match_operator:SI 7 "shiftable_operator"
10431 [(match_operand:SI 2 "s_register_operand" "r,r")
10432 (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))
10433 (clobber (reg:CC CC_REGNUM))]
10436 /* If we have an operation where (op x 0) is the identity operation and
10437 the conditional operator is LT or GE and we are comparing against zero and
10438 everything is in registers then we can do this in two instructions */
10439 if (operands[5] == const0_rtx
10440 && GET_CODE (operands[7]) != AND
10441 && REG_P (operands[3])
10442 && REG_P (operands[1])
10443 && REGNO (operands[1]) == REGNO (operands[2])
10444 && REGNO (operands[2]) != REGNO (operands[0]))
10446 if (GET_CODE (operands[6]) == GE)
10447 return \"and\\t%0, %3, %4, asr #31\;%I7\\t%0, %2, %0\";
10448 else if (GET_CODE (operands[6]) == LT)
10449 return \"bic\\t%0, %3, %4, asr #31\;%I7\\t%0, %2, %0\";
10452 if (CONST_INT_P (operands[5])
10453 && !const_ok_for_arm (INTVAL (operands[5])))
10454 output_asm_insn (\"cmn\\t%4, #%n5\", operands);
10456 output_asm_insn (\"cmp\\t%4, %5\", operands);
10458 if (which_alternative != 0)
10459 output_asm_insn (\"mov%d6\\t%0, %1\", operands);
10460 return \"%I7%D6\\t%0, %2, %3\";
10462 [(set_attr "conds" "clob")
10463 (set_attr "length" "8,12")
10464 (set_attr "type" "multiple")]
10467 (define_insn "*if_move_arith"
10468 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
10470 (match_operator 4 "arm_comparison_operator"
10471 [(match_operand 6 "cc_register" "") (const_int 0)])
10472 (match_operand:SI 1 "arm_rhs_operand" "0,?rI")
10473 (match_operator:SI 5 "shiftable_operator"
10474 [(match_operand:SI 2 "s_register_operand" "r,r")
10475 (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))]
10478 %I5%D4\\t%0, %2, %3
10479 %I5%D4\\t%0, %2, %3\;mov%d4\\t%0, %1"
10480 [(set_attr "conds" "use")
10481 (set_attr "length" "4,8")
10482 (set_attr_alternative "type"
10483 [(if_then_else (match_operand 3 "const_int_operand" "")
10484 (const_string "alu_shift_imm" )
10485 (const_string "alu_shift_reg"))
10486 (const_string "multiple")])]
10489 (define_insn "*ifcompare_move_not"
10490 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
10492 (match_operator 5 "arm_comparison_operator"
10493 [(match_operand:SI 3 "s_register_operand" "r,r")
10494 (match_operand:SI 4 "arm_add_operand" "rIL,rIL")])
10495 (match_operand:SI 1 "arm_not_operand" "0,?rIK")
10497 (match_operand:SI 2 "s_register_operand" "r,r"))))
10498 (clobber (reg:CC CC_REGNUM))]
10501 [(set_attr "conds" "clob")
10502 (set_attr "length" "8,12")
10503 (set_attr "type" "multiple")]
10506 (define_insn "*if_move_not"
10507 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
10509 (match_operator 4 "arm_comparison_operator"
10510 [(match_operand 3 "cc_register" "") (const_int 0)])
10511 (match_operand:SI 1 "arm_not_operand" "0,?rI,K")
10512 (not:SI (match_operand:SI 2 "s_register_operand" "r,r,r"))))]
10516 mov%d4\\t%0, %1\;mvn%D4\\t%0, %2
10517 mvn%d4\\t%0, #%B1\;mvn%D4\\t%0, %2"
10518 [(set_attr "conds" "use")
10519 (set_attr "type" "mvn_reg")
10520 (set_attr "length" "4,8,8")
10521 (set_attr "type" "mvn_reg,multiple,multiple")]
10524 (define_insn "*ifcompare_not_move"
10525 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
10527 (match_operator 5 "arm_comparison_operator"
10528 [(match_operand:SI 3 "s_register_operand" "r,r")
10529 (match_operand:SI 4 "arm_add_operand" "rIL,rIL")])
10531 (match_operand:SI 2 "s_register_operand" "r,r"))
10532 (match_operand:SI 1 "arm_not_operand" "0,?rIK")))
10533 (clobber (reg:CC CC_REGNUM))]
10536 [(set_attr "conds" "clob")
10537 (set_attr "length" "8,12")
10538 (set_attr "type" "multiple")]
10541 (define_insn "*if_not_move"
10542 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
10544 (match_operator 4 "arm_comparison_operator"
10545 [(match_operand 3 "cc_register" "") (const_int 0)])
10546 (not:SI (match_operand:SI 2 "s_register_operand" "r,r,r"))
10547 (match_operand:SI 1 "arm_not_operand" "0,?rI,K")))]
10551 mov%D4\\t%0, %1\;mvn%d4\\t%0, %2
10552 mvn%D4\\t%0, #%B1\;mvn%d4\\t%0, %2"
10553 [(set_attr "conds" "use")
10554 (set_attr "type" "mvn_reg,multiple,multiple")
10555 (set_attr "length" "4,8,8")]
10558 (define_insn "*ifcompare_shift_move"
10559 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
10561 (match_operator 6 "arm_comparison_operator"
10562 [(match_operand:SI 4 "s_register_operand" "r,r")
10563 (match_operand:SI 5 "arm_add_operand" "rIL,rIL")])
10564 (match_operator:SI 7 "shift_operator"
10565 [(match_operand:SI 2 "s_register_operand" "r,r")
10566 (match_operand:SI 3 "arm_rhs_operand" "rM,rM")])
10567 (match_operand:SI 1 "arm_not_operand" "0,?rIK")))
10568 (clobber (reg:CC CC_REGNUM))]
10571 [(set_attr "conds" "clob")
10572 (set_attr "length" "8,12")
10573 (set_attr "type" "multiple")]
10576 (define_insn "*if_shift_move"
10577 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
10579 (match_operator 5 "arm_comparison_operator"
10580 [(match_operand 6 "cc_register" "") (const_int 0)])
10581 (match_operator:SI 4 "shift_operator"
10582 [(match_operand:SI 2 "s_register_operand" "r,r,r")
10583 (match_operand:SI 3 "arm_rhs_operand" "rM,rM,rM")])
10584 (match_operand:SI 1 "arm_not_operand" "0,?rI,K")))]
10588 mov%D5\\t%0, %1\;mov%d5\\t%0, %2%S4
10589 mvn%D5\\t%0, #%B1\;mov%d5\\t%0, %2%S4"
10590 [(set_attr "conds" "use")
10591 (set_attr "shift" "2")
10592 (set_attr "length" "4,8,8")
10593 (set_attr_alternative "type"
10594 [(if_then_else (match_operand 3 "const_int_operand" "")
10595 (const_string "mov_shift" )
10596 (const_string "mov_shift_reg"))
10597 (const_string "multiple")
10598 (const_string "multiple")])]
10601 (define_insn "*ifcompare_move_shift"
10602 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
10604 (match_operator 6 "arm_comparison_operator"
10605 [(match_operand:SI 4 "s_register_operand" "r,r")
10606 (match_operand:SI 5 "arm_add_operand" "rIL,rIL")])
10607 (match_operand:SI 1 "arm_not_operand" "0,?rIK")
10608 (match_operator:SI 7 "shift_operator"
10609 [(match_operand:SI 2 "s_register_operand" "r,r")
10610 (match_operand:SI 3 "arm_rhs_operand" "rM,rM")])))
10611 (clobber (reg:CC CC_REGNUM))]
10614 [(set_attr "conds" "clob")
10615 (set_attr "length" "8,12")
10616 (set_attr "type" "multiple")]
10619 (define_insn "*if_move_shift"
10620 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
10622 (match_operator 5 "arm_comparison_operator"
10623 [(match_operand 6 "cc_register" "") (const_int 0)])
10624 (match_operand:SI 1 "arm_not_operand" "0,?rI,K")
10625 (match_operator:SI 4 "shift_operator"
10626 [(match_operand:SI 2 "s_register_operand" "r,r,r")
10627 (match_operand:SI 3 "arm_rhs_operand" "rM,rM,rM")])))]
10631 mov%d5\\t%0, %1\;mov%D5\\t%0, %2%S4
10632 mvn%d5\\t%0, #%B1\;mov%D5\\t%0, %2%S4"
10633 [(set_attr "conds" "use")
10634 (set_attr "shift" "2")
10635 (set_attr "length" "4,8,8")
10636 (set_attr_alternative "type"
10637 [(if_then_else (match_operand 3 "const_int_operand" "")
10638 (const_string "mov_shift" )
10639 (const_string "mov_shift_reg"))
10640 (const_string "multiple")
10641 (const_string "multiple")])]
10644 (define_insn "*ifcompare_shift_shift"
10645 [(set (match_operand:SI 0 "s_register_operand" "=r")
10647 (match_operator 7 "arm_comparison_operator"
10648 [(match_operand:SI 5 "s_register_operand" "r")
10649 (match_operand:SI 6 "arm_add_operand" "rIL")])
10650 (match_operator:SI 8 "shift_operator"
10651 [(match_operand:SI 1 "s_register_operand" "r")
10652 (match_operand:SI 2 "arm_rhs_operand" "rM")])
10653 (match_operator:SI 9 "shift_operator"
10654 [(match_operand:SI 3 "s_register_operand" "r")
10655 (match_operand:SI 4 "arm_rhs_operand" "rM")])))
10656 (clobber (reg:CC CC_REGNUM))]
10659 [(set_attr "conds" "clob")
10660 (set_attr "length" "12")
10661 (set_attr "type" "multiple")]
10664 (define_insn "*if_shift_shift"
10665 [(set (match_operand:SI 0 "s_register_operand" "=r")
10667 (match_operator 5 "arm_comparison_operator"
10668 [(match_operand 8 "cc_register" "") (const_int 0)])
10669 (match_operator:SI 6 "shift_operator"
10670 [(match_operand:SI 1 "s_register_operand" "r")
10671 (match_operand:SI 2 "arm_rhs_operand" "rM")])
10672 (match_operator:SI 7 "shift_operator"
10673 [(match_operand:SI 3 "s_register_operand" "r")
10674 (match_operand:SI 4 "arm_rhs_operand" "rM")])))]
10676 "mov%d5\\t%0, %1%S6\;mov%D5\\t%0, %3%S7"
10677 [(set_attr "conds" "use")
10678 (set_attr "shift" "1")
10679 (set_attr "length" "8")
10680 (set (attr "type") (if_then_else
10681 (and (match_operand 2 "const_int_operand" "")
10682 (match_operand 4 "const_int_operand" ""))
10683 (const_string "mov_shift")
10684 (const_string "mov_shift_reg")))]
10687 (define_insn "*ifcompare_not_arith"
10688 [(set (match_operand:SI 0 "s_register_operand" "=r")
10690 (match_operator 6 "arm_comparison_operator"
10691 [(match_operand:SI 4 "s_register_operand" "r")
10692 (match_operand:SI 5 "arm_add_operand" "rIL")])
10693 (not:SI (match_operand:SI 1 "s_register_operand" "r"))
10694 (match_operator:SI 7 "shiftable_operator"
10695 [(match_operand:SI 2 "s_register_operand" "r")
10696 (match_operand:SI 3 "arm_rhs_operand" "rI")])))
10697 (clobber (reg:CC CC_REGNUM))]
10700 [(set_attr "conds" "clob")
10701 (set_attr "length" "12")
10702 (set_attr "type" "multiple")]
10705 (define_insn "*if_not_arith"
10706 [(set (match_operand:SI 0 "s_register_operand" "=r")
10708 (match_operator 5 "arm_comparison_operator"
10709 [(match_operand 4 "cc_register" "") (const_int 0)])
10710 (not:SI (match_operand:SI 1 "s_register_operand" "r"))
10711 (match_operator:SI 6 "shiftable_operator"
10712 [(match_operand:SI 2 "s_register_operand" "r")
10713 (match_operand:SI 3 "arm_rhs_operand" "rI")])))]
10715 "mvn%d5\\t%0, %1\;%I6%D5\\t%0, %2, %3"
10716 [(set_attr "conds" "use")
10717 (set_attr "type" "mvn_reg")
10718 (set_attr "length" "8")]
10721 (define_insn "*ifcompare_arith_not"
10722 [(set (match_operand:SI 0 "s_register_operand" "=r")
10724 (match_operator 6 "arm_comparison_operator"
10725 [(match_operand:SI 4 "s_register_operand" "r")
10726 (match_operand:SI 5 "arm_add_operand" "rIL")])
10727 (match_operator:SI 7 "shiftable_operator"
10728 [(match_operand:SI 2 "s_register_operand" "r")
10729 (match_operand:SI 3 "arm_rhs_operand" "rI")])
10730 (not:SI (match_operand:SI 1 "s_register_operand" "r"))))
10731 (clobber (reg:CC CC_REGNUM))]
10734 [(set_attr "conds" "clob")
10735 (set_attr "length" "12")
10736 (set_attr "type" "multiple")]
10739 (define_insn "*if_arith_not"
10740 [(set (match_operand:SI 0 "s_register_operand" "=r")
10742 (match_operator 5 "arm_comparison_operator"
10743 [(match_operand 4 "cc_register" "") (const_int 0)])
10744 (match_operator:SI 6 "shiftable_operator"
10745 [(match_operand:SI 2 "s_register_operand" "r")
10746 (match_operand:SI 3 "arm_rhs_operand" "rI")])
10747 (not:SI (match_operand:SI 1 "s_register_operand" "r"))))]
10749 "mvn%D5\\t%0, %1\;%I6%d5\\t%0, %2, %3"
10750 [(set_attr "conds" "use")
10751 (set_attr "type" "multiple")
10752 (set_attr "length" "8")]
10755 (define_insn "*ifcompare_neg_move"
10756 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
10758 (match_operator 5 "arm_comparison_operator"
10759 [(match_operand:SI 3 "s_register_operand" "r,r")
10760 (match_operand:SI 4 "arm_add_operand" "rIL,rIL")])
10761 (neg:SI (match_operand:SI 2 "s_register_operand" "r,r"))
10762 (match_operand:SI 1 "arm_not_operand" "0,?rIK")))
10763 (clobber (reg:CC CC_REGNUM))]
10766 [(set_attr "conds" "clob")
10767 (set_attr "length" "8,12")
10768 (set_attr "type" "multiple")]
10771 (define_insn_and_split "*if_neg_move"
10772 [(set (match_operand:SI 0 "s_register_operand" "=l,r")
10774 (match_operator 4 "arm_comparison_operator"
10775 [(match_operand 3 "cc_register" "") (const_int 0)])
10776 (neg:SI (match_operand:SI 2 "s_register_operand" "l,r"))
10777 (match_operand:SI 1 "s_register_operand" "0,0")))]
10780 "&& reload_completed"
10781 [(cond_exec (match_op_dup 4 [(match_dup 3) (const_int 0)])
10782 (set (match_dup 0) (neg:SI (match_dup 2))))]
10784 [(set_attr "conds" "use")
10785 (set_attr "length" "4")
10786 (set_attr "arch" "t2,32")
10787 (set_attr "enabled_for_short_it" "yes,no")
10788 (set_attr "type" "logic_shift_imm")]
10791 (define_insn "*ifcompare_move_neg"
10792 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
10794 (match_operator 5 "arm_comparison_operator"
10795 [(match_operand:SI 3 "s_register_operand" "r,r")
10796 (match_operand:SI 4 "arm_add_operand" "rIL,rIL")])
10797 (match_operand:SI 1 "arm_not_operand" "0,?rIK")
10798 (neg:SI (match_operand:SI 2 "s_register_operand" "r,r"))))
10799 (clobber (reg:CC CC_REGNUM))]
10802 [(set_attr "conds" "clob")
10803 (set_attr "length" "8,12")
10804 (set_attr "type" "multiple")]
10807 (define_insn_and_split "*if_move_neg"
10808 [(set (match_operand:SI 0 "s_register_operand" "=l,r")
10810 (match_operator 4 "arm_comparison_operator"
10811 [(match_operand 3 "cc_register" "") (const_int 0)])
10812 (match_operand:SI 1 "s_register_operand" "0,0")
10813 (neg:SI (match_operand:SI 2 "s_register_operand" "l,r"))))]
10816 "&& reload_completed"
10817 [(cond_exec (match_dup 5)
10818 (set (match_dup 0) (neg:SI (match_dup 2))))]
10820 machine_mode mode = GET_MODE (operands[3]);
10821 rtx_code rc = GET_CODE (operands[4]);
10823 if (mode == CCFPmode || mode == CCFPEmode)
10824 rc = reverse_condition_maybe_unordered (rc);
10826 rc = reverse_condition (rc);
10828 operands[5] = gen_rtx_fmt_ee (rc, VOIDmode, operands[3], const0_rtx);
10830 [(set_attr "conds" "use")
10831 (set_attr "length" "4")
10832 (set_attr "arch" "t2,32")
10833 (set_attr "enabled_for_short_it" "yes,no")
10834 (set_attr "type" "logic_shift_imm")]
10837 (define_insn "*arith_adjacentmem"
10838 [(set (match_operand:SI 0 "s_register_operand" "=r")
10839 (match_operator:SI 1 "shiftable_operator"
10840 [(match_operand:SI 2 "memory_operand" "m")
10841 (match_operand:SI 3 "memory_operand" "m")]))
10842 (clobber (match_scratch:SI 4 "=r"))]
10843 "TARGET_ARM && adjacent_mem_locations (operands[2], operands[3])"
10849 HOST_WIDE_INT val1 = 0, val2 = 0;
10851 if (REGNO (operands[0]) > REGNO (operands[4]))
10853 ldm[1] = operands[4];
10854 ldm[2] = operands[0];
10858 ldm[1] = operands[0];
10859 ldm[2] = operands[4];
10862 base_reg = XEXP (operands[2], 0);
10864 if (!REG_P (base_reg))
10866 val1 = INTVAL (XEXP (base_reg, 1));
10867 base_reg = XEXP (base_reg, 0);
10870 if (!REG_P (XEXP (operands[3], 0)))
10871 val2 = INTVAL (XEXP (XEXP (operands[3], 0), 1));
10873 arith[0] = operands[0];
10874 arith[3] = operands[1];
10888 if (val1 !=0 && val2 != 0)
10892 if (val1 == 4 || val2 == 4)
10893 /* Other val must be 8, since we know they are adjacent and neither
10895 output_asm_insn (\"ldmib%?\\t%0, {%1, %2}\", ldm);
10896 else if (const_ok_for_arm (val1) || const_ok_for_arm (-val1))
10898 ldm[0] = ops[0] = operands[4];
10900 ops[2] = GEN_INT (val1);
10901 output_add_immediate (ops);
10903 output_asm_insn (\"ldmia%?\\t%0, {%1, %2}\", ldm);
10905 output_asm_insn (\"ldmda%?\\t%0, {%1, %2}\", ldm);
10909 /* Offset is out of range for a single add, so use two ldr. */
10912 ops[2] = GEN_INT (val1);
10913 output_asm_insn (\"ldr%?\\t%0, [%1, %2]\", ops);
10915 ops[2] = GEN_INT (val2);
10916 output_asm_insn (\"ldr%?\\t%0, [%1, %2]\", ops);
10919 else if (val1 != 0)
10922 output_asm_insn (\"ldmda%?\\t%0, {%1, %2}\", ldm);
10924 output_asm_insn (\"ldmia%?\\t%0, {%1, %2}\", ldm);
10929 output_asm_insn (\"ldmia%?\\t%0, {%1, %2}\", ldm);
10931 output_asm_insn (\"ldmda%?\\t%0, {%1, %2}\", ldm);
10933 output_asm_insn (\"%I3%?\\t%0, %1, %2\", arith);
10936 [(set_attr "length" "12")
10937 (set_attr "predicable" "yes")
10938 (set_attr "type" "load_4")]
10941 ; This pattern is never tried by combine, so do it as a peephole
10944 [(set (match_operand:SI 0 "arm_general_register_operand" "")
10945 (match_operand:SI 1 "arm_general_register_operand" ""))
10946 (set (reg:CC CC_REGNUM)
10947 (compare:CC (match_dup 1) (const_int 0)))]
10949 [(parallel [(set (reg:CC CC_REGNUM) (compare:CC (match_dup 1) (const_int 0)))
10950 (set (match_dup 0) (match_dup 1))])]
10955 [(set (match_operand:SI 0 "s_register_operand" "")
10956 (and:SI (ge:SI (match_operand:SI 1 "s_register_operand" "")
10958 (neg:SI (match_operator:SI 2 "arm_comparison_operator"
10959 [(match_operand:SI 3 "s_register_operand" "")
10960 (match_operand:SI 4 "arm_rhs_operand" "")]))))
10961 (clobber (match_operand:SI 5 "s_register_operand" ""))]
10963 [(set (match_dup 5) (not:SI (ashiftrt:SI (match_dup 1) (const_int 31))))
10964 (set (match_dup 0) (and:SI (match_op_dup 2 [(match_dup 3) (match_dup 4)])
10969 ;; This split can be used because CC_Z mode implies that the following
10970 ;; branch will be an equality, or an unsigned inequality, so the sign
10971 ;; extension is not needed.
10974 [(set (reg:CC_Z CC_REGNUM)
10976 (ashift:SI (subreg:SI (match_operand:QI 0 "memory_operand" "") 0)
10978 (match_operand 1 "const_int_operand" "")))
10979 (clobber (match_scratch:SI 2 ""))]
10981 && ((UINTVAL (operands[1]))
10982 == ((UINTVAL (operands[1])) >> 24) << 24)"
10983 [(set (match_dup 2) (zero_extend:SI (match_dup 0)))
10984 (set (reg:CC CC_REGNUM) (compare:CC (match_dup 2) (match_dup 1)))]
10986 operands[1] = GEN_INT (((unsigned long) INTVAL (operands[1])) >> 24);
10989 ;; ??? Check the patterns above for Thumb-2 usefulness
10991 (define_expand "prologue"
10992 [(clobber (const_int 0))]
10995 arm_expand_prologue ();
10997 thumb1_expand_prologue ();
11002 (define_expand "epilogue"
11003 [(clobber (const_int 0))]
11006 if (crtl->calls_eh_return)
11007 emit_insn (gen_force_register_use (gen_rtx_REG (Pmode, 2)));
11010 thumb1_expand_epilogue ();
11011 emit_jump_insn (gen_rtx_UNSPEC_VOLATILE (VOIDmode,
11012 gen_rtvec (1, ret_rtx), VUNSPEC_EPILOGUE));
11014 else if (HAVE_return)
11016 /* HAVE_return is testing for USE_RETURN_INSN (FALSE). Hence,
11017 no need for explicit testing again. */
11018 emit_jump_insn (gen_return ());
11020 else if (TARGET_32BIT)
11022 arm_expand_epilogue (true);
11028 ;; Note - although unspec_volatile's USE all hard registers,
11029 ;; USEs are ignored after relaod has completed. Thus we need
11030 ;; to add an unspec of the link register to ensure that flow
11031 ;; does not think that it is unused by the sibcall branch that
11032 ;; will replace the standard function epilogue.
11033 (define_expand "sibcall_epilogue"
11034 [(parallel [(unspec:SI [(reg:SI LR_REGNUM)] UNSPEC_REGISTER_USE)
11035 (unspec_volatile [(return)] VUNSPEC_EPILOGUE)])]
11038 arm_expand_epilogue (false);
11043 (define_expand "eh_epilogue"
11044 [(use (match_operand:SI 0 "register_operand" ""))
11045 (use (match_operand:SI 1 "register_operand" ""))
11046 (use (match_operand:SI 2 "register_operand" ""))]
11050 cfun->machine->eh_epilogue_sp_ofs = operands[1];
11051 if (!REG_P (operands[2]) || REGNO (operands[2]) != 2)
11053 rtx ra = gen_rtx_REG (Pmode, 2);
11055 emit_move_insn (ra, operands[2]);
11058 /* This is a hack -- we may have crystalized the function type too
11060 cfun->machine->func_type = 0;
11064 ;; This split is only used during output to reduce the number of patterns
11065 ;; that need assembler instructions adding to them. We allowed the setting
11066 ;; of the conditions to be implicit during rtl generation so that
11067 ;; the conditional compare patterns would work. However this conflicts to
11068 ;; some extent with the conditional data operations, so we have to split them
11071 ;; ??? Need to audit these splitters for Thumb-2. Why isn't normal
11072 ;; conditional execution sufficient?
11075 [(set (match_operand:SI 0 "s_register_operand" "")
11076 (if_then_else:SI (match_operator 1 "arm_comparison_operator"
11077 [(match_operand 2 "" "") (match_operand 3 "" "")])
11079 (match_operand 4 "" "")))
11080 (clobber (reg:CC CC_REGNUM))]
11081 "TARGET_ARM && reload_completed"
11082 [(set (match_dup 5) (match_dup 6))
11083 (cond_exec (match_dup 7)
11084 (set (match_dup 0) (match_dup 4)))]
11087 machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[1]),
11088 operands[2], operands[3]);
11089 enum rtx_code rc = GET_CODE (operands[1]);
11091 operands[5] = gen_rtx_REG (mode, CC_REGNUM);
11092 operands[6] = gen_rtx_COMPARE (mode, operands[2], operands[3]);
11093 if (mode == CCFPmode || mode == CCFPEmode)
11094 rc = reverse_condition_maybe_unordered (rc);
11096 rc = reverse_condition (rc);
11098 operands[7] = gen_rtx_fmt_ee (rc, VOIDmode, operands[5], const0_rtx);
11103 [(set (match_operand:SI 0 "s_register_operand" "")
11104 (if_then_else:SI (match_operator 1 "arm_comparison_operator"
11105 [(match_operand 2 "" "") (match_operand 3 "" "")])
11106 (match_operand 4 "" "")
11108 (clobber (reg:CC CC_REGNUM))]
11109 "TARGET_ARM && reload_completed"
11110 [(set (match_dup 5) (match_dup 6))
11111 (cond_exec (match_op_dup 1 [(match_dup 5) (const_int 0)])
11112 (set (match_dup 0) (match_dup 4)))]
11115 machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[1]),
11116 operands[2], operands[3]);
11118 operands[5] = gen_rtx_REG (mode, CC_REGNUM);
11119 operands[6] = gen_rtx_COMPARE (mode, operands[2], operands[3]);
11124 [(set (match_operand:SI 0 "s_register_operand" "")
11125 (if_then_else:SI (match_operator 1 "arm_comparison_operator"
11126 [(match_operand 2 "" "") (match_operand 3 "" "")])
11127 (match_operand 4 "" "")
11128 (match_operand 5 "" "")))
11129 (clobber (reg:CC CC_REGNUM))]
11130 "TARGET_ARM && reload_completed"
11131 [(set (match_dup 6) (match_dup 7))
11132 (cond_exec (match_op_dup 1 [(match_dup 6) (const_int 0)])
11133 (set (match_dup 0) (match_dup 4)))
11134 (cond_exec (match_dup 8)
11135 (set (match_dup 0) (match_dup 5)))]
11138 machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[1]),
11139 operands[2], operands[3]);
11140 enum rtx_code rc = GET_CODE (operands[1]);
11142 operands[6] = gen_rtx_REG (mode, CC_REGNUM);
11143 operands[7] = gen_rtx_COMPARE (mode, operands[2], operands[3]);
11144 if (mode == CCFPmode || mode == CCFPEmode)
11145 rc = reverse_condition_maybe_unordered (rc);
11147 rc = reverse_condition (rc);
11149 operands[8] = gen_rtx_fmt_ee (rc, VOIDmode, operands[6], const0_rtx);
11154 [(set (match_operand:SI 0 "s_register_operand" "")
11155 (if_then_else:SI (match_operator 1 "arm_comparison_operator"
11156 [(match_operand:SI 2 "s_register_operand" "")
11157 (match_operand:SI 3 "arm_add_operand" "")])
11158 (match_operand:SI 4 "arm_rhs_operand" "")
11160 (match_operand:SI 5 "s_register_operand" ""))))
11161 (clobber (reg:CC CC_REGNUM))]
11162 "TARGET_ARM && reload_completed"
11163 [(set (match_dup 6) (match_dup 7))
11164 (cond_exec (match_op_dup 1 [(match_dup 6) (const_int 0)])
11165 (set (match_dup 0) (match_dup 4)))
11166 (cond_exec (match_dup 8)
11167 (set (match_dup 0) (not:SI (match_dup 5))))]
11170 machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[1]),
11171 operands[2], operands[3]);
11172 enum rtx_code rc = GET_CODE (operands[1]);
11174 operands[6] = gen_rtx_REG (mode, CC_REGNUM);
11175 operands[7] = gen_rtx_COMPARE (mode, operands[2], operands[3]);
11176 if (mode == CCFPmode || mode == CCFPEmode)
11177 rc = reverse_condition_maybe_unordered (rc);
11179 rc = reverse_condition (rc);
11181 operands[8] = gen_rtx_fmt_ee (rc, VOIDmode, operands[6], const0_rtx);
11185 (define_insn "*cond_move_not"
11186 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
11187 (if_then_else:SI (match_operator 4 "arm_comparison_operator"
11188 [(match_operand 3 "cc_register" "") (const_int 0)])
11189 (match_operand:SI 1 "arm_rhs_operand" "0,?rI")
11191 (match_operand:SI 2 "s_register_operand" "r,r"))))]
11195 mov%d4\\t%0, %1\;mvn%D4\\t%0, %2"
11196 [(set_attr "conds" "use")
11197 (set_attr "type" "mvn_reg,multiple")
11198 (set_attr "length" "4,8")]
11201 ;; The next two patterns occur when an AND operation is followed by a
11202 ;; scc insn sequence
11204 (define_insn "*sign_extract_onebit"
11205 [(set (match_operand:SI 0 "s_register_operand" "=r")
11206 (sign_extract:SI (match_operand:SI 1 "s_register_operand" "r")
11208 (match_operand:SI 2 "const_int_operand" "n")))
11209 (clobber (reg:CC CC_REGNUM))]
11212 operands[2] = GEN_INT (1 << INTVAL (operands[2]));
11213 output_asm_insn (\"ands\\t%0, %1, %2\", operands);
11214 return \"mvnne\\t%0, #0\";
11216 [(set_attr "conds" "clob")
11217 (set_attr "length" "8")
11218 (set_attr "type" "multiple")]
11221 (define_insn "*not_signextract_onebit"
11222 [(set (match_operand:SI 0 "s_register_operand" "=r")
11224 (sign_extract:SI (match_operand:SI 1 "s_register_operand" "r")
11226 (match_operand:SI 2 "const_int_operand" "n"))))
11227 (clobber (reg:CC CC_REGNUM))]
11230 operands[2] = GEN_INT (1 << INTVAL (operands[2]));
11231 output_asm_insn (\"tst\\t%1, %2\", operands);
11232 output_asm_insn (\"mvneq\\t%0, #0\", operands);
11233 return \"movne\\t%0, #0\";
11235 [(set_attr "conds" "clob")
11236 (set_attr "length" "12")
11237 (set_attr "type" "multiple")]
11239 ;; ??? The above patterns need auditing for Thumb-2
11241 ;; Push multiple registers to the stack. Registers are in parallel (use ...)
11242 ;; expressions. For simplicity, the first register is also in the unspec
11244 ;; To avoid the usage of GNU extension, the length attribute is computed
11245 ;; in a C function arm_attr_length_push_multi.
11246 (define_insn "*push_multi"
11247 [(match_parallel 2 "multi_register_push"
11248 [(set (match_operand:BLK 0 "push_mult_memory_operand" "")
11249 (unspec:BLK [(match_operand:SI 1 "s_register_operand" "")]
11250 UNSPEC_PUSH_MULT))])]
11254 int num_saves = XVECLEN (operands[2], 0);
11256 /* For the StrongARM at least it is faster to
11257 use STR to store only a single register.
11258 In Thumb mode always use push, and the assembler will pick
11259 something appropriate. */
11260 if (num_saves == 1 && TARGET_ARM)
11261 output_asm_insn (\"str%?\\t%1, [%m0, #-4]!\", operands);
11268 strcpy (pattern, \"push%?\\t{%1\");
11270 strcpy (pattern, \"push\\t{%1\");
11272 for (i = 1; i < num_saves; i++)
11274 strcat (pattern, \", %|\");
11276 reg_names[REGNO (XEXP (XVECEXP (operands[2], 0, i), 0))]);
11279 strcat (pattern, \"}\");
11280 output_asm_insn (pattern, operands);
11285 [(set_attr "type" "store_16")
11286 (set (attr "length")
11287 (symbol_ref "arm_attr_length_push_multi (operands[2], operands[1])"))]
11290 (define_insn "stack_tie"
11291 [(set (mem:BLK (scratch))
11292 (unspec:BLK [(match_operand:SI 0 "s_register_operand" "rk")
11293 (match_operand:SI 1 "s_register_operand" "rk")]
11297 [(set_attr "length" "0")
11298 (set_attr "type" "block")]
11301 ;; Pop (as used in epilogue RTL)
11303 (define_insn "*load_multiple_with_writeback"
11304 [(match_parallel 0 "load_multiple_operation"
11305 [(set (match_operand:SI 1 "s_register_operand" "+rk")
11306 (plus:SI (match_dup 1)
11307 (match_operand:SI 2 "const_int_I_operand" "I")))
11308 (set (match_operand:SI 3 "s_register_operand" "=rk")
11309 (mem:SI (match_dup 1)))
11311 "TARGET_32BIT && (reload_in_progress || reload_completed)"
11314 arm_output_multireg_pop (operands, /*return_pc=*/false,
11315 /*cond=*/const_true_rtx,
11321 [(set_attr "type" "load_16")
11322 (set_attr "predicable" "yes")
11323 (set (attr "length")
11324 (symbol_ref "arm_attr_length_pop_multi (operands,
11325 /*return_pc=*/false,
11326 /*write_back_p=*/true)"))]
11329 ;; Pop with return (as used in epilogue RTL)
11331 ;; This instruction is generated when the registers are popped at the end of
11332 ;; epilogue. Here, instead of popping the value into LR and then generating
11333 ;; jump to LR, value is popped into PC directly. Hence, the pattern is combined
11335 (define_insn "*pop_multiple_with_writeback_and_return"
11336 [(match_parallel 0 "pop_multiple_return"
11338 (set (match_operand:SI 1 "s_register_operand" "+rk")
11339 (plus:SI (match_dup 1)
11340 (match_operand:SI 2 "const_int_I_operand" "I")))
11341 (set (match_operand:SI 3 "s_register_operand" "=rk")
11342 (mem:SI (match_dup 1)))
11344 "TARGET_32BIT && (reload_in_progress || reload_completed)"
11347 arm_output_multireg_pop (operands, /*return_pc=*/true,
11348 /*cond=*/const_true_rtx,
11354 [(set_attr "type" "load_16")
11355 (set_attr "predicable" "yes")
11356 (set (attr "length")
11357 (symbol_ref "arm_attr_length_pop_multi (operands, /*return_pc=*/true,
11358 /*write_back_p=*/true)"))]
11361 (define_insn "*pop_multiple_with_return"
11362 [(match_parallel 0 "pop_multiple_return"
11364 (set (match_operand:SI 2 "s_register_operand" "=rk")
11365 (mem:SI (match_operand:SI 1 "s_register_operand" "rk")))
11367 "TARGET_32BIT && (reload_in_progress || reload_completed)"
11370 arm_output_multireg_pop (operands, /*return_pc=*/true,
11371 /*cond=*/const_true_rtx,
11377 [(set_attr "type" "load_16")
11378 (set_attr "predicable" "yes")
11379 (set (attr "length")
11380 (symbol_ref "arm_attr_length_pop_multi (operands, /*return_pc=*/true,
11381 /*write_back_p=*/false)"))]
11384 ;; Load into PC and return
11385 (define_insn "*ldr_with_return"
11387 (set (reg:SI PC_REGNUM)
11388 (mem:SI (post_inc:SI (match_operand:SI 0 "s_register_operand" "+rk"))))]
11389 "TARGET_32BIT && (reload_in_progress || reload_completed)"
11390 "ldr%?\t%|pc, [%0], #4"
11391 [(set_attr "type" "load_4")
11392 (set_attr "predicable" "yes")]
11394 ;; Pop for floating point registers (as used in epilogue RTL)
11395 (define_insn "*vfp_pop_multiple_with_writeback"
11396 [(match_parallel 0 "pop_multiple_fp"
11397 [(set (match_operand:SI 1 "s_register_operand" "+rk")
11398 (plus:SI (match_dup 1)
11399 (match_operand:SI 2 "const_int_I_operand" "I")))
11400 (set (match_operand:DF 3 "vfp_hard_register_operand" "")
11401 (mem:DF (match_dup 1)))])]
11402 "TARGET_32BIT && TARGET_HARD_FLOAT"
11405 int num_regs = XVECLEN (operands[0], 0);
11408 strcpy (pattern, \"vldm\\t\");
11409 strcat (pattern, reg_names[REGNO (SET_DEST (XVECEXP (operands[0], 0, 0)))]);
11410 strcat (pattern, \"!, {\");
11411 op_list[0] = XEXP (XVECEXP (operands[0], 0, 1), 0);
11412 strcat (pattern, \"%P0\");
11413 if ((num_regs - 1) > 1)
11415 strcat (pattern, \"-%P1\");
11416 op_list [1] = XEXP (XVECEXP (operands[0], 0, num_regs - 1), 0);
11419 strcat (pattern, \"}\");
11420 output_asm_insn (pattern, op_list);
11424 [(set_attr "type" "load_16")
11425 (set_attr "conds" "unconditional")
11426 (set_attr "predicable" "no")]
11429 ;; Special patterns for dealing with the constant pool
11431 (define_insn "align_4"
11432 [(unspec_volatile [(const_int 0)] VUNSPEC_ALIGN)]
11435 assemble_align (32);
11438 [(set_attr "type" "no_insn")]
11441 (define_insn "align_8"
11442 [(unspec_volatile [(const_int 0)] VUNSPEC_ALIGN8)]
11445 assemble_align (64);
11448 [(set_attr "type" "no_insn")]
11451 (define_insn "consttable_end"
11452 [(unspec_volatile [(const_int 0)] VUNSPEC_POOL_END)]
11455 making_const_table = FALSE;
11458 [(set_attr "type" "no_insn")]
11461 (define_insn "consttable_1"
11462 [(unspec_volatile [(match_operand 0 "" "")] VUNSPEC_POOL_1)]
11465 making_const_table = TRUE;
11466 assemble_integer (operands[0], 1, BITS_PER_WORD, 1);
11467 assemble_zeros (3);
11470 [(set_attr "length" "4")
11471 (set_attr "type" "no_insn")]
11474 (define_insn "consttable_2"
11475 [(unspec_volatile [(match_operand 0 "" "")] VUNSPEC_POOL_2)]
11479 rtx x = operands[0];
11480 making_const_table = TRUE;
11481 switch (GET_MODE_CLASS (GET_MODE (x)))
11484 arm_emit_fp16_const (x);
11487 assemble_integer (operands[0], 2, BITS_PER_WORD, 1);
11488 assemble_zeros (2);
11493 [(set_attr "length" "4")
11494 (set_attr "type" "no_insn")]
11497 (define_insn "consttable_4"
11498 [(unspec_volatile [(match_operand 0 "" "")] VUNSPEC_POOL_4)]
11502 rtx x = operands[0];
11503 making_const_table = TRUE;
11504 scalar_float_mode float_mode;
11505 if (is_a <scalar_float_mode> (GET_MODE (x), &float_mode))
11506 assemble_real (*CONST_DOUBLE_REAL_VALUE (x), float_mode, BITS_PER_WORD);
11509 /* XXX: Sometimes gcc does something really dumb and ends up with
11510 a HIGH in a constant pool entry, usually because it's trying to
11511 load into a VFP register. We know this will always be used in
11512 combination with a LO_SUM which ignores the high bits, so just
11513 strip off the HIGH. */
11514 if (GET_CODE (x) == HIGH)
11516 assemble_integer (x, 4, BITS_PER_WORD, 1);
11517 mark_symbol_refs_as_used (x);
11521 [(set_attr "length" "4")
11522 (set_attr "type" "no_insn")]
11525 (define_insn "consttable_8"
11526 [(unspec_volatile [(match_operand 0 "" "")] VUNSPEC_POOL_8)]
11530 making_const_table = TRUE;
11531 scalar_float_mode float_mode;
11532 if (is_a <scalar_float_mode> (GET_MODE (operands[0]), &float_mode))
11533 assemble_real (*CONST_DOUBLE_REAL_VALUE (operands[0]),
11534 float_mode, BITS_PER_WORD);
11536 assemble_integer (operands[0], 8, BITS_PER_WORD, 1);
11539 [(set_attr "length" "8")
11540 (set_attr "type" "no_insn")]
11543 (define_insn "consttable_16"
11544 [(unspec_volatile [(match_operand 0 "" "")] VUNSPEC_POOL_16)]
11548 making_const_table = TRUE;
11549 scalar_float_mode float_mode;
11550 if (is_a <scalar_float_mode> (GET_MODE (operands[0]), &float_mode))
11551 assemble_real (*CONST_DOUBLE_REAL_VALUE (operands[0]),
11552 float_mode, BITS_PER_WORD);
11554 assemble_integer (operands[0], 16, BITS_PER_WORD, 1);
11557 [(set_attr "length" "16")
11558 (set_attr "type" "no_insn")]
11561 ;; V5 Instructions,
11563 (define_insn "clzsi2"
11564 [(set (match_operand:SI 0 "s_register_operand" "=r")
11565 (clz:SI (match_operand:SI 1 "s_register_operand" "r")))]
11566 "TARGET_32BIT && arm_arch5t"
11568 [(set_attr "predicable" "yes")
11569 (set_attr "type" "clz")])
11571 (define_insn "rbitsi2"
11572 [(set (match_operand:SI 0 "s_register_operand" "=r")
11573 (unspec:SI [(match_operand:SI 1 "s_register_operand" "r")] UNSPEC_RBIT))]
11574 "TARGET_32BIT && arm_arch_thumb2"
11576 [(set_attr "predicable" "yes")
11577 (set_attr "type" "clz")])
11579 ;; Keep this as a CTZ expression until after reload and then split
11580 ;; into RBIT + CLZ. Since RBIT is represented as an UNSPEC it is unlikely
11581 ;; to fold with any other expression.
11583 (define_insn_and_split "ctzsi2"
11584 [(set (match_operand:SI 0 "s_register_operand" "=r")
11585 (ctz:SI (match_operand:SI 1 "s_register_operand" "r")))]
11586 "TARGET_32BIT && arm_arch_thumb2"
11588 "&& reload_completed"
11591 emit_insn (gen_rbitsi2 (operands[0], operands[1]));
11592 emit_insn (gen_clzsi2 (operands[0], operands[0]));
11596 ;; V5E instructions.
11598 (define_insn "prefetch"
11599 [(prefetch (match_operand:SI 0 "address_operand" "p")
11600 (match_operand:SI 1 "" "")
11601 (match_operand:SI 2 "" ""))]
11602 "TARGET_32BIT && arm_arch5te"
11604 [(set_attr "type" "load_4")]
11607 ;; General predication pattern
11610 [(match_operator 0 "arm_comparison_operator"
11611 [(match_operand 1 "cc_register" "")
11614 && (!TARGET_NO_VOLATILE_CE || !volatile_refs_p (PATTERN (insn)))"
11616 [(set_attr "predicated" "yes")]
11619 (define_insn "force_register_use"
11620 [(unspec:SI [(match_operand:SI 0 "register_operand" "")] UNSPEC_REGISTER_USE)]
11623 [(set_attr "length" "0")
11624 (set_attr "type" "no_insn")]
11628 ;; Patterns for exception handling
11630 (define_expand "eh_return"
11631 [(use (match_operand 0 "general_operand" ""))]
11636 emit_insn (gen_arm_eh_return (operands[0]));
11638 emit_insn (gen_thumb_eh_return (operands[0]));
11643 ;; We can't expand this before we know where the link register is stored.
11644 (define_insn_and_split "arm_eh_return"
11645 [(unspec_volatile [(match_operand:SI 0 "s_register_operand" "r")]
11647 (clobber (match_scratch:SI 1 "=&r"))]
11650 "&& reload_completed"
11654 arm_set_return_address (operands[0], operands[1]);
11662 (define_insn "load_tp_hard"
11663 [(set (match_operand:SI 0 "register_operand" "=r")
11664 (unspec:SI [(const_int 0)] UNSPEC_TLS))]
11666 "mrc%?\\tp15, 0, %0, c13, c0, 3\\t@ load_tp_hard"
11667 [(set_attr "predicable" "yes")
11668 (set_attr "type" "mrs")]
11671 ;; Doesn't clobber R1-R3. Must use r0 for the first operand.
11672 (define_insn "load_tp_soft"
11673 [(set (reg:SI 0) (unspec:SI [(const_int 0)] UNSPEC_TLS))
11674 (clobber (reg:SI LR_REGNUM))
11675 (clobber (reg:SI IP_REGNUM))
11676 (clobber (reg:CC CC_REGNUM))]
11678 "bl\\t__aeabi_read_tp\\t@ load_tp_soft"
11679 [(set_attr "conds" "clob")
11680 (set_attr "type" "branch")]
11683 ;; tls descriptor call
11684 (define_insn "tlscall"
11685 [(set (reg:SI R0_REGNUM)
11686 (unspec:SI [(reg:SI R0_REGNUM)
11687 (match_operand:SI 0 "" "X")
11688 (match_operand 1 "" "")] UNSPEC_TLS))
11689 (clobber (reg:SI R1_REGNUM))
11690 (clobber (reg:SI LR_REGNUM))
11691 (clobber (reg:SI CC_REGNUM))]
11694 targetm.asm_out.internal_label (asm_out_file, "LPIC",
11695 INTVAL (operands[1]));
11696 return "bl\\t%c0(tlscall)";
11698 [(set_attr "conds" "clob")
11699 (set_attr "length" "4")
11700 (set_attr "type" "branch")]
11703 ;; For thread pointer builtin
11704 (define_expand "get_thread_pointersi"
11705 [(match_operand:SI 0 "s_register_operand" "=r")]
11709 arm_load_tp (operands[0]);
11715 ;; We only care about the lower 16 bits of the constant
11716 ;; being inserted into the upper 16 bits of the register.
11717 (define_insn "*arm_movtas_ze"
11718 [(set (zero_extract:SI (match_operand:SI 0 "s_register_operand" "+r,r")
11721 (match_operand:SI 1 "const_int_operand" ""))]
11726 [(set_attr "arch" "32,v8mb")
11727 (set_attr "predicable" "yes")
11728 (set_attr "length" "4")
11729 (set_attr "type" "alu_sreg")]
11732 (define_insn "*arm_rev"
11733 [(set (match_operand:SI 0 "s_register_operand" "=l,l,r")
11734 (bswap:SI (match_operand:SI 1 "s_register_operand" "l,l,r")))]
11740 [(set_attr "arch" "t1,t2,32")
11741 (set_attr "length" "2,2,4")
11742 (set_attr "predicable" "no,yes,yes")
11743 (set_attr "type" "rev")]
11746 (define_expand "arm_legacy_rev"
11747 [(set (match_operand:SI 2 "s_register_operand" "")
11748 (xor:SI (rotatert:SI (match_operand:SI 1 "s_register_operand" "")
11752 (lshiftrt:SI (match_dup 2)
11754 (set (match_operand:SI 3 "s_register_operand" "")
11755 (rotatert:SI (match_dup 1)
11758 (and:SI (match_dup 2)
11759 (const_int -65281)))
11760 (set (match_operand:SI 0 "s_register_operand" "")
11761 (xor:SI (match_dup 3)
11767 ;; Reuse temporaries to keep register pressure down.
11768 (define_expand "thumb_legacy_rev"
11769 [(set (match_operand:SI 2 "s_register_operand" "")
11770 (ashift:SI (match_operand:SI 1 "s_register_operand" "")
11772 (set (match_operand:SI 3 "s_register_operand" "")
11773 (lshiftrt:SI (match_dup 1)
11776 (ior:SI (match_dup 3)
11778 (set (match_operand:SI 4 "s_register_operand" "")
11780 (set (match_operand:SI 5 "s_register_operand" "")
11781 (rotatert:SI (match_dup 1)
11784 (ashift:SI (match_dup 5)
11787 (lshiftrt:SI (match_dup 5)
11790 (ior:SI (match_dup 5)
11793 (rotatert:SI (match_dup 5)
11795 (set (match_operand:SI 0 "s_register_operand" "")
11796 (ior:SI (match_dup 5)
11802 ;; ARM-specific expansion of signed mod by power of 2
11803 ;; using conditional negate.
11804 ;; For r0 % n where n is a power of 2 produce:
11806 ;; and r0, r0, #(n - 1)
11807 ;; and r1, r1, #(n - 1)
11808 ;; rsbpl r0, r1, #0
11810 (define_expand "modsi3"
11811 [(match_operand:SI 0 "register_operand" "")
11812 (match_operand:SI 1 "register_operand" "")
11813 (match_operand:SI 2 "const_int_operand" "")]
11816 HOST_WIDE_INT val = INTVAL (operands[2]);
11819 || exact_log2 (val) <= 0)
11822 rtx mask = GEN_INT (val - 1);
11824 /* In the special case of x0 % 2 we can do the even shorter:
11827 rsblt r0, r0, #0. */
11831 rtx cc_reg = arm_gen_compare_reg (LT,
11832 operands[1], const0_rtx, NULL_RTX);
11833 rtx cond = gen_rtx_LT (SImode, cc_reg, const0_rtx);
11834 rtx masked = gen_reg_rtx (SImode);
11836 emit_insn (gen_andsi3 (masked, operands[1], mask));
11837 emit_move_insn (operands[0],
11838 gen_rtx_IF_THEN_ELSE (SImode, cond,
11839 gen_rtx_NEG (SImode,
11845 rtx neg_op = gen_reg_rtx (SImode);
11846 rtx_insn *insn = emit_insn (gen_subsi3_compare0 (neg_op, const0_rtx,
11849 /* Extract the condition register and mode. */
11850 rtx cmp = XVECEXP (PATTERN (insn), 0, 0);
11851 rtx cc_reg = SET_DEST (cmp);
11852 rtx cond = gen_rtx_GE (SImode, cc_reg, const0_rtx);
11854 emit_insn (gen_andsi3 (operands[0], operands[1], mask));
11856 rtx masked_neg = gen_reg_rtx (SImode);
11857 emit_insn (gen_andsi3 (masked_neg, neg_op, mask));
11859 /* We want a conditional negate here, but emitting COND_EXEC rtxes
11860 during expand does not always work. Do an IF_THEN_ELSE instead. */
11861 emit_move_insn (operands[0],
11862 gen_rtx_IF_THEN_ELSE (SImode, cond,
11863 gen_rtx_NEG (SImode, masked_neg),
11871 (define_expand "bswapsi2"
11872 [(set (match_operand:SI 0 "s_register_operand" "=r")
11873 (bswap:SI (match_operand:SI 1 "s_register_operand" "r")))]
11874 "TARGET_EITHER && (arm_arch6 || !optimize_size)"
11878 rtx op2 = gen_reg_rtx (SImode);
11879 rtx op3 = gen_reg_rtx (SImode);
11883 rtx op4 = gen_reg_rtx (SImode);
11884 rtx op5 = gen_reg_rtx (SImode);
11886 emit_insn (gen_thumb_legacy_rev (operands[0], operands[1],
11887 op2, op3, op4, op5));
11891 emit_insn (gen_arm_legacy_rev (operands[0], operands[1],
11900 ;; bswap16 patterns: use revsh and rev16 instructions for the signed
11901 ;; and unsigned variants, respectively. For rev16, expose
11902 ;; byte-swapping in the lower 16 bits only.
11903 (define_insn "*arm_revsh"
11904 [(set (match_operand:SI 0 "s_register_operand" "=l,l,r")
11905 (sign_extend:SI (bswap:HI (match_operand:HI 1 "s_register_operand" "l,l,r"))))]
11911 [(set_attr "arch" "t1,t2,32")
11912 (set_attr "length" "2,2,4")
11913 (set_attr "type" "rev")]
11916 (define_insn "*arm_rev16"
11917 [(set (match_operand:HI 0 "s_register_operand" "=l,l,r")
11918 (bswap:HI (match_operand:HI 1 "s_register_operand" "l,l,r")))]
11924 [(set_attr "arch" "t1,t2,32")
11925 (set_attr "length" "2,2,4")
11926 (set_attr "type" "rev")]
11929 ;; There are no canonicalisation rules for the position of the lshiftrt, ashift
11930 ;; operations within an IOR/AND RTX, therefore we have two patterns matching
11931 ;; each valid permutation.
11933 (define_insn "arm_rev16si2"
11934 [(set (match_operand:SI 0 "register_operand" "=l,l,r")
11935 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "l,l,r")
11937 (match_operand:SI 3 "const_int_operand" "n,n,n"))
11938 (and:SI (lshiftrt:SI (match_dup 1)
11940 (match_operand:SI 2 "const_int_operand" "n,n,n"))))]
11942 && aarch_rev16_shleft_mask_imm_p (operands[3], SImode)
11943 && aarch_rev16_shright_mask_imm_p (operands[2], SImode)"
11945 [(set_attr "arch" "t1,t2,32")
11946 (set_attr "length" "2,2,4")
11947 (set_attr "type" "rev")]
11950 (define_insn "arm_rev16si2_alt"
11951 [(set (match_operand:SI 0 "register_operand" "=l,l,r")
11952 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "l,l,r")
11954 (match_operand:SI 2 "const_int_operand" "n,n,n"))
11955 (and:SI (ashift:SI (match_dup 1)
11957 (match_operand:SI 3 "const_int_operand" "n,n,n"))))]
11959 && aarch_rev16_shleft_mask_imm_p (operands[3], SImode)
11960 && aarch_rev16_shright_mask_imm_p (operands[2], SImode)"
11962 [(set_attr "arch" "t1,t2,32")
11963 (set_attr "length" "2,2,4")
11964 (set_attr "type" "rev")]
11967 (define_expand "bswaphi2"
11968 [(set (match_operand:HI 0 "s_register_operand" "=r")
11969 (bswap:HI (match_operand:HI 1 "s_register_operand" "r")))]
11974 ;; Patterns for LDRD/STRD in Thumb2 mode
11976 (define_insn "*thumb2_ldrd"
11977 [(set (match_operand:SI 0 "s_register_operand" "=r")
11978 (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk")
11979 (match_operand:SI 2 "ldrd_strd_offset_operand" "Do"))))
11980 (set (match_operand:SI 3 "s_register_operand" "=r")
11981 (mem:SI (plus:SI (match_dup 1)
11982 (match_operand:SI 4 "const_int_operand" ""))))]
11983 "TARGET_LDRD && TARGET_THUMB2 && reload_completed
11984 && ((INTVAL (operands[2]) + 4) == INTVAL (operands[4]))
11985 && (operands_ok_ldrd_strd (operands[0], operands[3],
11986 operands[1], INTVAL (operands[2]),
11988 "ldrd%?\t%0, %3, [%1, %2]"
11989 [(set_attr "type" "load_8")
11990 (set_attr "predicable" "yes")])
11992 (define_insn "*thumb2_ldrd_base"
11993 [(set (match_operand:SI 0 "s_register_operand" "=r")
11994 (mem:SI (match_operand:SI 1 "s_register_operand" "rk")))
11995 (set (match_operand:SI 2 "s_register_operand" "=r")
11996 (mem:SI (plus:SI (match_dup 1)
11998 "TARGET_LDRD && TARGET_THUMB2 && reload_completed
11999 && (operands_ok_ldrd_strd (operands[0], operands[2],
12000 operands[1], 0, false, true))"
12001 "ldrd%?\t%0, %2, [%1]"
12002 [(set_attr "type" "load_8")
12003 (set_attr "predicable" "yes")])
12005 (define_insn "*thumb2_ldrd_base_neg"
12006 [(set (match_operand:SI 0 "s_register_operand" "=r")
12007 (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk")
12009 (set (match_operand:SI 2 "s_register_operand" "=r")
12010 (mem:SI (match_dup 1)))]
12011 "TARGET_LDRD && TARGET_THUMB2 && reload_completed
12012 && (operands_ok_ldrd_strd (operands[0], operands[2],
12013 operands[1], -4, false, true))"
12014 "ldrd%?\t%0, %2, [%1, #-4]"
12015 [(set_attr "type" "load_8")
12016 (set_attr "predicable" "yes")])
12018 (define_insn "*thumb2_strd"
12019 [(set (mem:SI (plus:SI (match_operand:SI 0 "s_register_operand" "rk")
12020 (match_operand:SI 1 "ldrd_strd_offset_operand" "Do")))
12021 (match_operand:SI 2 "s_register_operand" "r"))
12022 (set (mem:SI (plus:SI (match_dup 0)
12023 (match_operand:SI 3 "const_int_operand" "")))
12024 (match_operand:SI 4 "s_register_operand" "r"))]
12025 "TARGET_LDRD && TARGET_THUMB2 && reload_completed
12026 && ((INTVAL (operands[1]) + 4) == INTVAL (operands[3]))
12027 && (operands_ok_ldrd_strd (operands[2], operands[4],
12028 operands[0], INTVAL (operands[1]),
12030 "strd%?\t%2, %4, [%0, %1]"
12031 [(set_attr "type" "store_8")
12032 (set_attr "predicable" "yes")])
12034 (define_insn "*thumb2_strd_base"
12035 [(set (mem:SI (match_operand:SI 0 "s_register_operand" "rk"))
12036 (match_operand:SI 1 "s_register_operand" "r"))
12037 (set (mem:SI (plus:SI (match_dup 0)
12039 (match_operand:SI 2 "s_register_operand" "r"))]
12040 "TARGET_LDRD && TARGET_THUMB2 && reload_completed
12041 && (operands_ok_ldrd_strd (operands[1], operands[2],
12042 operands[0], 0, false, false))"
12043 "strd%?\t%1, %2, [%0]"
12044 [(set_attr "type" "store_8")
12045 (set_attr "predicable" "yes")])
12047 (define_insn "*thumb2_strd_base_neg"
12048 [(set (mem:SI (plus:SI (match_operand:SI 0 "s_register_operand" "rk")
12050 (match_operand:SI 1 "s_register_operand" "r"))
12051 (set (mem:SI (match_dup 0))
12052 (match_operand:SI 2 "s_register_operand" "r"))]
12053 "TARGET_LDRD && TARGET_THUMB2 && reload_completed
12054 && (operands_ok_ldrd_strd (operands[1], operands[2],
12055 operands[0], -4, false, false))"
12056 "strd%?\t%1, %2, [%0, #-4]"
12057 [(set_attr "type" "store_8")
12058 (set_attr "predicable" "yes")])
12060 ;; ARMv8 CRC32 instructions.
12061 (define_insn "<crc_variant>"
12062 [(set (match_operand:SI 0 "s_register_operand" "=r")
12063 (unspec:SI [(match_operand:SI 1 "s_register_operand" "r")
12064 (match_operand:<crc_mode> 2 "s_register_operand" "r")]
12067 "<crc_variant>\\t%0, %1, %2"
12068 [(set_attr "type" "crc")
12069 (set_attr "conds" "unconditional")]
12072 ;; Load the load/store double peephole optimizations.
12073 (include "ldrdstrd.md")
12075 ;; Load the load/store multiple patterns
12076 (include "ldmstm.md")
12078 ;; Patterns in ldmstm.md don't cover more than 4 registers. This pattern covers
12079 ;; large lists without explicit writeback generated for APCS_FRAME epilogue.
12080 ;; The operands are validated through the load_multiple_operation
12081 ;; match_parallel predicate rather than through constraints so enable it only
12083 (define_insn "*load_multiple"
12084 [(match_parallel 0 "load_multiple_operation"
12085 [(set (match_operand:SI 2 "s_register_operand" "=rk")
12086 (mem:SI (match_operand:SI 1 "s_register_operand" "rk")))
12088 "TARGET_32BIT && reload_completed"
12091 arm_output_multireg_pop (operands, /*return_pc=*/false,
12092 /*cond=*/const_true_rtx,
12098 [(set_attr "predicable" "yes")]
12101 (define_expand "copysignsf3"
12102 [(match_operand:SF 0 "register_operand")
12103 (match_operand:SF 1 "register_operand")
12104 (match_operand:SF 2 "register_operand")]
12105 "TARGET_SOFT_FLOAT && arm_arch_thumb2"
12107 emit_move_insn (operands[0], operands[2]);
12108 emit_insn (gen_insv_t2 (simplify_gen_subreg (SImode, operands[0], SFmode, 0),
12109 GEN_INT (31), GEN_INT (0),
12110 simplify_gen_subreg (SImode, operands[1], SFmode, 0)));
12115 (define_expand "copysigndf3"
12116 [(match_operand:DF 0 "register_operand")
12117 (match_operand:DF 1 "register_operand")
12118 (match_operand:DF 2 "register_operand")]
12119 "TARGET_SOFT_FLOAT && arm_arch_thumb2"
12121 rtx op0_low = gen_lowpart (SImode, operands[0]);
12122 rtx op0_high = gen_highpart (SImode, operands[0]);
12123 rtx op1_low = gen_lowpart (SImode, operands[1]);
12124 rtx op1_high = gen_highpart (SImode, operands[1]);
12125 rtx op2_high = gen_highpart (SImode, operands[2]);
12127 rtx scratch1 = gen_reg_rtx (SImode);
12128 rtx scratch2 = gen_reg_rtx (SImode);
12129 emit_move_insn (scratch1, op2_high);
12130 emit_move_insn (scratch2, op1_high);
12132 emit_insn(gen_rtx_SET(scratch1,
12133 gen_rtx_LSHIFTRT (SImode, op2_high, GEN_INT(31))));
12134 emit_insn(gen_insv_t2(scratch2, GEN_INT(1), GEN_INT(31), scratch1));
12135 emit_move_insn (op0_low, op1_low);
12136 emit_move_insn (op0_high, scratch2);
12142 ;; movmisalign patterns for HImode and SImode.
12143 (define_expand "movmisalign<mode>"
12144 [(match_operand:HSI 0 "general_operand")
12145 (match_operand:HSI 1 "general_operand")]
12148 /* This pattern is not permitted to fail during expansion: if both arguments
12149 are non-registers (e.g. memory := constant), force operand 1 into a
12151 rtx (* gen_unaligned_load)(rtx, rtx);
12152 rtx tmp_dest = operands[0];
12153 if (!s_register_operand (operands[0], <MODE>mode)
12154 && !s_register_operand (operands[1], <MODE>mode))
12155 operands[1] = force_reg (<MODE>mode, operands[1]);
12157 if (<MODE>mode == HImode)
12159 gen_unaligned_load = gen_unaligned_loadhiu;
12160 tmp_dest = gen_reg_rtx (SImode);
12163 gen_unaligned_load = gen_unaligned_loadsi;
12165 if (MEM_P (operands[1]))
12167 emit_insn (gen_unaligned_load (tmp_dest, operands[1]));
12168 if (<MODE>mode == HImode)
12169 emit_move_insn (operands[0], gen_lowpart (HImode, tmp_dest));
12172 emit_insn (gen_unaligned_store<mode> (operands[0], operands[1]));
12177 (define_insn "<cdp>"
12178 [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "n")
12179 (match_operand:SI 1 "immediate_operand" "n")
12180 (match_operand:SI 2 "immediate_operand" "n")
12181 (match_operand:SI 3 "immediate_operand" "n")
12182 (match_operand:SI 4 "immediate_operand" "n")
12183 (match_operand:SI 5 "immediate_operand" "n")] CDPI)]
12184 "arm_coproc_builtin_available (VUNSPEC_<CDP>)"
12186 arm_const_bounds (operands[0], 0, 16);
12187 arm_const_bounds (operands[1], 0, 16);
12188 arm_const_bounds (operands[2], 0, (1 << 5));
12189 arm_const_bounds (operands[3], 0, (1 << 5));
12190 arm_const_bounds (operands[4], 0, (1 << 5));
12191 arm_const_bounds (operands[5], 0, 8);
12192 return "<cdp>\\tp%c0, %1, CR%c2, CR%c3, CR%c4, %5";
12194 [(set_attr "length" "4")
12195 (set_attr "type" "coproc")])
12197 (define_insn "*ldc"
12198 [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "n")
12199 (match_operand:SI 1 "immediate_operand" "n")
12200 (match_operand:SI 2 "memory_operand" "Uz")] LDCI)]
12201 "arm_coproc_builtin_available (VUNSPEC_<LDC>)"
12203 arm_const_bounds (operands[0], 0, 16);
12204 arm_const_bounds (operands[1], 0, (1 << 5));
12205 return "<ldc>\\tp%c0, CR%c1, %2";
12207 [(set_attr "length" "4")
12208 (set_attr "type" "coproc")])
12210 (define_insn "*stc"
12211 [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "n")
12212 (match_operand:SI 1 "immediate_operand" "n")
12213 (match_operand:SI 2 "memory_operand" "=Uz")] STCI)]
12214 "arm_coproc_builtin_available (VUNSPEC_<STC>)"
12216 arm_const_bounds (operands[0], 0, 16);
12217 arm_const_bounds (operands[1], 0, (1 << 5));
12218 return "<stc>\\tp%c0, CR%c1, %2";
12220 [(set_attr "length" "4")
12221 (set_attr "type" "coproc")])
12223 (define_expand "<ldc>"
12224 [(unspec_volatile [(match_operand:SI 0 "immediate_operand")
12225 (match_operand:SI 1 "immediate_operand")
12226 (mem:SI (match_operand:SI 2 "s_register_operand"))] LDCI)]
12227 "arm_coproc_builtin_available (VUNSPEC_<LDC>)")
12229 (define_expand "<stc>"
12230 [(unspec_volatile [(match_operand:SI 0 "immediate_operand")
12231 (match_operand:SI 1 "immediate_operand")
12232 (mem:SI (match_operand:SI 2 "s_register_operand"))] STCI)]
12233 "arm_coproc_builtin_available (VUNSPEC_<STC>)")
12235 (define_insn "<mcr>"
12236 [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "n")
12237 (match_operand:SI 1 "immediate_operand" "n")
12238 (match_operand:SI 2 "s_register_operand" "r")
12239 (match_operand:SI 3 "immediate_operand" "n")
12240 (match_operand:SI 4 "immediate_operand" "n")
12241 (match_operand:SI 5 "immediate_operand" "n")] MCRI)
12242 (use (match_dup 2))]
12243 "arm_coproc_builtin_available (VUNSPEC_<MCR>)"
12245 arm_const_bounds (operands[0], 0, 16);
12246 arm_const_bounds (operands[1], 0, 8);
12247 arm_const_bounds (operands[3], 0, (1 << 5));
12248 arm_const_bounds (operands[4], 0, (1 << 5));
12249 arm_const_bounds (operands[5], 0, 8);
12250 return "<mcr>\\tp%c0, %1, %2, CR%c3, CR%c4, %5";
12252 [(set_attr "length" "4")
12253 (set_attr "type" "coproc")])
12255 (define_insn "<mrc>"
12256 [(set (match_operand:SI 0 "s_register_operand" "=r")
12257 (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "n")
12258 (match_operand:SI 2 "immediate_operand" "n")
12259 (match_operand:SI 3 "immediate_operand" "n")
12260 (match_operand:SI 4 "immediate_operand" "n")
12261 (match_operand:SI 5 "immediate_operand" "n")] MRCI))]
12262 "arm_coproc_builtin_available (VUNSPEC_<MRC>)"
12264 arm_const_bounds (operands[1], 0, 16);
12265 arm_const_bounds (operands[2], 0, 8);
12266 arm_const_bounds (operands[3], 0, (1 << 5));
12267 arm_const_bounds (operands[4], 0, (1 << 5));
12268 arm_const_bounds (operands[5], 0, 8);
12269 return "<mrc>\\tp%c1, %2, %0, CR%c3, CR%c4, %5";
12271 [(set_attr "length" "4")
12272 (set_attr "type" "coproc")])
12274 (define_insn "<mcrr>"
12275 [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "n")
12276 (match_operand:SI 1 "immediate_operand" "n")
12277 (match_operand:DI 2 "s_register_operand" "r")
12278 (match_operand:SI 3 "immediate_operand" "n")] MCRRI)
12279 (use (match_dup 2))]
12280 "arm_coproc_builtin_available (VUNSPEC_<MCRR>)"
12282 arm_const_bounds (operands[0], 0, 16);
12283 arm_const_bounds (operands[1], 0, 8);
12284 arm_const_bounds (operands[3], 0, (1 << 5));
12285 return "<mcrr>\\tp%c0, %1, %Q2, %R2, CR%c3";
12287 [(set_attr "length" "4")
12288 (set_attr "type" "coproc")])
12290 (define_insn "<mrrc>"
12291 [(set (match_operand:DI 0 "s_register_operand" "=r")
12292 (unspec_volatile:DI [(match_operand:SI 1 "immediate_operand" "n")
12293 (match_operand:SI 2 "immediate_operand" "n")
12294 (match_operand:SI 3 "immediate_operand" "n")] MRRCI))]
12295 "arm_coproc_builtin_available (VUNSPEC_<MRRC>)"
12297 arm_const_bounds (operands[1], 0, 16);
12298 arm_const_bounds (operands[2], 0, 8);
12299 arm_const_bounds (operands[3], 0, (1 << 5));
12300 return "<mrrc>\\tp%c1, %2, %Q0, %R0, CR%c3";
12302 [(set_attr "length" "4")
12303 (set_attr "type" "coproc")])
12305 (define_expand "speculation_barrier"
12306 [(unspec_volatile [(const_int 0)] VUNSPEC_SPECULATION_BARRIER)]
12309 /* For thumb1 (except Armv8 derivatives), and for pre-Armv7 we don't
12310 have a usable barrier (and probably don't need one in practice).
12311 But to be safe if such code is run on later architectures, call a
12312 helper function in libgcc that will do the thing for the active
12314 if (!(arm_arch7 || arm_arch8))
12316 arm_emit_speculation_barrier_function ();
12322 ;; Generate a hard speculation barrier when we have not enabled speculation
12324 (define_insn "*speculation_barrier_insn"
12325 [(unspec_volatile [(const_int 0)] VUNSPEC_SPECULATION_BARRIER)]
12326 "arm_arch7 || arm_arch8"
12328 [(set_attr "type" "block")
12329 (set_attr "length" "8")]
12332 ;; Vector bits common to IWMMXT and Neon
12333 (include "vec-common.md")
12334 ;; Load the Intel Wireless Multimedia Extension patterns
12335 (include "iwmmxt.md")
12336 ;; Load the VFP co-processor patterns
12338 ;; Thumb-1 patterns
12339 (include "thumb1.md")
12340 ;; Thumb-2 patterns
12341 (include "thumb2.md")
12343 (include "neon.md")
12345 (include "crypto.md")
12346 ;; Synchronization Primitives
12347 (include "sync.md")
12348 ;; Fixed-point patterns
12349 (include "arm-fixed.md")