gcc/config/arm/constraints.md

   1 ;; Constraint definitions for ARM and Thumb
   2 ;; Copyright (C) 2006-2020 Free Software Foundation, Inc.
   3 ;; Contributed by ARM Ltd.
   4
   5 ;; This file is part of GCC.
   6
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published
   9 ;; by the Free Software Foundation; either version 3, or (at your
  10 ;; option) any later version.
  11
  12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ;; License for more details.
  16
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 ;; The following register constraints have been used:
  22 ;; - in ARM/Thumb-2 state: t, w, x, y, z
  23 ;; - in Thumb state: h, b
  24 ;; - in both states: l, c, k, q, Cs, Ts, US
  25 ;; In ARM state, 'l' is an alias for 'r'
  26 ;; 'f' and 'v' were previously used for FPA and MAVERICK registers.
  27
  28 ;; The following normal constraints have been used:
  29 ;; in ARM/Thumb-2 state: G, I, j, J, K, L, M
  30 ;; in Thumb-1 state: I, J, K, L, M, N, O
  31 ;; 'H' was previously used for FPA.
  32
  33 ;; The following multi-letter normal constraints have been used:
  34 ;; in ARM/Thumb-2 state: Da, Db, Dc, Dd, Dn, DN, Dm, Dl, DL, Do, Dv, Dy, Di,
  35 ;;                       Dt, Dp, Dz, Tu
  36 ;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe
  37 ;; in Thumb-2 state: Ha, Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py, Pz
  38 ;; in all states: Pf, Pg
  39
  40 ;; The following memory constraints have been used:
  41 ;; in ARM/Thumb-2 state: Uh, Ut, Uv, Uy, Un, Um, Us, Up, Uf
  42 ;; in ARM state: Uq
  43 ;; in Thumb state: Uu, Uw
  44 ;; in all states: Q
  45
  46 (define_register_constraint "Up" "TARGET_HAVE_MVE ? VPR_REG : NO_REGS"
  47   "MVE VPR register")
  48
  49 (define_register_constraint "Uf" "TARGET_HAVE_MVE ? VFPCC_REG : NO_REGS"
  50   "MVE FPCCR register")
  51
  52 (define_register_constraint "e" "TARGET_HAVE_MVE ? EVEN_REG : NO_REGS"
  53   "MVE EVEN registers @code{r0}, @code{r2}, @code{r4}, @code{r6}, @code{r8},
  54    @code{r10}, @code{r12}, @code{r14}")
  55
  56 (define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS"
  57  "The VFP registers @code{s0}-@code{s31}.")
  58
  59 (define_register_constraint "w"
  60   "TARGET_32BIT ? (TARGET_VFPD32 ? VFP_REGS : VFP_LO_REGS) : NO_REGS"
  61  "The VFP registers @code{d0}-@code{d15}, or @code{d0}-@code{d31} for VFPv3.")
  62
  63 (define_register_constraint "x" "TARGET_32BIT ? VFP_D0_D7_REGS : NO_REGS"
  64  "The VFP registers @code{d0}-@code{d7}.")
  65
  66 (define_register_constraint "y" "TARGET_REALLY_IWMMXT ? IWMMXT_REGS : NO_REGS"
  67  "The Intel iWMMX co-processor registers.")
  68
  69 (define_register_constraint "z"
  70  "TARGET_REALLY_IWMMXT ? IWMMXT_GR_REGS : NO_REGS"
  71  "The Intel iWMMX GR registers.")
  72
  73 (define_register_constraint "l" "TARGET_THUMB ? LO_REGS : GENERAL_REGS"
  74  "In Thumb state the core registers @code{r0}-@code{r7}.")
  75
  76 (define_register_constraint "h" "TARGET_THUMB ? HI_REGS : NO_REGS"
  77  "In Thumb state the core registers @code{r8}-@code{r15}.")
  78
  79 (define_constraint "j"
  80  "A constant suitable for a MOVW instruction. (ARM/Thumb-2)"
  81  (and (match_test "TARGET_HAVE_MOVT")
  82       (ior (and (match_code "high")
  83                 (match_test "arm_valid_symbolic_address_p (XEXP (op, 0))"))
  84            (and (match_code "const_int")
  85                 (match_test "(ival & 0xffff0000) == 0")))))
  86
  87 (define_constraint "Pj"
  88  "@internal A 12-bit constant suitable for an ADDW or SUBW instruction. (Thumb-2)"
  89  (and (match_code "const_int")
  90       (and (match_test "TARGET_THUMB2")
  91            (match_test "(ival & 0xfffff000) == 0"))))
  92
  93 (define_constraint "PJ"
  94  "@internal A constant that satisfies the Pj constrant if negated."
  95  (and (match_code "const_int")
  96       (and (match_test "TARGET_THUMB2")
  97            (match_test "((-ival) & 0xfffff000) == 0"))))
  98
  99 (define_register_constraint "k" "STACK_REG"
 100  "@internal The stack register.")
 101
 102 (define_register_constraint "b" "TARGET_THUMB ? BASE_REGS : NO_REGS"
 103  "@internal
 104   Thumb only.  The union of the low registers and the stack register.")
 105
 106 (define_constraint "c"
 107  "@internal The condition code register."
 108  (match_operand 0 "cc_register"))
 109
 110 (define_register_constraint "Cs" "CALLER_SAVE_REGS"
 111  "@internal The caller save registers.  Useful for sibcalls.")
 112
 113 (define_constraint "I"
 114  "In ARM/Thumb-2 state a constant that can be used as an immediate value in a
 115   Data Processing instruction.  In Thumb-1 state a constant in the range
 116   0-255."
 117  (and (match_code "const_int")
 118       (match_test "TARGET_32BIT ? const_ok_for_arm (ival)
 119                    : ival >= 0 && ival <= 255")))
 120
 121 (define_constraint "J"
 122  "In ARM/Thumb-2 state a constant in the range @minus{}4095-4095.  In Thumb-1
 123   state a constant in the range @minus{}255-@minus{}1."
 124  (and (match_code "const_int")
 125       (match_test "TARGET_32BIT ? (ival >= -4095 && ival <= 4095)
 126                    : (ival >= -255 && ival <= -1)")))
 127
 128 (define_constraint "K"
 129  "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
 130   inverted.  In Thumb-1 state a constant that satisfies the @code{I}
 131   constraint multiplied by any power of 2."
 132  (and (match_code "const_int")
 133       (match_test "TARGET_32BIT ? const_ok_for_arm (~ival)
 134                    : thumb_shiftable_const (ival)")))
 135
 136 (define_constraint "L"
 137  "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
 138   negated.  In Thumb-1 state a constant in the range @minus{}7-7."
 139  (and (match_code "const_int")
 140       (match_test "TARGET_32BIT ? const_ok_for_arm (-ival)
 141                    : (ival >= -7 && ival <= 7)")))
 142
 143 ;; The ARM state version is internal...
 144 ;; @internal In ARM/Thumb-2 state a constant in the range 0-32 or any
 145 ;; power of 2.
 146 (define_constraint "M"
 147  "In Thumb-1 state a constant that is a multiple of 4 in the range 0-1020."
 148  (and (match_code "const_int")
 149       (match_test "TARGET_32BIT ? ((ival >= 0 && ival <= 32)
 150                                  || (((ival & (ival - 1)) & 0xFFFFFFFF) == 0))
 151                    : ival >= 0 && ival <= 1020 && (ival & 3) == 0")))
 152
 153 (define_constraint "N"
 154  "Thumb-1 state a constant in the range 0-31."
 155  (and (match_code "const_int")
 156       (match_test "!TARGET_32BIT && (ival >= 0 && ival <= 31)")))
 157
 158 (define_constraint "O"
 159  "In Thumb-1 state a constant that is a multiple of 4 in the range
 160   @minus{}508-508."
 161  (and (match_code "const_int")
 162       (match_test "TARGET_THUMB1 && ival >= -508 && ival <= 508
 163                    && ((ival & 3) == 0)")))
 164
 165 (define_constraint "Pa"
 166   "@internal In Thumb-1 state a constant in the range -510 to +510"
 167   (and (match_code "const_int")
 168        (match_test "TARGET_THUMB1 && ival >= -510 && ival <= 510
 169                     && (ival > 255 || ival < -255)")))
 170
 171 (define_constraint "Pb"
 172   "@internal In Thumb-1 state a constant in the range -262 to +262"
 173   (and (match_code "const_int")
 174        (match_test "TARGET_THUMB1 && ival >= -262 && ival <= 262
 175                     && (ival > 255 || ival < -255)")))
 176
 177 (define_constraint "Pc"
 178   "@internal In Thumb-1 state a constant that is in the range 1021 to 1275"
 179   (and (match_code "const_int")
 180        (match_test "TARGET_THUMB1
 181                     && ival > 1020 && ival <= 1275")))
 182
 183 (define_constraint "Pd"
 184   "@internal In Thumb state a constant in the range 0 to 7"
 185   (and (match_code "const_int")
 186        (match_test "TARGET_THUMB && ival >= 0 && ival <= 7")))
 187
 188 (define_constraint "Pe"
 189   "@internal In Thumb-1 state a constant in the range 256 to +510"
 190   (and (match_code "const_int")
 191        (match_test "TARGET_THUMB1 && ival >= 256 && ival <= 510")))
 192
 193 (define_constraint "Pf"
 194   "Memory models except relaxed, consume or release ones."
 195   (and (match_code "const_int")
 196        (match_test "!is_mm_relaxed (memmodel_from_int (ival))
 197                     && !is_mm_consume (memmodel_from_int (ival))
 198                     && !is_mm_release (memmodel_from_int (ival))")))
 199
 200 (define_constraint "Pg"
 201   "@internal In Thumb-2 state a constant in range 1 to 32"
 202   (and (match_code "const_int")
 203        (match_test "TARGET_THUMB2 && ival >= 1 && ival <= 32")))
 204
 205 (define_constraint "Ps"
 206   "@internal In Thumb-2 state a constant in the range -255 to +255"
 207   (and (match_code "const_int")
 208        (match_test "TARGET_THUMB2 && ival >= -255 && ival <= 255")))
 209
 210 (define_constraint "Pt"
 211   "@internal In Thumb-2 state a constant in the range -7 to +7"
 212   (and (match_code "const_int")
 213        (match_test "TARGET_THUMB2 && ival >= -7 && ival <= 7")))
 214
 215 (define_constraint "Pu"
 216   "@internal In Thumb-2 state a constant in the range +1 to +8"
 217   (and (match_code "const_int")
 218        (match_test "TARGET_THUMB2 && ival >= 1 && ival <= 8")))
 219
 220 (define_constraint "Pv"
 221   "@internal In Thumb-2 state a constant in the range -255 to 0"
 222   (and (match_code "const_int")
 223        (match_test "TARGET_THUMB2 && ival >= -255 && ival <= 0")))
 224
 225 (define_constraint "Pw"
 226   "@internal In Thumb-2 state a constant in the range -255 to -1"
 227   (and (match_code "const_int")
 228        (match_test "TARGET_THUMB2 && ival >= -255 && ival <= -1")))
 229
 230 (define_constraint "Px"
 231   "@internal In Thumb-2 state a constant in the range -7 to -1"
 232   (and (match_code "const_int")
 233        (match_test "TARGET_THUMB2 && ival >= -7 && ival <= -1")))
 234
 235 (define_constraint "Py"
 236   "@internal In Thumb-2 state a constant in the range 0 to 255"
 237   (and (match_code "const_int")
 238        (match_test "TARGET_THUMB2 && ival >= 0 && ival <= 255")))
 239
 240 (define_constraint "Pz"
 241   "@internal In Thumb-2 state the constant 0"
 242   (and (match_code "const_int")
 243        (match_test "TARGET_THUMB2 && (ival == 0)")))
 244
 245 (define_constraint "G"
 246  "In ARM/Thumb-2 state the floating-point constant 0."
 247  (and (match_code "const_double")
 248       (match_test "TARGET_32BIT && arm_const_double_rtx (op)")))
 249
 250 (define_constraint "Ha"
 251   "@internal In ARM / Thumb-2 a float constant iff literal pools are allowed."
 252   (and (match_code "const_double")
 253        (match_test "satisfies_constraint_E (op)")
 254        (match_test "!arm_disable_literal_pool")))
 255
 256 (define_constraint "Dz"
 257  "@internal
 258   In ARM/Thumb-2 state a vector of constant zeros."
 259  (and (match_code "const_vector")
 260       (match_test "TARGET_NEON && op == CONST0_RTX (mode)")))
 261
 262 (define_constraint "Da"
 263  "@internal
 264   In ARM/Thumb-2 state a const_int, const_double or const_vector that can
 265   be generated with two Data Processing insns."
 266  (and (match_code "const_double,const_int,const_vector")
 267       (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 2")))
 268
 269 (define_constraint "Db"
 270  "@internal
 271   In ARM/Thumb-2 state a const_int, const_double or const_vector that can
 272   be generated with three Data Processing insns."
 273  (and (match_code "const_double,const_int,const_vector")
 274       (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 3")))
 275
 276 (define_constraint "Dc"
 277  "@internal
 278   In ARM/Thumb-2 state a const_int, const_double or const_vector that can
 279   be generated with four Data Processing insns.  This pattern is disabled
 280   if optimizing for space or when we have load-delay slots to fill."
 281  (and (match_code "const_double,const_int,const_vector")
 282       (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 4
 283                    && !(optimize_size || arm_ld_sched)")))
 284
 285 (define_constraint "Dd"
 286  "@internal
 287   In ARM/Thumb-2 state a const_int that can be used by insn adddi."
 288  (and (match_code "const_int")
 289       (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, PLUS)")))
 290
 291 (define_constraint "Di"
 292  "@internal
 293   In ARM/Thumb-2 state a const_int or const_double where both the high
 294   and low SImode words can be generated as immediates in 32-bit instructions."
 295  (and (match_code "const_double,const_int")
 296       (match_test "TARGET_32BIT && arm_const_double_by_immediates (op)")))
 297
 298 (define_constraint "Dm"
 299  "@internal
 300   In ARM/Thumb-2 state a const_vector which can be loaded with a Neon vmov
 301   immediate instruction."
 302  (and (match_code "const_vector")
 303       (match_test "TARGET_32BIT
 304                    && imm_for_neon_mov_operand (op, GET_MODE (op))")))
 305
 306 (define_constraint "Dn"
 307  "@internal
 308   In ARM/Thumb-2 state a DImode const_int which can be loaded with a Neon vmov
 309   immediate instruction."
 310  (and (match_code "const_int")
 311       (match_test "TARGET_32BIT && imm_for_neon_mov_operand (op, DImode)")))
 312
 313 (define_constraint "DN"
 314  "@internal
 315   In ARM/Thumb-2 state a TImode const_int which can be loaded with a Neon vmov
 316   immediate instruction."
 317  (and (match_code "const_int")
 318       (match_test "TARGET_32BIT && imm_for_neon_mov_operand (op, TImode)")))
 319
 320 (define_constraint "Dl"
 321  "@internal
 322   In ARM/Thumb-2 state a const_vector which can be used with a Neon vorr or
 323   vbic instruction."
 324  (and (match_code "const_vector")
 325       (match_test "TARGET_32BIT
 326                    && imm_for_neon_logic_operand (op, GET_MODE (op))")))
 327
 328 (define_constraint "DL"
 329  "@internal
 330   In ARM/Thumb-2 state a const_vector which can be used with a Neon vorn or
 331   vand instruction."
 332  (and (match_code "const_vector")
 333       (match_test "TARGET_32BIT
 334                    && imm_for_neon_inv_logic_operand (op, GET_MODE (op))")))
 335
 336 (define_constraint "Do"
 337  "@internal
 338   In ARM/Thumb2 state valid offset for an ldrd/strd instruction."
 339  (and (match_code "const_int")
 340       (match_test "TARGET_LDRD && offset_ok_for_ldrd_strd (ival)")))
 341
 342 (define_constraint "Dv"
 343  "@internal
 344   In ARM/Thumb-2 state a const_double which can be used with a VFP fconsts
 345   instruction."
 346  (and (match_code "const_double")
 347       (match_test "TARGET_32BIT && vfp3_const_double_rtx (op)")))
 348
 349 (define_constraint "Dy"
 350  "@internal
 351   In ARM/Thumb-2 state a const_double which can be used with a VFP fconstd
 352   instruction."
 353  (and (match_code "const_double")
 354       (match_test "TARGET_32BIT && TARGET_VFP_DOUBLE && vfp3_const_double_rtx (op)")))
 355
 356 (define_constraint "Dt"
 357  "@internal
 358   In ARM/ Thumb2 a const_double which can be used with a vcvt.f32.s32 with fract bits operation"
 359   (and (match_code "const_double")
 360        (match_test "TARGET_32BIT && vfp3_const_double_for_fract_bits (op)")))
 361
 362 (define_constraint "Dp"
 363  "@internal
 364   In ARM/ Thumb2 a const_double which can be used with a vcvt.s32.f32 with bits operation"
 365   (and (match_code "const_double")
 366        (match_test "TARGET_32BIT
 367                     && vfp3_const_double_for_bits (op) > 0")))
 368
 369 (define_constraint "Tu"
 370   "@internal In ARM / Thumb-2 an integer constant iff literal pools are
 371    allowed."
 372   (and (match_test "CONSTANT_P (op)")
 373        (match_test "!arm_disable_literal_pool")))
 374
 375 (define_register_constraint "Ts" "(arm_restrict_it) ? LO_REGS : GENERAL_REGS"
 376  "For arm_restrict_it the core registers @code{r0}-@code{r7}.  GENERAL_REGS otherwise.")
 377
 378 (define_memory_constraint "Ua"
 379  "@internal
 380   An address valid for loading/storing register exclusive"
 381  (match_operand 0 "mem_noofs_operand"))
 382
 383 (define_memory_constraint "Uh"
 384  "@internal
 385   An address suitable for byte and half-word loads which does not point inside a constant pool"
 386  (and (match_code "mem")
 387       (match_test "arm_legitimate_address_p (GET_MODE (op), XEXP (op, 0), false) && !arm_is_constant_pool_ref (op)")))
 388
 389 (define_memory_constraint "Ut"
 390  "@internal
 391   In ARM/Thumb-2 state an address valid for loading/storing opaque structure
 392   types wider than TImode."
 393  (and (match_code "mem")
 394       (match_test "TARGET_32BIT && neon_struct_mem_operand (op)")))
 395
 396 (define_memory_constraint "Uv"
 397  "@internal
 398   In ARM/Thumb-2 state a valid VFP load/store address."
 399  (and (match_code "mem")
 400       (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, FALSE)")))
 401
 402 (define_memory_constraint "Uy"
 403  "@internal
 404   In ARM/Thumb-2 state a valid iWMMX load/store address."
 405  (and (match_code "mem")
 406       (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, TRUE)")))
 407
 408 (define_memory_constraint "Un"
 409  "@internal
 410   In ARM/Thumb-2 state a valid address for Neon doubleword vector
 411   load/store instructions."
 412  (and (match_code "mem")
 413       (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 0, true)")))
 414
 415 (define_memory_constraint "Um"
 416  "@internal
 417   In ARM/Thumb-2 state a valid address for Neon element and structure
 418   load/store instructions."
 419  (and (match_code "mem")
 420       (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, true)")))
 421
 422 (define_memory_constraint "Us"
 423  "@internal
 424   In ARM/Thumb-2 state a valid address for non-offset loads/stores of
 425   quad-word values in four ARM registers."
 426  (and (match_code "mem")
 427       (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 1, true)")))
 428
 429 (define_memory_constraint "Uq"
 430  "@internal
 431   In ARM state an address valid in ldrsb instructions."
 432  (and (match_code "mem")
 433       (match_test "TARGET_ARM
 434                    && arm_legitimate_address_outer_p (GET_MODE (op), XEXP (op, 0),
 435                                                       SIGN_EXTEND, 0)
 436                    && !arm_is_constant_pool_ref (op)")))
 437
 438 (define_memory_constraint "Q"
 439  "@internal
 440   An address that is a single base register."
 441  (and (match_code "mem")
 442       (match_test "REG_P (XEXP (op, 0))")))
 443
 444 (define_memory_constraint "Uu"
 445  "@internal
 446   In Thumb state an address that is valid in 16bit encoding."
 447  (and (match_code "mem")
 448       (match_test "TARGET_THUMB
 449                    && thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
 450                                                    0)")))
 451
 452 ; The 16-bit post-increment LDR/STR accepted by thumb1_legitimate_address_p
 453 ; are actually LDM/STM instructions, so cannot be used to access unaligned
 454 ; data.
 455 (define_memory_constraint "Uw"
 456  "@internal
 457   In Thumb state an address that is valid in 16bit encoding, and that can be
 458   used for unaligned accesses."
 459  (and (match_code "mem")
 460       (match_test "TARGET_THUMB
 461                    && thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
 462                                                    0)
 463                    && GET_CODE (XEXP (op, 0)) != POST_INC")))
 464
 465 (define_constraint "US"
 466  "@internal
 467   US is a symbol reference."
 468  (match_code "symbol_ref")
 469 )
 470
 471 (define_memory_constraint "Uz"
 472  "@internal
 473   A memory access that is accessible as an LDC/STC operand"
 474  (and (match_code "mem")
 475       (match_test "arm_coproc_ldc_stc_legitimate_address (op)")))
 476
 477 ;; We used to have constraint letters for S and R in ARM state, but
 478 ;; all uses of these now appear to have been removed.
 479
 480 ;; Additionally, we used to have a Q constraint in Thumb state, but
 481 ;; this wasn't really a valid memory constraint.  Again, all uses of
 482 ;; this now seem to have been removed.
 483