gcc/config/arm/constraints.md

   1 ;; Constraint definitions for ARM and Thumb
   2 ;; Copyright (C) 2006, 2007, 2008 Free Software Foundation, Inc.
   3 ;; Contributed by ARM Ltd.
   4
   5 ;; This file is part of GCC.
   6
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published
   9 ;; by the Free Software Foundation; either version 3, or (at your
  10 ;; option) any later version.
  11
  12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ;; License for more details.
  16
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 ;; The following register constraints have been used:
  22 ;; - in ARM/Thumb-2 state: f, t, v, w, x, y, z
  23 ;; - in Thumb state: h, b
  24 ;; - in both states: l, c, k
  25 ;; In ARM state, 'l' is an alias for 'r'
  26
  27 ;; The following normal constraints have been used:
  28 ;; in ARM/Thumb-2 state: G, H, I, j, J, K, L, M
  29 ;; in Thumb-1 state: I, J, K, L, M, N, O
  30
  31 ;; The following multi-letter normal constraints have been used:
  32 ;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di
  33 ;; in Thumb-1 state: Pa, Pb, Pc, Pd
  34 ;; in Thumb-2 state: Ps, Pt, Pu, Pv, Pw, Px
  35
  36 ;; The following memory constraints have been used:
  37 ;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Um, Us
  38 ;; in ARM state: Uq
  39
  40
  41 (define_register_constraint "f" "TARGET_ARM ? FPA_REGS : NO_REGS"
  42  "Legacy FPA registers @code{f0}-@code{f7}.")
  43
  44 (define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS"
  45  "The VFP registers @code{s0}-@code{s31}.")
  46
  47 (define_register_constraint "v" "TARGET_ARM ? CIRRUS_REGS : NO_REGS"
  48  "The Cirrus Maverick co-processor registers.")
  49
  50 (define_register_constraint "w"
  51   "TARGET_32BIT ? (TARGET_VFPD32 ? VFP_REGS : VFP_LO_REGS) : NO_REGS"
  52  "The VFP registers @code{d0}-@code{d15}, or @code{d0}-@code{d31} for VFPv3.")
  53
  54 (define_register_constraint "x" "TARGET_32BIT ? VFP_D0_D7_REGS : NO_REGS"
  55  "The VFP registers @code{d0}-@code{d7}.")
  56
  57 (define_register_constraint "y" "TARGET_REALLY_IWMMXT ? IWMMXT_REGS : NO_REGS"
  58  "The Intel iWMMX co-processor registers.")
  59
  60 (define_register_constraint "z"
  61  "TARGET_REALLY_IWMMXT ? IWMMXT_GR_REGS : NO_REGS"
  62  "The Intel iWMMX GR registers.")
  63
  64 (define_register_constraint "l" "TARGET_THUMB ? LO_REGS : GENERAL_REGS"
  65  "In Thumb state the core registers @code{r0}-@code{r7}.")
  66
  67 (define_register_constraint "h" "TARGET_THUMB ? HI_REGS : NO_REGS"
  68  "In Thumb state the core registers @code{r8}-@code{r15}.")
  69
  70 (define_constraint "j"
  71  "A constant suitable for a MOVW instruction. (ARM/Thumb-2)"
  72  (and (match_test "TARGET_32BIT && arm_arch_thumb2")
  73       (ior (match_code "high")
  74            (and (match_code "const_int")
  75                 (match_test "(ival & 0xffff0000) == 0")))))
  76
  77 (define_register_constraint "k" "STACK_REG"
  78  "@internal The stack register.")
  79
  80 (define_register_constraint "b" "TARGET_THUMB ? BASE_REGS : NO_REGS"
  81  "@internal
  82   Thumb only.  The union of the low registers and the stack register.")
  83
  84 (define_register_constraint "c" "CC_REG"
  85  "@internal The condition code register.")
  86
  87 (define_constraint "I"
  88  "In ARM/Thumb-2 state a constant that can be used as an immediate value in a
  89   Data Processing instruction.  In Thumb-1 state a constant in the range
  90   0-255."
  91  (and (match_code "const_int")
  92       (match_test "TARGET_32BIT ? const_ok_for_arm (ival)
  93                    : ival >= 0 && ival <= 255")))
  94
  95 (define_constraint "J"
  96  "In ARM/Thumb-2 state a constant in the range @minus{}4095-4095.  In Thumb-1
  97   state a constant in the range @minus{}255-@minus{}1."
  98  (and (match_code "const_int")
  99       (match_test "TARGET_32BIT ? (ival >= -4095 && ival <= 4095)
 100                    : (ival >= -255 && ival <= -1)")))
 101
 102 (define_constraint "K"
 103  "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
 104   inverted.  In Thumb-1 state a constant that satisfies the @code{I}
 105   constraint multiplied by any power of 2."
 106  (and (match_code "const_int")
 107       (match_test "TARGET_32BIT ? const_ok_for_arm (~ival)
 108                    : thumb_shiftable_const (ival)")))
 109
 110 (define_constraint "L"
 111  "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
 112   negated.  In Thumb-1 state a constant in the range @minus{}7-7."
 113  (and (match_code "const_int")
 114       (match_test "TARGET_32BIT ? const_ok_for_arm (-ival)
 115                    : (ival >= -7 && ival <= 7)")))
 116
 117 ;; The ARM state version is internal...
 118 ;; @internal In ARM/Thumb-2 state a constant in the range 0-32 or any
 119 ;; power of 2.
 120 (define_constraint "M"
 121  "In Thumb-1 state a constant that is a multiple of 4 in the range 0-1020."
 122  (and (match_code "const_int")
 123       (match_test "TARGET_32BIT ? ((ival >= 0 && ival <= 32)
 124                                  || (((ival & (ival - 1)) & 0xFFFFFFFF) == 0))
 125                    : ival >= 0 && ival <= 1020 && (ival & 3) == 0")))
 126
 127 (define_constraint "N"
 128  "Thumb-1 state a constant in the range 0-31."
 129  (and (match_code "const_int")
 130       (match_test "!TARGET_32BIT && (ival >= 0 && ival <= 31)")))
 131
 132 (define_constraint "O"
 133  "In Thumb-1 state a constant that is a multiple of 4 in the range
 134   @minus{}508-508."
 135  (and (match_code "const_int")
 136       (match_test "TARGET_THUMB1 && ival >= -508 && ival <= 508
 137                    && ((ival & 3) == 0)")))
 138
 139 (define_constraint "Pa"
 140   "@internal In Thumb-1 state a constant in the range -510 to +510"
 141   (and (match_code "const_int")
 142        (match_test "TARGET_THUMB1 && ival >= -510 && ival <= 510
 143                     && (ival > 255 || ival < -255)")))
 144
 145 (define_constraint "Pb"
 146   "@internal In Thumb-1 state a constant in the range -262 to +262"
 147   (and (match_code "const_int")
 148        (match_test "TARGET_THUMB1 && ival >= -262 && ival <= 262
 149                     && (ival > 255 || ival < -255)")))
 150
 151 (define_constraint "Pc"
 152   "@internal In Thumb-1 state a constant that is in the range 1021 to 1275"
 153   (and (match_code "const_int")
 154        (match_test "TARGET_THUMB1
 155                     && ival > 1020 && ival <= 1275")))
 156
 157 (define_constraint "Pd"
 158   "@internal In Thumb-1 state a constant in the range 0 to 7"
 159   (and (match_code "const_int")
 160        (match_test "TARGET_THUMB1 && ival >= 0 && ival <= 7")))
 161
 162 (define_constraint "Ps"
 163   "@internal In Thumb-2 state a constant in the range -255 to +255"
 164   (and (match_code "const_int")
 165        (match_test "TARGET_THUMB2 && ival >= -255 && ival <= 255")))
 166
 167 (define_constraint "Pt"
 168   "@internal In Thumb-2 state a constant in the range -7 to +7"
 169   (and (match_code "const_int")
 170        (match_test "TARGET_THUMB2 && ival >= -7 && ival <= 7")))
 171
 172 (define_constraint "Pu"
 173   "@internal In Thumb-2 state a constant in the range +1 to +8"
 174   (and (match_code "const_int")
 175        (match_test "TARGET_THUMB2 && ival >= 1 && ival <= 8")))
 176
 177 (define_constraint "Pv"
 178   "@internal In Thumb-2 state a constant in the range -255 to 0"
 179   (and (match_code "const_int")
 180        (match_test "TARGET_THUMB2 && ival >= -255 && ival <= 0")))
 181
 182 (define_constraint "Pw"
 183   "@internal In Thumb-2 state a constant in the range -255 to -1"
 184   (and (match_code "const_int")
 185        (match_test "TARGET_THUMB2 && ival >= -255 && ival <= -1")))
 186
 187 (define_constraint "Px"
 188   "@internal In Thumb-2 state a constant in the range -7 to -1"
 189   (and (match_code "const_int")
 190        (match_test "TARGET_THUMB2 && ival >= -7 && ival <= -1")))
 191
 192 (define_constraint "G"
 193  "In ARM/Thumb-2 state a valid FPA immediate constant."
 194  (and (match_code "const_double")
 195       (match_test "TARGET_32BIT && arm_const_double_rtx (op)")))
 196
 197 (define_constraint "H"
 198  "In ARM/Thumb-2 state a valid FPA immediate constant when negated."
 199  (and (match_code "const_double")
 200       (match_test "TARGET_32BIT && neg_const_double_rtx_ok_for_fpa (op)")))
 201
 202 (define_constraint "Da"
 203  "@internal
 204   In ARM/Thumb-2 state a const_int, const_double or const_vector that can
 205   be generated with two Data Processing insns."
 206  (and (match_code "const_double,const_int,const_vector")
 207       (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 2")))
 208
 209 (define_constraint "Db"
 210  "@internal
 211   In ARM/Thumb-2 state a const_int, const_double or const_vector that can
 212   be generated with three Data Processing insns."
 213  (and (match_code "const_double,const_int,const_vector")
 214       (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 3")))
 215
 216 (define_constraint "Dc"
 217  "@internal
 218   In ARM/Thumb-2 state a const_int, const_double or const_vector that can
 219   be generated with four Data Processing insns.  This pattern is disabled
 220   if optimizing for space or when we have load-delay slots to fill."
 221  (and (match_code "const_double,const_int,const_vector")
 222       (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 4
 223                    && !(optimize_size || arm_ld_sched)")))
 224
 225 (define_constraint "Di"
 226  "@internal
 227   In ARM/Thumb-2 state a const_int or const_double where both the high
 228   and low SImode words can be generated as immediates in 32-bit instructions."
 229  (and (match_code "const_double,const_int")
 230       (match_test "TARGET_32BIT && arm_const_double_by_immediates (op)")))
 231
 232 (define_constraint "Dn"
 233  "@internal
 234   In ARM/Thumb-2 state a const_vector which can be loaded with a Neon vmov
 235   immediate instruction."
 236  (and (match_code "const_vector")
 237       (match_test "TARGET_32BIT
 238                    && imm_for_neon_mov_operand (op, GET_MODE (op))")))
 239
 240 (define_constraint "Dl"
 241  "@internal
 242   In ARM/Thumb-2 state a const_vector which can be used with a Neon vorr or
 243   vbic instruction."
 244  (and (match_code "const_vector")
 245       (match_test "TARGET_32BIT
 246                    && imm_for_neon_logic_operand (op, GET_MODE (op))")))
 247
 248 (define_constraint "DL"
 249  "@internal
 250   In ARM/Thumb-2 state a const_vector which can be used with a Neon vorn or
 251   vand instruction."
 252  (and (match_code "const_vector")
 253       (match_test "TARGET_32BIT
 254                    && imm_for_neon_inv_logic_operand (op, GET_MODE (op))")))
 255
 256 (define_constraint "Dv"
 257  "@internal
 258   In ARM/Thumb-2 state a const_double which can be used with a VFP fconsts
 259   instruction."
 260  (and (match_code "const_double")
 261       (match_test "TARGET_32BIT && vfp3_const_double_rtx (op)")))
 262
 263 (define_constraint "Dy"
 264  "@internal
 265   In ARM/Thumb-2 state a const_double which can be used with a VFP fconstd
 266   instruction."
 267  (and (match_code "const_double")
 268       (match_test "TARGET_32BIT && TARGET_VFP_DOUBLE && vfp3_const_double_rtx (op)")))
 269
 270 (define_memory_constraint "Ut"
 271  "@internal
 272   In ARM/Thumb-2 state an address valid for loading/storing opaque structure
 273   types wider than TImode."
 274  (and (match_code "mem")
 275       (match_test "TARGET_32BIT && neon_struct_mem_operand (op)")))
 276
 277 (define_memory_constraint "Uv"
 278  "@internal
 279   In ARM/Thumb-2 state a valid VFP load/store address."
 280  (and (match_code "mem")
 281       (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, FALSE)")))
 282
 283 (define_memory_constraint "Uy"
 284  "@internal
 285   In ARM/Thumb-2 state a valid iWMMX load/store address."
 286  (and (match_code "mem")
 287       (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, TRUE)")))
 288
 289 (define_memory_constraint "Un"
 290  "@internal
 291   In ARM/Thumb-2 state a valid address for Neon doubleword vector
 292   load/store instructions."
 293  (and (match_code "mem")
 294       (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 0)")))
 295
 296 (define_memory_constraint "Um"
 297  "@internal
 298   In ARM/Thumb-2 state a valid address for Neon element and structure
 299   load/store instructions."
 300  (and (match_code "mem")
 301       (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2)")))
 302
 303 (define_memory_constraint "Us"
 304  "@internal
 305   In ARM/Thumb-2 state a valid address for non-offset loads/stores of
 306   quad-word values in four ARM registers."
 307  (and (match_code "mem")
 308       (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 1)")))
 309
 310 (define_memory_constraint "Uq"
 311  "@internal
 312   In ARM state an address valid in ldrsb instructions."
 313  (and (match_code "mem")
 314       (match_test "TARGET_ARM
 315                    && arm_legitimate_address_outer_p (GET_MODE (op), XEXP (op, 0),
 316                                                       SIGN_EXTEND, 0)")))
 317
 318 (define_memory_constraint "Q"
 319  "@internal
 320   In ARM/Thumb-2 state an address that is a single base register."
 321  (and (match_code "mem")
 322       (match_test "REG_P (XEXP (op, 0))")))
 323
 324 ;; We used to have constraint letters for S and R in ARM state, but
 325 ;; all uses of these now appear to have been removed.
 326
 327 ;; Additionally, we used to have a Q constraint in Thumb state, but
 328 ;; this wasn't really a valid memory constraint.  Again, all uses of
 329 ;; this now seem to have been removed.