gcc/config/arm/constraints.md

   1 ;; Constraint definitions for ARM and Thumb
   2 ;; Copyright (C) 2006, 2007 Free Software Foundation, Inc.
   3 ;; Contributed by ARM Ltd.
   4
   5 ;; This file is part of GCC.
   6
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published
   9 ;; by the Free Software Foundation; either version 2, or (at your
  10 ;; option) any later version.
  11
  12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ;; License for more details.
  16
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING.  If not, write to
  19 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
  20 ;; Boston, MA 02110-1301, USA.
  21
  22 ;; The following register constraints have been used:
  23 ;; - in ARM/Thumb-2 state: f, v, w, y, z
  24 ;; - in Thumb state: h, k, b
  25 ;; - in both states: l, c
  26 ;; In ARM state, 'l' is an alias for 'r'
  27
  28 ;; The following normal constraints have been used:
  29 ;; in ARM/Thumb-2 state: G, H, I, J, K, L, M
  30 ;; in Thumb-1 state: I, J, K, L, M, N, O
  31
  32 ;; The following multi-letter normal constraints have been used:
  33 ;; in ARM/Thumb-2 state: Da, Db, Dc
  34
  35 ;; The following memory constraints have been used:
  36 ;; in ARM/Thumb-2 state: Q, Uv, Uy
  37 ;; in ARM state: Uq
  38
  39
  40 (define_register_constraint "f" "TARGET_ARM ? FPA_REGS : NO_REGS"
  41  "Legacy FPA registers @code{f0}-@code{f7}.")
  42
  43 (define_register_constraint "v" "TARGET_ARM ? CIRRUS_REGS : NO_REGS"
  44  "The Cirrus Maverick co-processor registers.")
  45
  46 (define_register_constraint "w" "TARGET_ARM ? VFP_REGS : NO_REGS"
  47  "The VFP registers @code{s0}-@code{s31}.")
  48
  49 (define_register_constraint "y" "TARGET_REALLY_IWMMXT ? IWMMXT_REGS : NO_REGS"
  50  "The Intel iWMMX co-processor registers.")
  51
  52 (define_register_constraint "z"
  53  "TARGET_REALLY_IWMMXT ? IWMMXT_GR_REGS : NO_REGS"
  54  "The Intel iWMMX GR registers.")
  55
  56 (define_register_constraint "l" "TARGET_THUMB ? LO_REGS : GENERAL_REGS"
  57  "In Thumb state the core registers @code{r0}-@code{r7}.")
  58
  59 (define_register_constraint "h" "TARGET_THUMB ? HI_REGS : NO_REGS"
  60  "In Thumb state the core registers @code{r8}-@code{r15}.")
  61
  62 (define_register_constraint "k" "TARGET_THUMB ? STACK_REG : NO_REGS"
  63  "@internal
  64   Thumb only.  The stack register.")
  65
  66 (define_register_constraint "b" "TARGET_THUMB ? BASE_REGS : NO_REGS"
  67  "@internal
  68   Thumb only.  The union of the low registers and the stack register.")
  69
  70 (define_register_constraint "c" "CC_REG"
  71  "@internal The condition code register.")
  72
  73 (define_constraint "I"
  74  "In ARM/Thumb-2 state a constant that can be used as an immediate value in a
  75   Data Processing instruction.  In Thumb-1 state a constant in the range
  76   0-255."
  77  (and (match_code "const_int")
  78       (match_test "TARGET_32BIT ? const_ok_for_arm (ival)
  79                    : ival >= 0 && ival <= 255")))
  80
  81 (define_constraint "J"
  82  "In ARM/Thumb-2 state a constant in the range @minus{}4095-4095.  In Thumb-1
  83   state a constant in the range @minus{}255-@minus{}1."
  84  (and (match_code "const_int")
  85       (match_test "TARGET_32BIT ? (ival >= -4095 && ival <= 4095)
  86                    : (ival >= -255 && ival <= -1)")))
  87
  88 (define_constraint "K"
  89  "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
  90   inverted.  In Thumb-1 state a constant that satisfies the @code{I}
  91   constraint multiplied by any power of 2."
  92  (and (match_code "const_int")
  93       (match_test "TARGET_32BIT ? const_ok_for_arm (~ival)
  94                    : thumb_shiftable_const (ival)")))
  95
  96 (define_constraint "L"
  97  "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
  98   negated.  In Thumb-1 state a constant in the range @minus{}7-7."
  99  (and (match_code "const_int")
 100       (match_test "TARGET_32BIT ? const_ok_for_arm (-ival)
 101                    : (ival >= -7 && ival <= 7)")))
 102
 103 ;; The ARM state version is internal...
 104 ;; @internal In ARM/Thumb-2 state a constant in the range 0-32 or any
 105 ;; power of 2.
 106 (define_constraint "M"
 107  "In Thumb-1 state a constant that is a multiple of 4 in the range 0-1020."
 108  (and (match_code "const_int")
 109       (match_test "TARGET_32BIT ? ((ival >= 0 && ival <= 32)
 110                                  || ((ival & (ival - 1)) == 0))
 111                    : ((ival >= 0 && ival <= 1020) && ((ival & 3) == 0))")))
 112
 113 (define_constraint "N"
 114  "In ARM/Thumb-2 state a constant suitable for a MOVW instruction.
 115   In Thumb-1 state a constant in the range 0-31."
 116  (and (match_code "const_int")
 117       (match_test "TARGET_32BIT ? arm_arch_thumb2 && ((ival & 0xffff0000) == 0)
 118                                 : (ival >= 0 && ival <= 31)")))
 119
 120 (define_constraint "O"
 121  "In Thumb-1 state a constant that is a multiple of 4 in the range
 122   @minus{}508-508."
 123  (and (match_code "const_int")
 124       (match_test "TARGET_THUMB1 && ival >= -508 && ival <= 508
 125                    && ((ival & 3) == 0)")))
 126
 127 (define_constraint "G"
 128  "In ARM/Thumb-2 state a valid FPA immediate constant."
 129  (and (match_code "const_double")
 130       (match_test "TARGET_32BIT && arm_const_double_rtx (op)")))
 131
 132 (define_constraint "H"
 133  "In ARM/Thumb-2 state a valid FPA immediate constant when negated."
 134  (and (match_code "const_double")
 135       (match_test "TARGET_32BIT && neg_const_double_rtx_ok_for_fpa (op)")))
 136
 137 (define_constraint "Da"
 138  "@internal
 139   In ARM/Thumb-2 state a const_int, const_double or const_vector that can
 140   be generated with two Data Processing insns."
 141  (and (match_code "const_double,const_int,const_vector")
 142       (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 2")))
 143
 144 (define_constraint "Db"
 145  "@internal
 146   In ARM/Thumb-2 state a const_int, const_double or const_vector that can
 147   be generated with three Data Processing insns."
 148  (and (match_code "const_double,const_int,const_vector")
 149       (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 3")))
 150
 151 (define_constraint "Dc"
 152  "@internal
 153   In ARM/Thumb-2 state a const_int, const_double or const_vector that can
 154   be generated with four Data Processing insns.  This pattern is disabled
 155   if optimizing for space or when we have load-delay slots to fill."
 156  (and (match_code "const_double,const_int,const_vector")
 157       (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 4
 158                    && !(optimize_size || arm_ld_sched)")))
 159
 160 (define_memory_constraint "Uv"
 161  "@internal
 162   In ARM/Thumb-2 state a valid VFP load/store address."
 163  (and (match_code "mem")
 164       (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, FALSE)")))
 165
 166 (define_memory_constraint "Uy"
 167  "@internal
 168   In ARM/Thumb-2 state a valid iWMMX load/store address."
 169  (and (match_code "mem")
 170       (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, TRUE)")))
 171
 172 (define_memory_constraint "Uq"
 173  "@internal
 174   In ARM state an address valid in ldrsb instructions."
 175  (and (match_code "mem")
 176       (match_test "TARGET_ARM
 177                    && arm_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
 178                                                 SIGN_EXTEND, 0)")))
 179
 180 (define_memory_constraint "Q"
 181  "@internal
 182   In ARM/Thumb-2 state an address that is a single base register."
 183  (and (match_code "mem")
 184       (match_test "REG_P (XEXP (op, 0))")))
 185
 186 ;; We used to have constraint letters for S and R in ARM state, but
 187 ;; all uses of these now appear to have been removed.
 188
 189 ;; Additionally, we used to have a Q constraint in Thumb state, but
 190 ;; this wasn't really a valid memory constraint.  Again, all uses of
 191 ;; this now seem to have been removed.