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1 ;; Constraint definitions for ARM and Thumb
2 ;; Copyright (C) 2006-2016 Free Software Foundation, Inc.
3 ;; Contributed by ARM Ltd.
4
5 ;; This file is part of GCC.
6
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
11
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
16
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
20
21 ;; The following register constraints have been used:
22 ;; - in ARM/Thumb-2 state: t, w, x, y, z
23 ;; - in Thumb state: h, b
24 ;; - in both states: l, c, k, q, Cs, Ts, US
25 ;; In ARM state, 'l' is an alias for 'r'
26 ;; 'f' and 'v' were previously used for FPA and MAVERICK registers.
27
28 ;; The following normal constraints have been used:
29 ;; in ARM/Thumb-2 state: G, I, j, J, K, L, M
30 ;; in Thumb-1 state: I, J, K, L, M, N, O
31 ;; 'H' was previously used for FPA.
32
33 ;; The following multi-letter normal constraints have been used:
34 ;; in ARM/Thumb-2 state: Da, Db, Dc, Dd, Dn, Dl, DL, Do, Dv, Dy, Di, Dt, Dp, Dz
35 ;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe
36 ;; in Thumb-2 state: Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py
37
38 ;; The following memory constraints have been used:
39 ;; in ARM/Thumb-2 state: Q, Uh, Ut, Uv, Uy, Un, Um, Us
40 ;; in ARM state: Uq
41 ;; in Thumb state: Uu, Uw
42
43
44 (define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS"
45 "The VFP registers @code{s0}-@code{s31}.")
46
47 (define_register_constraint "w"
48 "TARGET_32BIT ? (TARGET_VFPD32 ? VFP_REGS : VFP_LO_REGS) : NO_REGS"
49 "The VFP registers @code{d0}-@code{d15}, or @code{d0}-@code{d31} for VFPv3.")
50
51 (define_register_constraint "x" "TARGET_32BIT ? VFP_D0_D7_REGS : NO_REGS"
52 "The VFP registers @code{d0}-@code{d7}.")
53
54 (define_register_constraint "y" "TARGET_REALLY_IWMMXT ? IWMMXT_REGS : NO_REGS"
55 "The Intel iWMMX co-processor registers.")
56
57 (define_register_constraint "z"
58 "TARGET_REALLY_IWMMXT ? IWMMXT_GR_REGS : NO_REGS"
59 "The Intel iWMMX GR registers.")
60
61 (define_register_constraint "l" "TARGET_THUMB ? LO_REGS : GENERAL_REGS"
62 "In Thumb state the core registers @code{r0}-@code{r7}.")
63
64 (define_register_constraint "h" "TARGET_THUMB ? HI_REGS : NO_REGS"
65 "In Thumb state the core registers @code{r8}-@code{r15}.")
66
67 (define_constraint "j"
68 "A constant suitable for a MOVW instruction. (ARM/Thumb-2)"
69 (and (match_test "TARGET_32BIT && arm_arch_thumb2")
70 (ior (and (match_code "high")
71 (match_test "arm_valid_symbolic_address_p (XEXP (op, 0))"))
72 (and (match_code "const_int")
73 (match_test "(ival & 0xffff0000) == 0")))))
74
75 (define_constraint "Pj"
76 "@internal A 12-bit constant suitable for an ADDW or SUBW instruction. (Thumb-2)"
77 (and (match_code "const_int")
78 (and (match_test "TARGET_THUMB2")
79 (match_test "(ival & 0xfffff000) == 0"))))
80
81 (define_constraint "PJ"
82 "@internal A constant that satisfies the Pj constrant if negated."
83 (and (match_code "const_int")
84 (and (match_test "TARGET_THUMB2")
85 (match_test "((-ival) & 0xfffff000) == 0"))))
86
87 (define_register_constraint "k" "STACK_REG"
88 "@internal The stack register.")
89
90 (define_register_constraint "q" "(TARGET_ARM && TARGET_LDRD) ? CORE_REGS : GENERAL_REGS"
91 "@internal In ARM state with LDRD support, core registers, otherwise general registers.")
92
93 (define_register_constraint "b" "TARGET_THUMB ? BASE_REGS : NO_REGS"
94 "@internal
95 Thumb only. The union of the low registers and the stack register.")
96
97 (define_register_constraint "c" "CC_REG"
98 "@internal The condition code register.")
99
100 (define_register_constraint "Cs" "CALLER_SAVE_REGS"
101 "@internal The caller save registers. Useful for sibcalls.")
102
103 (define_constraint "I"
104 "In ARM/Thumb-2 state a constant that can be used as an immediate value in a
105 Data Processing instruction. In Thumb-1 state a constant in the range
106 0-255."
107 (and (match_code "const_int")
108 (match_test "TARGET_32BIT ? const_ok_for_arm (ival)
109 : ival >= 0 && ival <= 255")))
110
111 (define_constraint "J"
112 "In ARM/Thumb-2 state a constant in the range @minus{}4095-4095. In Thumb-1
113 state a constant in the range @minus{}255-@minus{}1."
114 (and (match_code "const_int")
115 (match_test "TARGET_32BIT ? (ival >= -4095 && ival <= 4095)
116 : (ival >= -255 && ival <= -1)")))
117
118 (define_constraint "K"
119 "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
120 inverted. In Thumb-1 state a constant that satisfies the @code{I}
121 constraint multiplied by any power of 2."
122 (and (match_code "const_int")
123 (match_test "TARGET_32BIT ? const_ok_for_arm (~ival)
124 : thumb_shiftable_const (ival)")))
125
126 (define_constraint "L"
127 "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
128 negated. In Thumb-1 state a constant in the range @minus{}7-7."
129 (and (match_code "const_int")
130 (match_test "TARGET_32BIT ? const_ok_for_arm (-ival)
131 : (ival >= -7 && ival <= 7)")))
132
133 ;; The ARM state version is internal...
134 ;; @internal In ARM/Thumb-2 state a constant in the range 0-32 or any
135 ;; power of 2.
136 (define_constraint "M"
137 "In Thumb-1 state a constant that is a multiple of 4 in the range 0-1020."
138 (and (match_code "const_int")
139 (match_test "TARGET_32BIT ? ((ival >= 0 && ival <= 32)
140 || (((ival & (ival - 1)) & 0xFFFFFFFF) == 0))
141 : ival >= 0 && ival <= 1020 && (ival & 3) == 0")))
142
143 (define_constraint "N"
144 "Thumb-1 state a constant in the range 0-31."
145 (and (match_code "const_int")
146 (match_test "!TARGET_32BIT && (ival >= 0 && ival <= 31)")))
147
148 (define_constraint "O"
149 "In Thumb-1 state a constant that is a multiple of 4 in the range
150 @minus{}508-508."
151 (and (match_code "const_int")
152 (match_test "TARGET_THUMB1 && ival >= -508 && ival <= 508
153 && ((ival & 3) == 0)")))
154
155 (define_constraint "Pa"
156 "@internal In Thumb-1 state a constant in the range -510 to +510"
157 (and (match_code "const_int")
158 (match_test "TARGET_THUMB1 && ival >= -510 && ival <= 510
159 && (ival > 255 || ival < -255)")))
160
161 (define_constraint "Pb"
162 "@internal In Thumb-1 state a constant in the range -262 to +262"
163 (and (match_code "const_int")
164 (match_test "TARGET_THUMB1 && ival >= -262 && ival <= 262
165 && (ival > 255 || ival < -255)")))
166
167 (define_constraint "Pc"
168 "@internal In Thumb-1 state a constant that is in the range 1021 to 1275"
169 (and (match_code "const_int")
170 (match_test "TARGET_THUMB1
171 && ival > 1020 && ival <= 1275")))
172
173 (define_constraint "Pd"
174 "@internal In Thumb state a constant in the range 0 to 7"
175 (and (match_code "const_int")
176 (match_test "TARGET_THUMB && ival >= 0 && ival <= 7")))
177
178 (define_constraint "Pe"
179 "@internal In Thumb-1 state a constant in the range 256 to +510"
180 (and (match_code "const_int")
181 (match_test "TARGET_THUMB1 && ival >= 256 && ival <= 510")))
182
183 (define_constraint "Ps"
184 "@internal In Thumb-2 state a constant in the range -255 to +255"
185 (and (match_code "const_int")
186 (match_test "TARGET_THUMB2 && ival >= -255 && ival <= 255")))
187
188 (define_constraint "Pt"
189 "@internal In Thumb-2 state a constant in the range -7 to +7"
190 (and (match_code "const_int")
191 (match_test "TARGET_THUMB2 && ival >= -7 && ival <= 7")))
192
193 (define_constraint "Pu"
194 "@internal In Thumb-2 state a constant in the range +1 to +8"
195 (and (match_code "const_int")
196 (match_test "TARGET_THUMB2 && ival >= 1 && ival <= 8")))
197
198 (define_constraint "Pv"
199 "@internal In Thumb-2 state a constant in the range -255 to 0"
200 (and (match_code "const_int")
201 (match_test "TARGET_THUMB2 && ival >= -255 && ival <= 0")))
202
203 (define_constraint "Pw"
204 "@internal In Thumb-2 state a constant in the range -255 to -1"
205 (and (match_code "const_int")
206 (match_test "TARGET_THUMB2 && ival >= -255 && ival <= -1")))
207
208 (define_constraint "Px"
209 "@internal In Thumb-2 state a constant in the range -7 to -1"
210 (and (match_code "const_int")
211 (match_test "TARGET_THUMB2 && ival >= -7 && ival <= -1")))
212
213 (define_constraint "Py"
214 "@internal In Thumb-2 state a constant in the range 0 to 255"
215 (and (match_code "const_int")
216 (match_test "TARGET_THUMB2 && ival >= 0 && ival <= 255")))
217
218 (define_constraint "Pz"
219 "@internal In Thumb-2 state the constant 0"
220 (and (match_code "const_int")
221 (match_test "TARGET_THUMB2 && (ival == 0)")))
222
223 (define_constraint "G"
224 "In ARM/Thumb-2 state the floating-point constant 0."
225 (and (match_code "const_double")
226 (match_test "TARGET_32BIT && arm_const_double_rtx (op)")))
227
228 (define_constraint "Dz"
229 "@internal
230 In ARM/Thumb-2 state a vector of constant zeros."
231 (and (match_code "const_vector")
232 (match_test "TARGET_NEON && op == CONST0_RTX (mode)")))
233
234 (define_constraint "Da"
235 "@internal
236 In ARM/Thumb-2 state a const_int, const_double or const_vector that can
237 be generated with two Data Processing insns."
238 (and (match_code "const_double,const_int,const_vector")
239 (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 2")))
240
241 (define_constraint "Db"
242 "@internal
243 In ARM/Thumb-2 state a const_int, const_double or const_vector that can
244 be generated with three Data Processing insns."
245 (and (match_code "const_double,const_int,const_vector")
246 (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 3")))
247
248 (define_constraint "Dc"
249 "@internal
250 In ARM/Thumb-2 state a const_int, const_double or const_vector that can
251 be generated with four Data Processing insns. This pattern is disabled
252 if optimizing for space or when we have load-delay slots to fill."
253 (and (match_code "const_double,const_int,const_vector")
254 (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 4
255 && !(optimize_size || arm_ld_sched)")))
256
257 (define_constraint "Dd"
258 "@internal
259 In ARM/Thumb-2 state a const_int that can be used by insn adddi."
260 (and (match_code "const_int")
261 (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, PLUS)")))
262
263 (define_constraint "De"
264 "@internal
265 In ARM/Thumb-2 state a const_int that can be used by insn anddi."
266 (and (match_code "const_int")
267 (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, AND)")))
268
269 (define_constraint "Df"
270 "@internal
271 In ARM/Thumb-2 state a const_int that can be used by insn iordi."
272 (and (match_code "const_int")
273 (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, IOR)")))
274
275 (define_constraint "Dg"
276 "@internal
277 In ARM/Thumb-2 state a const_int that can be used by insn xordi."
278 (and (match_code "const_int")
279 (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, XOR)")))
280
281 (define_constraint "Di"
282 "@internal
283 In ARM/Thumb-2 state a const_int or const_double where both the high
284 and low SImode words can be generated as immediates in 32-bit instructions."
285 (and (match_code "const_double,const_int")
286 (match_test "TARGET_32BIT && arm_const_double_by_immediates (op)")))
287
288 (define_constraint "Dn"
289 "@internal
290 In ARM/Thumb-2 state a const_vector or const_int which can be loaded with a
291 Neon vmov immediate instruction."
292 (and (match_code "const_vector,const_int")
293 (match_test "TARGET_32BIT
294 && imm_for_neon_mov_operand (op, GET_MODE (op))")))
295
296 (define_constraint "Dl"
297 "@internal
298 In ARM/Thumb-2 state a const_vector which can be used with a Neon vorr or
299 vbic instruction."
300 (and (match_code "const_vector")
301 (match_test "TARGET_32BIT
302 && imm_for_neon_logic_operand (op, GET_MODE (op))")))
303
304 (define_constraint "DL"
305 "@internal
306 In ARM/Thumb-2 state a const_vector which can be used with a Neon vorn or
307 vand instruction."
308 (and (match_code "const_vector")
309 (match_test "TARGET_32BIT
310 && imm_for_neon_inv_logic_operand (op, GET_MODE (op))")))
311
312 (define_constraint "Do"
313 "@internal
314 In ARM/Thumb2 state valid offset for an ldrd/strd instruction."
315 (and (match_code "const_int")
316 (match_test "TARGET_LDRD && offset_ok_for_ldrd_strd (ival)")))
317
318 (define_constraint "Dv"
319 "@internal
320 In ARM/Thumb-2 state a const_double which can be used with a VFP fconsts
321 instruction."
322 (and (match_code "const_double")
323 (match_test "TARGET_32BIT && vfp3_const_double_rtx (op)")))
324
325 (define_constraint "Dy"
326 "@internal
327 In ARM/Thumb-2 state a const_double which can be used with a VFP fconstd
328 instruction."
329 (and (match_code "const_double")
330 (match_test "TARGET_32BIT && TARGET_VFP_DOUBLE && vfp3_const_double_rtx (op)")))
331
332 (define_constraint "Dt"
333 "@internal
334 In ARM/ Thumb2 a const_double which can be used with a vcvt.f32.s32 with fract bits operation"
335 (and (match_code "const_double")
336 (match_test "TARGET_32BIT && TARGET_VFP && vfp3_const_double_for_fract_bits (op)")))
337
338 (define_constraint "Dp"
339 "@internal
340 In ARM/ Thumb2 a const_double which can be used with a vcvt.s32.f32 with bits operation"
341 (and (match_code "const_double")
342 (match_test "TARGET_32BIT && TARGET_VFP
343 && vfp3_const_double_for_bits (op) > 0")))
344
345 (define_register_constraint "Ts" "(arm_restrict_it) ? LO_REGS : GENERAL_REGS"
346 "For arm_restrict_it the core registers @code{r0}-@code{r7}. GENERAL_REGS otherwise.")
347
348 (define_memory_constraint "Ua"
349 "@internal
350 An address valid for loading/storing register exclusive"
351 (match_operand 0 "mem_noofs_operand"))
352
353 (define_memory_constraint "Uh"
354 "@internal
355 An address suitable for byte and half-word loads which does not point inside a constant pool"
356 (and (match_code "mem")
357 (match_test "arm_legitimate_address_p (GET_MODE (op), XEXP (op, 0), false) && !arm_is_constant_pool_ref (op)")))
358
359 (define_memory_constraint "Ut"
360 "@internal
361 In ARM/Thumb-2 state an address valid for loading/storing opaque structure
362 types wider than TImode."
363 (and (match_code "mem")
364 (match_test "TARGET_32BIT && neon_struct_mem_operand (op)")))
365
366 (define_memory_constraint "Uv"
367 "@internal
368 In ARM/Thumb-2 state a valid VFP load/store address."
369 (and (match_code "mem")
370 (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, FALSE)")))
371
372 (define_memory_constraint "Uy"
373 "@internal
374 In ARM/Thumb-2 state a valid iWMMX load/store address."
375 (and (match_code "mem")
376 (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, TRUE)")))
377
378 (define_memory_constraint "Un"
379 "@internal
380 In ARM/Thumb-2 state a valid address for Neon doubleword vector
381 load/store instructions."
382 (and (match_code "mem")
383 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 0, true)")))
384
385 (define_memory_constraint "Um"
386 "@internal
387 In ARM/Thumb-2 state a valid address for Neon element and structure
388 load/store instructions."
389 (and (match_code "mem")
390 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, true)")))
391
392 (define_memory_constraint "Us"
393 "@internal
394 In ARM/Thumb-2 state a valid address for non-offset loads/stores of
395 quad-word values in four ARM registers."
396 (and (match_code "mem")
397 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 1, true)")))
398
399 (define_memory_constraint "Uq"
400 "@internal
401 In ARM state an address valid in ldrsb instructions."
402 (and (match_code "mem")
403 (match_test "TARGET_ARM
404 && arm_legitimate_address_outer_p (GET_MODE (op), XEXP (op, 0),
405 SIGN_EXTEND, 0)
406 && !arm_is_constant_pool_ref (op)")))
407
408 (define_memory_constraint "Q"
409 "@internal
410 In ARM/Thumb-2 state an address that is a single base register."
411 (and (match_code "mem")
412 (match_test "REG_P (XEXP (op, 0))")))
413
414 (define_memory_constraint "Uu"
415 "@internal
416 In Thumb state an address that is valid in 16bit encoding."
417 (and (match_code "mem")
418 (match_test "TARGET_THUMB
419 && thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
420 0)")))
421
422 ; The 16-bit post-increment LDR/STR accepted by thumb1_legitimate_address_p
423 ; are actually LDM/STM instructions, so cannot be used to access unaligned
424 ; data.
425 (define_memory_constraint "Uw"
426 "@internal
427 In Thumb state an address that is valid in 16bit encoding, and that can be
428 used for unaligned accesses."
429 (and (match_code "mem")
430 (match_test "TARGET_THUMB
431 && thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
432 0)
433 && GET_CODE (XEXP (op, 0)) != POST_INC")))
434
435 (define_constraint "US"
436 "@internal
437 US is a symbol reference."
438 (match_code "symbol_ref")
439 )
440
441 ;; We used to have constraint letters for S and R in ARM state, but
442 ;; all uses of these now appear to have been removed.
443
444 ;; Additionally, we used to have a Q constraint in Thumb state, but
445 ;; this wasn't really a valid memory constraint. Again, all uses of
446 ;; this now seem to have been removed.
447