gcc/config/arm/constraints.md

   1 ;; Constraint definitions for ARM and Thumb
   2 ;; Copyright (C) 2006-2021 Free Software Foundation, Inc.
   3 ;; Contributed by ARM Ltd.
   4
   5 ;; This file is part of GCC.
   6
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published
   9 ;; by the Free Software Foundation; either version 3, or (at your
  10 ;; option) any later version.
  11
  12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ;; License for more details.
  16
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 ;; The following register constraints have been used:
  22 ;; - in ARM/Thumb-2 state: t, w, x, y, z
  23 ;; - in Thumb state: h, b
  24 ;; - in both states: l, c, k, q, Cs, Ts, US
  25 ;; In ARM state, 'l' is an alias for 'r'
  26 ;; 'f' and 'v' were previously used for FPA and MAVERICK registers.
  27
  28 ;; The following normal constraints have been used:
  29 ;; in ARM/Thumb-2 state: G, I, j, J, K, L, M
  30 ;; in Thumb-1 state: I, J, K, L, M, N, O
  31 ;; 'H' was previously used for FPA.
  32
  33 ;; The following multi-letter normal constraints have been used:
  34 ;; in ARM/Thumb-2 state: Da, Db, Dc, Dd, Dn, DN, Dm, Dl, DL, Do, Dv, Dy, Di,
  35 ;;                       Dt, Dp, Dz, Tu, Te
  36 ;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe
  37 ;; in Thumb-2 state: Ha, Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py, Pz, Rd, Rf, Rb, Ra,
  38 ;;                   Rg, Ri
  39 ;; in all states: Pf, Pg
  40
  41 ;; The following memory constraints have been used:
  42 ;; in ARM/Thumb-2 state: Uh, Ut, Uv, Uy, Un, Um, Us, Up, Uf, Ux, Ul
  43 ;; in ARM state: Uq
  44 ;; in Thumb state: Uu, Uw
  45 ;; in all states: Q
  46
  47 (define_register_constraint "Up" "TARGET_HAVE_MVE ? VPR_REG : NO_REGS"
  48   "MVE VPR register")
  49
  50 (define_memory_constraint "Ul"
  51  "@internal
  52   In ARM/Thumb-2 state a valid address for load instruction with XEXP (op, 0)
  53   being label of the literal data item to be loaded."
  54  (and (match_code "mem")
  55       (match_test "TARGET_HAVE_MVE && reload_completed
  56                    && (GET_CODE (XEXP (op, 0)) == LABEL_REF
  57                        || (GET_CODE (XEXP (op, 0)) == CONST
  58                            && GET_CODE (XEXP (XEXP (op, 0), 0)) == PLUS
  59                            && GET_CODE (XEXP (XEXP (XEXP (op, 0), 0), 0)) == LABEL_REF
  60                            && CONST_INT_P (XEXP (XEXP (XEXP (op, 0), 0), 1))))")))
  61
  62 (define_register_constraint "Uf" "TARGET_HAVE_MVE ? VFPCC_REG : NO_REGS"
  63   "MVE FPCCR register")
  64
  65 (define_register_constraint "Te" "TARGET_HAVE_MVE ? EVEN_REG : NO_REGS"
  66   "EVEN core registers @code{r0}, @code{r2}, @code{r4}, @code{r6}, @code{r8},
  67    @code{r10}, @code{r12}, @code{r14}")
  68
  69 (define_constraint "Rd"
  70   "@internal In Thumb-2 state a constant in range 1 to 16"
  71   (and (match_code "const_int")
  72        (match_test "TARGET_HAVE_MVE && ival >= 1 && ival <= 16")))
  73
  74 (define_constraint "Ra"
  75   "@internal In Thumb-2 state a constant in range 0 to 7"
  76   (and (match_code "const_int")
  77        (match_test "TARGET_HAVE_MVE && ival >= 0 && ival <= 7")))
  78
  79 (define_constraint "Rb"
  80   "@internal In Thumb-2 state a constant in range 1 to 8"
  81   (and (match_code "const_int")
  82        (match_test "TARGET_HAVE_MVE && ival >= 1 && ival <= 8")))
  83
  84 (define_constraint "Rc"
  85   "@internal In Thumb-2 state a constant in range 0 to 15"
  86   (and (match_code "const_int")
  87        (match_test "TARGET_HAVE_MVE && ival >= 0 && ival <= 15")))
  88
  89 (define_constraint "Re"
  90   "@internal In Thumb-2 state a constant in range 0 to 31"
  91   (and (match_code "const_int")
  92        (match_test "TARGET_HAVE_MVE && ival >= 0 && ival <= 31")))
  93
  94 (define_constraint "Rf"
  95   "@internal In Thumb-2 state a constant in range 1 to 32"
  96   (and (match_code "const_int")
  97        (match_test "TARGET_HAVE_MVE && ival >= 1 && ival <= 32")))
  98
  99 (define_constraint "Rg"
 100   "@internal In Thumb-2 state a constant is one among 1, 2, 4 and 8"
 101   (and (match_code "const_int")
 102        (match_test "TARGET_HAVE_MVE && ((ival == 1) || (ival == 2)
 103                                        || (ival == 4) || (ival == 8))")))
 104
 105 ;; True if the immediate is multiple of 8 and in range of -/+ 1016 for MVE.
 106 (define_predicate "mve_vldrd_immediate"
 107   (match_test "satisfies_constraint_Ri (op)"))
 108
 109 (define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS"
 110  "The VFP registers @code{s0}-@code{s31}.")
 111
 112 (define_register_constraint "w"
 113   "TARGET_32BIT ? (TARGET_VFPD32 ? VFP_REGS : VFP_LO_REGS) : NO_REGS"
 114  "The VFP registers @code{d0}-@code{d15}, or @code{d0}-@code{d31} for VFPv3.")
 115
 116 (define_register_constraint "x" "TARGET_32BIT ? VFP_D0_D7_REGS : NO_REGS"
 117  "The VFP registers @code{d0}-@code{d7}.")
 118
 119 (define_register_constraint "y" "TARGET_REALLY_IWMMXT ? IWMMXT_REGS : NO_REGS"
 120  "The Intel iWMMX co-processor registers.")
 121
 122 (define_register_constraint "z"
 123  "TARGET_REALLY_IWMMXT ? IWMMXT_GR_REGS : NO_REGS"
 124  "The Intel iWMMX GR registers.")
 125
 126 (define_register_constraint "l" "TARGET_THUMB ? LO_REGS : GENERAL_REGS"
 127  "In Thumb state the core registers @code{r0}-@code{r7}.")
 128
 129 (define_register_constraint "h" "TARGET_THUMB ? HI_REGS : NO_REGS"
 130  "In Thumb state the core registers @code{r8}-@code{r15}.")
 131
 132 (define_constraint "j"
 133  "A constant suitable for a MOVW instruction. (ARM/Thumb-2)"
 134  (and (match_test "TARGET_HAVE_MOVT")
 135       (ior (and (match_code "high")
 136                 (match_test "arm_valid_symbolic_address_p (XEXP (op, 0))"))
 137            (and (match_code "const_int")
 138                 (match_test "(ival & 0xffff0000) == 0")))))
 139
 140 (define_constraint "Pj"
 141  "@internal A 12-bit constant suitable for an ADDW or SUBW instruction. (Thumb-2)"
 142  (and (match_code "const_int")
 143       (and (match_test "TARGET_THUMB2")
 144            (match_test "(ival & 0xfffff000) == 0"))))
 145
 146 (define_constraint "PJ"
 147  "@internal A constant that satisfies the Pj constrant if negated."
 148  (and (match_code "const_int")
 149       (and (match_test "TARGET_THUMB2")
 150            (match_test "((-ival) & 0xfffff000) == 0"))))
 151
 152 (define_register_constraint "k" "STACK_REG"
 153  "@internal The stack register.")
 154
 155 (define_register_constraint "b" "TARGET_THUMB ? BASE_REGS : NO_REGS"
 156  "@internal
 157   Thumb only.  The union of the low registers and the stack register.")
 158
 159 (define_constraint "c"
 160  "@internal The condition code register."
 161  (match_operand 0 "cc_register"))
 162
 163 (define_register_constraint "Cs" "CALLER_SAVE_REGS"
 164  "@internal The caller save registers.  Useful for sibcalls.")
 165
 166 (define_constraint "I"
 167  "In ARM/Thumb-2 state a constant that can be used as an immediate value in a
 168   Data Processing instruction.  In Thumb-1 state a constant in the range
 169   0-255."
 170  (and (match_code "const_int")
 171       (match_test "TARGET_32BIT ? const_ok_for_arm (ival)
 172                    : ival >= 0 && ival <= 255")))
 173
 174 (define_constraint "J"
 175  "In ARM/Thumb-2 state a constant in the range @minus{}4095-4095.  In Thumb-1
 176   state a constant in the range @minus{}255-@minus{}1."
 177  (and (match_code "const_int")
 178       (match_test "TARGET_32BIT ? (ival >= -4095 && ival <= 4095)
 179                    : (ival >= -255 && ival <= -1)")))
 180
 181 (define_constraint "K"
 182  "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
 183   inverted.  In Thumb-1 state a constant that satisfies the @code{I}
 184   constraint multiplied by any power of 2."
 185  (and (match_code "const_int")
 186       (match_test "TARGET_32BIT ? const_ok_for_arm (~ival)
 187                    : thumb_shiftable_const (ival)")))
 188
 189 (define_constraint "L"
 190  "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
 191   negated.  In Thumb-1 state a constant in the range @minus{}7-7."
 192  (and (match_code "const_int")
 193       (match_test "TARGET_32BIT ? const_ok_for_arm (-ival)
 194                    : (ival >= -7 && ival <= 7)")))
 195
 196 ;; The ARM state version is internal...
 197 ;; @internal In ARM/Thumb-2 state a constant in the range 0-32 or any
 198 ;; power of 2.
 199 (define_constraint "M"
 200  "In Thumb-1 state a constant that is a multiple of 4 in the range 0-1020."
 201  (and (match_code "const_int")
 202       (match_test "TARGET_32BIT ? ((ival >= 0 && ival <= 32)
 203                                  || (((ival & (ival - 1)) & 0xFFFFFFFF) == 0))
 204                    : ival >= 0 && ival <= 1020 && (ival & 3) == 0")))
 205
 206 (define_constraint "N"
 207  "Thumb-1 state a constant in the range 0-31."
 208  (and (match_code "const_int")
 209       (match_test "!TARGET_32BIT && (ival >= 0 && ival <= 31)")))
 210
 211 (define_constraint "O"
 212  "In Thumb-1 state a constant that is a multiple of 4 in the range
 213   @minus{}508-508."
 214  (and (match_code "const_int")
 215       (match_test "TARGET_THUMB1 && ival >= -508 && ival <= 508
 216                    && ((ival & 3) == 0)")))
 217
 218 (define_constraint "Pa"
 219   "@internal In Thumb-1 state a constant in the range -510 to +510"
 220   (and (match_code "const_int")
 221        (match_test "TARGET_THUMB1 && ival >= -510 && ival <= 510
 222                     && (ival > 255 || ival < -255)")))
 223
 224 (define_constraint "Pb"
 225   "@internal In Thumb-1 state a constant in the range -262 to +262"
 226   (and (match_code "const_int")
 227        (match_test "TARGET_THUMB1 && ival >= -262 && ival <= 262
 228                     && (ival > 255 || ival < -255)")))
 229
 230 (define_constraint "Pc"
 231   "@internal In Thumb-1 state a constant that is in the range 1021 to 1275"
 232   (and (match_code "const_int")
 233        (match_test "TARGET_THUMB1
 234                     && ival > 1020 && ival <= 1275")))
 235
 236 (define_constraint "Pd"
 237   "@internal In Thumb state a constant in the range 0 to 7"
 238   (and (match_code "const_int")
 239        (match_test "TARGET_THUMB && ival >= 0 && ival <= 7")))
 240
 241 (define_constraint "Pe"
 242   "@internal In Thumb-1 state a constant in the range 256 to +510"
 243   (and (match_code "const_int")
 244        (match_test "TARGET_THUMB1 && ival >= 256 && ival <= 510")))
 245
 246 (define_constraint "Pf"
 247   "Memory models except relaxed, consume or release ones."
 248   (and (match_code "const_int")
 249        (match_test "!is_mm_relaxed (memmodel_from_int (ival))
 250                     && !is_mm_consume (memmodel_from_int (ival))
 251                     && !is_mm_release (memmodel_from_int (ival))")))
 252
 253 (define_constraint "Pg"
 254   "@internal In Thumb-2 state a constant in range 1 to 32"
 255   (and (match_code "const_int")
 256        (match_test "TARGET_THUMB2 && ival >= 1 && ival <= 32")))
 257
 258 (define_constraint "Ps"
 259   "@internal In Thumb-2 state a constant in the range -255 to +255"
 260   (and (match_code "const_int")
 261        (match_test "TARGET_THUMB2 && ival >= -255 && ival <= 255")))
 262
 263 (define_constraint "Pt"
 264   "@internal In Thumb-2 state a constant in the range -7 to +7"
 265   (and (match_code "const_int")
 266        (match_test "TARGET_THUMB2 && ival >= -7 && ival <= 7")))
 267
 268 (define_constraint "Pu"
 269   "@internal In Thumb-2 state a constant in the range +1 to +8"
 270   (and (match_code "const_int")
 271        (match_test "TARGET_THUMB2 && ival >= 1 && ival <= 8")))
 272
 273 (define_constraint "Pv"
 274   "@internal In Thumb-2 state a constant in the range -255 to 0"
 275   (and (match_code "const_int")
 276        (match_test "TARGET_THUMB2 && ival >= -255 && ival <= 0")))
 277
 278 (define_constraint "Pw"
 279   "@internal In Thumb-2 state a constant in the range -255 to -1"
 280   (and (match_code "const_int")
 281        (match_test "TARGET_THUMB2 && ival >= -255 && ival <= -1")))
 282
 283 (define_constraint "Px"
 284   "@internal In Thumb-2 state a constant in the range -7 to -1"
 285   (and (match_code "const_int")
 286        (match_test "TARGET_THUMB2 && ival >= -7 && ival <= -1")))
 287
 288 (define_constraint "Py"
 289   "@internal In Thumb-2 state a constant in the range 0 to 255"
 290   (and (match_code "const_int")
 291        (match_test "TARGET_THUMB2 && ival >= 0 && ival <= 255")))
 292
 293 (define_constraint "Pz"
 294   "@internal In Thumb-2 state the constant 0"
 295   (and (match_code "const_int")
 296        (match_test "TARGET_THUMB2 && (ival == 0)")))
 297
 298 (define_constraint "G"
 299  "In ARM/Thumb-2 state the floating-point constant 0."
 300  (and (match_code "const_double")
 301       (match_test "TARGET_32BIT && arm_const_double_rtx (op)")))
 302
 303 (define_constraint "Ha"
 304   "@internal In ARM / Thumb-2 a float constant iff literal pools are allowed."
 305   (and (match_code "const_double")
 306        (match_test "satisfies_constraint_E (op)")
 307        (match_test "!arm_disable_literal_pool")))
 308
 309 (define_constraint "Dz"
 310  "@internal
 311   In ARM/Thumb-2 state a vector of constant zeros."
 312  (and (match_code "const_vector")
 313       (match_test "(TARGET_NEON || TARGET_HAVE_MVE) && op == CONST0_RTX (mode)")))
 314
 315 (define_constraint "Da"
 316  "@internal
 317   In ARM/Thumb-2 state a const_int, const_double or const_vector that can
 318   be generated with two Data Processing insns."
 319  (and (match_code "const_double,const_int,const_vector")
 320       (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 2")))
 321
 322 (define_constraint "Db"
 323  "@internal
 324   In ARM/Thumb-2 state a const_int, const_double or const_vector that can
 325   be generated with three Data Processing insns."
 326  (and (match_code "const_double,const_int,const_vector")
 327       (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 3")))
 328
 329 (define_constraint "Dc"
 330  "@internal
 331   In ARM/Thumb-2 state a const_int, const_double or const_vector that can
 332   be generated with four Data Processing insns.  This pattern is disabled
 333   if optimizing for space or when we have load-delay slots to fill."
 334  (and (match_code "const_double,const_int,const_vector")
 335       (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 4
 336                    && !(optimize_size || arm_ld_sched)")))
 337
 338 (define_constraint "Dd"
 339  "@internal
 340   In ARM/Thumb-2 state a const_int that can be used by insn adddi."
 341  (and (match_code "const_int")
 342       (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, PLUS)")))
 343
 344 (define_constraint "Di"
 345  "@internal
 346   In ARM/Thumb-2 state a const_int or const_double where both the high
 347   and low SImode words can be generated as immediates in 32-bit instructions."
 348  (and (match_code "const_double,const_int")
 349       (match_test "TARGET_32BIT && arm_const_double_by_immediates (op)")))
 350
 351 (define_constraint "Dm"
 352  "@internal
 353   In ARM/Thumb-2 state a const_vector which can be loaded with a Neon vmov
 354   immediate instruction."
 355  (and (match_code "const_vector")
 356       (match_test "TARGET_32BIT
 357                    && imm_for_neon_mov_operand (op, GET_MODE (op))")))
 358
 359 (define_constraint "Dn"
 360  "@internal
 361   In ARM/Thumb-2 state a DImode const_int which can be loaded with a Neon vmov
 362   immediate instruction."
 363  (and (match_code "const_int")
 364       (match_test "TARGET_32BIT && imm_for_neon_mov_operand (op, DImode)")))
 365
 366 (define_constraint "DN"
 367  "@internal
 368   In ARM/Thumb-2 state a TImode const_int which can be loaded with a Neon vmov
 369   immediate instruction."
 370  (and (match_code "const_int")
 371       (match_test "TARGET_32BIT && imm_for_neon_mov_operand (op, TImode)")))
 372
 373 (define_constraint "Dl"
 374  "@internal
 375   In ARM/Thumb-2 state a const_vector which can be used with a Neon vorr or
 376   vbic instruction."
 377  (and (match_code "const_vector")
 378       (match_test "TARGET_32BIT
 379                    && imm_for_neon_logic_operand (op, GET_MODE (op))")))
 380
 381 (define_constraint "DL"
 382  "@internal
 383   In ARM/Thumb-2 state a const_vector which can be used with a Neon vorn or
 384   vand instruction."
 385  (and (match_code "const_vector")
 386       (match_test "TARGET_32BIT
 387                    && imm_for_neon_inv_logic_operand (op, GET_MODE (op))")))
 388
 389 (define_constraint "Do"
 390  "@internal
 391   In ARM/Thumb2 state valid offset for an ldrd/strd instruction."
 392  (and (match_code "const_int")
 393       (match_test "TARGET_LDRD && offset_ok_for_ldrd_strd (ival)")))
 394
 395 (define_constraint "Dv"
 396  "@internal
 397   In ARM/Thumb-2 state a const_double which can be used with a VFP fconsts
 398   instruction."
 399  (and (match_code "const_double")
 400       (match_test "TARGET_32BIT && vfp3_const_double_rtx (op)")))
 401
 402 (define_constraint "Dy"
 403  "@internal
 404   In ARM/Thumb-2 state a const_double which can be used with a VFP fconstd
 405   instruction."
 406  (and (match_code "const_double")
 407       (match_test "TARGET_32BIT && TARGET_VFP_DOUBLE && vfp3_const_double_rtx (op)")))
 408
 409 (define_constraint "Dt"
 410  "@internal
 411   In ARM/ Thumb2 a const_double which can be used with a vcvt.f32.s32 with fract bits operation"
 412   (and (match_code "const_double")
 413        (match_test "TARGET_32BIT && vfp3_const_double_for_fract_bits (op)")))
 414
 415 (define_constraint "Dp"
 416  "@internal
 417   In ARM/ Thumb2 a const_double which can be used with a vcvt.s32.f32 with bits operation"
 418   (and (match_code "const_double")
 419        (match_test "TARGET_32BIT
 420                     && vfp3_const_double_for_bits (op) > 0")))
 421
 422 (define_constraint "Tu"
 423   "@internal In ARM / Thumb-2 an integer constant iff literal pools are
 424    allowed."
 425   (and (match_test "CONSTANT_P (op)")
 426        (match_test "!arm_disable_literal_pool")))
 427
 428 (define_register_constraint "Ts" "(arm_restrict_it) ? LO_REGS : GENERAL_REGS"
 429  "For arm_restrict_it the core registers @code{r0}-@code{r7}.  GENERAL_REGS otherwise.")
 430
 431 (define_memory_constraint "Ua"
 432  "@internal
 433   An address valid for loading/storing register exclusive"
 434  (match_operand 0 "mem_noofs_operand"))
 435
 436 (define_memory_constraint "Uh"
 437  "@internal
 438   An address suitable for byte and half-word loads which does not point inside a constant pool"
 439  (and (match_code "mem")
 440       (match_test "arm_legitimate_address_p (GET_MODE (op), XEXP (op, 0), false) && !arm_is_constant_pool_ref (op)")))
 441
 442 (define_memory_constraint "Ut"
 443  "@internal
 444   In ARM/Thumb-2 state an address valid for loading/storing opaque structure
 445   types wider than TImode."
 446  (and (match_code "mem")
 447       (match_test "TARGET_32BIT && neon_struct_mem_operand (op)")))
 448
 449 (define_memory_constraint "Uv"
 450  "@internal
 451   In ARM/Thumb-2 state a valid VFP load/store address."
 452  (and (match_code "mem")
 453       (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, FALSE)")))
 454
 455 (define_memory_constraint "Uj"
 456  "@internal
 457   In ARM/Thumb-2 state a VFP load/store address that supports writeback
 458   for Neon but not for MVE"
 459  (and (match_code "mem")
 460       (match_test "TARGET_32BIT")
 461       (match_test "TARGET_HAVE_MVE
 462                    ? arm_coproc_mem_operand_no_writeback (op)
 463                    : neon_vector_mem_operand (op, 2, true)")))
 464
 465 (define_memory_constraint "Uy"
 466  "@internal
 467   In ARM/Thumb-2 state a valid iWMMX load/store address."
 468  (and (match_code "mem")
 469       (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, TRUE)")))
 470
 471 (define_memory_constraint "Un"
 472  "@internal
 473   In ARM/Thumb-2 state a valid address for Neon doubleword vector
 474   load/store instructions."
 475  (and (match_code "mem")
 476       (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 0, true)")))
 477
 478 (define_memory_constraint "Um"
 479  "@internal
 480   In ARM/Thumb-2 state a valid address for Neon element and structure
 481   load/store instructions."
 482  (and (match_code "mem")
 483       (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, true)")))
 484
 485 (define_memory_constraint "Us"
 486  "@internal
 487   In ARM/Thumb-2 state a valid address for non-offset loads/stores of
 488   quad-word values in four ARM registers."
 489  (and (match_code "mem")
 490       (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 1, true)")))
 491
 492 (define_memory_constraint "Ux"
 493  "@internal
 494   In ARM/Thumb-2 state a valid address and load into CORE regs or only to
 495   LO_REGS based on mode of op."
 496  (and (match_code "mem")
 497       (match_test "(TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT)
 498                    && mve_vector_mem_operand (GET_MODE (op),
 499                                               XEXP (op, 0), true)")))
 500
 501 (define_memory_constraint "Uq"
 502  "@internal
 503   In ARM state an address valid in ldrsb instructions."
 504  (and (match_code "mem")
 505       (match_test "TARGET_ARM
 506                    && arm_legitimate_address_outer_p (GET_MODE (op), XEXP (op, 0),
 507                                                       SIGN_EXTEND, 0)
 508                    && !arm_is_constant_pool_ref (op)")))
 509
 510 (define_memory_constraint "Q"
 511  "@internal
 512   An address that is a single base register."
 513  (and (match_code "mem")
 514       (match_test "REG_P (XEXP (op, 0))")))
 515
 516 (define_memory_constraint "Uu"
 517  "@internal
 518   In Thumb state an address that is valid in 16bit encoding."
 519  (and (match_code "mem")
 520       (match_test "TARGET_THUMB
 521                    && thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
 522                                                    0)")))
 523
 524 ; The 16-bit post-increment LDR/STR accepted by thumb1_legitimate_address_p
 525 ; are actually LDM/STM instructions, so cannot be used to access unaligned
 526 ; data.
 527 (define_memory_constraint "Uw"
 528  "@internal
 529   In Thumb state an address that is valid in 16bit encoding, and that can be
 530   used for unaligned accesses."
 531  (and (match_code "mem")
 532       (match_test "TARGET_THUMB
 533                    && thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
 534                                                    0)
 535                    && GET_CODE (XEXP (op, 0)) != POST_INC")))
 536
 537 (define_constraint "US"
 538  "@internal
 539   US is a symbol reference."
 540  (match_code "symbol_ref")
 541 )
 542
 543 (define_memory_constraint "Uz"
 544  "@internal
 545   A memory access that is accessible as an LDC/STC operand"
 546  (and (match_code "mem")
 547       (match_test "arm_coproc_ldc_stc_legitimate_address (op)")))
 548
 549 ;; We used to have constraint letters for S and R in ARM state, but
 550 ;; all uses of these now appear to have been removed.
 551
 552 ;; Additionally, we used to have a Q constraint in Thumb state, but
 553 ;; this wasn't really a valid memory constraint.  Again, all uses of
 554 ;; this now seem to have been removed.
 555