gcc/config/arm/constraints.md

   1 ;; Constraint definitions for ARM and Thumb
   2 ;; Copyright (C) 2006-2019 Free Software Foundation, Inc.
   3 ;; Contributed by ARM Ltd.
   4
   5 ;; This file is part of GCC.
   6
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published
   9 ;; by the Free Software Foundation; either version 3, or (at your
  10 ;; option) any later version.
  11
  12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ;; License for more details.
  16
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 ;; The following register constraints have been used:
  22 ;; - in ARM/Thumb-2 state: t, w, x, y, z
  23 ;; - in Thumb state: h, b
  24 ;; - in both states: l, c, k, q, Cs, Ts, US
  25 ;; In ARM state, 'l' is an alias for 'r'
  26 ;; 'f' and 'v' were previously used for FPA and MAVERICK registers.
  27
  28 ;; The following normal constraints have been used:
  29 ;; in ARM/Thumb-2 state: G, I, j, J, K, L, M
  30 ;; in Thumb-1 state: I, J, K, L, M, N, O
  31 ;; 'H' was previously used for FPA.
  32
  33 ;; The following multi-letter normal constraints have been used:
  34 ;; in ARM/Thumb-2 state: Da, Db, Dc, Dd, Dn, Dl, DL, Do, Dv, Dy, Di, Dt, Dp,
  35 ;;                       Dz, Tu
  36 ;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe
  37 ;; in Thumb-2 state: Ha, Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py, Pz
  38 ;; in all states: Pf
  39
  40 ;; The following memory constraints have been used:
  41 ;; in ARM/Thumb-2 state: Uh, Ut, Uv, Uy, Un, Um, Us
  42 ;; in ARM state: Uq
  43 ;; in Thumb state: Uu, Uw
  44 ;; in all states: Q
  45
  46
  47 (define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS"
  48  "The VFP registers @code{s0}-@code{s31}.")
  49
  50 (define_register_constraint "w"
  51   "TARGET_32BIT ? (TARGET_VFPD32 ? VFP_REGS : VFP_LO_REGS) : NO_REGS"
  52  "The VFP registers @code{d0}-@code{d15}, or @code{d0}-@code{d31} for VFPv3.")
  53
  54 (define_register_constraint "x" "TARGET_32BIT ? VFP_D0_D7_REGS : NO_REGS"
  55  "The VFP registers @code{d0}-@code{d7}.")
  56
  57 (define_register_constraint "y" "TARGET_REALLY_IWMMXT ? IWMMXT_REGS : NO_REGS"
  58  "The Intel iWMMX co-processor registers.")
  59
  60 (define_register_constraint "z"
  61  "TARGET_REALLY_IWMMXT ? IWMMXT_GR_REGS : NO_REGS"
  62  "The Intel iWMMX GR registers.")
  63
  64 (define_register_constraint "l" "TARGET_THUMB ? LO_REGS : GENERAL_REGS"
  65  "In Thumb state the core registers @code{r0}-@code{r7}.")
  66
  67 (define_register_constraint "h" "TARGET_THUMB ? HI_REGS : NO_REGS"
  68  "In Thumb state the core registers @code{r8}-@code{r15}.")
  69
  70 (define_constraint "j"
  71  "A constant suitable for a MOVW instruction. (ARM/Thumb-2)"
  72  (and (match_test "TARGET_HAVE_MOVT")
  73       (ior (and (match_code "high")
  74                 (match_test "arm_valid_symbolic_address_p (XEXP (op, 0))"))
  75            (and (match_code "const_int")
  76                 (match_test "(ival & 0xffff0000) == 0")))))
  77
  78 (define_constraint "Pj"
  79  "@internal A 12-bit constant suitable for an ADDW or SUBW instruction. (Thumb-2)"
  80  (and (match_code "const_int")
  81       (and (match_test "TARGET_THUMB2")
  82            (match_test "(ival & 0xfffff000) == 0"))))
  83
  84 (define_constraint "PJ"
  85  "@internal A constant that satisfies the Pj constrant if negated."
  86  (and (match_code "const_int")
  87       (and (match_test "TARGET_THUMB2")
  88            (match_test "((-ival) & 0xfffff000) == 0"))))
  89
  90 (define_register_constraint "k" "STACK_REG"
  91  "@internal The stack register.")
  92
  93 (define_register_constraint "q" "(TARGET_ARM && TARGET_LDRD) ? CORE_REGS : GENERAL_REGS"
  94   "@internal In ARM state with LDRD support, core registers, otherwise general registers.")
  95
  96 (define_register_constraint "b" "TARGET_THUMB ? BASE_REGS : NO_REGS"
  97  "@internal
  98   Thumb only.  The union of the low registers and the stack register.")
  99
 100 (define_register_constraint "c" "CC_REG"
 101  "@internal The condition code register.")
 102
 103 (define_register_constraint "Cs" "CALLER_SAVE_REGS"
 104  "@internal The caller save registers.  Useful for sibcalls.")
 105
 106 (define_constraint "I"
 107  "In ARM/Thumb-2 state a constant that can be used as an immediate value in a
 108   Data Processing instruction.  In Thumb-1 state a constant in the range
 109   0-255."
 110  (and (match_code "const_int")
 111       (match_test "TARGET_32BIT ? const_ok_for_arm (ival)
 112                    : ival >= 0 && ival <= 255")))
 113
 114 (define_constraint "J"
 115  "In ARM/Thumb-2 state a constant in the range @minus{}4095-4095.  In Thumb-1
 116   state a constant in the range @minus{}255-@minus{}1."
 117  (and (match_code "const_int")
 118       (match_test "TARGET_32BIT ? (ival >= -4095 && ival <= 4095)
 119                    : (ival >= -255 && ival <= -1)")))
 120
 121 (define_constraint "K"
 122  "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
 123   inverted.  In Thumb-1 state a constant that satisfies the @code{I}
 124   constraint multiplied by any power of 2."
 125  (and (match_code "const_int")
 126       (match_test "TARGET_32BIT ? const_ok_for_arm (~ival)
 127                    : thumb_shiftable_const (ival)")))
 128
 129 (define_constraint "L"
 130  "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
 131   negated.  In Thumb-1 state a constant in the range @minus{}7-7."
 132  (and (match_code "const_int")
 133       (match_test "TARGET_32BIT ? const_ok_for_arm (-ival)
 134                    : (ival >= -7 && ival <= 7)")))
 135
 136 ;; The ARM state version is internal...
 137 ;; @internal In ARM/Thumb-2 state a constant in the range 0-32 or any
 138 ;; power of 2.
 139 (define_constraint "M"
 140  "In Thumb-1 state a constant that is a multiple of 4 in the range 0-1020."
 141  (and (match_code "const_int")
 142       (match_test "TARGET_32BIT ? ((ival >= 0 && ival <= 32)
 143                                  || (((ival & (ival - 1)) & 0xFFFFFFFF) == 0))
 144                    : ival >= 0 && ival <= 1020 && (ival & 3) == 0")))
 145
 146 (define_constraint "N"
 147  "Thumb-1 state a constant in the range 0-31."
 148  (and (match_code "const_int")
 149       (match_test "!TARGET_32BIT && (ival >= 0 && ival <= 31)")))
 150
 151 (define_constraint "O"
 152  "In Thumb-1 state a constant that is a multiple of 4 in the range
 153   @minus{}508-508."
 154  (and (match_code "const_int")
 155       (match_test "TARGET_THUMB1 && ival >= -508 && ival <= 508
 156                    && ((ival & 3) == 0)")))
 157
 158 (define_constraint "Pa"
 159   "@internal In Thumb-1 state a constant in the range -510 to +510"
 160   (and (match_code "const_int")
 161        (match_test "TARGET_THUMB1 && ival >= -510 && ival <= 510
 162                     && (ival > 255 || ival < -255)")))
 163
 164 (define_constraint "Pb"
 165   "@internal In Thumb-1 state a constant in the range -262 to +262"
 166   (and (match_code "const_int")
 167        (match_test "TARGET_THUMB1 && ival >= -262 && ival <= 262
 168                     && (ival > 255 || ival < -255)")))
 169
 170 (define_constraint "Pc"
 171   "@internal In Thumb-1 state a constant that is in the range 1021 to 1275"
 172   (and (match_code "const_int")
 173        (match_test "TARGET_THUMB1
 174                     && ival > 1020 && ival <= 1275")))
 175
 176 (define_constraint "Pd"
 177   "@internal In Thumb state a constant in the range 0 to 7"
 178   (and (match_code "const_int")
 179        (match_test "TARGET_THUMB && ival >= 0 && ival <= 7")))
 180
 181 (define_constraint "Pe"
 182   "@internal In Thumb-1 state a constant in the range 256 to +510"
 183   (and (match_code "const_int")
 184        (match_test "TARGET_THUMB1 && ival >= 256 && ival <= 510")))
 185
 186 (define_constraint "Pf"
 187   "Memory models except relaxed, consume or release ones."
 188   (and (match_code "const_int")
 189        (match_test "!is_mm_relaxed (memmodel_from_int (ival))
 190                     && !is_mm_consume (memmodel_from_int (ival))
 191                     && !is_mm_release (memmodel_from_int (ival))")))
 192
 193 (define_constraint "Ps"
 194   "@internal In Thumb-2 state a constant in the range -255 to +255"
 195   (and (match_code "const_int")
 196        (match_test "TARGET_THUMB2 && ival >= -255 && ival <= 255")))
 197
 198 (define_constraint "Pt"
 199   "@internal In Thumb-2 state a constant in the range -7 to +7"
 200   (and (match_code "const_int")
 201        (match_test "TARGET_THUMB2 && ival >= -7 && ival <= 7")))
 202
 203 (define_constraint "Pu"
 204   "@internal In Thumb-2 state a constant in the range +1 to +8"
 205   (and (match_code "const_int")
 206        (match_test "TARGET_THUMB2 && ival >= 1 && ival <= 8")))
 207
 208 (define_constraint "Pv"
 209   "@internal In Thumb-2 state a constant in the range -255 to 0"
 210   (and (match_code "const_int")
 211        (match_test "TARGET_THUMB2 && ival >= -255 && ival <= 0")))
 212
 213 (define_constraint "Pw"
 214   "@internal In Thumb-2 state a constant in the range -255 to -1"
 215   (and (match_code "const_int")
 216        (match_test "TARGET_THUMB2 && ival >= -255 && ival <= -1")))
 217
 218 (define_constraint "Px"
 219   "@internal In Thumb-2 state a constant in the range -7 to -1"
 220   (and (match_code "const_int")
 221        (match_test "TARGET_THUMB2 && ival >= -7 && ival <= -1")))
 222
 223 (define_constraint "Py"
 224   "@internal In Thumb-2 state a constant in the range 0 to 255"
 225   (and (match_code "const_int")
 226        (match_test "TARGET_THUMB2 && ival >= 0 && ival <= 255")))
 227
 228 (define_constraint "Pz"
 229   "@internal In Thumb-2 state the constant 0"
 230   (and (match_code "const_int")
 231        (match_test "TARGET_THUMB2 && (ival == 0)")))
 232
 233 (define_constraint "G"
 234  "In ARM/Thumb-2 state the floating-point constant 0."
 235  (and (match_code "const_double")
 236       (match_test "TARGET_32BIT && arm_const_double_rtx (op)")))
 237
 238 (define_constraint "Ha"
 239   "@internal In ARM / Thumb-2 a float constant iff literal pools are allowed."
 240   (and (match_code "const_double")
 241        (match_test "satisfies_constraint_E (op)")
 242        (match_test "!arm_disable_literal_pool")))
 243
 244 (define_constraint "Dz"
 245  "@internal
 246   In ARM/Thumb-2 state a vector of constant zeros."
 247  (and (match_code "const_vector")
 248       (match_test "TARGET_NEON && op == CONST0_RTX (mode)")))
 249
 250 (define_constraint "Da"
 251  "@internal
 252   In ARM/Thumb-2 state a const_int, const_double or const_vector that can
 253   be generated with two Data Processing insns."
 254  (and (match_code "const_double,const_int,const_vector")
 255       (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 2")))
 256
 257 (define_constraint "Db"
 258  "@internal
 259   In ARM/Thumb-2 state a const_int, const_double or const_vector that can
 260   be generated with three Data Processing insns."
 261  (and (match_code "const_double,const_int,const_vector")
 262       (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 3")))
 263
 264 (define_constraint "Dc"
 265  "@internal
 266   In ARM/Thumb-2 state a const_int, const_double or const_vector that can
 267   be generated with four Data Processing insns.  This pattern is disabled
 268   if optimizing for space or when we have load-delay slots to fill."
 269  (and (match_code "const_double,const_int,const_vector")
 270       (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 4
 271                    && !(optimize_size || arm_ld_sched)")))
 272
 273 (define_constraint "Dd"
 274  "@internal
 275   In ARM/Thumb-2 state a const_int that can be used by insn adddi."
 276  (and (match_code "const_int")
 277       (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, PLUS)")))
 278
 279 (define_constraint "De"
 280  "@internal
 281   In ARM/Thumb-2 state a const_int that can be used by insn anddi."
 282  (and (match_code "const_int")
 283       (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, AND)")))
 284
 285 (define_constraint "Df"
 286  "@internal
 287   In ARM/Thumb-2 state a const_int that can be used by insn iordi."
 288  (and (match_code "const_int")
 289       (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, IOR)")))
 290
 291 (define_constraint "Dg"
 292  "@internal
 293   In ARM/Thumb-2 state a const_int that can be used by insn xordi."
 294  (and (match_code "const_int")
 295       (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, XOR)")))
 296
 297 (define_constraint "Di"
 298  "@internal
 299   In ARM/Thumb-2 state a const_int or const_double where both the high
 300   and low SImode words can be generated as immediates in 32-bit instructions."
 301  (and (match_code "const_double,const_int")
 302       (match_test "TARGET_32BIT && arm_const_double_by_immediates (op)")))
 303
 304 (define_constraint "Dn"
 305  "@internal
 306   In ARM/Thumb-2 state a const_vector or const_int which can be loaded with a
 307   Neon vmov immediate instruction."
 308  (and (match_code "const_vector,const_int")
 309       (match_test "TARGET_32BIT
 310                    && imm_for_neon_mov_operand (op, GET_MODE (op))")))
 311
 312 (define_constraint "Dl"
 313  "@internal
 314   In ARM/Thumb-2 state a const_vector which can be used with a Neon vorr or
 315   vbic instruction."
 316  (and (match_code "const_vector")
 317       (match_test "TARGET_32BIT
 318                    && imm_for_neon_logic_operand (op, GET_MODE (op))")))
 319
 320 (define_constraint "DL"
 321  "@internal
 322   In ARM/Thumb-2 state a const_vector which can be used with a Neon vorn or
 323   vand instruction."
 324  (and (match_code "const_vector")
 325       (match_test "TARGET_32BIT
 326                    && imm_for_neon_inv_logic_operand (op, GET_MODE (op))")))
 327
 328 (define_constraint "Do"
 329  "@internal
 330   In ARM/Thumb2 state valid offset for an ldrd/strd instruction."
 331  (and (match_code "const_int")
 332       (match_test "TARGET_LDRD && offset_ok_for_ldrd_strd (ival)")))
 333
 334 (define_constraint "Dv"
 335  "@internal
 336   In ARM/Thumb-2 state a const_double which can be used with a VFP fconsts
 337   instruction."
 338  (and (match_code "const_double")
 339       (match_test "TARGET_32BIT && vfp3_const_double_rtx (op)")))
 340
 341 (define_constraint "Dy"
 342  "@internal
 343   In ARM/Thumb-2 state a const_double which can be used with a VFP fconstd
 344   instruction."
 345  (and (match_code "const_double")
 346       (match_test "TARGET_32BIT && TARGET_VFP_DOUBLE && vfp3_const_double_rtx (op)")))
 347
 348 (define_constraint "Dt"
 349  "@internal
 350   In ARM/ Thumb2 a const_double which can be used with a vcvt.f32.s32 with fract bits operation"
 351   (and (match_code "const_double")
 352        (match_test "TARGET_32BIT && vfp3_const_double_for_fract_bits (op)")))
 353
 354 (define_constraint "Dp"
 355  "@internal
 356   In ARM/ Thumb2 a const_double which can be used with a vcvt.s32.f32 with bits operation"
 357   (and (match_code "const_double")
 358        (match_test "TARGET_32BIT
 359                     && vfp3_const_double_for_bits (op) > 0")))
 360
 361 (define_constraint "Tu"
 362   "@internal In ARM / Thumb-2 an integer constant iff literal pools are
 363    allowed."
 364   (and (match_test "CONSTANT_P (op)")
 365        (match_test "!arm_disable_literal_pool")))
 366
 367 (define_register_constraint "Ts" "(arm_restrict_it) ? LO_REGS : GENERAL_REGS"
 368  "For arm_restrict_it the core registers @code{r0}-@code{r7}.  GENERAL_REGS otherwise.")
 369
 370 (define_memory_constraint "Ua"
 371  "@internal
 372   An address valid for loading/storing register exclusive"
 373  (match_operand 0 "mem_noofs_operand"))
 374
 375 (define_memory_constraint "Uh"
 376  "@internal
 377   An address suitable for byte and half-word loads which does not point inside a constant pool"
 378  (and (match_code "mem")
 379       (match_test "arm_legitimate_address_p (GET_MODE (op), XEXP (op, 0), false) && !arm_is_constant_pool_ref (op)")))
 380
 381 (define_memory_constraint "Ut"
 382  "@internal
 383   In ARM/Thumb-2 state an address valid for loading/storing opaque structure
 384   types wider than TImode."
 385  (and (match_code "mem")
 386       (match_test "TARGET_32BIT && neon_struct_mem_operand (op)")))
 387
 388 (define_memory_constraint "Uv"
 389  "@internal
 390   In ARM/Thumb-2 state a valid VFP load/store address."
 391  (and (match_code "mem")
 392       (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, FALSE)")))
 393
 394 (define_memory_constraint "Uy"
 395  "@internal
 396   In ARM/Thumb-2 state a valid iWMMX load/store address."
 397  (and (match_code "mem")
 398       (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, TRUE)")))
 399
 400 (define_memory_constraint "Un"
 401  "@internal
 402   In ARM/Thumb-2 state a valid address for Neon doubleword vector
 403   load/store instructions."
 404  (and (match_code "mem")
 405       (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 0, true)")))
 406
 407 (define_memory_constraint "Um"
 408  "@internal
 409   In ARM/Thumb-2 state a valid address for Neon element and structure
 410   load/store instructions."
 411  (and (match_code "mem")
 412       (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, true)")))
 413
 414 (define_memory_constraint "Us"
 415  "@internal
 416   In ARM/Thumb-2 state a valid address for non-offset loads/stores of
 417   quad-word values in four ARM registers."
 418  (and (match_code "mem")
 419       (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 1, true)")))
 420
 421 (define_memory_constraint "Uq"
 422  "@internal
 423   In ARM state an address valid in ldrsb instructions."
 424  (and (match_code "mem")
 425       (match_test "TARGET_ARM
 426                    && arm_legitimate_address_outer_p (GET_MODE (op), XEXP (op, 0),
 427                                                       SIGN_EXTEND, 0)
 428                    && !arm_is_constant_pool_ref (op)")))
 429
 430 (define_memory_constraint "Q"
 431  "@internal
 432   An address that is a single base register."
 433  (and (match_code "mem")
 434       (match_test "REG_P (XEXP (op, 0))")))
 435
 436 (define_memory_constraint "Uu"
 437  "@internal
 438   In Thumb state an address that is valid in 16bit encoding."
 439  (and (match_code "mem")
 440       (match_test "TARGET_THUMB
 441                    && thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
 442                                                    0)")))
 443
 444 ; The 16-bit post-increment LDR/STR accepted by thumb1_legitimate_address_p
 445 ; are actually LDM/STM instructions, so cannot be used to access unaligned
 446 ; data.
 447 (define_memory_constraint "Uw"
 448  "@internal
 449   In Thumb state an address that is valid in 16bit encoding, and that can be
 450   used for unaligned accesses."
 451  (and (match_code "mem")
 452       (match_test "TARGET_THUMB
 453                    && thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
 454                                                    0)
 455                    && GET_CODE (XEXP (op, 0)) != POST_INC")))
 456
 457 (define_constraint "US"
 458  "@internal
 459   US is a symbol reference."
 460  (match_code "symbol_ref")
 461 )
 462
 463 (define_memory_constraint "Uz"
 464  "@internal
 465   A memory access that is accessible as an LDC/STC operand"
 466  (and (match_code "mem")
 467       (match_test "arm_coproc_ldc_stc_legitimate_address (op)")))
 468
 469 ;; We used to have constraint letters for S and R in ARM state, but
 470 ;; all uses of these now appear to have been removed.
 471
 472 ;; Additionally, we used to have a Q constraint in Thumb state, but
 473 ;; this wasn't really a valid memory constraint.  Again, all uses of
 474 ;; this now seem to have been removed.
 475