gcc/config/arm/constraints.md

   1 ;; Constraint definitions for ARM and Thumb
   2 ;; Copyright (C) 2006-2020 Free Software Foundation, Inc.
   3 ;; Contributed by ARM Ltd.
   4
   5 ;; This file is part of GCC.
   6
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published
   9 ;; by the Free Software Foundation; either version 3, or (at your
  10 ;; option) any later version.
  11
  12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ;; License for more details.
  16
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 ;; The following register constraints have been used:
  22 ;; - in ARM/Thumb-2 state: t, w, x, y, z
  23 ;; - in Thumb state: h, b
  24 ;; - in both states: l, c, k, q, Cs, Ts, US
  25 ;; In ARM state, 'l' is an alias for 'r'
  26 ;; 'f' and 'v' were previously used for FPA and MAVERICK registers.
  27
  28 ;; The following normal constraints have been used:
  29 ;; in ARM/Thumb-2 state: G, I, j, J, K, L, M
  30 ;; in Thumb-1 state: I, J, K, L, M, N, O
  31 ;; 'H' was previously used for FPA.
  32
  33 ;; The following multi-letter normal constraints have been used:
  34 ;; in ARM/Thumb-2 state: Da, Db, Dc, Dd, Dn, DN, Dm, Dl, DL, Do, Dv, Dy, Di,
  35 ;;                       Dt, Dp, Dz, Tu
  36 ;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe
  37 ;; in Thumb-2 state: Ha, Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py, Pz
  38 ;; in all states: Pf, Pg
  39
  40 ;; The following memory constraints have been used:
  41 ;; in ARM/Thumb-2 state: Uh, Ut, Uv, Uy, Un, Um, Us
  42 ;; in ARM state: Uq
  43 ;; in Thumb state: Uu, Uw
  44 ;; in all states: Q
  45
  46
  47 (define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS"
  48  "The VFP registers @code{s0}-@code{s31}.")
  49
  50 (define_register_constraint "w"
  51   "TARGET_32BIT ? (TARGET_VFPD32 ? VFP_REGS : VFP_LO_REGS) : NO_REGS"
  52  "The VFP registers @code{d0}-@code{d15}, or @code{d0}-@code{d31} for VFPv3.")
  53
  54 (define_register_constraint "x" "TARGET_32BIT ? VFP_D0_D7_REGS : NO_REGS"
  55  "The VFP registers @code{d0}-@code{d7}.")
  56
  57 (define_register_constraint "y" "TARGET_REALLY_IWMMXT ? IWMMXT_REGS : NO_REGS"
  58  "The Intel iWMMX co-processor registers.")
  59
  60 (define_register_constraint "z"
  61  "TARGET_REALLY_IWMMXT ? IWMMXT_GR_REGS : NO_REGS"
  62  "The Intel iWMMX GR registers.")
  63
  64 (define_register_constraint "l" "TARGET_THUMB ? LO_REGS : GENERAL_REGS"
  65  "In Thumb state the core registers @code{r0}-@code{r7}.")
  66
  67 (define_register_constraint "h" "TARGET_THUMB ? HI_REGS : NO_REGS"
  68  "In Thumb state the core registers @code{r8}-@code{r15}.")
  69
  70 (define_constraint "j"
  71  "A constant suitable for a MOVW instruction. (ARM/Thumb-2)"
  72  (and (match_test "TARGET_HAVE_MOVT")
  73       (ior (and (match_code "high")
  74                 (match_test "arm_valid_symbolic_address_p (XEXP (op, 0))"))
  75            (and (match_code "const_int")
  76                 (match_test "(ival & 0xffff0000) == 0")))))
  77
  78 (define_constraint "Pj"
  79  "@internal A 12-bit constant suitable for an ADDW or SUBW instruction. (Thumb-2)"
  80  (and (match_code "const_int")
  81       (and (match_test "TARGET_THUMB2")
  82            (match_test "(ival & 0xfffff000) == 0"))))
  83
  84 (define_constraint "PJ"
  85  "@internal A constant that satisfies the Pj constrant if negated."
  86  (and (match_code "const_int")
  87       (and (match_test "TARGET_THUMB2")
  88            (match_test "((-ival) & 0xfffff000) == 0"))))
  89
  90 (define_register_constraint "k" "STACK_REG"
  91  "@internal The stack register.")
  92
  93 (define_register_constraint "b" "TARGET_THUMB ? BASE_REGS : NO_REGS"
  94  "@internal
  95   Thumb only.  The union of the low registers and the stack register.")
  96
  97 (define_constraint "c"
  98  "@internal The condition code register."
  99  (match_operand 0 "cc_register"))
 100
 101 (define_register_constraint "Cs" "CALLER_SAVE_REGS"
 102  "@internal The caller save registers.  Useful for sibcalls.")
 103
 104 (define_constraint "I"
 105  "In ARM/Thumb-2 state a constant that can be used as an immediate value in a
 106   Data Processing instruction.  In Thumb-1 state a constant in the range
 107   0-255."
 108  (and (match_code "const_int")
 109       (match_test "TARGET_32BIT ? const_ok_for_arm (ival)
 110                    : ival >= 0 && ival <= 255")))
 111
 112 (define_constraint "J"
 113  "In ARM/Thumb-2 state a constant in the range @minus{}4095-4095.  In Thumb-1
 114   state a constant in the range @minus{}255-@minus{}1."
 115  (and (match_code "const_int")
 116       (match_test "TARGET_32BIT ? (ival >= -4095 && ival <= 4095)
 117                    : (ival >= -255 && ival <= -1)")))
 118
 119 (define_constraint "K"
 120  "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
 121   inverted.  In Thumb-1 state a constant that satisfies the @code{I}
 122   constraint multiplied by any power of 2."
 123  (and (match_code "const_int")
 124       (match_test "TARGET_32BIT ? const_ok_for_arm (~ival)
 125                    : thumb_shiftable_const (ival)")))
 126
 127 (define_constraint "L"
 128  "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
 129   negated.  In Thumb-1 state a constant in the range @minus{}7-7."
 130  (and (match_code "const_int")
 131       (match_test "TARGET_32BIT ? const_ok_for_arm (-ival)
 132                    : (ival >= -7 && ival <= 7)")))
 133
 134 ;; The ARM state version is internal...
 135 ;; @internal In ARM/Thumb-2 state a constant in the range 0-32 or any
 136 ;; power of 2.
 137 (define_constraint "M"
 138  "In Thumb-1 state a constant that is a multiple of 4 in the range 0-1020."
 139  (and (match_code "const_int")
 140       (match_test "TARGET_32BIT ? ((ival >= 0 && ival <= 32)
 141                                  || (((ival & (ival - 1)) & 0xFFFFFFFF) == 0))
 142                    : ival >= 0 && ival <= 1020 && (ival & 3) == 0")))
 143
 144 (define_constraint "N"
 145  "Thumb-1 state a constant in the range 0-31."
 146  (and (match_code "const_int")
 147       (match_test "!TARGET_32BIT && (ival >= 0 && ival <= 31)")))
 148
 149 (define_constraint "O"
 150  "In Thumb-1 state a constant that is a multiple of 4 in the range
 151   @minus{}508-508."
 152  (and (match_code "const_int")
 153       (match_test "TARGET_THUMB1 && ival >= -508 && ival <= 508
 154                    && ((ival & 3) == 0)")))
 155
 156 (define_constraint "Pa"
 157   "@internal In Thumb-1 state a constant in the range -510 to +510"
 158   (and (match_code "const_int")
 159        (match_test "TARGET_THUMB1 && ival >= -510 && ival <= 510
 160                     && (ival > 255 || ival < -255)")))
 161
 162 (define_constraint "Pb"
 163   "@internal In Thumb-1 state a constant in the range -262 to +262"
 164   (and (match_code "const_int")
 165        (match_test "TARGET_THUMB1 && ival >= -262 && ival <= 262
 166                     && (ival > 255 || ival < -255)")))
 167
 168 (define_constraint "Pc"
 169   "@internal In Thumb-1 state a constant that is in the range 1021 to 1275"
 170   (and (match_code "const_int")
 171        (match_test "TARGET_THUMB1
 172                     && ival > 1020 && ival <= 1275")))
 173
 174 (define_constraint "Pd"
 175   "@internal In Thumb state a constant in the range 0 to 7"
 176   (and (match_code "const_int")
 177        (match_test "TARGET_THUMB && ival >= 0 && ival <= 7")))
 178
 179 (define_constraint "Pe"
 180   "@internal In Thumb-1 state a constant in the range 256 to +510"
 181   (and (match_code "const_int")
 182        (match_test "TARGET_THUMB1 && ival >= 256 && ival <= 510")))
 183
 184 (define_constraint "Pf"
 185   "Memory models except relaxed, consume or release ones."
 186   (and (match_code "const_int")
 187        (match_test "!is_mm_relaxed (memmodel_from_int (ival))
 188                     && !is_mm_consume (memmodel_from_int (ival))
 189                     && !is_mm_release (memmodel_from_int (ival))")))
 190
 191 (define_constraint "Pg"
 192   "@internal In Thumb-2 state a constant in range 1 to 32"
 193   (and (match_code "const_int")
 194        (match_test "TARGET_THUMB2 && ival >= 1 && ival <= 32")))
 195
 196 (define_constraint "Ps"
 197   "@internal In Thumb-2 state a constant in the range -255 to +255"
 198   (and (match_code "const_int")
 199        (match_test "TARGET_THUMB2 && ival >= -255 && ival <= 255")))
 200
 201 (define_constraint "Pt"
 202   "@internal In Thumb-2 state a constant in the range -7 to +7"
 203   (and (match_code "const_int")
 204        (match_test "TARGET_THUMB2 && ival >= -7 && ival <= 7")))
 205
 206 (define_constraint "Pu"
 207   "@internal In Thumb-2 state a constant in the range +1 to +8"
 208   (and (match_code "const_int")
 209        (match_test "TARGET_THUMB2 && ival >= 1 && ival <= 8")))
 210
 211 (define_constraint "Pv"
 212   "@internal In Thumb-2 state a constant in the range -255 to 0"
 213   (and (match_code "const_int")
 214        (match_test "TARGET_THUMB2 && ival >= -255 && ival <= 0")))
 215
 216 (define_constraint "Pw"
 217   "@internal In Thumb-2 state a constant in the range -255 to -1"
 218   (and (match_code "const_int")
 219        (match_test "TARGET_THUMB2 && ival >= -255 && ival <= -1")))
 220
 221 (define_constraint "Px"
 222   "@internal In Thumb-2 state a constant in the range -7 to -1"
 223   (and (match_code "const_int")
 224        (match_test "TARGET_THUMB2 && ival >= -7 && ival <= -1")))
 225
 226 (define_constraint "Py"
 227   "@internal In Thumb-2 state a constant in the range 0 to 255"
 228   (and (match_code "const_int")
 229        (match_test "TARGET_THUMB2 && ival >= 0 && ival <= 255")))
 230
 231 (define_constraint "Pz"
 232   "@internal In Thumb-2 state the constant 0"
 233   (and (match_code "const_int")
 234        (match_test "TARGET_THUMB2 && (ival == 0)")))
 235
 236 (define_constraint "G"
 237  "In ARM/Thumb-2 state the floating-point constant 0."
 238  (and (match_code "const_double")
 239       (match_test "TARGET_32BIT && arm_const_double_rtx (op)")))
 240
 241 (define_constraint "Ha"
 242   "@internal In ARM / Thumb-2 a float constant iff literal pools are allowed."
 243   (and (match_code "const_double")
 244        (match_test "satisfies_constraint_E (op)")
 245        (match_test "!arm_disable_literal_pool")))
 246
 247 (define_constraint "Dz"
 248  "@internal
 249   In ARM/Thumb-2 state a vector of constant zeros."
 250  (and (match_code "const_vector")
 251       (match_test "TARGET_NEON && op == CONST0_RTX (mode)")))
 252
 253 (define_constraint "Da"
 254  "@internal
 255   In ARM/Thumb-2 state a const_int, const_double or const_vector that can
 256   be generated with two Data Processing insns."
 257  (and (match_code "const_double,const_int,const_vector")
 258       (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 2")))
 259
 260 (define_constraint "Db"
 261  "@internal
 262   In ARM/Thumb-2 state a const_int, const_double or const_vector that can
 263   be generated with three Data Processing insns."
 264  (and (match_code "const_double,const_int,const_vector")
 265       (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 3")))
 266
 267 (define_constraint "Dc"
 268  "@internal
 269   In ARM/Thumb-2 state a const_int, const_double or const_vector that can
 270   be generated with four Data Processing insns.  This pattern is disabled
 271   if optimizing for space or when we have load-delay slots to fill."
 272  (and (match_code "const_double,const_int,const_vector")
 273       (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 4
 274                    && !(optimize_size || arm_ld_sched)")))
 275
 276 (define_constraint "Dd"
 277  "@internal
 278   In ARM/Thumb-2 state a const_int that can be used by insn adddi."
 279  (and (match_code "const_int")
 280       (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, PLUS)")))
 281
 282 (define_constraint "Di"
 283  "@internal
 284   In ARM/Thumb-2 state a const_int or const_double where both the high
 285   and low SImode words can be generated as immediates in 32-bit instructions."
 286  (and (match_code "const_double,const_int")
 287       (match_test "TARGET_32BIT && arm_const_double_by_immediates (op)")))
 288
 289 (define_constraint "Dm"
 290  "@internal
 291   In ARM/Thumb-2 state a const_vector which can be loaded with a Neon vmov
 292   immediate instruction."
 293  (and (match_code "const_vector")
 294       (match_test "TARGET_32BIT
 295                    && imm_for_neon_mov_operand (op, GET_MODE (op))")))
 296
 297 (define_constraint "Dn"
 298  "@internal
 299   In ARM/Thumb-2 state a DImode const_int which can be loaded with a Neon vmov
 300   immediate instruction."
 301  (and (match_code "const_int")
 302       (match_test "TARGET_32BIT && imm_for_neon_mov_operand (op, DImode)")))
 303
 304 (define_constraint "DN"
 305  "@internal
 306   In ARM/Thumb-2 state a TImode const_int which can be loaded with a Neon vmov
 307   immediate instruction."
 308  (and (match_code "const_int")
 309       (match_test "TARGET_32BIT && imm_for_neon_mov_operand (op, TImode)")))
 310
 311 (define_constraint "Dl"
 312  "@internal
 313   In ARM/Thumb-2 state a const_vector which can be used with a Neon vorr or
 314   vbic instruction."
 315  (and (match_code "const_vector")
 316       (match_test "TARGET_32BIT
 317                    && imm_for_neon_logic_operand (op, GET_MODE (op))")))
 318
 319 (define_constraint "DL"
 320  "@internal
 321   In ARM/Thumb-2 state a const_vector which can be used with a Neon vorn or
 322   vand instruction."
 323  (and (match_code "const_vector")
 324       (match_test "TARGET_32BIT
 325                    && imm_for_neon_inv_logic_operand (op, GET_MODE (op))")))
 326
 327 (define_constraint "Do"
 328  "@internal
 329   In ARM/Thumb2 state valid offset for an ldrd/strd instruction."
 330  (and (match_code "const_int")
 331       (match_test "TARGET_LDRD && offset_ok_for_ldrd_strd (ival)")))
 332
 333 (define_constraint "Dv"
 334  "@internal
 335   In ARM/Thumb-2 state a const_double which can be used with a VFP fconsts
 336   instruction."
 337  (and (match_code "const_double")
 338       (match_test "TARGET_32BIT && vfp3_const_double_rtx (op)")))
 339
 340 (define_constraint "Dy"
 341  "@internal
 342   In ARM/Thumb-2 state a const_double which can be used with a VFP fconstd
 343   instruction."
 344  (and (match_code "const_double")
 345       (match_test "TARGET_32BIT && TARGET_VFP_DOUBLE && vfp3_const_double_rtx (op)")))
 346
 347 (define_constraint "Dt"
 348  "@internal
 349   In ARM/ Thumb2 a const_double which can be used with a vcvt.f32.s32 with fract bits operation"
 350   (and (match_code "const_double")
 351        (match_test "TARGET_32BIT && vfp3_const_double_for_fract_bits (op)")))
 352
 353 (define_constraint "Dp"
 354  "@internal
 355   In ARM/ Thumb2 a const_double which can be used with a vcvt.s32.f32 with bits operation"
 356   (and (match_code "const_double")
 357        (match_test "TARGET_32BIT
 358                     && vfp3_const_double_for_bits (op) > 0")))
 359
 360 (define_constraint "Tu"
 361   "@internal In ARM / Thumb-2 an integer constant iff literal pools are
 362    allowed."
 363   (and (match_test "CONSTANT_P (op)")
 364        (match_test "!arm_disable_literal_pool")))
 365
 366 (define_register_constraint "Ts" "(arm_restrict_it) ? LO_REGS : GENERAL_REGS"
 367  "For arm_restrict_it the core registers @code{r0}-@code{r7}.  GENERAL_REGS otherwise.")
 368
 369 (define_memory_constraint "Ua"
 370  "@internal
 371   An address valid for loading/storing register exclusive"
 372  (match_operand 0 "mem_noofs_operand"))
 373
 374 (define_memory_constraint "Uh"
 375  "@internal
 376   An address suitable for byte and half-word loads which does not point inside a constant pool"
 377  (and (match_code "mem")
 378       (match_test "arm_legitimate_address_p (GET_MODE (op), XEXP (op, 0), false) && !arm_is_constant_pool_ref (op)")))
 379
 380 (define_memory_constraint "Ut"
 381  "@internal
 382   In ARM/Thumb-2 state an address valid for loading/storing opaque structure
 383   types wider than TImode."
 384  (and (match_code "mem")
 385       (match_test "TARGET_32BIT && neon_struct_mem_operand (op)")))
 386
 387 (define_memory_constraint "Uv"
 388  "@internal
 389   In ARM/Thumb-2 state a valid VFP load/store address."
 390  (and (match_code "mem")
 391       (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, FALSE)")))
 392
 393 (define_memory_constraint "Uy"
 394  "@internal
 395   In ARM/Thumb-2 state a valid iWMMX load/store address."
 396  (and (match_code "mem")
 397       (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, TRUE)")))
 398
 399 (define_memory_constraint "Un"
 400  "@internal
 401   In ARM/Thumb-2 state a valid address for Neon doubleword vector
 402   load/store instructions."
 403  (and (match_code "mem")
 404       (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 0, true)")))
 405
 406 (define_memory_constraint "Um"
 407  "@internal
 408   In ARM/Thumb-2 state a valid address for Neon element and structure
 409   load/store instructions."
 410  (and (match_code "mem")
 411       (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, true)")))
 412
 413 (define_memory_constraint "Us"
 414  "@internal
 415   In ARM/Thumb-2 state a valid address for non-offset loads/stores of
 416   quad-word values in four ARM registers."
 417  (and (match_code "mem")
 418       (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 1, true)")))
 419
 420 (define_memory_constraint "Uq"
 421  "@internal
 422   In ARM state an address valid in ldrsb instructions."
 423  (and (match_code "mem")
 424       (match_test "TARGET_ARM
 425                    && arm_legitimate_address_outer_p (GET_MODE (op), XEXP (op, 0),
 426                                                       SIGN_EXTEND, 0)
 427                    && !arm_is_constant_pool_ref (op)")))
 428
 429 (define_memory_constraint "Q"
 430  "@internal
 431   An address that is a single base register."
 432  (and (match_code "mem")
 433       (match_test "REG_P (XEXP (op, 0))")))
 434
 435 (define_memory_constraint "Uu"
 436  "@internal
 437   In Thumb state an address that is valid in 16bit encoding."
 438  (and (match_code "mem")
 439       (match_test "TARGET_THUMB
 440                    && thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
 441                                                    0)")))
 442
 443 ; The 16-bit post-increment LDR/STR accepted by thumb1_legitimate_address_p
 444 ; are actually LDM/STM instructions, so cannot be used to access unaligned
 445 ; data.
 446 (define_memory_constraint "Uw"
 447  "@internal
 448   In Thumb state an address that is valid in 16bit encoding, and that can be
 449   used for unaligned accesses."
 450  (and (match_code "mem")
 451       (match_test "TARGET_THUMB
 452                    && thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
 453                                                    0)
 454                    && GET_CODE (XEXP (op, 0)) != POST_INC")))
 455
 456 (define_constraint "US"
 457  "@internal
 458   US is a symbol reference."
 459  (match_code "symbol_ref")
 460 )
 461
 462 (define_memory_constraint "Uz"
 463  "@internal
 464   A memory access that is accessible as an LDC/STC operand"
 465  (and (match_code "mem")
 466       (match_test "arm_coproc_ldc_stc_legitimate_address (op)")))
 467
 468 ;; We used to have constraint letters for S and R in ARM state, but
 469 ;; all uses of these now appear to have been removed.
 470
 471 ;; Additionally, we used to have a Q constraint in Thumb state, but
 472 ;; this wasn't really a valid memory constraint.  Again, all uses of
 473 ;; this now seem to have been removed.
 474