gcc/config/arm/constraints.md

   1 ;; Constraint definitions for ARM and Thumb
   2 ;; Copyright (C) 2006, 2007, 2008 Free Software Foundation, Inc.
   3 ;; Contributed by ARM Ltd.
   4
   5 ;; This file is part of GCC.
   6
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published
   9 ;; by the Free Software Foundation; either version 3, or (at your
  10 ;; option) any later version.
  11
  12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ;; License for more details.
  16
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 ;; The following register constraints have been used:
  22 ;; - in ARM/Thumb-2 state: f, t, v, w, x, y, z
  23 ;; - in Thumb state: h, b
  24 ;; - in both states: l, c, k
  25 ;; In ARM state, 'l' is an alias for 'r'
  26
  27 ;; The following normal constraints have been used:
  28 ;; in ARM/Thumb-2 state: G, H, I, J, K, L, M
  29 ;; in Thumb-1 state: I, J, K, L, M, N, O
  30
  31 ;; The following multi-letter normal constraints have been used:
  32 ;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv
  33
  34 ;; The following memory constraints have been used:
  35 ;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Us
  36 ;; in ARM state: Uq
  37
  38
  39 (define_register_constraint "f" "TARGET_ARM ? FPA_REGS : NO_REGS"
  40  "Legacy FPA registers @code{f0}-@code{f7}.")
  41
  42 (define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS"
  43  "The VFP registers @code{s0}-@code{s31}.")
  44
  45 (define_register_constraint "v" "TARGET_ARM ? CIRRUS_REGS : NO_REGS"
  46  "The Cirrus Maverick co-processor registers.")
  47
  48 (define_register_constraint "w"
  49   "TARGET_32BIT ? (TARGET_VFPD32 ? VFP_REGS : VFP_LO_REGS) : NO_REGS"
  50  "The VFP registers @code{d0}-@code{d15}, or @code{d0}-@code{d31} for VFPv3.")
  51
  52 (define_register_constraint "x" "TARGET_32BIT ? VFP_D0_D7_REGS : NO_REGS"
  53  "The VFP registers @code{d0}-@code{d7}.")
  54
  55 (define_register_constraint "y" "TARGET_REALLY_IWMMXT ? IWMMXT_REGS : NO_REGS"
  56  "The Intel iWMMX co-processor registers.")
  57
  58 (define_register_constraint "z"
  59  "TARGET_REALLY_IWMMXT ? IWMMXT_GR_REGS : NO_REGS"
  60  "The Intel iWMMX GR registers.")
  61
  62 (define_register_constraint "l" "TARGET_THUMB ? LO_REGS : GENERAL_REGS"
  63  "In Thumb state the core registers @code{r0}-@code{r7}.")
  64
  65 (define_register_constraint "h" "TARGET_THUMB ? HI_REGS : NO_REGS"
  66  "In Thumb state the core registers @code{r8}-@code{r15}.")
  67
  68 (define_register_constraint "k" "STACK_REG"
  69  "@internal The stack register.")
  70
  71 (define_register_constraint "b" "TARGET_THUMB ? BASE_REGS : NO_REGS"
  72  "@internal
  73   Thumb only.  The union of the low registers and the stack register.")
  74
  75 (define_register_constraint "c" "CC_REG"
  76  "@internal The condition code register.")
  77
  78 (define_constraint "I"
  79  "In ARM/Thumb-2 state a constant that can be used as an immediate value in a
  80   Data Processing instruction.  In Thumb-1 state a constant in the range
  81   0-255."
  82  (and (match_code "const_int")
  83       (match_test "TARGET_32BIT ? const_ok_for_arm (ival)
  84                    : ival >= 0 && ival <= 255")))
  85
  86 (define_constraint "J"
  87  "In ARM/Thumb-2 state a constant in the range @minus{}4095-4095.  In Thumb-1
  88   state a constant in the range @minus{}255-@minus{}1."
  89  (and (match_code "const_int")
  90       (match_test "TARGET_32BIT ? (ival >= -4095 && ival <= 4095)
  91                    : (ival >= -255 && ival <= -1)")))
  92
  93 (define_constraint "K"
  94  "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
  95   inverted.  In Thumb-1 state a constant that satisfies the @code{I}
  96   constraint multiplied by any power of 2."
  97  (and (match_code "const_int")
  98       (match_test "TARGET_32BIT ? const_ok_for_arm (~ival)
  99                    : thumb_shiftable_const (ival)")))
 100
 101 (define_constraint "L"
 102  "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
 103   negated.  In Thumb-1 state a constant in the range @minus{}7-7."
 104  (and (match_code "const_int")
 105       (match_test "TARGET_32BIT ? const_ok_for_arm (-ival)
 106                    : (ival >= -7 && ival <= 7)")))
 107
 108 ;; The ARM state version is internal...
 109 ;; @internal In ARM/Thumb-2 state a constant in the range 0-32 or any
 110 ;; power of 2.
 111 (define_constraint "M"
 112  "In Thumb-1 state a constant that is a multiple of 4 in the range 0-1020."
 113  (and (match_code "const_int")
 114       (match_test "TARGET_32BIT ? ((ival >= 0 && ival <= 32)
 115                                  || ((ival & (ival - 1)) == 0))
 116                    : ((ival >= 0 && ival <= 1020) && ((ival & 3) == 0))")))
 117
 118 (define_constraint "N"
 119  "In ARM/Thumb-2 state a constant suitable for a MOVW instruction.
 120   In Thumb-1 state a constant in the range 0-31."
 121  (and (match_code "const_int")
 122       (match_test "TARGET_32BIT ? arm_arch_thumb2 && ((ival & 0xffff0000) == 0)
 123                                 : (ival >= 0 && ival <= 31)")))
 124
 125 (define_constraint "O"
 126  "In Thumb-1 state a constant that is a multiple of 4 in the range
 127   @minus{}508-508."
 128  (and (match_code "const_int")
 129       (match_test "TARGET_THUMB1 && ival >= -508 && ival <= 508
 130                    && ((ival & 3) == 0)")))
 131
 132 (define_constraint "G"
 133  "In ARM/Thumb-2 state a valid FPA immediate constant."
 134  (and (match_code "const_double")
 135       (match_test "TARGET_32BIT && arm_const_double_rtx (op)")))
 136
 137 (define_constraint "H"
 138  "In ARM/Thumb-2 state a valid FPA immediate constant when negated."
 139  (and (match_code "const_double")
 140       (match_test "TARGET_32BIT && neg_const_double_rtx_ok_for_fpa (op)")))
 141
 142 (define_constraint "Da"
 143  "@internal
 144   In ARM/Thumb-2 state a const_int, const_double or const_vector that can
 145   be generated with two Data Processing insns."
 146  (and (match_code "const_double,const_int,const_vector")
 147       (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 2")))
 148
 149 (define_constraint "Db"
 150  "@internal
 151   In ARM/Thumb-2 state a const_int, const_double or const_vector that can
 152   be generated with three Data Processing insns."
 153  (and (match_code "const_double,const_int,const_vector")
 154       (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 3")))
 155
 156 (define_constraint "Dc"
 157  "@internal
 158   In ARM/Thumb-2 state a const_int, const_double or const_vector that can
 159   be generated with four Data Processing insns.  This pattern is disabled
 160   if optimizing for space or when we have load-delay slots to fill."
 161  (and (match_code "const_double,const_int,const_vector")
 162       (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 4
 163                    && !(optimize_size || arm_ld_sched)")))
 164
 165 (define_constraint "Dn"
 166  "@internal
 167   In ARM/Thumb-2 state a const_vector which can be loaded with a Neon vmov
 168   immediate instruction."
 169  (and (match_code "const_vector")
 170       (match_test "TARGET_32BIT
 171                    && imm_for_neon_mov_operand (op, GET_MODE (op))")))
 172
 173 (define_constraint "Dl"
 174  "@internal
 175   In ARM/Thumb-2 state a const_vector which can be used with a Neon vorr or
 176   vbic instruction."
 177  (and (match_code "const_vector")
 178       (match_test "TARGET_32BIT
 179                    && imm_for_neon_logic_operand (op, GET_MODE (op))")))
 180
 181 (define_constraint "DL"
 182  "@internal
 183   In ARM/Thumb-2 state a const_vector which can be used with a Neon vorn or
 184   vand instruction."
 185  (and (match_code "const_vector")
 186       (match_test "TARGET_32BIT
 187                    && imm_for_neon_inv_logic_operand (op, GET_MODE (op))")))
 188
 189 (define_constraint "Dv"
 190  "@internal
 191   In ARM/Thumb-2 state a const_double which can be used with a VFP fconsts
 192   or fconstd instruction."
 193  (and (match_code "const_double")
 194       (match_test "TARGET_32BIT && vfp3_const_double_rtx (op)")))
 195
 196 (define_memory_constraint "Ut"
 197  "@internal
 198   In ARM/Thumb-2 state an address valid for loading/storing opaque structure
 199   types wider than TImode."
 200  (and (match_code "mem")
 201       (match_test "TARGET_32BIT && neon_struct_mem_operand (op)")))
 202
 203 (define_memory_constraint "Uv"
 204  "@internal
 205   In ARM/Thumb-2 state a valid VFP load/store address."
 206  (and (match_code "mem")
 207       (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, FALSE)")))
 208
 209 (define_memory_constraint "Uy"
 210  "@internal
 211   In ARM/Thumb-2 state a valid iWMMX load/store address."
 212  (and (match_code "mem")
 213       (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, TRUE)")))
 214
 215 (define_memory_constraint "Un"
 216  "@internal
 217   In ARM/Thumb-2 state a valid address for Neon element and structure
 218   load/store instructions."
 219  (and (match_code "mem")
 220       (match_test "TARGET_32BIT && neon_vector_mem_operand (op, FALSE)")))
 221
 222 (define_memory_constraint "Us"
 223  "@internal
 224   In ARM/Thumb-2 state a valid address for non-offset loads/stores of
 225   quad-word values in four ARM registers."
 226  (and (match_code "mem")
 227       (match_test "TARGET_32BIT && neon_vector_mem_operand (op, TRUE)")))
 228
 229 (define_memory_constraint "Uq"
 230  "@internal
 231   In ARM state an address valid in ldrsb instructions."
 232  (and (match_code "mem")
 233       (match_test "TARGET_ARM
 234                    && arm_legitimate_address_outer_p (GET_MODE (op), XEXP (op, 0),
 235                                                       SIGN_EXTEND, 0)")))
 236
 237 (define_memory_constraint "Q"
 238  "@internal
 239   In ARM/Thumb-2 state an address that is a single base register."
 240  (and (match_code "mem")
 241       (match_test "REG_P (XEXP (op, 0))")))
 242
 243 ;; We used to have constraint letters for S and R in ARM state, but
 244 ;; all uses of these now appear to have been removed.
 245
 246 ;; Additionally, we used to have a Q constraint in Thumb state, but
 247 ;; this wasn't really a valid memory constraint.  Again, all uses of
 248 ;; this now seem to have been removed.