gcc/config/arm/constraints.md

   1 ;; Constraint definitions for ARM and Thumb
   2 ;; Copyright (C) 2006-2020 Free Software Foundation, Inc.
   3 ;; Contributed by ARM Ltd.
   4
   5 ;; This file is part of GCC.
   6
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published
   9 ;; by the Free Software Foundation; either version 3, or (at your
  10 ;; option) any later version.
  11
  12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ;; License for more details.
  16
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 ;; The following register constraints have been used:
  22 ;; - in ARM/Thumb-2 state: t, w, x, y, z
  23 ;; - in Thumb state: h, b
  24 ;; - in both states: l, c, k, q, Cs, Ts, US
  25 ;; In ARM state, 'l' is an alias for 'r'
  26 ;; 'f' and 'v' were previously used for FPA and MAVERICK registers.
  27
  28 ;; The following normal constraints have been used:
  29 ;; in ARM/Thumb-2 state: G, I, j, J, K, L, M
  30 ;; in Thumb-1 state: I, J, K, L, M, N, O
  31 ;; 'H' was previously used for FPA.
  32
  33 ;; The following multi-letter normal constraints have been used:
  34 ;; in ARM/Thumb-2 state: Da, Db, Dc, Dd, Dn, DN, Dm, Dl, DL, Do, Dv, Dy, Di,
  35 ;;                       Dt, Dp, Dz, Tu
  36 ;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe
  37 ;; in Thumb-2 state: Ha, Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py, Pz
  38 ;; in all states: Pf, Pg
  39
  40 ;; The following memory constraints have been used:
  41 ;; in ARM/Thumb-2 state: Uh, Ut, Uv, Uy, Un, Um, Us, Up, Uf
  42 ;; in ARM state: Uq
  43 ;; in Thumb state: Uu, Uw
  44 ;; in all states: Q
  45
  46 (define_register_constraint "Up" "TARGET_HAVE_MVE ? VPR_REG : NO_REGS"
  47   "MVE VPR register")
  48
  49 (define_register_constraint "Uf" "TARGET_HAVE_MVE ? VFPCC_REG : NO_REGS"
  50   "MVE FPCCR register")
  51
  52 (define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS"
  53  "The VFP registers @code{s0}-@code{s31}.")
  54
  55 (define_register_constraint "w"
  56   "TARGET_32BIT ? (TARGET_VFPD32 ? VFP_REGS : VFP_LO_REGS) : NO_REGS"
  57  "The VFP registers @code{d0}-@code{d15}, or @code{d0}-@code{d31} for VFPv3.")
  58
  59 (define_register_constraint "x" "TARGET_32BIT ? VFP_D0_D7_REGS : NO_REGS"
  60  "The VFP registers @code{d0}-@code{d7}.")
  61
  62 (define_register_constraint "y" "TARGET_REALLY_IWMMXT ? IWMMXT_REGS : NO_REGS"
  63  "The Intel iWMMX co-processor registers.")
  64
  65 (define_register_constraint "z"
  66  "TARGET_REALLY_IWMMXT ? IWMMXT_GR_REGS : NO_REGS"
  67  "The Intel iWMMX GR registers.")
  68
  69 (define_register_constraint "l" "TARGET_THUMB ? LO_REGS : GENERAL_REGS"
  70  "In Thumb state the core registers @code{r0}-@code{r7}.")
  71
  72 (define_register_constraint "h" "TARGET_THUMB ? HI_REGS : NO_REGS"
  73  "In Thumb state the core registers @code{r8}-@code{r15}.")
  74
  75 (define_constraint "j"
  76  "A constant suitable for a MOVW instruction. (ARM/Thumb-2)"
  77  (and (match_test "TARGET_HAVE_MOVT")
  78       (ior (and (match_code "high")
  79                 (match_test "arm_valid_symbolic_address_p (XEXP (op, 0))"))
  80            (and (match_code "const_int")
  81                 (match_test "(ival & 0xffff0000) == 0")))))
  82
  83 (define_constraint "Pj"
  84  "@internal A 12-bit constant suitable for an ADDW or SUBW instruction. (Thumb-2)"
  85  (and (match_code "const_int")
  86       (and (match_test "TARGET_THUMB2")
  87            (match_test "(ival & 0xfffff000) == 0"))))
  88
  89 (define_constraint "PJ"
  90  "@internal A constant that satisfies the Pj constrant if negated."
  91  (and (match_code "const_int")
  92       (and (match_test "TARGET_THUMB2")
  93            (match_test "((-ival) & 0xfffff000) == 0"))))
  94
  95 (define_register_constraint "k" "STACK_REG"
  96  "@internal The stack register.")
  97
  98 (define_register_constraint "b" "TARGET_THUMB ? BASE_REGS : NO_REGS"
  99  "@internal
 100   Thumb only.  The union of the low registers and the stack register.")
 101
 102 (define_constraint "c"
 103  "@internal The condition code register."
 104  (match_operand 0 "cc_register"))
 105
 106 (define_register_constraint "Cs" "CALLER_SAVE_REGS"
 107  "@internal The caller save registers.  Useful for sibcalls.")
 108
 109 (define_constraint "I"
 110  "In ARM/Thumb-2 state a constant that can be used as an immediate value in a
 111   Data Processing instruction.  In Thumb-1 state a constant in the range
 112   0-255."
 113  (and (match_code "const_int")
 114       (match_test "TARGET_32BIT ? const_ok_for_arm (ival)
 115                    : ival >= 0 && ival <= 255")))
 116
 117 (define_constraint "J"
 118  "In ARM/Thumb-2 state a constant in the range @minus{}4095-4095.  In Thumb-1
 119   state a constant in the range @minus{}255-@minus{}1."
 120  (and (match_code "const_int")
 121       (match_test "TARGET_32BIT ? (ival >= -4095 && ival <= 4095)
 122                    : (ival >= -255 && ival <= -1)")))
 123
 124 (define_constraint "K"
 125  "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
 126   inverted.  In Thumb-1 state a constant that satisfies the @code{I}
 127   constraint multiplied by any power of 2."
 128  (and (match_code "const_int")
 129       (match_test "TARGET_32BIT ? const_ok_for_arm (~ival)
 130                    : thumb_shiftable_const (ival)")))
 131
 132 (define_constraint "L"
 133  "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
 134   negated.  In Thumb-1 state a constant in the range @minus{}7-7."
 135  (and (match_code "const_int")
 136       (match_test "TARGET_32BIT ? const_ok_for_arm (-ival)
 137                    : (ival >= -7 && ival <= 7)")))
 138
 139 ;; The ARM state version is internal...
 140 ;; @internal In ARM/Thumb-2 state a constant in the range 0-32 or any
 141 ;; power of 2.
 142 (define_constraint "M"
 143  "In Thumb-1 state a constant that is a multiple of 4 in the range 0-1020."
 144  (and (match_code "const_int")
 145       (match_test "TARGET_32BIT ? ((ival >= 0 && ival <= 32)
 146                                  || (((ival & (ival - 1)) & 0xFFFFFFFF) == 0))
 147                    : ival >= 0 && ival <= 1020 && (ival & 3) == 0")))
 148
 149 (define_constraint "N"
 150  "Thumb-1 state a constant in the range 0-31."
 151  (and (match_code "const_int")
 152       (match_test "!TARGET_32BIT && (ival >= 0 && ival <= 31)")))
 153
 154 (define_constraint "O"
 155  "In Thumb-1 state a constant that is a multiple of 4 in the range
 156   @minus{}508-508."
 157  (and (match_code "const_int")
 158       (match_test "TARGET_THUMB1 && ival >= -508 && ival <= 508
 159                    && ((ival & 3) == 0)")))
 160
 161 (define_constraint "Pa"
 162   "@internal In Thumb-1 state a constant in the range -510 to +510"
 163   (and (match_code "const_int")
 164        (match_test "TARGET_THUMB1 && ival >= -510 && ival <= 510
 165                     && (ival > 255 || ival < -255)")))
 166
 167 (define_constraint "Pb"
 168   "@internal In Thumb-1 state a constant in the range -262 to +262"
 169   (and (match_code "const_int")
 170        (match_test "TARGET_THUMB1 && ival >= -262 && ival <= 262
 171                     && (ival > 255 || ival < -255)")))
 172
 173 (define_constraint "Pc"
 174   "@internal In Thumb-1 state a constant that is in the range 1021 to 1275"
 175   (and (match_code "const_int")
 176        (match_test "TARGET_THUMB1
 177                     && ival > 1020 && ival <= 1275")))
 178
 179 (define_constraint "Pd"
 180   "@internal In Thumb state a constant in the range 0 to 7"
 181   (and (match_code "const_int")
 182        (match_test "TARGET_THUMB && ival >= 0 && ival <= 7")))
 183
 184 (define_constraint "Pe"
 185   "@internal In Thumb-1 state a constant in the range 256 to +510"
 186   (and (match_code "const_int")
 187        (match_test "TARGET_THUMB1 && ival >= 256 && ival <= 510")))
 188
 189 (define_constraint "Pf"
 190   "Memory models except relaxed, consume or release ones."
 191   (and (match_code "const_int")
 192        (match_test "!is_mm_relaxed (memmodel_from_int (ival))
 193                     && !is_mm_consume (memmodel_from_int (ival))
 194                     && !is_mm_release (memmodel_from_int (ival))")))
 195
 196 (define_constraint "Pg"
 197   "@internal In Thumb-2 state a constant in range 1 to 32"
 198   (and (match_code "const_int")
 199        (match_test "TARGET_THUMB2 && ival >= 1 && ival <= 32")))
 200
 201 (define_constraint "Ps"
 202   "@internal In Thumb-2 state a constant in the range -255 to +255"
 203   (and (match_code "const_int")
 204        (match_test "TARGET_THUMB2 && ival >= -255 && ival <= 255")))
 205
 206 (define_constraint "Pt"
 207   "@internal In Thumb-2 state a constant in the range -7 to +7"
 208   (and (match_code "const_int")
 209        (match_test "TARGET_THUMB2 && ival >= -7 && ival <= 7")))
 210
 211 (define_constraint "Pu"
 212   "@internal In Thumb-2 state a constant in the range +1 to +8"
 213   (and (match_code "const_int")
 214        (match_test "TARGET_THUMB2 && ival >= 1 && ival <= 8")))
 215
 216 (define_constraint "Pv"
 217   "@internal In Thumb-2 state a constant in the range -255 to 0"
 218   (and (match_code "const_int")
 219        (match_test "TARGET_THUMB2 && ival >= -255 && ival <= 0")))
 220
 221 (define_constraint "Pw"
 222   "@internal In Thumb-2 state a constant in the range -255 to -1"
 223   (and (match_code "const_int")
 224        (match_test "TARGET_THUMB2 && ival >= -255 && ival <= -1")))
 225
 226 (define_constraint "Px"
 227   "@internal In Thumb-2 state a constant in the range -7 to -1"
 228   (and (match_code "const_int")
 229        (match_test "TARGET_THUMB2 && ival >= -7 && ival <= -1")))
 230
 231 (define_constraint "Py"
 232   "@internal In Thumb-2 state a constant in the range 0 to 255"
 233   (and (match_code "const_int")
 234        (match_test "TARGET_THUMB2 && ival >= 0 && ival <= 255")))
 235
 236 (define_constraint "Pz"
 237   "@internal In Thumb-2 state the constant 0"
 238   (and (match_code "const_int")
 239        (match_test "TARGET_THUMB2 && (ival == 0)")))
 240
 241 (define_constraint "G"
 242  "In ARM/Thumb-2 state the floating-point constant 0."
 243  (and (match_code "const_double")
 244       (match_test "TARGET_32BIT && arm_const_double_rtx (op)")))
 245
 246 (define_constraint "Ha"
 247   "@internal In ARM / Thumb-2 a float constant iff literal pools are allowed."
 248   (and (match_code "const_double")
 249        (match_test "satisfies_constraint_E (op)")
 250        (match_test "!arm_disable_literal_pool")))
 251
 252 (define_constraint "Dz"
 253  "@internal
 254   In ARM/Thumb-2 state a vector of constant zeros."
 255  (and (match_code "const_vector")
 256       (match_test "TARGET_NEON && op == CONST0_RTX (mode)")))
 257
 258 (define_constraint "Da"
 259  "@internal
 260   In ARM/Thumb-2 state a const_int, const_double or const_vector that can
 261   be generated with two Data Processing insns."
 262  (and (match_code "const_double,const_int,const_vector")
 263       (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 2")))
 264
 265 (define_constraint "Db"
 266  "@internal
 267   In ARM/Thumb-2 state a const_int, const_double or const_vector that can
 268   be generated with three Data Processing insns."
 269  (and (match_code "const_double,const_int,const_vector")
 270       (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 3")))
 271
 272 (define_constraint "Dc"
 273  "@internal
 274   In ARM/Thumb-2 state a const_int, const_double or const_vector that can
 275   be generated with four Data Processing insns.  This pattern is disabled
 276   if optimizing for space or when we have load-delay slots to fill."
 277  (and (match_code "const_double,const_int,const_vector")
 278       (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 4
 279                    && !(optimize_size || arm_ld_sched)")))
 280
 281 (define_constraint "Dd"
 282  "@internal
 283   In ARM/Thumb-2 state a const_int that can be used by insn adddi."
 284  (and (match_code "const_int")
 285       (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, PLUS)")))
 286
 287 (define_constraint "Di"
 288  "@internal
 289   In ARM/Thumb-2 state a const_int or const_double where both the high
 290   and low SImode words can be generated as immediates in 32-bit instructions."
 291  (and (match_code "const_double,const_int")
 292       (match_test "TARGET_32BIT && arm_const_double_by_immediates (op)")))
 293
 294 (define_constraint "Dm"
 295  "@internal
 296   In ARM/Thumb-2 state a const_vector which can be loaded with a Neon vmov
 297   immediate instruction."
 298  (and (match_code "const_vector")
 299       (match_test "TARGET_32BIT
 300                    && imm_for_neon_mov_operand (op, GET_MODE (op))")))
 301
 302 (define_constraint "Dn"
 303  "@internal
 304   In ARM/Thumb-2 state a DImode const_int which can be loaded with a Neon vmov
 305   immediate instruction."
 306  (and (match_code "const_int")
 307       (match_test "TARGET_32BIT && imm_for_neon_mov_operand (op, DImode)")))
 308
 309 (define_constraint "DN"
 310  "@internal
 311   In ARM/Thumb-2 state a TImode const_int which can be loaded with a Neon vmov
 312   immediate instruction."
 313  (and (match_code "const_int")
 314       (match_test "TARGET_32BIT && imm_for_neon_mov_operand (op, TImode)")))
 315
 316 (define_constraint "Dl"
 317  "@internal
 318   In ARM/Thumb-2 state a const_vector which can be used with a Neon vorr or
 319   vbic instruction."
 320  (and (match_code "const_vector")
 321       (match_test "TARGET_32BIT
 322                    && imm_for_neon_logic_operand (op, GET_MODE (op))")))
 323
 324 (define_constraint "DL"
 325  "@internal
 326   In ARM/Thumb-2 state a const_vector which can be used with a Neon vorn or
 327   vand instruction."
 328  (and (match_code "const_vector")
 329       (match_test "TARGET_32BIT
 330                    && imm_for_neon_inv_logic_operand (op, GET_MODE (op))")))
 331
 332 (define_constraint "Do"
 333  "@internal
 334   In ARM/Thumb2 state valid offset for an ldrd/strd instruction."
 335  (and (match_code "const_int")
 336       (match_test "TARGET_LDRD && offset_ok_for_ldrd_strd (ival)")))
 337
 338 (define_constraint "Dv"
 339  "@internal
 340   In ARM/Thumb-2 state a const_double which can be used with a VFP fconsts
 341   instruction."
 342  (and (match_code "const_double")
 343       (match_test "TARGET_32BIT && vfp3_const_double_rtx (op)")))
 344
 345 (define_constraint "Dy"
 346  "@internal
 347   In ARM/Thumb-2 state a const_double which can be used with a VFP fconstd
 348   instruction."
 349  (and (match_code "const_double")
 350       (match_test "TARGET_32BIT && TARGET_VFP_DOUBLE && vfp3_const_double_rtx (op)")))
 351
 352 (define_constraint "Dt"
 353  "@internal
 354   In ARM/ Thumb2 a const_double which can be used with a vcvt.f32.s32 with fract bits operation"
 355   (and (match_code "const_double")
 356        (match_test "TARGET_32BIT && vfp3_const_double_for_fract_bits (op)")))
 357
 358 (define_constraint "Dp"
 359  "@internal
 360   In ARM/ Thumb2 a const_double which can be used with a vcvt.s32.f32 with bits operation"
 361   (and (match_code "const_double")
 362        (match_test "TARGET_32BIT
 363                     && vfp3_const_double_for_bits (op) > 0")))
 364
 365 (define_constraint "Tu"
 366   "@internal In ARM / Thumb-2 an integer constant iff literal pools are
 367    allowed."
 368   (and (match_test "CONSTANT_P (op)")
 369        (match_test "!arm_disable_literal_pool")))
 370
 371 (define_register_constraint "Ts" "(arm_restrict_it) ? LO_REGS : GENERAL_REGS"
 372  "For arm_restrict_it the core registers @code{r0}-@code{r7}.  GENERAL_REGS otherwise.")
 373
 374 (define_memory_constraint "Ua"
 375  "@internal
 376   An address valid for loading/storing register exclusive"
 377  (match_operand 0 "mem_noofs_operand"))
 378
 379 (define_memory_constraint "Uh"
 380  "@internal
 381   An address suitable for byte and half-word loads which does not point inside a constant pool"
 382  (and (match_code "mem")
 383       (match_test "arm_legitimate_address_p (GET_MODE (op), XEXP (op, 0), false) && !arm_is_constant_pool_ref (op)")))
 384
 385 (define_memory_constraint "Ut"
 386  "@internal
 387   In ARM/Thumb-2 state an address valid for loading/storing opaque structure
 388   types wider than TImode."
 389  (and (match_code "mem")
 390       (match_test "TARGET_32BIT && neon_struct_mem_operand (op)")))
 391
 392 (define_memory_constraint "Uv"
 393  "@internal
 394   In ARM/Thumb-2 state a valid VFP load/store address."
 395  (and (match_code "mem")
 396       (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, FALSE)")))
 397
 398 (define_memory_constraint "Uy"
 399  "@internal
 400   In ARM/Thumb-2 state a valid iWMMX load/store address."
 401  (and (match_code "mem")
 402       (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, TRUE)")))
 403
 404 (define_memory_constraint "Un"
 405  "@internal
 406   In ARM/Thumb-2 state a valid address for Neon doubleword vector
 407   load/store instructions."
 408  (and (match_code "mem")
 409       (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 0, true)")))
 410
 411 (define_memory_constraint "Um"
 412  "@internal
 413   In ARM/Thumb-2 state a valid address for Neon element and structure
 414   load/store instructions."
 415  (and (match_code "mem")
 416       (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, true)")))
 417
 418 (define_memory_constraint "Us"
 419  "@internal
 420   In ARM/Thumb-2 state a valid address for non-offset loads/stores of
 421   quad-word values in four ARM registers."
 422  (and (match_code "mem")
 423       (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 1, true)")))
 424
 425 (define_memory_constraint "Uq"
 426  "@internal
 427   In ARM state an address valid in ldrsb instructions."
 428  (and (match_code "mem")
 429       (match_test "TARGET_ARM
 430                    && arm_legitimate_address_outer_p (GET_MODE (op), XEXP (op, 0),
 431                                                       SIGN_EXTEND, 0)
 432                    && !arm_is_constant_pool_ref (op)")))
 433
 434 (define_memory_constraint "Q"
 435  "@internal
 436   An address that is a single base register."
 437  (and (match_code "mem")
 438       (match_test "REG_P (XEXP (op, 0))")))
 439
 440 (define_memory_constraint "Uu"
 441  "@internal
 442   In Thumb state an address that is valid in 16bit encoding."
 443  (and (match_code "mem")
 444       (match_test "TARGET_THUMB
 445                    && thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
 446                                                    0)")))
 447
 448 ; The 16-bit post-increment LDR/STR accepted by thumb1_legitimate_address_p
 449 ; are actually LDM/STM instructions, so cannot be used to access unaligned
 450 ; data.
 451 (define_memory_constraint "Uw"
 452  "@internal
 453   In Thumb state an address that is valid in 16bit encoding, and that can be
 454   used for unaligned accesses."
 455  (and (match_code "mem")
 456       (match_test "TARGET_THUMB
 457                    && thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
 458                                                    0)
 459                    && GET_CODE (XEXP (op, 0)) != POST_INC")))
 460
 461 (define_constraint "US"
 462  "@internal
 463   US is a symbol reference."
 464  (match_code "symbol_ref")
 465 )
 466
 467 (define_memory_constraint "Uz"
 468  "@internal
 469   A memory access that is accessible as an LDC/STC operand"
 470  (and (match_code "mem")
 471       (match_test "arm_coproc_ldc_stc_legitimate_address (op)")))
 472
 473 ;; We used to have constraint letters for S and R in ARM state, but
 474 ;; all uses of these now appear to have been removed.
 475
 476 ;; Additionally, we used to have a Q constraint in Thumb state, but
 477 ;; this wasn't really a valid memory constraint.  Again, all uses of
 478 ;; this now seem to have been removed.
 479