gcc/config/arm/cortex-a53.md

   1 ;; ARM Cortex-A53 pipeline description
   2 ;; Copyright (C) 2013-2014 Free Software Foundation, Inc.
   3 ;;
   4 ;; Contributed by ARM Ltd.
   5 ;;
   6 ;; This file is part of GCC.
   7 ;;
   8 ;; GCC is free software; you can redistribute it and/or modify it
   9 ;; under the terms of the GNU General Public License as published by
  10 ;; the Free Software Foundation; either version 3, or (at your option)
  11 ;; any later version.
  12 ;;
  13 ;; GCC is distributed in the hope that it will be useful, but
  14 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16 ;; General Public License for more details.
  17 ;;
  18 ;; You should have received a copy of the GNU General Public License
  19 ;; along with GCC; see the file COPYING3.  If not see
  20 ;; <http://www.gnu.org/licenses/>.
  21
  22 (define_automaton "cortex_a53")
  23
  24 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  25 ;; Functional units.
  26 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  27
  28 ;; There are two main integer execution pipelines, described as
  29 ;; slot 0 and issue slot 1.
  30
  31 (define_cpu_unit "cortex_a53_slot0" "cortex_a53")
  32 (define_cpu_unit "cortex_a53_slot1" "cortex_a53")
  33
  34 (define_reservation "cortex_a53_slot_any" "cortex_a53_slot0|cortex_a53_slot1")
  35 (define_reservation "cortex_a53_single_issue" "cortex_a53_slot0+cortex_a53_slot1")
  36
  37 ;; The load/store pipeline.  Load/store instructions can dual-issue from
  38 ;; either pipeline, but two load/stores cannot simultaneously issue.
  39
  40 (define_cpu_unit "cortex_a53_ls" "cortex_a53")
  41
  42 ;; The store pipeline.  Shared between both execution pipelines.
  43
  44 (define_cpu_unit "cortex_a53_store" "cortex_a53")
  45
  46 ;; The branch pipeline.  Branches can dual-issue with other instructions
  47 ;; (except when those instructions take multiple cycles to issue).
  48
  49 (define_cpu_unit "cortex_a53_branch" "cortex_a53")
  50
  51 ;; The integer divider.
  52
  53 (define_cpu_unit "cortex_a53_idiv" "cortex_a53")
  54
  55 ;; The floating-point add pipeline used to model the usage
  56 ;; of the add pipeline by fmac instructions.
  57
  58 (define_cpu_unit "cortex_a53_fpadd_pipe" "cortex_a53")
  59
  60 ;; Floating-point div/sqrt (long latency, out-of-order completion).
  61
  62 (define_cpu_unit "cortex_a53_fp_div_sqrt" "cortex_a53")
  63
  64 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  65 ;; ALU instructions.
  66 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  67
  68 (define_insn_reservation "cortex_a53_alu" 2
  69   (and (eq_attr "tune" "cortexa53")
  70        (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
  71                         alu_reg,alus_reg,logic_reg,logics_reg,\
  72                         adc_imm,adcs_imm,adc_reg,adcs_reg,\
  73                         adr,bfm,csel,rev,\
  74                         shift_imm,shift_reg,\
  75                         mov_imm,mov_reg,mvn_imm,mvn_reg,\
  76                         mrs,multiple,no_insn"))
  77   "cortex_a53_slot_any")
  78
  79 (define_insn_reservation "cortex_a53_alu_shift" 2
  80   (and (eq_attr "tune" "cortexa53")
  81        (eq_attr "type" "alu_shift_imm,alus_shift_imm,\
  82                         logic_shift_imm,logics_shift_imm,\
  83                         alu_shift_reg,alus_shift_reg,\
  84                         logic_shift_reg,logics_shift_reg,\
  85                         extend,mov_shift,mov_shift_reg,\
  86                         mvn_shift,mvn_shift_reg"))
  87   "cortex_a53_slot_any")
  88
  89 ;; Forwarding path for unshifted operands.
  90
  91 (define_bypass 1 "cortex_a53_alu,cortex_a53_alu_shift"
  92   "cortex_a53_alu")
  93
  94 (define_bypass 1 "cortex_a53_alu,cortex_a53_alu_shift"
  95   "cortex_a53_alu_shift"
  96   "arm_no_early_alu_shift_dep")
  97
  98 ;; The multiplier pipeline can forward results so there's no need to specify
  99 ;; bypasses. Multiplies can only single-issue currently.
 100
 101 (define_insn_reservation "cortex_a53_mul" 3
 102   (and (eq_attr "tune" "cortexa53")
 103        (ior (eq_attr "mul32" "yes")
 104             (eq_attr "mul64" "yes")))
 105   "cortex_a53_single_issue")
 106
 107 ;; A multiply with a single-register result or an MLA, followed by an
 108 ;; MLA with an accumulator dependency, has its result forwarded so two
 109 ;; such instructions can issue back-to-back.
 110
 111 (define_bypass 1 "cortex_a53_mul"
 112                "cortex_a53_mul"
 113                "arm_mac_accumulator_is_mul_result")
 114
 115 ;; Punt with a high enough latency for divides.
 116 (define_insn_reservation "cortex_a53_udiv" 8
 117   (and (eq_attr "tune" "cortexa53")
 118        (eq_attr "type" "udiv"))
 119   "(cortex_a53_slot0+cortex_a53_idiv),cortex_a53_idiv*7")
 120
 121 (define_insn_reservation "cortex_a53_sdiv" 9
 122   (and (eq_attr "tune" "cortexa53")
 123        (eq_attr "type" "sdiv"))
 124   "(cortex_a53_slot0+cortex_a53_idiv),cortex_a53_idiv*8")
 125
 126
 127 (define_bypass 2 "cortex_a53_mul,cortex_a53_udiv,cortex_a53_sdiv"
 128                "cortex_a53_alu")
 129 (define_bypass 2 "cortex_a53_mul,cortex_a53_udiv,cortex_a53_sdiv"
 130                "cortex_a53_alu_shift"
 131                "arm_no_early_alu_shift_dep")
 132
 133 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 134 ;; Load/store instructions.
 135 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 136
 137 ;; Address-generation happens in the issue stage.
 138
 139 (define_insn_reservation "cortex_a53_load1" 3
 140   (and (eq_attr "tune" "cortexa53")
 141        (eq_attr "type" "load_byte,load1,load_acq"))
 142   "cortex_a53_slot_any+cortex_a53_ls")
 143
 144 (define_insn_reservation "cortex_a53_store1" 2
 145   (and (eq_attr "tune" "cortexa53")
 146        (eq_attr "type" "store1,store_rel"))
 147   "cortex_a53_slot_any+cortex_a53_ls+cortex_a53_store")
 148
 149 (define_insn_reservation "cortex_a53_load2" 3
 150   (and (eq_attr "tune" "cortexa53")
 151        (eq_attr "type" "load2"))
 152   "cortex_a53_single_issue+cortex_a53_ls")
 153
 154 (define_insn_reservation "cortex_a53_store2" 2
 155   (and (eq_attr "tune" "cortexa53")
 156        (eq_attr "type" "store2"))
 157   "cortex_a53_single_issue+cortex_a53_ls+cortex_a53_store")
 158
 159 (define_insn_reservation "cortex_a53_load3plus" 4
 160   (and (eq_attr "tune" "cortexa53")
 161        (eq_attr "type" "load3,load4"))
 162   "(cortex_a53_single_issue+cortex_a53_ls)*2")
 163
 164 (define_insn_reservation "cortex_a53_store3plus" 3
 165   (and (eq_attr "tune" "cortexa53")
 166        (eq_attr "type" "store3,store4"))
 167   "(cortex_a53_single_issue+cortex_a53_ls+cortex_a53_store)*2")
 168
 169 ;; Load/store addresses are required early in Issue.
 170 (define_bypass 3 "cortex_a53_load1,cortex_a53_load2,cortex_a53_load3plus,cortex_a53_alu,cortex_a53_alu_shift"
 171                  "cortex_a53_load*"
 172                  "arm_early_load_addr_dep")
 173 (define_bypass 3 "cortex_a53_load1,cortex_a53_load2,cortex_a53_load3plus,cortex_a53_alu,cortex_a53_alu_shift"
 174                  "cortex_a53_store*"
 175                  "arm_early_store_addr_dep")
 176
 177 ;; Load data can forward in the ALU pipeline
 178 (define_bypass 2 "cortex_a53_load1,cortex_a53_load2"
 179                "cortex_a53_alu")
 180 (define_bypass 2 "cortex_a53_load1,cortex_a53_load2"
 181                "cortex_a53_alu_shift"
 182                "arm_no_early_alu_shift_dep")
 183
 184 ;; ALU ops can forward to stores.
 185 (define_bypass 0 "cortex_a53_alu,cortex_a53_alu_shift"
 186                  "cortex_a53_store1,cortex_a53_store2,cortex_a53_store3plus"
 187                  "arm_no_early_store_addr_dep")
 188
 189 (define_bypass 1 "cortex_a53_mul,cortex_a53_udiv,cortex_a53_sdiv,cortex_a53_load1,cortex_a53_load2,cortex_a53_load3plus"
 190                  "cortex_a53_store1,cortex_a53_store2,cortex_a53_store3plus"
 191                  "arm_no_early_store_addr_dep")
 192
 193 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 194 ;; Branches.
 195 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 196
 197 ;; Currently models all branches as dual-issuable from either execution
 198 ;; slot, which isn't true for all cases. We still need to model indirect
 199 ;; branches.
 200
 201 (define_insn_reservation "cortex_a53_branch" 0
 202   (and (eq_attr "tune" "cortexa53")
 203        (eq_attr "type" "branch,call"))
 204   "cortex_a53_slot_any+cortex_a53_branch")
 205
 206 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 207 ;; Floating-point arithmetic.
 208 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 209
 210 (define_insn_reservation "cortex_a53_fpalu" 4
 211   (and (eq_attr "tune" "cortexa53")
 212        (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fmov, fmuls,\
 213                         f_cvt,f_cvtf2i,f_cvti2f,\
 214                         fcmps, fcmpd, fcsel"))
 215   "cortex_a53_slot0+cortex_a53_fpadd_pipe")
 216
 217 (define_insn_reservation "cortex_a53_fconst" 2
 218   (and (eq_attr "tune" "cortexa53")
 219        (eq_attr "type" "fconsts,fconstd"))
 220   "cortex_a53_slot0+cortex_a53_fpadd_pipe")
 221
 222 (define_insn_reservation "cortex_a53_fpmul" 4
 223   (and (eq_attr "tune" "cortexa53")
 224        (eq_attr "type" "fmuls,fmuld"))
 225   "cortex_a53_slot0")
 226
 227 ;; For single-precision multiply-accumulate, the add (accumulate) is issued after
 228 ;; the multiply completes. Model that accordingly.
 229
 230 (define_insn_reservation "cortex_a53_fpmac" 8
 231   (and (eq_attr "tune" "cortexa53")
 232        (eq_attr "type" "fmacs,fmacd,ffmas,ffmad"))
 233   "cortex_a53_slot0, nothing*3, cortex_a53_fpadd_pipe")
 234
 235 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 236 ;; Floating-point divide/square root instructions.
 237 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 238 ;; fsqrt really takes one cycle less, but that is not modelled.
 239
 240 (define_insn_reservation "cortex_a53_fdivs" 14
 241   (and (eq_attr "tune" "cortexa53")
 242        (eq_attr "type" "fdivs, fsqrts"))
 243   "cortex_a53_slot0, cortex_a53_fp_div_sqrt * 13")
 244
 245 (define_insn_reservation "cortex_a53_fdivd" 29
 246   (and (eq_attr "tune" "cortexa53")
 247        (eq_attr "type" "fdivd, fsqrtd"))
 248   "cortex_a53_slot0, cortex_a53_fp_div_sqrt * 28")
 249
 250 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 251 ;; VFP to/from core transfers.
 252 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 253
 254 (define_insn_reservation "cortex_a53_r2f" 4
 255   (and (eq_attr "tune" "cortexa53")
 256        (eq_attr "type" "f_mcr,f_mcrr"))
 257   "cortex_a53_slot0")
 258
 259 (define_insn_reservation "cortex_a53_f2r" 2
 260   (and (eq_attr "tune" "cortexa53")
 261        (eq_attr "type" "f_mrc,f_mrrc"))
 262   "cortex_a53_slot0")
 263
 264 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 265 ;; VFP flag transfer.
 266 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 267
 268 (define_insn_reservation "cortex_a53_f_flags" 4
 269   (and (eq_attr "tune" "cortexa53")
 270        (eq_attr "type" "f_flag"))
 271   "cortex_a53_slot0")
 272
 273 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 274 ;; VFP load/store.
 275 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 276
 277 (define_insn_reservation "cortex_a53_f_loads" 4
 278   (and (eq_attr "tune" "cortexa53")
 279        (eq_attr "type" "f_loads"))
 280   "cortex_a53_slot0")
 281
 282 (define_insn_reservation "cortex_a53_f_loadd" 5
 283   (and (eq_attr "tune" "cortexa53")
 284        (eq_attr "type" "f_loadd"))
 285   "cortex_a53_slot0")
 286
 287 (define_insn_reservation "cortex_a53_f_stores" 0
 288   (and (eq_attr "tune" "cortexa53")
 289        (eq_attr "type" "f_stores"))
 290   "cortex_a53_slot0")
 291
 292 (define_insn_reservation "cortex_a53_f_stored" 0
 293   (and (eq_attr "tune" "cortexa53")
 294        (eq_attr "type" "f_stored"))
 295   "cortex_a53_slot0")
 296
 297 ;; Load-to-use for floating-point values has a penalty of one cycle,
 298 ;; i.e. a latency of two.
 299
 300 (define_bypass 2 "cortex_a53_f_loads"
 301                  "cortex_a53_fpalu, cortex_a53_fpmac, cortex_a53_fpmul,\
 302                   cortex_a53_fdivs, cortex_a53_fdivd,\
 303                   cortex_a53_f2r")
 304
 305 (define_bypass 2 "cortex_a53_f_loadd"
 306                  "cortex_a53_fpalu, cortex_a53_fpmac, cortex_a53_fpmul,\
 307                   cortex_a53_fdivs, cortex_a53_fdivd,\
 308                   cortex_a53_f2r")
 309