gcc/config/arm/cortex-a7.md

   1 ;; ARM Cortex-A7 pipeline description
   2 ;; Copyright (C) 2012-2013 Free Software Foundation, Inc.
   3 ;;
   4 ;; Contributed by ARM Ltd.
   5 ;; Based on cortex-a5.md which was originally contributed by CodeSourcery.
   6 ;;
   7 ;; This file is part of GCC.
   8 ;;
   9 ;; GCC is free software; you can redistribute it and/or modify it
  10 ;; under the terms of the GNU General Public License as published by
  11 ;; the Free Software Foundation; either version 3, or (at your option)
  12 ;; any later version.
  13 ;;
  14 ;; GCC is distributed in the hope that it will be useful, but
  15 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17 ;; General Public License for more details.
  18 ;;
  19 ;; You should have received a copy of the GNU General Public License
  20 ;; along with GCC; see the file COPYING3.  If not see
  21 ;; <http://www.gnu.org/licenses/>.
  22
  23 (define_automaton "cortex_a7")
  24
  25 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  26 ;; Functional units.
  27 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  28
  29 ;; The Cortex-A7 pipeline integer and vfp pipeline.
  30 ;; The decode is the same for all instructions, so do not model it.
  31 ;; We only model the first execution stage because
  32 ;; instructions always advance one stage per cycle in order.
  33 ;; We model all of the LS, Branch, ALU, MAC and FPU pipelines together.
  34
  35 (define_cpu_unit "cortex_a7_ex1, cortex_a7_ex2" "cortex_a7")
  36
  37 (define_reservation "cortex_a7_both" "cortex_a7_ex1+cortex_a7_ex2")
  38
  39 (define_cpu_unit "cortex_a7_branch" "cortex_a7")
  40
  41 ;; Cortex-A7 is in order and can dual-issue under limited circumstances.
  42 ;; ex2 can be reserved only after ex1 is reserved.
  43
  44 (final_presence_set "cortex_a7_ex2" "cortex_a7_ex1")
  45
  46 ;; Pseudo-unit for blocking the multiply pipeline when a double-precision
  47 ;; multiply is in progress.
  48
  49 (define_cpu_unit "cortex_a7_fpmul_pipe" "cortex_a7")
  50
  51 ;; The floating-point add pipeline (ex1/f1 stage), used to model the usage
  52 ;; of the add pipeline by fmac instructions, etc.
  53
  54 (define_cpu_unit "cortex_a7_fpadd_pipe" "cortex_a7")
  55
  56 ;; Floating-point div/sqrt (long latency, out-of-order completion).
  57
  58 (define_cpu_unit "cortex_a7_fp_div_sqrt" "cortex_a7")
  59
  60 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  61 ;; Branches.
  62 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  63
  64 ;; A direct branch can dual issue either as younger or older instruction,
  65 ;; but branches cannot dual issue with branches.
  66 ;; No latency as there is no result.
  67
  68 (define_insn_reservation "cortex_a7_branch" 0
  69   (and (eq_attr "tune" "cortexa7")
  70        (and (eq_attr "type" "branch")
  71             (eq_attr "neon_type" "none")))
  72   "(cortex_a7_ex2|cortex_a7_ex1)+cortex_a7_branch")
  73
  74 ;; Call cannot dual-issue as an older instruction. It can dual-issue
  75 ;; as a younger instruction, or single-issue.  Call cannot dual-issue
  76 ;; with another branch instruction.  The result is available the next
  77 ;; cycle.
  78 (define_insn_reservation "cortex_a7_call" 1
  79   (and (eq_attr "tune" "cortexa7")
  80        (and (eq_attr "type" "call")
  81             (eq_attr "neon_type" "none")))
  82   "(cortex_a7_ex2|cortex_a7_both)+cortex_a7_branch")
  83
  84 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  85 ;; ALU instructions.
  86 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  87
  88 ;; ALU instruction with an immediate operand can dual-issue.
  89 (define_insn_reservation "cortex_a7_alu_imm" 2
  90   (and (eq_attr "tune" "cortexa7")
  91        (and (ior (eq_attr "type" "arlo_imm")
  92                  (ior (eq_attr "type" "extend")
  93                       (and (eq_attr "insn" "mov")
  94                            (not (eq_attr "length" "8")))))
  95             (eq_attr "neon_type" "none")))
  96   "cortex_a7_ex2|cortex_a7_ex1")
  97
  98 ;; ALU instruction with register operands can dual-issue
  99 ;; with a younger immediate-based instruction.
 100 (define_insn_reservation "cortex_a7_alu_reg" 2
 101   (and (eq_attr "tune" "cortexa7")
 102        (and (eq_attr "type" "arlo_reg,shift,shift_reg")
 103             (eq_attr "neon_type" "none")))
 104   "cortex_a7_ex1")
 105
 106 (define_insn_reservation "cortex_a7_alu_shift" 2
 107   (and (eq_attr "tune" "cortexa7")
 108        (and (eq_attr "type" "arlo_shift,arlo_shift_reg")
 109             (eq_attr "neon_type" "none")))
 110   "cortex_a7_ex1")
 111
 112 ;; Forwarding path for unshifted operands.
 113 (define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_reg,cortex_a7_alu_shift"
 114   "cortex_a7_alu_imm,cortex_a7_alu_reg,cortex_a7_mul")
 115
 116 (define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_reg,cortex_a7_alu_shift"
 117   "cortex_a7_store*"
 118   "arm_no_early_store_addr_dep")
 119
 120 (define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_reg,cortex_a7_alu_shift"
 121   "cortex_a7_alu_shift"
 122   "arm_no_early_alu_shift_dep")
 123
 124 ;; The multiplier pipeline can forward results from wr stage only so
 125 ;; there's no need to specify bypasses.
 126 ;; Multiply instructions cannot dual-issue.
 127
 128 (define_insn_reservation "cortex_a7_mul" 2
 129   (and (eq_attr "tune" "cortexa7")
 130        (and (eq_attr "neon_type" "none")
 131             (ior (eq_attr "mul32" "yes")
 132                  (eq_attr "mul64" "yes"))))
 133   "cortex_a7_both")
 134
 135 ;; Forward the result of a multiply operation to the accumulator
 136 ;; of the following multiply and accumulate instruction.
 137 (define_bypass 1 "cortex_a7_mul"
 138                  "cortex_a7_mul"
 139                  "arm_mac_accumulator_is_result")
 140
 141 ;; The latency depends on the operands, so we use an estimate here.
 142 (define_insn_reservation "cortex_a7_idiv" 5
 143   (and (eq_attr "tune" "cortexa7")
 144        (eq_attr "type" "udiv,sdiv"))
 145   "cortex_a7_both*5")
 146
 147 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 148 ;; Load/store instructions.
 149 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 150
 151 ;; Address-generation happens in the issue stage.
 152 ;; Double-word accesses can be issued in a single cycle,
 153 ;; and occupy only one pipeline stage.
 154
 155 (define_insn_reservation "cortex_a7_load1" 2
 156   (and (eq_attr "tune" "cortexa7")
 157        (and (eq_attr "type" "load_byte,load1")
 158             (eq_attr "neon_type" "none")))
 159   "cortex_a7_ex1")
 160
 161 (define_insn_reservation "cortex_a7_store1" 0
 162   (and (eq_attr "tune" "cortexa7")
 163        (and (eq_attr "type" "store1")
 164             (eq_attr "neon_type" "none")))
 165   "cortex_a7_ex1")
 166
 167 (define_insn_reservation "cortex_a7_load2" 2
 168   (and (eq_attr "tune" "cortexa7")
 169        (and (eq_attr "type" "load2")
 170             (eq_attr "neon_type" "none")))
 171   "cortex_a7_both")
 172
 173 (define_insn_reservation "cortex_a7_store2" 0
 174   (and (eq_attr "tune" "cortexa7")
 175        (and (eq_attr "type" "store2")
 176             (eq_attr "neon_type" "none")))
 177   "cortex_a7_both")
 178
 179 (define_insn_reservation "cortex_a7_load3" 3
 180   (and (eq_attr "tune" "cortexa7")
 181        (and (eq_attr "type" "load3")
 182             (eq_attr "neon_type" "none")))
 183   "cortex_a7_both, cortex_a7_ex1")
 184
 185 (define_insn_reservation "cortex_a7_store3" 0
 186   (and (eq_attr "tune" "cortexa7")
 187        (and (eq_attr "type" "store4")
 188             (eq_attr "neon_type" "none")))
 189   "cortex_a7_both, cortex_a7_ex1")
 190
 191 (define_insn_reservation "cortex_a7_load4" 3
 192   (and (eq_attr "tune" "cortexa7")
 193        (and (eq_attr "type" "load4")
 194             (eq_attr "neon_type" "none")))
 195   "cortex_a7_both, cortex_a7_both")
 196
 197 (define_insn_reservation "cortex_a7_store4" 0
 198   (and (eq_attr "tune" "cortexa7")
 199        (and (eq_attr "type" "store3")
 200             (eq_attr "neon_type" "none")))
 201   "cortex_a7_both, cortex_a7_both")
 202
 203 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 204 ;; Floating-point arithmetic.
 205 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 206 ;; Neon integer, neon floating point, and single-precision floating
 207 ;; point instructions of the same type have the same timing
 208 ;; characteristics, but neon instructions cannot dual-issue.
 209
 210 (define_insn_reservation "cortex_a7_fpalu" 4
 211   (and (eq_attr "tune" "cortexa7")
 212        (and (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys,\
 213                              f_cvt, fcmps, fcmpd")
 214             (eq_attr "neon_type" "none")))
 215   "cortex_a7_ex1+cortex_a7_fpadd_pipe")
 216
 217 ;; For fconsts and fconstd, 8-bit immediate data is passed directly from
 218 ;; f1 to f3 (which I think reduces the latency by one cycle).
 219
 220 (define_insn_reservation "cortex_a7_fconst" 3
 221   (and (eq_attr "tune" "cortexa7")
 222        (and (eq_attr "type" "fconsts,fconstd")
 223             (eq_attr "neon_type" "none")))
 224   "cortex_a7_ex1+cortex_a7_fpadd_pipe")
 225
 226 ;; We should try not to attempt to issue a single-precision multiplication in
 227 ;; the middle of a double-precision multiplication operation (the usage of
 228 ;; cortex_a7_fpmul_pipe).
 229
 230 (define_insn_reservation "cortex_a7_fpmuls" 4
 231   (and (eq_attr "tune" "cortexa7")
 232        (and (eq_attr "type" "fmuls")
 233             (eq_attr "neon_type" "none")))
 234   "cortex_a7_ex1+cortex_a7_fpmul_pipe")
 235
 236 (define_insn_reservation "cortex_a7_neon_mul" 4
 237   (and (eq_attr "tune" "cortexa7")
 238        (eq_attr "neon_type"
 239                 "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
 240                  neon_mul_qqq_8_16_32_ddd_32,\
 241                  neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar,\
 242                  neon_mul_ddd_16_scalar_32_16_long_scalar,\
 243                  neon_mul_qqd_32_scalar,\
 244                  neon_fp_vmul_ddd,\
 245                  neon_fp_vmul_qqd"))
 246   "(cortex_a7_both+cortex_a7_fpmul_pipe)*2")
 247
 248 (define_insn_reservation "cortex_a7_fpmacs" 8
 249   (and (eq_attr "tune" "cortexa7")
 250        (and (eq_attr "type" "fmacs,ffmas")
 251             (eq_attr "neon_type" "none")))
 252   "cortex_a7_ex1+cortex_a7_fpmul_pipe")
 253
 254 (define_insn_reservation "cortex_a7_neon_mla" 8
 255   (and (eq_attr "tune" "cortexa7")
 256        (eq_attr "neon_type"
 257                 "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
 258                  neon_mla_qqq_8_16,\
 259                  neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long,\
 260                  neon_mla_qqq_32_qqd_32_scalar,\
 261                  neon_mla_ddd_16_scalar_qdd_32_16_long_scalar,\
 262                  neon_fp_vmla_ddd,\
 263                  neon_fp_vmla_qqq,\
 264                  neon_fp_vmla_ddd_scalar,\
 265                  neon_fp_vmla_qqq_scalar"))
 266   "cortex_a7_both+cortex_a7_fpmul_pipe")
 267
 268 (define_bypass 4 "cortex_a7_fpmacs,cortex_a7_neon_mla"
 269                  "cortex_a7_fpmacs,cortex_a7_neon_mla"
 270                  "arm_mac_accumulator_is_result")
 271
 272 ;; Non-multiply instructions can issue between two cycles of a
 273 ;; double-precision multiply.
 274
 275 (define_insn_reservation "cortex_a7_fpmuld" 7
 276   (and (eq_attr "tune" "cortexa7")
 277        (and (eq_attr "type" "fmuld")
 278             (eq_attr "neon_type" "none")))
 279   "cortex_a7_ex1+cortex_a7_fpmul_pipe, cortex_a7_fpmul_pipe*3")
 280
 281 (define_insn_reservation "cortex_a7_fpmacd" 11
 282   (and (eq_attr "tune" "cortexa7")
 283        (and (eq_attr "type" "fmacd")
 284             (eq_attr "neon_type" "none")))
 285   "cortex_a7_ex1+cortex_a7_fpmul_pipe, cortex_a7_fpmul_pipe*3")
 286
 287 (define_insn_reservation "cortex_a7_fpfmad" 8
 288   (and (eq_attr "tune" "cortexa7")
 289        (and (eq_attr "type" "ffmad")
 290             (eq_attr "neon_type" "none")))
 291   "cortex_a7_ex1+cortex_a7_fpmul_pipe, cortex_a7_fpmul_pipe*4")
 292
 293 (define_bypass 7 "cortex_a7_fpmacd"
 294                  "cortex_a7_fpmacd,cortex_a7_fpfmad"
 295                  "arm_mac_accumulator_is_result")
 296
 297 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 298 ;; Floating-point divide/square root instructions.
 299 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 300
 301 (define_insn_reservation "cortex_a7_fdivs" 16
 302   (and (eq_attr "tune" "cortexa7")
 303        (and (eq_attr "type" "fdivs")
 304             (eq_attr "neon_type" "none")))
 305   "cortex_a7_ex1+cortex_a7_fp_div_sqrt, cortex_a7_fp_div_sqrt * 13")
 306
 307 (define_insn_reservation "cortex_a7_fdivd" 31
 308   (and (eq_attr "tune" "cortexa7")
 309        (and (eq_attr "type" "fdivd")
 310             (eq_attr "neon_type" "none")))
 311   "cortex_a7_ex1+cortex_a7_fp_div_sqrt, cortex_a7_fp_div_sqrt * 28")
 312
 313 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 314 ;; VFP to/from core transfers.
 315 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 316
 317 ;; Core-to-VFP transfers.
 318
 319 (define_insn_reservation "cortex_a7_r2f" 4
 320   (and (eq_attr "tune" "cortexa7")
 321        (and (eq_attr "type" "r_2_f")
 322             (eq_attr "neon_type" "none")))
 323   "cortex_a7_both")
 324
 325 (define_insn_reservation "cortex_a7_f2r" 2
 326   (and (eq_attr "tune" "cortexa7")
 327        (and (eq_attr "type" "f_2_r")
 328             (eq_attr "neon_type" "none")))
 329   "cortex_a7_ex1")
 330
 331 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 332 ;; VFP flag transfer.
 333 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 334
 335 ;; Fuxne: The flag forwarding from fmstat to the second instruction is
 336 ;; not modeled at present.
 337
 338 (define_insn_reservation "cortex_a7_f_flags" 4
 339   (and (eq_attr "tune" "cortexa7")
 340        (and (eq_attr "type" "f_flag")
 341             (eq_attr "neon_type" "none")))
 342   "cortex_a7_ex1")
 343
 344 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 345 ;; VFP load/store.
 346 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 347
 348 (define_insn_reservation "cortex_a7_f_loads" 4
 349   (and (eq_attr "tune" "cortexa7")
 350        (and (eq_attr "type" "f_loads")
 351             (eq_attr "neon_type" "none")))
 352   "cortex_a7_ex1")
 353
 354 (define_insn_reservation "cortex_a7_f_loadd" 4
 355   (and (eq_attr "tune" "cortexa7")
 356        (and (eq_attr "type" "f_loadd")
 357             (eq_attr "neon_type" "none")))
 358   "cortex_a7_both")
 359
 360 (define_insn_reservation "cortex_a7_f_stores" 0
 361   (and (eq_attr "tune" "cortexa7")
 362        (and (eq_attr "type" "f_stores")
 363             (eq_attr "neon_type" "none")))
 364   "cortex_a7_ex1")
 365
 366 (define_insn_reservation "cortex_a7_f_stored" 0
 367   (and (eq_attr "tune" "cortexa7")
 368        (and (eq_attr "type" "f_stored")
 369             (eq_attr "neon_type" "none")))
 370   "cortex_a7_both")
 371
 372 ;; Load-to-use for floating-point values has a penalty of one cycle,
 373 ;; i.e. a latency of two.
 374
 375 (define_bypass 2 "cortex_a7_f_loads, cortex_a7_f_loadd"
 376                   "cortex_a7_fpalu,\
 377                    cortex_a7_fpmuls,cortex_a7_fpmacs,\
 378                    cortex_a7_fpmuld,cortex_a7_fpmacd, cortex_a7_fpfmad,\
 379                    cortex_a7_fdivs, cortex_a7_fdivd,\
 380                    cortex_a7_f2r")
 381
 382 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 383 ;; NEON
 384 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 385
 386 ;; Simple modeling for all neon instructions not covered earlier.
 387
 388 (define_insn_reservation "cortex_a7_neon" 4
 389   (and (eq_attr "tune" "cortexa7")
 390        (eq_attr "neon_type"
 391                 "!none,\
 392                   neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
 393                   neon_mul_qqq_8_16_32_ddd_32,\
 394                   neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar,\
 395                   neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
 396                   neon_mla_qqq_8_16,\
 397                   neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long,\
 398                   neon_mla_qqq_32_qqd_32_scalar,\
 399                   neon_mul_ddd_16_scalar_32_16_long_scalar,\
 400                   neon_mul_qqd_32_scalar,\
 401                   neon_mla_ddd_16_scalar_qdd_32_16_long_scalar,\
 402                   neon_fp_vmul_ddd,\
 403                   neon_fp_vmul_qqd,\
 404                   neon_fp_vmla_ddd,\
 405                   neon_fp_vmla_qqq,\
 406                   neon_fp_vmla_ddd_scalar,\
 407                   neon_fp_vmla_qqq_scalar"))
 408   "cortex_a7_both*2")