gcc/config/arm/cortex-a7.md

   1 ;; ARM Cortex-A7 pipeline description
   2 ;; Copyright (C) 2012-2013 Free Software Foundation, Inc.
   3 ;;
   4 ;; Contributed by ARM Ltd.
   5 ;; Based on cortex-a5.md which was originally contributed by CodeSourcery.
   6 ;;
   7 ;; This file is part of GCC.
   8 ;;
   9 ;; GCC is free software; you can redistribute it and/or modify it
  10 ;; under the terms of the GNU General Public License as published by
  11 ;; the Free Software Foundation; either version 3, or (at your option)
  12 ;; any later version.
  13 ;;
  14 ;; GCC is distributed in the hope that it will be useful, but
  15 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17 ;; General Public License for more details.
  18 ;;
  19 ;; You should have received a copy of the GNU General Public License
  20 ;; along with GCC; see the file COPYING3.  If not see
  21 ;; <http://www.gnu.org/licenses/>.
  22
  23 (define_automaton "cortex_a7")
  24
  25 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  26 ;; Functional units.
  27 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  28
  29 ;; The Cortex-A7 pipeline integer and vfp pipeline.
  30 ;; The decode is the same for all instructions, so do not model it.
  31 ;; We only model the first execution stage because
  32 ;; instructions always advance one stage per cycle in order.
  33 ;; We model all of the LS, Branch, ALU, MAC and FPU pipelines together.
  34
  35 (define_cpu_unit "cortex_a7_ex1, cortex_a7_ex2" "cortex_a7")
  36
  37 (define_reservation "cortex_a7_both" "cortex_a7_ex1+cortex_a7_ex2")
  38
  39 (define_cpu_unit "cortex_a7_branch" "cortex_a7")
  40
  41 ;; Cortex-A7 is in order and can dual-issue under limited circumstances.
  42 ;; ex2 can be reserved only after ex1 is reserved.
  43
  44 (final_presence_set "cortex_a7_ex2" "cortex_a7_ex1")
  45
  46 ;; Pseudo-unit for blocking the multiply pipeline when a double-precision
  47 ;; multiply is in progress.
  48
  49 (define_cpu_unit "cortex_a7_fpmul_pipe" "cortex_a7")
  50
  51 ;; The floating-point add pipeline (ex1/f1 stage), used to model the usage
  52 ;; of the add pipeline by fmac instructions, etc.
  53
  54 (define_cpu_unit "cortex_a7_fpadd_pipe" "cortex_a7")
  55
  56 ;; Floating-point div/sqrt (long latency, out-of-order completion).
  57
  58 (define_cpu_unit "cortex_a7_fp_div_sqrt" "cortex_a7")
  59
  60 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  61 ;; Branches.
  62 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  63
  64 ;; A direct branch can dual issue either as younger or older instruction,
  65 ;; but branches cannot dual issue with branches.
  66 ;; No latency as there is no result.
  67
  68 (define_insn_reservation "cortex_a7_branch" 0
  69   (and (eq_attr "tune" "cortexa7")
  70        (and (eq_attr "type" "branch")
  71             (eq_attr "neon_type" "none")))
  72   "(cortex_a7_ex2|cortex_a7_ex1)+cortex_a7_branch")
  73
  74 ;; Call cannot dual-issue as an older instruction. It can dual-issue
  75 ;; as a younger instruction, or single-issue.  Call cannot dual-issue
  76 ;; with another branch instruction.  The result is available the next
  77 ;; cycle.
  78 (define_insn_reservation "cortex_a7_call" 1
  79   (and (eq_attr "tune" "cortexa7")
  80        (and (eq_attr "type" "call")
  81             (eq_attr "neon_type" "none")))
  82   "(cortex_a7_ex2|cortex_a7_both)+cortex_a7_branch")
  83
  84 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  85 ;; ALU instructions.
  86 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  87
  88 ;; ALU instruction with an immediate operand can dual-issue.
  89 (define_insn_reservation "cortex_a7_alu_imm" 2
  90   (and (eq_attr "tune" "cortexa7")
  91        (and (ior (eq_attr "type" "simple_alu_imm")
  92                  (ior (eq_attr "type" "simple_alu_shift")
  93                       (and (eq_attr "insn" "mov")
  94                            (not (eq_attr "length" "8")))))
  95             (eq_attr "neon_type" "none")))
  96   "cortex_a7_ex2|cortex_a7_ex1")
  97
  98 ;; ALU instruction with register operands can dual-issue
  99 ;; with a younger immediate-based instruction.
 100 (define_insn_reservation "cortex_a7_alu_reg" 2
 101   (and (eq_attr "tune" "cortexa7")
 102        (and (eq_attr "type" "alu_reg")
 103             (eq_attr "neon_type" "none")))
 104   "cortex_a7_ex1")
 105
 106 (define_insn_reservation "cortex_a7_alu_shift" 2
 107   (and (eq_attr "tune" "cortexa7")
 108        (and (eq_attr "type" "alu_shift,alu_shift_reg")
 109             (eq_attr "neon_type" "none")))
 110   "cortex_a7_ex1")
 111
 112 ;; Forwarding path for unshifted operands.
 113 (define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_reg,cortex_a7_alu_shift"
 114   "cortex_a7_alu_imm,cortex_a7_alu_reg,cortex_a7_mul")
 115
 116 (define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_reg,cortex_a7_alu_shift"
 117   "cortex_a7_store*"
 118   "arm_no_early_store_addr_dep")
 119
 120 (define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_reg,cortex_a7_alu_shift"
 121   "cortex_a7_alu_shift"
 122   "arm_no_early_alu_shift_dep")
 123
 124 ;; The multiplier pipeline can forward results from wr stage only so
 125 ;; there's no need to specify bypasses.
 126 ;; Multiply instructions cannot dual-issue.
 127
 128 (define_insn_reservation "cortex_a7_mul" 2
 129   (and (eq_attr "tune" "cortexa7")
 130        (and (eq_attr "type" "mult")
 131             (eq_attr "neon_type" "none")))
 132   "cortex_a7_both")
 133
 134 ;; Forward the result of a multiply operation to the accumulator
 135 ;; of the following multiply and accumulate instruction.
 136 (define_bypass 1 "cortex_a7_mul"
 137                  "cortex_a7_mul"
 138                  "arm_mac_accumulator_is_result")
 139
 140 ;; The latency depends on the operands, so we use an estimate here.
 141 (define_insn_reservation "cortex_a7_idiv" 5
 142   (and (eq_attr "tune" "cortexa7")
 143        (eq_attr "insn" "udiv,sdiv"))
 144   "cortex_a7_both*5")
 145
 146 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 147 ;; Load/store instructions.
 148 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 149
 150 ;; Address-generation happens in the issue stage.
 151 ;; Double-word accesses can be issued in a single cycle,
 152 ;; and occupy only one pipeline stage.
 153
 154 (define_insn_reservation "cortex_a7_load1" 2
 155   (and (eq_attr "tune" "cortexa7")
 156        (and (eq_attr "type" "load_byte,load1")
 157             (eq_attr "neon_type" "none")))
 158   "cortex_a7_ex1")
 159
 160 (define_insn_reservation "cortex_a7_store1" 0
 161   (and (eq_attr "tune" "cortexa7")
 162        (and (eq_attr "type" "store1")
 163             (eq_attr "neon_type" "none")))
 164   "cortex_a7_ex1")
 165
 166 (define_insn_reservation "cortex_a7_load2" 2
 167   (and (eq_attr "tune" "cortexa7")
 168        (and (eq_attr "type" "load2")
 169             (eq_attr "neon_type" "none")))
 170   "cortex_a7_both")
 171
 172 (define_insn_reservation "cortex_a7_store2" 0
 173   (and (eq_attr "tune" "cortexa7")
 174        (and (eq_attr "type" "store2")
 175             (eq_attr "neon_type" "none")))
 176   "cortex_a7_both")
 177
 178 (define_insn_reservation "cortex_a7_load3" 3
 179   (and (eq_attr "tune" "cortexa7")
 180        (and (eq_attr "type" "load3")
 181             (eq_attr "neon_type" "none")))
 182   "cortex_a7_both, cortex_a7_ex1")
 183
 184 (define_insn_reservation "cortex_a7_store3" 0
 185   (and (eq_attr "tune" "cortexa7")
 186        (and (eq_attr "type" "store4")
 187             (eq_attr "neon_type" "none")))
 188   "cortex_a7_both, cortex_a7_ex1")
 189
 190 (define_insn_reservation "cortex_a7_load4" 3
 191   (and (eq_attr "tune" "cortexa7")
 192        (and (eq_attr "type" "load4")
 193             (eq_attr "neon_type" "none")))
 194   "cortex_a7_both, cortex_a7_both")
 195
 196 (define_insn_reservation "cortex_a7_store4" 0
 197   (and (eq_attr "tune" "cortexa7")
 198        (and (eq_attr "type" "store3")
 199             (eq_attr "neon_type" "none")))
 200   "cortex_a7_both, cortex_a7_both")
 201
 202 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 203 ;; Floating-point arithmetic.
 204 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 205 ;; Neon integer, neon floating point, and single-precision floating
 206 ;; point instructions of the same type have the same timing
 207 ;; characteristics, but neon instructions cannot dual-issue.
 208
 209 (define_insn_reservation "cortex_a7_fpalu" 4
 210   (and (eq_attr "tune" "cortexa7")
 211        (and (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys,\
 212                              f_cvt, fcmps, fcmpd")
 213             (eq_attr "neon_type" "none")))
 214   "cortex_a7_ex1+cortex_a7_fpadd_pipe")
 215
 216 ;; For fconsts and fconstd, 8-bit immediate data is passed directly from
 217 ;; f1 to f3 (which I think reduces the latency by one cycle).
 218
 219 (define_insn_reservation "cortex_a7_fconst" 3
 220   (and (eq_attr "tune" "cortexa7")
 221        (and (eq_attr "type" "fconsts,fconstd")
 222             (eq_attr "neon_type" "none")))
 223   "cortex_a7_ex1+cortex_a7_fpadd_pipe")
 224
 225 ;; We should try not to attempt to issue a single-precision multiplication in
 226 ;; the middle of a double-precision multiplication operation (the usage of
 227 ;; cortex_a7_fpmul_pipe).
 228
 229 (define_insn_reservation "cortex_a7_fpmuls" 4
 230   (and (eq_attr "tune" "cortexa7")
 231        (and (eq_attr "type" "fmuls")
 232             (eq_attr "neon_type" "none")))
 233   "cortex_a7_ex1+cortex_a7_fpmul_pipe")
 234
 235 (define_insn_reservation "cortex_a7_neon_mul" 4
 236   (and (eq_attr "tune" "cortexa7")
 237        (eq_attr "neon_type"
 238                 "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
 239                  neon_mul_qqq_8_16_32_ddd_32,\
 240                  neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar,\
 241                  neon_mul_ddd_16_scalar_32_16_long_scalar,\
 242                  neon_mul_qqd_32_scalar,\
 243                  neon_fp_vmul_ddd,\
 244                  neon_fp_vmul_qqd"))
 245   "(cortex_a7_both+cortex_a7_fpmul_pipe)*2")
 246
 247 (define_insn_reservation "cortex_a7_fpmacs" 8
 248   (and (eq_attr "tune" "cortexa7")
 249        (and (eq_attr "type" "fmacs,ffmas")
 250             (eq_attr "neon_type" "none")))
 251   "cortex_a7_ex1+cortex_a7_fpmul_pipe")
 252
 253 (define_insn_reservation "cortex_a7_neon_mla" 8
 254   (and (eq_attr "tune" "cortexa7")
 255        (eq_attr "neon_type"
 256                 "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
 257                  neon_mla_qqq_8_16,\
 258                  neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long,\
 259                  neon_mla_qqq_32_qqd_32_scalar,\
 260                  neon_mla_ddd_16_scalar_qdd_32_16_long_scalar,\
 261                  neon_fp_vmla_ddd,\
 262                  neon_fp_vmla_qqq,\
 263                  neon_fp_vmla_ddd_scalar,\
 264                  neon_fp_vmla_qqq_scalar"))
 265   "cortex_a7_both+cortex_a7_fpmul_pipe")
 266
 267 (define_bypass 4 "cortex_a7_fpmacs,cortex_a7_neon_mla"
 268                  "cortex_a7_fpmacs,cortex_a7_neon_mla"
 269                  "arm_mac_accumulator_is_result")
 270
 271 ;; Non-multiply instructions can issue between two cycles of a
 272 ;; double-precision multiply.
 273
 274 (define_insn_reservation "cortex_a7_fpmuld" 7
 275   (and (eq_attr "tune" "cortexa7")
 276        (and (eq_attr "type" "fmuld")
 277             (eq_attr "neon_type" "none")))
 278   "cortex_a7_ex1+cortex_a7_fpmul_pipe, cortex_a7_fpmul_pipe*3")
 279
 280 (define_insn_reservation "cortex_a7_fpmacd" 11
 281   (and (eq_attr "tune" "cortexa7")
 282        (and (eq_attr "type" "fmacd")
 283             (eq_attr "neon_type" "none")))
 284   "cortex_a7_ex1+cortex_a7_fpmul_pipe, cortex_a7_fpmul_pipe*3")
 285
 286 (define_insn_reservation "cortex_a7_fpfmad" 8
 287   (and (eq_attr "tune" "cortexa7")
 288        (and (eq_attr "type" "ffmad")
 289             (eq_attr "neon_type" "none")))
 290   "cortex_a7_ex1+cortex_a7_fpmul_pipe, cortex_a7_fpmul_pipe*4")
 291
 292 (define_bypass 7 "cortex_a7_fpmacd"
 293                  "cortex_a7_fpmacd,cortex_a7_fpfmad"
 294                  "arm_mac_accumulator_is_result")
 295
 296 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 297 ;; Floating-point divide/square root instructions.
 298 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 299
 300 (define_insn_reservation "cortex_a7_fdivs" 16
 301   (and (eq_attr "tune" "cortexa7")
 302        (and (eq_attr "type" "fdivs")
 303             (eq_attr "neon_type" "none")))
 304   "cortex_a7_ex1+cortex_a7_fp_div_sqrt, cortex_a7_fp_div_sqrt * 13")
 305
 306 (define_insn_reservation "cortex_a7_fdivd" 31
 307   (and (eq_attr "tune" "cortexa7")
 308        (and (eq_attr "type" "fdivd")
 309             (eq_attr "neon_type" "none")))
 310   "cortex_a7_ex1+cortex_a7_fp_div_sqrt, cortex_a7_fp_div_sqrt * 28")
 311
 312 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 313 ;; VFP to/from core transfers.
 314 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 315
 316 ;; Core-to-VFP transfers.
 317
 318 (define_insn_reservation "cortex_a7_r2f" 4
 319   (and (eq_attr "tune" "cortexa7")
 320        (and (eq_attr "type" "r_2_f")
 321             (eq_attr "neon_type" "none")))
 322   "cortex_a7_both")
 323
 324 (define_insn_reservation "cortex_a7_f2r" 2
 325   (and (eq_attr "tune" "cortexa7")
 326        (and (eq_attr "type" "f_2_r")
 327             (eq_attr "neon_type" "none")))
 328   "cortex_a7_ex1")
 329
 330 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 331 ;; VFP flag transfer.
 332 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 333
 334 ;; Fuxne: The flag forwarding from fmstat to the second instruction is
 335 ;; not modeled at present.
 336
 337 (define_insn_reservation "cortex_a7_f_flags" 4
 338   (and (eq_attr "tune" "cortexa7")
 339        (and (eq_attr "type" "f_flag")
 340             (eq_attr "neon_type" "none")))
 341   "cortex_a7_ex1")
 342
 343 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 344 ;; VFP load/store.
 345 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 346
 347 (define_insn_reservation "cortex_a7_f_loads" 4
 348   (and (eq_attr "tune" "cortexa7")
 349        (and (eq_attr "type" "f_loads")
 350             (eq_attr "neon_type" "none")))
 351   "cortex_a7_ex1")
 352
 353 (define_insn_reservation "cortex_a7_f_loadd" 4
 354   (and (eq_attr "tune" "cortexa7")
 355        (and (eq_attr "type" "f_loadd")
 356             (eq_attr "neon_type" "none")))
 357   "cortex_a7_both")
 358
 359 (define_insn_reservation "cortex_a7_f_stores" 0
 360   (and (eq_attr "tune" "cortexa7")
 361        (and (eq_attr "type" "f_stores")
 362             (eq_attr "neon_type" "none")))
 363   "cortex_a7_ex1")
 364
 365 (define_insn_reservation "cortex_a7_f_stored" 0
 366   (and (eq_attr "tune" "cortexa7")
 367        (and (eq_attr "type" "f_stored")
 368             (eq_attr "neon_type" "none")))
 369   "cortex_a7_both")
 370
 371 ;; Load-to-use for floating-point values has a penalty of one cycle,
 372 ;; i.e. a latency of two.
 373
 374 (define_bypass 2 "cortex_a7_f_loads, cortex_a7_f_loadd"
 375                   "cortex_a7_fpalu,\
 376                    cortex_a7_fpmuls,cortex_a7_fpmacs,\
 377                    cortex_a7_fpmuld,cortex_a7_fpmacd, cortex_a7_fpfmad,\
 378                    cortex_a7_fdivs, cortex_a7_fdivd,\
 379                    cortex_a7_f2r")
 380
 381 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 382 ;; NEON
 383 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 384
 385 ;; Simple modeling for all neon instructions not covered earlier.
 386
 387 (define_insn_reservation "cortex_a7_neon" 4
 388   (and (eq_attr "tune" "cortexa7")
 389        (eq_attr "neon_type"
 390                 "!none,\
 391                   neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
 392                   neon_mul_qqq_8_16_32_ddd_32,\
 393                   neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar,\
 394                   neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
 395                   neon_mla_qqq_8_16,\
 396                   neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long,\
 397                   neon_mla_qqq_32_qqd_32_scalar,\
 398                   neon_mul_ddd_16_scalar_32_16_long_scalar,\
 399                   neon_mul_qqd_32_scalar,\
 400                   neon_mla_ddd_16_scalar_qdd_32_16_long_scalar,\
 401                   neon_fp_vmul_ddd,\
 402                   neon_fp_vmul_qqd,\
 403                   neon_fp_vmla_ddd,\
 404                   neon_fp_vmla_qqq,\
 405                   neon_fp_vmla_ddd_scalar,\
 406                   neon_fp_vmla_qqq_scalar"))
 407   "cortex_a7_both*2")