gcc/config/arm/cortex-a7.md

   1 ;; ARM Cortex-A7 pipeline description
   2 ;; Copyright (C) 2012-2013 Free Software Foundation, Inc.
   3 ;;
   4 ;; Contributed by ARM Ltd.
   5 ;; Based on cortex-a5.md which was originally contributed by CodeSourcery.
   6 ;;
   7 ;; This file is part of GCC.
   8 ;;
   9 ;; GCC is free software; you can redistribute it and/or modify it
  10 ;; under the terms of the GNU General Public License as published by
  11 ;; the Free Software Foundation; either version 3, or (at your option)
  12 ;; any later version.
  13 ;;
  14 ;; GCC is distributed in the hope that it will be useful, but
  15 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17 ;; General Public License for more details.
  18 ;;
  19 ;; You should have received a copy of the GNU General Public License
  20 ;; along with GCC; see the file COPYING3.  If not see
  21 ;; <http://www.gnu.org/licenses/>.
  22
  23 (define_automaton "cortex_a7")
  24
  25 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  26 ;; Functional units.
  27 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  28
  29 ;; The Cortex-A7 pipeline integer and vfp pipeline.
  30 ;; The decode is the same for all instructions, so do not model it.
  31 ;; We only model the first execution stage because
  32 ;; instructions always advance one stage per cycle in order.
  33 ;; We model all of the LS, Branch, ALU, MAC and FPU pipelines together.
  34
  35 (define_cpu_unit "cortex_a7_ex1, cortex_a7_ex2" "cortex_a7")
  36
  37 (define_reservation "cortex_a7_both" "cortex_a7_ex1+cortex_a7_ex2")
  38
  39 (define_cpu_unit "cortex_a7_branch" "cortex_a7")
  40
  41 ;; Cortex-A7 is in order and can dual-issue under limited circumstances.
  42 ;; ex2 can be reserved only after ex1 is reserved.
  43
  44 (final_presence_set "cortex_a7_ex2" "cortex_a7_ex1")
  45
  46 ;; Pseudo-unit for blocking the multiply pipeline when a double-precision
  47 ;; multiply is in progress.
  48
  49 (define_cpu_unit "cortex_a7_fpmul_pipe" "cortex_a7")
  50
  51 ;; The floating-point add pipeline (ex1/f1 stage), used to model the usage
  52 ;; of the add pipeline by fmac instructions, etc.
  53
  54 (define_cpu_unit "cortex_a7_fpadd_pipe" "cortex_a7")
  55
  56 ;; Floating-point div/sqrt (long latency, out-of-order completion).
  57
  58 (define_cpu_unit "cortex_a7_fp_div_sqrt" "cortex_a7")
  59
  60 ;; Neon pipeline
  61 (define_cpu_unit "cortex_a7_neon" "cortex_a7")
  62
  63 (define_reservation "cortex_a7_all" "cortex_a7_both+\
  64                                      cortex_a7_fpmul_pipe+\
  65                                      cortex_a7_fpadd_pipe+\
  66                                      cortex_a7_fp_div_sqrt+\
  67                                      cortex_a7_neon")
  68
  69 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  70 ;; Branches.
  71 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  72
  73 ;; A direct branch can dual issue either as younger or older instruction,
  74 ;; but branches cannot dual issue with branches.
  75 ;; No latency as there is no result.
  76
  77 (define_insn_reservation "cortex_a7_branch" 0
  78   (and (eq_attr "tune" "cortexa7")
  79        (and (eq_attr "type" "branch")
  80             (eq_attr "neon_type" "none")))
  81   "(cortex_a7_ex2|cortex_a7_ex1)+cortex_a7_branch")
  82
  83 ;; A call reserves all issue slots. The result is available the next cycle.
  84 (define_insn_reservation "cortex_a7_call" 1
  85   (and (eq_attr "tune" "cortexa7")
  86        (and (eq_attr "type" "call")
  87             (eq_attr "neon_type" "none")))
  88   "cortex_a7_all")
  89
  90 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  91 ;; ALU instructions.
  92 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  93
  94 ;; ALU instruction with an immediate operand can dual-issue.
  95 (define_insn_reservation "cortex_a7_alu_imm" 2
  96   (and (eq_attr "tune" "cortexa7")
  97        (and (ior (eq_attr "type" "simple_alu_imm")
  98                  (ior (eq_attr "type" "simple_alu_shift")
  99                       (and (eq_attr "insn" "mov")
 100                            (not (eq_attr "length" "8")))))
 101             (eq_attr "neon_type" "none")))
 102   "cortex_a7_ex2|cortex_a7_ex1")
 103
 104 ;; ALU instruction with register operands can dual-issue
 105 ;; with a younger immediate-based instruction.
 106 (define_insn_reservation "cortex_a7_alu_reg" 2
 107   (and (eq_attr "tune" "cortexa7")
 108        (and (eq_attr "type" "alu_reg")
 109             (eq_attr "neon_type" "none")))
 110   "cortex_a7_ex1")
 111
 112 (define_insn_reservation "cortex_a7_alu_shift" 2
 113   (and (eq_attr "tune" "cortexa7")
 114        (and (eq_attr "type" "alu_shift,alu_shift_reg")
 115             (eq_attr "neon_type" "none")))
 116   "cortex_a7_ex1")
 117
 118 ;; Forwarding path for unshifted operands.
 119 (define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_reg,cortex_a7_alu_shift"
 120   "cortex_a7_alu_imm,cortex_a7_alu_reg,cortex_a7_mul")
 121
 122 (define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_reg,cortex_a7_alu_shift"
 123   "cortex_a7_store*"
 124   "arm_no_early_store_addr_dep")
 125
 126 (define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_reg,cortex_a7_alu_shift"
 127   "cortex_a7_alu_shift"
 128   "arm_no_early_alu_shift_dep")
 129
 130 ;; The multiplier pipeline can forward results from wr stage only so
 131 ;; there's no need to specify bypasses.
 132 ;; Multiply instructions cannot dual-issue.
 133
 134 (define_insn_reservation "cortex_a7_mul" 2
 135   (and (eq_attr "tune" "cortexa7")
 136        (and (eq_attr "type" "mult")
 137             (eq_attr "neon_type" "none")))
 138   "cortex_a7_both")
 139
 140 ;; Forward the result of a multiply operation to the accumulator
 141 ;; of the following multiply and accumulate instruction.
 142 (define_bypass 1 "cortex_a7_mul"
 143                  "cortex_a7_mul"
 144                  "arm_mac_accumulator_is_result")
 145
 146 ;; The latency depends on the operands, so we use an estimate here.
 147 (define_insn_reservation "cortex_a7_idiv" 5
 148   (and (eq_attr "tune" "cortexa7")
 149        (eq_attr "insn" "udiv,sdiv"))
 150   "cortex_a7_all*5")
 151
 152 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 153 ;; Load/store instructions.
 154 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 155
 156 ;; Address-generation happens in the issue stage.
 157 ;; Double-word accesses can be issued in a single cycle,
 158 ;; and occupy only one pipeline stage.
 159
 160 (define_insn_reservation "cortex_a7_load1" 2
 161   (and (eq_attr "tune" "cortexa7")
 162        (and (eq_attr "type" "load_byte,load1")
 163             (eq_attr "neon_type" "none")))
 164   "cortex_a7_ex1")
 165
 166 (define_insn_reservation "cortex_a7_store1" 0
 167   (and (eq_attr "tune" "cortexa7")
 168        (and (eq_attr "type" "store1")
 169             (eq_attr "neon_type" "none")))
 170   "cortex_a7_ex1")
 171
 172 (define_insn_reservation "cortex_a7_load2" 2
 173   (and (eq_attr "tune" "cortexa7")
 174        (and (eq_attr "type" "load2")
 175             (eq_attr "neon_type" "none")))
 176   "cortex_a7_both")
 177
 178 (define_insn_reservation "cortex_a7_store2" 0
 179   (and (eq_attr "tune" "cortexa7")
 180        (and (eq_attr "type" "store2")
 181             (eq_attr "neon_type" "none")))
 182   "cortex_a7_both")
 183
 184 (define_insn_reservation "cortex_a7_load3" 3
 185   (and (eq_attr "tune" "cortexa7")
 186        (and (eq_attr "type" "load3")
 187             (eq_attr "neon_type" "none")))
 188   "cortex_a7_both, cortex_a7_ex1")
 189
 190 (define_insn_reservation "cortex_a7_store3" 0
 191   (and (eq_attr "tune" "cortexa7")
 192        (and (eq_attr "type" "store4")
 193             (eq_attr "neon_type" "none")))
 194   "cortex_a7_both, cortex_a7_ex1")
 195
 196 (define_insn_reservation "cortex_a7_load4" 3
 197   (and (eq_attr "tune" "cortexa7")
 198        (and (eq_attr "type" "load4")
 199             (eq_attr "neon_type" "none")))
 200   "cortex_a7_both, cortex_a7_both")
 201
 202 (define_insn_reservation "cortex_a7_store4" 0
 203   (and (eq_attr "tune" "cortexa7")
 204        (and (eq_attr "type" "store3")
 205             (eq_attr "neon_type" "none")))
 206   "cortex_a7_both, cortex_a7_both")
 207
 208 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 209 ;; Floating-point arithmetic.
 210 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 211 ;; Neon integer, neon floating point, and single-precision floating
 212 ;; point instructions of the same type have the same timing
 213 ;; characteristics, but neon instructions cannot dual-issue.
 214
 215 (define_insn_reservation "cortex_a7_fpalu" 4
 216   (and (eq_attr "tune" "cortexa7")
 217        (and (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys,\
 218                              f_cvt, fcmps, fcmpd")
 219             (eq_attr "neon_type" "none")))
 220   "cortex_a7_ex1+cortex_a7_fpadd_pipe")
 221
 222 ;; For fconsts and fconstd, 8-bit immediate data is passed directly from
 223 ;; f1 to f3 (which I think reduces the latency by one cycle).
 224
 225 (define_insn_reservation "cortex_a7_fconst" 3
 226   (and (eq_attr "tune" "cortexa7")
 227        (and (eq_attr "type" "fconsts,fconstd")
 228             (eq_attr "neon_type" "none")))
 229   "cortex_a7_ex1+cortex_a7_fpadd_pipe")
 230
 231 ;; We should try not to attempt to issue a single-precision multiplication in
 232 ;; the middle of a double-precision multiplication operation (the usage of
 233 ;; cortex_a7_fpmul_pipe).
 234
 235 (define_insn_reservation "cortex_a7_fpmuls" 4
 236   (and (eq_attr "tune" "cortexa7")
 237        (and (eq_attr "type" "fmuls")
 238             (eq_attr "neon_type" "none")))
 239   "cortex_a7_ex1+cortex_a7_fpmul_pipe")
 240
 241 (define_insn_reservation "cortex_a7_neon_mul" 4
 242   (and (eq_attr "tune" "cortexa7")
 243        (eq_attr "neon_type"
 244                 "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
 245                  neon_mul_qqq_8_16_32_ddd_32,\
 246                  neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar,\
 247                  neon_mul_ddd_16_scalar_32_16_long_scalar,\
 248                  neon_mul_qqd_32_scalar,\
 249                  neon_fp_vmul_ddd,\
 250                  neon_fp_vmul_qqd"))
 251   "(cortex_a7_both+cortex_a7_fpmul_pipe)*2")
 252
 253 (define_insn_reservation "cortex_a7_fpmacs" 8
 254   (and (eq_attr "tune" "cortexa7")
 255        (and (eq_attr "type" "fmacs,ffmas")
 256             (eq_attr "neon_type" "none")))
 257   "cortex_a7_ex1+cortex_a7_fpmul_pipe")
 258
 259 (define_insn_reservation "cortex_a7_neon_mla" 8
 260   (and (eq_attr "tune" "cortexa7")
 261        (eq_attr "neon_type"
 262                 "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
 263                  neon_mla_qqq_8_16,\
 264                  neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long,\
 265                  neon_mla_qqq_32_qqd_32_scalar,\
 266                  neon_mla_ddd_16_scalar_qdd_32_16_long_scalar,\
 267                  neon_fp_vmla_ddd,\
 268                  neon_fp_vmla_qqq,\
 269                  neon_fp_vmla_ddd_scalar,\
 270                  neon_fp_vmla_qqq_scalar"))
 271   "cortex_a7_both+cortex_a7_fpmul_pipe")
 272
 273 (define_bypass 4 "cortex_a7_fpmacs,cortex_a7_neon_mla"
 274                  "cortex_a7_fpmacs,cortex_a7_neon_mla"
 275                  "arm_mac_accumulator_is_result")
 276
 277 ;; Non-multiply instructions can issue between two cycles of a
 278 ;; double-precision multiply.
 279
 280 (define_insn_reservation "cortex_a7_fpmuld" 7
 281   (and (eq_attr "tune" "cortexa7")
 282        (and (eq_attr "type" "fmuld")
 283             (eq_attr "neon_type" "none")))
 284   "cortex_a7_ex1+cortex_a7_fpmul_pipe, cortex_a7_fpmul_pipe*3")
 285
 286 (define_insn_reservation "cortex_a7_fpmacd" 11
 287   (and (eq_attr "tune" "cortexa7")
 288        (and (eq_attr "type" "fmacd")
 289             (eq_attr "neon_type" "none")))
 290   "cortex_a7_ex1+cortex_a7_fpmul_pipe, cortex_a7_fpmul_pipe*3")
 291
 292 (define_insn_reservation "cortex_a7_fpfmad" 8
 293   (and (eq_attr "tune" "cortexa7")
 294        (and (eq_attr "type" "ffmad")
 295             (eq_attr "neon_type" "none")))
 296   "cortex_a7_ex1+cortex_a7_fpmul_pipe, cortex_a7_fpmul_pipe*4")
 297
 298 (define_bypass 7 "cortex_a7_fpmacd"
 299                  "cortex_a7_fpmacd,cortex_a7_fpfmad"
 300                  "arm_mac_accumulator_is_result")
 301
 302 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 303 ;; Floating-point divide/square root instructions.
 304 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 305
 306 (define_insn_reservation "cortex_a7_fdivs" 16
 307   (and (eq_attr "tune" "cortexa7")
 308        (and (eq_attr "type" "fdivs")
 309             (eq_attr "neon_type" "none")))
 310   "cortex_a7_ex1+cortex_a7_fp_div_sqrt, cortex_a7_fp_div_sqrt * 13")
 311
 312 (define_insn_reservation "cortex_a7_fdivd" 31
 313   (and (eq_attr "tune" "cortexa7")
 314        (and (eq_attr "type" "fdivd")
 315             (eq_attr "neon_type" "none")))
 316   "cortex_a7_ex1+cortex_a7_fp_div_sqrt, cortex_a7_fp_div_sqrt * 28")
 317
 318 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 319 ;; VFP to/from core transfers.
 320 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 321
 322 ;; Core-to-VFP transfers.
 323
 324 (define_insn_reservation "cortex_a7_r2f" 4
 325   (and (eq_attr "tune" "cortexa7")
 326        (and (eq_attr "type" "r_2_f")
 327             (eq_attr "neon_type" "none")))
 328   "cortex_a7_both")
 329
 330 (define_insn_reservation "cortex_a7_f2r" 2
 331   (and (eq_attr "tune" "cortexa7")
 332        (and (eq_attr "type" "f_2_r")
 333             (eq_attr "neon_type" "none")))
 334   "cortex_a7_ex1")
 335
 336 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 337 ;; VFP flag transfer.
 338 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 339
 340 ;; Fuxne: The flag forwarding from fmstat to the second instruction is
 341 ;; not modeled at present.
 342
 343 (define_insn_reservation "cortex_a7_f_flags" 4
 344   (and (eq_attr "tune" "cortexa7")
 345        (and (eq_attr "type" "f_flag")
 346             (eq_attr "neon_type" "none")))
 347   "cortex_a7_ex1")
 348
 349 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 350 ;; VFP load/store.
 351 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 352
 353 (define_insn_reservation "cortex_a7_f_loads" 4
 354   (and (eq_attr "tune" "cortexa7")
 355        (and (eq_attr "type" "f_loads")
 356             (eq_attr "neon_type" "none")))
 357   "cortex_a7_ex1")
 358
 359 (define_insn_reservation "cortex_a7_f_loadd" 4
 360   (and (eq_attr "tune" "cortexa7")
 361        (and (eq_attr "type" "f_loadd")
 362             (eq_attr "neon_type" "none")))
 363   "cortex_a7_both")
 364
 365 (define_insn_reservation "cortex_a7_f_stores" 0
 366   (and (eq_attr "tune" "cortexa7")
 367        (and (eq_attr "type" "f_stores")
 368             (eq_attr "neon_type" "none")))
 369   "cortex_a7_ex1")
 370
 371 (define_insn_reservation "cortex_a7_f_stored" 0
 372   (and (eq_attr "tune" "cortexa7")
 373        (and (eq_attr "type" "f_stored")
 374             (eq_attr "neon_type" "none")))
 375   "cortex_a7_both")
 376
 377 ;; Load-to-use for floating-point values has a penalty of one cycle,
 378 ;; i.e. a latency of two.
 379
 380 (define_bypass 2 "cortex_a7_f_loads, cortex_a7_f_loadd"
 381                   "cortex_a7_fpalu,\
 382                    cortex_a7_fpmuls,cortex_a7_fpmacs,\
 383                    cortex_a7_fpmuld,cortex_a7_fpmacd, cortex_a7_fpfmad,\
 384                    cortex_a7_fdivs, cortex_a7_fdivd,\
 385                    cortex_a7_f2r")
 386
 387 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 388 ;; NEON
 389 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 390
 391 ;; Simple modeling for all neon instructions not covered earlier.
 392
 393 (define_insn_reservation "cortex_a7_neon" 4
 394   (and (eq_attr "tune" "cortexa7")
 395        (eq_attr "neon_type"
 396                 "!none,\
 397                   neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
 398                   neon_mul_qqq_8_16_32_ddd_32,\
 399                   neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar,\
 400                   neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
 401                   neon_mla_qqq_8_16,\
 402                   neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long,\
 403                   neon_mla_qqq_32_qqd_32_scalar,\
 404                   neon_mul_ddd_16_scalar_32_16_long_scalar,\
 405                   neon_mul_qqd_32_scalar,\
 406                   neon_mla_ddd_16_scalar_qdd_32_16_long_scalar,\
 407                   neon_fp_vmul_ddd,\
 408                   neon_fp_vmul_qqd,\
 409                   neon_fp_vmla_ddd,\
 410                   neon_fp_vmla_qqq,\
 411                   neon_fp_vmla_ddd_scalar,\
 412                   neon_fp_vmla_qqq_scalar"))
 413   "cortex_a7_both*2")