gcc/config/arm/cortex-a7.md

   1 ;; ARM Cortex-A7 pipeline description
   2 ;; Copyright (C) 2012-2013 Free Software Foundation, Inc.
   3 ;;
   4 ;; Contributed by ARM Ltd.
   5 ;; Based on cortex-a5.md which was originally contributed by CodeSourcery.
   6 ;;
   7 ;; This file is part of GCC.
   8 ;;
   9 ;; GCC is free software; you can redistribute it and/or modify it
  10 ;; under the terms of the GNU General Public License as published by
  11 ;; the Free Software Foundation; either version 3, or (at your option)
  12 ;; any later version.
  13 ;;
  14 ;; GCC is distributed in the hope that it will be useful, but
  15 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17 ;; General Public License for more details.
  18 ;;
  19 ;; You should have received a copy of the GNU General Public License
  20 ;; along with GCC; see the file COPYING3.  If not see
  21 ;; <http://www.gnu.org/licenses/>.
  22
  23 (define_automaton "cortex_a7")
  24
  25 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  26 ;; Functional units.
  27 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  28
  29 ;; The Cortex-A7 pipeline integer and vfp pipeline.
  30 ;; The decode is the same for all instructions, so do not model it.
  31 ;; We only model the first execution stage because
  32 ;; instructions always advance one stage per cycle in order.
  33 ;; We model all of the LS, Branch, ALU, MAC and FPU pipelines together.
  34
  35 (define_cpu_unit "cortex_a7_ex1, cortex_a7_ex2" "cortex_a7")
  36
  37 (define_reservation "cortex_a7_both" "cortex_a7_ex1+cortex_a7_ex2")
  38
  39 (define_cpu_unit "cortex_a7_branch" "cortex_a7")
  40
  41 ;; Cortex-A7 is in order and can dual-issue under limited circumstances.
  42 ;; ex2 can be reserved only after ex1 is reserved.
  43
  44 (final_presence_set "cortex_a7_ex2" "cortex_a7_ex1")
  45
  46 ;; Pseudo-unit for blocking the multiply pipeline when a double-precision
  47 ;; multiply is in progress.
  48
  49 (define_cpu_unit "cortex_a7_fpmul_pipe" "cortex_a7")
  50
  51 ;; The floating-point add pipeline (ex1/f1 stage), used to model the usage
  52 ;; of the add pipeline by fmac instructions, etc.
  53
  54 (define_cpu_unit "cortex_a7_fpadd_pipe" "cortex_a7")
  55
  56 ;; Floating-point div/sqrt (long latency, out-of-order completion).
  57
  58 (define_cpu_unit "cortex_a7_fp_div_sqrt" "cortex_a7")
  59
  60 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  61 ;; Branches.
  62 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  63
  64 ;; A direct branch can dual issue either as younger or older instruction,
  65 ;; but branches cannot dual issue with branches.
  66 ;; No latency as there is no result.
  67
  68 (define_insn_reservation "cortex_a7_branch" 0
  69   (and (eq_attr "tune" "cortexa7")
  70        (eq_attr "type" "branch"))
  71   "(cortex_a7_ex2|cortex_a7_ex1)+cortex_a7_branch")
  72
  73 ;; Call cannot dual-issue as an older instruction. It can dual-issue
  74 ;; as a younger instruction, or single-issue.  Call cannot dual-issue
  75 ;; with another branch instruction.  The result is available the next
  76 ;; cycle.
  77 (define_insn_reservation "cortex_a7_call" 1
  78   (and (eq_attr "tune" "cortexa7")
  79        (eq_attr "type" "call"))
  80   "(cortex_a7_ex2|cortex_a7_both)+cortex_a7_branch")
  81
  82 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  83 ;; ALU instructions.
  84 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  85
  86 ;; ALU instruction with an immediate operand can dual-issue.
  87 (define_insn_reservation "cortex_a7_alu_imm" 2
  88   (and (eq_attr "tune" "cortexa7")
  89        (ior (eq_attr "type" "adr,alu_imm,alus_imm,logic_imm,logics_imm,\
  90                              mov_imm,mvn_imm,extend")
  91             (and (eq_attr "type" "mov_reg,mov_shift,mov_shift_reg")
  92                  (not (eq_attr "length" "8")))))
  93   "cortex_a7_ex2|cortex_a7_ex1")
  94
  95 ;; ALU instruction with register operands can dual-issue
  96 ;; with a younger immediate-based instruction.
  97 (define_insn_reservation "cortex_a7_alu_reg" 2
  98   (and (eq_attr "tune" "cortexa7")
  99        (eq_attr "type" "alu_reg,alus_reg,logic_reg,logics_reg,\
 100                         adc_imm,adcs_imm,adc_reg,adcs_reg,\
 101                         bfm,rev,\
 102                         shift_imm,shift_reg,mov_reg,mvn_reg"))
 103   "cortex_a7_ex1")
 104
 105 (define_insn_reservation "cortex_a7_alu_shift" 2
 106   (and (eq_attr "tune" "cortexa7")
 107        (eq_attr "type" "alu_shift_imm,alus_shift_imm,\
 108                         logic_shift_imm,logics_shift_imm,\
 109                         alu_shift_reg,alus_shift_reg,\
 110                         logic_shift_reg,logics_shift_reg,\
 111                         mov_shift,mov_shift_reg,\
 112                         mvn_shift,mvn_shift_reg,\
 113                         multiple,no_insn"))
 114   "cortex_a7_ex1")
 115
 116 ;; Forwarding path for unshifted operands.
 117 (define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_reg,cortex_a7_alu_shift"
 118   "cortex_a7_alu_imm,cortex_a7_alu_reg,cortex_a7_mul")
 119
 120 (define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_reg,cortex_a7_alu_shift"
 121   "cortex_a7_store*"
 122   "arm_no_early_store_addr_dep")
 123
 124 (define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_reg,cortex_a7_alu_shift"
 125   "cortex_a7_alu_shift"
 126   "arm_no_early_alu_shift_dep")
 127
 128 ;; The multiplier pipeline can forward results from wr stage only so
 129 ;; there's no need to specify bypasses.
 130 ;; Multiply instructions cannot dual-issue.
 131
 132 (define_insn_reservation "cortex_a7_mul" 2
 133   (and (eq_attr "tune" "cortexa7")
 134        (ior (eq_attr "mul32" "yes")
 135             (eq_attr "mul64" "yes")))
 136   "cortex_a7_both")
 137
 138 ;; Forward the result of a multiply operation to the accumulator
 139 ;; of the following multiply and accumulate instruction.
 140 (define_bypass 1 "cortex_a7_mul"
 141                  "cortex_a7_mul"
 142                  "arm_mac_accumulator_is_result")
 143
 144 ;; The latency depends on the operands, so we use an estimate here.
 145 (define_insn_reservation "cortex_a7_idiv" 5
 146   (and (eq_attr "tune" "cortexa7")
 147        (eq_attr "type" "udiv,sdiv"))
 148   "cortex_a7_both*5")
 149
 150 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 151 ;; Load/store instructions.
 152 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 153
 154 ;; Address-generation happens in the issue stage.
 155 ;; Double-word accesses can be issued in a single cycle,
 156 ;; and occupy only one pipeline stage.
 157
 158 (define_insn_reservation "cortex_a7_load1" 2
 159   (and (eq_attr "tune" "cortexa7")
 160        (eq_attr "type" "load_byte,load1"))
 161   "cortex_a7_ex1")
 162
 163 (define_insn_reservation "cortex_a7_store1" 0
 164   (and (eq_attr "tune" "cortexa7")
 165        (eq_attr "type" "store1"))
 166   "cortex_a7_ex1")
 167
 168 (define_insn_reservation "cortex_a7_load2" 2
 169   (and (eq_attr "tune" "cortexa7")
 170        (eq_attr "type" "load2"))
 171   "cortex_a7_both")
 172
 173 (define_insn_reservation "cortex_a7_store2" 0
 174   (and (eq_attr "tune" "cortexa7")
 175        (eq_attr "type" "store2"))
 176   "cortex_a7_both")
 177
 178 (define_insn_reservation "cortex_a7_load3" 3
 179   (and (eq_attr "tune" "cortexa7")
 180        (eq_attr "type" "load3"))
 181   "cortex_a7_both, cortex_a7_ex1")
 182
 183 (define_insn_reservation "cortex_a7_store3" 0
 184   (and (eq_attr "tune" "cortexa7")
 185        (eq_attr "type" "store4"))
 186   "cortex_a7_both, cortex_a7_ex1")
 187
 188 (define_insn_reservation "cortex_a7_load4" 3
 189   (and (eq_attr "tune" "cortexa7")
 190        (eq_attr "type" "load4"))
 191   "cortex_a7_both, cortex_a7_both")
 192
 193 (define_insn_reservation "cortex_a7_store4" 0
 194   (and (eq_attr "tune" "cortexa7")
 195        (eq_attr "type" "store3"))
 196   "cortex_a7_both, cortex_a7_both")
 197
 198 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 199 ;; Floating-point arithmetic.
 200 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 201 ;; Neon integer, neon floating point, and single-precision floating
 202 ;; point instructions of the same type have the same timing
 203 ;; characteristics, but neon instructions cannot dual-issue.
 204
 205 (define_insn_reservation "cortex_a7_fpalu" 4
 206   (and (eq_attr "tune" "cortexa7")
 207        (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys,\
 208                         f_cvt, f_cvtf2i, f_cvti2f, fcmps, fcmpd"))
 209   "cortex_a7_ex1+cortex_a7_fpadd_pipe")
 210
 211 ;; For fconsts and fconstd, 8-bit immediate data is passed directly from
 212 ;; f1 to f3 (which I think reduces the latency by one cycle).
 213
 214 (define_insn_reservation "cortex_a7_fconst" 3
 215   (and (eq_attr "tune" "cortexa7")
 216        (eq_attr "type" "fconsts,fconstd"))
 217   "cortex_a7_ex1+cortex_a7_fpadd_pipe")
 218
 219 ;; We should try not to attempt to issue a single-precision multiplication in
 220 ;; the middle of a double-precision multiplication operation (the usage of
 221 ;; cortex_a7_fpmul_pipe).
 222
 223 (define_insn_reservation "cortex_a7_fpmuls" 4
 224   (and (eq_attr "tune" "cortexa7")
 225        (eq_attr "type" "fmuls"))
 226   "cortex_a7_ex1+cortex_a7_fpmul_pipe")
 227
 228 (define_insn_reservation "cortex_a7_neon_mul" 4
 229   (and (eq_attr "tune" "cortexa7")
 230        (eq_attr "type"
 231                 "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
 232                  neon_mul_qqq_8_16_32_ddd_32,\
 233                  neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar,\
 234                  neon_mul_ddd_16_scalar_32_16_long_scalar,\
 235                  neon_mul_qqd_32_scalar,\
 236                  neon_fp_vmul_ddd,\
 237                  neon_fp_vmul_qqd"))
 238   "(cortex_a7_both+cortex_a7_fpmul_pipe)*2")
 239
 240 (define_insn_reservation "cortex_a7_fpmacs" 8
 241   (and (eq_attr "tune" "cortexa7")
 242        (eq_attr "type" "fmacs,ffmas"))
 243   "cortex_a7_ex1+cortex_a7_fpmul_pipe")
 244
 245 (define_insn_reservation "cortex_a7_neon_mla" 8
 246   (and (eq_attr "tune" "cortexa7")
 247        (eq_attr "type"
 248                 "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
 249                  neon_mla_qqq_8_16,\
 250                  neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long,\
 251                  neon_mla_qqq_32_qqd_32_scalar,\
 252                  neon_mla_ddd_16_scalar_qdd_32_16_long_scalar,\
 253                  neon_fp_vmla_ddd,\
 254                  neon_fp_vmla_qqq,\
 255                  neon_fp_vmla_ddd_scalar,\
 256                  neon_fp_vmla_qqq_scalar"))
 257   "cortex_a7_both+cortex_a7_fpmul_pipe")
 258
 259 (define_bypass 4 "cortex_a7_fpmacs,cortex_a7_neon_mla"
 260                  "cortex_a7_fpmacs,cortex_a7_neon_mla"
 261                  "arm_mac_accumulator_is_result")
 262
 263 ;; Non-multiply instructions can issue between two cycles of a
 264 ;; double-precision multiply.
 265
 266 (define_insn_reservation "cortex_a7_fpmuld" 7
 267   (and (eq_attr "tune" "cortexa7")
 268        (eq_attr "type" "fmuld"))
 269   "cortex_a7_ex1+cortex_a7_fpmul_pipe, cortex_a7_fpmul_pipe*3")
 270
 271 (define_insn_reservation "cortex_a7_fpmacd" 11
 272   (and (eq_attr "tune" "cortexa7")
 273        (eq_attr "type" "fmacd"))
 274   "cortex_a7_ex1+cortex_a7_fpmul_pipe, cortex_a7_fpmul_pipe*3")
 275
 276 (define_insn_reservation "cortex_a7_fpfmad" 8
 277   (and (eq_attr "tune" "cortexa7")
 278        (eq_attr "type" "ffmad"))
 279   "cortex_a7_ex1+cortex_a7_fpmul_pipe, cortex_a7_fpmul_pipe*4")
 280
 281 (define_bypass 7 "cortex_a7_fpmacd"
 282                  "cortex_a7_fpmacd,cortex_a7_fpfmad"
 283                  "arm_mac_accumulator_is_result")
 284
 285 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 286 ;; Floating-point divide/square root instructions.
 287 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 288
 289 (define_insn_reservation "cortex_a7_fdivs" 16
 290   (and (eq_attr "tune" "cortexa7")
 291        (eq_attr "type" "fdivs, fsqrts"))
 292   "cortex_a7_ex1+cortex_a7_fp_div_sqrt, cortex_a7_fp_div_sqrt * 13")
 293
 294 (define_insn_reservation "cortex_a7_fdivd" 31
 295   (and (eq_attr "tune" "cortexa7")
 296        (eq_attr "type" "fdivd, fsqrtd"))
 297   "cortex_a7_ex1+cortex_a7_fp_div_sqrt, cortex_a7_fp_div_sqrt * 28")
 298
 299 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 300 ;; VFP to/from core transfers.
 301 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 302
 303 ;; Core-to-VFP transfers.
 304
 305 (define_insn_reservation "cortex_a7_r2f" 4
 306   (and (eq_attr "tune" "cortexa7")
 307        (eq_attr "type" "f_mcr,f_mcrr"))
 308   "cortex_a7_both")
 309
 310 (define_insn_reservation "cortex_a7_f2r" 2
 311   (and (eq_attr "tune" "cortexa7")
 312        (eq_attr "type" "f_mrc,f_mrrc"))
 313   "cortex_a7_ex1")
 314
 315 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 316 ;; VFP flag transfer.
 317 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 318
 319 ;; Fuxne: The flag forwarding from fmstat to the second instruction is
 320 ;; not modeled at present.
 321
 322 (define_insn_reservation "cortex_a7_f_flags" 4
 323   (and (eq_attr "tune" "cortexa7")
 324        (eq_attr "type" "f_flag"))
 325   "cortex_a7_ex1")
 326
 327 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 328 ;; VFP load/store.
 329 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 330
 331 (define_insn_reservation "cortex_a7_f_loads" 4
 332   (and (eq_attr "tune" "cortexa7")
 333        (eq_attr "type" "f_loads"))
 334   "cortex_a7_ex1")
 335
 336 (define_insn_reservation "cortex_a7_f_loadd" 4
 337   (and (eq_attr "tune" "cortexa7")
 338        (eq_attr "type" "f_loadd"))
 339   "cortex_a7_both")
 340
 341 (define_insn_reservation "cortex_a7_f_stores" 0
 342   (and (eq_attr "tune" "cortexa7")
 343        (eq_attr "type" "f_stores"))
 344   "cortex_a7_ex1")
 345
 346 (define_insn_reservation "cortex_a7_f_stored" 0
 347   (and (eq_attr "tune" "cortexa7")
 348        (eq_attr "type" "f_stored"))
 349   "cortex_a7_both")
 350
 351 ;; Load-to-use for floating-point values has a penalty of one cycle,
 352 ;; i.e. a latency of two.
 353
 354 (define_bypass 2 "cortex_a7_f_loads, cortex_a7_f_loadd"
 355                   "cortex_a7_fpalu,\
 356                    cortex_a7_fpmuls,cortex_a7_fpmacs,\
 357                    cortex_a7_fpmuld,cortex_a7_fpmacd, cortex_a7_fpfmad,\
 358                    cortex_a7_fdivs, cortex_a7_fdivd,\
 359                    cortex_a7_f2r")
 360
 361 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 362 ;; NEON
 363 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 364
 365 ;; Simple modeling for all neon instructions not covered earlier.
 366
 367 (define_insn_reservation "cortex_a7_neon" 4
 368   (and (eq_attr "tune" "cortexa7")
 369        (eq_attr "type"
 370                 "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
 371                  neon_mul_qqq_8_16_32_ddd_32,\
 372                  neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar,\
 373                  neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
 374                  neon_mla_qqq_8_16,\
 375                  neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long,\
 376                  neon_mla_qqq_32_qqd_32_scalar,\
 377                  neon_mul_ddd_16_scalar_32_16_long_scalar,\
 378                  neon_mul_qqd_32_scalar,\
 379                  neon_mla_ddd_16_scalar_qdd_32_16_long_scalar,\
 380                  neon_fp_vmul_ddd,\
 381                  neon_fp_vmul_qqd,\
 382                  neon_fp_vmla_ddd,\
 383                  neon_fp_vmla_qqq,\
 384                  neon_fp_vmla_ddd_scalar,\
 385                  neon_fp_vmla_qqq_scalar"))
 386   "cortex_a7_both*2")