gcc/config/arm/cortex-a9.md

   1 ;; ARM Cortex-A9 pipeline description
   2 ;; Copyright (C) 2008-2013 Free Software Foundation, Inc.
   3 ;; Originally written by CodeSourcery for VFP.
   4 ;;
   5 ;; Rewritten by Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
   6 ;; Integer Pipeline description contributed by ARM Ltd.
   7 ;; VFP Pipeline description rewritten and contributed by ARM Ltd.
   8
   9 ;; This file is part of GCC.
  10 ;;
  11 ;; GCC is free software; you can redistribute it and/or modify it
  12 ;; under the terms of the GNU General Public License as published by
  13 ;; the Free Software Foundation; either version 3, or (at your option)
  14 ;; any later version.
  15 ;;
  16 ;; GCC is distributed in the hope that it will be useful, but
  17 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  18 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  19 ;; General Public License for more details.
  20 ;;
  21 ;; You should have received a copy of the GNU General Public License
  22 ;; along with GCC; see the file COPYING3.  If not see
  23 ;; <http://www.gnu.org/licenses/>.
  24
  25 (define_automaton "cortex_a9")
  26
  27 ;; The Cortex-A9 core is modelled as a dual issue pipeline that has
  28 ;; the following components.
  29 ;; 1. 1 Load Store Pipeline.
  30 ;; 2. P0 / main pipeline for data processing instructions.
  31 ;; 3. P1 / Dual pipeline for Data processing instructions.
  32 ;; 4. MAC pipeline for multiply as well as multiply
  33 ;;    and accumulate instructions.
  34 ;; 5. 1 VFP and an optional Neon unit.
  35 ;; The Load/Store, VFP and Neon issue pipeline are multiplexed.
  36 ;; The P0 / main pipeline and M1 stage of the MAC pipeline are
  37 ;;   multiplexed.
  38 ;; The P1 / dual pipeline and M2 stage of the MAC pipeline are
  39 ;;   multiplexed.
  40 ;; There are only 4 integer register read ports and hence at any point of
  41 ;; time we can't have issue down the E1 and the E2 ports unless
  42 ;; of course there are bypass paths that get exercised.
  43 ;; Both P0 and P1 have 2 stages E1 and E2.
  44 ;; Data processing instructions issue to E1 or E2 depending on
  45 ;; whether they have an early shift or not.
  46
  47 (define_cpu_unit "ca9_issue_vfp_neon, cortex_a9_ls" "cortex_a9")
  48 (define_cpu_unit "cortex_a9_p0_e1, cortex_a9_p0_e2" "cortex_a9")
  49 (define_cpu_unit "cortex_a9_p1_e1, cortex_a9_p1_e2" "cortex_a9")
  50 (define_cpu_unit "cortex_a9_p0_wb, cortex_a9_p1_wb" "cortex_a9")
  51 (define_cpu_unit "cortex_a9_mac_m1, cortex_a9_mac_m2" "cortex_a9")
  52 (define_cpu_unit "cortex_a9_branch, cortex_a9_issue_branch" "cortex_a9")
  53
  54 (define_reservation "cortex_a9_p0_default" "cortex_a9_p0_e2, cortex_a9_p0_wb")
  55 (define_reservation "cortex_a9_p1_default" "cortex_a9_p1_e2, cortex_a9_p1_wb")
  56 (define_reservation "cortex_a9_p0_shift" "cortex_a9_p0_e1, cortex_a9_p0_default")
  57 (define_reservation "cortex_a9_p1_shift" "cortex_a9_p1_e1, cortex_a9_p1_default")
  58
  59 (define_reservation "cortex_a9_multcycle1"
  60   "cortex_a9_p0_e2 + cortex_a9_mac_m1 + cortex_a9_mac_m2 + \
  61 cortex_a9_p1_e2 + cortex_a9_p0_e1 + cortex_a9_p1_e1")
  62
  63 (define_reservation "cortex_a9_mult16"
  64   "cortex_a9_mac_m1, cortex_a9_mac_m2, cortex_a9_p0_wb")
  65 (define_reservation "cortex_a9_mac16"
  66   "cortex_a9_multcycle1, cortex_a9_mac_m2, cortex_a9_p0_wb")
  67 (define_reservation "cortex_a9_mult"
  68   "cortex_a9_mac_m1*2, cortex_a9_mac_m2, cortex_a9_p0_wb")
  69 (define_reservation "cortex_a9_mac"
  70   "cortex_a9_multcycle1*2 ,cortex_a9_mac_m2, cortex_a9_p0_wb")
  71 (define_reservation "cortex_a9_mult_long"
  72   "cortex_a9_mac_m1*3, cortex_a9_mac_m2, cortex_a9_p0_wb")
  73
  74 ;; Issue at the same time along the load store pipeline and
  75 ;; the VFP / Neon pipeline is not possible.
  76 (exclusion_set "cortex_a9_ls" "ca9_issue_vfp_neon")
  77
  78 ;; Default data processing instruction without any shift
  79 ;; The only exception to this is the mov instruction
  80 ;; which can go down E2 without any problem.
  81 (define_insn_reservation "cortex_a9_dp" 2
  82   (and (eq_attr "tune" "cortexa9")
  83        (and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
  84                              mov_imm,mov_reg,mvn_imm,mvn_reg,\
  85                              mov_shift_reg,mov_shift")
  86             (eq_attr "neon_type" "none")))
  87   "cortex_a9_p0_default|cortex_a9_p1_default")
  88
  89 ;; An instruction using the shifter will go down E1.
  90 (define_insn_reservation "cortex_a9_dp_shift" 3
  91    (and (eq_attr "tune" "cortexa9")
  92         (eq_attr "type" "arlo_shift_reg,extend,arlo_shift,\
  93                          mvn_shift,mvn_shift_reg"))
  94    "cortex_a9_p0_shift | cortex_a9_p1_shift")
  95
  96 ;; Loads have a latency of 4 cycles.
  97 ;; We don't model autoincrement instructions. These
  98 ;; instructions use the load store pipeline and 1 of
  99 ;; the E2 units to write back the result of the increment.
 100
 101 (define_insn_reservation "cortex_a9_load1_2" 4
 102   (and (eq_attr "tune" "cortexa9")
 103        (eq_attr "type" "load1, load2, load_byte, f_loads, f_loadd"))
 104   "cortex_a9_ls")
 105
 106 ;; Loads multiples and store multiples can't be issued for 2 cycles in a
 107 ;; row. The description below assumes that addresses are 64 bit aligned.
 108 ;; If not, there is an extra cycle latency which is not modelled.
 109
 110 (define_insn_reservation "cortex_a9_load3_4" 5
 111   (and (eq_attr "tune" "cortexa9")
 112        (eq_attr "type" "load3, load4"))
 113   "cortex_a9_ls, cortex_a9_ls")
 114
 115 (define_insn_reservation "cortex_a9_store1_2" 0
 116   (and (eq_attr "tune" "cortexa9")
 117        (eq_attr "type" "store1, store2, f_stores, f_stored"))
 118   "cortex_a9_ls")
 119
 120 ;; Almost all our store multiples use an auto-increment
 121 ;; form. Don't issue back to back load and store multiples
 122 ;; because the load store unit will stall.
 123
 124 (define_insn_reservation "cortex_a9_store3_4" 0
 125   (and (eq_attr "tune" "cortexa9")
 126        (eq_attr "type" "store3, store4"))
 127   "cortex_a9_ls+(cortex_a9_p0_default | cortex_a9_p1_default), cortex_a9_ls")
 128
 129 ;; We get 16*16 multiply / mac results in 3 cycles.
 130 (define_insn_reservation "cortex_a9_mult16" 3
 131   (and (eq_attr "tune" "cortexa9")
 132        (eq_attr "type" "smulxy"))
 133        "cortex_a9_mult16")
 134
 135 ;; The 16*16 mac is slightly different that it
 136 ;; reserves M1 and M2 in the same cycle.
 137 (define_insn_reservation "cortex_a9_mac16" 3
 138   (and (eq_attr "tune" "cortexa9")
 139        (eq_attr "type" "smlaxy"))
 140   "cortex_a9_mac16")
 141
 142 (define_insn_reservation "cortex_a9_multiply" 4
 143   (and (eq_attr "tune" "cortexa9")
 144        (eq_attr "type" "mul,smmul,smmulr"))
 145        "cortex_a9_mult")
 146
 147 (define_insn_reservation "cortex_a9_mac" 4
 148   (and (eq_attr "tune" "cortexa9")
 149        (eq_attr "type" "mla,smmla"))
 150        "cortex_a9_mac")
 151
 152 (define_insn_reservation "cortex_a9_multiply_long" 5
 153   (and (eq_attr "tune" "cortexa9")
 154        (eq_attr "type" "smull,umull,smulls,umulls,smlal,smlals,umlal,umlals"))
 155        "cortex_a9_mult_long")
 156
 157 ;; An instruction with a result in E2 can be forwarded
 158 ;; to E2 or E1 or M1 or the load store unit in the next cycle.
 159
 160 (define_bypass 1 "cortex_a9_dp"
 161                  "cortex_a9_dp_shift, cortex_a9_multiply,
 162  cortex_a9_load1_2, cortex_a9_dp, cortex_a9_store1_2,
 163  cortex_a9_mult16, cortex_a9_mac16, cortex_a9_mac, cortex_a9_store3_4, cortex_a9_load3_4,
 164  cortex_a9_multiply_long")
 165
 166 (define_bypass 2 "cortex_a9_dp_shift"
 167                  "cortex_a9_dp_shift, cortex_a9_multiply,
 168  cortex_a9_load1_2, cortex_a9_dp, cortex_a9_store1_2,
 169  cortex_a9_mult16, cortex_a9_mac16, cortex_a9_mac, cortex_a9_store3_4, cortex_a9_load3_4,
 170  cortex_a9_multiply_long")
 171
 172 ;; An instruction in the load store pipeline can provide
 173 ;; read access to a DP instruction in the P0 default pipeline
 174 ;; before the writeback stage.
 175
 176 (define_bypass 3 "cortex_a9_load1_2" "cortex_a9_dp, cortex_a9_load1_2,
 177 cortex_a9_store3_4, cortex_a9_store1_2")
 178
 179 (define_bypass 4 "cortex_a9_load3_4" "cortex_a9_dp, cortex_a9_load1_2,
 180 cortex_a9_store3_4, cortex_a9_store1_2,  cortex_a9_load3_4")
 181
 182 ;; Calls and branches.
 183
 184 ;; Branch instructions
 185
 186 (define_insn_reservation "cortex_a9_branch" 0
 187   (and (eq_attr "tune" "cortexa9")
 188        (eq_attr "type" "branch"))
 189   "cortex_a9_branch")
 190
 191 ;; Call latencies are essentially 0 but make sure
 192 ;; dual issue doesn't happen i.e the next instruction
 193 ;; starts at the next cycle.
 194 (define_insn_reservation "cortex_a9_call"  0
 195   (and (eq_attr "tune" "cortexa9")
 196        (eq_attr "type" "call"))
 197   "cortex_a9_issue_branch + cortex_a9_multcycle1 + cortex_a9_ls + ca9_issue_vfp_neon")
 198
 199
 200 ;; Pipelining for VFP instructions.
 201 ;; Issue happens either along load store unit or the VFP / Neon unit.
 202 ;; Pipeline   Instruction Classification.
 203 ;; FPS - fcpys, ffariths, ffarithd,r_2_f,f_2_r
 204 ;; FP_ADD   - fadds, faddd, fcmps (1)
 205 ;; FPMUL   - fmul{s,d}, fmac{s,d}, ffma{s,d}
 206 ;; FPDIV - fdiv{s,d}
 207 (define_cpu_unit "ca9fps" "cortex_a9")
 208 (define_cpu_unit "ca9fp_add1, ca9fp_add2, ca9fp_add3, ca9fp_add4" "cortex_a9")
 209 (define_cpu_unit "ca9fp_mul1, ca9fp_mul2 , ca9fp_mul3, ca9fp_mul4" "cortex_a9")
 210 (define_cpu_unit "ca9fp_ds1" "cortex_a9")
 211
 212
 213 ;; fmrs, fmrrd, fmstat and fmrx - The data is available after 1 cycle.
 214 (define_insn_reservation "cortex_a9_fps" 2
 215  (and (eq_attr "tune" "cortexa9")
 216       (eq_attr "type" "fcpys, fconsts, fconstd, ffariths, ffarithd, r_2_f, f_2_r, f_flag"))
 217  "ca9_issue_vfp_neon + ca9fps")
 218
 219 (define_bypass 1
 220   "cortex_a9_fps"
 221   "cortex_a9_fadd, cortex_a9_fps, cortex_a9_fcmp, cortex_a9_dp, cortex_a9_dp_shift, cortex_a9_multiply, cortex_a9_multiply_long")
 222
 223 ;; Scheduling on the FP_ADD pipeline.
 224 (define_reservation "ca9fp_add" "ca9_issue_vfp_neon + ca9fp_add1, ca9fp_add2, ca9fp_add3, ca9fp_add4")
 225
 226 (define_insn_reservation "cortex_a9_fadd" 4
 227   (and (eq_attr "tune" "cortexa9")
 228        (eq_attr "type" "fadds, faddd, f_cvt"))
 229   "ca9fp_add")
 230
 231 (define_insn_reservation "cortex_a9_fcmp" 1
 232   (and (eq_attr "tune" "cortexa9")
 233       (eq_attr "type" "fcmps, fcmpd"))
 234  "ca9_issue_vfp_neon + ca9fp_add1")
 235
 236 ;; Scheduling for the Multiply and MAC instructions.
 237 (define_reservation "ca9fmuls"
 238   "ca9fp_mul1 + ca9_issue_vfp_neon, ca9fp_mul2, ca9fp_mul3, ca9fp_mul4")
 239
 240 (define_reservation "ca9fmuld"
 241   "ca9fp_mul1 + ca9_issue_vfp_neon, (ca9fp_mul1 + ca9fp_mul2), ca9fp_mul2, ca9fp_mul3, ca9fp_mul4")
 242
 243 (define_insn_reservation "cortex_a9_fmuls" 4
 244   (and (eq_attr "tune" "cortexa9")
 245        (eq_attr "type" "fmuls"))
 246   "ca9fmuls")
 247
 248 (define_insn_reservation "cortex_a9_fmuld" 5
 249   (and (eq_attr "tune" "cortexa9")
 250        (eq_attr "type" "fmuld"))
 251   "ca9fmuld")
 252
 253 (define_insn_reservation "cortex_a9_fmacs" 8
 254   (and (eq_attr "tune" "cortexa9")
 255        (eq_attr "type" "fmacs,ffmas"))
 256   "ca9fmuls, ca9fp_add")
 257
 258 (define_insn_reservation "cortex_a9_fmacd" 9
 259   (and (eq_attr "tune" "cortexa9")
 260        (eq_attr "type" "fmacd,ffmad"))
 261   "ca9fmuld, ca9fp_add")
 262
 263 ;; Division pipeline description.
 264 (define_insn_reservation "cortex_a9_fdivs" 15
 265   (and (eq_attr "tune" "cortexa9")
 266        (eq_attr "type" "fdivs"))
 267   "ca9fp_ds1 + ca9_issue_vfp_neon, nothing*14")
 268
 269 (define_insn_reservation "cortex_a9_fdivd" 25
 270   (and (eq_attr "tune" "cortexa9")
 271        (eq_attr "type" "fdivd"))
 272   "ca9fp_ds1 + ca9_issue_vfp_neon, nothing*24")
 273
 274 ;; Include Neon pipeline description
 275 (include "cortex-a9-neon.md")