gcc/config/arm/cortex-m4.md

   1 ;; ARM Cortex-M4 pipeline description
   2 ;; Copyright (C) 2010-2019 Free Software Foundation, Inc.
   3 ;; Contributed by CodeSourcery.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but
  13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 ;; General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 (define_automaton "cortex_m4")
  22
  23 ;; We model the pipelining of LDR instructions by using two artificial units.
  24
  25 (define_cpu_unit "cortex_m4_a" "cortex_m4")
  26
  27 (define_cpu_unit "cortex_m4_b" "cortex_m4")
  28
  29 (define_reservation "cortex_m4_ex" "cortex_m4_a+cortex_m4_b")
  30
  31 ;; ALU and multiply is one cycle.
  32 (define_insn_reservation "cortex_m4_alu" 1
  33   (and (eq_attr "tune" "cortexm4")
  34        (ior (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
  35                              alu_sreg,alus_sreg,logic_reg,logics_reg,\
  36                              adc_imm,adcs_imm,adc_reg,adcs_reg,\
  37                              adr,bfm,clz,rbit,rev,alu_dsp_reg,\
  38                              shift_imm,shift_reg,extend,\
  39                              alu_shift_imm,alus_shift_imm,\
  40                              logic_shift_imm,logics_shift_imm,\
  41                              alu_shift_reg,alus_shift_reg,\
  42                              logic_shift_reg,logics_shift_reg,\
  43                              mov_imm,mov_reg,mov_shift,mov_shift_reg,\
  44                              mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg,\
  45                              mrs,multiple")
  46             (ior (eq_attr "mul32" "yes")
  47                  (eq_attr "widen_mul64" "yes"))))
  48   "cortex_m4_ex")
  49
  50 ;; Byte, half-word and word load is two cycles.
  51 (define_insn_reservation "cortex_m4_load1" 2
  52   (and (eq_attr "tune" "cortexm4")
  53        (eq_attr "type" "load_byte,load_4"))
  54   "cortex_m4_a, cortex_m4_b")
  55
  56 ;; str rx, [ry, #imm] is always one cycle.
  57 (define_insn_reservation "cortex_m4_store1_1" 1
  58   (and (and (eq_attr "tune" "cortexm4")
  59             (eq_attr "type" "store_4"))
  60        (match_test "arm_address_offset_is_imm (insn)"))
  61   "cortex_m4_a")
  62
  63 ;; Other byte, half-word and word load is two cycles.
  64 (define_insn_reservation "cortex_m4_store1_2" 2
  65   (and (and (eq_attr "tune" "cortexm4")
  66             (eq_attr "type" "store_4"))
  67        (not (match_test "arm_address_offset_is_imm (insn)")))
  68   "cortex_m4_a*2")
  69
  70 (define_insn_reservation "cortex_m4_load2" 3
  71   (and (eq_attr "tune" "cortexm4")
  72        (eq_attr "type" "load_8"))
  73   "cortex_m4_ex*3")
  74
  75 (define_insn_reservation "cortex_m4_store2" 3
  76   (and (eq_attr "tune" "cortexm4")
  77        (eq_attr "type" "store_8"))
  78   "cortex_m4_ex*3")
  79
  80 (define_insn_reservation "cortex_m4_load3" 4
  81   (and (eq_attr "tune" "cortexm4")
  82        (eq_attr "type" "load_12"))
  83   "cortex_m4_ex*4")
  84
  85 (define_insn_reservation "cortex_m4_store3" 4
  86   (and (eq_attr "tune" "cortexm4")
  87        (eq_attr "type" "store_12"))
  88   "cortex_m4_ex*4")
  89
  90 (define_insn_reservation "cortex_m4_load4" 5
  91   (and (eq_attr "tune" "cortexm4")
  92        (eq_attr "type" "load_16"))
  93   "cortex_m4_ex*5")
  94
  95 (define_insn_reservation "cortex_m4_store4" 5
  96   (and (eq_attr "tune" "cortexm4")
  97        (eq_attr "type" "store_16"))
  98   "cortex_m4_ex*5")
  99
 100 (define_bypass 1 "cortex_m4_load1"
 101                  "cortex_m4_store1_1,cortex_m4_store1_2"
 102                  "arm_no_early_store_addr_dep")
 103
 104 ;; If the address of load or store depends on the result of the preceding
 105 ;; instruction, the latency is increased by one.
 106
 107 (define_bypass 2 "cortex_m4_alu"
 108                  "cortex_m4_load1"
 109                  "arm_early_load_addr_dep")
 110
 111 (define_bypass 2 "cortex_m4_alu"
 112                  "cortex_m4_store1_1,cortex_m4_store1_2"
 113                  "arm_early_store_addr_dep")
 114
 115 (define_insn_reservation "cortex_m4_branch" 3
 116   (and (eq_attr "tune" "cortexm4")
 117        (eq_attr "type" "branch"))
 118   "cortex_m4_ex*3")
 119
 120 (define_insn_reservation "cortex_m4_call" 3
 121   (and (eq_attr "tune" "cortexm4")
 122        (eq_attr "type" "call"))
 123   "cortex_m4_ex*3")
 124
 125 (define_insn_reservation "cortex_m4_block" 1
 126   (and (eq_attr "tune" "cortexm4")
 127        (eq_attr "type" "block"))
 128   "cortex_m4_ex")