gcc/config/arm/fa606te.md

   1 ;; Faraday FA606TE Pipeline Description
   2 ;; Copyright (C) 2010-2019 Free Software Foundation, Inc.
   3 ;; Written by Mingfeng Wu, based on ARM926EJ-S Pipeline Description.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it under
   8 ;; the terms of the GNU General Public License as published by the Free
   9 ;; Software Foundation; either version 3, or (at your option) any later
  10 ;; version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  13 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14 ;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  15 ;; for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.  */
  20
  21 ;; These descriptions are based on the information contained in the
  22 ;; FA606TE Core Design Note, Copyright (c) 2010 Faraday Technology Corp.
  23
  24 ;; Modeled pipeline characteristics:
  25 ;; LD -> any use: latency = 2 (1 cycle penalty).
  26 ;; ALU -> any use: latency = 1 (0 cycle penalty).
  27
  28 ;; This automaton provides a pipeline description for the Faraday
  29 ;; FA606TE core.
  30 ;;
  31 ;; The model given here assumes that the condition for all conditional
  32 ;; instructions is "true", i.e., that all of the instructions are
  33 ;; actually executed.
  34
  35 (define_automaton "fa606te")
  36
  37 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  38 ;; Pipelines
  39 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  40
  41 ;; There is a single pipeline
  42 ;;
  43 ;;   The ALU pipeline has fetch, decode, execute, memory, and
  44 ;;   write stages.  We only need to model the execute, memory and write
  45 ;;   stages.
  46
  47 ;;      E      M      W
  48
  49 (define_cpu_unit "fa606te_core" "fa606te")
  50
  51 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  52 ;; ALU Instructions
  53 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  54
  55 ;; ALU instructions require two cycles to execute, and use the ALU
  56 ;; pipeline in each of the three stages.  The results are available
  57 ;; after the execute stage has finished.
  58 ;;
  59 ;; If the destination register is the PC, the pipelines are stalled
  60 ;; for several cycles.  That case is not modeled here.
  61
  62 ;; ALU operations
  63 (define_insn_reservation "606te_alu_op" 1
  64  (and (eq_attr "tune" "fa606te")
  65       (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
  66                        alu_sreg,alus_sreg,logic_reg,logics_reg,\
  67                        adc_imm,adcs_imm,adc_reg,adcs_reg,\
  68                        adr,bfm,rev,\
  69                        shift_imm,shift_reg,extend,\
  70                        alu_shift_imm,alus_shift_imm,\
  71                        logic_shift_imm,logics_shift_imm,\
  72                        alu_shift_reg,alus_shift_reg,\
  73                        logic_shift_reg,logics_shift_reg,\
  74                        mov_imm,mov_reg,mov_shift,mov_shift_reg,\
  75                        mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg,\
  76                        mrs,multiple,no_insn"))
  77  "fa606te_core")
  78
  79 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  80 ;; Multiplication Instructions
  81 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  82
  83 (define_insn_reservation "606te_mult1" 2
  84  (and (eq_attr "tune" "fa606te")
  85       (eq_attr "type" "smlalxy"))
  86  "fa606te_core")
  87
  88 (define_insn_reservation "606te_mult2" 3
  89  (and (eq_attr "tune" "fa606te")
  90       (eq_attr "type" "smlaxy,smulxy,smulwy,smlawy"))
  91  "fa606te_core*2")
  92
  93 (define_insn_reservation "606te_mult3" 4
  94  (and (eq_attr "tune" "fa606te")
  95       (eq_attr "type" "mul,mla,muls,mlas"))
  96  "fa606te_core*3")
  97
  98 (define_insn_reservation "606te_mult4" 5
  99  (and (eq_attr "tune" "fa606te")
 100       (eq_attr "type" "umull,umlal,smull,smlal,umulls,umlals,smulls,smlals"))
 101  "fa606te_core*4")
 102
 103 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 104 ;; Load/Store Instructions
 105 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 106
 107 ;; The models for load/store instructions do not accurately describe
 108 ;; the difference between operations with a base register writeback
 109 ;; (such as "ldm!").  These models assume that all memory references
 110 ;; hit in dcache.
 111
 112 (define_insn_reservation "606te_load1_op" 2
 113  (and (eq_attr "tune" "fa606te")
 114       (eq_attr "type" "load_4,load_byte"))
 115  "fa606te_core")
 116
 117 (define_insn_reservation "606te_load2_op" 3
 118  (and (eq_attr "tune" "fa606te")
 119       (eq_attr "type" "load_8"))
 120  "fa606te_core*2")
 121
 122 (define_insn_reservation "606te_load3_op" 4
 123  (and (eq_attr "tune" "fa606te")
 124       (eq_attr "type" "load_12"))
 125  "fa606te_core*3")
 126
 127 (define_insn_reservation "606te_load4_op" 5
 128  (and (eq_attr "tune" "fa606te")
 129       (eq_attr "type" "load_16"))
 130  "fa606te_core*4")
 131
 132 (define_insn_reservation "606te_store1_op" 0
 133  (and (eq_attr "tune" "fa606te")
 134       (eq_attr "type" "store_4"))
 135  "fa606te_core")
 136
 137 (define_insn_reservation "606te_store2_op" 1
 138  (and (eq_attr "tune" "fa606te")
 139       (eq_attr "type" "store_8"))
 140  "fa606te_core*2")
 141
 142 (define_insn_reservation "606te_store3_op" 2
 143  (and (eq_attr "tune" "fa606te")
 144       (eq_attr "type" "store_12"))
 145  "fa606te_core*3")
 146
 147 (define_insn_reservation "606te_store4_op" 3
 148  (and (eq_attr "tune" "fa606te")
 149       (eq_attr "type" "store_16"))
 150  "fa606te_core*4")
 151
 152
 153 ;;(define_insn_reservation "606te_ldm_op" 9
 154 ;; (and (eq_attr "tune" "fa606te")
 155 ;;      (eq_attr "type" "load_8,load_12,load_16,store_8,store_12,store_16"))
 156 ;; "fa606te_core*7")
 157
 158 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 159 ;; Branch and Call Instructions
 160 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 161
 162 ;; Branch instructions are difficult to model accurately.  The FA606TE
 163 ;; core can predict most branches.  If the branch is predicted
 164 ;; correctly, and predicted early enough, the branch can be completely
 165 ;; eliminated from the instruction stream.  Some branches can
 166 ;; therefore appear to require zero cycles to execute.  We assume that
 167 ;; all branches are predicted correctly, and that the latency is
 168 ;; therefore the minimum value.
 169
 170 (define_insn_reservation "606te_branch_op" 0
 171  (and (eq_attr "tune" "fa606te")
 172       (eq_attr "type" "branch"))
 173  "fa606te_core")
 174
 175 ;; The latency for a call is actually the latency when the result is available.
 176 ;; i.e. R0 ready for int return value.  For most cases, the return value is set
 177 ;; by a mov instruction, which has 1 cycle latency.
 178 (define_insn_reservation "606te_call_op" 1
 179  (and (eq_attr "tune" "fa606te")
 180       (eq_attr "type" "call"))
 181  "fa606te_core")
 182