gcc/config/arm/fa626te.md

   1 ;; Faraday FA626TE Pipeline Description
   2 ;; Copyright (C) 2010-2019 Free Software Foundation, Inc.
   3 ;; Written by I-Jui Sung, based on ARM926EJ-S Pipeline Description.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it under
   8 ;; the terms of the GNU General Public License as published by the Free
   9 ;; Software Foundation; either version 3, or (at your option) any later
  10 ;; version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  13 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14 ;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  15 ;; for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.  */
  20
  21 ;; These descriptions are based on the information contained in the
  22 ;; FA626TE Core Design Note, Copyright (c) 2010 Faraday Technology Corp.
  23
  24 ;; Modeled pipeline characteristics:
  25 ;; ALU -> simple address LDR/STR: latency = 2 (available after 2 cycles).
  26 ;; ALU -> shifted address LDR/STR: latency = 3.
  27 ;;              ( extra 1 cycle unavoidable stall).
  28 ;; ALU -> other use: latency = 2 (available after 2 cycles).
  29 ;; LD  -> simple address LDR/STR: latency = 3 (available after 3 cycles).
  30 ;; LD  -> shifted address LDR/STR: latency = 4
  31 ;;              ( extra 1 cycle unavoidable stall).
  32 ;; LD  -> any other use: latency = 3 (available after 3 cycles).
  33
  34 ;; This automaton provides a pipeline description for the Faraday
  35 ;; FA626TE core.
  36 ;;
  37 ;; The model given here assumes that the condition for all conditional
  38 ;; instructions is "true", i.e., that all of the instructions are
  39 ;; actually executed.
  40
  41 (define_automaton "fa626te")
  42
  43 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  44 ;; Pipelines
  45 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  46
  47 ;; There is a single pipeline
  48 ;;
  49 ;;   The ALU pipeline has fetch, decode, execute, memory, and
  50 ;;   write stages.  We only need to model the execute, memory and write
  51 ;;   stages.
  52
  53 ;;      S      E      M      W
  54
  55 (define_cpu_unit "fa626te_core" "fa626te")
  56
  57 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  58 ;; ALU Instructions
  59 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  60
  61 ;; ALU instructions require two cycles to execute, and use the ALU
  62 ;; pipeline in each of the three stages.  The results are available
  63 ;; after the execute stage has finished.
  64 ;;
  65 ;; If the destination register is the PC, the pipelines are stalled
  66 ;; for several cycles.  That case is not modeled here.
  67
  68 ;; ALU operations
  69 (define_insn_reservation "626te_alu_op" 1
  70  (and (eq_attr "tune" "fa626,fa626te")
  71       (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
  72                        alu_sreg,alus_sreg,logic_reg,logics_reg,\
  73                        adc_imm,adcs_imm,adc_reg,adcs_reg,\
  74                        adr,bfm,rev,\
  75                        shift_imm,shift_reg,\
  76                        mov_imm,mov_reg,mvn_imm,mvn_reg,\
  77                        mrs,multiple,no_insn"))
  78  "fa626te_core")
  79
  80 (define_insn_reservation "626te_alu_shift_op" 2
  81  (and (eq_attr "tune" "fa626,fa626te")
  82       (eq_attr "type" "extend,\
  83                        alu_shift_imm,alus_shift_imm,\
  84                        logic_shift_imm,logics_shift_imm,\
  85                        alu_shift_reg,alus_shift_reg,\
  86                        logic_shift_reg,logics_shift_reg,\
  87                        mov_shift,mov_shift_reg,\
  88                        mvn_shift,mvn_shift_reg"))
  89  "fa626te_core")
  90
  91 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  92 ;; Multiplication Instructions
  93 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  94
  95 (define_insn_reservation "626te_mult1" 2
  96  (and (eq_attr "tune" "fa626,fa626te")
  97       (eq_attr "type" "smulwy,smlawy,smulxy,smlaxy"))
  98  "fa626te_core")
  99
 100 (define_insn_reservation "626te_mult2" 2
 101  (and (eq_attr "tune" "fa626,fa626te")
 102       (eq_attr "type" "mul,mla"))
 103  "fa626te_core")
 104
 105 (define_insn_reservation "626te_mult3" 3
 106  (and (eq_attr "tune" "fa626,fa626te")
 107       (eq_attr "type" "muls,mlas,smull,smlal,umull,umlal,smlalxy,smlawx"))
 108  "fa626te_core*2")
 109
 110 (define_insn_reservation "626te_mult4" 4
 111  (and (eq_attr "tune" "fa626,fa626te")
 112       (eq_attr "type" "smulls,smlals,umulls,umlals"))
 113  "fa626te_core*3")
 114
 115 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 116 ;; Load/Store Instructions
 117 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 118
 119 ;; The models for load/store instructions do not accurately describe
 120 ;; the difference between operations with a base register writeback
 121 ;; (such as "ldm!").  These models assume that all memory references
 122 ;; hit in dcache.
 123
 124 (define_insn_reservation "626te_load1_op" 3
 125  (and (eq_attr "tune" "fa626,fa626te")
 126       (eq_attr "type" "load_4,load_byte"))
 127  "fa626te_core")
 128
 129 (define_insn_reservation "626te_load2_op" 4
 130  (and (eq_attr "tune" "fa626,fa626te")
 131       (eq_attr "type" "load_8,load_12"))
 132  "fa626te_core*2")
 133
 134 (define_insn_reservation "626te_load3_op" 5
 135  (and (eq_attr "tune" "fa626,fa626te")
 136       (eq_attr "type" "load_16"))
 137  "fa626te_core*3")
 138
 139 (define_insn_reservation "626te_store1_op" 0
 140  (and (eq_attr "tune" "fa626,fa626te")
 141       (eq_attr "type" "store_4"))
 142  "fa626te_core")
 143
 144 (define_insn_reservation "626te_store2_op" 1
 145  (and (eq_attr "tune" "fa626,fa626te")
 146       (eq_attr "type" "store_8,store_12"))
 147  "fa626te_core*2")
 148
 149 (define_insn_reservation "626te_store3_op" 2
 150  (and (eq_attr "tune" "fa626,fa626te")
 151       (eq_attr "type" "store_16"))
 152  "fa626te_core*3")
 153
 154 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 155 ;; Branch and Call Instructions
 156 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 157
 158 ;; Branch instructions are difficult to model accurately.  The FA626TE
 159 ;; core can predict most branches.  If the branch is predicted
 160 ;; correctly, and predicted early enough, the branch can be completely
 161 ;; eliminated from the instruction stream.  Some branches can
 162 ;; therefore appear to require zero cycle to execute.  We assume that
 163 ;; all branches are predicted correctly, and that the latency is
 164 ;; therefore the minimum value.
 165
 166 (define_insn_reservation "626te_branch_op" 0
 167  (and (eq_attr "tune" "fa626,fa626te")
 168       (eq_attr "type" "branch"))
 169  "fa626te_core")
 170
 171 ;; The latency for a call is actually the latency when the result is available.
 172 ;; i.e. R0 ready for int return value.
 173 (define_insn_reservation "626te_call_op" 1
 174  (and (eq_attr "tune" "fa626,fa626te")
 175       (eq_attr "type" "call"))
 176  "fa626te_core")
 177