gcc/config/arm/iterators.md

   1 ;; Code and mode itertator and attribute definitions for the ARM backend
   2 ;; Copyright (C) 2010-2014 Free Software Foundation, Inc.
   3 ;; Contributed by ARM Ltd.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published
   9 ;; by the Free Software Foundation; either version 3, or (at your
  10 ;; option) any later version.
  11
  12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ;; License for more details.
  16
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21
  22 ;;----------------------------------------------------------------------------
  23 ;; Mode iterators
  24 ;;----------------------------------------------------------------------------
  25
  26 ;; A list of modes that are exactly 64 bits in size. This is used to expand
  27 ;; some splits that are the same for all modes when operating on ARM
  28 ;; registers.
  29 (define_mode_iterator ANY64 [DI DF V8QI V4HI V2SI V2SF])
  30
  31 (define_mode_iterator ANY128 [V2DI V2DF V16QI V8HI V4SI V4SF])
  32
  33 ;; A list of integer modes that are up to one word long
  34 (define_mode_iterator QHSI [QI HI SI])
  35
  36 ;; A list of integer modes that are less than a word
  37 (define_mode_iterator NARROW [QI HI])
  38
  39 ;; A list of all the integer modes up to 64bit
  40 (define_mode_iterator QHSD [QI HI SI DI])
  41
  42 ;; A list of the 32bit and 64bit integer modes
  43 (define_mode_iterator SIDI [SI DI])
  44
  45 ;; A list of modes which the VFP unit can handle
  46 (define_mode_iterator SDF [(SF "TARGET_VFP") (DF "TARGET_VFP_DOUBLE")])
  47
  48 ;; Integer element sizes implemented by IWMMXT.
  49 (define_mode_iterator VMMX [V2SI V4HI V8QI])
  50
  51 (define_mode_iterator VMMX2 [V4HI V2SI])
  52
  53 ;; Integer element sizes for shifts.
  54 (define_mode_iterator VSHFT [V4HI V2SI DI])
  55
  56 ;; Integer and float modes supported by Neon and IWMMXT.
  57 (define_mode_iterator VALL [V2DI V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF])
  58
  59 ;; Integer and float modes supported by Neon and IWMMXT, except V2DI.
  60 (define_mode_iterator VALLW [V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF])
  61
  62 ;; Integer modes supported by Neon and IWMMXT
  63 (define_mode_iterator VINT [V2DI V2SI V4HI V8QI V4SI V8HI V16QI])
  64
  65 ;; Integer modes supported by Neon and IWMMXT, except V2DI
  66 (define_mode_iterator VINTW [V2SI V4HI V8QI V4SI V8HI V16QI])
  67
  68 ;; Double-width vector modes.
  69 (define_mode_iterator VD [V8QI V4HI V2SI V2SF])
  70
  71 ;; Double-width vector modes plus 64-bit elements.
  72 (define_mode_iterator VDX [V8QI V4HI V2SI V2SF DI])
  73
  74 ;; Double-width vector modes without floating-point elements.
  75 (define_mode_iterator VDI [V8QI V4HI V2SI])
  76
  77 ;; Quad-width vector modes.
  78 (define_mode_iterator VQ [V16QI V8HI V4SI V4SF])
  79
  80 ;; Quad-width vector modes plus 64-bit elements.
  81 (define_mode_iterator VQX [V16QI V8HI V4SI V4SF V2DI])
  82
  83 ;; Quad-width vector modes without floating-point elements.
  84 (define_mode_iterator VQI [V16QI V8HI V4SI])
  85
  86 ;; Quad-width vector modes, with TImode added, for moves.
  87 (define_mode_iterator VQXMOV [V16QI V8HI V4SI V4SF V2DI TI])
  88
  89 ;; Opaque structure types wider than TImode.
  90 (define_mode_iterator VSTRUCT [EI OI CI XI])
  91
  92 ;; Opaque structure types used in table lookups (except vtbl1/vtbx1).
  93 (define_mode_iterator VTAB [TI EI OI])
  94
  95 ;; Widenable modes.
  96 (define_mode_iterator VW [V8QI V4HI V2SI])
  97
  98 ;; Narrowable modes.
  99 (define_mode_iterator VN [V8HI V4SI V2DI])
 100
 101 ;; All supported vector modes (except singleton DImode).
 102 (define_mode_iterator VDQ [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DI])
 103
 104 ;; All supported vector modes (except those with 64-bit integer elements).
 105 (define_mode_iterator VDQW [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF])
 106
 107 ;; Supported integer vector modes (not 64 bit elements).
 108 (define_mode_iterator VDQIW [V8QI V16QI V4HI V8HI V2SI V4SI])
 109
 110 ;; Supported integer vector modes (not singleton DI)
 111 (define_mode_iterator VDQI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
 112
 113 ;; Vector modes, including 64-bit integer elements.
 114 (define_mode_iterator VDQX [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF DI V2DI])
 115
 116 ;; Vector modes including 64-bit integer elements, but no floats.
 117 (define_mode_iterator VDQIX [V8QI V16QI V4HI V8HI V2SI V4SI DI V2DI])
 118
 119 ;; Vector modes for float->int conversions.
 120 (define_mode_iterator VCVTF [V2SF V4SF])
 121
 122 ;; Vector modes form int->float conversions.
 123 (define_mode_iterator VCVTI [V2SI V4SI])
 124
 125 ;; Vector modes for doubleword multiply-accumulate, etc. insns.
 126 (define_mode_iterator VMD [V4HI V2SI V2SF])
 127
 128 ;; Vector modes for quadword multiply-accumulate, etc. insns.
 129 (define_mode_iterator VMQ [V8HI V4SI V4SF])
 130
 131 ;; Above modes combined.
 132 (define_mode_iterator VMDQ [V4HI V2SI V2SF V8HI V4SI V4SF])
 133
 134 ;; As VMD, but integer modes only.
 135 (define_mode_iterator VMDI [V4HI V2SI])
 136
 137 ;; As VMQ, but integer modes only.
 138 (define_mode_iterator VMQI [V8HI V4SI])
 139
 140 ;; Above modes combined.
 141 (define_mode_iterator VMDQI [V4HI V2SI V8HI V4SI])
 142
 143 ;; Modes with 8-bit and 16-bit elements.
 144 (define_mode_iterator VX [V8QI V4HI V16QI V8HI])
 145
 146 ;; Modes with 8-bit elements.
 147 (define_mode_iterator VE [V8QI V16QI])
 148
 149 ;; Modes with 64-bit elements only.
 150 (define_mode_iterator V64 [DI V2DI])
 151
 152 ;; Modes with 32-bit elements only.
 153 (define_mode_iterator V32 [V2SI V2SF V4SI V4SF])
 154
 155 ;; Modes with 8-bit, 16-bit and 32-bit elements.
 156 (define_mode_iterator VU [V16QI V8HI V4SI])
 157
 158 ;; Iterators used for fixed-point support.
 159 (define_mode_iterator FIXED [QQ HQ SQ UQQ UHQ USQ HA SA UHA USA])
 160
 161 (define_mode_iterator ADDSUB [V4QQ V2HQ V2HA])
 162
 163 (define_mode_iterator UQADDSUB [V4UQQ V2UHQ UQQ UHQ V2UHA UHA])
 164
 165 (define_mode_iterator QADDSUB [V4QQ V2HQ QQ HQ V2HA HA SQ SA])
 166
 167 (define_mode_iterator QMUL [HQ HA])
 168
 169 ;;----------------------------------------------------------------------------
 170 ;; Code iterators
 171 ;;----------------------------------------------------------------------------
 172
 173 ;; A list of condition codes used in compare instructions where
 174 ;; the carry flag from the addition is used instead of doing the
 175 ;; compare a second time.
 176 (define_code_iterator LTUGEU [ltu geu])
 177
 178 ;; A list of ...
 179 (define_code_iterator ior_xor [ior xor])
 180
 181 ;; Operations on two halves of a quadword vector.
 182 (define_code_iterator vqh_ops [plus smin smax umin umax])
 183
 184 ;; Operations on two halves of a quadword vector,
 185 ;; without unsigned variants (for use with *SFmode pattern).
 186 (define_code_iterator vqhs_ops [plus smin smax])
 187
 188 ;; A list of widening operators
 189 (define_code_iterator SE [sign_extend zero_extend])
 190
 191 ;; Right shifts
 192 (define_code_iterator rshifts [ashiftrt lshiftrt])
 193
 194 ;;----------------------------------------------------------------------------
 195 ;; Int iterators
 196 ;;----------------------------------------------------------------------------
 197
 198 (define_int_iterator VRINT [UNSPEC_VRINTZ UNSPEC_VRINTP UNSPEC_VRINTM
 199                             UNSPEC_VRINTR UNSPEC_VRINTX UNSPEC_VRINTA])
 200
 201 (define_int_iterator NEON_VRINT [UNSPEC_NVRINTP UNSPEC_NVRINTZ UNSPEC_NVRINTM
 202                               UNSPEC_NVRINTX UNSPEC_NVRINTA UNSPEC_NVRINTN])
 203
 204 (define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W
 205                           UNSPEC_CRC32CB UNSPEC_CRC32CH UNSPEC_CRC32CW])
 206
 207 (define_int_iterator CRYPTO_UNARY [UNSPEC_AESMC UNSPEC_AESIMC])
 208
 209 (define_int_iterator CRYPTO_BINARY [UNSPEC_AESD UNSPEC_AESE
 210                                     UNSPEC_SHA1SU1 UNSPEC_SHA256SU0])
 211
 212 (define_int_iterator CRYPTO_TERNARY [UNSPEC_SHA1SU0 UNSPEC_SHA256H
 213                                      UNSPEC_SHA256H2 UNSPEC_SHA256SU1])
 214
 215 (define_int_iterator CRYPTO_SELECTING [UNSPEC_SHA1C UNSPEC_SHA1M
 216                                        UNSPEC_SHA1P])
 217
 218 ;;----------------------------------------------------------------------------
 219 ;; Mode attributes
 220 ;;----------------------------------------------------------------------------
 221
 222 ;; Determine element size suffix from vector mode.
 223 (define_mode_attr MMX_char [(V8QI "b") (V4HI "h") (V2SI "w") (DI "d")])
 224
 225 ;; vtbl<n> suffix for NEON vector modes.
 226 (define_mode_attr VTAB_n [(TI "2") (EI "3") (OI "4")])
 227
 228 ;; (Opposite) mode to convert to/from for NEON mode conversions.
 229 (define_mode_attr V_CVTTO [(V2SI "V2SF") (V2SF "V2SI")
 230                (V4SI "V4SF") (V4SF "V4SI")])
 231
 232 ;; As above but in lower case.
 233 (define_mode_attr V_cvtto [(V2SI "v2sf") (V2SF "v2si")
 234                            (V4SI "v4sf") (V4SF "v4si")])
 235
 236 ;; Define element mode for each vector mode.
 237 (define_mode_attr V_elem [(V8QI "QI") (V16QI "QI")
 238               (V4HI "HI") (V8HI "HI")
 239                           (V2SI "SI") (V4SI "SI")
 240                           (V2SF "SF") (V4SF "SF")
 241                           (DI "DI")   (V2DI "DI")])
 242
 243 ;; Element modes for vector extraction, padded up to register size.
 244
 245 (define_mode_attr V_ext [(V8QI "SI") (V16QI "SI")
 246              (V4HI "SI") (V8HI "SI")
 247              (V2SI "SI") (V4SI "SI")
 248              (V2SF "SF") (V4SF "SF")
 249              (DI "DI") (V2DI "DI")])
 250
 251 ;; Mode of pair of elements for each vector mode, to define transfer
 252 ;; size for structure lane/dup loads and stores.
 253 (define_mode_attr V_two_elem [(V8QI "HI")   (V16QI "HI")
 254                               (V4HI "SI")   (V8HI "SI")
 255                               (V2SI "V2SI") (V4SI "V2SI")
 256                               (V2SF "V2SF") (V4SF "V2SF")
 257                               (DI "V2DI")   (V2DI "V2DI")])
 258
 259 ;; Similar, for three elements.
 260 (define_mode_attr V_three_elem [(V8QI "BLK") (V16QI "BLK")
 261                                 (V4HI "BLK") (V8HI "BLK")
 262                                 (V2SI "BLK") (V4SI "BLK")
 263                                 (V2SF "BLK") (V4SF "BLK")
 264                                 (DI "EI")    (V2DI "EI")])
 265
 266 ;; Similar, for four elements.
 267 (define_mode_attr V_four_elem [(V8QI "SI")   (V16QI "SI")
 268                                (V4HI "V4HI") (V8HI "V4HI")
 269                                (V2SI "V4SI") (V4SI "V4SI")
 270                                (V2SF "V4SF") (V4SF "V4SF")
 271                                (DI "OI")     (V2DI "OI")])
 272
 273 ;; Register width from element mode
 274 (define_mode_attr V_reg [(V8QI "P") (V16QI "q")
 275                          (V4HI "P") (V8HI  "q")
 276                          (V2SI "P") (V4SI  "q")
 277                          (V2SF "P") (V4SF  "q")
 278                          (DI   "P") (V2DI  "q")
 279                          (SF   "")  (DF    "P")])
 280
 281 ;; Wider modes with the same number of elements.
 282 (define_mode_attr V_widen [(V8QI "V8HI") (V4HI "V4SI") (V2SI "V2DI")])
 283
 284 ;; Narrower modes with the same number of elements.
 285 (define_mode_attr V_narrow [(V8HI "V8QI") (V4SI "V4HI") (V2DI "V2SI")])
 286
 287 ;; Narrower modes with double the number of elements.
 288 (define_mode_attr V_narrow_pack [(V4SI "V8HI") (V8HI "V16QI") (V2DI "V4SI")
 289                                  (V4HI "V8QI") (V2SI "V4HI")  (DI "V2SI")])
 290
 291 ;; Modes with half the number of equal-sized elements.
 292 (define_mode_attr V_HALF [(V16QI "V8QI") (V8HI "V4HI")
 293               (V4SI  "V2SI") (V4SF "V2SF") (V2DF "DF")
 294                           (V2DI "DI")])
 295
 296 ;; Same, but lower-case.
 297 (define_mode_attr V_half [(V16QI "v8qi") (V8HI "v4hi")
 298               (V4SI  "v2si") (V4SF "v2sf")
 299                           (V2DI "di")])
 300
 301 ;; Modes with twice the number of equal-sized elements.
 302 (define_mode_attr V_DOUBLE [(V8QI "V16QI") (V4HI "V8HI")
 303                 (V2SI "V4SI") (V2SF "V4SF") (DF "V2DF")
 304                             (DI "V2DI")])
 305
 306 ;; Same, but lower-case.
 307 (define_mode_attr V_double [(V8QI "v16qi") (V4HI "v8hi")
 308                 (V2SI "v4si") (V2SF "v4sf")
 309                             (DI "v2di")])
 310
 311 ;; Modes with double-width elements.
 312 (define_mode_attr V_double_width [(V8QI "V4HI") (V16QI "V8HI")
 313                   (V4HI "V2SI") (V8HI "V4SI")
 314                   (V2SI "DI")   (V4SI "V2DI")])
 315
 316 ;; Double-sized modes with the same element size.
 317 ;; Used for neon_vdup_lane, where the second operand is double-sized
 318 ;; even when the first one is quad.
 319 (define_mode_attr V_double_vector_mode [(V16QI "V8QI") (V8HI "V4HI")
 320                                         (V4SI "V2SI") (V4SF "V2SF")
 321                                         (V8QI "V8QI") (V4HI "V4HI")
 322                                         (V2SI "V2SI") (V2SF "V2SF")])
 323
 324 ;; Mode of result of comparison operations (and bit-select operand 1).
 325 (define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI")
 326                     (V4HI "V4HI") (V8HI  "V8HI")
 327                                 (V2SI "V2SI") (V4SI  "V4SI")
 328                                 (V2SF "V2SI") (V4SF  "V4SI")
 329                                 (DI   "DI")   (V2DI  "V2DI")])
 330
 331 (define_mode_attr v_cmp_result [(V8QI "v8qi") (V16QI "v16qi")
 332                                 (V4HI "v4hi") (V8HI  "v8hi")
 333                                 (V2SI "v2si") (V4SI  "v4si")
 334                                 (DI   "di")   (V2DI  "v2di")
 335                                 (V2SF "v2si") (V4SF  "v4si")])
 336
 337 ;; Get element type from double-width mode, for operations where we
 338 ;; don't care about signedness.
 339 (define_mode_attr V_if_elem [(V8QI "i8")  (V16QI "i8")
 340                  (V4HI "i16") (V8HI  "i16")
 341                              (V2SI "i32") (V4SI  "i32")
 342                              (DI   "i64") (V2DI  "i64")
 343                  (V2SF "f32") (V4SF  "f32")
 344                  (SF "f32") (DF "f64")])
 345
 346 ;; Same, but for operations which work on signed values.
 347 (define_mode_attr V_s_elem [(V8QI "s8")  (V16QI "s8")
 348                 (V4HI "s16") (V8HI  "s16")
 349                             (V2SI "s32") (V4SI  "s32")
 350                             (DI   "s64") (V2DI  "s64")
 351                 (V2SF "f32") (V4SF  "f32")])
 352
 353 ;; Same, but for operations which work on unsigned values.
 354 (define_mode_attr V_u_elem [(V8QI "u8")  (V16QI "u8")
 355                 (V4HI "u16") (V8HI  "u16")
 356                             (V2SI "u32") (V4SI  "u32")
 357                             (DI   "u64") (V2DI  "u64")
 358                             (V2SF "f32") (V4SF  "f32")])
 359
 360 ;; Element types for extraction of unsigned scalars.
 361 (define_mode_attr V_uf_sclr [(V8QI "u8")  (V16QI "u8")
 362                  (V4HI "u16") (V8HI "u16")
 363                              (V2SI "32") (V4SI "32")
 364                              (V2SF "32") (V4SF "32")])
 365
 366 (define_mode_attr V_sz_elem [(V8QI "8")  (V16QI "8")
 367                  (V4HI "16") (V8HI  "16")
 368                              (V2SI "32") (V4SI  "32")
 369                              (DI   "64") (V2DI  "64")
 370                  (V2SF "32") (V4SF  "32")])
 371
 372 (define_mode_attr V_elem_ch [(V8QI "b")  (V16QI "b")
 373                              (V4HI "h") (V8HI  "h")
 374                              (V2SI "s") (V4SI  "s")
 375                              (DI   "d") (V2DI  "d")
 376                              (V2SF "s") (V4SF  "s")])
 377
 378 ;; Element sizes for duplicating ARM registers to all elements of a vector.
 379 (define_mode_attr VD_dup [(V8QI "8") (V4HI "16") (V2SI "32") (V2SF "32")])
 380
 381 ;; Opaque integer types for results of pair-forming intrinsics (vtrn, etc.)
 382 (define_mode_attr V_PAIR [(V8QI "TI") (V16QI "OI")
 383               (V4HI "TI") (V8HI  "OI")
 384                           (V2SI "TI") (V4SI  "OI")
 385                           (V2SF "TI") (V4SF  "OI")
 386                           (DI   "TI") (V2DI  "OI")])
 387
 388 ;; Same, but lower-case.
 389 (define_mode_attr V_pair [(V8QI "ti") (V16QI "oi")
 390               (V4HI "ti") (V8HI  "oi")
 391                           (V2SI "ti") (V4SI  "oi")
 392                           (V2SF "ti") (V4SF  "oi")
 393                           (DI   "ti") (V2DI  "oi")])
 394
 395 ;; Extra suffix on some 64-bit insn names (to avoid collision with standard
 396 ;; names which we don't want to define).
 397 (define_mode_attr V_suf64 [(V8QI "") (V16QI "")
 398                            (V4HI "") (V8HI "")
 399                            (V2SI "") (V4SI "")
 400                            (V2SF "") (V4SF "")
 401                            (DI "_neon") (V2DI "")])
 402
 403
 404 ;; Scalars to be presented to scalar multiplication instructions
 405 ;; must satisfy the following constraints.
 406 ;; 1. If the mode specifies 16-bit elements, the scalar must be in D0-D7.
 407 ;; 2. If the mode specifies 32-bit elements, the scalar must be in D0-D15.
 408
 409 ;; This mode attribute is used to obtain the correct register constraints.
 410
 411 (define_mode_attr scalar_mul_constraint [(V4HI "x") (V2SI "t") (V2SF "t")
 412                                          (V8HI "x") (V4SI "t") (V4SF "t")])
 413
 414 ;; Predicates used for setting type for neon instructions
 415
 416 (define_mode_attr Is_float_mode [(V8QI "false") (V16QI "false")
 417                  (V4HI "false") (V8HI "false")
 418                  (V2SI "false") (V4SI "false")
 419                  (V2SF "true") (V4SF "true")
 420                  (DI "false") (V2DI "false")])
 421
 422 (define_mode_attr Scalar_mul_8_16 [(V8QI "true") (V16QI "true")
 423                    (V4HI "true") (V8HI "true")
 424                    (V2SI "false") (V4SI "false")
 425                    (V2SF "false") (V4SF "false")
 426                    (DI "false") (V2DI "false")])
 427
 428
 429 (define_mode_attr Is_d_reg [(V8QI "true") (V16QI "false")
 430                             (V4HI "true") (V8HI  "false")
 431                             (V2SI "true") (V4SI  "false")
 432                             (V2SF "true") (V4SF  "false")
 433                             (DI   "true") (V2DI  "false")])
 434
 435 (define_mode_attr V_mode_nunits [(V8QI "8") (V16QI "16")
 436                                  (V4HI "4") (V8HI "8")
 437                                  (V2SI "2") (V4SI "4")
 438                                  (V2SF "2") (V4SF "4")
 439                                  (DI "1")   (V2DI "2")
 440                                  (DF "1")   (V2DF "2")])
 441
 442 ;; Same as V_widen, but lower-case.
 443 (define_mode_attr V_widen_l [(V8QI "v8hi") (V4HI "v4si") ( V2SI "v2di")])
 444
 445 ;; Widen. Result is half the number of elements, but widened to double-width.
 446 (define_mode_attr V_unpack   [(V16QI "V8HI") (V8HI "V4SI") (V4SI "V2DI")])
 447
 448 ;; Conditions to be used in extend<mode>di patterns.
 449 (define_mode_attr qhs_zextenddi_cond [(SI "") (HI "&& arm_arch6") (QI "")])
 450 (define_mode_attr qhs_sextenddi_cond [(SI "") (HI "&& arm_arch6")
 451                                       (QI "&& arm_arch6")])
 452 (define_mode_attr qhs_zextenddi_op [(SI "s_register_operand")
 453                                    (HI "nonimmediate_operand")
 454                                    (QI "nonimmediate_operand")])
 455 (define_mode_attr qhs_extenddi_op [(SI "s_register_operand")
 456                                    (HI "nonimmediate_operand")
 457                                    (QI "arm_reg_or_extendqisi_mem_op")])
 458 (define_mode_attr qhs_extenddi_cstr [(SI "r,0,r,r,r") (HI "r,0,rm,rm,r") (QI "r,0,rUq,rm,r")])
 459 (define_mode_attr qhs_zextenddi_cstr [(SI "r,0,r,r") (HI "r,0,rm,r") (QI "r,0,rm,r")])
 460
 461 ;; Mode attributes used for fixed-point support.
 462 (define_mode_attr qaddsub_suf [(V4UQQ "8") (V2UHQ "16") (UQQ "8") (UHQ "16")
 463                                (V2UHA "16") (UHA "16")
 464                                (V4QQ "8") (V2HQ "16") (QQ "8") (HQ "16")
 465                                (V2HA "16") (HA "16") (SQ "") (SA "")])
 466
 467 ;; Mode attribute for vshll.
 468 (define_mode_attr V_innermode [(V8QI "QI") (V4HI "HI") (V2SI "SI")])
 469
 470 ;; Mode attributes used for VFP support.
 471 (define_mode_attr F_constraint [(SF "t") (DF "w")])
 472 (define_mode_attr vfp_type [(SF "s") (DF "d")])
 473 (define_mode_attr vfp_double_cond [(SF "") (DF "&& TARGET_VFP_DOUBLE")])
 474
 475 ;; Mode attribute used to build the "type" attribute.
 476 (define_mode_attr q [(V8QI "") (V16QI "_q")
 477                      (V4HI "") (V8HI "_q")
 478                      (V2SI "") (V4SI "_q")
 479                      (V2SF "") (V4SF "_q")
 480                      (DI "")   (V2DI "_q")
 481                      (DF "")   (V2DF "_q")])
 482
 483 ;;----------------------------------------------------------------------------
 484 ;; Code attributes
 485 ;;----------------------------------------------------------------------------
 486
 487 ;; Assembler mnemonics for vqh_ops and vqhs_ops iterators.
 488 (define_code_attr VQH_mnem [(plus "vadd") (smin "vmin") (smax "vmax")
 489                 (umin "vmin") (umax "vmax")])
 490
 491 ;; Type attributes for vqh_ops and vqhs_ops iterators.
 492 (define_code_attr VQH_type [(plus "add") (smin "minmax") (smax "minmax")
 493                 (umin "minmax") (umax "minmax")])
 494
 495 ;; Signs of above, where relevant.
 496 (define_code_attr VQH_sign [(plus "i") (smin "s") (smax "s") (umin "u")
 497                 (umax "u")])
 498
 499 (define_code_attr cnb [(ltu "CC_C") (geu "CC")])
 500 (define_code_attr optab [(ltu "ltu") (geu "geu")])
 501
 502 ;; Assembler mnemonics for signedness of widening operations.
 503 (define_code_attr US [(sign_extend "s") (zero_extend "u")])
 504
 505 ;; Right shifts
 506 (define_code_attr shift [(ashiftrt "ashr") (lshiftrt "lshr")])
 507 (define_code_attr shifttype [(ashiftrt "signed") (lshiftrt "unsigned")])
 508
 509 ;;----------------------------------------------------------------------------
 510 ;; Int attributes
 511 ;;----------------------------------------------------------------------------
 512
 513 ;; Standard names for floating point to integral rounding instructions.
 514 (define_int_attr vrint_pattern [(UNSPEC_VRINTZ "btrunc") (UNSPEC_VRINTP "ceil")
 515                          (UNSPEC_VRINTA "round") (UNSPEC_VRINTM "floor")
 516                          (UNSPEC_VRINTR "nearbyint") (UNSPEC_VRINTX "rint")])
 517
 518 ;; Suffixes for vrint instructions specifying rounding modes.
 519 (define_int_attr vrint_variant [(UNSPEC_VRINTZ "z") (UNSPEC_VRINTP "p")
 520                                (UNSPEC_VRINTA "a") (UNSPEC_VRINTM "m")
 521                                (UNSPEC_VRINTR "r") (UNSPEC_VRINTX "x")])
 522
 523 ;; Some of the vrint instuctions are predicable.
 524 (define_int_attr vrint_predicable [(UNSPEC_VRINTZ "yes") (UNSPEC_VRINTP "no")
 525                                   (UNSPEC_VRINTA "no") (UNSPEC_VRINTM "no")
 526                                   (UNSPEC_VRINTR "yes") (UNSPEC_VRINTX "yes")])
 527
 528 (define_int_attr vrint_conds [(UNSPEC_VRINTZ "nocond") (UNSPEC_VRINTP "unconditional")
 529                               (UNSPEC_VRINTA "unconditional") (UNSPEC_VRINTM "unconditional")
 530                               (UNSPEC_VRINTR "nocond") (UNSPEC_VRINTX "nocond")])
 531
 532 (define_int_attr nvrint_variant [(UNSPEC_NVRINTZ "z") (UNSPEC_NVRINTP "p")
 533                                 (UNSPEC_NVRINTA "a") (UNSPEC_NVRINTM "m")
 534                                 (UNSPEC_NVRINTX "x") (UNSPEC_NVRINTN "n")])
 535
 536 (define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h")
 537                         (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32CB "crc32cb")
 538                         (UNSPEC_CRC32CH "crc32ch") (UNSPEC_CRC32CW "crc32cw")])
 539
 540 (define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI")
 541                         (UNSPEC_CRC32W "SI") (UNSPEC_CRC32CB "QI")
 542                         (UNSPEC_CRC32CH "HI") (UNSPEC_CRC32CW "SI")])
 543
 544 (define_int_attr crypto_pattern [(UNSPEC_SHA1H "sha1h") (UNSPEC_AESMC "aesmc")
 545                           (UNSPEC_AESIMC "aesimc") (UNSPEC_AESD "aesd")
 546                           (UNSPEC_AESE "aese") (UNSPEC_SHA1SU1 "sha1su1")
 547                           (UNSPEC_SHA256SU0 "sha256su0") (UNSPEC_SHA1C "sha1c")
 548                           (UNSPEC_SHA1M "sha1m") (UNSPEC_SHA1P "sha1p")
 549                           (UNSPEC_SHA1SU0 "sha1su0") (UNSPEC_SHA256H "sha256h")
 550                           (UNSPEC_SHA256H2 "sha256h2")
 551                           (UNSPEC_SHA256SU1 "sha256su1")])
 552
 553 (define_int_attr crypto_type
 554  [(UNSPEC_AESE "crypto_aes") (UNSPEC_AESD "crypto_aes")
 555  (UNSPEC_AESMC "crypto_aes") (UNSPEC_AESIMC "crypto_aes")
 556  (UNSPEC_SHA1C "crypto_sha1_slow") (UNSPEC_SHA1P "crypto_sha1_slow")
 557  (UNSPEC_SHA1M "crypto_sha1_slow") (UNSPEC_SHA1SU1 "crypto_sha1_fast")
 558  (UNSPEC_SHA1SU0 "crypto_sha1_xor") (UNSPEC_SHA256H "crypto_sha256_slow")
 559  (UNSPEC_SHA256H2 "crypto_sha256_slow") (UNSPEC_SHA256SU0 "crypto_sha256_fast")
 560  (UNSPEC_SHA256SU1 "crypto_sha256_slow")])
 561
 562 (define_int_attr crypto_size_sfx [(UNSPEC_SHA1H "32") (UNSPEC_AESMC "8")
 563                           (UNSPEC_AESIMC "8") (UNSPEC_AESD "8")
 564                           (UNSPEC_AESE "8") (UNSPEC_SHA1SU1 "32")
 565                           (UNSPEC_SHA256SU0 "32") (UNSPEC_SHA1C "32")
 566                           (UNSPEC_SHA1M "32") (UNSPEC_SHA1P "32")
 567                           (UNSPEC_SHA1SU0 "32") (UNSPEC_SHA256H "32")
 568                           (UNSPEC_SHA256H2 "32") (UNSPEC_SHA256SU1 "32")])
 569
 570 (define_int_attr crypto_mode [(UNSPEC_SHA1H "V4SI") (UNSPEC_AESMC "V16QI")
 571                           (UNSPEC_AESIMC "V16QI") (UNSPEC_AESD "V16QI")
 572                           (UNSPEC_AESE "V16QI") (UNSPEC_SHA1SU1 "V4SI")
 573                           (UNSPEC_SHA256SU0 "V4SI") (UNSPEC_SHA1C "V4SI")
 574                           (UNSPEC_SHA1M "V4SI") (UNSPEC_SHA1P "V4SI")
 575                           (UNSPEC_SHA1SU0 "V4SI") (UNSPEC_SHA256H "V4SI")
 576                           (UNSPEC_SHA256H2 "V4SI") (UNSPEC_SHA256SU1 "V4SI")])
 577
 578 ;; Both kinds of return insn.
 579 (define_code_iterator returns [return simple_return])
 580 (define_code_attr return_str [(return "") (simple_return "simple_")])
 581 (define_code_attr return_simple_p [(return "false") (simple_return "true")])
 582 (define_code_attr return_cond_false [(return " && USE_RETURN_INSN (FALSE)")
 583                                (simple_return " && use_simple_return_p ()")])
 584 (define_code_attr return_cond_true [(return " && USE_RETURN_INSN (TRUE)")
 585                                (simple_return " && use_simple_return_p ()")])