gcc/config/arm/iwmmxt.md

   1 ;; Patterns for the Intel Wireless MMX technology architecture.
   2 ;; Copyright (C) 2003-2013 Free Software Foundation, Inc.
   3 ;; Contributed by Red Hat.
   4
   5 ;; This file is part of GCC.
   6
   7 ;; GCC is free software; you can redistribute it and/or modify it under
   8 ;; the terms of the GNU General Public License as published by the Free
   9 ;; Software Foundation; either version 3, or (at your option) any later
  10 ;; version.
  11
  12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ;; License for more details.
  16
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 ;; Register numbers
  22 (define_constants
  23   [(WCGR0           43)
  24    (WCGR1           44)
  25    (WCGR2           45)
  26    (WCGR3           46)
  27   ]
  28 )
  29
  30 (define_insn "tbcstv8qi"
  31   [(set (match_operand:V8QI                   0 "register_operand" "=y")
  32         (vec_duplicate:V8QI (match_operand:QI 1 "s_register_operand" "r")))]
  33   "TARGET_REALLY_IWMMXT"
  34   "tbcstb%?\\t%0, %1"
  35   [(set_attr "predicable" "yes")
  36    (set_attr "wtype" "tbcst")]
  37 )
  38
  39 (define_insn "tbcstv4hi"
  40   [(set (match_operand:V4HI                   0 "register_operand" "=y")
  41         (vec_duplicate:V4HI (match_operand:HI 1 "s_register_operand" "r")))]
  42   "TARGET_REALLY_IWMMXT"
  43   "tbcsth%?\\t%0, %1"
  44   [(set_attr "predicable" "yes")
  45    (set_attr "wtype" "tbcst")]
  46 )
  47
  48 (define_insn "tbcstv2si"
  49   [(set (match_operand:V2SI                   0 "register_operand" "=y")
  50         (vec_duplicate:V2SI (match_operand:SI 1 "s_register_operand" "r")))]
  51   "TARGET_REALLY_IWMMXT"
  52   "tbcstw%?\\t%0, %1"
  53   [(set_attr "predicable" "yes")
  54    (set_attr "wtype" "tbcst")]
  55 )
  56
  57 (define_insn "iwmmxt_iordi3"
  58   [(set (match_operand:DI         0 "register_operand" "=y,?&r,?&r")
  59         (ior:DI (match_operand:DI 1 "register_operand" "%y,0,r")
  60                 (match_operand:DI 2 "register_operand"  "y,r,r")))]
  61   "TARGET_REALLY_IWMMXT"
  62   "@
  63    wor%?\\t%0, %1, %2
  64    #
  65    #"
  66   [(set_attr "predicable" "yes")
  67    (set_attr "length" "4,8,8")
  68    (set_attr "wtype" "wor,none,none")]
  69 )
  70
  71 (define_insn "iwmmxt_xordi3"
  72   [(set (match_operand:DI         0 "register_operand" "=y,?&r,?&r")
  73         (xor:DI (match_operand:DI 1 "register_operand" "%y,0,r")
  74                 (match_operand:DI 2 "register_operand"  "y,r,r")))]
  75   "TARGET_REALLY_IWMMXT"
  76   "@
  77    wxor%?\\t%0, %1, %2
  78    #
  79    #"
  80   [(set_attr "predicable" "yes")
  81    (set_attr "length" "4,8,8")
  82    (set_attr "wtype" "wxor,none,none")]
  83 )
  84
  85 (define_insn "iwmmxt_anddi3"
  86   [(set (match_operand:DI         0 "register_operand" "=y,?&r,?&r")
  87         (and:DI (match_operand:DI 1 "register_operand" "%y,0,r")
  88                 (match_operand:DI 2 "register_operand"  "y,r,r")))]
  89   "TARGET_REALLY_IWMMXT"
  90   "@
  91    wand%?\\t%0, %1, %2
  92    #
  93    #"
  94   [(set_attr "predicable" "yes")
  95    (set_attr "length" "4,8,8")
  96    (set_attr "wtype" "wand,none,none")]
  97 )
  98
  99 (define_insn "iwmmxt_nanddi3"
 100   [(set (match_operand:DI                 0 "register_operand" "=y")
 101         (and:DI (match_operand:DI         1 "register_operand"  "y")
 102                 (not:DI (match_operand:DI 2 "register_operand"  "y"))))]
 103   "TARGET_REALLY_IWMMXT"
 104   "wandn%?\\t%0, %1, %2"
 105   [(set_attr "predicable" "yes")
 106    (set_attr "wtype" "wandn")]
 107 )
 108
 109 (define_insn "*iwmmxt_arm_movdi"
 110   [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, r, m,y,y,yr,y,yrUy,*w, r,*w,*w, *Uv")
 111         (match_operand:DI 1 "di_operand"              "rDa,Db,Dc,mi,r,y,yr,y,yrUy,y, r,*w,*w,*Uvi,*w"))]
 112   "TARGET_REALLY_IWMMXT
 113    && (   register_operand (operands[0], DImode)
 114        || register_operand (operands[1], DImode))"
 115   "*
 116   switch (which_alternative)
 117     {
 118     case 0:
 119     case 1:
 120     case 2:
 121       return \"#\";
 122     case 3: case 4:
 123       return output_move_double (operands, true, NULL);
 124     case 5:
 125       return \"wmov%?\\t%0,%1\";
 126     case 6:
 127       return \"tmcrr%?\\t%0,%Q1,%R1\";
 128     case 7:
 129       return \"tmrrc%?\\t%Q0,%R0,%1\";
 130     case 8:
 131       return \"wldrd%?\\t%0,%1\";
 132     case 9:
 133       return \"wstrd%?\\t%1,%0\";
 134     case 10:
 135       return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
 136     case 11:
 137       return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
 138     case 12:
 139       if (TARGET_VFP_SINGLE)
 140         return \"fcpys%?\\t%0, %1\\t%@ int\;fcpys%?\\t%p0, %p1\\t%@ int\";
 141       else
 142         return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
 143     case 13: case 14:
 144       return output_move_vfp (operands);
 145     default:
 146       gcc_unreachable ();
 147     }
 148   "
 149   [(set (attr "length") (cond [(eq_attr "alternative" "0,3,4") (const_int 8)
 150                               (eq_attr "alternative" "1") (const_int 12)
 151                               (eq_attr "alternative" "2") (const_int 16)
 152                               (eq_attr "alternative" "12")
 153                                (if_then_else
 154                                  (eq (symbol_ref "TARGET_VFP_SINGLE") (const_int 1))
 155                                  (const_int 8)
 156                                  (const_int 4))]
 157                               (const_int 4)))
 158    (set_attr "type" "*,*,*,load2,store2,*,*,*,*,*,r_2_f,f_2_r,ffarithd,f_loadd,f_stored")
 159    (set_attr "arm_pool_range" "*,*,*,1020,*,*,*,*,*,*,*,*,*,1020,*")
 160    (set_attr "arm_neg_pool_range" "*,*,*,1008,*,*,*,*,*,*,*,*,*,1008,*")
 161    (set_attr "wtype" "*,*,*,*,*,wmov,tmcrr,tmrrc,wldr,wstr,*,*,*,*,*")]
 162 )
 163
 164 (define_insn "*iwmmxt_movsi_insn"
 165   [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk, m,z,r,?z,?Uy,*t, r,*t,*t  ,*Uv")
 166         (match_operand:SI 1 "general_operand"      " rk,I,K,j,mi,rk,r,z,Uy,  z, r,*t,*t,*Uvi, *t"))]
 167   "TARGET_REALLY_IWMMXT
 168    && (   register_operand (operands[0], SImode)
 169        || register_operand (operands[1], SImode))"
 170   "*
 171    switch (which_alternative)
 172      {
 173      case 0: return \"mov\\t%0, %1\";
 174      case 1: return \"mov\\t%0, %1\";
 175      case 2: return \"mvn\\t%0, #%B1\";
 176      case 3: return \"movw\\t%0, %1\";
 177      case 4: return \"ldr\\t%0, %1\";
 178      case 5: return \"str\\t%1, %0\";
 179      case 6: return \"tmcr\\t%0, %1\";
 180      case 7: return \"tmrc\\t%0, %1\";
 181      case 8: return arm_output_load_gr (operands);
 182      case 9: return \"wstrw\\t%1, %0\";
 183      case 10:return \"fmsr\\t%0, %1\";
 184      case 11:return \"fmrs\\t%0, %1\";
 185      case 12:return \"fcpys\\t%0, %1\\t%@ int\";
 186      case 13: case 14:
 187        return output_move_vfp (operands);
 188      default:
 189        gcc_unreachable ();
 190      }"
 191   [(set_attr "type"           "*,*,*,*,load1,store1,*,*,*,*,r_2_f,f_2_r,fcpys,f_loads,f_stores")
 192    (set_attr "length"         "*,*,*,*,*,        *,*,*,  16,     *,*,*,*,*,*")
 193    (set_attr "pool_range"     "*,*,*,*,4096,     *,*,*,1024,     *,*,*,*,1020,*")
 194    (set_attr "neg_pool_range" "*,*,*,*,4084,     *,*,*,   *,  1012,*,*,*,1008,*")
 195    ;; Note - the "predicable" attribute is not allowed to have alternatives.
 196    ;; Since the wSTRw wCx instruction is not predicable, we cannot support
 197    ;; predicating any of the alternatives in this template.  Instead,
 198    ;; we do the predication ourselves, in cond_iwmmxt_movsi_insn.
 199    (set_attr "predicable"     "no")
 200    ;; Also - we have to pretend that these insns clobber the condition code
 201    ;; bits as otherwise arm_final_prescan_insn() will try to conditionalize
 202    ;; them.
 203    (set_attr "conds" "clob")
 204    (set_attr "wtype" "*,*,*,*,*,*,tmcr,tmrc,wldr,wstr,*,*,*,*,*")]
 205 )
 206
 207 ;; Because iwmmxt_movsi_insn is not predicable, we provide the
 208 ;; cond_exec version explicitly, with appropriate constraints.
 209
 210 (define_insn "*cond_iwmmxt_movsi_insn"
 211   [(cond_exec
 212      (match_operator 2 "arm_comparison_operator"
 213       [(match_operand 3 "cc_register" "")
 214       (const_int 0)])
 215      (set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m,z,r")
 216           (match_operand:SI 1 "general_operand"      "rI,K,mi,r,r,z")))]
 217   "TARGET_REALLY_IWMMXT
 218    && (   register_operand (operands[0], SImode)
 219        || register_operand (operands[1], SImode))"
 220   "*
 221    switch (which_alternative)
 222    {
 223    case 0: return \"mov%?\\t%0, %1\";
 224    case 1: return \"mvn%?\\t%0, #%B1\";
 225    case 2: return \"ldr%?\\t%0, %1\";
 226    case 3: return \"str%?\\t%1, %0\";
 227    case 4: return \"tmcr%?\\t%0, %1\";
 228    default: return \"tmrc%?\\t%0, %1\";
 229   }"
 230   [(set_attr "type"           "*,*,load1,store1,*,*")
 231    (set_attr "pool_range"     "*,*,4096,     *,*,*")
 232    (set_attr "neg_pool_range" "*,*,4084,     *,*,*")]
 233 )
 234
 235 (define_insn "mov<mode>_internal"
 236   [(set (match_operand:VMMX 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r,?r,?m")
 237         (match_operand:VMMX 1 "general_operand"       "y,y,mi,y,r,r,mi,r"))]
 238   "TARGET_REALLY_IWMMXT"
 239   "*
 240    switch (which_alternative)
 241    {
 242    case 0: return \"wmov%?\\t%0, %1\";
 243    case 1: return \"wstrd%?\\t%1, %0\";
 244    case 2: return \"wldrd%?\\t%0, %1\";
 245    case 3: return \"tmrrc%?\\t%Q0, %R0, %1\";
 246    case 4: return \"tmcrr%?\\t%0, %Q1, %R1\";
 247    case 5: return \"#\";
 248    default: return output_move_double (operands, true, NULL);
 249    }"
 250   [(set_attr "predicable" "yes")
 251    (set_attr "length"         "4,     4,   4,4,4,8,   8,8")
 252    (set_attr "type"           "*,*,*,*,*,*,load1,store1")
 253    (set_attr "pool_range"     "*,     *, 256,*,*,*, 256,*")
 254    (set_attr "neg_pool_range" "*,     *, 244,*,*,*, 244,*")
 255    (set_attr "wtype"          "wmov,wstr,wldr,tmrrc,tmcrr,*,*,*")]
 256 )
 257
 258 (define_expand "iwmmxt_setwcgr0"
 259   [(set (reg:SI WCGR0)
 260         (match_operand:SI 0 "register_operand"  ""))]
 261   "TARGET_REALLY_IWMMXT"
 262   {}
 263 )
 264
 265 (define_expand "iwmmxt_setwcgr1"
 266   [(set (reg:SI WCGR1)
 267         (match_operand:SI 0 "register_operand"  ""))]
 268   "TARGET_REALLY_IWMMXT"
 269   {}
 270 )
 271
 272 (define_expand "iwmmxt_setwcgr2"
 273   [(set (reg:SI WCGR2)
 274         (match_operand:SI 0 "register_operand"  ""))]
 275   "TARGET_REALLY_IWMMXT"
 276   {}
 277 )
 278
 279 (define_expand "iwmmxt_setwcgr3"
 280   [(set (reg:SI WCGR3)
 281         (match_operand:SI 0 "register_operand"  ""))]
 282   "TARGET_REALLY_IWMMXT"
 283   {}
 284 )
 285
 286 (define_expand "iwmmxt_getwcgr0"
 287   [(set (match_operand:SI 0 "register_operand"  "")
 288         (reg:SI WCGR0))]
 289   "TARGET_REALLY_IWMMXT"
 290   {}
 291 )
 292
 293 (define_expand "iwmmxt_getwcgr1"
 294   [(set (match_operand:SI 0 "register_operand"  "")
 295         (reg:SI WCGR1))]
 296   "TARGET_REALLY_IWMMXT"
 297   {}
 298 )
 299
 300 (define_expand "iwmmxt_getwcgr2"
 301   [(set (match_operand:SI 0 "register_operand"  "")
 302         (reg:SI WCGR2))]
 303   "TARGET_REALLY_IWMMXT"
 304   {}
 305 )
 306
 307 (define_expand "iwmmxt_getwcgr3"
 308   [(set (match_operand:SI 0 "register_operand"  "")
 309         (reg:SI WCGR3))]
 310   "TARGET_REALLY_IWMMXT"
 311   {}
 312 )
 313
 314 (define_insn "*and<mode>3_iwmmxt"
 315   [(set (match_operand:VMMX           0 "register_operand" "=y")
 316         (and:VMMX (match_operand:VMMX 1 "register_operand"  "y")
 317                   (match_operand:VMMX 2 "register_operand"  "y")))]
 318   "TARGET_REALLY_IWMMXT"
 319   "wand\\t%0, %1, %2"
 320   [(set_attr "predicable" "yes")
 321    (set_attr "wtype" "wand")]
 322 )
 323
 324 (define_insn "*ior<mode>3_iwmmxt"
 325   [(set (match_operand:VMMX           0 "register_operand" "=y")
 326         (ior:VMMX (match_operand:VMMX 1 "register_operand"  "y")
 327                   (match_operand:VMMX 2 "register_operand"  "y")))]
 328   "TARGET_REALLY_IWMMXT"
 329   "wor\\t%0, %1, %2"
 330   [(set_attr "predicable" "yes")
 331    (set_attr "wtype" "wor")]
 332 )
 333
 334 (define_insn "*xor<mode>3_iwmmxt"
 335   [(set (match_operand:VMMX           0 "register_operand" "=y")
 336         (xor:VMMX (match_operand:VMMX 1 "register_operand"  "y")
 337                   (match_operand:VMMX 2 "register_operand"  "y")))]
 338   "TARGET_REALLY_IWMMXT"
 339   "wxor\\t%0, %1, %2"
 340   [(set_attr "predicable" "yes")
 341    (set_attr "wtype" "wxor")]
 342 )
 343
 344
 345 ;; Vector add/subtract
 346
 347 (define_insn "*add<mode>3_iwmmxt"
 348   [(set (match_operand:VMMX            0 "register_operand" "=y")
 349         (plus:VMMX (match_operand:VMMX 1 "register_operand" "y")
 350                    (match_operand:VMMX 2 "register_operand" "y")))]
 351   "TARGET_REALLY_IWMMXT"
 352   "wadd<MMX_char>%?\\t%0, %1, %2"
 353   [(set_attr "predicable" "yes")
 354    (set_attr "wtype" "wadd")]
 355 )
 356
 357 (define_insn "ssaddv8qi3"
 358   [(set (match_operand:V8QI               0 "register_operand" "=y")
 359         (ss_plus:V8QI (match_operand:V8QI 1 "register_operand"  "y")
 360                       (match_operand:V8QI 2 "register_operand"  "y")))]
 361   "TARGET_REALLY_IWMMXT"
 362   "waddbss%?\\t%0, %1, %2"
 363   [(set_attr "predicable" "yes")
 364    (set_attr "wtype" "wadd")]
 365 )
 366
 367 (define_insn "ssaddv4hi3"
 368   [(set (match_operand:V4HI               0 "register_operand" "=y")
 369         (ss_plus:V4HI (match_operand:V4HI 1 "register_operand"  "y")
 370                       (match_operand:V4HI 2 "register_operand"  "y")))]
 371   "TARGET_REALLY_IWMMXT"
 372   "waddhss%?\\t%0, %1, %2"
 373   [(set_attr "predicable" "yes")
 374    (set_attr "wtype" "wadd")]
 375 )
 376
 377 (define_insn "ssaddv2si3"
 378   [(set (match_operand:V2SI               0 "register_operand" "=y")
 379         (ss_plus:V2SI (match_operand:V2SI 1 "register_operand"  "y")
 380                       (match_operand:V2SI 2 "register_operand"  "y")))]
 381   "TARGET_REALLY_IWMMXT"
 382   "waddwss%?\\t%0, %1, %2"
 383   [(set_attr "predicable" "yes")
 384    (set_attr "wtype" "wadd")]
 385 )
 386
 387 (define_insn "usaddv8qi3"
 388   [(set (match_operand:V8QI               0 "register_operand" "=y")
 389         (us_plus:V8QI (match_operand:V8QI 1 "register_operand"  "y")
 390                       (match_operand:V8QI 2 "register_operand"  "y")))]
 391   "TARGET_REALLY_IWMMXT"
 392   "waddbus%?\\t%0, %1, %2"
 393   [(set_attr "predicable" "yes")
 394    (set_attr "wtype" "wadd")]
 395 )
 396
 397 (define_insn "usaddv4hi3"
 398   [(set (match_operand:V4HI               0 "register_operand" "=y")
 399         (us_plus:V4HI (match_operand:V4HI 1 "register_operand"  "y")
 400                       (match_operand:V4HI 2 "register_operand"  "y")))]
 401   "TARGET_REALLY_IWMMXT"
 402   "waddhus%?\\t%0, %1, %2"
 403   [(set_attr "predicable" "yes")
 404    (set_attr "wtype" "wadd")]
 405 )
 406
 407 (define_insn "usaddv2si3"
 408   [(set (match_operand:V2SI               0 "register_operand" "=y")
 409         (us_plus:V2SI (match_operand:V2SI 1 "register_operand"  "y")
 410                       (match_operand:V2SI 2 "register_operand"  "y")))]
 411   "TARGET_REALLY_IWMMXT"
 412   "waddwus%?\\t%0, %1, %2"
 413   [(set_attr "predicable" "yes")
 414    (set_attr "wtype" "wadd")]
 415 )
 416
 417 (define_insn "*sub<mode>3_iwmmxt"
 418   [(set (match_operand:VMMX             0 "register_operand" "=y")
 419         (minus:VMMX (match_operand:VMMX 1 "register_operand"  "y")
 420                     (match_operand:VMMX 2 "register_operand"  "y")))]
 421   "TARGET_REALLY_IWMMXT"
 422   "wsub<MMX_char>%?\\t%0, %1, %2"
 423   [(set_attr "predicable" "yes")
 424    (set_attr "wtype" "wsub")]
 425 )
 426
 427 (define_insn "sssubv8qi3"
 428   [(set (match_operand:V8QI                0 "register_operand" "=y")
 429         (ss_minus:V8QI (match_operand:V8QI 1 "register_operand"  "y")
 430                        (match_operand:V8QI 2 "register_operand"  "y")))]
 431   "TARGET_REALLY_IWMMXT"
 432   "wsubbss%?\\t%0, %1, %2"
 433   [(set_attr "predicable" "yes")
 434    (set_attr "wtype" "wsub")]
 435 )
 436
 437 (define_insn "sssubv4hi3"
 438   [(set (match_operand:V4HI                0 "register_operand" "=y")
 439         (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "y")
 440                        (match_operand:V4HI 2 "register_operand" "y")))]
 441   "TARGET_REALLY_IWMMXT"
 442   "wsubhss%?\\t%0, %1, %2"
 443   [(set_attr "predicable" "yes")
 444    (set_attr "wtype" "wsub")]
 445 )
 446
 447 (define_insn "sssubv2si3"
 448   [(set (match_operand:V2SI                0 "register_operand" "=y")
 449         (ss_minus:V2SI (match_operand:V2SI 1 "register_operand" "y")
 450                        (match_operand:V2SI 2 "register_operand" "y")))]
 451   "TARGET_REALLY_IWMMXT"
 452   "wsubwss%?\\t%0, %1, %2"
 453   [(set_attr "predicable" "yes")
 454    (set_attr "wtype" "wsub")]
 455 )
 456
 457 (define_insn "ussubv8qi3"
 458   [(set (match_operand:V8QI                0 "register_operand" "=y")
 459         (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "y")
 460                        (match_operand:V8QI 2 "register_operand" "y")))]
 461   "TARGET_REALLY_IWMMXT"
 462   "wsubbus%?\\t%0, %1, %2"
 463   [(set_attr "predicable" "yes")
 464    (set_attr "wtype" "wsub")]
 465 )
 466
 467 (define_insn "ussubv4hi3"
 468   [(set (match_operand:V4HI                0 "register_operand" "=y")
 469         (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "y")
 470                        (match_operand:V4HI 2 "register_operand" "y")))]
 471   "TARGET_REALLY_IWMMXT"
 472   "wsubhus%?\\t%0, %1, %2"
 473   [(set_attr "predicable" "yes")
 474    (set_attr "wtype" "wsub")]
 475 )
 476
 477 (define_insn "ussubv2si3"
 478   [(set (match_operand:V2SI                0 "register_operand" "=y")
 479         (us_minus:V2SI (match_operand:V2SI 1 "register_operand" "y")
 480                        (match_operand:V2SI 2 "register_operand" "y")))]
 481   "TARGET_REALLY_IWMMXT"
 482   "wsubwus%?\\t%0, %1, %2"
 483   [(set_attr "predicable" "yes")
 484    (set_attr "wtype" "wsub")]
 485 )
 486
 487 (define_insn "*mulv4hi3_iwmmxt"
 488   [(set (match_operand:V4HI            0 "register_operand" "=y")
 489         (mult:V4HI (match_operand:V4HI 1 "register_operand" "y")
 490                    (match_operand:V4HI 2 "register_operand" "y")))]
 491   "TARGET_REALLY_IWMMXT"
 492   "wmulul%?\\t%0, %1, %2"
 493   [(set_attr "predicable" "yes")
 494    (set_attr "wtype" "wmul")]
 495 )
 496
 497 (define_insn "smulv4hi3_highpart"
 498   [(set (match_operand:V4HI 0 "register_operand" "=y")
 499           (truncate:V4HI
 500             (lshiftrt:V4SI
 501               (mult:V4SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
 502                          (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
 503               (const_int 16))))]
 504   "TARGET_REALLY_IWMMXT"
 505   "wmulsm%?\\t%0, %1, %2"
 506   [(set_attr "predicable" "yes")
 507    (set_attr "wtype" "wmul")]
 508 )
 509
 510 (define_insn "umulv4hi3_highpart"
 511   [(set (match_operand:V4HI 0 "register_operand" "=y")
 512           (truncate:V4HI
 513             (lshiftrt:V4SI
 514               (mult:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
 515                          (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
 516               (const_int 16))))]
 517   "TARGET_REALLY_IWMMXT"
 518   "wmulum%?\\t%0, %1, %2"
 519   [(set_attr "predicable" "yes")
 520    (set_attr "wtype" "wmul")]
 521 )
 522
 523 (define_insn "iwmmxt_wmacs"
 524   [(set (match_operand:DI               0 "register_operand" "=y")
 525         (unspec:DI [(match_operand:DI   1 "register_operand" "0")
 526                     (match_operand:V4HI 2 "register_operand" "y")
 527                     (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACS))]
 528   "TARGET_REALLY_IWMMXT"
 529   "wmacs%?\\t%0, %2, %3"
 530   [(set_attr "predicable" "yes")
 531    (set_attr "wtype" "wmac")]
 532 )
 533
 534 (define_insn "iwmmxt_wmacsz"
 535   [(set (match_operand:DI               0 "register_operand" "=y")
 536         (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")
 537                     (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACSZ))]
 538   "TARGET_REALLY_IWMMXT"
 539   "wmacsz%?\\t%0, %1, %2"
 540   [(set_attr "predicable" "yes")
 541    (set_attr "wtype" "wmac")]
 542 )
 543
 544 (define_insn "iwmmxt_wmacu"
 545   [(set (match_operand:DI               0 "register_operand" "=y")
 546         (unspec:DI [(match_operand:DI   1 "register_operand" "0")
 547                     (match_operand:V4HI 2 "register_operand" "y")
 548                     (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACU))]
 549   "TARGET_REALLY_IWMMXT"
 550   "wmacu%?\\t%0, %2, %3"
 551   [(set_attr "predicable" "yes")
 552    (set_attr "wtype" "wmac")]
 553 )
 554
 555 (define_insn "iwmmxt_wmacuz"
 556   [(set (match_operand:DI               0 "register_operand" "=y")
 557         (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")
 558                     (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACUZ))]
 559   "TARGET_REALLY_IWMMXT"
 560   "wmacuz%?\\t%0, %1, %2"
 561   [(set_attr "predicable" "yes")
 562    (set_attr "wtype" "wmac")]
 563 )
 564
 565 ;; Same as xordi3, but don't show input operands so that we don't think
 566 ;; they are live.
 567 (define_insn "iwmmxt_clrdi"
 568   [(set (match_operand:DI 0 "register_operand" "=y")
 569         (unspec:DI [(const_int 0)] UNSPEC_CLRDI))]
 570   "TARGET_REALLY_IWMMXT"
 571   "wxor%?\\t%0, %0, %0"
 572   [(set_attr "predicable" "yes")
 573    (set_attr "wtype" "wxor")]
 574 )
 575
 576 ;; Seems like cse likes to generate these, so we have to support them.
 577
 578 (define_insn "iwmmxt_clrv8qi"
 579   [(set (match_operand:V8QI 0 "s_register_operand" "=y")
 580         (const_vector:V8QI [(const_int 0) (const_int 0)
 581                             (const_int 0) (const_int 0)
 582                             (const_int 0) (const_int 0)
 583                             (const_int 0) (const_int 0)]))]
 584   "TARGET_REALLY_IWMMXT"
 585   "wxor%?\\t%0, %0, %0"
 586   [(set_attr "predicable" "yes")
 587    (set_attr "wtype" "wxor")]
 588 )
 589
 590 (define_insn "iwmmxt_clrv4hi"
 591   [(set (match_operand:V4HI 0 "s_register_operand" "=y")
 592         (const_vector:V4HI [(const_int 0) (const_int 0)
 593                             (const_int 0) (const_int 0)]))]
 594   "TARGET_REALLY_IWMMXT"
 595   "wxor%?\\t%0, %0, %0"
 596   [(set_attr "predicable" "yes")
 597    (set_attr "wtype" "wxor")]
 598 )
 599
 600 (define_insn "iwmmxt_clrv2si"
 601   [(set (match_operand:V2SI 0 "register_operand" "=y")
 602         (const_vector:V2SI [(const_int 0) (const_int 0)]))]
 603   "TARGET_REALLY_IWMMXT"
 604   "wxor%?\\t%0, %0, %0"
 605   [(set_attr "predicable" "yes")
 606    (set_attr "wtype" "wxor")]
 607 )
 608
 609 ;; Unsigned averages/sum of absolute differences
 610
 611 (define_insn "iwmmxt_uavgrndv8qi3"
 612   [(set (match_operand:V8QI                                    0 "register_operand" "=y")
 613         (truncate:V8QI
 614           (lshiftrt:V8HI
 615             (plus:V8HI
 616               (plus:V8HI (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
 617                          (zero_extend:V8HI (match_operand:V8QI 2 "register_operand" "y")))
 618               (const_vector:V8HI [(const_int 1)
 619                                   (const_int 1)
 620                                   (const_int 1)
 621                                   (const_int 1)
 622                                   (const_int 1)
 623                                   (const_int 1)
 624                                   (const_int 1)
 625                                   (const_int 1)]))
 626             (const_int 1))))]
 627   "TARGET_REALLY_IWMMXT"
 628   "wavg2br%?\\t%0, %1, %2"
 629   [(set_attr "predicable" "yes")
 630    (set_attr "wtype" "wavg2")]
 631 )
 632
 633 (define_insn "iwmmxt_uavgrndv4hi3"
 634   [(set (match_operand:V4HI                                    0 "register_operand" "=y")
 635         (truncate:V4HI
 636           (lshiftrt:V4SI
 637             (plus:V4SI
 638               (plus:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
 639                          (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
 640               (const_vector:V4SI [(const_int 1)
 641                                   (const_int 1)
 642                                   (const_int 1)
 643                                   (const_int 1)]))
 644             (const_int 1))))]
 645   "TARGET_REALLY_IWMMXT"
 646   "wavg2hr%?\\t%0, %1, %2"
 647   [(set_attr "predicable" "yes")
 648    (set_attr "wtype" "wavg2")]
 649 )
 650
 651 (define_insn "iwmmxt_uavgv8qi3"
 652   [(set (match_operand:V8QI                                  0 "register_operand" "=y")
 653         (truncate:V8QI
 654           (lshiftrt:V8HI
 655             (plus:V8HI (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
 656                        (zero_extend:V8HI (match_operand:V8QI 2 "register_operand" "y")))
 657             (const_int 1))))]
 658   "TARGET_REALLY_IWMMXT"
 659   "wavg2b%?\\t%0, %1, %2"
 660   [(set_attr "predicable" "yes")
 661    (set_attr "wtype" "wavg2")]
 662 )
 663
 664 (define_insn "iwmmxt_uavgv4hi3"
 665   [(set (match_operand:V4HI                                  0 "register_operand" "=y")
 666         (truncate:V4HI
 667           (lshiftrt:V4SI
 668             (plus:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
 669                        (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
 670             (const_int 1))))]
 671   "TARGET_REALLY_IWMMXT"
 672   "wavg2h%?\\t%0, %1, %2"
 673   [(set_attr "predicable" "yes")
 674    (set_attr "wtype" "wavg2")]
 675 )
 676
 677 ;; Insert/extract/shuffle
 678
 679 (define_insn "iwmmxt_tinsrb"
 680   [(set (match_operand:V8QI                0 "register_operand" "=y")
 681         (vec_merge:V8QI
 682           (vec_duplicate:V8QI
 683             (truncate:QI (match_operand:SI 2 "nonimmediate_operand" "r")))
 684           (match_operand:V8QI              1 "register_operand"     "0")
 685           (match_operand:SI                3 "immediate_operand"    "i")))]
 686   "TARGET_REALLY_IWMMXT"
 687   "*
 688    {
 689      return arm_output_iwmmxt_tinsr (operands);
 690    }
 691    "
 692   [(set_attr "predicable" "yes")
 693    (set_attr "wtype" "tinsr")]
 694 )
 695
 696 (define_insn "iwmmxt_tinsrh"
 697   [(set (match_operand:V4HI                0 "register_operand"    "=y")
 698         (vec_merge:V4HI
 699           (vec_duplicate:V4HI
 700             (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "r")))
 701           (match_operand:V4HI              1 "register_operand"     "0")
 702           (match_operand:SI                3 "immediate_operand"    "i")))]
 703   "TARGET_REALLY_IWMMXT"
 704   "*
 705    {
 706      return arm_output_iwmmxt_tinsr (operands);
 707    }
 708    "
 709   [(set_attr "predicable" "yes")
 710    (set_attr "wtype" "tinsr")]
 711 )
 712
 713 (define_insn "iwmmxt_tinsrw"
 714   [(set (match_operand:V2SI   0 "register_operand"    "=y")
 715         (vec_merge:V2SI
 716           (vec_duplicate:V2SI
 717             (match_operand:SI 2 "nonimmediate_operand" "r"))
 718           (match_operand:V2SI 1 "register_operand"     "0")
 719           (match_operand:SI   3 "immediate_operand"    "i")))]
 720   "TARGET_REALLY_IWMMXT"
 721   "*
 722    {
 723      return arm_output_iwmmxt_tinsr (operands);
 724    }
 725    "
 726   [(set_attr "predicable" "yes")
 727    (set_attr "wtype" "tinsr")]
 728 )
 729
 730 (define_insn "iwmmxt_textrmub"
 731   [(set (match_operand:SI                                   0 "register_operand" "=r")
 732         (zero_extend:SI (vec_select:QI (match_operand:V8QI  1 "register_operand" "y")
 733                                        (parallel
 734                                          [(match_operand:SI 2 "immediate_operand" "i")]))))]
 735   "TARGET_REALLY_IWMMXT"
 736   "textrmub%?\\t%0, %1, %2"
 737   [(set_attr "predicable" "yes")
 738    (set_attr "wtype" "textrm")]
 739 )
 740
 741 (define_insn "iwmmxt_textrmsb"
 742   [(set (match_operand:SI                                   0 "register_operand" "=r")
 743         (sign_extend:SI (vec_select:QI (match_operand:V8QI  1 "register_operand" "y")
 744                                        (parallel
 745                                          [(match_operand:SI 2 "immediate_operand" "i")]))))]
 746   "TARGET_REALLY_IWMMXT"
 747   "textrmsb%?\\t%0, %1, %2"
 748   [(set_attr "predicable" "yes")
 749    (set_attr "wtype" "textrm")]
 750 )
 751
 752 (define_insn "iwmmxt_textrmuh"
 753   [(set (match_operand:SI                                   0 "register_operand" "=r")
 754         (zero_extend:SI (vec_select:HI (match_operand:V4HI  1 "register_operand" "y")
 755                                        (parallel
 756                                          [(match_operand:SI 2 "immediate_operand" "i")]))))]
 757   "TARGET_REALLY_IWMMXT"
 758   "textrmuh%?\\t%0, %1, %2"
 759   [(set_attr "predicable" "yes")
 760    (set_attr "wtype" "textrm")]
 761 )
 762
 763 (define_insn "iwmmxt_textrmsh"
 764   [(set (match_operand:SI                                   0 "register_operand" "=r")
 765         (sign_extend:SI (vec_select:HI (match_operand:V4HI  1 "register_operand" "y")
 766                                        (parallel
 767                                          [(match_operand:SI 2 "immediate_operand" "i")]))))]
 768   "TARGET_REALLY_IWMMXT"
 769   "textrmsh%?\\t%0, %1, %2"
 770   [(set_attr "predicable" "yes")
 771    (set_attr "wtype" "textrm")]
 772 )
 773
 774 ;; There are signed/unsigned variants of this instruction, but they are
 775 ;; pointless.
 776 (define_insn "iwmmxt_textrmw"
 777   [(set (match_operand:SI                           0 "register_operand" "=r")
 778         (vec_select:SI (match_operand:V2SI          1 "register_operand" "y")
 779                        (parallel [(match_operand:SI 2 "immediate_operand" "i")])))]
 780   "TARGET_REALLY_IWMMXT"
 781   "textrmsw%?\\t%0, %1, %2"
 782   [(set_attr "predicable" "yes")
 783    (set_attr "wtype" "textrm")]
 784 )
 785
 786 (define_insn "iwmmxt_wshufh"
 787   [(set (match_operand:V4HI               0 "register_operand" "=y")
 788         (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
 789                       (match_operand:SI   2 "immediate_operand" "i")] UNSPEC_WSHUFH))]
 790   "TARGET_REALLY_IWMMXT"
 791   "wshufh%?\\t%0, %1, %2"
 792   [(set_attr "predicable" "yes")
 793    (set_attr "wtype" "wshufh")]
 794 )
 795
 796 ;; Mask-generating comparisons
 797 ;;
 798 ;; Note - you cannot use patterns like these here:
 799 ;;
 800 ;;   (set (match:<vector>) (<comparator>:<vector> (match:<vector>) (match:<vector>)))
 801 ;;
 802 ;; Because GCC will assume that the truth value (1 or 0) is installed
 803 ;; into the entire destination vector, (with the '1' going into the least
 804 ;; significant element of the vector).  This is not how these instructions
 805 ;; behave.
 806
 807 (define_insn "eqv8qi3"
 808   [(set (match_operand:V8QI                        0 "register_operand" "=y")
 809         (unspec_volatile:V8QI [(match_operand:V8QI 1 "register_operand"  "y")
 810                                (match_operand:V8QI 2 "register_operand"  "y")]
 811                               VUNSPEC_WCMP_EQ))]
 812   "TARGET_REALLY_IWMMXT"
 813   "wcmpeqb%?\\t%0, %1, %2"
 814   [(set_attr "predicable" "yes")
 815    (set_attr "wtype" "wcmpeq")]
 816 )
 817
 818 (define_insn "eqv4hi3"
 819   [(set (match_operand:V4HI                        0 "register_operand" "=y")
 820         (unspec_volatile:V4HI [(match_operand:V4HI 1 "register_operand"  "y")
 821                                (match_operand:V4HI 2 "register_operand"  "y")]
 822                                VUNSPEC_WCMP_EQ))]
 823   "TARGET_REALLY_IWMMXT"
 824   "wcmpeqh%?\\t%0, %1, %2"
 825   [(set_attr "predicable" "yes")
 826    (set_attr "wtype" "wcmpeq")]
 827 )
 828
 829 (define_insn "eqv2si3"
 830   [(set (match_operand:V2SI    0 "register_operand" "=y")
 831         (unspec_volatile:V2SI
 832           [(match_operand:V2SI 1 "register_operand"  "y")
 833            (match_operand:V2SI 2 "register_operand"  "y")]
 834            VUNSPEC_WCMP_EQ))]
 835   "TARGET_REALLY_IWMMXT"
 836   "wcmpeqw%?\\t%0, %1, %2"
 837   [(set_attr "predicable" "yes")
 838    (set_attr "wtype" "wcmpeq")]
 839 )
 840
 841 (define_insn "gtuv8qi3"
 842   [(set (match_operand:V8QI                        0 "register_operand" "=y")
 843         (unspec_volatile:V8QI [(match_operand:V8QI 1 "register_operand"  "y")
 844                                (match_operand:V8QI 2 "register_operand"  "y")]
 845                                VUNSPEC_WCMP_GTU))]
 846   "TARGET_REALLY_IWMMXT"
 847   "wcmpgtub%?\\t%0, %1, %2"
 848   [(set_attr "predicable" "yes")
 849    (set_attr "wtype" "wcmpgt")]
 850 )
 851
 852 (define_insn "gtuv4hi3"
 853   [(set (match_operand:V4HI                        0 "register_operand" "=y")
 854         (unspec_volatile:V4HI [(match_operand:V4HI 1 "register_operand"  "y")
 855                                (match_operand:V4HI 2 "register_operand"  "y")]
 856                                VUNSPEC_WCMP_GTU))]
 857   "TARGET_REALLY_IWMMXT"
 858   "wcmpgtuh%?\\t%0, %1, %2"
 859   [(set_attr "predicable" "yes")
 860    (set_attr "wtype" "wcmpgt")]
 861 )
 862
 863 (define_insn "gtuv2si3"
 864   [(set (match_operand:V2SI                        0 "register_operand" "=y")
 865         (unspec_volatile:V2SI [(match_operand:V2SI 1 "register_operand"  "y")
 866                                (match_operand:V2SI 2 "register_operand"  "y")]
 867                                VUNSPEC_WCMP_GTU))]
 868   "TARGET_REALLY_IWMMXT"
 869   "wcmpgtuw%?\\t%0, %1, %2"
 870   [(set_attr "predicable" "yes")
 871    (set_attr "wtype" "wcmpgt")]
 872 )
 873
 874 (define_insn "gtv8qi3"
 875   [(set (match_operand:V8QI                        0 "register_operand" "=y")
 876         (unspec_volatile:V8QI [(match_operand:V8QI 1 "register_operand"  "y")
 877                                (match_operand:V8QI 2 "register_operand"  "y")]
 878                                VUNSPEC_WCMP_GT))]
 879   "TARGET_REALLY_IWMMXT"
 880   "wcmpgtsb%?\\t%0, %1, %2"
 881   [(set_attr "predicable" "yes")
 882    (set_attr "wtype" "wcmpgt")]
 883 )
 884
 885 (define_insn "gtv4hi3"
 886   [(set (match_operand:V4HI                        0 "register_operand" "=y")
 887         (unspec_volatile:V4HI [(match_operand:V4HI 1 "register_operand"  "y")
 888                                (match_operand:V4HI 2 "register_operand"  "y")]
 889                                VUNSPEC_WCMP_GT))]
 890   "TARGET_REALLY_IWMMXT"
 891   "wcmpgtsh%?\\t%0, %1, %2"
 892   [(set_attr "predicable" "yes")
 893    (set_attr "wtype" "wcmpgt")]
 894 )
 895
 896 (define_insn "gtv2si3"
 897   [(set (match_operand:V2SI                        0 "register_operand" "=y")
 898         (unspec_volatile:V2SI [(match_operand:V2SI 1 "register_operand"  "y")
 899                                (match_operand:V2SI 2 "register_operand"  "y")]
 900                                VUNSPEC_WCMP_GT))]
 901   "TARGET_REALLY_IWMMXT"
 902   "wcmpgtsw%?\\t%0, %1, %2"
 903   [(set_attr "predicable" "yes")
 904    (set_attr "wtype" "wcmpgt")]
 905 )
 906
 907 ;; Max/min insns
 908
 909 (define_insn "*smax<mode>3_iwmmxt"
 910   [(set (match_operand:VMMX            0 "register_operand" "=y")
 911         (smax:VMMX (match_operand:VMMX 1 "register_operand" "y")
 912                    (match_operand:VMMX 2 "register_operand" "y")))]
 913   "TARGET_REALLY_IWMMXT"
 914   "wmaxs<MMX_char>%?\\t%0, %1, %2"
 915   [(set_attr "predicable" "yes")
 916    (set_attr "wtype" "wmax")]
 917 )
 918
 919 (define_insn "*umax<mode>3_iwmmxt"
 920   [(set (match_operand:VMMX            0 "register_operand" "=y")
 921         (umax:VMMX (match_operand:VMMX 1 "register_operand" "y")
 922                    (match_operand:VMMX 2 "register_operand" "y")))]
 923   "TARGET_REALLY_IWMMXT"
 924   "wmaxu<MMX_char>%?\\t%0, %1, %2"
 925   [(set_attr "predicable" "yes")
 926    (set_attr "wtype" "wmax")]
 927 )
 928
 929 (define_insn "*smin<mode>3_iwmmxt"
 930   [(set (match_operand:VMMX            0 "register_operand" "=y")
 931         (smin:VMMX (match_operand:VMMX 1 "register_operand" "y")
 932                    (match_operand:VMMX 2 "register_operand" "y")))]
 933   "TARGET_REALLY_IWMMXT"
 934   "wmins<MMX_char>%?\\t%0, %1, %2"
 935   [(set_attr "predicable" "yes")
 936    (set_attr "wtype" "wmin")]
 937 )
 938
 939 (define_insn "*umin<mode>3_iwmmxt"
 940   [(set (match_operand:VMMX            0 "register_operand" "=y")
 941         (umin:VMMX (match_operand:VMMX 1 "register_operand" "y")
 942                    (match_operand:VMMX 2 "register_operand" "y")))]
 943   "TARGET_REALLY_IWMMXT"
 944   "wminu<MMX_char>%?\\t%0, %1, %2"
 945   [(set_attr "predicable" "yes")
 946    (set_attr "wtype" "wmin")]
 947 )
 948
 949 ;; Pack/unpack insns.
 950
 951 (define_insn "iwmmxt_wpackhss"
 952   [(set (match_operand:V8QI                     0 "register_operand" "=y")
 953         (vec_concat:V8QI
 954           (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y"))
 955           (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
 956   "TARGET_REALLY_IWMMXT"
 957   "wpackhss%?\\t%0, %1, %2"
 958   [(set_attr "predicable" "yes")
 959    (set_attr "wtype" "wpack")]
 960 )
 961
 962 (define_insn "iwmmxt_wpackwss"
 963   [(set (match_operand:V4HI                     0 "register_operand" "=y")
 964         (vec_concat:V4HI
 965           (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y"))
 966           (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
 967   "TARGET_REALLY_IWMMXT"
 968   "wpackwss%?\\t%0, %1, %2"
 969   [(set_attr "predicable" "yes")
 970    (set_attr "wtype" "wpack")]
 971 )
 972
 973 (define_insn "iwmmxt_wpackdss"
 974   [(set (match_operand:V2SI                 0 "register_operand" "=y")
 975         (vec_concat:V2SI
 976           (ss_truncate:SI (match_operand:DI 1 "register_operand" "y"))
 977           (ss_truncate:SI (match_operand:DI 2 "register_operand" "y"))))]
 978   "TARGET_REALLY_IWMMXT"
 979   "wpackdss%?\\t%0, %1, %2"
 980   [(set_attr "predicable" "yes")
 981    (set_attr "wtype" "wpack")]
 982 )
 983
 984 (define_insn "iwmmxt_wpackhus"
 985   [(set (match_operand:V8QI                     0 "register_operand" "=y")
 986         (vec_concat:V8QI
 987           (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y"))
 988           (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
 989   "TARGET_REALLY_IWMMXT"
 990   "wpackhus%?\\t%0, %1, %2"
 991   [(set_attr "predicable" "yes")
 992    (set_attr "wtype" "wpack")]
 993 )
 994
 995 (define_insn "iwmmxt_wpackwus"
 996   [(set (match_operand:V4HI                     0 "register_operand" "=y")
 997         (vec_concat:V4HI
 998           (us_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y"))
 999           (us_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
1000   "TARGET_REALLY_IWMMXT"
1001   "wpackwus%?\\t%0, %1, %2"
1002   [(set_attr "predicable" "yes")
1003    (set_attr "wtype" "wpack")]
1004 )
1005
1006 (define_insn "iwmmxt_wpackdus"
1007   [(set (match_operand:V2SI                 0 "register_operand" "=y")
1008         (vec_concat:V2SI
1009           (us_truncate:SI (match_operand:DI 1 "register_operand" "y"))
1010           (us_truncate:SI (match_operand:DI 2 "register_operand" "y"))))]
1011   "TARGET_REALLY_IWMMXT"
1012   "wpackdus%?\\t%0, %1, %2"
1013   [(set_attr "predicable" "yes")
1014    (set_attr "wtype" "wpack")]
1015 )
1016
1017 (define_insn "iwmmxt_wunpckihb"
1018   [(set (match_operand:V8QI                                      0 "register_operand" "=y")
1019         (vec_merge:V8QI
1020           (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y")
1021                            (parallel [(const_int 4)
1022                                       (const_int 0)
1023                                       (const_int 5)
1024                                       (const_int 1)
1025                                       (const_int 6)
1026                                       (const_int 2)
1027                                       (const_int 7)
1028                                       (const_int 3)]))
1029           (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
1030                            (parallel [(const_int 0)
1031                                       (const_int 4)
1032                                       (const_int 1)
1033                                       (const_int 5)
1034                                       (const_int 2)
1035                                       (const_int 6)
1036                                       (const_int 3)
1037                                       (const_int 7)]))
1038           (const_int 85)))]
1039   "TARGET_REALLY_IWMMXT"
1040   "wunpckihb%?\\t%0, %1, %2"
1041   [(set_attr "predicable" "yes")
1042    (set_attr "wtype" "wunpckih")]
1043 )
1044
1045 (define_insn "iwmmxt_wunpckihh"
1046   [(set (match_operand:V4HI                                      0 "register_operand" "=y")
1047         (vec_merge:V4HI
1048           (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y")
1049                            (parallel [(const_int 2)
1050                                       (const_int 0)
1051                                       (const_int 3)
1052                                       (const_int 1)]))
1053           (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
1054                            (parallel [(const_int 0)
1055                                       (const_int 2)
1056                                       (const_int 1)
1057                                       (const_int 3)]))
1058           (const_int 5)))]
1059   "TARGET_REALLY_IWMMXT"
1060   "wunpckihh%?\\t%0, %1, %2"
1061   [(set_attr "predicable" "yes")
1062    (set_attr "wtype" "wunpckih")]
1063 )
1064
1065 (define_insn "iwmmxt_wunpckihw"
1066   [(set (match_operand:V2SI                    0 "register_operand" "=y")
1067         (vec_merge:V2SI
1068           (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y")
1069                            (parallel [(const_int 1)
1070                                       (const_int 0)]))
1071           (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
1072                            (parallel [(const_int 0)
1073                                       (const_int 1)]))
1074           (const_int 1)))]
1075   "TARGET_REALLY_IWMMXT"
1076   "wunpckihw%?\\t%0, %1, %2"
1077   [(set_attr "predicable" "yes")
1078    (set_attr "wtype" "wunpckih")]
1079 )
1080
1081 (define_insn "iwmmxt_wunpckilb"
1082   [(set (match_operand:V8QI                                      0 "register_operand" "=y")
1083         (vec_merge:V8QI
1084           (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y")
1085                            (parallel [(const_int 0)
1086                                       (const_int 4)
1087                                       (const_int 1)
1088                                       (const_int 5)
1089                                       (const_int 2)
1090                                       (const_int 6)
1091                                       (const_int 3)
1092                                       (const_int 7)]))
1093           (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
1094                            (parallel [(const_int 4)
1095                                       (const_int 0)
1096                                       (const_int 5)
1097                                       (const_int 1)
1098                                       (const_int 6)
1099                                       (const_int 2)
1100                                       (const_int 7)
1101                                       (const_int 3)]))
1102           (const_int 85)))]
1103   "TARGET_REALLY_IWMMXT"
1104   "wunpckilb%?\\t%0, %1, %2"
1105   [(set_attr "predicable" "yes")
1106    (set_attr "wtype" "wunpckil")]
1107 )
1108
1109 (define_insn "iwmmxt_wunpckilh"
1110   [(set (match_operand:V4HI                                      0 "register_operand" "=y")
1111         (vec_merge:V4HI
1112           (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y")
1113                            (parallel [(const_int 0)
1114                                       (const_int 2)
1115                                       (const_int 1)
1116                                       (const_int 3)]))
1117           (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
1118                            (parallel [(const_int 2)
1119                                       (const_int 0)
1120                                       (const_int 3)
1121                                       (const_int 1)]))
1122           (const_int 5)))]
1123   "TARGET_REALLY_IWMMXT"
1124   "wunpckilh%?\\t%0, %1, %2"
1125   [(set_attr "predicable" "yes")
1126    (set_attr "wtype" "wunpckil")]
1127 )
1128
1129 (define_insn "iwmmxt_wunpckilw"
1130   [(set (match_operand:V2SI                    0 "register_operand" "=y")
1131         (vec_merge:V2SI
1132           (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y")
1133                            (parallel [(const_int 0)
1134                                       (const_int 1)]))
1135           (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
1136                            (parallel [(const_int 1)
1137                                       (const_int 0)]))
1138           (const_int 1)))]
1139   "TARGET_REALLY_IWMMXT"
1140   "wunpckilw%?\\t%0, %1, %2"
1141   [(set_attr "predicable" "yes")
1142    (set_attr "wtype" "wunpckil")]
1143 )
1144
1145 (define_insn "iwmmxt_wunpckehub"
1146   [(set (match_operand:V4HI                     0 "register_operand" "=y")
1147         (vec_select:V4HI
1148           (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
1149           (parallel [(const_int 4) (const_int 5)
1150                      (const_int 6) (const_int 7)])))]
1151   "TARGET_REALLY_IWMMXT"
1152   "wunpckehub%?\\t%0, %1"
1153   [(set_attr "predicable" "yes")
1154    (set_attr "wtype" "wunpckeh")]
1155 )
1156
1157 (define_insn "iwmmxt_wunpckehuh"
1158   [(set (match_operand:V2SI                     0 "register_operand" "=y")
1159         (vec_select:V2SI
1160           (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
1161           (parallel [(const_int 2) (const_int 3)])))]
1162   "TARGET_REALLY_IWMMXT"
1163   "wunpckehuh%?\\t%0, %1"
1164   [(set_attr "predicable" "yes")
1165    (set_attr "wtype" "wunpckeh")]
1166 )
1167
1168 (define_insn "iwmmxt_wunpckehuw"
1169   [(set (match_operand:DI                       0 "register_operand" "=y")
1170         (vec_select:DI
1171           (zero_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
1172           (parallel [(const_int 1)])))]
1173   "TARGET_REALLY_IWMMXT"
1174   "wunpckehuw%?\\t%0, %1"
1175   [(set_attr "predicable" "yes")
1176    (set_attr "wtype" "wunpckeh")]
1177 )
1178
1179 (define_insn "iwmmxt_wunpckehsb"
1180   [(set (match_operand:V4HI                     0 "register_operand" "=y")
1181         (vec_select:V4HI
1182           (sign_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
1183           (parallel [(const_int 4) (const_int 5)
1184                      (const_int 6) (const_int 7)])))]
1185   "TARGET_REALLY_IWMMXT"
1186   "wunpckehsb%?\\t%0, %1"
1187   [(set_attr "predicable" "yes")
1188    (set_attr "wtype" "wunpckeh")]
1189 )
1190
1191 (define_insn "iwmmxt_wunpckehsh"
1192   [(set (match_operand:V2SI                     0 "register_operand" "=y")
1193         (vec_select:V2SI
1194           (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
1195           (parallel [(const_int 2) (const_int 3)])))]
1196   "TARGET_REALLY_IWMMXT"
1197   "wunpckehsh%?\\t%0, %1"
1198   [(set_attr "predicable" "yes")
1199    (set_attr "wtype" "wunpckeh")]
1200 )
1201
1202 (define_insn "iwmmxt_wunpckehsw"
1203   [(set (match_operand:DI                       0 "register_operand" "=y")
1204         (vec_select:DI
1205           (sign_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
1206           (parallel [(const_int 1)])))]
1207   "TARGET_REALLY_IWMMXT"
1208   "wunpckehsw%?\\t%0, %1"
1209   [(set_attr "predicable" "yes")
1210    (set_attr "wtype" "wunpckeh")]
1211 )
1212
1213 (define_insn "iwmmxt_wunpckelub"
1214   [(set (match_operand:V4HI                     0 "register_operand" "=y")
1215         (vec_select:V4HI
1216           (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
1217           (parallel [(const_int 0) (const_int 1)
1218                      (const_int 2) (const_int 3)])))]
1219   "TARGET_REALLY_IWMMXT"
1220   "wunpckelub%?\\t%0, %1"
1221   [(set_attr "predicable" "yes")
1222    (set_attr "wtype" "wunpckel")]
1223 )
1224
1225 (define_insn "iwmmxt_wunpckeluh"
1226   [(set (match_operand:V2SI                     0 "register_operand" "=y")
1227         (vec_select:V2SI
1228           (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
1229           (parallel [(const_int 0) (const_int 1)])))]
1230   "TARGET_REALLY_IWMMXT"
1231   "wunpckeluh%?\\t%0, %1"
1232   [(set_attr "predicable" "yes")
1233    (set_attr "wtype" "wunpckel")]
1234 )
1235
1236 (define_insn "iwmmxt_wunpckeluw"
1237   [(set (match_operand:DI                       0 "register_operand" "=y")
1238         (vec_select:DI
1239           (zero_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
1240           (parallel [(const_int 0)])))]
1241   "TARGET_REALLY_IWMMXT"
1242   "wunpckeluw%?\\t%0, %1"
1243   [(set_attr "predicable" "yes")
1244    (set_attr "wtype" "wunpckel")]
1245 )
1246
1247 (define_insn "iwmmxt_wunpckelsb"
1248   [(set (match_operand:V4HI                     0 "register_operand" "=y")
1249         (vec_select:V4HI
1250           (sign_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
1251           (parallel [(const_int 0) (const_int 1)
1252                      (const_int 2) (const_int 3)])))]
1253   "TARGET_REALLY_IWMMXT"
1254   "wunpckelsb%?\\t%0, %1"
1255   [(set_attr "predicable" "yes")
1256    (set_attr "wtype" "wunpckel")]
1257 )
1258
1259 (define_insn "iwmmxt_wunpckelsh"
1260   [(set (match_operand:V2SI                     0 "register_operand" "=y")
1261         (vec_select:V2SI
1262           (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
1263           (parallel [(const_int 0) (const_int 1)])))]
1264   "TARGET_REALLY_IWMMXT"
1265   "wunpckelsh%?\\t%0, %1"
1266   [(set_attr "predicable" "yes")
1267    (set_attr "wtype" "wunpckel")]
1268 )
1269
1270 (define_insn "iwmmxt_wunpckelsw"
1271   [(set (match_operand:DI                       0 "register_operand" "=y")
1272         (vec_select:DI
1273           (sign_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
1274           (parallel [(const_int 0)])))]
1275   "TARGET_REALLY_IWMMXT"
1276   "wunpckelsw%?\\t%0, %1"
1277   [(set_attr "predicable" "yes")
1278    (set_attr "wtype" "wunpckel")]
1279 )
1280
1281 ;; Shifts
1282
1283 (define_insn "ror<mode>3"
1284   [(set (match_operand:VSHFT                 0 "register_operand" "=y,y")
1285         (rotatert:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
1286                         (match_operand:SI    2 "imm_or_reg_operand" "z,i")))]
1287   "TARGET_REALLY_IWMMXT"
1288   "*
1289   switch  (which_alternative)
1290     {
1291     case 0:
1292       return \"wror<MMX_char>g%?\\t%0, %1, %2\";
1293     case 1:
1294       return arm_output_iwmmxt_shift_immediate (\"wror<MMX_char>\", operands, true);
1295     default:
1296       gcc_unreachable ();
1297     }
1298   "
1299   [(set_attr "predicable" "yes")
1300    (set_attr "arch" "*, iwmmxt2")
1301    (set_attr "wtype" "wror, wror")]
1302 )
1303
1304 (define_insn "ashr<mode>3_iwmmxt"
1305   [(set (match_operand:VSHFT                 0 "register_operand" "=y,y")
1306         (ashiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
1307                         (match_operand:SI    2 "imm_or_reg_operand" "z,i")))]
1308   "TARGET_REALLY_IWMMXT"
1309   "*
1310   switch  (which_alternative)
1311     {
1312     case 0:
1313       return \"wsra<MMX_char>g%?\\t%0, %1, %2\";
1314     case 1:
1315       return arm_output_iwmmxt_shift_immediate (\"wsra<MMX_char>\", operands, true);
1316     default:
1317       gcc_unreachable ();
1318     }
1319   "
1320   [(set_attr "predicable" "yes")
1321    (set_attr "arch" "*, iwmmxt2")
1322    (set_attr "wtype" "wsra, wsra")]
1323 )
1324
1325 (define_insn "lshr<mode>3_iwmmxt"
1326   [(set (match_operand:VSHFT                 0 "register_operand" "=y,y")
1327         (lshiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
1328                         (match_operand:SI    2 "imm_or_reg_operand" "z,i")))]
1329   "TARGET_REALLY_IWMMXT"
1330   "*
1331   switch  (which_alternative)
1332     {
1333     case 0:
1334       return \"wsrl<MMX_char>g%?\\t%0, %1, %2\";
1335     case 1:
1336       return arm_output_iwmmxt_shift_immediate (\"wsrl<MMX_char>\", operands, false);
1337     default:
1338       gcc_unreachable ();
1339     }
1340   "
1341   [(set_attr "predicable" "yes")
1342    (set_attr "arch" "*, iwmmxt2")
1343    (set_attr "wtype" "wsrl, wsrl")]
1344 )
1345
1346 (define_insn "ashl<mode>3_iwmmxt"
1347   [(set (match_operand:VSHFT               0 "register_operand" "=y,y")
1348         (ashift:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
1349                       (match_operand:SI    2 "imm_or_reg_operand" "z,i")))]
1350   "TARGET_REALLY_IWMMXT"
1351   "*
1352   switch  (which_alternative)
1353     {
1354     case 0:
1355       return \"wsll<MMX_char>g%?\\t%0, %1, %2\";
1356     case 1:
1357       return arm_output_iwmmxt_shift_immediate (\"wsll<MMX_char>\", operands, false);
1358     default:
1359       gcc_unreachable ();
1360     }
1361   "
1362   [(set_attr "predicable" "yes")
1363    (set_attr "arch" "*, iwmmxt2")
1364    (set_attr "wtype" "wsll, wsll")]
1365 )
1366
1367 (define_insn "ror<mode>3_di"
1368   [(set (match_operand:VSHFT                 0 "register_operand" "=y,y")
1369         (rotatert:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
1370                         (match_operand:DI    2 "imm_or_reg_operand" "y,i")))]
1371   "TARGET_REALLY_IWMMXT"
1372   "*
1373   switch (which_alternative)
1374     {
1375     case 0:
1376       return \"wror<MMX_char>%?\\t%0, %1, %2\";
1377     case 1:
1378       return arm_output_iwmmxt_shift_immediate (\"wror<MMX_char>\", operands, true);
1379     default:
1380       gcc_unreachable ();
1381     }
1382   "
1383   [(set_attr "predicable" "yes")
1384    (set_attr "arch" "*, iwmmxt2")
1385    (set_attr "wtype" "wror, wror")]
1386 )
1387
1388 (define_insn "ashr<mode>3_di"
1389   [(set (match_operand:VSHFT                 0 "register_operand" "=y,y")
1390         (ashiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
1391                         (match_operand:DI    2 "imm_or_reg_operand" "y,i")))]
1392   "TARGET_REALLY_IWMMXT"
1393   "*
1394   switch (which_alternative)
1395     {
1396     case 0:
1397       return \"wsra<MMX_char>%?\\t%0, %1, %2\";
1398     case 1:
1399       return arm_output_iwmmxt_shift_immediate (\"wsra<MMX_char>\", operands, true);
1400     default:
1401       gcc_unreachable ();
1402     }
1403   "
1404   [(set_attr "predicable" "yes")
1405    (set_attr "arch" "*, iwmmxt2")
1406    (set_attr "wtype" "wsra, wsra")]
1407 )
1408
1409 (define_insn "lshr<mode>3_di"
1410   [(set (match_operand:VSHFT                 0 "register_operand" "=y,y")
1411         (lshiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
1412                         (match_operand:DI    2 "register_operand" "y,i")))]
1413   "TARGET_REALLY_IWMMXT"
1414   "*
1415   switch (which_alternative)
1416     {
1417     case 0:
1418       return \"wsrl<MMX_char>%?\\t%0, %1, %2\";
1419     case 1:
1420       return arm_output_iwmmxt_shift_immediate (\"wsrl<MMX_char>\", operands, false);
1421     default:
1422       gcc_unreachable ();
1423     }
1424   "
1425   [(set_attr "predicable" "yes")
1426    (set_attr "arch" "*, iwmmxt2")
1427    (set_attr "wtype" "wsrl, wsrl")]
1428 )
1429
1430 (define_insn "ashl<mode>3_di"
1431   [(set (match_operand:VSHFT               0 "register_operand" "=y,y")
1432         (ashift:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
1433                       (match_operand:DI    2 "imm_or_reg_operand" "y,i")))]
1434   "TARGET_REALLY_IWMMXT"
1435   "*
1436   switch (which_alternative)
1437     {
1438     case 0:
1439       return \"wsll<MMX_char>%?\\t%0, %1, %2\";
1440     case 1:
1441       return arm_output_iwmmxt_shift_immediate (\"wsll<MMX_char>\", operands, false);
1442     default:
1443       gcc_unreachable ();
1444     }
1445   "
1446   [(set_attr "predicable" "yes")
1447    (set_attr "arch" "*, iwmmxt2")
1448    (set_attr "wtype" "wsll, wsll")]
1449 )
1450
1451 (define_insn "iwmmxt_wmadds"
1452   [(set (match_operand:V2SI                                        0 "register_operand" "=y")
1453         (plus:V2SI
1454           (mult:V2SI
1455             (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
1456                              (parallel [(const_int 1) (const_int 3)]))
1457             (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))
1458                              (parallel [(const_int 1) (const_int 3)])))
1459           (mult:V2SI
1460             (vec_select:V2SI (sign_extend:V4SI (match_dup 1))
1461                              (parallel [(const_int 0) (const_int 2)]))
1462             (vec_select:V2SI (sign_extend:V4SI (match_dup 2))
1463                              (parallel [(const_int 0) (const_int 2)])))))]
1464   "TARGET_REALLY_IWMMXT"
1465   "wmadds%?\\t%0, %1, %2"
1466   [(set_attr "predicable" "yes")
1467    (set_attr "wtype" "wmadd")]
1468 )
1469
1470 (define_insn "iwmmxt_wmaddu"
1471   [(set (match_operand:V2SI               0 "register_operand" "=y")
1472         (plus:V2SI
1473           (mult:V2SI
1474             (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
1475                              (parallel [(const_int 1) (const_int 3)]))
1476             (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))
1477                              (parallel [(const_int 1) (const_int 3)])))
1478           (mult:V2SI
1479             (vec_select:V2SI (zero_extend:V4SI (match_dup 1))
1480                              (parallel [(const_int 0) (const_int 2)]))
1481             (vec_select:V2SI (zero_extend:V4SI (match_dup 2))
1482                              (parallel [(const_int 0) (const_int 2)])))))]
1483   "TARGET_REALLY_IWMMXT"
1484   "wmaddu%?\\t%0, %1, %2"
1485   [(set_attr "predicable" "yes")
1486    (set_attr "wtype" "wmadd")]
1487 )
1488
1489 (define_insn "iwmmxt_tmia"
1490   [(set (match_operand:DI                     0 "register_operand" "=y")
1491         (plus:DI (match_operand:DI            1 "register_operand" "0")
1492                  (mult:DI (sign_extend:DI
1493                             (match_operand:SI 2 "register_operand" "r"))
1494                           (sign_extend:DI
1495                             (match_operand:SI 3 "register_operand" "r")))))]
1496   "TARGET_REALLY_IWMMXT"
1497   "tmia%?\\t%0, %2, %3"
1498   [(set_attr "predicable" "yes")
1499    (set_attr "wtype" "tmia")]
1500 )
1501
1502 (define_insn "iwmmxt_tmiaph"
1503   [(set (match_operand:DI                                    0 "register_operand" "=y")
1504         (plus:DI (match_operand:DI                           1 "register_operand" "0")
1505                  (plus:DI
1506                    (mult:DI (sign_extend:DI
1507                               (truncate:HI (match_operand:SI 2 "register_operand" "r")))
1508                             (sign_extend:DI
1509                               (truncate:HI (match_operand:SI 3 "register_operand" "r"))))
1510                    (mult:DI (sign_extend:DI
1511                               (truncate:HI (ashiftrt:SI (match_dup 2) (const_int 16))))
1512                             (sign_extend:DI
1513                               (truncate:HI (ashiftrt:SI (match_dup 3) (const_int 16))))))))]
1514   "TARGET_REALLY_IWMMXT"
1515   "tmiaph%?\\t%0, %2, %3"
1516   [(set_attr "predicable" "yes")
1517    (set_attr "wtype" "tmiaph")]
1518 )
1519
1520 (define_insn "iwmmxt_tmiabb"
1521   [(set (match_operand:DI                                  0 "register_operand" "=y")
1522         (plus:DI (match_operand:DI                         1 "register_operand" "0")
1523                  (mult:DI (sign_extend:DI
1524                             (truncate:HI (match_operand:SI 2 "register_operand" "r")))
1525                           (sign_extend:DI
1526                             (truncate:HI (match_operand:SI 3 "register_operand" "r"))))))]
1527   "TARGET_REALLY_IWMMXT"
1528   "tmiabb%?\\t%0, %2, %3"
1529   [(set_attr "predicable" "yes")
1530    (set_attr "wtype" "tmiaxy")]
1531 )
1532
1533 (define_insn "iwmmxt_tmiatb"
1534   [(set (match_operand:DI                         0 "register_operand" "=y")
1535         (plus:DI (match_operand:DI                1 "register_operand" "0")
1536                  (mult:DI (sign_extend:DI
1537                             (truncate:HI
1538                               (ashiftrt:SI
1539                                 (match_operand:SI 2 "register_operand" "r")
1540                                 (const_int 16))))
1541                           (sign_extend:DI
1542                             (truncate:HI
1543                               (match_operand:SI   3 "register_operand" "r"))))))]
1544   "TARGET_REALLY_IWMMXT"
1545   "tmiatb%?\\t%0, %2, %3"
1546   [(set_attr "predicable" "yes")
1547    (set_attr "wtype" "tmiaxy")]
1548 )
1549
1550 (define_insn "iwmmxt_tmiabt"
1551   [(set (match_operand:DI                         0 "register_operand" "=y")
1552         (plus:DI (match_operand:DI                1 "register_operand" "0")
1553                  (mult:DI (sign_extend:DI
1554                             (truncate:HI
1555                               (match_operand:SI   2 "register_operand" "r")))
1556                           (sign_extend:DI
1557                             (truncate:HI
1558                               (ashiftrt:SI
1559                                 (match_operand:SI 3 "register_operand" "r")
1560                                 (const_int 16)))))))]
1561   "TARGET_REALLY_IWMMXT"
1562   "tmiabt%?\\t%0, %2, %3"
1563   [(set_attr "predicable" "yes")
1564    (set_attr "wtype" "tmiaxy")]
1565 )
1566
1567 (define_insn "iwmmxt_tmiatt"
1568   [(set (match_operand:DI          0 "register_operand" "=y")
1569         (plus:DI (match_operand:DI 1 "register_operand" "0")
1570                  (mult:DI (sign_extend:DI
1571                             (truncate:HI
1572                               (ashiftrt:SI
1573                                 (match_operand:SI 2 "register_operand" "r")
1574                                 (const_int 16))))
1575                           (sign_extend:DI
1576                             (truncate:HI
1577                               (ashiftrt:SI
1578                                 (match_operand:SI 3 "register_operand" "r")
1579                                 (const_int 16)))))))]
1580   "TARGET_REALLY_IWMMXT"
1581   "tmiatt%?\\t%0, %2, %3"
1582   [(set_attr "predicable" "yes")
1583    (set_attr "wtype" "tmiaxy")]
1584 )
1585
1586 (define_insn "iwmmxt_tmovmskb"
1587   [(set (match_operand:SI               0 "register_operand" "=r")
1588         (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
1589   "TARGET_REALLY_IWMMXT"
1590   "tmovmskb%?\\t%0, %1"
1591   [(set_attr "predicable" "yes")
1592    (set_attr "wtype" "tmovmsk")]
1593 )
1594
1595 (define_insn "iwmmxt_tmovmskh"
1596   [(set (match_operand:SI               0 "register_operand" "=r")
1597         (unspec:SI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
1598   "TARGET_REALLY_IWMMXT"
1599   "tmovmskh%?\\t%0, %1"
1600   [(set_attr "predicable" "yes")
1601    (set_attr "wtype" "tmovmsk")]
1602 )
1603
1604 (define_insn "iwmmxt_tmovmskw"
1605   [(set (match_operand:SI               0 "register_operand" "=r")
1606         (unspec:SI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
1607   "TARGET_REALLY_IWMMXT"
1608   "tmovmskw%?\\t%0, %1"
1609   [(set_attr "predicable" "yes")
1610    (set_attr "wtype" "tmovmsk")]
1611 )
1612
1613 (define_insn "iwmmxt_waccb"
1614   [(set (match_operand:DI               0 "register_operand" "=y")
1615         (unspec:DI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_WACC))]
1616   "TARGET_REALLY_IWMMXT"
1617   "waccb%?\\t%0, %1"
1618   [(set_attr "predicable" "yes")
1619    (set_attr "wtype" "wacc")]
1620 )
1621
1622 (define_insn "iwmmxt_wacch"
1623   [(set (match_operand:DI               0 "register_operand" "=y")
1624         (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_WACC))]
1625   "TARGET_REALLY_IWMMXT"
1626   "wacch%?\\t%0, %1"
1627   [(set_attr "predicable" "yes")
1628    (set_attr "wtype" "wacc")]
1629 )
1630
1631 (define_insn "iwmmxt_waccw"
1632   [(set (match_operand:DI               0 "register_operand" "=y")
1633         (unspec:DI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_WACC))]
1634   "TARGET_REALLY_IWMMXT"
1635   "waccw%?\\t%0, %1"
1636   [(set_attr "predicable" "yes")
1637    (set_attr "wtype" "wacc")]
1638 )
1639
1640 ;; use unspec here to prevent 8 * imm to be optimized by cse
1641 (define_insn "iwmmxt_waligni"
1642   [(set (match_operand:V8QI                                0 "register_operand" "=y")
1643         (unspec:V8QI [(subreg:V8QI
1644                         (ashiftrt:TI
1645                           (subreg:TI (vec_concat:V16QI
1646                                        (match_operand:V8QI 1 "register_operand" "y")
1647                                        (match_operand:V8QI 2 "register_operand" "y")) 0)
1648                           (mult:SI
1649                             (match_operand:SI              3 "immediate_operand" "i")
1650                             (const_int 8))) 0)] UNSPEC_WALIGNI))]
1651   "TARGET_REALLY_IWMMXT"
1652   "waligni%?\\t%0, %1, %2, %3"
1653   [(set_attr "predicable" "yes")
1654    (set_attr "wtype" "waligni")]
1655 )
1656
1657 (define_insn "iwmmxt_walignr"
1658   [(set (match_operand:V8QI                           0 "register_operand" "=y")
1659         (subreg:V8QI (ashiftrt:TI
1660                        (subreg:TI (vec_concat:V16QI
1661                                     (match_operand:V8QI 1 "register_operand" "y")
1662                                     (match_operand:V8QI 2 "register_operand" "y")) 0)
1663                        (mult:SI
1664                          (zero_extract:SI (match_operand:SI 3 "register_operand" "z") (const_int 3) (const_int 0))
1665                          (const_int 8))) 0))]
1666   "TARGET_REALLY_IWMMXT"
1667   "walignr%U3%?\\t%0, %1, %2"
1668   [(set_attr "predicable" "yes")
1669    (set_attr "wtype" "walignr")]
1670 )
1671
1672 (define_insn "iwmmxt_walignr0"
1673   [(set (match_operand:V8QI                           0 "register_operand" "=y")
1674         (subreg:V8QI (ashiftrt:TI
1675                        (subreg:TI (vec_concat:V16QI
1676                                     (match_operand:V8QI 1 "register_operand" "y")
1677                                     (match_operand:V8QI 2 "register_operand" "y")) 0)
1678                        (mult:SI
1679                          (zero_extract:SI (reg:SI WCGR0) (const_int 3) (const_int 0))
1680                          (const_int 8))) 0))]
1681   "TARGET_REALLY_IWMMXT"
1682   "walignr0%?\\t%0, %1, %2"
1683   [(set_attr "predicable" "yes")
1684    (set_attr "wtype" "walignr")]
1685 )
1686
1687 (define_insn "iwmmxt_walignr1"
1688   [(set (match_operand:V8QI                           0 "register_operand" "=y")
1689         (subreg:V8QI (ashiftrt:TI
1690                        (subreg:TI (vec_concat:V16QI
1691                                     (match_operand:V8QI 1 "register_operand" "y")
1692                                     (match_operand:V8QI 2 "register_operand" "y")) 0)
1693                        (mult:SI
1694                          (zero_extract:SI (reg:SI WCGR1) (const_int 3) (const_int 0))
1695                          (const_int 8))) 0))]
1696   "TARGET_REALLY_IWMMXT"
1697   "walignr1%?\\t%0, %1, %2"
1698   [(set_attr "predicable" "yes")
1699    (set_attr "wtype" "walignr")]
1700 )
1701
1702 (define_insn "iwmmxt_walignr2"
1703   [(set (match_operand:V8QI                           0 "register_operand" "=y")
1704         (subreg:V8QI (ashiftrt:TI
1705                        (subreg:TI (vec_concat:V16QI
1706                                     (match_operand:V8QI 1 "register_operand" "y")
1707                                     (match_operand:V8QI 2 "register_operand" "y")) 0)
1708                        (mult:SI
1709                          (zero_extract:SI (reg:SI WCGR2) (const_int 3) (const_int 0))
1710                          (const_int 8))) 0))]
1711   "TARGET_REALLY_IWMMXT"
1712   "walignr2%?\\t%0, %1, %2"
1713   [(set_attr "predicable" "yes")
1714    (set_attr "wtype" "walignr")]
1715 )
1716
1717 (define_insn "iwmmxt_walignr3"
1718   [(set (match_operand:V8QI                           0 "register_operand" "=y")
1719         (subreg:V8QI (ashiftrt:TI
1720                        (subreg:TI (vec_concat:V16QI
1721                                     (match_operand:V8QI 1 "register_operand" "y")
1722                                     (match_operand:V8QI 2 "register_operand" "y")) 0)
1723                        (mult:SI
1724                          (zero_extract:SI (reg:SI WCGR3) (const_int 3) (const_int 0))
1725                          (const_int 8))) 0))]
1726   "TARGET_REALLY_IWMMXT"
1727   "walignr3%?\\t%0, %1, %2"
1728   [(set_attr "predicable" "yes")
1729    (set_attr "wtype" "walignr")]
1730 )
1731
1732 (define_insn "iwmmxt_wsadb"
1733   [(set (match_operand:V2SI               0 "register_operand" "=y")
1734         (unspec:V2SI [
1735                       (match_operand:V2SI 1 "register_operand" "0")
1736                       (match_operand:V8QI 2 "register_operand" "y")
1737                       (match_operand:V8QI 3 "register_operand" "y")] UNSPEC_WSAD))]
1738   "TARGET_REALLY_IWMMXT"
1739   "wsadb%?\\t%0, %2, %3"
1740   [(set_attr "predicable" "yes")
1741    (set_attr "wtype" "wsad")]
1742 )
1743
1744 (define_insn "iwmmxt_wsadh"
1745   [(set (match_operand:V2SI               0 "register_operand" "=y")
1746         (unspec:V2SI [
1747                       (match_operand:V2SI 1 "register_operand" "0")
1748                       (match_operand:V4HI 2 "register_operand" "y")
1749                       (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WSAD))]
1750   "TARGET_REALLY_IWMMXT"
1751   "wsadh%?\\t%0, %2, %3"
1752   [(set_attr "predicable" "yes")
1753    (set_attr "wtype" "wsad")]
1754 )
1755
1756 (define_insn "iwmmxt_wsadbz"
1757   [(set (match_operand:V2SI               0 "register_operand" "=y")
1758         (unspec:V2SI [(match_operand:V8QI 1 "register_operand" "y")
1759                       (match_operand:V8QI 2 "register_operand" "y")] UNSPEC_WSADZ))]
1760   "TARGET_REALLY_IWMMXT"
1761   "wsadbz%?\\t%0, %1, %2"
1762   [(set_attr "predicable" "yes")
1763    (set_attr "wtype" "wsad")]
1764 )
1765
1766 (define_insn "iwmmxt_wsadhz"
1767   [(set (match_operand:V2SI               0 "register_operand" "=y")
1768         (unspec:V2SI [(match_operand:V4HI 1 "register_operand" "y")
1769                       (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WSADZ))]
1770   "TARGET_REALLY_IWMMXT"
1771   "wsadhz%?\\t%0, %1, %2"
1772   [(set_attr "predicable" "yes")
1773    (set_attr "wtype" "wsad")]
1774 )
1775
1776 (include "iwmmxt2.md")