gcc/config/arm/iwmmxt.md

   1 ;; Patterns for the Intel Wireless MMX technology architecture.
   2 ;; Copyright (C) 2003, 2004 Free Software Foundation, Inc.
   3 ;; Contributed by Red Hat.
   4
   5 ;; This file is part of GCC.
   6
   7 ;; GCC is free software; you can redistribute it and/or modify it under
   8 ;; the terms of the GNU General Public License as published by the Free
   9 ;; Software Foundation; either version 2, or (at your option) any later
  10 ;; version.
  11
  12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ;; License for more details.
  16
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING.  If not, write to
  19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
  20 ;; Boston, MA 02111-1307, USA.
  21
  22 (define_insn "iwmmxt_iordi3"
  23   [(set (match_operand:DI         0 "register_operand" "=y,?&r,?&r")
  24         (ior:DI (match_operand:DI 1 "register_operand" "%y,0,r")
  25                 (match_operand:DI 2 "register_operand"  "y,r,r")))]
  26   "TARGET_REALLY_IWMMXT"
  27   "@
  28    wor%?\\t%0, %1, %2
  29    #
  30    #"
  31   [(set_attr "predicable" "yes")
  32    (set_attr "length" "4,8,8")])
  33
  34 (define_insn "iwmmxt_xordi3"
  35   [(set (match_operand:DI         0 "register_operand" "=y,?&r,?&r")
  36         (xor:DI (match_operand:DI 1 "register_operand" "%y,0,r")
  37                 (match_operand:DI 2 "register_operand"  "y,r,r")))]
  38   "TARGET_REALLY_IWMMXT"
  39   "@
  40    wxor%?\\t%0, %1, %2
  41    #
  42    #"
  43   [(set_attr "predicable" "yes")
  44    (set_attr "length" "4,8,8")])
  45
  46 (define_insn "iwmmxt_anddi3"
  47   [(set (match_operand:DI         0 "register_operand" "=y,?&r,?&r")
  48         (and:DI (match_operand:DI 1 "register_operand" "%y,0,r")
  49                 (match_operand:DI 2 "register_operand"  "y,r,r")))]
  50   "TARGET_REALLY_IWMMXT"
  51   "@
  52    wand%?\\t%0, %1, %2
  53    #
  54    #"
  55   [(set_attr "predicable" "yes")
  56    (set_attr "length" "4,8,8")])
  57
  58 (define_insn "iwmmxt_nanddi3"
  59   [(set (match_operand:DI                 0 "register_operand" "=y")
  60         (and:DI (match_operand:DI         1 "register_operand"  "y")
  61                 (not:DI (match_operand:DI 2 "register_operand"  "y"))))]
  62   "TARGET_REALLY_IWMMXT"
  63   "wandn%?\\t%0, %1, %2"
  64   [(set_attr "predicable" "yes")])
  65
  66 (define_insn "*iwmmxt_arm_movdi"
  67   [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, o<>,y,y,yr,y,yrm")
  68         (match_operand:DI 1 "di_operand"              "rIK,mi,r  ,y,yr,y,yrm,y"))]
  69   "TARGET_REALLY_IWMMXT"
  70   "*
  71 {
  72   switch (which_alternative)
  73     {
  74     default:
  75       return output_move_double (operands);
  76     case 3:
  77       return \"wmov%?\\t%0,%1\";
  78     case 4:
  79       return \"tmcrr%?\\t%0,%Q1,%R1\";
  80     case 5:
  81       return \"tmrrc%?\\t%Q0,%R0,%1\";
  82     case 6:
  83       return \"wldrd%?\\t%0,%1\";
  84     case 7:
  85       return \"wstrd%?\\t%1,%0\";
  86     }
  87 }"
  88   [(set_attr "length"         "8,8,8,4,4,4,4,4")
  89    (set_attr "type"           "*,load1,store2,*,*,*,*,*")
  90    (set_attr "pool_range"     "*,1020,*,*,*,*,*,*")
  91    (set_attr "neg_pool_range" "*,1012,*,*,*,*,*,*")]
  92 )
  93
  94 (define_insn "*iwmmxt_movsi_insn"
  95   [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m,z,r,?z,m,z")
  96         (match_operand:SI 1 "general_operand"      "rI,K,mi,r,r,z,m,z,z"))]
  97   "TARGET_REALLY_IWMMXT
  98    && (   register_operand (operands[0], SImode)
  99        || register_operand (operands[1], SImode))"
 100   "*
 101    switch (which_alternative)
 102    {
 103    case 0: return \"mov\\t%0, %1\";
 104    case 1: return \"mvn\\t%0, #%B1\";
 105    case 2: return \"ldr\\t%0, %1\";
 106    case 3: return \"str\\t%1, %0\";
 107    case 4: return \"tmcr\\t%0, %1\";
 108    case 5: return \"tmrc\\t%0, %1\";
 109    case 6: return arm_output_load_gr (operands);
 110    case 7: return \"wstrw\\t%1, %0\";
 111    default:return \"wstrw\\t%1, [sp, #-4]!\;wldrw\\t%0, [sp], #4\\t@move CG reg\";
 112   }"
 113   [(set_attr "type"           "*,*,load1,store1,*,*,load1,store1,*")
 114    (set_attr "length"         "*,*,*,        *,*,*,  16,     *,8")
 115    (set_attr "pool_range"     "*,*,4096,     *,*,*,1024,     *,*")
 116    (set_attr "neg_pool_range" "*,*,4084,     *,*,*,   *,  1012,*")
 117    ;; Note - the "predicable" attribute is not allowed to have alternatives.
 118    ;; Since the wSTRw wCx instruction is not predicable, we cannot support
 119    ;; predicating any of the alternatives in this template.  Instead,
 120    ;; we do the predication ourselves, in cond_iwmmxt_movsi_insn.
 121    (set_attr "predicable"     "no")
 122    ;; Also - we have to pretend that these insns clobber the condition code
 123    ;; bits as otherwise arm_final_prescan_insn() will try to conditionalize
 124    ;; them.
 125    (set_attr "conds" "clob")]
 126 )
 127
 128 ;; Because iwmmxt_movsi_insn is not predicable, we provide the
 129 ;; cond_exec version explicitly, with appropriate constraints.
 130
 131 (define_insn "*cond_iwmmxt_movsi_insn"
 132   [(cond_exec
 133      (match_operator 2 "arm_comparison_operator"
 134       [(match_operand 3 "cc_register" "")
 135       (const_int 0)])
 136      (set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m,z,r")
 137           (match_operand:SI 1 "general_operand"      "rI,K,mi,r,r,z")))]
 138   "TARGET_REALLY_IWMMXT
 139    && (   register_operand (operands[0], SImode)
 140        || register_operand (operands[1], SImode))"
 141   "*
 142    switch (which_alternative)
 143    {
 144    case 0: return \"mov%?\\t%0, %1\";
 145    case 1: return \"mvn%?\\t%0, #%B1\";
 146    case 2: return \"ldr%?\\t%0, %1\";
 147    case 3: return \"str%?\\t%1, %0\";
 148    case 4: return \"tmcr%?\\t%0, %1\";
 149    default: return \"tmrc%?\\t%0, %1\";
 150   }"
 151   [(set_attr "type"           "*,*,load1,store1,*,*")
 152    (set_attr "pool_range"     "*,*,4096,     *,*,*")
 153    (set_attr "neg_pool_range" "*,*,4084,     *,*,*")]
 154 )
 155
 156 (define_insn "movv8qi_internal"
 157   [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r")
 158         (match_operand:V8QI 1 "general_operand"       "y,y,m,y,r,i"))]
 159   "TARGET_REALLY_IWMMXT"
 160   "*
 161    switch (which_alternative)
 162    {
 163    case 0: return \"wmov%?\\t%0, %1\";
 164    case 1: return \"wstrd%?\\t%1, %0\";
 165    case 2: return \"wldrd%?\\t%0, %1\";
 166    case 3: return \"tmrrc%?\\t%Q0, %R0, %1\";
 167    case 4: return \"tmcrr%?\\t%0, %Q1, %R1\";
 168    default: return output_move_double (operands);
 169    }"
 170   [(set_attr "predicable" "yes")
 171    (set_attr "length"         "4,     4,   4,4,4,   8")
 172    (set_attr "type"           "*,store1,load1,*,*,load1")
 173    (set_attr "pool_range"     "*,     *, 256,*,*, 256")
 174    (set_attr "neg_pool_range" "*,     *, 244,*,*, 244")])
 175
 176 (define_insn "movv4hi_internal"
 177   [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r")
 178         (match_operand:V4HI 1 "general_operand"       "y,y,m,y,r,i"))]
 179   "TARGET_REALLY_IWMMXT"
 180   "*
 181    switch (which_alternative)
 182    {
 183    case 0: return \"wmov%?\\t%0, %1\";
 184    case 1: return \"wstrd%?\\t%1, %0\";
 185    case 2: return \"wldrd%?\\t%0, %1\";
 186    case 3: return \"tmrrc%?\\t%Q0, %R0, %1\";
 187    case 4: return \"tmcrr%?\\t%0, %Q1, %R1\";
 188    default: return output_move_double (operands);
 189    }"
 190   [(set_attr "predicable" "yes")
 191    (set_attr "length"         "4,     4,   4,4,4,   8")
 192    (set_attr "type"           "*,store1,load1,*,*,load1")
 193    (set_attr "pool_range"     "*,     *, 256,*,*, 256")
 194    (set_attr "neg_pool_range" "*,     *, 244,*,*, 244")])
 195
 196 (define_insn "movv2si_internal"
 197   [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r")
 198         (match_operand:V2SI 1 "general_operand"       "y,y,m,y,r,i"))]
 199   "TARGET_REALLY_IWMMXT"
 200   "*
 201    switch (which_alternative)
 202    {
 203    case 0: return \"wmov%?\\t%0, %1\";
 204    case 1: return \"wstrd%?\\t%1, %0\";
 205    case 2: return \"wldrd%?\\t%0, %1\";
 206    case 3: return \"tmrrc%?\\t%Q0, %R0, %1\";
 207    case 4: return \"tmcrr%?\\t%0, %Q1, %R1\";
 208    default: return output_move_double (operands);
 209    }"
 210   [(set_attr "predicable" "yes")
 211    (set_attr "length"         "4,     4,   4,4,4,  24")
 212    (set_attr "type"           "*,store1,load1,*,*,load1")
 213    (set_attr "pool_range"     "*,     *, 256,*,*, 256")
 214    (set_attr "neg_pool_range" "*,     *, 244,*,*, 244")])
 215
 216 ;; This pattern should not be needed.  It is to match a
 217 ;; wierd case generated by GCC when no optimizations are
 218 ;; enabled.  (Try compiling gcc/testsuite/gcc.c-torture/
 219 ;; compile/simd-5.c at -O0).  The mode for operands[1] is
 220 ;; deliberately omitted.
 221 (define_insn "movv2si_internal_2"
 222   [(set (match_operand:V2SI 0 "nonimmediate_operand" "=?r")
 223         (match_operand      1 "immediate_operand"      "i"))]
 224   "TARGET_REALLY_IWMMXT"
 225   "* return output_move_double (operands);"
 226   [(set_attr "predicable"     "yes")
 227    (set_attr "length"         "8")
 228    (set_attr "type"           "load1")
 229    (set_attr "pool_range"     "256")
 230    (set_attr "neg_pool_range" "244")])
 231
 232 ;; Vector add/subtract
 233
 234 (define_insn "addv8qi3"
 235   [(set (match_operand:V8QI            0 "register_operand" "=y")
 236         (plus:V8QI (match_operand:V8QI 1 "register_operand"  "y")
 237                    (match_operand:V8QI 2 "register_operand"  "y")))]
 238   "TARGET_REALLY_IWMMXT"
 239   "waddb%?\\t%0, %1, %2"
 240   [(set_attr "predicable" "yes")])
 241
 242 (define_insn "addv4hi3"
 243   [(set (match_operand:V4HI            0 "register_operand" "=y")
 244         (plus:V4HI (match_operand:V4HI 1 "register_operand"  "y")
 245                    (match_operand:V4HI 2 "register_operand"  "y")))]
 246   "TARGET_REALLY_IWMMXT"
 247   "waddh%?\\t%0, %1, %2"
 248   [(set_attr "predicable" "yes")])
 249
 250 (define_insn "addv2si3"
 251   [(set (match_operand:V2SI            0 "register_operand" "=y")
 252         (plus:V2SI (match_operand:V2SI 1 "register_operand"  "y")
 253                    (match_operand:V2SI 2 "register_operand"  "y")))]
 254   "TARGET_REALLY_IWMMXT"
 255   "waddw%?\\t%0, %1, %2"
 256   [(set_attr "predicable" "yes")])
 257
 258 (define_insn "ssaddv8qi3"
 259   [(set (match_operand:V8QI               0 "register_operand" "=y")
 260         (ss_plus:V8QI (match_operand:V8QI 1 "register_operand"  "y")
 261                       (match_operand:V8QI 2 "register_operand"  "y")))]
 262   "TARGET_REALLY_IWMMXT"
 263   "waddbss%?\\t%0, %1, %2"
 264   [(set_attr "predicable" "yes")])
 265
 266 (define_insn "ssaddv4hi3"
 267   [(set (match_operand:V4HI               0 "register_operand" "=y")
 268         (ss_plus:V4HI (match_operand:V4HI 1 "register_operand"  "y")
 269                       (match_operand:V4HI 2 "register_operand"  "y")))]
 270   "TARGET_REALLY_IWMMXT"
 271   "waddhss%?\\t%0, %1, %2"
 272   [(set_attr "predicable" "yes")])
 273
 274 (define_insn "ssaddv2si3"
 275   [(set (match_operand:V2SI               0 "register_operand" "=y")
 276         (ss_plus:V2SI (match_operand:V2SI 1 "register_operand"  "y")
 277                       (match_operand:V2SI 2 "register_operand"  "y")))]
 278   "TARGET_REALLY_IWMMXT"
 279   "waddwss%?\\t%0, %1, %2"
 280   [(set_attr "predicable" "yes")])
 281
 282 (define_insn "usaddv8qi3"
 283   [(set (match_operand:V8QI               0 "register_operand" "=y")
 284         (us_plus:V8QI (match_operand:V8QI 1 "register_operand"  "y")
 285                       (match_operand:V8QI 2 "register_operand"  "y")))]
 286   "TARGET_REALLY_IWMMXT"
 287   "waddbus%?\\t%0, %1, %2"
 288   [(set_attr "predicable" "yes")])
 289
 290 (define_insn "usaddv4hi3"
 291   [(set (match_operand:V4HI               0 "register_operand" "=y")
 292         (us_plus:V4HI (match_operand:V4HI 1 "register_operand"  "y")
 293                       (match_operand:V4HI 2 "register_operand"  "y")))]
 294   "TARGET_REALLY_IWMMXT"
 295   "waddhus%?\\t%0, %1, %2"
 296   [(set_attr "predicable" "yes")])
 297
 298 (define_insn "usaddv2si3"
 299   [(set (match_operand:V2SI               0 "register_operand" "=y")
 300         (us_plus:V2SI (match_operand:V2SI 1 "register_operand"  "y")
 301                       (match_operand:V2SI 2 "register_operand"  "y")))]
 302   "TARGET_REALLY_IWMMXT"
 303   "waddwus%?\\t%0, %1, %2"
 304   [(set_attr "predicable" "yes")])
 305
 306 (define_insn "subv8qi3"
 307   [(set (match_operand:V8QI             0 "register_operand" "=y")
 308         (minus:V8QI (match_operand:V8QI 1 "register_operand"  "y")
 309                     (match_operand:V8QI 2 "register_operand"  "y")))]
 310   "TARGET_REALLY_IWMMXT"
 311   "wsubb%?\\t%0, %1, %2"
 312   [(set_attr "predicable" "yes")])
 313
 314 (define_insn "subv4hi3"
 315   [(set (match_operand:V4HI             0 "register_operand" "=y")
 316         (minus:V4HI (match_operand:V4HI 1 "register_operand"  "y")
 317                     (match_operand:V4HI 2 "register_operand"  "y")))]
 318   "TARGET_REALLY_IWMMXT"
 319   "wsubh%?\\t%0, %1, %2"
 320   [(set_attr "predicable" "yes")])
 321
 322 (define_insn "subv2si3"
 323   [(set (match_operand:V2SI             0 "register_operand" "=y")
 324         (minus:V2SI (match_operand:V2SI 1 "register_operand"  "y")
 325                     (match_operand:V2SI 2 "register_operand"  "y")))]
 326   "TARGET_REALLY_IWMMXT"
 327   "wsubw%?\\t%0, %1, %2"
 328   [(set_attr "predicable" "yes")])
 329
 330 (define_insn "sssubv8qi3"
 331   [(set (match_operand:V8QI                0 "register_operand" "=y")
 332         (ss_minus:V8QI (match_operand:V8QI 1 "register_operand"  "y")
 333                        (match_operand:V8QI 2 "register_operand"  "y")))]
 334   "TARGET_REALLY_IWMMXT"
 335   "wsubbss%?\\t%0, %1, %2"
 336   [(set_attr "predicable" "yes")])
 337
 338 (define_insn "sssubv4hi3"
 339   [(set (match_operand:V4HI                0 "register_operand" "=y")
 340         (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "y")
 341                        (match_operand:V4HI 2 "register_operand" "y")))]
 342   "TARGET_REALLY_IWMMXT"
 343   "wsubhss%?\\t%0, %1, %2"
 344   [(set_attr "predicable" "yes")])
 345
 346 (define_insn "sssubv2si3"
 347   [(set (match_operand:V2SI                0 "register_operand" "=y")
 348         (ss_minus:V2SI (match_operand:V2SI 1 "register_operand" "y")
 349                        (match_operand:V2SI 2 "register_operand" "y")))]
 350   "TARGET_REALLY_IWMMXT"
 351   "wsubwss%?\\t%0, %1, %2"
 352   [(set_attr "predicable" "yes")])
 353
 354 (define_insn "ussubv8qi3"
 355   [(set (match_operand:V8QI                0 "register_operand" "=y")
 356         (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "y")
 357                        (match_operand:V8QI 2 "register_operand" "y")))]
 358   "TARGET_REALLY_IWMMXT"
 359   "wsubbus%?\\t%0, %1, %2"
 360   [(set_attr "predicable" "yes")])
 361
 362 (define_insn "ussubv4hi3"
 363   [(set (match_operand:V4HI                0 "register_operand" "=y")
 364         (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "y")
 365                        (match_operand:V4HI 2 "register_operand" "y")))]
 366   "TARGET_REALLY_IWMMXT"
 367   "wsubhus%?\\t%0, %1, %2"
 368   [(set_attr "predicable" "yes")])
 369
 370 (define_insn "ussubv2si3"
 371   [(set (match_operand:V2SI                0 "register_operand" "=y")
 372         (us_minus:V2SI (match_operand:V2SI 1 "register_operand" "y")
 373                        (match_operand:V2SI 2 "register_operand" "y")))]
 374   "TARGET_REALLY_IWMMXT"
 375   "wsubwus%?\\t%0, %1, %2"
 376   [(set_attr "predicable" "yes")])
 377
 378 (define_insn "mulv4hi3"
 379   [(set (match_operand:V4HI            0 "register_operand" "=y")
 380         (mult:V4HI (match_operand:V4HI 1 "register_operand" "y")
 381                    (match_operand:V4HI 2 "register_operand" "y")))]
 382   "TARGET_REALLY_IWMMXT"
 383   "wmulul%?\\t%0, %1, %2"
 384   [(set_attr "predicable" "yes")])
 385
 386 (define_insn "smulv4hi3_highpart"
 387   [(set (match_operand:V4HI                                0 "register_operand" "=y")
 388         (truncate:V4HI
 389          (lshiftrt:V4SI
 390           (mult:V4SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
 391                      (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
 392           (const_int 16))))]
 393   "TARGET_REALLY_IWMMXT"
 394   "wmulsm%?\\t%0, %1, %2"
 395   [(set_attr "predicable" "yes")])
 396
 397 (define_insn "umulv4hi3_highpart"
 398   [(set (match_operand:V4HI                                0 "register_operand" "=y")
 399         (truncate:V4HI
 400          (lshiftrt:V4SI
 401           (mult:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
 402                      (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
 403           (const_int 16))))]
 404   "TARGET_REALLY_IWMMXT"
 405   "wmulum%?\\t%0, %1, %2"
 406   [(set_attr "predicable" "yes")])
 407
 408 (define_insn "iwmmxt_wmacs"
 409   [(set (match_operand:DI               0 "register_operand" "=y")
 410         (unspec:DI [(match_operand:DI   1 "register_operand" "0")
 411                     (match_operand:V4HI 2 "register_operand" "y")
 412                     (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACS))]
 413   "TARGET_REALLY_IWMMXT"
 414   "wmacs%?\\t%0, %2, %3"
 415   [(set_attr "predicable" "yes")])
 416
 417 (define_insn "iwmmxt_wmacsz"
 418   [(set (match_operand:DI               0 "register_operand" "=y")
 419         (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")
 420                     (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACSZ))]
 421   "TARGET_REALLY_IWMMXT"
 422   "wmacsz%?\\t%0, %1, %2"
 423   [(set_attr "predicable" "yes")])
 424
 425 (define_insn "iwmmxt_wmacu"
 426   [(set (match_operand:DI               0 "register_operand" "=y")
 427         (unspec:DI [(match_operand:DI   1 "register_operand" "0")
 428                     (match_operand:V4HI 2 "register_operand" "y")
 429                     (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACU))]
 430   "TARGET_REALLY_IWMMXT"
 431   "wmacu%?\\t%0, %2, %3"
 432   [(set_attr "predicable" "yes")])
 433
 434 (define_insn "iwmmxt_wmacuz"
 435   [(set (match_operand:DI               0 "register_operand" "=y")
 436         (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")
 437                     (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACUZ))]
 438   "TARGET_REALLY_IWMMXT"
 439   "wmacuz%?\\t%0, %1, %2"
 440   [(set_attr "predicable" "yes")])
 441
 442 ;; Same as xordi3, but don't show input operands so that we don't think
 443 ;; they are live.
 444 (define_insn "iwmmxt_clrdi"
 445   [(set (match_operand:DI 0 "register_operand" "=y")
 446         (unspec:DI [(const_int 0)] UNSPEC_CLRDI))]
 447   "TARGET_REALLY_IWMMXT"
 448   "wxor%?\\t%0, %0, %0"
 449   [(set_attr "predicable" "yes")])
 450
 451 ;; Seems like cse likes to generate these, so we have to support them.
 452
 453 (define_insn "*iwmmxt_clrv8qi"
 454   [(set (match_operand:V8QI 0 "register_operand" "=y")
 455         (const_vector:V8QI [(const_int 0) (const_int 0)
 456                             (const_int 0) (const_int 0)
 457                             (const_int 0) (const_int 0)
 458                             (const_int 0) (const_int 0)]))]
 459   "TARGET_REALLY_IWMMXT"
 460   "wxor%?\\t%0, %0, %0"
 461   [(set_attr "predicable" "yes")])
 462
 463 (define_insn "*iwmmxt_clrv4hi"
 464   [(set (match_operand:V4HI 0 "register_operand" "=y")
 465         (const_vector:V4HI [(const_int 0) (const_int 0)
 466                             (const_int 0) (const_int 0)]))]
 467   "TARGET_REALLY_IWMMXT"
 468   "wxor%?\\t%0, %0, %0"
 469   [(set_attr "predicable" "yes")])
 470
 471 (define_insn "*iwmmxt_clrv2si"
 472   [(set (match_operand:V2SI 0 "register_operand" "=y")
 473         (const_vector:V2SI [(const_int 0) (const_int 0)]))]
 474   "TARGET_REALLY_IWMMXT"
 475   "wxor%?\\t%0, %0, %0"
 476   [(set_attr "predicable" "yes")])
 477
 478 ;; Unsigned averages/sum of absolute differences
 479
 480 (define_insn "iwmmxt_uavgrndv8qi3"
 481   [(set (match_operand:V8QI              0 "register_operand" "=y")
 482         (ashiftrt:V8QI
 483          (plus:V8QI (plus:V8QI
 484                      (match_operand:V8QI 1 "register_operand" "y")
 485                      (match_operand:V8QI 2 "register_operand" "y"))
 486                     (const_vector:V8QI [(const_int 1)
 487                                         (const_int 1)
 488                                         (const_int 1)
 489                                         (const_int 1)
 490                                         (const_int 1)
 491                                         (const_int 1)
 492                                         (const_int 1)
 493                                         (const_int 1)]))
 494          (const_int 1)))]
 495   "TARGET_REALLY_IWMMXT"
 496   "wavg2br%?\\t%0, %1, %2"
 497   [(set_attr "predicable" "yes")])
 498
 499 (define_insn "iwmmxt_uavgrndv4hi3"
 500   [(set (match_operand:V4HI              0 "register_operand" "=y")
 501         (ashiftrt:V4HI
 502          (plus:V4HI (plus:V4HI
 503                      (match_operand:V4HI 1 "register_operand" "y")
 504                      (match_operand:V4HI 2 "register_operand" "y"))
 505                     (const_vector:V4HI [(const_int 1)
 506                                         (const_int 1)
 507                                         (const_int 1)
 508                                         (const_int 1)]))
 509          (const_int 1)))]
 510   "TARGET_REALLY_IWMMXT"
 511   "wavg2hr%?\\t%0, %1, %2"
 512   [(set_attr "predicable" "yes")])
 513
 514
 515 (define_insn "iwmmxt_uavgv8qi3"
 516   [(set (match_operand:V8QI                 0 "register_operand" "=y")
 517         (ashiftrt:V8QI (plus:V8QI
 518                         (match_operand:V8QI 1 "register_operand" "y")
 519                         (match_operand:V8QI 2 "register_operand" "y"))
 520                        (const_int 1)))]
 521   "TARGET_REALLY_IWMMXT"
 522   "wavg2b%?\\t%0, %1, %2"
 523   [(set_attr "predicable" "yes")])
 524
 525 (define_insn "iwmmxt_uavgv4hi3"
 526   [(set (match_operand:V4HI                 0 "register_operand" "=y")
 527         (ashiftrt:V4HI (plus:V4HI
 528                         (match_operand:V4HI 1 "register_operand" "y")
 529                         (match_operand:V4HI 2 "register_operand" "y"))
 530                        (const_int 1)))]
 531   "TARGET_REALLY_IWMMXT"
 532   "wavg2h%?\\t%0, %1, %2"
 533   [(set_attr "predicable" "yes")])
 534
 535 (define_insn "iwmmxt_psadbw"
 536   [(set (match_operand:V8QI                       0 "register_operand" "=y")
 537         (abs:V8QI (minus:V8QI (match_operand:V8QI 1 "register_operand" "y")
 538                               (match_operand:V8QI 2 "register_operand" "y"))))]
 539   "TARGET_REALLY_IWMMXT"
 540   "psadbw%?\\t%0, %1, %2"
 541   [(set_attr "predicable" "yes")])
 542
 543
 544 ;; Insert/extract/shuffle
 545
 546 (define_insn "iwmmxt_tinsrb"
 547   [(set (match_operand:V8QI                             0 "register_operand"    "=y")
 548         (vec_merge:V8QI (match_operand:V8QI             1 "register_operand"     "0")
 549                         (vec_duplicate:V8QI
 550                          (truncate:QI (match_operand:SI 2 "nonimmediate_operand" "r")))
 551                         (match_operand:SI               3 "immediate_operand"    "i")))]
 552   "TARGET_REALLY_IWMMXT"
 553   "tinsrb%?\\t%0, %2, %3"
 554   [(set_attr "predicable" "yes")])
 555
 556 (define_insn "iwmmxt_tinsrh"
 557   [(set (match_operand:V4HI                             0 "register_operand"    "=y")
 558         (vec_merge:V4HI (match_operand:V4HI             1 "register_operand"     "0")
 559                         (vec_duplicate:V4HI
 560                          (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "r")))
 561                         (match_operand:SI               3 "immediate_operand"    "i")))]
 562   "TARGET_REALLY_IWMMXT"
 563   "tinsrh%?\\t%0, %2, %3"
 564   [(set_attr "predicable" "yes")])
 565
 566 (define_insn "iwmmxt_tinsrw"
 567   [(set (match_operand:V2SI                 0 "register_operand"    "=y")
 568         (vec_merge:V2SI (match_operand:V2SI 1 "register_operand"     "0")
 569                         (vec_duplicate:V2SI
 570                          (match_operand:SI  2 "nonimmediate_operand" "r"))
 571                         (match_operand:SI   3 "immediate_operand"    "i")))]
 572   "TARGET_REALLY_IWMMXT"
 573   "tinsrw%?\\t%0, %2, %3"
 574   [(set_attr "predicable" "yes")])
 575
 576 (define_insn "iwmmxt_textrmub"
 577   [(set (match_operand:SI                                  0 "register_operand" "=r")
 578         (zero_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y")
 579                                        (parallel
 580                                         [(match_operand:SI 2 "immediate_operand" "i")]))))]
 581   "TARGET_REALLY_IWMMXT"
 582   "textrmub%?\\t%0, %1, %2"
 583   [(set_attr "predicable" "yes")])
 584
 585 (define_insn "iwmmxt_textrmsb"
 586   [(set (match_operand:SI                                  0 "register_operand" "=r")
 587         (sign_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y")
 588                                        (parallel
 589                                         [(match_operand:SI 2 "immediate_operand" "i")]))))]
 590   "TARGET_REALLY_IWMMXT"
 591   "textrmsb%?\\t%0, %1, %2"
 592   [(set_attr "predicable" "yes")])
 593
 594 (define_insn "iwmmxt_textrmuh"
 595   [(set (match_operand:SI                                  0 "register_operand" "=r")
 596         (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
 597                                        (parallel
 598                                         [(match_operand:SI 2 "immediate_operand" "i")]))))]
 599   "TARGET_REALLY_IWMMXT"
 600   "textrmuh%?\\t%0, %1, %2"
 601   [(set_attr "predicable" "yes")])
 602
 603 (define_insn "iwmmxt_textrmsh"
 604   [(set (match_operand:SI                                  0 "register_operand" "=r")
 605         (sign_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
 606                                        (parallel
 607                                         [(match_operand:SI 2 "immediate_operand" "i")]))))]
 608   "TARGET_REALLY_IWMMXT"
 609   "textrmsh%?\\t%0, %1, %2"
 610   [(set_attr "predicable" "yes")])
 611
 612 ;; There are signed/unsigned variants of this instruction, but they are
 613 ;; pointless.
 614 (define_insn "iwmmxt_textrmw"
 615   [(set (match_operand:SI                           0 "register_operand" "=r")
 616         (vec_select:SI (match_operand:V2SI          1 "register_operand" "y")
 617                        (parallel [(match_operand:SI 2 "immediate_operand" "i")])))]
 618   "TARGET_REALLY_IWMMXT"
 619   "textrmsw%?\\t%0, %1, %2"
 620   [(set_attr "predicable" "yes")])
 621
 622 (define_insn "iwmmxt_wshufh"
 623   [(set (match_operand:V4HI               0 "register_operand" "=y")
 624         (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
 625                       (match_operand:SI   2 "immediate_operand" "i")] UNSPEC_WSHUFH))]
 626   "TARGET_REALLY_IWMMXT"
 627   "wshufh%?\\t%0, %1, %2"
 628   [(set_attr "predicable" "yes")])
 629
 630 ;; Mask-generating comparisons
 631 ;;
 632 ;; Note - you cannot use patterns like these here:
 633 ;;
 634 ;;   (set:<vector> (match:<vector>) (<comparator>:<vector> (match:<vector>) (match:<vector>)))
 635 ;;
 636 ;; Because GCC will assume that the truth value (1 or 0) is installed
 637 ;; into the entire destination vector, (with the '1' going into the least
 638 ;; significant element of the vector).  This is not how these instructions
 639 ;; behave.
 640 ;;
 641 ;; Unfortunately the current patterns are illegal.  They are SET insns
 642 ;; without a SET in them.  They work in most cases for ordinary code
 643 ;; generation, but there are circumstances where they can cause gcc to fail.
 644 ;; XXX - FIXME.
 645
 646 (define_insn "eqv8qi3"
 647   [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y")
 648                      (match_operand:V8QI 1 "register_operand"  "y")
 649                      (match_operand:V8QI 2 "register_operand"  "y")]
 650                     VUNSPEC_WCMP_EQ)]
 651   "TARGET_REALLY_IWMMXT"
 652   "wcmpeqb%?\\t%0, %1, %2"
 653   [(set_attr "predicable" "yes")])
 654
 655 (define_insn "eqv4hi3"
 656   [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y")
 657                      (match_operand:V4HI 1 "register_operand"  "y")
 658                      (match_operand:V4HI 2 "register_operand"  "y")]
 659                     VUNSPEC_WCMP_EQ)]
 660   "TARGET_REALLY_IWMMXT"
 661   "wcmpeqh%?\\t%0, %1, %2"
 662   [(set_attr "predicable" "yes")])
 663
 664 (define_insn "eqv2si3"
 665   [(unspec_volatile:V2SI [(match_operand:V2SI 0 "register_operand" "=y")
 666                           (match_operand:V2SI 1 "register_operand"  "y")
 667                           (match_operand:V2SI 2 "register_operand"  "y")]
 668                          VUNSPEC_WCMP_EQ)]
 669   "TARGET_REALLY_IWMMXT"
 670   "wcmpeqw%?\\t%0, %1, %2"
 671   [(set_attr "predicable" "yes")])
 672
 673 (define_insn "gtuv8qi3"
 674   [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y")
 675                      (match_operand:V8QI 1 "register_operand"  "y")
 676                      (match_operand:V8QI 2 "register_operand"  "y")]
 677                     VUNSPEC_WCMP_GTU)]
 678   "TARGET_REALLY_IWMMXT"
 679   "wcmpgtub%?\\t%0, %1, %2"
 680   [(set_attr "predicable" "yes")])
 681
 682 (define_insn "gtuv4hi3"
 683   [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y")
 684                      (match_operand:V4HI 1 "register_operand"  "y")
 685                      (match_operand:V4HI 2 "register_operand"  "y")]
 686                     VUNSPEC_WCMP_GTU)]
 687   "TARGET_REALLY_IWMMXT"
 688   "wcmpgtuh%?\\t%0, %1, %2"
 689   [(set_attr "predicable" "yes")])
 690
 691 (define_insn "gtuv2si3"
 692   [(unspec_volatile [(match_operand:V2SI 0 "register_operand" "=y")
 693                      (match_operand:V2SI 1 "register_operand"  "y")
 694                      (match_operand:V2SI 2 "register_operand"  "y")]
 695                     VUNSPEC_WCMP_GTU)]
 696   "TARGET_REALLY_IWMMXT"
 697   "wcmpgtuw%?\\t%0, %1, %2"
 698   [(set_attr "predicable" "yes")])
 699
 700 (define_insn "gtv8qi3"
 701   [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y")
 702                      (match_operand:V8QI 1 "register_operand"  "y")
 703                      (match_operand:V8QI 2 "register_operand"  "y")]
 704                     VUNSPEC_WCMP_GT)]
 705   "TARGET_REALLY_IWMMXT"
 706   "wcmpgtsb%?\\t%0, %1, %2"
 707   [(set_attr "predicable" "yes")])
 708
 709 (define_insn "gtv4hi3"
 710   [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y")
 711                      (match_operand:V4HI 1 "register_operand"  "y")
 712                      (match_operand:V4HI 2 "register_operand"  "y")]
 713                     VUNSPEC_WCMP_GT)]
 714   "TARGET_REALLY_IWMMXT"
 715   "wcmpgtsh%?\\t%0, %1, %2"
 716   [(set_attr "predicable" "yes")])
 717
 718 (define_insn "gtv2si3"
 719   [(unspec_volatile [(match_operand:V2SI 0 "register_operand" "=y")
 720                      (match_operand:V2SI 1 "register_operand"  "y")
 721                      (match_operand:V2SI 2 "register_operand"  "y")]
 722                     VUNSPEC_WCMP_GT)]
 723   "TARGET_REALLY_IWMMXT"
 724   "wcmpgtsw%?\\t%0, %1, %2"
 725   [(set_attr "predicable" "yes")])
 726
 727 ;; Max/min insns
 728
 729 (define_insn "smaxv8qi3"
 730   [(set (match_operand:V8QI            0 "register_operand" "=y")
 731         (smax:V8QI (match_operand:V8QI 1 "register_operand" "y")
 732                    (match_operand:V8QI 2 "register_operand" "y")))]
 733   "TARGET_REALLY_IWMMXT"
 734   "wmaxsb%?\\t%0, %1, %2"
 735   [(set_attr "predicable" "yes")])
 736
 737 (define_insn "umaxv8qi3"
 738   [(set (match_operand:V8QI            0 "register_operand" "=y")
 739         (umax:V8QI (match_operand:V8QI 1 "register_operand" "y")
 740                    (match_operand:V8QI 2 "register_operand" "y")))]
 741   "TARGET_REALLY_IWMMXT"
 742   "wmaxub%?\\t%0, %1, %2"
 743   [(set_attr "predicable" "yes")])
 744
 745 (define_insn "smaxv4hi3"
 746   [(set (match_operand:V4HI            0 "register_operand" "=y")
 747         (smax:V4HI (match_operand:V4HI 1 "register_operand" "y")
 748                    (match_operand:V4HI 2 "register_operand" "y")))]
 749   "TARGET_REALLY_IWMMXT"
 750   "wmaxsh%?\\t%0, %1, %2"
 751   [(set_attr "predicable" "yes")])
 752
 753 (define_insn "umaxv4hi3"
 754   [(set (match_operand:V4HI            0 "register_operand" "=y")
 755         (umax:V4HI (match_operand:V4HI 1 "register_operand" "y")
 756                    (match_operand:V4HI 2 "register_operand" "y")))]
 757   "TARGET_REALLY_IWMMXT"
 758   "wmaxuh%?\\t%0, %1, %2"
 759   [(set_attr "predicable" "yes")])
 760
 761 (define_insn "smaxv2si3"
 762   [(set (match_operand:V2SI            0 "register_operand" "=y")
 763         (smax:V2SI (match_operand:V2SI 1 "register_operand" "y")
 764                    (match_operand:V2SI 2 "register_operand" "y")))]
 765   "TARGET_REALLY_IWMMXT"
 766   "wmaxsw%?\\t%0, %1, %2"
 767   [(set_attr "predicable" "yes")])
 768
 769 (define_insn "umaxv2si3"
 770   [(set (match_operand:V2SI            0 "register_operand" "=y")
 771         (umax:V2SI (match_operand:V2SI 1 "register_operand" "y")
 772                    (match_operand:V2SI 2 "register_operand" "y")))]
 773   "TARGET_REALLY_IWMMXT"
 774   "wmaxuw%?\\t%0, %1, %2"
 775   [(set_attr "predicable" "yes")])
 776
 777 (define_insn "sminv8qi3"
 778   [(set (match_operand:V8QI            0 "register_operand" "=y")
 779         (smin:V8QI (match_operand:V8QI 1 "register_operand" "y")
 780                    (match_operand:V8QI 2 "register_operand" "y")))]
 781   "TARGET_REALLY_IWMMXT"
 782   "wminsb%?\\t%0, %1, %2"
 783   [(set_attr "predicable" "yes")])
 784
 785 (define_insn "uminv8qi3"
 786   [(set (match_operand:V8QI            0 "register_operand" "=y")
 787         (umin:V8QI (match_operand:V8QI 1 "register_operand" "y")
 788                    (match_operand:V8QI 2 "register_operand" "y")))]
 789   "TARGET_REALLY_IWMMXT"
 790   "wminub%?\\t%0, %1, %2"
 791   [(set_attr "predicable" "yes")])
 792
 793 (define_insn "sminv4hi3"
 794   [(set (match_operand:V4HI            0 "register_operand" "=y")
 795         (smin:V4HI (match_operand:V4HI 1 "register_operand" "y")
 796                    (match_operand:V4HI 2 "register_operand" "y")))]
 797   "TARGET_REALLY_IWMMXT"
 798   "wminsh%?\\t%0, %1, %2"
 799   [(set_attr "predicable" "yes")])
 800
 801 (define_insn "uminv4hi3"
 802   [(set (match_operand:V4HI            0 "register_operand" "=y")
 803         (umin:V4HI (match_operand:V4HI 1 "register_operand" "y")
 804                    (match_operand:V4HI 2 "register_operand" "y")))]
 805   "TARGET_REALLY_IWMMXT"
 806   "wminuh%?\\t%0, %1, %2"
 807   [(set_attr "predicable" "yes")])
 808
 809 (define_insn "sminv2si3"
 810   [(set (match_operand:V2SI            0 "register_operand" "=y")
 811         (smin:V2SI (match_operand:V2SI 1 "register_operand" "y")
 812                    (match_operand:V2SI 2 "register_operand" "y")))]
 813   "TARGET_REALLY_IWMMXT"
 814   "wminsw%?\\t%0, %1, %2"
 815   [(set_attr "predicable" "yes")])
 816
 817 (define_insn "uminv2si3"
 818   [(set (match_operand:V2SI            0 "register_operand" "=y")
 819         (umin:V2SI (match_operand:V2SI 1 "register_operand" "y")
 820                    (match_operand:V2SI 2 "register_operand" "y")))]
 821   "TARGET_REALLY_IWMMXT"
 822   "wminuw%?\\t%0, %1, %2"
 823   [(set_attr "predicable" "yes")])
 824
 825 ;; Pack/unpack insns.
 826
 827 (define_insn "iwmmxt_wpackhss"
 828   [(set (match_operand:V8QI                    0 "register_operand" "=y")
 829         (vec_concat:V8QI
 830          (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y"))
 831          (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
 832   "TARGET_REALLY_IWMMXT"
 833   "wpackhss%?\\t%0, %1, %2"
 834   [(set_attr "predicable" "yes")])
 835
 836 (define_insn "iwmmxt_wpackwss"
 837   [(set (match_operand:V4HI                    0 "register_operand" "=y")
 838         (vec_concat:V4HI
 839          (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y"))
 840          (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
 841   "TARGET_REALLY_IWMMXT"
 842   "wpackwss%?\\t%0, %1, %2"
 843   [(set_attr "predicable" "yes")])
 844
 845 (define_insn "iwmmxt_wpackdss"
 846   [(set (match_operand:V2SI                0 "register_operand" "=y")
 847         (vec_concat:V2SI
 848          (ss_truncate:SI (match_operand:DI 1 "register_operand" "y"))
 849          (ss_truncate:SI (match_operand:DI 2 "register_operand" "y"))))]
 850   "TARGET_REALLY_IWMMXT"
 851   "wpackdss%?\\t%0, %1, %2"
 852   [(set_attr "predicable" "yes")])
 853
 854 (define_insn "iwmmxt_wpackhus"
 855   [(set (match_operand:V8QI                    0 "register_operand" "=y")
 856         (vec_concat:V8QI
 857          (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y"))
 858          (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
 859   "TARGET_REALLY_IWMMXT"
 860   "wpackhus%?\\t%0, %1, %2"
 861   [(set_attr "predicable" "yes")])
 862
 863 (define_insn "iwmmxt_wpackwus"
 864   [(set (match_operand:V4HI                    0 "register_operand" "=y")
 865         (vec_concat:V4HI
 866          (us_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y"))
 867          (us_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
 868   "TARGET_REALLY_IWMMXT"
 869   "wpackwus%?\\t%0, %1, %2"
 870   [(set_attr "predicable" "yes")])
 871
 872 (define_insn "iwmmxt_wpackdus"
 873   [(set (match_operand:V2SI                0 "register_operand" "=y")
 874         (vec_concat:V2SI
 875          (us_truncate:SI (match_operand:DI 1 "register_operand" "y"))
 876          (us_truncate:SI (match_operand:DI 2 "register_operand" "y"))))]
 877   "TARGET_REALLY_IWMMXT"
 878   "wpackdus%?\\t%0, %1, %2"
 879   [(set_attr "predicable" "yes")])
 880
 881
 882 (define_insn "iwmmxt_wunpckihb"
 883   [(set (match_operand:V8QI                   0 "register_operand" "=y")
 884         (vec_merge:V8QI
 885          (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y")
 886                           (parallel [(const_int 4)
 887                                      (const_int 0)
 888                                      (const_int 5)
 889                                      (const_int 1)
 890                                      (const_int 6)
 891                                      (const_int 2)
 892                                      (const_int 7)
 893                                      (const_int 3)]))
 894          (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
 895                           (parallel [(const_int 0)
 896                                      (const_int 4)
 897                                      (const_int 1)
 898                                      (const_int 5)
 899                                      (const_int 2)
 900                                      (const_int 6)
 901                                      (const_int 3)
 902                                      (const_int 7)]))
 903          (const_int 85)))]
 904   "TARGET_REALLY_IWMMXT"
 905   "wunpckihb%?\\t%0, %1, %2"
 906   [(set_attr "predicable" "yes")])
 907
 908 (define_insn "iwmmxt_wunpckihh"
 909   [(set (match_operand:V4HI                   0 "register_operand" "=y")
 910         (vec_merge:V4HI
 911          (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y")
 912                           (parallel [(const_int 0)
 913                                      (const_int 2)
 914                                      (const_int 1)
 915                                      (const_int 3)]))
 916          (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
 917                           (parallel [(const_int 2)
 918                                      (const_int 0)
 919                                      (const_int 3)
 920                                      (const_int 1)]))
 921          (const_int 5)))]
 922   "TARGET_REALLY_IWMMXT"
 923   "wunpckihh%?\\t%0, %1, %2"
 924   [(set_attr "predicable" "yes")])
 925
 926 (define_insn "iwmmxt_wunpckihw"
 927   [(set (match_operand:V2SI                   0 "register_operand" "=y")
 928         (vec_merge:V2SI
 929          (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y")
 930                           (parallel [(const_int 0)
 931                                      (const_int 1)]))
 932          (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
 933                           (parallel [(const_int 1)
 934                                      (const_int 0)]))
 935          (const_int 1)))]
 936   "TARGET_REALLY_IWMMXT"
 937   "wunpckihw%?\\t%0, %1, %2"
 938   [(set_attr "predicable" "yes")])
 939
 940 (define_insn "iwmmxt_wunpckilb"
 941   [(set (match_operand:V8QI                   0 "register_operand" "=y")
 942         (vec_merge:V8QI
 943          (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y")
 944                           (parallel [(const_int 0)
 945                                      (const_int 4)
 946                                      (const_int 1)
 947                                      (const_int 5)
 948                                      (const_int 2)
 949                                      (const_int 6)
 950                                      (const_int 3)
 951                                      (const_int 7)]))
 952          (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
 953                           (parallel [(const_int 4)
 954                                      (const_int 0)
 955                                      (const_int 5)
 956                                      (const_int 1)
 957                                      (const_int 6)
 958                                      (const_int 2)
 959                                      (const_int 7)
 960                                      (const_int 3)]))
 961          (const_int 85)))]
 962   "TARGET_REALLY_IWMMXT"
 963   "wunpckilb%?\\t%0, %1, %2"
 964   [(set_attr "predicable" "yes")])
 965
 966 (define_insn "iwmmxt_wunpckilh"
 967   [(set (match_operand:V4HI                   0 "register_operand" "=y")
 968         (vec_merge:V4HI
 969          (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y")
 970                           (parallel [(const_int 2)
 971                                      (const_int 0)
 972                                      (const_int 3)
 973                                      (const_int 1)]))
 974          (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
 975                           (parallel [(const_int 0)
 976                                      (const_int 2)
 977                                      (const_int 1)
 978                                      (const_int 3)]))
 979          (const_int 5)))]
 980   "TARGET_REALLY_IWMMXT"
 981   "wunpckilh%?\\t%0, %1, %2"
 982   [(set_attr "predicable" "yes")])
 983
 984 (define_insn "iwmmxt_wunpckilw"
 985   [(set (match_operand:V2SI                   0 "register_operand" "=y")
 986         (vec_merge:V2SI
 987          (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y")
 988                            (parallel [(const_int 1)
 989                                       (const_int 0)]))
 990          (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
 991                           (parallel [(const_int 0)
 992                                      (const_int 1)]))
 993          (const_int 1)))]
 994   "TARGET_REALLY_IWMMXT"
 995   "wunpckilw%?\\t%0, %1, %2"
 996   [(set_attr "predicable" "yes")])
 997
 998 (define_insn "iwmmxt_wunpckehub"
 999   [(set (match_operand:V4HI                   0 "register_operand" "=y")
1000         (zero_extend:V4HI
1001          (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
1002                           (parallel [(const_int 4) (const_int 5)
1003                                      (const_int 6) (const_int 7)]))))]
1004   "TARGET_REALLY_IWMMXT"
1005   "wunpckehub%?\\t%0, %1"
1006   [(set_attr "predicable" "yes")])
1007
1008 (define_insn "iwmmxt_wunpckehuh"
1009   [(set (match_operand:V2SI                   0 "register_operand" "=y")
1010         (zero_extend:V2SI
1011          (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
1012                           (parallel [(const_int 2) (const_int 3)]))))]
1013   "TARGET_REALLY_IWMMXT"
1014   "wunpckehuh%?\\t%0, %1"
1015   [(set_attr "predicable" "yes")])
1016
1017 (define_insn "iwmmxt_wunpckehuw"
1018   [(set (match_operand:DI                   0 "register_operand" "=y")
1019         (zero_extend:DI
1020          (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
1021                         (parallel [(const_int 1)]))))]
1022   "TARGET_REALLY_IWMMXT"
1023   "wunpckehuw%?\\t%0, %1"
1024   [(set_attr "predicable" "yes")])
1025
1026 (define_insn "iwmmxt_wunpckehsb"
1027   [(set (match_operand:V4HI                   0 "register_operand" "=y")
1028         (sign_extend:V4HI
1029          (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
1030                           (parallel [(const_int 4) (const_int 5)
1031                                      (const_int 6) (const_int 7)]))))]
1032   "TARGET_REALLY_IWMMXT"
1033   "wunpckehsb%?\\t%0, %1"
1034   [(set_attr "predicable" "yes")])
1035
1036 (define_insn "iwmmxt_wunpckehsh"
1037   [(set (match_operand:V2SI                   0 "register_operand" "=y")
1038         (sign_extend:V2SI
1039          (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
1040                           (parallel [(const_int 2) (const_int 3)]))))]
1041   "TARGET_REALLY_IWMMXT"
1042   "wunpckehsh%?\\t%0, %1"
1043   [(set_attr "predicable" "yes")])
1044
1045 (define_insn "iwmmxt_wunpckehsw"
1046   [(set (match_operand:DI                   0 "register_operand" "=y")
1047         (sign_extend:DI
1048          (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
1049                         (parallel [(const_int 1)]))))]
1050   "TARGET_REALLY_IWMMXT"
1051   "wunpckehsw%?\\t%0, %1"
1052   [(set_attr "predicable" "yes")])
1053
1054 (define_insn "iwmmxt_wunpckelub"
1055   [(set (match_operand:V4HI                   0 "register_operand" "=y")
1056         (zero_extend:V4HI
1057          (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
1058                           (parallel [(const_int 0) (const_int 1)
1059                                      (const_int 2) (const_int 3)]))))]
1060   "TARGET_REALLY_IWMMXT"
1061   "wunpckelub%?\\t%0, %1"
1062   [(set_attr "predicable" "yes")])
1063
1064 (define_insn "iwmmxt_wunpckeluh"
1065   [(set (match_operand:V2SI                   0 "register_operand" "=y")
1066         (zero_extend:V2SI
1067          (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
1068                           (parallel [(const_int 0) (const_int 1)]))))]
1069   "TARGET_REALLY_IWMMXT"
1070   "wunpckeluh%?\\t%0, %1"
1071   [(set_attr "predicable" "yes")])
1072
1073 (define_insn "iwmmxt_wunpckeluw"
1074   [(set (match_operand:DI                   0 "register_operand" "=y")
1075         (zero_extend:DI
1076          (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
1077                         (parallel [(const_int 0)]))))]
1078   "TARGET_REALLY_IWMMXT"
1079   "wunpckeluw%?\\t%0, %1"
1080   [(set_attr "predicable" "yes")])
1081
1082 (define_insn "iwmmxt_wunpckelsb"
1083   [(set (match_operand:V4HI                   0 "register_operand" "=y")
1084         (sign_extend:V4HI
1085          (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
1086                           (parallel [(const_int 0) (const_int 1)
1087                                      (const_int 2) (const_int 3)]))))]
1088   "TARGET_REALLY_IWMMXT"
1089   "wunpckelsb%?\\t%0, %1"
1090   [(set_attr "predicable" "yes")])
1091
1092 (define_insn "iwmmxt_wunpckelsh"
1093   [(set (match_operand:V2SI                   0 "register_operand" "=y")
1094         (sign_extend:V2SI
1095          (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
1096                           (parallel [(const_int 0) (const_int 1)]))))]
1097   "TARGET_REALLY_IWMMXT"
1098   "wunpckelsh%?\\t%0, %1"
1099   [(set_attr "predicable" "yes")])
1100
1101 (define_insn "iwmmxt_wunpckelsw"
1102   [(set (match_operand:DI                   0 "register_operand" "=y")
1103         (sign_extend:DI
1104          (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
1105                         (parallel [(const_int 0)]))))]
1106   "TARGET_REALLY_IWMMXT"
1107   "wunpckelsw%?\\t%0, %1"
1108   [(set_attr "predicable" "yes")])
1109
1110 ;; Shifts
1111
1112 (define_insn "rorv4hi3"
1113   [(set (match_operand:V4HI                0 "register_operand" "=y")
1114         (rotatert:V4HI (match_operand:V4HI 1 "register_operand" "y")
1115                        (match_operand:SI   2 "register_operand" "z")))]
1116   "TARGET_REALLY_IWMMXT"
1117   "wrorhg%?\\t%0, %1, %2"
1118   [(set_attr "predicable" "yes")])
1119
1120 (define_insn "rorv2si3"
1121   [(set (match_operand:V2SI                0 "register_operand" "=y")
1122         (rotatert:V2SI (match_operand:V2SI 1 "register_operand" "y")
1123                        (match_operand:SI   2 "register_operand" "z")))]
1124   "TARGET_REALLY_IWMMXT"
1125   "wrorwg%?\\t%0, %1, %2"
1126   [(set_attr "predicable" "yes")])
1127
1128 (define_insn "rordi3"
1129   [(set (match_operand:DI              0 "register_operand" "=y")
1130         (rotatert:DI (match_operand:DI 1 "register_operand" "y")
1131                    (match_operand:SI   2 "register_operand" "z")))]
1132   "TARGET_REALLY_IWMMXT"
1133   "wrordg%?\\t%0, %1, %2"
1134   [(set_attr "predicable" "yes")])
1135
1136 (define_insn "ashrv4hi3"
1137   [(set (match_operand:V4HI                0 "register_operand" "=y")
1138         (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y")
1139                        (match_operand:SI   2 "register_operand" "z")))]
1140   "TARGET_REALLY_IWMMXT"
1141   "wsrahg%?\\t%0, %1, %2"
1142   [(set_attr "predicable" "yes")])
1143
1144 (define_insn "ashrv2si3"
1145   [(set (match_operand:V2SI                0 "register_operand" "=y")
1146         (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y")
1147                        (match_operand:SI   2 "register_operand" "z")))]
1148   "TARGET_REALLY_IWMMXT"
1149   "wsrawg%?\\t%0, %1, %2"
1150   [(set_attr "predicable" "yes")])
1151
1152 (define_insn "ashrdi3_iwmmxt"
1153   [(set (match_operand:DI              0 "register_operand" "=y")
1154         (ashiftrt:DI (match_operand:DI 1 "register_operand" "y")
1155                    (match_operand:SI   2 "register_operand" "z")))]
1156   "TARGET_REALLY_IWMMXT"
1157   "wsradg%?\\t%0, %1, %2"
1158   [(set_attr "predicable" "yes")])
1159
1160 (define_insn "lshrv4hi3"
1161   [(set (match_operand:V4HI                0 "register_operand" "=y")
1162         (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y")
1163                        (match_operand:SI   2 "register_operand" "z")))]
1164   "TARGET_REALLY_IWMMXT"
1165   "wsrlhg%?\\t%0, %1, %2"
1166   [(set_attr "predicable" "yes")])
1167
1168 (define_insn "lshrv2si3"
1169   [(set (match_operand:V2SI                0 "register_operand" "=y")
1170         (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y")
1171                        (match_operand:SI   2 "register_operand" "z")))]
1172   "TARGET_REALLY_IWMMXT"
1173   "wsrlwg%?\\t%0, %1, %2"
1174   [(set_attr "predicable" "yes")])
1175
1176 (define_insn "lshrdi3_iwmmxt"
1177   [(set (match_operand:DI              0 "register_operand" "=y")
1178         (lshiftrt:DI (match_operand:DI 1 "register_operand" "y")
1179                      (match_operand:SI 2 "register_operand" "z")))]
1180   "TARGET_REALLY_IWMMXT"
1181   "wsrldg%?\\t%0, %1, %2"
1182   [(set_attr "predicable" "yes")])
1183
1184 (define_insn "ashlv4hi3"
1185   [(set (match_operand:V4HI              0 "register_operand" "=y")
1186         (ashift:V4HI (match_operand:V4HI 1 "register_operand" "y")
1187                      (match_operand:SI   2 "register_operand" "z")))]
1188   "TARGET_REALLY_IWMMXT"
1189   "wsllhg%?\\t%0, %1, %2"
1190   [(set_attr "predicable" "yes")])
1191
1192 (define_insn "ashlv2si3"
1193   [(set (match_operand:V2SI              0 "register_operand" "=y")
1194         (ashift:V2SI (match_operand:V2SI 1 "register_operand" "y")
1195                        (match_operand:SI 2 "register_operand" "z")))]
1196   "TARGET_REALLY_IWMMXT"
1197   "wsllwg%?\\t%0, %1, %2"
1198   [(set_attr "predicable" "yes")])
1199
1200 (define_insn "ashldi3_iwmmxt"
1201   [(set (match_operand:DI            0 "register_operand" "=y")
1202         (ashift:DI (match_operand:DI 1 "register_operand" "y")
1203                    (match_operand:SI 2 "register_operand" "z")))]
1204   "TARGET_REALLY_IWMMXT"
1205   "wslldg%?\\t%0, %1, %2"
1206   [(set_attr "predicable" "yes")])
1207
1208 (define_insn "rorv4hi3_di"
1209   [(set (match_operand:V4HI                0 "register_operand" "=y")
1210         (rotatert:V4HI (match_operand:V4HI 1 "register_operand" "y")
1211                        (match_operand:DI   2 "register_operand" "y")))]
1212   "TARGET_REALLY_IWMMXT"
1213   "wrorh%?\\t%0, %1, %2"
1214   [(set_attr "predicable" "yes")])
1215
1216 (define_insn "rorv2si3_di"
1217   [(set (match_operand:V2SI                0 "register_operand" "=y")
1218         (rotatert:V2SI (match_operand:V2SI 1 "register_operand" "y")
1219                        (match_operand:DI   2 "register_operand" "y")))]
1220   "TARGET_REALLY_IWMMXT"
1221   "wrorw%?\\t%0, %1, %2"
1222   [(set_attr "predicable" "yes")])
1223
1224 (define_insn "rordi3_di"
1225   [(set (match_operand:DI              0 "register_operand" "=y")
1226         (rotatert:DI (match_operand:DI 1 "register_operand" "y")
1227                    (match_operand:DI   2 "register_operand" "y")))]
1228   "TARGET_REALLY_IWMMXT"
1229   "wrord%?\\t%0, %1, %2"
1230   [(set_attr "predicable" "yes")])
1231
1232 (define_insn "ashrv4hi3_di"
1233   [(set (match_operand:V4HI                0 "register_operand" "=y")
1234         (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y")
1235                        (match_operand:DI   2 "register_operand" "y")))]
1236   "TARGET_REALLY_IWMMXT"
1237   "wsrah%?\\t%0, %1, %2"
1238   [(set_attr "predicable" "yes")])
1239
1240 (define_insn "ashrv2si3_di"
1241   [(set (match_operand:V2SI                0 "register_operand" "=y")
1242         (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y")
1243                        (match_operand:DI   2 "register_operand" "y")))]
1244   "TARGET_REALLY_IWMMXT"
1245   "wsraw%?\\t%0, %1, %2"
1246   [(set_attr "predicable" "yes")])
1247
1248 (define_insn "ashrdi3_di"
1249   [(set (match_operand:DI              0 "register_operand" "=y")
1250         (ashiftrt:DI (match_operand:DI 1 "register_operand" "y")
1251                    (match_operand:DI   2 "register_operand" "y")))]
1252   "TARGET_REALLY_IWMMXT"
1253   "wsrad%?\\t%0, %1, %2"
1254   [(set_attr "predicable" "yes")])
1255
1256 (define_insn "lshrv4hi3_di"
1257   [(set (match_operand:V4HI                0 "register_operand" "=y")
1258         (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y")
1259                        (match_operand:DI   2 "register_operand" "y")))]
1260   "TARGET_REALLY_IWMMXT"
1261   "wsrlh%?\\t%0, %1, %2"
1262   [(set_attr "predicable" "yes")])
1263
1264 (define_insn "lshrv2si3_di"
1265   [(set (match_operand:V2SI                0 "register_operand" "=y")
1266         (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y")
1267                        (match_operand:DI   2 "register_operand" "y")))]
1268   "TARGET_REALLY_IWMMXT"
1269   "wsrlw%?\\t%0, %1, %2"
1270   [(set_attr "predicable" "yes")])
1271
1272 (define_insn "lshrdi3_di"
1273   [(set (match_operand:DI              0 "register_operand" "=y")
1274         (lshiftrt:DI (match_operand:DI 1 "register_operand" "y")
1275                      (match_operand:DI 2 "register_operand" "y")))]
1276   "TARGET_REALLY_IWMMXT"
1277   "wsrld%?\\t%0, %1, %2"
1278   [(set_attr "predicable" "yes")])
1279
1280 (define_insn "ashlv4hi3_di"
1281   [(set (match_operand:V4HI              0 "register_operand" "=y")
1282         (ashift:V4HI (match_operand:V4HI 1 "register_operand" "y")
1283                      (match_operand:DI   2 "register_operand" "y")))]
1284   "TARGET_REALLY_IWMMXT"
1285   "wsllh%?\\t%0, %1, %2"
1286   [(set_attr "predicable" "yes")])
1287
1288 (define_insn "ashlv2si3_di"
1289   [(set (match_operand:V2SI              0 "register_operand" "=y")
1290         (ashift:V2SI (match_operand:V2SI 1 "register_operand" "y")
1291                        (match_operand:DI 2 "register_operand" "y")))]
1292   "TARGET_REALLY_IWMMXT"
1293   "wsllw%?\\t%0, %1, %2"
1294   [(set_attr "predicable" "yes")])
1295
1296 (define_insn "ashldi3_di"
1297   [(set (match_operand:DI            0 "register_operand" "=y")
1298         (ashift:DI (match_operand:DI 1 "register_operand" "y")
1299                    (match_operand:DI 2 "register_operand" "y")))]
1300   "TARGET_REALLY_IWMMXT"
1301   "wslld%?\\t%0, %1, %2"
1302   [(set_attr "predicable" "yes")])
1303
1304 (define_insn "iwmmxt_wmadds"
1305   [(set (match_operand:V4HI               0 "register_operand" "=y")
1306         (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
1307                       (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMADDS))]
1308   "TARGET_REALLY_IWMMXT"
1309   "wmadds%?\\t%0, %1, %2"
1310   [(set_attr "predicable" "yes")])
1311
1312 (define_insn "iwmmxt_wmaddu"
1313   [(set (match_operand:V4HI               0 "register_operand" "=y")
1314         (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
1315                       (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMADDU))]
1316   "TARGET_REALLY_IWMMXT"
1317   "wmaddu%?\\t%0, %1, %2"
1318   [(set_attr "predicable" "yes")])
1319
1320 (define_insn "iwmmxt_tmia"
1321   [(set (match_operand:DI                    0 "register_operand" "=y")
1322         (plus:DI (match_operand:DI           1 "register_operand" "0")
1323                  (mult:DI (sign_extend:DI
1324                            (match_operand:SI 2 "register_operand" "r"))
1325                           (sign_extend:DI
1326                            (match_operand:SI 3 "register_operand" "r")))))]
1327   "TARGET_REALLY_IWMMXT"
1328   "tmia%?\\t%0, %2, %3"
1329   [(set_attr "predicable" "yes")])
1330
1331 (define_insn "iwmmxt_tmiaph"
1332   [(set (match_operand:DI          0 "register_operand" "=y")
1333         (plus:DI (match_operand:DI 1 "register_operand" "0")
1334                  (plus:DI
1335                   (mult:DI (sign_extend:DI
1336                             (truncate:HI (match_operand:SI 2 "register_operand" "r")))
1337                            (sign_extend:DI
1338                             (truncate:HI (match_operand:SI 3 "register_operand" "r"))))
1339                   (mult:DI (sign_extend:DI
1340                             (truncate:HI (ashiftrt:SI (match_dup 2) (const_int 16))))
1341                            (sign_extend:DI
1342                             (truncate:HI (ashiftrt:SI (match_dup 3) (const_int 16))))))))]
1343   "TARGET_REALLY_IWMMXT"
1344   "tmiaph%?\\t%0, %2, %3"
1345   [(set_attr "predicable" "yes")])
1346
1347 (define_insn "iwmmxt_tmiabb"
1348   [(set (match_operand:DI          0 "register_operand" "=y")
1349         (plus:DI (match_operand:DI 1 "register_operand" "0")
1350                  (mult:DI (sign_extend:DI
1351                            (truncate:HI (match_operand:SI 2 "register_operand" "r")))
1352                           (sign_extend:DI
1353                            (truncate:HI (match_operand:SI 3 "register_operand" "r"))))))]
1354   "TARGET_REALLY_IWMMXT"
1355   "tmiabb%?\\t%0, %2, %3"
1356   [(set_attr "predicable" "yes")])
1357
1358 (define_insn "iwmmxt_tmiatb"
1359   [(set (match_operand:DI          0 "register_operand" "=y")
1360         (plus:DI (match_operand:DI 1 "register_operand" "0")
1361                  (mult:DI (sign_extend:DI
1362                            (truncate:HI (ashiftrt:SI
1363                                          (match_operand:SI 2 "register_operand" "r")
1364                                          (const_int 16))))
1365                           (sign_extend:DI
1366                            (truncate:HI (match_operand:SI 3 "register_operand" "r"))))))]
1367   "TARGET_REALLY_IWMMXT"
1368   "tmiatb%?\\t%0, %2, %3"
1369   [(set_attr "predicable" "yes")])
1370
1371 (define_insn "iwmmxt_tmiabt"
1372   [(set (match_operand:DI          0 "register_operand" "=y")
1373         (plus:DI (match_operand:DI 1 "register_operand" "0")
1374                  (mult:DI (sign_extend:DI
1375                            (truncate:HI (match_operand:SI 2 "register_operand" "r")))
1376                           (sign_extend:DI
1377                            (truncate:HI (ashiftrt:SI
1378                                          (match_operand:SI 3 "register_operand" "r")
1379                                          (const_int 16)))))))]
1380   "TARGET_REALLY_IWMMXT"
1381   "tmiabt%?\\t%0, %2, %3"
1382   [(set_attr "predicable" "yes")])
1383
1384 (define_insn "iwmmxt_tmiatt"
1385   [(set (match_operand:DI          0 "register_operand" "=y")
1386         (plus:DI (match_operand:DI 1 "register_operand" "0")
1387                  (mult:DI (sign_extend:DI
1388                            (truncate:HI (ashiftrt:SI
1389                                          (match_operand:SI 2 "register_operand" "r")
1390                                          (const_int 16))))
1391                           (sign_extend:DI
1392                            (truncate:HI (ashiftrt:SI
1393                                          (match_operand:SI 3 "register_operand" "r")
1394                                          (const_int 16)))))))]
1395   "TARGET_REALLY_IWMMXT"
1396   "tmiatt%?\\t%0, %2, %3"
1397   [(set_attr "predicable" "yes")])
1398
1399 (define_insn "iwmmxt_tbcstqi"
1400   [(set (match_operand:V8QI                   0 "register_operand" "=y")
1401         (vec_duplicate:V8QI (match_operand:QI 1 "register_operand" "r")))]
1402   "TARGET_REALLY_IWMMXT"
1403   "tbcstb%?\\t%0, %1"
1404   [(set_attr "predicable" "yes")])
1405
1406 (define_insn "iwmmxt_tbcsthi"
1407   [(set (match_operand:V4HI                   0 "register_operand" "=y")
1408         (vec_duplicate:V4HI (match_operand:HI 1 "register_operand" "r")))]
1409   "TARGET_REALLY_IWMMXT"
1410   "tbcsth%?\\t%0, %1"
1411   [(set_attr "predicable" "yes")])
1412
1413 (define_insn "iwmmxt_tbcstsi"
1414   [(set (match_operand:V2SI                   0 "register_operand" "=y")
1415         (vec_duplicate:V2SI (match_operand:SI 1 "register_operand" "r")))]
1416   "TARGET_REALLY_IWMMXT"
1417   "tbcstw%?\\t%0, %1"
1418   [(set_attr "predicable" "yes")])
1419
1420 (define_insn "iwmmxt_tmovmskb"
1421   [(set (match_operand:SI               0 "register_operand" "=r")
1422         (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
1423   "TARGET_REALLY_IWMMXT"
1424   "tmovmskb%?\\t%0, %1"
1425   [(set_attr "predicable" "yes")])
1426
1427 (define_insn "iwmmxt_tmovmskh"
1428   [(set (match_operand:SI               0 "register_operand" "=r")
1429         (unspec:SI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
1430   "TARGET_REALLY_IWMMXT"
1431   "tmovmskh%?\\t%0, %1"
1432   [(set_attr "predicable" "yes")])
1433
1434 (define_insn "iwmmxt_tmovmskw"
1435   [(set (match_operand:SI               0 "register_operand" "=r")
1436         (unspec:SI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
1437   "TARGET_REALLY_IWMMXT"
1438   "tmovmskw%?\\t%0, %1"
1439   [(set_attr "predicable" "yes")])
1440
1441 (define_insn "iwmmxt_waccb"
1442   [(set (match_operand:DI               0 "register_operand" "=y")
1443         (unspec:DI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_WACC))]
1444   "TARGET_REALLY_IWMMXT"
1445   "waccb%?\\t%0, %1"
1446   [(set_attr "predicable" "yes")])
1447
1448 (define_insn "iwmmxt_wacch"
1449   [(set (match_operand:DI               0 "register_operand" "=y")
1450         (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_WACC))]
1451   "TARGET_REALLY_IWMMXT"
1452   "wacch%?\\t%0, %1"
1453   [(set_attr "predicable" "yes")])
1454
1455 (define_insn "iwmmxt_waccw"
1456   [(set (match_operand:DI               0 "register_operand" "=y")
1457         (unspec:DI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_WACC))]
1458   "TARGET_REALLY_IWMMXT"
1459   "waccw%?\\t%0, %1"
1460   [(set_attr "predicable" "yes")])
1461
1462 (define_insn "iwmmxt_walign"
1463   [(set (match_operand:V8QI                           0 "register_operand" "=y,y")
1464         (subreg:V8QI (ashiftrt:TI
1465                       (subreg:TI (vec_concat:V16QI
1466                                   (match_operand:V8QI 1 "register_operand" "y,y")
1467                                   (match_operand:V8QI 2 "register_operand" "y,y")) 0)
1468                       (mult:SI
1469                        (match_operand:SI              3 "nonmemory_operand" "i,z")
1470                        (const_int 8))) 0))]
1471   "TARGET_REALLY_IWMMXT"
1472   "@
1473    waligni%?\\t%0, %1, %2, %3
1474    walignr%U3%?\\t%0, %1, %2"
1475   [(set_attr "predicable" "yes")])
1476
1477 (define_insn "iwmmxt_tmrc"
1478   [(set (match_operand:SI                      0 "register_operand" "=r")
1479         (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "i")]
1480                             VUNSPEC_TMRC))]
1481   "TARGET_REALLY_IWMMXT"
1482   "tmrc%?\\t%0, %w1"
1483   [(set_attr "predicable" "yes")])
1484
1485 (define_insn "iwmmxt_tmcr"
1486   [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")
1487                         (match_operand:SI 1 "register_operand"  "r")]
1488                        VUNSPEC_TMCR)]
1489   "TARGET_REALLY_IWMMXT"
1490   "tmcr%?\\t%w0, %1"
1491   [(set_attr "predicable" "yes")])
1492
1493 (define_insn "iwmmxt_wsadb"
1494   [(set (match_operand:V8QI               0 "register_operand" "=y")
1495         (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
1496                       (match_operand:V8QI 2 "register_operand" "y")] UNSPEC_WSAD))]
1497   "TARGET_REALLY_IWMMXT"
1498   "wsadb%?\\t%0, %1, %2"
1499   [(set_attr "predicable" "yes")])
1500
1501 (define_insn "iwmmxt_wsadh"
1502   [(set (match_operand:V4HI               0 "register_operand" "=y")
1503         (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
1504                       (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WSAD))]
1505   "TARGET_REALLY_IWMMXT"
1506   "wsadh%?\\t%0, %1, %2"
1507   [(set_attr "predicable" "yes")])
1508
1509 (define_insn "iwmmxt_wsadbz"
1510   [(set (match_operand:V8QI               0 "register_operand" "=y")
1511         (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
1512                       (match_operand:V8QI 2 "register_operand" "y")] UNSPEC_WSADZ))]
1513   "TARGET_REALLY_IWMMXT"
1514   "wsadbz%?\\t%0, %1, %2"
1515   [(set_attr "predicable" "yes")])
1516
1517 (define_insn "iwmmxt_wsadhz"
1518   [(set (match_operand:V4HI               0 "register_operand" "=y")
1519         (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
1520                       (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WSADZ))]
1521   "TARGET_REALLY_IWMMXT"
1522   "wsadhz%?\\t%0, %1, %2"
1523   [(set_attr "predicable" "yes")])
1524