gcc/config/arm/iwmmxt2.md

   1 ;; Patterns for the Intel Wireless MMX technology architecture.
   2 ;; Copyright (C) 2011, 2012 Free Software Foundation, Inc.
   3 ;; Written by Marvell, Inc.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published
   9 ;; by the Free Software Foundation; either version 3, or (at your
  10 ;; option) any later version.
  11
  12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ;; License for more details.
  16
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 (define_c_enum "unspec" [
  22   UNSPEC_WADDC          ; Used by the intrinsic form of the iWMMXt WADDC instruction.
  23   UNSPEC_WABS           ; Used by the intrinsic form of the iWMMXt WABS instruction.
  24   UNSPEC_WQMULWMR       ; Used by the intrinsic form of the iWMMXt WQMULWMR instruction.
  25   UNSPEC_WQMULMR        ; Used by the intrinsic form of the iWMMXt WQMULMR instruction.
  26   UNSPEC_WQMULWM        ; Used by the intrinsic form of the iWMMXt WQMULWM instruction.
  27   UNSPEC_WQMULM         ; Used by the intrinsic form of the iWMMXt WQMULM instruction.
  28   UNSPEC_WQMIAxyn       ; Used by the intrinsic form of the iWMMXt WMIAxyn instruction.
  29   UNSPEC_WQMIAxy        ; Used by the intrinsic form of the iWMMXt WMIAxy instruction.
  30   UNSPEC_TANDC          ; Used by the intrinsic form of the iWMMXt TANDC instruction.
  31   UNSPEC_TORC           ; Used by the intrinsic form of the iWMMXt TORC instruction.
  32   UNSPEC_TORVSC         ; Used by the intrinsic form of the iWMMXt TORVSC instruction.
  33   UNSPEC_TEXTRC         ; Used by the intrinsic form of the iWMMXt TEXTRC instruction.
  34 ])
  35
  36 (define_insn "iwmmxt_wabs<mode>3"
  37   [(set (match_operand:VMMX               0 "register_operand" "=y")
  38         (unspec:VMMX [(match_operand:VMMX 1 "register_operand"  "y")] UNSPEC_WABS))]
  39   "TARGET_REALLY_IWMMXT"
  40   "wabs<MMX_char>%?\\t%0, %1"
  41   [(set_attr "predicable" "yes")
  42    (set_attr "wtype" "wabs")]
  43 )
  44
  45 (define_insn "iwmmxt_wabsdiffb"
  46   [(set (match_operand:V8QI                          0 "register_operand" "=y")
  47         (truncate:V8QI
  48           (abs:V8HI
  49             (minus:V8HI
  50               (zero_extend:V8HI (match_operand:V8QI  1 "register_operand"  "y"))
  51               (zero_extend:V8HI (match_operand:V8QI  2 "register_operand"  "y"))))))]
  52  "TARGET_REALLY_IWMMXT"
  53  "wabsdiffb%?\\t%0, %1, %2"
  54  [(set_attr "predicable" "yes")
  55   (set_attr "wtype" "wabsdiff")]
  56 )
  57
  58 (define_insn "iwmmxt_wabsdiffh"
  59   [(set (match_operand:V4HI                          0 "register_operand" "=y")
  60         (truncate: V4HI
  61           (abs:V4SI
  62             (minus:V4SI
  63               (zero_extend:V4SI (match_operand:V4HI  1 "register_operand"  "y"))
  64               (zero_extend:V4SI (match_operand:V4HI  2 "register_operand"  "y"))))))]
  65   "TARGET_REALLY_IWMMXT"
  66   "wabsdiffh%?\\t%0, %1, %2"
  67   [(set_attr "predicable" "yes")
  68    (set_attr "wtype" "wabsdiff")]
  69 )
  70
  71 (define_insn "iwmmxt_wabsdiffw"
  72   [(set (match_operand:V2SI                          0 "register_operand" "=y")
  73         (truncate: V2SI
  74           (abs:V2DI
  75             (minus:V2DI
  76               (zero_extend:V2DI (match_operand:V2SI  1 "register_operand"  "y"))
  77               (zero_extend:V2DI (match_operand:V2SI  2 "register_operand"  "y"))))))]
  78  "TARGET_REALLY_IWMMXT"
  79  "wabsdiffw%?\\t%0, %1, %2"
  80  [(set_attr "predicable" "yes")
  81   (set_attr "wtype" "wabsdiff")]
  82 )
  83
  84 (define_insn "iwmmxt_waddsubhx"
  85   [(set (match_operand:V4HI                                        0 "register_operand" "=y")
  86         (vec_merge:V4HI
  87           (ss_minus:V4HI
  88             (match_operand:V4HI                                    1 "register_operand" "y")
  89             (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
  90                              (parallel [(const_int 1) (const_int 0) (const_int 3) (const_int 2)])))
  91           (ss_plus:V4HI
  92             (match_dup 1)
  93             (vec_select:V4HI (match_dup 2)
  94                              (parallel [(const_int 1) (const_int 0) (const_int 3) (const_int 2)])))
  95           (const_int 10)))]
  96   "TARGET_REALLY_IWMMXT"
  97   "waddsubhx%?\\t%0, %1, %2"
  98   [(set_attr "predicable" "yes")
  99    (set_attr "wtype" "waddsubhx")]
 100 )
 101
 102 (define_insn "iwmmxt_wsubaddhx"
 103   [(set (match_operand:V4HI                                        0 "register_operand" "=y")
 104         (vec_merge:V4HI
 105           (ss_plus:V4HI
 106             (match_operand:V4HI                                    1 "register_operand" "y")
 107             (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
 108                              (parallel [(const_int 1) (const_int 0) (const_int 3) (const_int 2)])))
 109           (ss_minus:V4HI
 110             (match_dup 1)
 111             (vec_select:V4HI (match_dup 2)
 112                              (parallel [(const_int 1) (const_int 0) (const_int 3) (const_int 2)])))
 113           (const_int 10)))]
 114   "TARGET_REALLY_IWMMXT"
 115   "wsubaddhx%?\\t%0, %1, %2"
 116   [(set_attr "predicable" "yes")
 117    (set_attr "wtype" "wsubaddhx")]
 118 )
 119
 120 (define_insn "addc<mode>3"
 121   [(set (match_operand:VMMX2      0 "register_operand" "=y")
 122         (unspec:VMMX2
 123           [(plus:VMMX2
 124              (match_operand:VMMX2 1 "register_operand"  "y")
 125              (match_operand:VMMX2 2 "register_operand"  "y"))] UNSPEC_WADDC))]
 126   "TARGET_REALLY_IWMMXT"
 127   "wadd<MMX_char>c%?\\t%0, %1, %2"
 128   [(set_attr "predicable" "yes")
 129    (set_attr "wtype" "wadd")]
 130 )
 131
 132 (define_insn "iwmmxt_avg4"
 133 [(set (match_operand:V8QI                                 0 "register_operand" "=y")
 134       (truncate:V8QI
 135         (vec_select:V8HI
 136           (vec_merge:V8HI
 137             (lshiftrt:V8HI
 138               (plus:V8HI
 139                 (plus:V8HI
 140                   (plus:V8HI
 141                     (plus:V8HI
 142                       (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
 143                       (zero_extend:V8HI (match_operand:V8QI 2 "register_operand" "y")))
 144                     (vec_select:V8HI (zero_extend:V8HI (match_dup 1))
 145                                      (parallel [(const_int 7) (const_int 0) (const_int 1) (const_int 2)
 146                                                 (const_int 3) (const_int 4) (const_int 5) (const_int 6)])))
 147                   (vec_select:V8HI (zero_extend:V8HI (match_dup 2))
 148                                    (parallel [(const_int 7) (const_int 0) (const_int 1) (const_int 2)
 149                                               (const_int 3) (const_int 4) (const_int 5) (const_int 6)])))
 150                 (const_vector:V8HI [(const_int 1) (const_int 1) (const_int 1) (const_int 1)
 151                                     (const_int 1) (const_int 1) (const_int 1) (const_int 1)]))
 152               (const_int 2))
 153             (const_vector:V8HI [(const_int 0) (const_int 0) (const_int 0) (const_int 0)
 154                                 (const_int 0) (const_int 0) (const_int 0) (const_int 0)])
 155             (const_int 254))
 156           (parallel [(const_int 1) (const_int 2) (const_int 3) (const_int 4)
 157                      (const_int 5) (const_int 6) (const_int 7) (const_int 0)]))))]
 158   "TARGET_REALLY_IWMMXT"
 159   "wavg4%?\\t%0, %1, %2"
 160   [(set_attr "predicable" "yes")
 161    (set_attr "wtype" "wavg4")]
 162 )
 163
 164 (define_insn "iwmmxt_avg4r"
 165   [(set (match_operand:V8QI                                   0 "register_operand" "=y")
 166         (truncate:V8QI
 167           (vec_select:V8HI
 168             (vec_merge:V8HI
 169               (lshiftrt:V8HI
 170                 (plus:V8HI
 171                   (plus:V8HI
 172                     (plus:V8HI
 173                       (plus:V8HI
 174                         (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
 175                         (zero_extend:V8HI (match_operand:V8QI 2 "register_operand" "y")))
 176                       (vec_select:V8HI (zero_extend:V8HI (match_dup 1))
 177                                        (parallel [(const_int 7) (const_int 0) (const_int 1) (const_int 2)
 178                                                   (const_int 3) (const_int 4) (const_int 5) (const_int 6)])))
 179                     (vec_select:V8HI (zero_extend:V8HI (match_dup 2))
 180                                      (parallel [(const_int 7) (const_int 0) (const_int 1) (const_int 2)
 181                                                 (const_int 3) (const_int 4) (const_int 5) (const_int 6)])))
 182                   (const_vector:V8HI [(const_int 2) (const_int 2) (const_int 2) (const_int 2)
 183                                       (const_int 2) (const_int 2) (const_int 2) (const_int 2)]))
 184                 (const_int 2))
 185               (const_vector:V8HI [(const_int 0) (const_int 0) (const_int 0) (const_int 0)
 186                                   (const_int 0) (const_int 0) (const_int 0) (const_int 0)])
 187               (const_int 254))
 188             (parallel [(const_int 1) (const_int 2) (const_int 3) (const_int 4)
 189                        (const_int 5) (const_int 6) (const_int 7) (const_int 0)]))))]
 190   "TARGET_REALLY_IWMMXT"
 191   "wavg4r%?\\t%0, %1, %2"
 192   [(set_attr "predicable" "yes")
 193    (set_attr "wtype" "wavg4")]
 194 )
 195
 196 (define_insn "iwmmxt_wmaddsx"
 197   [(set (match_operand:V2SI                                        0 "register_operand" "=y")
 198         (plus:V2SI
 199           (mult:V2SI
 200             (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
 201                              (parallel [(const_int 1) (const_int 3)]))
 202             (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))
 203                              (parallel [(const_int 0) (const_int 2)])))
 204           (mult:V2SI
 205             (vec_select:V2SI (sign_extend:V4SI (match_dup 1))
 206                              (parallel [(const_int 0) (const_int 2)]))
 207             (vec_select:V2SI (sign_extend:V4SI (match_dup 2))
 208                              (parallel [(const_int 1) (const_int 3)])))))]
 209  "TARGET_REALLY_IWMMXT"
 210   "wmaddsx%?\\t%0, %1, %2"
 211   [(set_attr "predicable" "yes")
 212         (set_attr "wtype" "wmadd")]
 213 )
 214
 215 (define_insn "iwmmxt_wmaddux"
 216   [(set (match_operand:V2SI                                        0 "register_operand" "=y")
 217         (plus:V2SI
 218           (mult:V2SI
 219             (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
 220                              (parallel [(const_int 1) (const_int 3)]))
 221             (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))
 222                              (parallel [(const_int 0) (const_int 2)])))
 223           (mult:V2SI
 224             (vec_select:V2SI (zero_extend:V4SI (match_dup 1))
 225                              (parallel [(const_int 0) (const_int 2)]))
 226             (vec_select:V2SI (zero_extend:V4SI (match_dup 2))
 227                              (parallel [(const_int 1) (const_int 3)])))))]
 228   "TARGET_REALLY_IWMMXT"
 229   "wmaddux%?\\t%0, %1, %2"
 230   [(set_attr "predicable" "yes")
 231    (set_attr "wtype" "wmadd")]
 232 )
 233
 234 (define_insn "iwmmxt_wmaddsn"
 235  [(set (match_operand:V2SI                                     0 "register_operand" "=y")
 236     (minus:V2SI
 237       (mult:V2SI
 238         (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
 239                          (parallel [(const_int 0) (const_int 2)]))
 240         (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))
 241                          (parallel [(const_int 0) (const_int 2)])))
 242       (mult:V2SI
 243         (vec_select:V2SI (sign_extend:V4SI (match_dup 1))
 244                          (parallel [(const_int 1) (const_int 3)]))
 245         (vec_select:V2SI (sign_extend:V4SI (match_dup 2))
 246                          (parallel [(const_int 1) (const_int 3)])))))]
 247  "TARGET_REALLY_IWMMXT"
 248  "wmaddsn%?\\t%0, %1, %2"
 249  [(set_attr "predicable" "yes")
 250   (set_attr "wtype" "wmadd")]
 251 )
 252
 253 (define_insn "iwmmxt_wmaddun"
 254   [(set (match_operand:V2SI                                        0 "register_operand" "=y")
 255         (minus:V2SI
 256           (mult:V2SI
 257             (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
 258                              (parallel [(const_int 0) (const_int 2)]))
 259             (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))
 260                              (parallel [(const_int 0) (const_int 2)])))
 261           (mult:V2SI
 262             (vec_select:V2SI (zero_extend:V4SI (match_dup 1))
 263                              (parallel [(const_int 1) (const_int 3)]))
 264             (vec_select:V2SI (zero_extend:V4SI (match_dup 2))
 265                              (parallel [(const_int 1) (const_int 3)])))))]
 266   "TARGET_REALLY_IWMMXT"
 267   "wmaddun%?\\t%0, %1, %2"
 268   [(set_attr "predicable" "yes")
 269    (set_attr "wtype" "wmadd")]
 270 )
 271
 272 (define_insn "iwmmxt_wmulwsm"
 273   [(set (match_operand:V2SI                         0 "register_operand" "=y")
 274         (truncate:V2SI
 275           (ashiftrt:V2DI
 276             (mult:V2DI
 277               (sign_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
 278               (sign_extend:V2DI (match_operand:V2SI 2 "register_operand" "y")))
 279             (const_int 32))))]
 280   "TARGET_REALLY_IWMMXT"
 281   "wmulwsm%?\\t%0, %1, %2"
 282   [(set_attr "predicable" "yes")
 283    (set_attr "wtype" "wmulw")]
 284 )
 285
 286 (define_insn "iwmmxt_wmulwum"
 287   [(set (match_operand:V2SI                         0 "register_operand" "=y")
 288         (truncate:V2SI
 289           (lshiftrt:V2DI
 290             (mult:V2DI
 291               (zero_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
 292               (zero_extend:V2DI (match_operand:V2SI 2 "register_operand" "y")))
 293             (const_int 32))))]
 294   "TARGET_REALLY_IWMMXT"
 295   "wmulwum%?\\t%0, %1, %2"
 296   [(set_attr "predicable" "yes")
 297    (set_attr "wtype" "wmulw")]
 298 )
 299
 300 (define_insn "iwmmxt_wmulsmr"
 301   [(set (match_operand:V4HI                           0 "register_operand" "=y")
 302         (truncate:V4HI
 303           (ashiftrt:V4SI
 304             (plus:V4SI
 305               (mult:V4SI
 306                 (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
 307                 (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
 308               (const_vector:V4SI [(const_int 32768)
 309                                   (const_int 32768)
 310                                   (const_int 32768)]))
 311             (const_int 16))))]
 312   "TARGET_REALLY_IWMMXT"
 313   "wmulsmr%?\\t%0, %1, %2"
 314   [(set_attr "predicable" "yes")
 315    (set_attr "wtype" "wmul")]
 316 )
 317
 318 (define_insn "iwmmxt_wmulumr"
 319   [(set (match_operand:V4HI                           0 "register_operand" "=y")
 320         (truncate:V4HI
 321           (lshiftrt:V4SI
 322             (plus:V4SI
 323               (mult:V4SI
 324                 (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
 325                 (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
 326               (const_vector:V4SI [(const_int 32768)
 327                                   (const_int 32768)
 328                                   (const_int 32768)
 329                                   (const_int 32768)]))
 330           (const_int 16))))]
 331   "TARGET_REALLY_IWMMXT"
 332   "wmulumr%?\\t%0, %1, %2"
 333   [(set_attr "predicable" "yes")
 334    (set_attr "wtype" "wmul")]
 335 )
 336
 337 (define_insn "iwmmxt_wmulwsmr"
 338   [(set (match_operand:V2SI                           0 "register_operand" "=y")
 339         (truncate:V2SI
 340           (ashiftrt:V2DI
 341             (plus:V2DI
 342               (mult:V2DI
 343                 (sign_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
 344                 (sign_extend:V2DI (match_operand:V2SI 2 "register_operand" "y")))
 345               (const_vector:V2DI [(const_int 2147483648)
 346                                   (const_int 2147483648)]))
 347             (const_int 32))))]
 348   "TARGET_REALLY_IWMMXT"
 349   "wmulwsmr%?\\t%0, %1, %2"
 350   [(set_attr "predicable" "yes")
 351    (set_attr "wtype" "wmul")]
 352 )
 353
 354 (define_insn "iwmmxt_wmulwumr"
 355   [(set (match_operand:V2SI                           0 "register_operand" "=y")
 356         (truncate:V2SI
 357           (lshiftrt:V2DI
 358             (plus:V2DI
 359               (mult:V2DI
 360                 (zero_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
 361                 (zero_extend:V2DI (match_operand:V2SI 2 "register_operand" "y")))
 362               (const_vector:V2DI [(const_int 2147483648)
 363                                   (const_int 2147483648)]))
 364             (const_int 32))))]
 365   "TARGET_REALLY_IWMMXT"
 366   "wmulwumr%?\\t%0, %1, %2"
 367   [(set_attr "predicable" "yes")
 368    (set_attr "wtype" "wmulw")]
 369 )
 370
 371 (define_insn "iwmmxt_wmulwl"
 372   [(set (match_operand:V2SI   0 "register_operand" "=y")
 373         (mult:V2SI
 374           (match_operand:V2SI 1 "register_operand" "y")
 375           (match_operand:V2SI 2 "register_operand" "y")))]
 376   "TARGET_REALLY_IWMMXT"
 377   "wmulwl%?\\t%0, %1, %2"
 378   [(set_attr "predicable" "yes")
 379    (set_attr "wtype" "wmulw")]
 380 )
 381
 382 (define_insn "iwmmxt_wqmulm"
 383   [(set (match_operand:V4HI            0 "register_operand" "=y")
 384         (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
 385                       (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WQMULM))]
 386   "TARGET_REALLY_IWMMXT"
 387   "wqmulm%?\\t%0, %1, %2"
 388   [(set_attr "predicable" "yes")
 389    (set_attr "wtype" "wqmulm")]
 390 )
 391
 392 (define_insn "iwmmxt_wqmulwm"
 393   [(set (match_operand:V2SI               0 "register_operand" "=y")
 394         (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "y")
 395                       (match_operand:V2SI 2 "register_operand" "y")] UNSPEC_WQMULWM))]
 396   "TARGET_REALLY_IWMMXT"
 397   "wqmulwm%?\\t%0, %1, %2"
 398   [(set_attr "predicable" "yes")
 399    (set_attr "wtype" "wqmulwm")]
 400 )
 401
 402 (define_insn "iwmmxt_wqmulmr"
 403   [(set (match_operand:V4HI               0 "register_operand" "=y")
 404         (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
 405                       (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WQMULMR))]
 406   "TARGET_REALLY_IWMMXT"
 407   "wqmulmr%?\\t%0, %1, %2"
 408   [(set_attr "predicable" "yes")
 409    (set_attr "wtype" "wqmulm")]
 410 )
 411
 412 (define_insn "iwmmxt_wqmulwmr"
 413   [(set (match_operand:V2SI            0 "register_operand" "=y")
 414         (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "y")
 415                       (match_operand:V2SI 2 "register_operand" "y")] UNSPEC_WQMULWMR))]
 416   "TARGET_REALLY_IWMMXT"
 417   "wqmulwmr%?\\t%0, %1, %2"
 418   [(set_attr "predicable" "yes")
 419    (set_attr "wtype" "wqmulwm")]
 420 )
 421
 422 (define_insn "iwmmxt_waddbhusm"
 423   [(set (match_operand:V8QI                          0 "register_operand" "=y")
 424         (vec_concat:V8QI
 425           (const_vector:V4QI [(const_int 0) (const_int 0) (const_int 0) (const_int 0)])
 426           (us_truncate:V4QI
 427             (ss_plus:V4HI
 428               (match_operand:V4HI                    1 "register_operand" "y")
 429               (zero_extend:V4HI
 430                 (vec_select:V4QI (match_operand:V8QI 2 "register_operand" "y")
 431                                  (parallel [(const_int 4) (const_int 5) (const_int 6) (const_int 7)])))))))]
 432   "TARGET_REALLY_IWMMXT"
 433   "waddbhusm%?\\t%0, %1, %2"
 434   [(set_attr "predicable" "yes")
 435    (set_attr "wtype" "waddbhus")]
 436 )
 437
 438 (define_insn "iwmmxt_waddbhusl"
 439   [(set (match_operand:V8QI                          0 "register_operand" "=y")
 440         (vec_concat:V8QI
 441           (us_truncate:V4QI
 442             (ss_plus:V4HI
 443               (match_operand:V4HI                    1 "register_operand" "y")
 444               (zero_extend:V4HI
 445                 (vec_select:V4QI (match_operand:V8QI 2 "register_operand" "y")
 446                                  (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)])))))
 447           (const_vector:V4QI [(const_int 0) (const_int 0) (const_int 0) (const_int 0)])))]
 448   "TARGET_REALLY_IWMMXT"
 449   "waddbhusl%?\\t%0, %1, %2"
 450   [(set_attr "predicable" "yes")
 451    (set_attr "wtype" "waddbhus")]
 452 )
 453
 454 (define_insn "iwmmxt_wqmiabb"
 455   [(set (match_operand:V2SI                                  0 "register_operand" "=y")
 456         (unspec:V2SI [(match_operand:V2SI                    1 "register_operand" "0")
 457                       (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 0))
 458                       (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 32))
 459                       (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 0))
 460                       (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 32))] UNSPEC_WQMIAxy))]
 461   "TARGET_REALLY_IWMMXT"
 462   "wqmiabb%?\\t%0, %2, %3"
 463   [(set_attr "predicable" "yes")
 464    (set_attr "wtype" "wqmiaxy")]
 465 )
 466
 467 (define_insn "iwmmxt_wqmiabt"
 468   [(set (match_operand:V2SI                                  0 "register_operand" "=y")
 469         (unspec:V2SI [(match_operand:V2SI                    1 "register_operand" "0")
 470                       (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 0))
 471                       (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 32))
 472                       (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 16))
 473                       (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 48))] UNSPEC_WQMIAxy))]
 474   "TARGET_REALLY_IWMMXT"
 475   "wqmiabt%?\\t%0, %2, %3"
 476   [(set_attr "predicable" "yes")
 477    (set_attr "wtype" "wqmiaxy")]
 478 )
 479
 480 (define_insn "iwmmxt_wqmiatb"
 481   [(set (match_operand:V2SI                                  0 "register_operand" "=y")
 482         (unspec:V2SI [(match_operand:V2SI                    1 "register_operand" "0")
 483                       (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 16))
 484                       (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 48))
 485                       (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 0))
 486                       (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 32))] UNSPEC_WQMIAxy))]
 487   "TARGET_REALLY_IWMMXT"
 488   "wqmiatb%?\\t%0, %2, %3"
 489   [(set_attr "predicable" "yes")
 490    (set_attr "wtype" "wqmiaxy")]
 491 )
 492
 493 (define_insn "iwmmxt_wqmiatt"
 494   [(set (match_operand:V2SI                                  0 "register_operand" "=y")
 495         (unspec:V2SI [(match_operand:V2SI                    1 "register_operand" "0")
 496                       (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 16))
 497                       (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 48))
 498                       (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 16))
 499                       (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 48))] UNSPEC_WQMIAxy))]
 500   "TARGET_REALLY_IWMMXT"
 501   "wqmiatt%?\\t%0, %2, %3"
 502   [(set_attr "predicable" "yes")
 503    (set_attr "wtype" "wqmiaxy")]
 504 )
 505
 506 (define_insn "iwmmxt_wqmiabbn"
 507   [(set (match_operand:V2SI                                  0 "register_operand" "=y")
 508         (unspec:V2SI [(match_operand:V2SI                    1 "register_operand" "0")
 509                       (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 0))
 510                       (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 32))
 511                       (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 0))
 512                       (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 32))] UNSPEC_WQMIAxyn))]
 513   "TARGET_REALLY_IWMMXT"
 514   "wqmiabbn%?\\t%0, %2, %3"
 515   [(set_attr "predicable" "yes")
 516    (set_attr "wtype" "wqmiaxy")]
 517 )
 518
 519 (define_insn "iwmmxt_wqmiabtn"
 520   [(set (match_operand:V2SI                                  0 "register_operand" "=y")
 521         (unspec:V2SI [(match_operand:V2SI                    1 "register_operand" "0")
 522                       (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 0))
 523                       (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 32))
 524                       (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 16))
 525                       (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 48))] UNSPEC_WQMIAxyn))]
 526   "TARGET_REALLY_IWMMXT"
 527   "wqmiabtn%?\\t%0, %2, %3"
 528   [(set_attr "predicable" "yes")
 529    (set_attr "wtype" "wqmiaxy")]
 530 )
 531
 532 (define_insn "iwmmxt_wqmiatbn"
 533   [(set (match_operand:V2SI                                  0 "register_operand" "=y")
 534         (unspec:V2SI [(match_operand:V2SI                    1 "register_operand" "0")
 535                       (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 16))
 536                       (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 48))
 537                       (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 0))
 538                       (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 32))] UNSPEC_WQMIAxyn))]
 539   "TARGET_REALLY_IWMMXT"
 540   "wqmiatbn%?\\t%0, %2, %3"
 541   [(set_attr "predicable" "yes")
 542    (set_attr "wtype" "wqmiaxy")]
 543 )
 544
 545 (define_insn "iwmmxt_wqmiattn"
 546  [(set (match_operand:V2SI                                  0 "register_operand" "=y")
 547        (unspec:V2SI [(match_operand:V2SI                    1 "register_operand" "0")
 548                      (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 16))
 549                      (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 48))
 550                      (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 16))
 551                      (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 48))] UNSPEC_WQMIAxyn))]
 552   "TARGET_REALLY_IWMMXT"
 553   "wqmiattn%?\\t%0, %2, %3"
 554   [(set_attr "predicable" "yes")
 555    (set_attr "wtype" "wqmiaxy")]
 556 )
 557
 558 (define_insn "iwmmxt_wmiabb"
 559   [(set (match_operand:DI                                 0 "register_operand" "=y")
 560         (plus:DI (match_operand:DI                        1 "register_operand" "0")
 561                  (plus:DI
 562                    (mult:DI
 563                      (sign_extend:DI
 564                        (vec_select:HI (match_operand:V4HI 2 "register_operand" "y")
 565                                       (parallel [(const_int 0)])))
 566                      (sign_extend:DI
 567                        (vec_select:HI (match_operand:V4HI 3 "register_operand" "y")
 568                                       (parallel [(const_int 0)]))))
 569                    (mult:DI
 570                      (sign_extend:DI
 571                        (vec_select:HI (match_dup 2)
 572                                       (parallel [(const_int 2)])))
 573                      (sign_extend:DI
 574                        (vec_select:HI (match_dup 3)
 575                                       (parallel [(const_int 2)])))))))]
 576   "TARGET_REALLY_IWMMXT"
 577   "wmiabb%?\\t%0, %2, %3"
 578   [(set_attr "predicable" "yes")
 579    (set_attr "wtype" "wmiaxy")]
 580 )
 581
 582 (define_insn "iwmmxt_wmiabt"
 583   [(set (match_operand:DI                                 0 "register_operand" "=y")
 584         (plus:DI (match_operand:DI                        1 "register_operand" "0")
 585                  (plus:DI
 586                    (mult:DI
 587                      (sign_extend:DI
 588                        (vec_select:HI (match_operand:V4HI 2 "register_operand" "y")
 589                                       (parallel [(const_int 0)])))
 590                      (sign_extend:DI
 591                        (vec_select:HI (match_operand:V4HI 3 "register_operand" "y")
 592                                       (parallel [(const_int 1)]))))
 593                    (mult:DI
 594                      (sign_extend:DI
 595                        (vec_select:HI (match_dup 2)
 596                                       (parallel [(const_int 2)])))
 597                      (sign_extend:DI
 598                        (vec_select:HI (match_dup 3)
 599                                       (parallel [(const_int 3)])))))))]
 600   "TARGET_REALLY_IWMMXT"
 601   "wmiabt%?\\t%0, %2, %3"
 602   [(set_attr "predicable" "yes")
 603    (set_attr "wtype" "wmiaxy")]
 604 )
 605
 606 (define_insn "iwmmxt_wmiatb"
 607   [(set (match_operand:DI                                 0 "register_operand" "=y")
 608         (plus:DI (match_operand:DI                        1 "register_operand" "0")
 609                  (plus:DI
 610                    (mult:DI
 611                      (sign_extend:DI
 612                        (vec_select:HI (match_operand:V4HI 2 "register_operand" "y")
 613                                       (parallel [(const_int 1)])))
 614                      (sign_extend:DI
 615                        (vec_select:HI (match_operand:V4HI 3 "register_operand" "y")
 616                                       (parallel [(const_int 0)]))))
 617                    (mult:DI
 618                      (sign_extend:DI
 619                        (vec_select:HI (match_dup 2)
 620                                       (parallel [(const_int 3)])))
 621                      (sign_extend:DI
 622                        (vec_select:HI (match_dup 3)
 623                                       (parallel [(const_int 2)])))))))]
 624   "TARGET_REALLY_IWMMXT"
 625   "wmiatb%?\\t%0, %2, %3"
 626   [(set_attr "predicable" "yes")
 627    (set_attr "wtype" "wmiaxy")]
 628 )
 629
 630 (define_insn "iwmmxt_wmiatt"
 631   [(set (match_operand:DI                          0 "register_operand" "=y")
 632         (plus:DI (match_operand:DI                 1 "register_operand" "0")
 633           (plus:DI
 634             (mult:DI
 635               (sign_extend:DI
 636                 (vec_select:HI (match_operand:V4HI 2 "register_operand" "y")
 637                                (parallel [(const_int 1)])))
 638               (sign_extend:DI
 639                 (vec_select:HI (match_operand:V4HI 3 "register_operand" "y")
 640                                (parallel [(const_int 1)]))))
 641             (mult:DI
 642               (sign_extend:DI
 643                 (vec_select:HI (match_dup 2)
 644                                (parallel [(const_int 3)])))
 645               (sign_extend:DI
 646                 (vec_select:HI (match_dup 3)
 647                                (parallel [(const_int 3)])))))))]
 648   "TARGET_REALLY_IWMMXT"
 649   "wmiatt%?\\t%0, %2, %3"
 650   [(set_attr "predicable" "yes")
 651    (set_attr "wtype" "wmiaxy")]
 652 )
 653
 654 (define_insn "iwmmxt_wmiabbn"
 655   [(set (match_operand:DI                                  0 "register_operand" "=y")
 656         (minus:DI (match_operand:DI                        1 "register_operand" "0")
 657                   (plus:DI
 658                     (mult:DI
 659                       (sign_extend:DI
 660                         (vec_select:HI (match_operand:V4HI 2 "register_operand" "y")
 661                                        (parallel [(const_int 0)])))
 662                       (sign_extend:DI
 663                         (vec_select:HI (match_operand:V4HI 3 "register_operand" "y")
 664                                        (parallel [(const_int 0)]))))
 665                     (mult:DI
 666                       (sign_extend:DI
 667                         (vec_select:HI (match_dup 2)
 668                                        (parallel [(const_int 2)])))
 669                       (sign_extend:DI
 670                         (vec_select:HI (match_dup 3)
 671                                        (parallel [(const_int 2)])))))))]
 672   "TARGET_REALLY_IWMMXT"
 673   "wmiabbn%?\\t%0, %2, %3"
 674   [(set_attr "predicable" "yes")
 675    (set_attr "wtype" "wmiaxy")]
 676 )
 677
 678 (define_insn "iwmmxt_wmiabtn"
 679   [(set (match_operand:DI                                  0 "register_operand" "=y")
 680         (minus:DI (match_operand:DI                        1 "register_operand" "0")
 681                   (plus:DI
 682                     (mult:DI
 683                       (sign_extend:DI
 684                         (vec_select:HI (match_operand:V4HI 2 "register_operand" "y")
 685                                        (parallel [(const_int 0)])))
 686                       (sign_extend:DI
 687                         (vec_select:HI (match_operand:V4HI 3 "register_operand" "y")
 688                                        (parallel [(const_int 1)]))))
 689                     (mult:DI
 690                       (sign_extend:DI
 691                         (vec_select:HI (match_dup 2)
 692                                        (parallel [(const_int 2)])))
 693                       (sign_extend:DI
 694                         (vec_select:HI (match_dup 3)
 695                                        (parallel [(const_int 3)])))))))]
 696   "TARGET_REALLY_IWMMXT"
 697   "wmiabtn%?\\t%0, %2, %3"
 698   [(set_attr "predicable" "yes")
 699    (set_attr "wtype" "wmiaxy")]
 700 )
 701
 702 (define_insn "iwmmxt_wmiatbn"
 703   [(set (match_operand:DI                                  0 "register_operand" "=y")
 704         (minus:DI (match_operand:DI                        1 "register_operand" "0")
 705                   (plus:DI
 706                     (mult:DI
 707                       (sign_extend:DI
 708                         (vec_select:HI (match_operand:V4HI 2 "register_operand" "y")
 709                                        (parallel [(const_int 1)])))
 710                       (sign_extend:DI
 711                         (vec_select:HI (match_operand:V4HI 3 "register_operand" "y")
 712                                        (parallel [(const_int 0)]))))
 713                     (mult:DI
 714                       (sign_extend:DI
 715                         (vec_select:HI (match_dup 2)
 716                                        (parallel [(const_int 3)])))
 717                       (sign_extend:DI
 718                         (vec_select:HI (match_dup 3)
 719                                        (parallel [(const_int 2)])))))))]
 720   "TARGET_REALLY_IWMMXT"
 721   "wmiatbn%?\\t%0, %2, %3"
 722   [(set_attr "predicable" "yes")
 723    (set_attr "wtype" "wmiaxy")]
 724 )
 725
 726 (define_insn "iwmmxt_wmiattn"
 727   [(set (match_operand:DI                                  0 "register_operand" "=y")
 728         (minus:DI (match_operand:DI                        1 "register_operand" "0")
 729                   (plus:DI
 730                     (mult:DI
 731                       (sign_extend:DI
 732                         (vec_select:HI (match_operand:V4HI 2 "register_operand" "y")
 733                                        (parallel [(const_int 1)])))
 734                       (sign_extend:DI
 735                         (vec_select:HI (match_operand:V4HI 3 "register_operand" "y")
 736                                        (parallel [(const_int 1)]))))
 737                     (mult:DI
 738                       (sign_extend:DI
 739                         (vec_select:HI (match_dup 2)
 740                                        (parallel [(const_int 3)])))
 741                       (sign_extend:DI
 742                         (vec_select:HI (match_dup 3)
 743                                        (parallel [(const_int 3)])))))))]
 744   "TARGET_REALLY_IWMMXT"
 745   "wmiattn%?\\t%0, %2, %3"
 746   [(set_attr "predicable" "yes")
 747    (set_attr "wtype" "wmiaxy")]
 748 )
 749
 750 (define_insn "iwmmxt_wmiawbb"
 751   [(set (match_operand:DI       0 "register_operand" "=y")
 752         (plus:DI
 753           (match_operand:DI      1 "register_operand" "0")
 754           (mult:DI
 755             (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 0)])))
 756             (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 0)]))))))]
 757   "TARGET_REALLY_IWMMXT"
 758   "wmiawbb%?\\t%0, %2, %3"
 759   [(set_attr "predicable" "yes")
 760    (set_attr "wtype" "wmiawxy")]
 761 )
 762
 763 (define_insn "iwmmxt_wmiawbt"
 764   [(set (match_operand:DI                                      0 "register_operand" "=y")
 765         (plus:DI
 766           (match_operand:DI                                    1 "register_operand" "0")
 767           (mult:DI
 768             (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 0)])))
 769             (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 1)]))))))]
 770   "TARGET_REALLY_IWMMXT"
 771   "wmiawbt%?\\t%0, %2, %3"
 772   [(set_attr "predicable" "yes")
 773    (set_attr "wtype" "wmiawxy")]
 774 )
 775
 776 (define_insn "iwmmxt_wmiawtb"
 777   [(set (match_operand:DI                                      0 "register_operand" "=y")
 778         (plus:DI
 779           (match_operand:DI                                    1 "register_operand" "0")
 780           (mult:DI
 781             (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 1)])))
 782             (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 0)]))))))]
 783   "TARGET_REALLY_IWMMXT"
 784   "wmiawtb%?\\t%0, %2, %3"
 785   [(set_attr "predicable" "yes")
 786    (set_attr "wtype" "wmiawxy")]
 787 )
 788
 789 (define_insn "iwmmxt_wmiawtt"
 790 [(set (match_operand:DI                                      0 "register_operand" "=y")
 791       (plus:DI
 792         (match_operand:DI                                    1 "register_operand" "0")
 793         (mult:DI
 794           (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 1)])))
 795           (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 1)]))))))]
 796   "TARGET_REALLY_IWMMXT"
 797   "wmiawtt%?\\t%0, %2, %3"
 798   [(set_attr "predicable" "yes")
 799    (set_attr "wtype" "wmiawxy")]
 800 )
 801
 802 (define_insn "iwmmxt_wmiawbbn"
 803   [(set (match_operand:DI                                      0 "register_operand" "=y")
 804         (minus:DI
 805           (match_operand:DI                                    1 "register_operand" "0")
 806           (mult:DI
 807             (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 0)])))
 808             (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 0)]))))))]
 809   "TARGET_REALLY_IWMMXT"
 810   "wmiawbbn%?\\t%0, %2, %3"
 811   [(set_attr "predicable" "yes")
 812    (set_attr "wtype" "wmiawxy")]
 813 )
 814
 815 (define_insn "iwmmxt_wmiawbtn"
 816   [(set (match_operand:DI                                      0 "register_operand" "=y")
 817         (minus:DI
 818           (match_operand:DI                                    1 "register_operand" "0")
 819           (mult:DI
 820             (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 0)])))
 821             (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 1)]))))))]
 822   "TARGET_REALLY_IWMMXT"
 823   "wmiawbtn%?\\t%0, %2, %3"
 824   [(set_attr "predicable" "yes")
 825    (set_attr "wtype" "wmiawxy")]
 826 )
 827
 828 (define_insn "iwmmxt_wmiawtbn"
 829   [(set (match_operand:DI                                      0 "register_operand" "=y")
 830         (minus:DI
 831           (match_operand:DI                                    1 "register_operand" "0")
 832           (mult:DI
 833             (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 1)])))
 834             (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 0)]))))))]
 835   "TARGET_REALLY_IWMMXT"
 836   "wmiawtbn%?\\t%0, %2, %3"
 837   [(set_attr "predicable" "yes")
 838    (set_attr "wtype" "wmiawxy")]
 839 )
 840
 841 (define_insn "iwmmxt_wmiawttn"
 842   [(set (match_operand:DI                                      0 "register_operand" "=y")
 843         (minus:DI
 844           (match_operand:DI                                    1 "register_operand" "0")
 845           (mult:DI
 846             (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 1)])))
 847             (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 1)]))))))]
 848   "TARGET_REALLY_IWMMXT"
 849   "wmiawttn%?\\t%0, %2, %3"
 850   [(set_attr "predicable" "yes")
 851    (set_attr "wtype" "wmiawxy")]
 852 )
 853
 854 (define_insn "iwmmxt_wmerge"
 855   [(set (match_operand:DI         0 "register_operand" "=y")
 856         (ior:DI
 857           (ashift:DI
 858             (match_operand:DI     2 "register_operand" "y")
 859             (minus:SI
 860               (const_int 64)
 861               (mult:SI
 862                 (match_operand:SI 3 "immediate_operand" "i")
 863                 (const_int 8))))
 864           (lshiftrt:DI
 865             (ashift:DI
 866               (match_operand:DI   1 "register_operand" "y")
 867               (mult:SI
 868                 (match_dup 3)
 869                 (const_int 8)))
 870             (mult:SI
 871               (match_dup 3)
 872               (const_int 8)))))]
 873   "TARGET_REALLY_IWMMXT"
 874   "wmerge%?\\t%0, %1, %2, %3"
 875   [(set_attr "predicable" "yes")
 876    (set_attr "wtype" "wmerge")]
 877 )
 878
 879 (define_insn "iwmmxt_tandc<mode>3"
 880   [(set (reg:CC CC_REGNUM)
 881         (subreg:CC (unspec:VMMX [(const_int 0)] UNSPEC_TANDC) 0))
 882    (unspec:CC [(reg:SI 15)] UNSPEC_TANDC)]
 883   "TARGET_REALLY_IWMMXT"
 884   "tandc<MMX_char>%?\\t r15"
 885   [(set_attr "predicable" "yes")
 886    (set_attr "wtype" "tandc")]
 887 )
 888
 889 (define_insn "iwmmxt_torc<mode>3"
 890   [(set (reg:CC CC_REGNUM)
 891         (subreg:CC (unspec:VMMX [(const_int 0)] UNSPEC_TORC) 0))
 892    (unspec:CC [(reg:SI 15)] UNSPEC_TORC)]
 893   "TARGET_REALLY_IWMMXT"
 894   "torc<MMX_char>%?\\t r15"
 895   [(set_attr "predicable" "yes")
 896    (set_attr "wtype" "torc")]
 897 )
 898
 899 (define_insn "iwmmxt_torvsc<mode>3"
 900   [(set (reg:CC CC_REGNUM)
 901         (subreg:CC (unspec:VMMX [(const_int 0)] UNSPEC_TORVSC) 0))
 902    (unspec:CC [(reg:SI 15)] UNSPEC_TORVSC)]
 903   "TARGET_REALLY_IWMMXT"
 904   "torvsc<MMX_char>%?\\t r15"
 905   [(set_attr "predicable" "yes")
 906    (set_attr "wtype" "torvsc")]
 907 )
 908
 909 (define_insn "iwmmxt_textrc<mode>3"
 910   [(set (reg:CC CC_REGNUM)
 911         (subreg:CC (unspec:VMMX [(const_int 0)
 912                                  (match_operand:SI 0 "immediate_operand" "i")] UNSPEC_TEXTRC) 0))
 913    (unspec:CC [(reg:SI 15)] UNSPEC_TEXTRC)]
 914   "TARGET_REALLY_IWMMXT"
 915   "textrc<MMX_char>%?\\t r15, %0"
 916   [(set_attr "predicable" "yes")
 917    (set_attr "wtype" "textrc")]
 918 )