gcc/config/arm/ldmstm.md

   1 /* ARM ldm/stm instruction patterns.  This file was automatically generated
   2    using arm-ldmstm.ml.  Please do not edit manually.
   3
   4    Copyright (C) 2010-2017 Free Software Foundation, Inc.
   5    Contributed by CodeSourcery.
   6
   7    This file is part of GCC.
   8
   9    GCC is free software; you can redistribute it and/or modify it
  10    under the terms of the GNU General Public License as published
  11    by the Free Software Foundation; either version 3, or (at your
  12    option) any later version.
  13
  14    GCC is distributed in the hope that it will be useful, but WITHOUT
  15    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  17    License for more details.
  18
  19    You should have received a copy of the GNU General Public License and
  20    a copy of the GCC Runtime Library Exception along with this program;
  21    see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
  22    <http://www.gnu.org/licenses/>.  */
  23
  24 (define_insn "*ldm4_"
  25   [(match_parallel 0 "load_multiple_operation"
  26     [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
  27           (mem:SI (match_operand:SI 5 "s_register_operand" "rk")))
  28      (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
  29           (mem:SI (plus:SI (match_dup 5)
  30                   (const_int 4))))
  31      (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
  32           (mem:SI (plus:SI (match_dup 5)
  33                   (const_int 8))))
  34      (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
  35           (mem:SI (plus:SI (match_dup 5)
  36                   (const_int 12))))])]
  37   "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
  38   "ldm%?\t%5, {%1, %2, %3, %4}"
  39   [(set_attr "type" "load_16")
  40    (set_attr "predicable" "yes")
  41    (set_attr "predicable_short_it" "no")])
  42
  43 (define_insn "*thumb_ldm4_ia"
  44   [(match_parallel 0 "load_multiple_operation"
  45     [(set (match_operand:SI 1 "low_register_operand" "")
  46           (mem:SI (match_operand:SI 5 "s_register_operand" "l")))
  47      (set (match_operand:SI 2 "low_register_operand" "")
  48           (mem:SI (plus:SI (match_dup 5)
  49                   (const_int 4))))
  50      (set (match_operand:SI 3 "low_register_operand" "")
  51           (mem:SI (plus:SI (match_dup 5)
  52                   (const_int 8))))
  53      (set (match_operand:SI 4 "low_register_operand" "")
  54           (mem:SI (plus:SI (match_dup 5)
  55                   (const_int 12))))])]
  56   "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
  57   "ldmia\t%5, {%1, %2, %3, %4}"
  58   [(set_attr "type" "load_16")])
  59
  60 (define_insn "*ldm4_ia_update"
  61   [(match_parallel 0 "load_multiple_operation"
  62     [(set (match_operand:SI 5 "s_register_operand" "+&rk")
  63           (plus:SI (match_dup 5) (const_int 16)))
  64      (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
  65           (mem:SI (match_dup 5)))
  66      (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
  67           (mem:SI (plus:SI (match_dup 5)
  68                   (const_int 4))))
  69      (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
  70           (mem:SI (plus:SI (match_dup 5)
  71                   (const_int 8))))
  72      (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
  73           (mem:SI (plus:SI (match_dup 5)
  74                   (const_int 12))))])]
  75   "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
  76   "ldmia%?\t%5!, {%1, %2, %3, %4}"
  77   [(set_attr "type" "load_16")
  78    (set_attr "predicable" "yes")
  79    (set_attr "predicable_short_it" "no")])
  80
  81 (define_insn "*thumb_ldm4_ia_update"
  82   [(match_parallel 0 "load_multiple_operation"
  83     [(set (match_operand:SI 5 "s_register_operand" "+&l")
  84           (plus:SI (match_dup 5) (const_int 16)))
  85      (set (match_operand:SI 1 "low_register_operand" "")
  86           (mem:SI (match_dup 5)))
  87      (set (match_operand:SI 2 "low_register_operand" "")
  88           (mem:SI (plus:SI (match_dup 5)
  89                   (const_int 4))))
  90      (set (match_operand:SI 3 "low_register_operand" "")
  91           (mem:SI (plus:SI (match_dup 5)
  92                   (const_int 8))))
  93      (set (match_operand:SI 4 "low_register_operand" "")
  94           (mem:SI (plus:SI (match_dup 5)
  95                   (const_int 12))))])]
  96   "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5"
  97   "ldmia\t%5!, {%1, %2, %3, %4}"
  98   [(set_attr "type" "load_16")])
  99
 100 (define_insn "*stm4_"
 101   [(match_parallel 0 "store_multiple_operation"
 102     [(set (mem:SI (match_operand:SI 5 "s_register_operand" "rk"))
 103           (match_operand:SI 1 "arm_hard_general_register_operand" ""))
 104      (set (mem:SI (plus:SI (match_dup 5) (const_int 4)))
 105           (match_operand:SI 2 "arm_hard_general_register_operand" ""))
 106      (set (mem:SI (plus:SI (match_dup 5) (const_int 8)))
 107           (match_operand:SI 3 "arm_hard_general_register_operand" ""))
 108      (set (mem:SI (plus:SI (match_dup 5) (const_int 12)))
 109           (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
 110   "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
 111   "stm%?\t%5, {%1, %2, %3, %4}"
 112   [(set_attr "type" "store_16")
 113    (set_attr "predicable" "yes")
 114    (set_attr "predicable_short_it" "no")])
 115
 116 (define_insn "*stm4_ia_update"
 117   [(match_parallel 0 "store_multiple_operation"
 118     [(set (match_operand:SI 5 "s_register_operand" "+&rk")
 119           (plus:SI (match_dup 5) (const_int 16)))
 120      (set (mem:SI (match_dup 5))
 121           (match_operand:SI 1 "arm_hard_general_register_operand" ""))
 122      (set (mem:SI (plus:SI (match_dup 5) (const_int 4)))
 123           (match_operand:SI 2 "arm_hard_general_register_operand" ""))
 124      (set (mem:SI (plus:SI (match_dup 5) (const_int 8)))
 125           (match_operand:SI 3 "arm_hard_general_register_operand" ""))
 126      (set (mem:SI (plus:SI (match_dup 5) (const_int 12)))
 127           (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
 128   "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
 129   "stmia%?\t%5!, {%1, %2, %3, %4}"
 130   [(set_attr "type" "store_16")
 131    (set_attr "predicable" "yes")
 132    (set_attr "predicable_short_it" "no")])
 133
 134 (define_insn "*thumb_stm4_ia_update"
 135   [(match_parallel 0 "store_multiple_operation"
 136     [(set (match_operand:SI 5 "s_register_operand" "+&l")
 137           (plus:SI (match_dup 5) (const_int 16)))
 138      (set (mem:SI (match_dup 5))
 139           (match_operand:SI 1 "low_register_operand" ""))
 140      (set (mem:SI (plus:SI (match_dup 5) (const_int 4)))
 141           (match_operand:SI 2 "low_register_operand" ""))
 142      (set (mem:SI (plus:SI (match_dup 5) (const_int 8)))
 143           (match_operand:SI 3 "low_register_operand" ""))
 144      (set (mem:SI (plus:SI (match_dup 5) (const_int 12)))
 145           (match_operand:SI 4 "low_register_operand" ""))])]
 146   "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5"
 147   "stmia\t%5!, {%1, %2, %3, %4}"
 148   [(set_attr "type" "store_16")])
 149
 150 (define_insn "*ldm4_ib"
 151   [(match_parallel 0 "load_multiple_operation"
 152     [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
 153           (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk")
 154                   (const_int 4))))
 155      (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
 156           (mem:SI (plus:SI (match_dup 5)
 157                   (const_int 8))))
 158      (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
 159           (mem:SI (plus:SI (match_dup 5)
 160                   (const_int 12))))
 161      (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
 162           (mem:SI (plus:SI (match_dup 5)
 163                   (const_int 16))))])]
 164   "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
 165   "ldmib%?\t%5, {%1, %2, %3, %4}"
 166   [(set_attr "type" "load_16")
 167    (set_attr "predicable" "yes")])
 168
 169 (define_insn "*ldm4_ib_update"
 170   [(match_parallel 0 "load_multiple_operation"
 171     [(set (match_operand:SI 5 "s_register_operand" "+&rk")
 172           (plus:SI (match_dup 5) (const_int 16)))
 173      (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
 174           (mem:SI (plus:SI (match_dup 5)
 175                   (const_int 4))))
 176      (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
 177           (mem:SI (plus:SI (match_dup 5)
 178                   (const_int 8))))
 179      (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
 180           (mem:SI (plus:SI (match_dup 5)
 181                   (const_int 12))))
 182      (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
 183           (mem:SI (plus:SI (match_dup 5)
 184                   (const_int 16))))])]
 185   "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
 186   "ldmib%?\t%5!, {%1, %2, %3, %4}"
 187   [(set_attr "type" "load_16")
 188    (set_attr "predicable" "yes")])
 189
 190 (define_insn "*stm4_ib"
 191   [(match_parallel 0 "store_multiple_operation"
 192     [(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int 4)))
 193           (match_operand:SI 1 "arm_hard_general_register_operand" ""))
 194      (set (mem:SI (plus:SI (match_dup 5) (const_int 8)))
 195           (match_operand:SI 2 "arm_hard_general_register_operand" ""))
 196      (set (mem:SI (plus:SI (match_dup 5) (const_int 12)))
 197           (match_operand:SI 3 "arm_hard_general_register_operand" ""))
 198      (set (mem:SI (plus:SI (match_dup 5) (const_int 16)))
 199           (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
 200   "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
 201   "stmib%?\t%5, {%1, %2, %3, %4}"
 202   [(set_attr "type" "store_16")
 203    (set_attr "predicable" "yes")])
 204
 205 (define_insn "*stm4_ib_update"
 206   [(match_parallel 0 "store_multiple_operation"
 207     [(set (match_operand:SI 5 "s_register_operand" "+&rk")
 208           (plus:SI (match_dup 5) (const_int 16)))
 209      (set (mem:SI (plus:SI (match_dup 5) (const_int 4)))
 210           (match_operand:SI 1 "arm_hard_general_register_operand" ""))
 211      (set (mem:SI (plus:SI (match_dup 5) (const_int 8)))
 212           (match_operand:SI 2 "arm_hard_general_register_operand" ""))
 213      (set (mem:SI (plus:SI (match_dup 5) (const_int 12)))
 214           (match_operand:SI 3 "arm_hard_general_register_operand" ""))
 215      (set (mem:SI (plus:SI (match_dup 5) (const_int 16)))
 216           (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
 217   "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
 218   "stmib%?\t%5!, {%1, %2, %3, %4}"
 219   [(set_attr "type" "store_16")
 220    (set_attr "predicable" "yes")])
 221
 222 (define_insn "*ldm4_da"
 223   [(match_parallel 0 "load_multiple_operation"
 224     [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
 225           (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk")
 226                   (const_int -12))))
 227      (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
 228           (mem:SI (plus:SI (match_dup 5)
 229                   (const_int -8))))
 230      (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
 231           (mem:SI (plus:SI (match_dup 5)
 232                   (const_int -4))))
 233      (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
 234           (mem:SI (match_dup 5)))])]
 235   "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
 236   "ldmda%?\t%5, {%1, %2, %3, %4}"
 237   [(set_attr "type" "load_16")
 238    (set_attr "predicable" "yes")])
 239
 240 (define_insn "*ldm4_da_update"
 241   [(match_parallel 0 "load_multiple_operation"
 242     [(set (match_operand:SI 5 "s_register_operand" "+&rk")
 243           (plus:SI (match_dup 5) (const_int -16)))
 244      (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
 245           (mem:SI (plus:SI (match_dup 5)
 246                   (const_int -12))))
 247      (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
 248           (mem:SI (plus:SI (match_dup 5)
 249                   (const_int -8))))
 250      (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
 251           (mem:SI (plus:SI (match_dup 5)
 252                   (const_int -4))))
 253      (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
 254           (mem:SI (match_dup 5)))])]
 255   "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
 256   "ldmda%?\t%5!, {%1, %2, %3, %4}"
 257   [(set_attr "type" "load_16")
 258    (set_attr "predicable" "yes")])
 259
 260 (define_insn "*stm4_da"
 261   [(match_parallel 0 "store_multiple_operation"
 262     [(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -12)))
 263           (match_operand:SI 1 "arm_hard_general_register_operand" ""))
 264      (set (mem:SI (plus:SI (match_dup 5) (const_int -8)))
 265           (match_operand:SI 2 "arm_hard_general_register_operand" ""))
 266      (set (mem:SI (plus:SI (match_dup 5) (const_int -4)))
 267           (match_operand:SI 3 "arm_hard_general_register_operand" ""))
 268      (set (mem:SI (match_dup 5))
 269           (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
 270   "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
 271   "stmda%?\t%5, {%1, %2, %3, %4}"
 272   [(set_attr "type" "store_16")
 273    (set_attr "predicable" "yes")])
 274
 275 (define_insn "*stm4_da_update"
 276   [(match_parallel 0 "store_multiple_operation"
 277     [(set (match_operand:SI 5 "s_register_operand" "+&rk")
 278           (plus:SI (match_dup 5) (const_int -16)))
 279      (set (mem:SI (plus:SI (match_dup 5) (const_int -12)))
 280           (match_operand:SI 1 "arm_hard_general_register_operand" ""))
 281      (set (mem:SI (plus:SI (match_dup 5) (const_int -8)))
 282           (match_operand:SI 2 "arm_hard_general_register_operand" ""))
 283      (set (mem:SI (plus:SI (match_dup 5) (const_int -4)))
 284           (match_operand:SI 3 "arm_hard_general_register_operand" ""))
 285      (set (mem:SI (match_dup 5))
 286           (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
 287   "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
 288   "stmda%?\t%5!, {%1, %2, %3, %4}"
 289   [(set_attr "type" "store_16")
 290    (set_attr "predicable" "yes")])
 291
 292 (define_insn "*ldm4_db"
 293   [(match_parallel 0 "load_multiple_operation"
 294     [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
 295           (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk")
 296                   (const_int -16))))
 297      (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
 298           (mem:SI (plus:SI (match_dup 5)
 299                   (const_int -12))))
 300      (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
 301           (mem:SI (plus:SI (match_dup 5)
 302                   (const_int -8))))
 303      (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
 304           (mem:SI (plus:SI (match_dup 5)
 305                   (const_int -4))))])]
 306   "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
 307   "ldmdb%?\t%5, {%1, %2, %3, %4}"
 308   [(set_attr "type" "load_16")
 309    (set_attr "predicable" "yes")
 310    (set_attr "predicable_short_it" "no")])
 311
 312 (define_insn "*ldm4_db_update"
 313   [(match_parallel 0 "load_multiple_operation"
 314     [(set (match_operand:SI 5 "s_register_operand" "+&rk")
 315           (plus:SI (match_dup 5) (const_int -16)))
 316      (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
 317           (mem:SI (plus:SI (match_dup 5)
 318                   (const_int -16))))
 319      (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
 320           (mem:SI (plus:SI (match_dup 5)
 321                   (const_int -12))))
 322      (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
 323           (mem:SI (plus:SI (match_dup 5)
 324                   (const_int -8))))
 325      (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
 326           (mem:SI (plus:SI (match_dup 5)
 327                   (const_int -4))))])]
 328   "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
 329   "ldmdb%?\t%5!, {%1, %2, %3, %4}"
 330   [(set_attr "type" "load_16")
 331    (set_attr "predicable" "yes")
 332    (set_attr "predicable_short_it" "no")])
 333
 334 (define_insn "*stm4_db"
 335   [(match_parallel 0 "store_multiple_operation"
 336     [(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -16)))
 337           (match_operand:SI 1 "arm_hard_general_register_operand" ""))
 338      (set (mem:SI (plus:SI (match_dup 5) (const_int -12)))
 339           (match_operand:SI 2 "arm_hard_general_register_operand" ""))
 340      (set (mem:SI (plus:SI (match_dup 5) (const_int -8)))
 341           (match_operand:SI 3 "arm_hard_general_register_operand" ""))
 342      (set (mem:SI (plus:SI (match_dup 5) (const_int -4)))
 343           (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
 344   "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
 345   "stmdb%?\t%5, {%1, %2, %3, %4}"
 346   [(set_attr "type" "store_16")
 347    (set_attr "predicable" "yes")
 348    (set_attr "predicable_short_it" "no")])
 349
 350 (define_insn "*stm4_db_update"
 351   [(match_parallel 0 "store_multiple_operation"
 352     [(set (match_operand:SI 5 "s_register_operand" "+&rk")
 353           (plus:SI (match_dup 5) (const_int -16)))
 354      (set (mem:SI (plus:SI (match_dup 5) (const_int -16)))
 355           (match_operand:SI 1 "arm_hard_general_register_operand" ""))
 356      (set (mem:SI (plus:SI (match_dup 5) (const_int -12)))
 357           (match_operand:SI 2 "arm_hard_general_register_operand" ""))
 358      (set (mem:SI (plus:SI (match_dup 5) (const_int -8)))
 359           (match_operand:SI 3 "arm_hard_general_register_operand" ""))
 360      (set (mem:SI (plus:SI (match_dup 5) (const_int -4)))
 361           (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
 362   "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
 363   "stmdb%?\t%5!, {%1, %2, %3, %4}"
 364   [(set_attr "type" "store_16")
 365    (set_attr "predicable" "yes")
 366    (set_attr "predicable_short_it" "no")])
 367
 368 (define_peephole2
 369   [(set (match_operand:SI 0 "s_register_operand" "")
 370         (match_operand:SI 4 "memory_operand" ""))
 371    (set (match_operand:SI 1 "s_register_operand" "")
 372         (match_operand:SI 5 "memory_operand" ""))
 373    (set (match_operand:SI 2 "s_register_operand" "")
 374         (match_operand:SI 6 "memory_operand" ""))
 375    (set (match_operand:SI 3 "s_register_operand" "")
 376         (match_operand:SI 7 "memory_operand" ""))]
 377   ""
 378   [(const_int 0)]
 379 {
 380   if (gen_ldm_seq (operands, 4, false))
 381     DONE;
 382   else
 383     FAIL;
 384 })
 385
 386 (define_peephole2
 387   [(set (match_operand:SI 0 "s_register_operand" "")
 388         (match_operand:SI 4 "memory_operand" ""))
 389    (parallel
 390     [(set (match_operand:SI 1 "s_register_operand" "")
 391           (match_operand:SI 5 "memory_operand" ""))
 392      (set (match_operand:SI 2 "s_register_operand" "")
 393           (match_operand:SI 6 "memory_operand" ""))
 394      (set (match_operand:SI 3 "s_register_operand" "")
 395           (match_operand:SI 7 "memory_operand" ""))])]
 396   ""
 397   [(const_int 0)]
 398 {
 399   if (gen_ldm_seq (operands, 4, false))
 400     DONE;
 401   else
 402     FAIL;
 403 })
 404
 405 (define_peephole2
 406   [(set (match_operand:SI 0 "s_register_operand" "")
 407         (match_operand:SI 8 "const_int_operand" ""))
 408    (set (match_operand:SI 4 "memory_operand" "")
 409         (match_dup 0))
 410    (set (match_operand:SI 1 "s_register_operand" "")
 411         (match_operand:SI 9 "const_int_operand" ""))
 412    (set (match_operand:SI 5 "memory_operand" "")
 413         (match_dup 1))
 414    (set (match_operand:SI 2 "s_register_operand" "")
 415         (match_operand:SI 10 "const_int_operand" ""))
 416    (set (match_operand:SI 6 "memory_operand" "")
 417         (match_dup 2))
 418    (set (match_operand:SI 3 "s_register_operand" "")
 419         (match_operand:SI 11 "const_int_operand" ""))
 420    (set (match_operand:SI 7 "memory_operand" "")
 421         (match_dup 3))]
 422   ""
 423   [(const_int 0)]
 424 {
 425   if (gen_const_stm_seq (operands, 4))
 426     DONE;
 427   else
 428     FAIL;
 429 })
 430
 431 (define_peephole2
 432   [(set (match_operand:SI 0 "s_register_operand" "")
 433         (match_operand:SI 8 "const_int_operand" ""))
 434    (set (match_operand:SI 1 "s_register_operand" "")
 435         (match_operand:SI 9 "const_int_operand" ""))
 436    (set (match_operand:SI 2 "s_register_operand" "")
 437         (match_operand:SI 10 "const_int_operand" ""))
 438    (set (match_operand:SI 3 "s_register_operand" "")
 439         (match_operand:SI 11 "const_int_operand" ""))
 440    (set (match_operand:SI 4 "memory_operand" "")
 441         (match_dup 0))
 442    (set (match_operand:SI 5 "memory_operand" "")
 443         (match_dup 1))
 444    (set (match_operand:SI 6 "memory_operand" "")
 445         (match_dup 2))
 446    (set (match_operand:SI 7 "memory_operand" "")
 447         (match_dup 3))]
 448   ""
 449   [(const_int 0)]
 450 {
 451   if (gen_const_stm_seq (operands, 4))
 452     DONE;
 453   else
 454     FAIL;
 455 })
 456
 457 (define_peephole2
 458   [(set (match_operand:SI 4 "memory_operand" "")
 459         (match_operand:SI 0 "s_register_operand" ""))
 460    (set (match_operand:SI 5 "memory_operand" "")
 461         (match_operand:SI 1 "s_register_operand" ""))
 462    (set (match_operand:SI 6 "memory_operand" "")
 463         (match_operand:SI 2 "s_register_operand" ""))
 464    (set (match_operand:SI 7 "memory_operand" "")
 465         (match_operand:SI 3 "s_register_operand" ""))]
 466   ""
 467   [(const_int 0)]
 468 {
 469   if (gen_stm_seq (operands, 4))
 470     DONE;
 471   else
 472     FAIL;
 473 })
 474
 475 (define_insn "*ldm3_"
 476   [(match_parallel 0 "load_multiple_operation"
 477     [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
 478           (mem:SI (match_operand:SI 4 "s_register_operand" "rk")))
 479      (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
 480           (mem:SI (plus:SI (match_dup 4)
 481                   (const_int 4))))
 482      (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
 483           (mem:SI (plus:SI (match_dup 4)
 484                   (const_int 8))))])]
 485   "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
 486   "ldm%?\t%4, {%1, %2, %3}"
 487   [(set_attr "type" "load_12")
 488    (set_attr "predicable" "yes")
 489    (set_attr "predicable_short_it" "no")])
 490
 491 (define_insn "*thumb_ldm3_ia"
 492   [(match_parallel 0 "load_multiple_operation"
 493     [(set (match_operand:SI 1 "low_register_operand" "")
 494           (mem:SI (match_operand:SI 4 "s_register_operand" "l")))
 495      (set (match_operand:SI 2 "low_register_operand" "")
 496           (mem:SI (plus:SI (match_dup 4)
 497                   (const_int 4))))
 498      (set (match_operand:SI 3 "low_register_operand" "")
 499           (mem:SI (plus:SI (match_dup 4)
 500                   (const_int 8))))])]
 501   "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3"
 502   "ldmia\t%4, {%1, %2, %3}"
 503   [(set_attr "type" "load_12")])
 504
 505 (define_insn "*ldm3_ia_update"
 506   [(match_parallel 0 "load_multiple_operation"
 507     [(set (match_operand:SI 4 "s_register_operand" "+&rk")
 508           (plus:SI (match_dup 4) (const_int 12)))
 509      (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
 510           (mem:SI (match_dup 4)))
 511      (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
 512           (mem:SI (plus:SI (match_dup 4)
 513                   (const_int 4))))
 514      (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
 515           (mem:SI (plus:SI (match_dup 4)
 516                   (const_int 8))))])]
 517   "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
 518   "ldmia%?\t%4!, {%1, %2, %3}"
 519   [(set_attr "type" "load_12")
 520    (set_attr "predicable" "yes")
 521    (set_attr "predicable_short_it" "no")])
 522
 523 (define_insn "*thumb_ldm3_ia_update"
 524   [(match_parallel 0 "load_multiple_operation"
 525     [(set (match_operand:SI 4 "s_register_operand" "+&l")
 526           (plus:SI (match_dup 4) (const_int 12)))
 527      (set (match_operand:SI 1 "low_register_operand" "")
 528           (mem:SI (match_dup 4)))
 529      (set (match_operand:SI 2 "low_register_operand" "")
 530           (mem:SI (plus:SI (match_dup 4)
 531                   (const_int 4))))
 532      (set (match_operand:SI 3 "low_register_operand" "")
 533           (mem:SI (plus:SI (match_dup 4)
 534                   (const_int 8))))])]
 535   "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
 536   "ldmia\t%4!, {%1, %2, %3}"
 537   [(set_attr "type" "load_12")])
 538
 539 (define_insn "*stm3_"
 540   [(match_parallel 0 "store_multiple_operation"
 541     [(set (mem:SI (match_operand:SI 4 "s_register_operand" "rk"))
 542           (match_operand:SI 1 "arm_hard_general_register_operand" ""))
 543      (set (mem:SI (plus:SI (match_dup 4) (const_int 4)))
 544           (match_operand:SI 2 "arm_hard_general_register_operand" ""))
 545      (set (mem:SI (plus:SI (match_dup 4) (const_int 8)))
 546           (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
 547   "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
 548   "stm%?\t%4, {%1, %2, %3}"
 549   [(set_attr "type" "store_12")
 550    (set_attr "predicable" "yes")
 551    (set_attr "predicable_short_it" "no")])
 552
 553 (define_insn "*stm3_ia_update"
 554   [(match_parallel 0 "store_multiple_operation"
 555     [(set (match_operand:SI 4 "s_register_operand" "+&rk")
 556           (plus:SI (match_dup 4) (const_int 12)))
 557      (set (mem:SI (match_dup 4))
 558           (match_operand:SI 1 "arm_hard_general_register_operand" ""))
 559      (set (mem:SI (plus:SI (match_dup 4) (const_int 4)))
 560           (match_operand:SI 2 "arm_hard_general_register_operand" ""))
 561      (set (mem:SI (plus:SI (match_dup 4) (const_int 8)))
 562           (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
 563   "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
 564   "stmia%?\t%4!, {%1, %2, %3}"
 565   [(set_attr "type" "store_12")
 566    (set_attr "predicable" "yes")
 567    (set_attr "predicable_short_it" "no")])
 568
 569 (define_insn "*thumb_stm3_ia_update"
 570   [(match_parallel 0 "store_multiple_operation"
 571     [(set (match_operand:SI 4 "s_register_operand" "+&l")
 572           (plus:SI (match_dup 4) (const_int 12)))
 573      (set (mem:SI (match_dup 4))
 574           (match_operand:SI 1 "low_register_operand" ""))
 575      (set (mem:SI (plus:SI (match_dup 4) (const_int 4)))
 576           (match_operand:SI 2 "low_register_operand" ""))
 577      (set (mem:SI (plus:SI (match_dup 4) (const_int 8)))
 578           (match_operand:SI 3 "low_register_operand" ""))])]
 579   "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
 580   "stmia\t%4!, {%1, %2, %3}"
 581   [(set_attr "type" "store_12")])
 582
 583 (define_insn "*ldm3_ib"
 584   [(match_parallel 0 "load_multiple_operation"
 585     [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
 586           (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk")
 587                   (const_int 4))))
 588      (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
 589           (mem:SI (plus:SI (match_dup 4)
 590                   (const_int 8))))
 591      (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
 592           (mem:SI (plus:SI (match_dup 4)
 593                   (const_int 12))))])]
 594   "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
 595   "ldmib%?\t%4, {%1, %2, %3}"
 596   [(set_attr "type" "load_12")
 597    (set_attr "predicable" "yes")])
 598
 599 (define_insn "*ldm3_ib_update"
 600   [(match_parallel 0 "load_multiple_operation"
 601     [(set (match_operand:SI 4 "s_register_operand" "+&rk")
 602           (plus:SI (match_dup 4) (const_int 12)))
 603      (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
 604           (mem:SI (plus:SI (match_dup 4)
 605                   (const_int 4))))
 606      (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
 607           (mem:SI (plus:SI (match_dup 4)
 608                   (const_int 8))))
 609      (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
 610           (mem:SI (plus:SI (match_dup 4)
 611                   (const_int 12))))])]
 612   "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
 613   "ldmib%?\t%4!, {%1, %2, %3}"
 614   [(set_attr "type" "load_12")
 615    (set_attr "predicable" "yes")])
 616
 617 (define_insn "*stm3_ib"
 618   [(match_parallel 0 "store_multiple_operation"
 619     [(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int 4)))
 620           (match_operand:SI 1 "arm_hard_general_register_operand" ""))
 621      (set (mem:SI (plus:SI (match_dup 4) (const_int 8)))
 622           (match_operand:SI 2 "arm_hard_general_register_operand" ""))
 623      (set (mem:SI (plus:SI (match_dup 4) (const_int 12)))
 624           (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
 625   "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
 626   "stmib%?\t%4, {%1, %2, %3}"
 627   [(set_attr "type" "store_12")
 628    (set_attr "predicable" "yes")])
 629
 630 (define_insn "*stm3_ib_update"
 631   [(match_parallel 0 "store_multiple_operation"
 632     [(set (match_operand:SI 4 "s_register_operand" "+&rk")
 633           (plus:SI (match_dup 4) (const_int 12)))
 634      (set (mem:SI (plus:SI (match_dup 4) (const_int 4)))
 635           (match_operand:SI 1 "arm_hard_general_register_operand" ""))
 636      (set (mem:SI (plus:SI (match_dup 4) (const_int 8)))
 637           (match_operand:SI 2 "arm_hard_general_register_operand" ""))
 638      (set (mem:SI (plus:SI (match_dup 4) (const_int 12)))
 639           (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
 640   "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
 641   "stmib%?\t%4!, {%1, %2, %3}"
 642   [(set_attr "type" "store_12")
 643    (set_attr "predicable" "yes")])
 644
 645 (define_insn "*ldm3_da"
 646   [(match_parallel 0 "load_multiple_operation"
 647     [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
 648           (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk")
 649                   (const_int -8))))
 650      (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
 651           (mem:SI (plus:SI (match_dup 4)
 652                   (const_int -4))))
 653      (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
 654           (mem:SI (match_dup 4)))])]
 655   "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
 656   "ldmda%?\t%4, {%1, %2, %3}"
 657   [(set_attr "type" "load_12")
 658    (set_attr "predicable" "yes")])
 659
 660 (define_insn "*ldm3_da_update"
 661   [(match_parallel 0 "load_multiple_operation"
 662     [(set (match_operand:SI 4 "s_register_operand" "+&rk")
 663           (plus:SI (match_dup 4) (const_int -12)))
 664      (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
 665           (mem:SI (plus:SI (match_dup 4)
 666                   (const_int -8))))
 667      (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
 668           (mem:SI (plus:SI (match_dup 4)
 669                   (const_int -4))))
 670      (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
 671           (mem:SI (match_dup 4)))])]
 672   "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
 673   "ldmda%?\t%4!, {%1, %2, %3}"
 674   [(set_attr "type" "load_12")
 675    (set_attr "predicable" "yes")])
 676
 677 (define_insn "*stm3_da"
 678   [(match_parallel 0 "store_multiple_operation"
 679     [(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -8)))
 680           (match_operand:SI 1 "arm_hard_general_register_operand" ""))
 681      (set (mem:SI (plus:SI (match_dup 4) (const_int -4)))
 682           (match_operand:SI 2 "arm_hard_general_register_operand" ""))
 683      (set (mem:SI (match_dup 4))
 684           (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
 685   "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
 686   "stmda%?\t%4, {%1, %2, %3}"
 687   [(set_attr "type" "store_12")
 688    (set_attr "predicable" "yes")])
 689
 690 (define_insn "*stm3_da_update"
 691   [(match_parallel 0 "store_multiple_operation"
 692     [(set (match_operand:SI 4 "s_register_operand" "+&rk")
 693           (plus:SI (match_dup 4) (const_int -12)))
 694      (set (mem:SI (plus:SI (match_dup 4) (const_int -8)))
 695           (match_operand:SI 1 "arm_hard_general_register_operand" ""))
 696      (set (mem:SI (plus:SI (match_dup 4) (const_int -4)))
 697           (match_operand:SI 2 "arm_hard_general_register_operand" ""))
 698      (set (mem:SI (match_dup 4))
 699           (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
 700   "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
 701   "stmda%?\t%4!, {%1, %2, %3}"
 702   [(set_attr "type" "store_12")
 703    (set_attr "predicable" "yes")])
 704
 705 (define_insn "*ldm3_db"
 706   [(match_parallel 0 "load_multiple_operation"
 707     [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
 708           (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk")
 709                   (const_int -12))))
 710      (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
 711           (mem:SI (plus:SI (match_dup 4)
 712                   (const_int -8))))
 713      (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
 714           (mem:SI (plus:SI (match_dup 4)
 715                   (const_int -4))))])]
 716   "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
 717   "ldmdb%?\t%4, {%1, %2, %3}"
 718   [(set_attr "type" "load_12")
 719    (set_attr "predicable" "yes")
 720    (set_attr "predicable_short_it" "no")])
 721
 722 (define_insn "*ldm3_db_update"
 723   [(match_parallel 0 "load_multiple_operation"
 724     [(set (match_operand:SI 4 "s_register_operand" "+&rk")
 725           (plus:SI (match_dup 4) (const_int -12)))
 726      (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
 727           (mem:SI (plus:SI (match_dup 4)
 728                   (const_int -12))))
 729      (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
 730           (mem:SI (plus:SI (match_dup 4)
 731                   (const_int -8))))
 732      (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
 733           (mem:SI (plus:SI (match_dup 4)
 734                   (const_int -4))))])]
 735   "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
 736   "ldmdb%?\t%4!, {%1, %2, %3}"
 737   [(set_attr "type" "load_12")
 738    (set_attr "predicable" "yes")
 739    (set_attr "predicable_short_it" "no")])
 740
 741 (define_insn "*stm3_db"
 742   [(match_parallel 0 "store_multiple_operation"
 743     [(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -12)))
 744           (match_operand:SI 1 "arm_hard_general_register_operand" ""))
 745      (set (mem:SI (plus:SI (match_dup 4) (const_int -8)))
 746           (match_operand:SI 2 "arm_hard_general_register_operand" ""))
 747      (set (mem:SI (plus:SI (match_dup 4) (const_int -4)))
 748           (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
 749   "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
 750   "stmdb%?\t%4, {%1, %2, %3}"
 751   [(set_attr "type" "store_12")
 752    (set_attr "predicable" "yes")
 753    (set_attr "predicable_short_it" "no")])
 754
 755 (define_insn "*stm3_db_update"
 756   [(match_parallel 0 "store_multiple_operation"
 757     [(set (match_operand:SI 4 "s_register_operand" "+&rk")
 758           (plus:SI (match_dup 4) (const_int -12)))
 759      (set (mem:SI (plus:SI (match_dup 4) (const_int -12)))
 760           (match_operand:SI 1 "arm_hard_general_register_operand" ""))
 761      (set (mem:SI (plus:SI (match_dup 4) (const_int -8)))
 762           (match_operand:SI 2 "arm_hard_general_register_operand" ""))
 763      (set (mem:SI (plus:SI (match_dup 4) (const_int -4)))
 764           (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
 765   "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
 766   "stmdb%?\t%4!, {%1, %2, %3}"
 767   [(set_attr "type" "store_12")
 768    (set_attr "predicable" "yes")
 769    (set_attr "predicable_short_it" "no")])
 770
 771 (define_peephole2
 772   [(set (match_operand:SI 0 "s_register_operand" "")
 773         (match_operand:SI 3 "memory_operand" ""))
 774    (set (match_operand:SI 1 "s_register_operand" "")
 775         (match_operand:SI 4 "memory_operand" ""))
 776    (set (match_operand:SI 2 "s_register_operand" "")
 777         (match_operand:SI 5 "memory_operand" ""))]
 778   ""
 779   [(const_int 0)]
 780 {
 781   if (gen_ldm_seq (operands, 3, false))
 782     DONE;
 783   else
 784     FAIL;
 785 })
 786
 787 (define_peephole2
 788   [(set (match_operand:SI 0 "s_register_operand" "")
 789         (match_operand:SI 3 "memory_operand" ""))
 790    (parallel
 791     [(set (match_operand:SI 1 "s_register_operand" "")
 792           (match_operand:SI 4 "memory_operand" ""))
 793      (set (match_operand:SI 2 "s_register_operand" "")
 794           (match_operand:SI 5 "memory_operand" ""))])]
 795   ""
 796   [(const_int 0)]
 797 {
 798   if (gen_ldm_seq (operands, 3, false))
 799     DONE;
 800   else
 801     FAIL;
 802 })
 803
 804 (define_peephole2
 805   [(set (match_operand:SI 0 "s_register_operand" "")
 806         (match_operand:SI 6 "const_int_operand" ""))
 807    (set (match_operand:SI 3 "memory_operand" "")
 808         (match_dup 0))
 809    (set (match_operand:SI 1 "s_register_operand" "")
 810         (match_operand:SI 7 "const_int_operand" ""))
 811    (set (match_operand:SI 4 "memory_operand" "")
 812         (match_dup 1))
 813    (set (match_operand:SI 2 "s_register_operand" "")
 814         (match_operand:SI 8 "const_int_operand" ""))
 815    (set (match_operand:SI 5 "memory_operand" "")
 816         (match_dup 2))]
 817   ""
 818   [(const_int 0)]
 819 {
 820   if (gen_const_stm_seq (operands, 3))
 821     DONE;
 822   else
 823     FAIL;
 824 })
 825
 826 (define_peephole2
 827   [(set (match_operand:SI 0 "s_register_operand" "")
 828         (match_operand:SI 6 "const_int_operand" ""))
 829    (set (match_operand:SI 1 "s_register_operand" "")
 830         (match_operand:SI 7 "const_int_operand" ""))
 831    (set (match_operand:SI 2 "s_register_operand" "")
 832         (match_operand:SI 8 "const_int_operand" ""))
 833    (set (match_operand:SI 3 "memory_operand" "")
 834         (match_dup 0))
 835    (set (match_operand:SI 4 "memory_operand" "")
 836         (match_dup 1))
 837    (set (match_operand:SI 5 "memory_operand" "")
 838         (match_dup 2))]
 839   ""
 840   [(const_int 0)]
 841 {
 842   if (gen_const_stm_seq (operands, 3))
 843     DONE;
 844   else
 845     FAIL;
 846 })
 847
 848 (define_peephole2
 849   [(set (match_operand:SI 3 "memory_operand" "")
 850         (match_operand:SI 0 "s_register_operand" ""))
 851    (set (match_operand:SI 4 "memory_operand" "")
 852         (match_operand:SI 1 "s_register_operand" ""))
 853    (set (match_operand:SI 5 "memory_operand" "")
 854         (match_operand:SI 2 "s_register_operand" ""))]
 855   ""
 856   [(const_int 0)]
 857 {
 858   if (gen_stm_seq (operands, 3))
 859     DONE;
 860   else
 861     FAIL;
 862 })
 863
 864 (define_insn "*ldm2_"
 865   [(match_parallel 0 "load_multiple_operation"
 866     [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
 867           (mem:SI (match_operand:SI 3 "s_register_operand" "rk")))
 868      (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
 869           (mem:SI (plus:SI (match_dup 3)
 870                   (const_int 4))))])]
 871   "TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
 872   "ldm%?\t%3, {%1, %2}"
 873   [(set_attr "type" "load_8")
 874    (set_attr "predicable" "yes")
 875    (set_attr "predicable_short_it" "no")])
 876
 877 (define_insn "*thumb_ldm2_ia"
 878   [(match_parallel 0 "load_multiple_operation"
 879     [(set (match_operand:SI 1 "low_register_operand" "")
 880           (mem:SI (match_operand:SI 3 "s_register_operand" "l")))
 881      (set (match_operand:SI 2 "low_register_operand" "")
 882           (mem:SI (plus:SI (match_dup 3)
 883                   (const_int 4))))])]
 884   "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 2"
 885   "ldmia\t%3, {%1, %2}"
 886   [(set_attr "type" "load_8")])
 887
 888 (define_insn "*ldm2_ia_update"
 889   [(match_parallel 0 "load_multiple_operation"
 890     [(set (match_operand:SI 3 "s_register_operand" "+&rk")
 891           (plus:SI (match_dup 3) (const_int 8)))
 892      (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
 893           (mem:SI (match_dup 3)))
 894      (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
 895           (mem:SI (plus:SI (match_dup 3)
 896                   (const_int 4))))])]
 897   "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
 898   "ldmia%?\t%3!, {%1, %2}"
 899   [(set_attr "type" "load_8")
 900    (set_attr "predicable" "yes")
 901    (set_attr "predicable_short_it" "no")])
 902
 903 (define_insn "*thumb_ldm2_ia_update"
 904   [(match_parallel 0 "load_multiple_operation"
 905     [(set (match_operand:SI 3 "s_register_operand" "+&l")
 906           (plus:SI (match_dup 3) (const_int 8)))
 907      (set (match_operand:SI 1 "low_register_operand" "")
 908           (mem:SI (match_dup 3)))
 909      (set (match_operand:SI 2 "low_register_operand" "")
 910           (mem:SI (plus:SI (match_dup 3)
 911                   (const_int 4))))])]
 912   "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3"
 913   "ldmia\t%3!, {%1, %2}"
 914   [(set_attr "type" "load_8")])
 915
 916 (define_insn "*stm2_"
 917   [(match_parallel 0 "store_multiple_operation"
 918     [(set (mem:SI (match_operand:SI 3 "s_register_operand" "rk"))
 919           (match_operand:SI 1 "arm_hard_general_register_operand" ""))
 920      (set (mem:SI (plus:SI (match_dup 3) (const_int 4)))
 921           (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
 922   "TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
 923   "stm%?\t%3, {%1, %2}"
 924   [(set_attr "type" "store_8")
 925    (set_attr "predicable" "yes")
 926    (set_attr "predicable_short_it" "no")])
 927
 928 (define_insn "*stm2_ia_update"
 929   [(match_parallel 0 "store_multiple_operation"
 930     [(set (match_operand:SI 3 "s_register_operand" "+&rk")
 931           (plus:SI (match_dup 3) (const_int 8)))
 932      (set (mem:SI (match_dup 3))
 933           (match_operand:SI 1 "arm_hard_general_register_operand" ""))
 934      (set (mem:SI (plus:SI (match_dup 3) (const_int 4)))
 935           (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
 936   "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
 937   "stmia%?\t%3!, {%1, %2}"
 938   [(set_attr "type" "store_8")
 939    (set_attr "predicable" "yes")
 940    (set_attr "predicable_short_it" "no")])
 941
 942 (define_insn "*thumb_stm2_ia_update"
 943   [(match_parallel 0 "store_multiple_operation"
 944     [(set (match_operand:SI 3 "s_register_operand" "+&l")
 945           (plus:SI (match_dup 3) (const_int 8)))
 946      (set (mem:SI (match_dup 3))
 947           (match_operand:SI 1 "low_register_operand" ""))
 948      (set (mem:SI (plus:SI (match_dup 3) (const_int 4)))
 949           (match_operand:SI 2 "low_register_operand" ""))])]
 950   "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3"
 951   "stmia\t%3!, {%1, %2}"
 952   [(set_attr "type" "store_8")])
 953
 954 (define_insn "*ldm2_ib"
 955   [(match_parallel 0 "load_multiple_operation"
 956     [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
 957           (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk")
 958                   (const_int 4))))
 959      (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
 960           (mem:SI (plus:SI (match_dup 3)
 961                   (const_int 8))))])]
 962   "TARGET_ARM && XVECLEN (operands[0], 0) == 2"
 963   "ldmib%?\t%3, {%1, %2}"
 964   [(set_attr "type" "load_8")
 965    (set_attr "predicable" "yes")])
 966
 967 (define_insn "*ldm2_ib_update"
 968   [(match_parallel 0 "load_multiple_operation"
 969     [(set (match_operand:SI 3 "s_register_operand" "+&rk")
 970           (plus:SI (match_dup 3) (const_int 8)))
 971      (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
 972           (mem:SI (plus:SI (match_dup 3)
 973                   (const_int 4))))
 974      (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
 975           (mem:SI (plus:SI (match_dup 3)
 976                   (const_int 8))))])]
 977   "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
 978   "ldmib%?\t%3!, {%1, %2}"
 979   [(set_attr "type" "load_8")
 980    (set_attr "predicable" "yes")])
 981
 982 (define_insn "*stm2_ib"
 983   [(match_parallel 0 "store_multiple_operation"
 984     [(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int 4)))
 985           (match_operand:SI 1 "arm_hard_general_register_operand" ""))
 986      (set (mem:SI (plus:SI (match_dup 3) (const_int 8)))
 987           (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
 988   "TARGET_ARM && XVECLEN (operands[0], 0) == 2"
 989   "stmib%?\t%3, {%1, %2}"
 990   [(set_attr "type" "store_8")
 991    (set_attr "predicable" "yes")])
 992
 993 (define_insn "*stm2_ib_update"
 994   [(match_parallel 0 "store_multiple_operation"
 995     [(set (match_operand:SI 3 "s_register_operand" "+&rk")
 996           (plus:SI (match_dup 3) (const_int 8)))
 997      (set (mem:SI (plus:SI (match_dup 3) (const_int 4)))
 998           (match_operand:SI 1 "arm_hard_general_register_operand" ""))
 999      (set (mem:SI (plus:SI (match_dup 3) (const_int 8)))
1000           (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
1001   "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
1002   "stmib%?\t%3!, {%1, %2}"
1003   [(set_attr "type" "store_8")
1004    (set_attr "predicable" "yes")])
1005
1006 (define_insn "*ldm2_da"
1007   [(match_parallel 0 "load_multiple_operation"
1008     [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
1009           (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk")
1010                   (const_int -4))))
1011      (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
1012           (mem:SI (match_dup 3)))])]
1013   "TARGET_ARM && XVECLEN (operands[0], 0) == 2"
1014   "ldmda%?\t%3, {%1, %2}"
1015   [(set_attr "type" "load_8")
1016    (set_attr "predicable" "yes")])
1017
1018 (define_insn "*ldm2_da_update"
1019   [(match_parallel 0 "load_multiple_operation"
1020     [(set (match_operand:SI 3 "s_register_operand" "+&rk")
1021           (plus:SI (match_dup 3) (const_int -8)))
1022      (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
1023           (mem:SI (plus:SI (match_dup 3)
1024                   (const_int -4))))
1025      (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
1026           (mem:SI (match_dup 3)))])]
1027   "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
1028   "ldmda%?\t%3!, {%1, %2}"
1029   [(set_attr "type" "load_8")
1030    (set_attr "predicable" "yes")])
1031
1032 (define_insn "*stm2_da"
1033   [(match_parallel 0 "store_multiple_operation"
1034     [(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -4)))
1035           (match_operand:SI 1 "arm_hard_general_register_operand" ""))
1036      (set (mem:SI (match_dup 3))
1037           (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
1038   "TARGET_ARM && XVECLEN (operands[0], 0) == 2"
1039   "stmda%?\t%3, {%1, %2}"
1040   [(set_attr "type" "store_8")
1041    (set_attr "predicable" "yes")])
1042
1043 (define_insn "*stm2_da_update"
1044   [(match_parallel 0 "store_multiple_operation"
1045     [(set (match_operand:SI 3 "s_register_operand" "+&rk")
1046           (plus:SI (match_dup 3) (const_int -8)))
1047      (set (mem:SI (plus:SI (match_dup 3) (const_int -4)))
1048           (match_operand:SI 1 "arm_hard_general_register_operand" ""))
1049      (set (mem:SI (match_dup 3))
1050           (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
1051   "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
1052   "stmda%?\t%3!, {%1, %2}"
1053   [(set_attr "type" "store_8")
1054    (set_attr "predicable" "yes")])
1055
1056 (define_insn "*ldm2_db"
1057   [(match_parallel 0 "load_multiple_operation"
1058     [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
1059           (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk")
1060                   (const_int -8))))
1061      (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
1062           (mem:SI (plus:SI (match_dup 3)
1063                   (const_int -4))))])]
1064   "TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
1065   "ldmdb%?\t%3, {%1, %2}"
1066   [(set_attr "type" "load_8")
1067    (set_attr "predicable" "yes")
1068    (set_attr "predicable_short_it" "no")])
1069
1070 (define_insn "*ldm2_db_update"
1071   [(match_parallel 0 "load_multiple_operation"
1072     [(set (match_operand:SI 3 "s_register_operand" "+&rk")
1073           (plus:SI (match_dup 3) (const_int -8)))
1074      (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
1075           (mem:SI (plus:SI (match_dup 3)
1076                   (const_int -8))))
1077      (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
1078           (mem:SI (plus:SI (match_dup 3)
1079                   (const_int -4))))])]
1080   "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
1081   "ldmdb%?\t%3!, {%1, %2}"
1082   [(set_attr "type" "load_8")
1083    (set_attr "predicable" "yes")
1084    (set_attr "predicable_short_it" "no")])
1085
1086 (define_insn "*stm2_db"
1087   [(match_parallel 0 "store_multiple_operation"
1088     [(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -8)))
1089           (match_operand:SI 1 "arm_hard_general_register_operand" ""))
1090      (set (mem:SI (plus:SI (match_dup 3) (const_int -4)))
1091           (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
1092   "TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
1093   "stmdb%?\t%3, {%1, %2}"
1094   [(set_attr "type" "store_8")
1095    (set_attr "predicable" "yes")
1096    (set_attr "predicable_short_it" "no")])
1097
1098 (define_insn "*stm2_db_update"
1099   [(match_parallel 0 "store_multiple_operation"
1100     [(set (match_operand:SI 3 "s_register_operand" "+&rk")
1101           (plus:SI (match_dup 3) (const_int -8)))
1102      (set (mem:SI (plus:SI (match_dup 3) (const_int -8)))
1103           (match_operand:SI 1 "arm_hard_general_register_operand" ""))
1104      (set (mem:SI (plus:SI (match_dup 3) (const_int -4)))
1105           (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
1106   "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
1107   "stmdb%?\t%3!, {%1, %2}"
1108   [(set_attr "type" "store_8")
1109    (set_attr "predicable" "yes")
1110    (set_attr "predicable_short_it" "no")])
1111
1112 (define_peephole2
1113   [(set (match_operand:SI 0 "s_register_operand" "")
1114         (match_operand:SI 2 "memory_operand" ""))
1115    (set (match_operand:SI 1 "s_register_operand" "")
1116         (match_operand:SI 3 "memory_operand" ""))]
1117   ""
1118   [(const_int 0)]
1119 {
1120   if (gen_ldm_seq (operands, 2, false))
1121     DONE;
1122   else
1123     FAIL;
1124 })
1125
1126 (define_peephole2
1127   [(set (match_operand:SI 0 "s_register_operand" "")
1128         (match_operand:SI 4 "const_int_operand" ""))
1129    (set (match_operand:SI 2 "memory_operand" "")
1130         (match_dup 0))
1131    (set (match_operand:SI 1 "s_register_operand" "")
1132         (match_operand:SI 5 "const_int_operand" ""))
1133    (set (match_operand:SI 3 "memory_operand" "")
1134         (match_dup 1))]
1135   ""
1136   [(const_int 0)]
1137 {
1138   if (gen_const_stm_seq (operands, 2))
1139     DONE;
1140   else
1141     FAIL;
1142 })
1143
1144 (define_peephole2
1145   [(set (match_operand:SI 0 "s_register_operand" "")
1146         (match_operand:SI 4 "const_int_operand" ""))
1147    (set (match_operand:SI 1 "s_register_operand" "")
1148         (match_operand:SI 5 "const_int_operand" ""))
1149    (set (match_operand:SI 2 "memory_operand" "")
1150         (match_dup 0))
1151    (set (match_operand:SI 3 "memory_operand" "")
1152         (match_dup 1))]
1153   ""
1154   [(const_int 0)]
1155 {
1156   if (gen_const_stm_seq (operands, 2))
1157     DONE;
1158   else
1159     FAIL;
1160 })
1161
1162 (define_peephole2
1163   [(set (match_operand:SI 2 "memory_operand" "")
1164         (match_operand:SI 0 "s_register_operand" ""))
1165    (set (match_operand:SI 3 "memory_operand" "")
1166         (match_operand:SI 1 "s_register_operand" ""))]
1167   ""
1168   [(const_int 0)]
1169 {
1170   if (gen_stm_seq (operands, 2))
1171     DONE;
1172   else
1173     FAIL;
1174 })
1175
1176 (define_peephole2
1177   [(set (match_operand:SI 0 "s_register_operand" "")
1178         (match_operand:SI 2 "memory_operand" ""))
1179    (set (match_operand:SI 1 "s_register_operand" "")
1180         (match_operand:SI 3 "memory_operand" ""))
1181    (parallel
1182      [(set (match_operand:SI 4 "s_register_operand" "")
1183            (match_operator:SI 5 "commutative_binary_operator"
1184             [(match_operand:SI 6 "s_register_operand" "")
1185              (match_operand:SI 7 "s_register_operand" "")]))
1186       (clobber (reg:CC CC_REGNUM))])]
1187   "((((REGNO (operands[6]) == REGNO (operands[0]))
1188          && (REGNO (operands[7]) == REGNO (operands[1])))
1189       || ((REGNO (operands[7]) == REGNO (operands[0]))
1190          && (REGNO (operands[6]) == REGNO (operands[1]))))
1191     && (peep2_regno_dead_p (3, REGNO (operands[0]))
1192       || (REGNO (operands[0]) == REGNO (operands[4])))
1193     && (peep2_regno_dead_p (3, REGNO (operands[1]))
1194       || (REGNO (operands[1]) == REGNO (operands[4]))))"
1195   [(parallel
1196     [(set (match_dup 4) (match_op_dup 5 [(match_dup 6) (match_dup 7)]))
1197      (clobber (reg:CC CC_REGNUM))])]
1198 {
1199   if (!gen_ldm_seq (operands, 2, true))
1200     FAIL;
1201 })
1202
1203 (define_peephole2
1204   [(set (match_operand:SI 0 "s_register_operand" "")
1205         (match_operand:SI 2 "memory_operand" ""))
1206    (set (match_operand:SI 1 "s_register_operand" "")
1207         (match_operand:SI 3 "memory_operand" ""))
1208    (set (match_operand:SI 4 "s_register_operand" "")
1209         (match_operator:SI 5 "commutative_binary_operator"
1210          [(match_operand:SI 6 "s_register_operand" "")
1211           (match_operand:SI 7 "s_register_operand" "")]))]
1212   "((((REGNO (operands[6]) == REGNO (operands[0]))
1213          && (REGNO (operands[7]) == REGNO (operands[1])))
1214       || ((REGNO (operands[7]) == REGNO (operands[0]))
1215          && (REGNO (operands[6]) == REGNO (operands[1]))))
1216     && (peep2_regno_dead_p (3, REGNO (operands[0]))
1217       || (REGNO (operands[0]) == REGNO (operands[4])))
1218     && (peep2_regno_dead_p (3, REGNO (operands[1]))
1219       || (REGNO (operands[1]) == REGNO (operands[4]))))"
1220   [(set (match_dup 4) (match_op_dup 5 [(match_dup 6) (match_dup 7)]))]
1221 {
1222   if (!gen_ldm_seq (operands, 2, true))
1223     FAIL;
1224 })
1225