1 ;; Arm M-profile Vector Extension Machine Description
2 ;; Copyright (C) 2019-2020 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify it
7 ;; under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful, but
12 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 ;; General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 (define_insn "*mve_mov<mode>"
21 [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Ux,w")
22 (match_operand:MVE_types 1 "general_operand" "w,r,w,Dn,Uxi,r,Dm,w,Ul"))]
23 "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT"
25 if (which_alternative == 3 || which_alternative == 6)
28 static char templ[40];
30 is_valid = simd_immediate_valid_for_move (operands[1], <MODE>mode,
31 &operands[1], &width);
33 gcc_assert (is_valid != 0);
36 return "vmov.f32\t%q0, %1 @ <mode>";
38 sprintf (templ, "vmov.i%d\t%%q0, %%x1 @ <mode>", width);
42 if (which_alternative == 4 || which_alternative == 7)
45 int regno = (which_alternative == 7)
46 ? REGNO (operands[1]) : REGNO (operands[0]);
50 if (<MODE>mode == V2DFmode || <MODE>mode == V2DImode)
52 if (which_alternative == 7)
54 ops[1] = gen_rtx_REG (DImode, regno);
55 output_asm_insn ("vstr.64\t%P1, %E0",ops);
59 ops[0] = gen_rtx_REG (DImode, regno);
60 output_asm_insn ("vldr.64\t%P0, %E1",ops);
63 else if (<MODE>mode == TImode)
65 if (which_alternative == 7)
66 output_asm_insn ("vstr.64\t%q1, %E0",ops);
68 output_asm_insn ("vldr.64\t%q0, %E1",ops);
72 if (which_alternative == 7)
74 ops[1] = gen_rtx_REG (TImode, regno);
75 output_asm_insn ("vstr<V_sz_elem1>.<V_sz_elem>\t%q1, %E0",ops);
79 ops[0] = gen_rtx_REG (TImode, regno);
80 output_asm_insn ("vldr<V_sz_elem1>.<V_sz_elem>\t%q0, %E1",ops);
85 switch (which_alternative)
88 return "vmov\t%q0, %q1";
90 return "vmov\t%e0, %Q1, %R1 @ <mode>\;vmov\t%f0, %J1, %K1";
92 return "vmov\t%Q0, %R0, %e1 @ <mode>\;vmov\t%J0, %K0, %f1";
94 return output_move_quad (operands);
96 return output_move_neon (operands);
102 [(set_attr "type" "mve_move,mve_move,mve_move,mve_move,mve_load,multiple,mve_move,mve_store,mve_load")
103 (set_attr "length" "4,8,8,4,8,8,4,4,4")
104 (set_attr "thumb2_pool_range" "*,*,*,*,1018,*,*,*,*")
105 (set_attr "neg_pool_range" "*,*,*,*,996,*,*,*,*")])
107 (define_insn "*mve_mov<mode>"
108 [(set (match_operand:MVE_types 0 "s_register_operand" "=w,w")
109 (vec_duplicate:MVE_types
110 (match_operand:SI 1 "nonmemory_operand" "r,i")))]
111 "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT"
113 if (which_alternative == 0)
114 return "vdup.<V_sz_elem>\t%q0, %1";
115 return "vmov.<V_sz_elem>\t%q0, %1";
117 [(set_attr "length" "4,4")
118 (set_attr "type" "mve_move,mve_move")])
123 (define_insn "mve_vst4q<mode>"
124 [(set (match_operand:XI 0 "neon_struct_operand" "=Um")
125 (unspec:XI [(match_operand:XI 1 "s_register_operand" "w")
126 (unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
132 int regno = REGNO (operands[1]);
133 ops[0] = gen_rtx_REG (TImode, regno);
134 ops[1] = gen_rtx_REG (TImode, regno+4);
135 ops[2] = gen_rtx_REG (TImode, regno+8);
136 ops[3] = gen_rtx_REG (TImode, regno+12);
137 rtx reg = operands[0];
138 while (reg && !REG_P (reg))
140 gcc_assert (REG_P (reg));
142 ops[5] = operands[0];
143 /* Here in first three instructions data is stored to ops[4]'s location but
144 in the fourth instruction data is stored to operands[0], this is to
145 support the writeback. */
146 output_asm_insn ("vst40.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t"
147 "vst41.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t"
148 "vst42.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t"
149 "vst43.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, %5", ops);
152 [(set_attr "length" "16")])
157 (define_insn "mve_vrndq_m_f<mode>"
159 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
160 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
161 (match_operand:MVE_0 2 "s_register_operand" "w")
162 (match_operand:HI 3 "vpr_register_operand" "Up")]
165 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
166 "vpst\;vrintzt.f%#<V_sz_elem> %q0, %q2"
167 [(set_attr "type" "mve_move")
168 (set_attr "length""8")])
173 (define_insn "mve_vrndxq_f<mode>"
175 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
176 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
179 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
180 "vrintx.f%#<V_sz_elem> %q0, %q1"
181 [(set_attr "type" "mve_move")
187 (define_insn "mve_vrndq_f<mode>"
189 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
190 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
193 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
194 "vrintz.f%#<V_sz_elem> %q0, %q1"
195 [(set_attr "type" "mve_move")
201 (define_insn "mve_vrndpq_f<mode>"
203 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
204 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
207 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
208 "vrintp.f%#<V_sz_elem> %q0, %q1"
209 [(set_attr "type" "mve_move")
215 (define_insn "mve_vrndnq_f<mode>"
217 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
218 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
221 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
222 "vrintn.f%#<V_sz_elem> %q0, %q1"
223 [(set_attr "type" "mve_move")
229 (define_insn "mve_vrndmq_f<mode>"
231 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
232 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
235 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
236 "vrintm.f%#<V_sz_elem> %q0, %q1"
237 [(set_attr "type" "mve_move")
243 (define_insn "mve_vrndaq_f<mode>"
245 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
246 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
249 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
250 "vrinta.f%#<V_sz_elem> %q0, %q1"
251 [(set_attr "type" "mve_move")
257 (define_insn "mve_vrev64q_f<mode>"
259 (set (match_operand:MVE_0 0 "s_register_operand" "=&w")
260 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
263 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
264 "vrev64.%#<V_sz_elem> %q0, %q1"
265 [(set_attr "type" "mve_move")
271 (define_insn "mve_vnegq_f<mode>"
273 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
274 (neg:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")))
276 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
277 "vneg.f%#<V_sz_elem> %q0, %q1"
278 [(set_attr "type" "mve_move")
284 (define_insn "mve_vdupq_n_f<mode>"
286 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
287 (unspec:MVE_0 [(match_operand:<V_elem> 1 "s_register_operand" "r")]
290 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
291 "vdup.%#<V_sz_elem> %q0, %1"
292 [(set_attr "type" "mve_move")
298 (define_insn "mve_vabsq_f<mode>"
300 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
301 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
304 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
305 "vabs.f%#<V_sz_elem> %q0, %q1"
306 [(set_attr "type" "mve_move")
312 (define_insn "mve_vrev32q_fv8hf"
314 (set (match_operand:V8HF 0 "s_register_operand" "=w")
315 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "w")]
318 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
320 [(set_attr "type" "mve_move")
325 (define_insn "mve_vcvttq_f32_f16v4sf"
327 (set (match_operand:V4SF 0 "s_register_operand" "=w")
328 (unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")]
331 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
332 "vcvtt.f32.f16 %q0, %q1"
333 [(set_attr "type" "mve_move")
339 (define_insn "mve_vcvtbq_f32_f16v4sf"
341 (set (match_operand:V4SF 0 "s_register_operand" "=w")
342 (unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")]
345 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
346 "vcvtb.f32.f16 %q0, %q1"
347 [(set_attr "type" "mve_move")
351 ;; [vcvtq_to_f_s, vcvtq_to_f_u])
353 (define_insn "mve_vcvtq_to_f_<supf><mode>"
355 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
356 (unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
359 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
360 "vcvt.f%#<V_sz_elem>.<supf>%#<V_sz_elem> %q0, %q1"
361 [(set_attr "type" "mve_move")
365 ;; [vrev64q_u, vrev64q_s])
367 (define_insn "mve_vrev64q_<supf><mode>"
369 (set (match_operand:MVE_2 0 "s_register_operand" "=&w")
370 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
374 "vrev64.%#<V_sz_elem> %q0, %q1"
375 [(set_attr "type" "mve_move")
379 ;; [vcvtq_from_f_s, vcvtq_from_f_u])
381 (define_insn "mve_vcvtq_from_f_<supf><mode>"
383 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
384 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
387 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
388 "vcvt.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
389 [(set_attr "type" "mve_move")
393 (define_insn "mve_vqnegq_s<mode>"
395 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
396 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
400 "vqneg.s%#<V_sz_elem> %q0, %q1"
401 [(set_attr "type" "mve_move")
407 (define_insn "mve_vqabsq_s<mode>"
409 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
410 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
414 "vqabs.s%#<V_sz_elem> %q0, %q1"
415 [(set_attr "type" "mve_move")
421 (define_insn "mve_vnegq_s<mode>"
423 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
424 (neg:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")))
427 "vneg.s%#<V_sz_elem> %q0, %q1"
428 [(set_attr "type" "mve_move")
432 ;; [vmvnq_u, vmvnq_s])
434 (define_insn "mve_vmvnq_u<mode>"
436 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
437 (not:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")))
441 [(set_attr "type" "mve_move")
443 (define_expand "mve_vmvnq_s<mode>"
445 (set (match_operand:MVE_2 0 "s_register_operand")
446 (not:MVE_2 (match_operand:MVE_2 1 "s_register_operand")))
452 ;; [vdupq_n_u, vdupq_n_s])
454 (define_insn "mve_vdupq_n_<supf><mode>"
456 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
457 (unspec:MVE_2 [(match_operand:<V_elem> 1 "s_register_operand" "r")]
461 "vdup.%#<V_sz_elem> %q0, %1"
462 [(set_attr "type" "mve_move")
466 ;; [vclzq_u, vclzq_s])
468 (define_insn "mve_vclzq_<supf><mode>"
470 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
471 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
475 "vclz.i%#<V_sz_elem> %q0, %q1"
476 [(set_attr "type" "mve_move")
482 (define_insn "mve_vclsq_s<mode>"
484 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
485 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
489 "vcls.s%#<V_sz_elem> %q0, %q1"
490 [(set_attr "type" "mve_move")
494 ;; [vaddvq_s, vaddvq_u])
496 (define_insn "mve_vaddvq_<supf><mode>"
498 (set (match_operand:SI 0 "s_register_operand" "=Te")
499 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")]
503 "vaddv.<supf>%#<V_sz_elem>\t%0, %q1"
504 [(set_attr "type" "mve_move")
510 (define_insn "mve_vabsq_s<mode>"
512 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
513 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
517 "vabs.s%#<V_sz_elem>\t%q0, %q1"
518 [(set_attr "type" "mve_move")
522 ;; [vrev32q_u, vrev32q_s])
524 (define_insn "mve_vrev32q_<supf><mode>"
526 (set (match_operand:MVE_3 0 "s_register_operand" "=w")
527 (unspec:MVE_3 [(match_operand:MVE_3 1 "s_register_operand" "w")]
531 "vrev32.%#<V_sz_elem>\t%q0, %q1"
532 [(set_attr "type" "mve_move")
536 ;; [vmovltq_u, vmovltq_s])
538 (define_insn "mve_vmovltq_<supf><mode>"
540 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
541 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")]
545 "vmovlt.<supf>%#<V_sz_elem> %q0, %q1"
546 [(set_attr "type" "mve_move")
550 ;; [vmovlbq_s, vmovlbq_u])
552 (define_insn "mve_vmovlbq_<supf><mode>"
554 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
555 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")]
559 "vmovlb.<supf>%#<V_sz_elem> %q0, %q1"
560 [(set_attr "type" "mve_move")
564 ;; [vcvtpq_s, vcvtpq_u])
566 (define_insn "mve_vcvtpq_<supf><mode>"
568 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
569 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
572 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
573 "vcvtp.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
574 [(set_attr "type" "mve_move")
578 ;; [vcvtnq_s, vcvtnq_u])
580 (define_insn "mve_vcvtnq_<supf><mode>"
582 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
583 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
586 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
587 "vcvtn.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
588 [(set_attr "type" "mve_move")
592 ;; [vcvtmq_s, vcvtmq_u])
594 (define_insn "mve_vcvtmq_<supf><mode>"
596 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
597 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
600 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
601 "vcvtm.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
602 [(set_attr "type" "mve_move")
606 ;; [vcvtaq_u, vcvtaq_s])
608 (define_insn "mve_vcvtaq_<supf><mode>"
610 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
611 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
614 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
615 "vcvta.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
616 [(set_attr "type" "mve_move")
620 ;; [vmvnq_n_u, vmvnq_n_s])
622 (define_insn "mve_vmvnq_n_<supf><mode>"
624 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
625 (unspec:MVE_5 [(match_operand:HI 1 "immediate_operand" "i")]
629 "vmvn.i%#<V_sz_elem> %q0, %1"
630 [(set_attr "type" "mve_move")
634 ;; [vrev16q_u, vrev16q_s])
636 (define_insn "mve_vrev16q_<supf>v16qi"
638 (set (match_operand:V16QI 0 "s_register_operand" "=w")
639 (unspec:V16QI [(match_operand:V16QI 1 "s_register_operand" "w")]
644 [(set_attr "type" "mve_move")
648 ;; [vaddlvq_s vaddlvq_u])
650 (define_insn "mve_vaddlvq_<supf>v4si"
652 (set (match_operand:DI 0 "s_register_operand" "=r")
653 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")]
657 "vaddlv.<supf>32 %Q0, %R0, %q1"
658 [(set_attr "type" "mve_move")
662 ;; [vctp8q vctp16q vctp32q vctp64q])
664 (define_insn "mve_vctp<mode1>qhi"
666 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
667 (unspec:HI [(match_operand:SI 1 "s_register_operand" "r")]
672 [(set_attr "type" "mve_move")
678 (define_insn "mve_vpnothi"
680 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
681 (unspec:HI [(match_operand:HI 1 "vpr_register_operand" "0")]
686 [(set_attr "type" "mve_move")
692 (define_insn "mve_vsubq_n_f<mode>"
694 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
695 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
696 (match_operand:<V_elem> 2 "s_register_operand" "r")]
699 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
700 "vsub.f<V_sz_elem> %q0, %q1, %2"
701 [(set_attr "type" "mve_move")
707 (define_insn "mve_vbrsrq_n_f<mode>"
709 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
710 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
711 (match_operand:SI 2 "s_register_operand" "r")]
714 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
715 "vbrsr.<V_sz_elem> %q0, %q1, %2"
716 [(set_attr "type" "mve_move")
720 ;; [vcvtq_n_to_f_s, vcvtq_n_to_f_u])
722 (define_insn "mve_vcvtq_n_to_f_<supf><mode>"
724 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
725 (unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")
726 (match_operand:SI 2 "<MVE_pred2>" "<MVE_constraint2>")]
729 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
730 "vcvt.f<V_sz_elem>.<supf><V_sz_elem>\t%q0, %q1, %2"
731 [(set_attr "type" "mve_move")
736 (define_insn "mve_vcreateq_f<mode>"
738 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
739 (unspec:MVE_0 [(match_operand:DI 1 "s_register_operand" "r")
740 (match_operand:DI 2 "s_register_operand" "r")]
743 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
744 "vmov %q0[2], %q0[0], %Q2, %Q1\;vmov %q0[3], %q0[1], %R2, %R1"
745 [(set_attr "type" "mve_move")
746 (set_attr "length""8")])
749 ;; [vcreateq_u, vcreateq_s])
751 (define_insn "mve_vcreateq_<supf><mode>"
753 (set (match_operand:MVE_1 0 "s_register_operand" "=w")
754 (unspec:MVE_1 [(match_operand:DI 1 "s_register_operand" "r")
755 (match_operand:DI 2 "s_register_operand" "r")]
759 "vmov %q0[2], %q0[0], %Q2, %Q1\;vmov %q0[3], %q0[1], %R2, %R1"
760 [(set_attr "type" "mve_move")
761 (set_attr "length""8")])
764 ;; [vshrq_n_s, vshrq_n_u])
766 (define_insn "mve_vshrq_n_<supf><mode>"
768 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
769 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
770 (match_operand:SI 2 "<MVE_pred2>" "<MVE_constraint2>")]
774 "vshr.<supf><V_sz_elem>\t%q0, %q1, %2"
775 [(set_attr "type" "mve_move")
779 ;; [vcvtq_n_from_f_s, vcvtq_n_from_f_u])
781 (define_insn "mve_vcvtq_n_from_f_<supf><mode>"
783 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
784 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")
785 (match_operand:SI 2 "<MVE_pred2>" "<MVE_constraint2>")]
788 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
789 "vcvt.<supf><V_sz_elem>.f<V_sz_elem>\t%q0, %q1, %2"
790 [(set_attr "type" "mve_move")
796 (define_insn "mve_vaddlvq_p_<supf>v4si"
798 (set (match_operand:DI 0 "s_register_operand" "=r")
799 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
800 (match_operand:HI 2 "vpr_register_operand" "Up")]
804 "vpst\;vaddlvt.<supf>32 %Q0, %R0, %q1"
805 [(set_attr "type" "mve_move")
806 (set_attr "length""8")])
809 ;; [vcmpneq_u, vcmpneq_s])
811 (define_insn "mve_vcmpneq_<supf><mode>"
813 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
814 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
815 (match_operand:MVE_2 2 "s_register_operand" "w")]
819 "vcmp.i%#<V_sz_elem> ne, %q1, %q2"
820 [(set_attr "type" "mve_move")
824 ;; [vshlq_s, vshlq_u])
826 (define_insn "mve_vshlq_<supf><mode>"
828 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
829 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
830 (match_operand:MVE_2 2 "s_register_operand" "w")]
834 "vshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
835 [(set_attr "type" "mve_move")
839 ;; [vabdq_s, vabdq_u])
841 (define_insn "mve_vabdq_<supf><mode>"
843 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
844 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
845 (match_operand:MVE_2 2 "s_register_operand" "w")]
849 "vabd.<supf>%#<V_sz_elem> %q0, %q1, %q2"
850 [(set_attr "type" "mve_move")
854 ;; [vaddq_n_s, vaddq_n_u])
856 (define_insn "mve_vaddq_n_<supf><mode>"
858 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
859 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
860 (match_operand:<V_elem> 2 "s_register_operand" "r")]
864 "vadd.i%#<V_sz_elem> %q0, %q1, %2"
865 [(set_attr "type" "mve_move")
869 ;; [vaddvaq_s, vaddvaq_u])
871 (define_insn "mve_vaddvaq_<supf><mode>"
873 (set (match_operand:SI 0 "s_register_operand" "=Te")
874 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
875 (match_operand:MVE_2 2 "s_register_operand" "w")]
879 "vaddva.<supf>%#<V_sz_elem> %0, %q2"
880 [(set_attr "type" "mve_move")
884 ;; [vaddvq_p_u, vaddvq_p_s])
886 (define_insn "mve_vaddvq_p_<supf><mode>"
888 (set (match_operand:SI 0 "s_register_operand" "=Te")
889 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
890 (match_operand:HI 2 "vpr_register_operand" "Up")]
894 "vpst\;vaddvt.<supf>%#<V_sz_elem> %0, %q1"
895 [(set_attr "type" "mve_move")
896 (set_attr "length""8")])
899 ;; [vandq_u, vandq_s])
901 ;; signed and unsigned versions are the same: define the unsigned
902 ;; insn, and use an expander for the signed one as we still reference
903 ;; both names from arm_mve.h.
904 ;; We use the same code as in neon.md (TODO: avoid this duplication).
905 (define_insn "mve_vandq_u<mode>"
907 (set (match_operand:MVE_2 0 "s_register_operand" "=w,w")
908 (and:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w,0")
909 (match_operand:MVE_2 2 "neon_inv_logic_op2" "w,DL")))
914 * return neon_output_logic_immediate (\"vand\", &operands[2], <MODE>mode, 1, VALID_NEON_QREG_MODE (<MODE>mode));"
915 [(set_attr "type" "mve_move")
917 (define_expand "mve_vandq_s<mode>"
919 (set (match_operand:MVE_2 0 "s_register_operand")
920 (and:MVE_2 (match_operand:MVE_2 1 "s_register_operand")
921 (match_operand:MVE_2 2 "neon_inv_logic_op2")))
927 ;; [vbicq_s, vbicq_u])
929 (define_insn "mve_vbicq_u<mode>"
931 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
932 (and:MVE_2 (not:MVE_2 (match_operand:MVE_2 2 "s_register_operand" "w"))
933 (match_operand:MVE_2 1 "s_register_operand" "w")))
936 "vbic\t%q0, %q1, %q2"
937 [(set_attr "type" "mve_move")
940 (define_expand "mve_vbicq_s<mode>"
942 (set (match_operand:MVE_2 0 "s_register_operand")
943 (and:MVE_2 (not:MVE_2 (match_operand:MVE_2 2 "s_register_operand"))
944 (match_operand:MVE_2 1 "s_register_operand")))
950 ;; [vbrsrq_n_u, vbrsrq_n_s])
952 (define_insn "mve_vbrsrq_n_<supf><mode>"
954 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
955 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
956 (match_operand:SI 2 "s_register_operand" "r")]
960 "vbrsr.%#<V_sz_elem> %q0, %q1, %2"
961 [(set_attr "type" "mve_move")
965 ;; [vcaddq_rot270_s, vcaddq_rot270_u])
967 (define_insn "mve_vcaddq_rot270_<supf><mode>"
969 (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
970 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
971 (match_operand:MVE_2 2 "s_register_operand" "w")]
975 "vcadd.i%#<V_sz_elem> %q0, %q1, %q2, #270"
976 [(set_attr "type" "mve_move")
980 ;; [vcaddq_rot90_u, vcaddq_rot90_s])
982 (define_insn "mve_vcaddq_rot90_<supf><mode>"
984 (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
985 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
986 (match_operand:MVE_2 2 "s_register_operand" "w")]
990 "vcadd.i%#<V_sz_elem> %q0, %q1, %q2, #90"
991 [(set_attr "type" "mve_move")
997 (define_insn "mve_vcmpcsq_n_u<mode>"
999 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1000 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1001 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1005 "vcmp.u%#<V_sz_elem> cs, %q1, %2"
1006 [(set_attr "type" "mve_move")
1012 (define_insn "mve_vcmpcsq_u<mode>"
1014 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1015 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1016 (match_operand:MVE_2 2 "s_register_operand" "w")]
1020 "vcmp.u%#<V_sz_elem> cs, %q1, %q2"
1021 [(set_attr "type" "mve_move")
1025 ;; [vcmpeqq_n_s, vcmpeqq_n_u])
1027 (define_insn "mve_vcmpeqq_n_<supf><mode>"
1029 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1030 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1031 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1035 "vcmp.i%#<V_sz_elem> eq, %q1, %2"
1036 [(set_attr "type" "mve_move")
1040 ;; [vcmpeqq_u, vcmpeqq_s])
1042 (define_insn "mve_vcmpeqq_<supf><mode>"
1044 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1045 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1046 (match_operand:MVE_2 2 "s_register_operand" "w")]
1050 "vcmp.i%#<V_sz_elem> eq, %q1, %q2"
1051 [(set_attr "type" "mve_move")
1057 (define_insn "mve_vcmpgeq_n_s<mode>"
1059 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1060 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1061 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1065 "vcmp.s%#<V_sz_elem> ge, %q1, %2"
1066 [(set_attr "type" "mve_move")
1072 (define_insn "mve_vcmpgeq_s<mode>"
1074 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1075 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1076 (match_operand:MVE_2 2 "s_register_operand" "w")]
1080 "vcmp.s%#<V_sz_elem> ge, %q1, %q2"
1081 [(set_attr "type" "mve_move")
1087 (define_insn "mve_vcmpgtq_n_s<mode>"
1089 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1090 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1091 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1095 "vcmp.s%#<V_sz_elem> gt, %q1, %2"
1096 [(set_attr "type" "mve_move")
1102 (define_insn "mve_vcmpgtq_s<mode>"
1104 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1105 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1106 (match_operand:MVE_2 2 "s_register_operand" "w")]
1110 "vcmp.s%#<V_sz_elem> gt, %q1, %q2"
1111 [(set_attr "type" "mve_move")
1117 (define_insn "mve_vcmphiq_n_u<mode>"
1119 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1120 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1121 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1125 "vcmp.u%#<V_sz_elem> hi, %q1, %2"
1126 [(set_attr "type" "mve_move")
1132 (define_insn "mve_vcmphiq_u<mode>"
1134 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1135 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1136 (match_operand:MVE_2 2 "s_register_operand" "w")]
1140 "vcmp.u%#<V_sz_elem> hi, %q1, %q2"
1141 [(set_attr "type" "mve_move")
1147 (define_insn "mve_vcmpleq_n_s<mode>"
1149 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1150 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1151 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1155 "vcmp.s%#<V_sz_elem> le, %q1, %2"
1156 [(set_attr "type" "mve_move")
1162 (define_insn "mve_vcmpleq_s<mode>"
1164 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1165 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1166 (match_operand:MVE_2 2 "s_register_operand" "w")]
1170 "vcmp.s%#<V_sz_elem> le, %q1, %q2"
1171 [(set_attr "type" "mve_move")
1177 (define_insn "mve_vcmpltq_n_s<mode>"
1179 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1180 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1181 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1185 "vcmp.s%#<V_sz_elem> lt, %q1, %2"
1186 [(set_attr "type" "mve_move")
1192 (define_insn "mve_vcmpltq_s<mode>"
1194 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1195 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1196 (match_operand:MVE_2 2 "s_register_operand" "w")]
1200 "vcmp.s%#<V_sz_elem> lt, %q1, %q2"
1201 [(set_attr "type" "mve_move")
1205 ;; [vcmpneq_n_u, vcmpneq_n_s])
1207 (define_insn "mve_vcmpneq_n_<supf><mode>"
1209 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1210 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1211 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1215 "vcmp.i%#<V_sz_elem> ne, %q1, %2"
1216 [(set_attr "type" "mve_move")
1220 ;; [veorq_u, veorq_s])
1222 (define_insn "mve_veorq_u<mode>"
1224 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1225 (xor:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
1226 (match_operand:MVE_2 2 "s_register_operand" "w")))
1229 "veor\t%q0, %q1, %q2"
1230 [(set_attr "type" "mve_move")
1232 (define_expand "mve_veorq_s<mode>"
1234 (set (match_operand:MVE_2 0 "s_register_operand")
1235 (xor:MVE_2 (match_operand:MVE_2 1 "s_register_operand")
1236 (match_operand:MVE_2 2 "s_register_operand")))
1242 ;; [vhaddq_n_u, vhaddq_n_s])
1244 (define_insn "mve_vhaddq_n_<supf><mode>"
1246 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1247 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1248 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1252 "vhadd.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
1253 [(set_attr "type" "mve_move")
1257 ;; [vhaddq_s, vhaddq_u])
1259 (define_insn "mve_vhaddq_<supf><mode>"
1261 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1262 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1263 (match_operand:MVE_2 2 "s_register_operand" "w")]
1267 "vhadd.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1268 [(set_attr "type" "mve_move")
1272 ;; [vhcaddq_rot270_s])
1274 (define_insn "mve_vhcaddq_rot270_s<mode>"
1276 (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
1277 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1278 (match_operand:MVE_2 2 "s_register_operand" "w")]
1282 "vhcadd.s%#<V_sz_elem>\t%q0, %q1, %q2, #270"
1283 [(set_attr "type" "mve_move")
1287 ;; [vhcaddq_rot90_s])
1289 (define_insn "mve_vhcaddq_rot90_s<mode>"
1291 (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
1292 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1293 (match_operand:MVE_2 2 "s_register_operand" "w")]
1297 "vhcadd.s%#<V_sz_elem>\t%q0, %q1, %q2, #90"
1298 [(set_attr "type" "mve_move")
1302 ;; [vhsubq_n_u, vhsubq_n_s])
1304 (define_insn "mve_vhsubq_n_<supf><mode>"
1306 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1307 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1308 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1312 "vhsub.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
1313 [(set_attr "type" "mve_move")
1317 ;; [vhsubq_s, vhsubq_u])
1319 (define_insn "mve_vhsubq_<supf><mode>"
1321 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1322 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1323 (match_operand:MVE_2 2 "s_register_operand" "w")]
1327 "vhsub.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1328 [(set_attr "type" "mve_move")
1334 (define_insn "mve_vmaxaq_s<mode>"
1336 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1337 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
1338 (match_operand:MVE_2 2 "s_register_operand" "w")]
1342 "vmaxa.s%#<V_sz_elem> %q0, %q2"
1343 [(set_attr "type" "mve_move")
1349 (define_insn "mve_vmaxavq_s<mode>"
1351 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
1352 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
1353 (match_operand:MVE_2 2 "s_register_operand" "w")]
1357 "vmaxav.s%#<V_sz_elem>\t%0, %q2"
1358 [(set_attr "type" "mve_move")
1362 ;; [vmaxq_u, vmaxq_s])
1364 (define_insn "mve_vmaxq_s<mode>"
1366 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1367 (smax:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
1368 (match_operand:MVE_2 2 "s_register_operand" "w")))
1371 "vmax.%#<V_s_elem>\t%q0, %q1, %q2"
1372 [(set_attr "type" "mve_move")
1375 (define_insn "mve_vmaxq_u<mode>"
1377 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1378 (umax:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
1379 (match_operand:MVE_2 2 "s_register_operand" "w")))
1382 "vmax.%#<V_u_elem>\t%q0, %q1, %q2"
1383 [(set_attr "type" "mve_move")
1387 ;; [vmaxvq_u, vmaxvq_s])
1389 (define_insn "mve_vmaxvq_<supf><mode>"
1391 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
1392 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
1393 (match_operand:MVE_2 2 "s_register_operand" "w")]
1397 "vmaxv.<supf>%#<V_sz_elem>\t%0, %q2"
1398 [(set_attr "type" "mve_move")
1404 (define_insn "mve_vminaq_s<mode>"
1406 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1407 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
1408 (match_operand:MVE_2 2 "s_register_operand" "w")]
1412 "vmina.s%#<V_sz_elem>\t%q0, %q2"
1413 [(set_attr "type" "mve_move")
1419 (define_insn "mve_vminavq_s<mode>"
1421 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
1422 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
1423 (match_operand:MVE_2 2 "s_register_operand" "w")]
1427 "vminav.s%#<V_sz_elem>\t%0, %q2"
1428 [(set_attr "type" "mve_move")
1432 ;; [vminq_s, vminq_u])
1434 (define_insn "mve_vminq_s<mode>"
1436 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1437 (smin:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
1438 (match_operand:MVE_2 2 "s_register_operand" "w")))
1441 "vmin.%#<V_s_elem>\t%q0, %q1, %q2"
1442 [(set_attr "type" "mve_move")
1445 (define_insn "mve_vminq_u<mode>"
1447 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1448 (umin:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
1449 (match_operand:MVE_2 2 "s_register_operand" "w")))
1452 "vmin.%#<V_u_elem>\t%q0, %q1, %q2"
1453 [(set_attr "type" "mve_move")
1457 ;; [vminvq_u, vminvq_s])
1459 (define_insn "mve_vminvq_<supf><mode>"
1461 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
1462 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
1463 (match_operand:MVE_2 2 "s_register_operand" "w")]
1467 "vminv.<supf>%#<V_sz_elem>\t%0, %q2"
1468 [(set_attr "type" "mve_move")
1472 ;; [vmladavq_u, vmladavq_s])
1474 (define_insn "mve_vmladavq_<supf><mode>"
1476 (set (match_operand:SI 0 "s_register_operand" "=Te")
1477 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
1478 (match_operand:MVE_2 2 "s_register_operand" "w")]
1482 "vmladav.<supf>%#<V_sz_elem>\t%0, %q1, %q2"
1483 [(set_attr "type" "mve_move")
1489 (define_insn "mve_vmladavxq_s<mode>"
1491 (set (match_operand:SI 0 "s_register_operand" "=Te")
1492 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
1493 (match_operand:MVE_2 2 "s_register_operand" "w")]
1497 "vmladavx.s%#<V_sz_elem>\t%0, %q1, %q2"
1498 [(set_attr "type" "mve_move")
1504 (define_insn "mve_vmlsdavq_s<mode>"
1506 (set (match_operand:SI 0 "s_register_operand" "=Te")
1507 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
1508 (match_operand:MVE_2 2 "s_register_operand" "w")]
1512 "vmlsdav.s%#<V_sz_elem>\t%0, %q1, %q2"
1513 [(set_attr "type" "mve_move")
1519 (define_insn "mve_vmlsdavxq_s<mode>"
1521 (set (match_operand:SI 0 "s_register_operand" "=Te")
1522 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
1523 (match_operand:MVE_2 2 "s_register_operand" "w")]
1527 "vmlsdavx.s%#<V_sz_elem>\t%0, %q1, %q2"
1528 [(set_attr "type" "mve_move")
1532 ;; [vmulhq_s, vmulhq_u])
1534 (define_insn "mve_vmulhq_<supf><mode>"
1536 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1537 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1538 (match_operand:MVE_2 2 "s_register_operand" "w")]
1542 "vmulh.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1543 [(set_attr "type" "mve_move")
1547 ;; [vmullbq_int_u, vmullbq_int_s])
1549 (define_insn "mve_vmullbq_int_<supf><mode>"
1551 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
1552 (unspec:<V_double_width> [(match_operand:MVE_2 1 "s_register_operand" "w")
1553 (match_operand:MVE_2 2 "s_register_operand" "w")]
1557 "vmullb.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1558 [(set_attr "type" "mve_move")
1562 ;; [vmulltq_int_u, vmulltq_int_s])
1564 (define_insn "mve_vmulltq_int_<supf><mode>"
1566 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
1567 (unspec:<V_double_width> [(match_operand:MVE_2 1 "s_register_operand" "w")
1568 (match_operand:MVE_2 2 "s_register_operand" "w")]
1572 "vmullt.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1573 [(set_attr "type" "mve_move")
1577 ;; [vmulq_n_u, vmulq_n_s])
1579 (define_insn "mve_vmulq_n_<supf><mode>"
1581 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1582 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1583 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1587 "vmul.i%#<V_sz_elem>\t%q0, %q1, %2"
1588 [(set_attr "type" "mve_move")
1592 ;; [vmulq_u, vmulq_s])
1594 (define_insn "mve_vmulq_<supf><mode>"
1596 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1597 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1598 (match_operand:MVE_2 2 "s_register_operand" "w")]
1602 "vmul.i%#<V_sz_elem>\t%q0, %q1, %q2"
1603 [(set_attr "type" "mve_move")
1606 (define_insn "mve_vmulq<mode>"
1608 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1609 (mult:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
1610 (match_operand:MVE_2 2 "s_register_operand" "w")))
1613 "vmul.i%#<V_sz_elem>\t%q0, %q1, %q2"
1614 [(set_attr "type" "mve_move")
1618 ;; [vornq_u, vornq_s])
1620 (define_insn "mve_vornq_<supf><mode>"
1622 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1623 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1624 (match_operand:MVE_2 2 "s_register_operand" "w")]
1628 "vorn %q0, %q1, %q2"
1629 [(set_attr "type" "mve_move")
1633 ;; [vorrq_s, vorrq_u])
1635 ;; signed and unsigned versions are the same: define the unsigned
1636 ;; insn, and use an expander for the signed one as we still reference
1637 ;; both names from arm_mve.h.
1638 ;; We use the same code as in neon.md (TODO: avoid this duplication).
1639 (define_insn "mve_vorrq_s<mode>"
1641 (set (match_operand:MVE_2 0 "s_register_operand" "=w,w")
1642 (ior:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w,0")
1643 (match_operand:MVE_2 2 "neon_logic_op2" "w,Dl")))
1648 * return neon_output_logic_immediate (\"vorr\", &operands[2], <MODE>mode, 0, VALID_NEON_QREG_MODE (<MODE>mode));"
1649 [(set_attr "type" "mve_move")
1651 (define_expand "mve_vorrq_u<mode>"
1653 (set (match_operand:MVE_2 0 "s_register_operand")
1654 (ior:MVE_2 (match_operand:MVE_2 1 "s_register_operand")
1655 (match_operand:MVE_2 2 "neon_logic_op2")))
1661 ;; [vqaddq_n_s, vqaddq_n_u])
1663 (define_insn "mve_vqaddq_n_<supf><mode>"
1665 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1666 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1667 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1671 "vqadd.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
1672 [(set_attr "type" "mve_move")
1676 ;; [vqaddq_u, vqaddq_s])
1678 (define_insn "mve_vqaddq_<supf><mode>"
1680 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1681 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1682 (match_operand:MVE_2 2 "s_register_operand" "w")]
1686 "vqadd.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1687 [(set_attr "type" "mve_move")
1693 (define_insn "mve_vqdmulhq_n_s<mode>"
1695 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1696 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1697 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1701 "vqdmulh.s%#<V_sz_elem>\t%q0, %q1, %2"
1702 [(set_attr "type" "mve_move")
1708 (define_insn "mve_vqdmulhq_s<mode>"
1710 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1711 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1712 (match_operand:MVE_2 2 "s_register_operand" "w")]
1716 "vqdmulh.s%#<V_sz_elem>\t%q0, %q1, %q2"
1717 [(set_attr "type" "mve_move")
1723 (define_insn "mve_vqrdmulhq_n_s<mode>"
1725 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1726 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1727 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1731 "vqrdmulh.s%#<V_sz_elem>\t%q0, %q1, %2"
1732 [(set_attr "type" "mve_move")
1738 (define_insn "mve_vqrdmulhq_s<mode>"
1740 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1741 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1742 (match_operand:MVE_2 2 "s_register_operand" "w")]
1746 "vqrdmulh.s%#<V_sz_elem>\t%q0, %q1, %q2"
1747 [(set_attr "type" "mve_move")
1751 ;; [vqrshlq_n_s, vqrshlq_n_u])
1753 (define_insn "mve_vqrshlq_n_<supf><mode>"
1755 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1756 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
1757 (match_operand:SI 2 "s_register_operand" "r")]
1761 "vqrshl.<supf>%#<V_sz_elem>\t%q0, %2"
1762 [(set_attr "type" "mve_move")
1766 ;; [vqrshlq_s, vqrshlq_u])
1768 (define_insn "mve_vqrshlq_<supf><mode>"
1770 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1771 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1772 (match_operand:MVE_2 2 "s_register_operand" "w")]
1776 "vqrshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1777 [(set_attr "type" "mve_move")
1781 ;; [vqshlq_n_s, vqshlq_n_u])
1783 (define_insn "mve_vqshlq_n_<supf><mode>"
1785 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1786 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1787 (match_operand:SI 2 "immediate_operand" "i")]
1791 "vqshl.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
1792 [(set_attr "type" "mve_move")
1796 ;; [vqshlq_r_u, vqshlq_r_s])
1798 (define_insn "mve_vqshlq_r_<supf><mode>"
1800 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1801 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
1802 (match_operand:SI 2 "s_register_operand" "r")]
1806 "vqshl.<supf>%#<V_sz_elem>\t%q0, %2"
1807 [(set_attr "type" "mve_move")
1811 ;; [vqshlq_s, vqshlq_u])
1813 (define_insn "mve_vqshlq_<supf><mode>"
1815 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1816 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1817 (match_operand:MVE_2 2 "s_register_operand" "w")]
1821 "vqshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1822 [(set_attr "type" "mve_move")
1828 (define_insn "mve_vqshluq_n_s<mode>"
1830 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1831 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1832 (match_operand:SI 2 "mve_imm_7" "Ra")]
1836 "vqshlu.s%#<V_sz_elem>\t%q0, %q1, %2"
1837 [(set_attr "type" "mve_move")
1841 ;; [vqsubq_n_s, vqsubq_n_u])
1843 (define_insn "mve_vqsubq_n_<supf><mode>"
1845 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1846 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1847 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1851 "vqsub.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
1852 [(set_attr "type" "mve_move")
1856 ;; [vqsubq_u, vqsubq_s])
1858 (define_insn "mve_vqsubq_<supf><mode>"
1860 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1861 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1862 (match_operand:MVE_2 2 "s_register_operand" "w")]
1866 "vqsub.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1867 [(set_attr "type" "mve_move")
1871 ;; [vrhaddq_s, vrhaddq_u])
1873 (define_insn "mve_vrhaddq_<supf><mode>"
1875 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1876 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1877 (match_operand:MVE_2 2 "s_register_operand" "w")]
1881 "vrhadd.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1882 [(set_attr "type" "mve_move")
1886 ;; [vrmulhq_s, vrmulhq_u])
1888 (define_insn "mve_vrmulhq_<supf><mode>"
1890 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1891 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1892 (match_operand:MVE_2 2 "s_register_operand" "w")]
1896 "vrmulh.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1897 [(set_attr "type" "mve_move")
1901 ;; [vrshlq_n_u, vrshlq_n_s])
1903 (define_insn "mve_vrshlq_n_<supf><mode>"
1905 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1906 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
1907 (match_operand:SI 2 "s_register_operand" "r")]
1911 "vrshl.<supf>%#<V_sz_elem>\t%q0, %2"
1912 [(set_attr "type" "mve_move")
1916 ;; [vrshlq_s, vrshlq_u])
1918 (define_insn "mve_vrshlq_<supf><mode>"
1920 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1921 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1922 (match_operand:MVE_2 2 "s_register_operand" "w")]
1926 "vrshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1927 [(set_attr "type" "mve_move")
1931 ;; [vrshrq_n_s, vrshrq_n_u])
1933 (define_insn "mve_vrshrq_n_<supf><mode>"
1935 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1936 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1937 (match_operand:SI 2 "<MVE_pred2>" "<MVE_constraint2>")]
1941 "vrshr.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
1942 [(set_attr "type" "mve_move")
1946 ;; [vshlq_n_u, vshlq_n_s])
1948 (define_insn "mve_vshlq_n_<supf><mode>"
1950 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1951 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1952 (match_operand:SI 2 "immediate_operand" "i")]
1956 "vshl.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
1957 [(set_attr "type" "mve_move")
1961 ;; [vshlq_r_s, vshlq_r_u])
1963 (define_insn "mve_vshlq_r_<supf><mode>"
1965 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1966 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
1967 (match_operand:SI 2 "s_register_operand" "r")]
1971 "vshl.<supf>%#<V_sz_elem>\t%q0, %2"
1972 [(set_attr "type" "mve_move")
1976 ;; [vsubq_n_s, vsubq_n_u])
1978 (define_insn "mve_vsubq_n_<supf><mode>"
1980 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1981 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1982 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1986 "vsub.i%#<V_sz_elem>\t%q0, %q1, %2"
1987 [(set_attr "type" "mve_move")
1991 ;; [vsubq_s, vsubq_u])
1993 (define_insn "mve_vsubq_<supf><mode>"
1995 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1996 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1997 (match_operand:MVE_2 2 "s_register_operand" "w")]
2001 "vsub.i%#<V_sz_elem>\t%q0, %q1, %q2"
2002 [(set_attr "type" "mve_move")
2005 (define_insn "mve_vsubq<mode>"
2007 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2008 (minus:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
2009 (match_operand:MVE_2 2 "s_register_operand" "w")))
2012 "vsub.i%#<V_sz_elem>\t%q0, %q1, %q2"
2013 [(set_attr "type" "mve_move")
2019 (define_insn "mve_vabdq_f<mode>"
2021 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2022 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2023 (match_operand:MVE_0 2 "s_register_operand" "w")]
2026 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2027 "vabd.f%#<V_sz_elem> %q0, %q1, %q2"
2028 [(set_attr "type" "mve_move")
2032 ;; [vaddlvaq_s vaddlvaq_u])
2034 (define_insn "mve_vaddlvaq_<supf>v4si"
2036 (set (match_operand:DI 0 "s_register_operand" "=r")
2037 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
2038 (match_operand:V4SI 2 "s_register_operand" "w")]
2042 "vaddlva.<supf>32 %Q0, %R0, %q2"
2043 [(set_attr "type" "mve_move")
2049 (define_insn "mve_vaddq_n_f<mode>"
2051 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2052 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2053 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2056 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2057 "vadd.f%#<V_sz_elem> %q0, %q1, %2"
2058 [(set_attr "type" "mve_move")
2064 (define_insn "mve_vandq_f<mode>"
2066 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2067 (and:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")
2068 (match_operand:MVE_0 2 "s_register_operand" "w")))
2070 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2071 "vand %q0, %q1, %q2"
2072 [(set_attr "type" "mve_move")
2078 (define_insn "mve_vbicq_f<mode>"
2080 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2081 (and:MVE_0 (not:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w"))
2082 (match_operand:MVE_0 2 "s_register_operand" "w")))
2084 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2085 "vbic %q0, %q1, %q2"
2086 [(set_attr "type" "mve_move")
2090 ;; [vbicq_n_s, vbicq_n_u])
2092 (define_insn "mve_vbicq_n_<supf><mode>"
2094 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
2095 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
2096 (match_operand:SI 2 "immediate_operand" "i")]
2100 "vbic.i%#<V_sz_elem> %q0, %2"
2101 [(set_attr "type" "mve_move")
2105 ;; [vcaddq_rot270_f])
2107 (define_insn "mve_vcaddq_rot270_f<mode>"
2109 (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
2110 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2111 (match_operand:MVE_0 2 "s_register_operand" "w")]
2114 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2115 "vcadd.f%#<V_sz_elem> %q0, %q1, %q2, #270"
2116 [(set_attr "type" "mve_move")
2120 ;; [vcaddq_rot90_f])
2122 (define_insn "mve_vcaddq_rot90_f<mode>"
2124 (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
2125 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2126 (match_operand:MVE_0 2 "s_register_operand" "w")]
2129 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2130 "vcadd.f%#<V_sz_elem> %q0, %q1, %q2, #90"
2131 [(set_attr "type" "mve_move")
2137 (define_insn "mve_vcmpeqq_f<mode>"
2139 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2140 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2141 (match_operand:MVE_0 2 "s_register_operand" "w")]
2144 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2145 "vcmp.f%#<V_sz_elem> eq, %q1, %q2"
2146 [(set_attr "type" "mve_move")
2152 (define_insn "mve_vcmpeqq_n_f<mode>"
2154 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2155 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2156 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2159 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2160 "vcmp.f%#<V_sz_elem> eq, %q1, %2"
2161 [(set_attr "type" "mve_move")
2167 (define_insn "mve_vcmpgeq_f<mode>"
2169 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2170 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2171 (match_operand:MVE_0 2 "s_register_operand" "w")]
2174 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2175 "vcmp.f%#<V_sz_elem> ge, %q1, %q2"
2176 [(set_attr "type" "mve_move")
2182 (define_insn "mve_vcmpgeq_n_f<mode>"
2184 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2185 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2186 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2189 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2190 "vcmp.f%#<V_sz_elem> ge, %q1, %2"
2191 [(set_attr "type" "mve_move")
2197 (define_insn "mve_vcmpgtq_f<mode>"
2199 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2200 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2201 (match_operand:MVE_0 2 "s_register_operand" "w")]
2204 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2205 "vcmp.f%#<V_sz_elem> gt, %q1, %q2"
2206 [(set_attr "type" "mve_move")
2212 (define_insn "mve_vcmpgtq_n_f<mode>"
2214 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2215 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2216 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2219 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2220 "vcmp.f%#<V_sz_elem> gt, %q1, %2"
2221 [(set_attr "type" "mve_move")
2227 (define_insn "mve_vcmpleq_f<mode>"
2229 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2230 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2231 (match_operand:MVE_0 2 "s_register_operand" "w")]
2234 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2235 "vcmp.f%#<V_sz_elem> le, %q1, %q2"
2236 [(set_attr "type" "mve_move")
2242 (define_insn "mve_vcmpleq_n_f<mode>"
2244 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2245 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2246 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2249 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2250 "vcmp.f%#<V_sz_elem> le, %q1, %2"
2251 [(set_attr "type" "mve_move")
2257 (define_insn "mve_vcmpltq_f<mode>"
2259 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2260 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2261 (match_operand:MVE_0 2 "s_register_operand" "w")]
2264 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2265 "vcmp.f%#<V_sz_elem> lt, %q1, %q2"
2266 [(set_attr "type" "mve_move")
2272 (define_insn "mve_vcmpltq_n_f<mode>"
2274 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2275 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2276 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2279 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2280 "vcmp.f%#<V_sz_elem> lt, %q1, %2"
2281 [(set_attr "type" "mve_move")
2287 (define_insn "mve_vcmpneq_f<mode>"
2289 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2290 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2291 (match_operand:MVE_0 2 "s_register_operand" "w")]
2294 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2295 "vcmp.f%#<V_sz_elem> ne, %q1, %q2"
2296 [(set_attr "type" "mve_move")
2302 (define_insn "mve_vcmpneq_n_f<mode>"
2304 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2305 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2306 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2309 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2310 "vcmp.f%#<V_sz_elem> ne, %q1, %2"
2311 [(set_attr "type" "mve_move")
2317 (define_insn "mve_vcmulq_f<mode>"
2319 (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
2320 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2321 (match_operand:MVE_0 2 "s_register_operand" "w")]
2324 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2325 "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #0"
2326 [(set_attr "type" "mve_move")
2330 ;; [vcmulq_rot180_f])
2332 (define_insn "mve_vcmulq_rot180_f<mode>"
2334 (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
2335 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2336 (match_operand:MVE_0 2 "s_register_operand" "w")]
2339 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2340 "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #180"
2341 [(set_attr "type" "mve_move")
2345 ;; [vcmulq_rot270_f])
2347 (define_insn "mve_vcmulq_rot270_f<mode>"
2349 (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
2350 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2351 (match_operand:MVE_0 2 "s_register_operand" "w")]
2354 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2355 "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #270"
2356 [(set_attr "type" "mve_move")
2360 ;; [vcmulq_rot90_f])
2362 (define_insn "mve_vcmulq_rot90_f<mode>"
2364 (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
2365 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2366 (match_operand:MVE_0 2 "s_register_operand" "w")]
2369 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2370 "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #90"
2371 [(set_attr "type" "mve_move")
2375 ;; [vctp8q_m vctp16q_m vctp32q_m vctp64q_m])
2377 (define_insn "mve_vctp<mode1>q_mhi"
2379 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2380 (unspec:HI [(match_operand:SI 1 "s_register_operand" "r")
2381 (match_operand:HI 2 "vpr_register_operand" "Up")]
2385 "vpst\;vctpt.<mode1> %1"
2386 [(set_attr "type" "mve_move")
2387 (set_attr "length""8")])
2390 ;; [vcvtbq_f16_f32])
2392 (define_insn "mve_vcvtbq_f16_f32v8hf"
2394 (set (match_operand:V8HF 0 "s_register_operand" "=w")
2395 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
2396 (match_operand:V4SF 2 "s_register_operand" "w")]
2399 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2400 "vcvtb.f16.f32 %q0, %q2"
2401 [(set_attr "type" "mve_move")
2405 ;; [vcvttq_f16_f32])
2407 (define_insn "mve_vcvttq_f16_f32v8hf"
2409 (set (match_operand:V8HF 0 "s_register_operand" "=w")
2410 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
2411 (match_operand:V4SF 2 "s_register_operand" "w")]
2414 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2415 "vcvtt.f16.f32 %q0, %q2"
2416 [(set_attr "type" "mve_move")
2422 (define_insn "mve_veorq_f<mode>"
2424 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2425 (xor:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")
2426 (match_operand:MVE_0 2 "s_register_operand" "w")))
2428 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2429 "veor %q0, %q1, %q2"
2430 [(set_attr "type" "mve_move")
2436 (define_insn "mve_vmaxnmaq_f<mode>"
2438 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2439 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
2440 (match_operand:MVE_0 2 "s_register_operand" "w")]
2443 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2444 "vmaxnma.f%#<V_sz_elem> %q0, %q2"
2445 [(set_attr "type" "mve_move")
2451 (define_insn "mve_vmaxnmavq_f<mode>"
2453 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
2454 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
2455 (match_operand:MVE_0 2 "s_register_operand" "w")]
2458 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2459 "vmaxnmav.f%#<V_sz_elem> %0, %q2"
2460 [(set_attr "type" "mve_move")
2466 (define_insn "mve_vmaxnmq_f<mode>"
2468 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2469 (smax:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")
2470 (match_operand:MVE_0 2 "s_register_operand" "w")))
2472 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2473 "vmaxnm.f%#<V_sz_elem> %q0, %q1, %q2"
2474 [(set_attr "type" "mve_move")
2480 (define_insn "mve_vmaxnmvq_f<mode>"
2482 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
2483 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
2484 (match_operand:MVE_0 2 "s_register_operand" "w")]
2487 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2488 "vmaxnmv.f%#<V_sz_elem> %0, %q2"
2489 [(set_attr "type" "mve_move")
2495 (define_insn "mve_vminnmaq_f<mode>"
2497 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2498 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
2499 (match_operand:MVE_0 2 "s_register_operand" "w")]
2502 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2503 "vminnma.f%#<V_sz_elem> %q0, %q2"
2504 [(set_attr "type" "mve_move")
2510 (define_insn "mve_vminnmavq_f<mode>"
2512 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
2513 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
2514 (match_operand:MVE_0 2 "s_register_operand" "w")]
2517 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2518 "vminnmav.f%#<V_sz_elem> %0, %q2"
2519 [(set_attr "type" "mve_move")
2525 (define_insn "mve_vminnmq_f<mode>"
2527 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2528 (smin:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")
2529 (match_operand:MVE_0 2 "s_register_operand" "w")))
2531 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2532 "vminnm.f%#<V_sz_elem> %q0, %q1, %q2"
2533 [(set_attr "type" "mve_move")
2539 (define_insn "mve_vminnmvq_f<mode>"
2541 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
2542 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
2543 (match_operand:MVE_0 2 "s_register_operand" "w")]
2546 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2547 "vminnmv.f%#<V_sz_elem> %0, %q2"
2548 [(set_attr "type" "mve_move")
2552 ;; [vmlaldavq_u, vmlaldavq_s])
2554 (define_insn "mve_vmlaldavq_<supf><mode>"
2556 (set (match_operand:DI 0 "s_register_operand" "=r")
2557 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
2558 (match_operand:MVE_5 2 "s_register_operand" "w")]
2562 "vmlaldav.<supf>%#<V_sz_elem> %Q0, %R0, %q1, %q2"
2563 [(set_attr "type" "mve_move")
2569 (define_insn "mve_vmlaldavxq_s<mode>"
2571 (set (match_operand:DI 0 "s_register_operand" "=r")
2572 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
2573 (match_operand:MVE_5 2 "s_register_operand" "w")]
2577 "vmlaldavx.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
2578 [(set_attr "type" "mve_move")
2584 (define_insn "mve_vmlsldavq_s<mode>"
2586 (set (match_operand:DI 0 "s_register_operand" "=r")
2587 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
2588 (match_operand:MVE_5 2 "s_register_operand" "w")]
2592 "vmlsldav.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
2593 [(set_attr "type" "mve_move")
2599 (define_insn "mve_vmlsldavxq_s<mode>"
2601 (set (match_operand:DI 0 "s_register_operand" "=r")
2602 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
2603 (match_operand:MVE_5 2 "s_register_operand" "w")]
2607 "vmlsldavx.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
2608 [(set_attr "type" "mve_move")
2612 ;; [vmovnbq_u, vmovnbq_s])
2614 (define_insn "mve_vmovnbq_<supf><mode>"
2616 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
2617 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
2618 (match_operand:MVE_5 2 "s_register_operand" "w")]
2622 "vmovnb.i%#<V_sz_elem> %q0, %q2"
2623 [(set_attr "type" "mve_move")
2627 ;; [vmovntq_s, vmovntq_u])
2629 (define_insn "mve_vmovntq_<supf><mode>"
2631 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
2632 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
2633 (match_operand:MVE_5 2 "s_register_operand" "w")]
2637 "vmovnt.i%#<V_sz_elem> %q0, %q2"
2638 [(set_attr "type" "mve_move")
2644 (define_insn "mve_vmulq_f<mode>"
2646 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2647 (mult:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")
2648 (match_operand:MVE_0 2 "s_register_operand" "w")))
2650 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2651 "vmul.f%#<V_sz_elem> %q0, %q1, %q2"
2652 [(set_attr "type" "mve_move")
2658 (define_insn "mve_vmulq_n_f<mode>"
2660 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2661 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2662 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2665 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2666 "vmul.f%#<V_sz_elem> %q0, %q1, %2"
2667 [(set_attr "type" "mve_move")
2673 (define_insn "mve_vornq_f<mode>"
2675 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2676 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2677 (match_operand:MVE_0 2 "s_register_operand" "w")]
2680 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2681 "vorn %q0, %q1, %q2"
2682 [(set_attr "type" "mve_move")
2688 (define_insn "mve_vorrq_f<mode>"
2690 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2691 (ior:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")
2692 (match_operand:MVE_0 2 "s_register_operand" "w")))
2694 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2695 "vorr %q0, %q1, %q2"
2696 [(set_attr "type" "mve_move")
2700 ;; [vorrq_n_u, vorrq_n_s])
2702 (define_insn "mve_vorrq_n_<supf><mode>"
2704 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
2705 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
2706 (match_operand:SI 2 "immediate_operand" "i")]
2710 "vorr.i%#<V_sz_elem> %q0, %2"
2711 [(set_attr "type" "mve_move")
2717 (define_insn "mve_vqdmullbq_n_s<mode>"
2719 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
2720 (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w")
2721 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2725 "vqdmullb.s%#<V_sz_elem> %q0, %q1, %2"
2726 [(set_attr "type" "mve_move")
2732 (define_insn "mve_vqdmullbq_s<mode>"
2734 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
2735 (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w")
2736 (match_operand:MVE_5 2 "s_register_operand" "w")]
2740 "vqdmullb.s%#<V_sz_elem> %q0, %q1, %q2"
2741 [(set_attr "type" "mve_move")
2747 (define_insn "mve_vqdmulltq_n_s<mode>"
2749 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
2750 (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w")
2751 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2755 "vqdmullt.s%#<V_sz_elem> %q0, %q1, %2"
2756 [(set_attr "type" "mve_move")
2762 (define_insn "mve_vqdmulltq_s<mode>"
2764 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
2765 (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w")
2766 (match_operand:MVE_5 2 "s_register_operand" "w")]
2770 "vqdmullt.s%#<V_sz_elem> %q0, %q1, %q2"
2771 [(set_attr "type" "mve_move")
2775 ;; [vqmovnbq_u, vqmovnbq_s])
2777 (define_insn "mve_vqmovnbq_<supf><mode>"
2779 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
2780 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
2781 (match_operand:MVE_5 2 "s_register_operand" "w")]
2785 "vqmovnb.<supf>%#<V_sz_elem> %q0, %q2"
2786 [(set_attr "type" "mve_move")
2790 ;; [vqmovntq_u, vqmovntq_s])
2792 (define_insn "mve_vqmovntq_<supf><mode>"
2794 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
2795 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
2796 (match_operand:MVE_5 2 "s_register_operand" "w")]
2800 "vqmovnt.<supf>%#<V_sz_elem> %q0, %q2"
2801 [(set_attr "type" "mve_move")
2807 (define_insn "mve_vqmovunbq_s<mode>"
2809 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
2810 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
2811 (match_operand:MVE_5 2 "s_register_operand" "w")]
2815 "vqmovunb.s%#<V_sz_elem> %q0, %q2"
2816 [(set_attr "type" "mve_move")
2822 (define_insn "mve_vqmovuntq_s<mode>"
2824 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
2825 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
2826 (match_operand:MVE_5 2 "s_register_operand" "w")]
2830 "vqmovunt.s%#<V_sz_elem> %q0, %q2"
2831 [(set_attr "type" "mve_move")
2835 ;; [vrmlaldavhxq_s])
2837 (define_insn "mve_vrmlaldavhxq_sv4si"
2839 (set (match_operand:DI 0 "s_register_operand" "=r")
2840 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
2841 (match_operand:V4SI 2 "s_register_operand" "w")]
2845 "vrmlaldavhx.s32 %Q0, %R0, %q1, %q2"
2846 [(set_attr "type" "mve_move")
2852 (define_insn "mve_vrmlsldavhq_sv4si"
2854 (set (match_operand:DI 0 "s_register_operand" "=r")
2855 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
2856 (match_operand:V4SI 2 "s_register_operand" "w")]
2860 "vrmlsldavh.s32\t%Q0, %R0, %q1, %q2"
2861 [(set_attr "type" "mve_move")
2865 ;; [vrmlsldavhxq_s])
2867 (define_insn "mve_vrmlsldavhxq_sv4si"
2869 (set (match_operand:DI 0 "s_register_operand" "=r")
2870 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
2871 (match_operand:V4SI 2 "s_register_operand" "w")]
2875 "vrmlsldavhx.s32\t%Q0, %R0, %q1, %q2"
2876 [(set_attr "type" "mve_move")
2880 ;; [vshllbq_n_s, vshllbq_n_u])
2882 (define_insn "mve_vshllbq_n_<supf><mode>"
2884 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
2885 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")
2886 (match_operand:SI 2 "immediate_operand" "i")]
2890 "vshllb.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
2891 [(set_attr "type" "mve_move")
2895 ;; [vshlltq_n_u, vshlltq_n_s])
2897 (define_insn "mve_vshlltq_n_<supf><mode>"
2899 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
2900 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")
2901 (match_operand:SI 2 "immediate_operand" "i")]
2905 "vshllt.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
2906 [(set_attr "type" "mve_move")
2912 (define_insn "mve_vsubq_f<mode>"
2914 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2915 (minus:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")
2916 (match_operand:MVE_0 2 "s_register_operand" "w")))
2918 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2919 "vsub.f%#<V_sz_elem>\t%q0, %q1, %q2"
2920 [(set_attr "type" "mve_move")
2924 ;; [vmulltq_poly_p])
2926 (define_insn "mve_vmulltq_poly_p<mode>"
2928 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
2929 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")
2930 (match_operand:MVE_3 2 "s_register_operand" "w")]
2934 "vmullt.p%#<V_sz_elem>\t%q0, %q1, %q2"
2935 [(set_attr "type" "mve_move")
2939 ;; [vmullbq_poly_p])
2941 (define_insn "mve_vmullbq_poly_p<mode>"
2943 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
2944 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")
2945 (match_operand:MVE_3 2 "s_register_operand" "w")]
2949 "vmullb.p%#<V_sz_elem>\t%q0, %q1, %q2"
2950 [(set_attr "type" "mve_move")
2954 ;; [vrmlaldavhq_u vrmlaldavhq_s])
2956 (define_insn "mve_vrmlaldavhq_<supf>v4si"
2958 (set (match_operand:DI 0 "s_register_operand" "=r")
2959 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
2960 (match_operand:V4SI 2 "s_register_operand" "w")]
2964 "vrmlaldavh.<supf>32 %Q0, %R0, %q1, %q2"
2965 [(set_attr "type" "mve_move")
2969 ;; [vbicq_m_n_s, vbicq_m_n_u])
2971 (define_insn "mve_vbicq_m_n_<supf><mode>"
2973 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
2974 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
2975 (match_operand:SI 2 "immediate_operand" "i")
2976 (match_operand:HI 3 "vpr_register_operand" "Up")]
2980 "vpst\;vbict.i%#<V_sz_elem> %q0, %2"
2981 [(set_attr "type" "mve_move")
2982 (set_attr "length""8")])
2986 (define_insn "mve_vcmpeqq_m_f<mode>"
2988 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2989 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2990 (match_operand:MVE_0 2 "s_register_operand" "w")
2991 (match_operand:HI 3 "vpr_register_operand" "Up")]
2994 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2995 "vpst\;vcmpt.f%#<V_sz_elem> eq, %q1, %q2"
2996 [(set_attr "type" "mve_move")
2997 (set_attr "length""8")])
2999 ;; [vcvtaq_m_u, vcvtaq_m_s])
3001 (define_insn "mve_vcvtaq_m_<supf><mode>"
3003 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
3004 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
3005 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
3006 (match_operand:HI 3 "vpr_register_operand" "Up")]
3009 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3010 "vpst\;vcvtat.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
3011 [(set_attr "type" "mve_move")
3012 (set_attr "length""8")])
3014 ;; [vcvtq_m_to_f_s, vcvtq_m_to_f_u])
3016 (define_insn "mve_vcvtq_m_to_f_<supf><mode>"
3018 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
3019 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
3020 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
3021 (match_operand:HI 3 "vpr_register_operand" "Up")]
3024 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3025 "vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem> %q0, %q2"
3026 [(set_attr "type" "mve_move")
3027 (set_attr "length""8")])
3029 ;; [vqrshrnbq_n_u, vqrshrnbq_n_s])
3031 (define_insn "mve_vqrshrnbq_n_<supf><mode>"
3033 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3034 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3035 (match_operand:MVE_5 2 "s_register_operand" "w")
3036 (match_operand:SI 3 "mve_imm_8" "Rb")]
3040 "vqrshrnb.<supf>%#<V_sz_elem> %q0, %q2, %3"
3041 [(set_attr "type" "mve_move")
3044 ;; [vqrshrunbq_n_s])
3046 (define_insn "mve_vqrshrunbq_n_s<mode>"
3048 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3049 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3050 (match_operand:MVE_5 2 "s_register_operand" "w")
3051 (match_operand:SI 3 "mve_imm_8" "Rb")]
3055 "vqrshrunb.s%#<V_sz_elem>\t%q0, %q2, %3"
3056 [(set_attr "type" "mve_move")
3059 ;; [vrmlaldavhaq_s vrmlaldavhaq_u])
3061 (define_insn "mve_vrmlaldavhaq_<supf>v4si"
3063 (set (match_operand:DI 0 "s_register_operand" "=r")
3064 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
3065 (match_operand:V4SI 2 "s_register_operand" "w")
3066 (match_operand:V4SI 3 "s_register_operand" "w")]
3070 "vrmlaldavha.<supf>32 %Q0, %R0, %q2, %q3"
3071 [(set_attr "type" "mve_move")
3075 ;; [vabavq_s, vabavq_u])
3077 (define_insn "mve_vabavq_<supf><mode>"
3079 (set (match_operand:SI 0 "s_register_operand" "=r")
3080 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
3081 (match_operand:MVE_2 2 "s_register_operand" "w")
3082 (match_operand:MVE_2 3 "s_register_operand" "w")]
3086 "vabav.<supf>%#<V_sz_elem>\t%0, %q2, %q3"
3087 [(set_attr "type" "mve_move")
3091 ;; [vshlcq_u vshlcq_s]
3093 (define_expand "mve_vshlcq_vec_<supf><mode>"
3094 [(match_operand:MVE_2 0 "s_register_operand")
3095 (match_operand:MVE_2 1 "s_register_operand")
3096 (match_operand:SI 2 "s_register_operand")
3097 (match_operand:SI 3 "mve_imm_32")
3098 (unspec:MVE_2 [(const_int 0)] VSHLCQ)]
3101 rtx ignore_wb = gen_reg_rtx (SImode);
3102 emit_insn(gen_mve_vshlcq_<supf><mode>(operands[0], ignore_wb, operands[1],
3103 operands[2], operands[3]));
3107 (define_expand "mve_vshlcq_carry_<supf><mode>"
3108 [(match_operand:SI 0 "s_register_operand")
3109 (match_operand:MVE_2 1 "s_register_operand")
3110 (match_operand:SI 2 "s_register_operand")
3111 (match_operand:SI 3 "mve_imm_32")
3112 (unspec:MVE_2 [(const_int 0)] VSHLCQ)]
3115 rtx ignore_vec = gen_reg_rtx (<MODE>mode);
3116 emit_insn(gen_mve_vshlcq_<supf><mode>(ignore_vec, operands[0], operands[1],
3117 operands[2], operands[3]));
3121 (define_insn "mve_vshlcq_<supf><mode>"
3122 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
3123 (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0")
3124 (match_operand:SI 3 "s_register_operand" "1")
3125 (match_operand:SI 4 "mve_imm_32" "Rf")]
3127 (set (match_operand:SI 1 "s_register_operand" "=r")
3128 (unspec:SI [(match_dup 2)
3133 "vshlc %q0, %1, %4")
3138 (define_insn "mve_vabsq_m_s<mode>"
3140 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3141 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3142 (match_operand:MVE_2 2 "s_register_operand" "w")
3143 (match_operand:HI 3 "vpr_register_operand" "Up")]
3147 "vpst\;vabst.s%#<V_sz_elem> %q0, %q2"
3148 [(set_attr "type" "mve_move")
3149 (set_attr "length""8")])
3152 ;; [vaddvaq_p_u, vaddvaq_p_s])
3154 (define_insn "mve_vaddvaq_p_<supf><mode>"
3156 (set (match_operand:SI 0 "s_register_operand" "=Te")
3157 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
3158 (match_operand:MVE_2 2 "s_register_operand" "w")
3159 (match_operand:HI 3 "vpr_register_operand" "Up")]
3163 "vpst\;vaddvat.<supf>%#<V_sz_elem> %0, %q2"
3164 [(set_attr "type" "mve_move")
3165 (set_attr "length""8")])
3170 (define_insn "mve_vclsq_m_s<mode>"
3172 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3173 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3174 (match_operand:MVE_2 2 "s_register_operand" "w")
3175 (match_operand:HI 3 "vpr_register_operand" "Up")]
3179 "vpst\;vclst.s%#<V_sz_elem> %q0, %q2"
3180 [(set_attr "type" "mve_move")
3181 (set_attr "length""8")])
3184 ;; [vclzq_m_s, vclzq_m_u])
3186 (define_insn "mve_vclzq_m_<supf><mode>"
3188 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3189 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3190 (match_operand:MVE_2 2 "s_register_operand" "w")
3191 (match_operand:HI 3 "vpr_register_operand" "Up")]
3195 "vpst\;vclzt.i%#<V_sz_elem> %q0, %q2"
3196 [(set_attr "type" "mve_move")
3197 (set_attr "length""8")])
3202 (define_insn "mve_vcmpcsq_m_n_u<mode>"
3204 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3205 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3206 (match_operand:<V_elem> 2 "s_register_operand" "r")
3207 (match_operand:HI 3 "vpr_register_operand" "Up")]
3211 "vpst\;vcmpt.u%#<V_sz_elem> cs, %q1, %2"
3212 [(set_attr "type" "mve_move")
3213 (set_attr "length""8")])
3218 (define_insn "mve_vcmpcsq_m_u<mode>"
3220 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3221 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3222 (match_operand:MVE_2 2 "s_register_operand" "w")
3223 (match_operand:HI 3 "vpr_register_operand" "Up")]
3227 "vpst\;vcmpt.u%#<V_sz_elem> cs, %q1, %q2"
3228 [(set_attr "type" "mve_move")
3229 (set_attr "length""8")])
3232 ;; [vcmpeqq_m_n_u, vcmpeqq_m_n_s])
3234 (define_insn "mve_vcmpeqq_m_n_<supf><mode>"
3236 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3237 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3238 (match_operand:<V_elem> 2 "s_register_operand" "r")
3239 (match_operand:HI 3 "vpr_register_operand" "Up")]
3243 "vpst\;vcmpt.i%#<V_sz_elem> eq, %q1, %2"
3244 [(set_attr "type" "mve_move")
3245 (set_attr "length""8")])
3248 ;; [vcmpeqq_m_u, vcmpeqq_m_s])
3250 (define_insn "mve_vcmpeqq_m_<supf><mode>"
3252 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3253 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3254 (match_operand:MVE_2 2 "s_register_operand" "w")
3255 (match_operand:HI 3 "vpr_register_operand" "Up")]
3259 "vpst\;vcmpt.i%#<V_sz_elem> eq, %q1, %q2"
3260 [(set_attr "type" "mve_move")
3261 (set_attr "length""8")])
3266 (define_insn "mve_vcmpgeq_m_n_s<mode>"
3268 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3269 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3270 (match_operand:<V_elem> 2 "s_register_operand" "r")
3271 (match_operand:HI 3 "vpr_register_operand" "Up")]
3275 "vpst\;vcmpt.s%#<V_sz_elem> ge, %q1, %2"
3276 [(set_attr "type" "mve_move")
3277 (set_attr "length""8")])
3282 (define_insn "mve_vcmpgeq_m_s<mode>"
3284 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3285 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3286 (match_operand:MVE_2 2 "s_register_operand" "w")
3287 (match_operand:HI 3 "vpr_register_operand" "Up")]
3291 "vpst\;vcmpt.s%#<V_sz_elem> ge, %q1, %q2"
3292 [(set_attr "type" "mve_move")
3293 (set_attr "length""8")])
3298 (define_insn "mve_vcmpgtq_m_n_s<mode>"
3300 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3301 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3302 (match_operand:<V_elem> 2 "s_register_operand" "r")
3303 (match_operand:HI 3 "vpr_register_operand" "Up")]
3307 "vpst\;vcmpt.s%#<V_sz_elem> gt, %q1, %2"
3308 [(set_attr "type" "mve_move")
3309 (set_attr "length""8")])
3314 (define_insn "mve_vcmpgtq_m_s<mode>"
3316 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3317 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3318 (match_operand:MVE_2 2 "s_register_operand" "w")
3319 (match_operand:HI 3 "vpr_register_operand" "Up")]
3323 "vpst\;vcmpt.s%#<V_sz_elem> gt, %q1, %q2"
3324 [(set_attr "type" "mve_move")
3325 (set_attr "length""8")])
3330 (define_insn "mve_vcmphiq_m_n_u<mode>"
3332 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3333 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3334 (match_operand:<V_elem> 2 "s_register_operand" "r")
3335 (match_operand:HI 3 "vpr_register_operand" "Up")]
3339 "vpst\;vcmpt.u%#<V_sz_elem> hi, %q1, %2"
3340 [(set_attr "type" "mve_move")
3341 (set_attr "length""8")])
3346 (define_insn "mve_vcmphiq_m_u<mode>"
3348 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3349 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3350 (match_operand:MVE_2 2 "s_register_operand" "w")
3351 (match_operand:HI 3 "vpr_register_operand" "Up")]
3355 "vpst\;vcmpt.u%#<V_sz_elem> hi, %q1, %q2"
3356 [(set_attr "type" "mve_move")
3357 (set_attr "length""8")])
3362 (define_insn "mve_vcmpleq_m_n_s<mode>"
3364 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3365 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3366 (match_operand:<V_elem> 2 "s_register_operand" "r")
3367 (match_operand:HI 3 "vpr_register_operand" "Up")]
3371 "vpst\;vcmpt.s%#<V_sz_elem> le, %q1, %2"
3372 [(set_attr "type" "mve_move")
3373 (set_attr "length""8")])
3378 (define_insn "mve_vcmpleq_m_s<mode>"
3380 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3381 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3382 (match_operand:MVE_2 2 "s_register_operand" "w")
3383 (match_operand:HI 3 "vpr_register_operand" "Up")]
3387 "vpst\;vcmpt.s%#<V_sz_elem> le, %q1, %q2"
3388 [(set_attr "type" "mve_move")
3389 (set_attr "length""8")])
3394 (define_insn "mve_vcmpltq_m_n_s<mode>"
3396 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3397 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3398 (match_operand:<V_elem> 2 "s_register_operand" "r")
3399 (match_operand:HI 3 "vpr_register_operand" "Up")]
3403 "vpst\;vcmpt.s%#<V_sz_elem> lt, %q1, %2"
3404 [(set_attr "type" "mve_move")
3405 (set_attr "length""8")])
3410 (define_insn "mve_vcmpltq_m_s<mode>"
3412 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3413 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3414 (match_operand:MVE_2 2 "s_register_operand" "w")
3415 (match_operand:HI 3 "vpr_register_operand" "Up")]
3419 "vpst\;vcmpt.s%#<V_sz_elem> lt, %q1, %q2"
3420 [(set_attr "type" "mve_move")
3421 (set_attr "length""8")])
3424 ;; [vcmpneq_m_n_u, vcmpneq_m_n_s])
3426 (define_insn "mve_vcmpneq_m_n_<supf><mode>"
3428 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3429 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3430 (match_operand:<V_elem> 2 "s_register_operand" "r")
3431 (match_operand:HI 3 "vpr_register_operand" "Up")]
3435 "vpst\;vcmpt.i%#<V_sz_elem> ne, %q1, %2"
3436 [(set_attr "type" "mve_move")
3437 (set_attr "length""8")])
3440 ;; [vcmpneq_m_s, vcmpneq_m_u])
3442 (define_insn "mve_vcmpneq_m_<supf><mode>"
3444 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3445 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3446 (match_operand:MVE_2 2 "s_register_operand" "w")
3447 (match_operand:HI 3 "vpr_register_operand" "Up")]
3451 "vpst\;vcmpt.i%#<V_sz_elem> ne, %q1, %q2"
3452 [(set_attr "type" "mve_move")
3453 (set_attr "length""8")])
3456 ;; [vdupq_m_n_s, vdupq_m_n_u])
3458 (define_insn "mve_vdupq_m_n_<supf><mode>"
3460 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3461 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3462 (match_operand:<V_elem> 2 "s_register_operand" "r")
3463 (match_operand:HI 3 "vpr_register_operand" "Up")]
3467 "vpst\;vdupt.%#<V_sz_elem> %q0, %2"
3468 [(set_attr "type" "mve_move")
3469 (set_attr "length""8")])
3474 (define_insn "mve_vmaxaq_m_s<mode>"
3476 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3477 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3478 (match_operand:MVE_2 2 "s_register_operand" "w")
3479 (match_operand:HI 3 "vpr_register_operand" "Up")]
3483 "vpst\;vmaxat.s%#<V_sz_elem> %q0, %q2"
3484 [(set_attr "type" "mve_move")
3485 (set_attr "length""8")])
3490 (define_insn "mve_vmaxavq_p_s<mode>"
3492 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
3493 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
3494 (match_operand:MVE_2 2 "s_register_operand" "w")
3495 (match_operand:HI 3 "vpr_register_operand" "Up")]
3499 "vpst\;vmaxavt.s%#<V_sz_elem> %0, %q2"
3500 [(set_attr "type" "mve_move")
3501 (set_attr "length""8")])
3504 ;; [vmaxvq_p_u, vmaxvq_p_s])
3506 (define_insn "mve_vmaxvq_p_<supf><mode>"
3508 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
3509 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
3510 (match_operand:MVE_2 2 "s_register_operand" "w")
3511 (match_operand:HI 3 "vpr_register_operand" "Up")]
3515 "vpst\;vmaxvt.<supf>%#<V_sz_elem> %0, %q2"
3516 [(set_attr "type" "mve_move")
3517 (set_attr "length""8")])
3522 (define_insn "mve_vminaq_m_s<mode>"
3524 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3525 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3526 (match_operand:MVE_2 2 "s_register_operand" "w")
3527 (match_operand:HI 3 "vpr_register_operand" "Up")]
3531 "vpst\;vminat.s%#<V_sz_elem> %q0, %q2"
3532 [(set_attr "type" "mve_move")
3533 (set_attr "length""8")])
3538 (define_insn "mve_vminavq_p_s<mode>"
3540 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
3541 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
3542 (match_operand:MVE_2 2 "s_register_operand" "w")
3543 (match_operand:HI 3 "vpr_register_operand" "Up")]
3547 "vpst\;vminavt.s%#<V_sz_elem> %0, %q2"
3548 [(set_attr "type" "mve_move")
3549 (set_attr "length""8")])
3552 ;; [vminvq_p_s, vminvq_p_u])
3554 (define_insn "mve_vminvq_p_<supf><mode>"
3556 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
3557 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
3558 (match_operand:MVE_2 2 "s_register_operand" "w")
3559 (match_operand:HI 3 "vpr_register_operand" "Up")]
3563 "vpst\;vminvt.<supf>%#<V_sz_elem>\t%0, %q2"
3564 [(set_attr "type" "mve_move")
3565 (set_attr "length""8")])
3568 ;; [vmladavaq_u, vmladavaq_s])
3570 (define_insn "mve_vmladavaq_<supf><mode>"
3572 (set (match_operand:SI 0 "s_register_operand" "=Te")
3573 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
3574 (match_operand:MVE_2 2 "s_register_operand" "w")
3575 (match_operand:MVE_2 3 "s_register_operand" "w")]
3579 "vmladava.<supf>%#<V_sz_elem> %0, %q2, %q3"
3580 [(set_attr "type" "mve_move")
3584 ;; [vmladavq_p_u, vmladavq_p_s])
3586 (define_insn "mve_vmladavq_p_<supf><mode>"
3588 (set (match_operand:SI 0 "s_register_operand" "=Te")
3589 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
3590 (match_operand:MVE_2 2 "s_register_operand" "w")
3591 (match_operand:HI 3 "vpr_register_operand" "Up")]
3595 "vpst\;vmladavt.<supf>%#<V_sz_elem>\t%0, %q1, %q2"
3596 [(set_attr "type" "mve_move")
3597 (set_attr "length""8")])
3602 (define_insn "mve_vmladavxq_p_s<mode>"
3604 (set (match_operand:SI 0 "s_register_operand" "=Te")
3605 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
3606 (match_operand:MVE_2 2 "s_register_operand" "w")
3607 (match_operand:HI 3 "vpr_register_operand" "Up")]
3611 "vpst\;vmladavxt.s%#<V_sz_elem>\t%0, %q1, %q2"
3612 [(set_attr "type" "mve_move")
3613 (set_attr "length""8")])
3616 ;; [vmlaq_n_u, vmlaq_n_s])
3618 (define_insn "mve_vmlaq_n_<supf><mode>"
3620 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3621 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3622 (match_operand:MVE_2 2 "s_register_operand" "w")
3623 (match_operand:<V_elem> 3 "s_register_operand" "r")]
3627 "vmla.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
3628 [(set_attr "type" "mve_move")
3632 ;; [vmlasq_n_u, vmlasq_n_s])
3634 (define_insn "mve_vmlasq_n_<supf><mode>"
3636 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3637 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3638 (match_operand:MVE_2 2 "s_register_operand" "w")
3639 (match_operand:<V_elem> 3 "s_register_operand" "r")]
3643 "vmlas.<supf>%#<V_sz_elem> %q0, %q2, %3"
3644 [(set_attr "type" "mve_move")
3650 (define_insn "mve_vmlsdavq_p_s<mode>"
3652 (set (match_operand:SI 0 "s_register_operand" "=Te")
3653 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
3654 (match_operand:MVE_2 2 "s_register_operand" "w")
3655 (match_operand:HI 3 "vpr_register_operand" "Up")]
3659 "vpst\;vmlsdavt.s%#<V_sz_elem> %0, %q1, %q2"
3660 [(set_attr "type" "mve_move")
3661 (set_attr "length""8")])
3666 (define_insn "mve_vmlsdavxq_p_s<mode>"
3668 (set (match_operand:SI 0 "s_register_operand" "=Te")
3669 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
3670 (match_operand:MVE_2 2 "s_register_operand" "w")
3671 (match_operand:HI 3 "vpr_register_operand" "Up")]
3675 "vpst\;vmlsdavxt.s%#<V_sz_elem> %0, %q1, %q2"
3676 [(set_attr "type" "mve_move")
3677 (set_attr "length""8")])
3680 ;; [vmvnq_m_s, vmvnq_m_u])
3682 (define_insn "mve_vmvnq_m_<supf><mode>"
3684 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3685 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3686 (match_operand:MVE_2 2 "s_register_operand" "w")
3687 (match_operand:HI 3 "vpr_register_operand" "Up")]
3691 "vpst\;vmvnt %q0, %q2"
3692 [(set_attr "type" "mve_move")
3693 (set_attr "length""8")])
3698 (define_insn "mve_vnegq_m_s<mode>"
3700 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3701 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3702 (match_operand:MVE_2 2 "s_register_operand" "w")
3703 (match_operand:HI 3 "vpr_register_operand" "Up")]
3707 "vpst\;vnegt.s%#<V_sz_elem>\t%q0, %q2"
3708 [(set_attr "type" "mve_move")
3709 (set_attr "length""8")])
3712 ;; [vpselq_u, vpselq_s])
3714 (define_insn "mve_vpselq_<supf><mode>"
3716 (set (match_operand:MVE_1 0 "s_register_operand" "=w")
3717 (unspec:MVE_1 [(match_operand:MVE_1 1 "s_register_operand" "w")
3718 (match_operand:MVE_1 2 "s_register_operand" "w")
3719 (match_operand:HI 3 "vpr_register_operand" "Up")]
3723 "vpsel %q0, %q1, %q2"
3724 [(set_attr "type" "mve_move")
3730 (define_insn "mve_vqabsq_m_s<mode>"
3732 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3733 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3734 (match_operand:MVE_2 2 "s_register_operand" "w")
3735 (match_operand:HI 3 "vpr_register_operand" "Up")]
3739 "vpst\;vqabst.s%#<V_sz_elem>\t%q0, %q2"
3740 [(set_attr "type" "mve_move")
3741 (set_attr "length""8")])
3746 (define_insn "mve_vqdmlahq_n_<supf><mode>"
3748 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3749 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3750 (match_operand:MVE_2 2 "s_register_operand" "w")
3751 (match_operand:<V_elem> 3 "s_register_operand" "r")]
3755 "vqdmlah.s%#<V_sz_elem>\t%q0, %q2, %3"
3756 [(set_attr "type" "mve_move")
3762 (define_insn "mve_vqdmlashq_n_<supf><mode>"
3764 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3765 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3766 (match_operand:MVE_2 2 "s_register_operand" "w")
3767 (match_operand:<V_elem> 3 "s_register_operand" "r")]
3771 "vqdmlash.s%#<V_sz_elem>\t%q0, %q2, %3"
3772 [(set_attr "type" "mve_move")
3778 (define_insn "mve_vqnegq_m_s<mode>"
3780 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3781 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3782 (match_operand:MVE_2 2 "s_register_operand" "w")
3783 (match_operand:HI 3 "vpr_register_operand" "Up")]
3787 "vpst\;vqnegt.s%#<V_sz_elem> %q0, %q2"
3788 [(set_attr "type" "mve_move")
3789 (set_attr "length""8")])
3794 (define_insn "mve_vqrdmladhq_s<mode>"
3796 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3797 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3798 (match_operand:MVE_2 2 "s_register_operand" "w")
3799 (match_operand:MVE_2 3 "s_register_operand" "w")]
3803 "vqrdmladh.s%#<V_sz_elem>\t%q0, %q2, %q3"
3804 [(set_attr "type" "mve_move")
3810 (define_insn "mve_vqrdmladhxq_s<mode>"
3812 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3813 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3814 (match_operand:MVE_2 2 "s_register_operand" "w")
3815 (match_operand:MVE_2 3 "s_register_operand" "w")]
3819 "vqrdmladhx.s%#<V_sz_elem>\t%q0, %q2, %q3"
3820 [(set_attr "type" "mve_move")
3826 (define_insn "mve_vqrdmlahq_n_<supf><mode>"
3828 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3829 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3830 (match_operand:MVE_2 2 "s_register_operand" "w")
3831 (match_operand:<V_elem> 3 "s_register_operand" "r")]
3835 "vqrdmlah.s%#<V_sz_elem>\t%q0, %q2, %3"
3836 [(set_attr "type" "mve_move")
3840 ;; [vqrdmlashq_n_s])
3842 (define_insn "mve_vqrdmlashq_n_<supf><mode>"
3844 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3845 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3846 (match_operand:MVE_2 2 "s_register_operand" "w")
3847 (match_operand:<V_elem> 3 "s_register_operand" "r")]
3851 "vqrdmlash.s%#<V_sz_elem>\t%q0, %q2, %3"
3852 [(set_attr "type" "mve_move")
3858 (define_insn "mve_vqrdmlsdhq_s<mode>"
3860 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3861 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3862 (match_operand:MVE_2 2 "s_register_operand" "w")
3863 (match_operand:MVE_2 3 "s_register_operand" "w")]
3867 "vqrdmlsdh.s%#<V_sz_elem>\t%q0, %q2, %q3"
3868 [(set_attr "type" "mve_move")
3874 (define_insn "mve_vqrdmlsdhxq_s<mode>"
3876 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3877 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3878 (match_operand:MVE_2 2 "s_register_operand" "w")
3879 (match_operand:MVE_2 3 "s_register_operand" "w")]
3883 "vqrdmlsdhx.s%#<V_sz_elem>\t%q0, %q2, %q3"
3884 [(set_attr "type" "mve_move")
3888 ;; [vqrshlq_m_n_s, vqrshlq_m_n_u])
3890 (define_insn "mve_vqrshlq_m_n_<supf><mode>"
3892 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3893 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3894 (match_operand:SI 2 "s_register_operand" "r")
3895 (match_operand:HI 3 "vpr_register_operand" "Up")]
3899 "vpst\;vqrshlt.<supf>%#<V_sz_elem> %q0, %2"
3900 [(set_attr "type" "mve_move")
3901 (set_attr "length""8")])
3904 ;; [vqshlq_m_r_u, vqshlq_m_r_s])
3906 (define_insn "mve_vqshlq_m_r_<supf><mode>"
3908 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3909 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3910 (match_operand:SI 2 "s_register_operand" "r")
3911 (match_operand:HI 3 "vpr_register_operand" "Up")]
3915 "vpst\;vqshlt.<supf>%#<V_sz_elem>\t%q0, %2"
3916 [(set_attr "type" "mve_move")
3917 (set_attr "length""8")])
3920 ;; [vrev64q_m_u, vrev64q_m_s])
3922 (define_insn "mve_vrev64q_m_<supf><mode>"
3924 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3925 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3926 (match_operand:MVE_2 2 "s_register_operand" "w")
3927 (match_operand:HI 3 "vpr_register_operand" "Up")]
3931 "vpst\;vrev64t.%#<V_sz_elem>\t%q0, %q2"
3932 [(set_attr "type" "mve_move")
3933 (set_attr "length""8")])
3936 ;; [vrshlq_m_n_s, vrshlq_m_n_u])
3938 (define_insn "mve_vrshlq_m_n_<supf><mode>"
3940 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3941 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3942 (match_operand:SI 2 "s_register_operand" "r")
3943 (match_operand:HI 3 "vpr_register_operand" "Up")]
3947 "vpst\;vrshlt.<supf>%#<V_sz_elem>\t%q0, %2"
3948 [(set_attr "type" "mve_move")
3949 (set_attr "length""8")])
3952 ;; [vshlq_m_r_u, vshlq_m_r_s])
3954 (define_insn "mve_vshlq_m_r_<supf><mode>"
3956 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3957 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3958 (match_operand:SI 2 "s_register_operand" "r")
3959 (match_operand:HI 3 "vpr_register_operand" "Up")]
3963 "vpst\;vshlt.<supf>%#<V_sz_elem>\t%q0, %2"
3964 [(set_attr "type" "mve_move")
3965 (set_attr "length""8")])
3968 ;; [vsliq_n_u, vsliq_n_s])
3970 (define_insn "mve_vsliq_n_<supf><mode>"
3972 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3973 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3974 (match_operand:MVE_2 2 "s_register_operand" "w")
3975 (match_operand:SI 3 "<MVE_pred>" "<MVE_constraint>")]
3979 "vsli.%#<V_sz_elem>\t%q0, %q2, %3"
3980 [(set_attr "type" "mve_move")
3984 ;; [vsriq_n_u, vsriq_n_s])
3986 (define_insn "mve_vsriq_n_<supf><mode>"
3988 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3989 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3990 (match_operand:MVE_2 2 "s_register_operand" "w")
3991 (match_operand:SI 3 "mve_imm_selective_upto_8" "Rg")]
3995 "vsri.%#<V_sz_elem>\t%q0, %q2, %3"
3996 [(set_attr "type" "mve_move")
4002 (define_insn "mve_vqdmlsdhxq_s<mode>"
4004 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4005 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4006 (match_operand:MVE_2 2 "s_register_operand" "w")
4007 (match_operand:MVE_2 3 "s_register_operand" "w")]
4011 "vqdmlsdhx.s%#<V_sz_elem>\t%q0, %q2, %q3"
4012 [(set_attr "type" "mve_move")
4018 (define_insn "mve_vqdmlsdhq_s<mode>"
4020 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4021 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4022 (match_operand:MVE_2 2 "s_register_operand" "w")
4023 (match_operand:MVE_2 3 "s_register_operand" "w")]
4027 "vqdmlsdh.s%#<V_sz_elem>\t%q0, %q2, %q3"
4028 [(set_attr "type" "mve_move")
4034 (define_insn "mve_vqdmladhxq_s<mode>"
4036 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4037 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4038 (match_operand:MVE_2 2 "s_register_operand" "w")
4039 (match_operand:MVE_2 3 "s_register_operand" "w")]
4043 "vqdmladhx.s%#<V_sz_elem>\t%q0, %q2, %q3"
4044 [(set_attr "type" "mve_move")
4050 (define_insn "mve_vqdmladhq_s<mode>"
4052 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4053 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4054 (match_operand:MVE_2 2 "s_register_operand" "w")
4055 (match_operand:MVE_2 3 "s_register_operand" "w")]
4059 "vqdmladh.s%#<V_sz_elem>\t%q0, %q2, %q3"
4060 [(set_attr "type" "mve_move")
4066 (define_insn "mve_vmlsdavaxq_s<mode>"
4068 (set (match_operand:SI 0 "s_register_operand" "=Te")
4069 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
4070 (match_operand:MVE_2 2 "s_register_operand" "w")
4071 (match_operand:MVE_2 3 "s_register_operand" "w")]
4075 "vmlsdavax.s%#<V_sz_elem>\t%0, %q2, %q3"
4076 [(set_attr "type" "mve_move")
4082 (define_insn "mve_vmlsdavaq_s<mode>"
4084 (set (match_operand:SI 0 "s_register_operand" "=Te")
4085 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
4086 (match_operand:MVE_2 2 "s_register_operand" "w")
4087 (match_operand:MVE_2 3 "s_register_operand" "w")]
4091 "vmlsdava.s%#<V_sz_elem>\t%0, %q2, %q3"
4092 [(set_attr "type" "mve_move")
4098 (define_insn "mve_vmladavaxq_s<mode>"
4100 (set (match_operand:SI 0 "s_register_operand" "=Te")
4101 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
4102 (match_operand:MVE_2 2 "s_register_operand" "w")
4103 (match_operand:MVE_2 3 "s_register_operand" "w")]
4107 "vmladavax.s%#<V_sz_elem>\t%0, %q2, %q3"
4108 [(set_attr "type" "mve_move")
4113 (define_insn "mve_vabsq_m_f<mode>"
4115 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4116 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4117 (match_operand:MVE_0 2 "s_register_operand" "w")
4118 (match_operand:HI 3 "vpr_register_operand" "Up")]
4121 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4122 "vpst\;vabst.f%#<V_sz_elem> %q0, %q2"
4123 [(set_attr "type" "mve_move")
4124 (set_attr "length""8")])
4127 ;; [vaddlvaq_p_s vaddlvaq_p_u])
4129 (define_insn "mve_vaddlvaq_p_<supf>v4si"
4131 (set (match_operand:DI 0 "s_register_operand" "=r")
4132 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
4133 (match_operand:V4SI 2 "s_register_operand" "w")
4134 (match_operand:HI 3 "vpr_register_operand" "Up")]
4138 "vpst\;vaddlvat.<supf>32 %Q0, %R0, %q2"
4139 [(set_attr "type" "mve_move")
4140 (set_attr "length""8")])
4144 (define_insn "mve_vcmlaq_f<mode>"
4146 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4147 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4148 (match_operand:MVE_0 2 "s_register_operand" "w")
4149 (match_operand:MVE_0 3 "s_register_operand" "w")]
4152 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4153 "vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #0"
4154 [(set_attr "type" "mve_move")
4158 ;; [vcmlaq_rot180_f])
4160 (define_insn "mve_vcmlaq_rot180_f<mode>"
4162 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4163 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4164 (match_operand:MVE_0 2 "s_register_operand" "w")
4165 (match_operand:MVE_0 3 "s_register_operand" "w")]
4168 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4169 "vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #180"
4170 [(set_attr "type" "mve_move")
4174 ;; [vcmlaq_rot270_f])
4176 (define_insn "mve_vcmlaq_rot270_f<mode>"
4178 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4179 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4180 (match_operand:MVE_0 2 "s_register_operand" "w")
4181 (match_operand:MVE_0 3 "s_register_operand" "w")]
4184 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4185 "vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #270"
4186 [(set_attr "type" "mve_move")
4190 ;; [vcmlaq_rot90_f])
4192 (define_insn "mve_vcmlaq_rot90_f<mode>"
4194 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4195 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4196 (match_operand:MVE_0 2 "s_register_operand" "w")
4197 (match_operand:MVE_0 3 "s_register_operand" "w")]
4200 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4201 "vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #90"
4202 [(set_attr "type" "mve_move")
4208 (define_insn "mve_vcmpeqq_m_n_f<mode>"
4210 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4211 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4212 (match_operand:<V_elem> 2 "s_register_operand" "r")
4213 (match_operand:HI 3 "vpr_register_operand" "Up")]
4216 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4217 "vpst\;vcmpt.f%#<V_sz_elem> eq, %q1, %2"
4218 [(set_attr "type" "mve_move")
4219 (set_attr "length""8")])
4224 (define_insn "mve_vcmpgeq_m_f<mode>"
4226 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4227 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4228 (match_operand:MVE_0 2 "s_register_operand" "w")
4229 (match_operand:HI 3 "vpr_register_operand" "Up")]
4232 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4233 "vpst\;vcmpt.f%#<V_sz_elem> ge, %q1, %q2"
4234 [(set_attr "type" "mve_move")
4235 (set_attr "length""8")])
4240 (define_insn "mve_vcmpgeq_m_n_f<mode>"
4242 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4243 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4244 (match_operand:<V_elem> 2 "s_register_operand" "r")
4245 (match_operand:HI 3 "vpr_register_operand" "Up")]
4248 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4249 "vpst\;vcmpt.f%#<V_sz_elem> ge, %q1, %2"
4250 [(set_attr "type" "mve_move")
4251 (set_attr "length""8")])
4256 (define_insn "mve_vcmpgtq_m_f<mode>"
4258 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4259 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4260 (match_operand:MVE_0 2 "s_register_operand" "w")
4261 (match_operand:HI 3 "vpr_register_operand" "Up")]
4264 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4265 "vpst\;vcmpt.f%#<V_sz_elem> gt, %q1, %q2"
4266 [(set_attr "type" "mve_move")
4267 (set_attr "length""8")])
4272 (define_insn "mve_vcmpgtq_m_n_f<mode>"
4274 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4275 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4276 (match_operand:<V_elem> 2 "s_register_operand" "r")
4277 (match_operand:HI 3 "vpr_register_operand" "Up")]
4280 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4281 "vpst\;vcmpt.f%#<V_sz_elem> gt, %q1, %2"
4282 [(set_attr "type" "mve_move")
4283 (set_attr "length""8")])
4288 (define_insn "mve_vcmpleq_m_f<mode>"
4290 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4291 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4292 (match_operand:MVE_0 2 "s_register_operand" "w")
4293 (match_operand:HI 3 "vpr_register_operand" "Up")]
4296 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4297 "vpst\;vcmpt.f%#<V_sz_elem> le, %q1, %q2"
4298 [(set_attr "type" "mve_move")
4299 (set_attr "length""8")])
4304 (define_insn "mve_vcmpleq_m_n_f<mode>"
4306 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4307 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4308 (match_operand:<V_elem> 2 "s_register_operand" "r")
4309 (match_operand:HI 3 "vpr_register_operand" "Up")]
4312 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4313 "vpst\;vcmpt.f%#<V_sz_elem> le, %q1, %2"
4314 [(set_attr "type" "mve_move")
4315 (set_attr "length""8")])
4320 (define_insn "mve_vcmpltq_m_f<mode>"
4322 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4323 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4324 (match_operand:MVE_0 2 "s_register_operand" "w")
4325 (match_operand:HI 3 "vpr_register_operand" "Up")]
4328 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4329 "vpst\;vcmpt.f%#<V_sz_elem> lt, %q1, %q2"
4330 [(set_attr "type" "mve_move")
4331 (set_attr "length""8")])
4336 (define_insn "mve_vcmpltq_m_n_f<mode>"
4338 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4339 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4340 (match_operand:<V_elem> 2 "s_register_operand" "r")
4341 (match_operand:HI 3 "vpr_register_operand" "Up")]
4344 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4345 "vpst\;vcmpt.f%#<V_sz_elem> lt, %q1, %2"
4346 [(set_attr "type" "mve_move")
4347 (set_attr "length""8")])
4352 (define_insn "mve_vcmpneq_m_f<mode>"
4354 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4355 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4356 (match_operand:MVE_0 2 "s_register_operand" "w")
4357 (match_operand:HI 3 "vpr_register_operand" "Up")]
4360 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4361 "vpst\;vcmpt.f%#<V_sz_elem> ne, %q1, %q2"
4362 [(set_attr "type" "mve_move")
4363 (set_attr "length""8")])
4368 (define_insn "mve_vcmpneq_m_n_f<mode>"
4370 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4371 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4372 (match_operand:<V_elem> 2 "s_register_operand" "r")
4373 (match_operand:HI 3 "vpr_register_operand" "Up")]
4376 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4377 "vpst\;vcmpt.f%#<V_sz_elem> ne, %q1, %2"
4378 [(set_attr "type" "mve_move")
4379 (set_attr "length""8")])
4382 ;; [vcvtbq_m_f16_f32])
4384 (define_insn "mve_vcvtbq_m_f16_f32v8hf"
4386 (set (match_operand:V8HF 0 "s_register_operand" "=w")
4387 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
4388 (match_operand:V4SF 2 "s_register_operand" "w")
4389 (match_operand:HI 3 "vpr_register_operand" "Up")]
4392 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4393 "vpst\;vcvtbt.f16.f32 %q0, %q2"
4394 [(set_attr "type" "mve_move")
4395 (set_attr "length""8")])
4398 ;; [vcvtbq_m_f32_f16])
4400 (define_insn "mve_vcvtbq_m_f32_f16v4sf"
4402 (set (match_operand:V4SF 0 "s_register_operand" "=w")
4403 (unspec:V4SF [(match_operand:V4SF 1 "s_register_operand" "0")
4404 (match_operand:V8HF 2 "s_register_operand" "w")
4405 (match_operand:HI 3 "vpr_register_operand" "Up")]
4408 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4409 "vpst\;vcvtbt.f32.f16 %q0, %q2"
4410 [(set_attr "type" "mve_move")
4411 (set_attr "length""8")])
4414 ;; [vcvttq_m_f16_f32])
4416 (define_insn "mve_vcvttq_m_f16_f32v8hf"
4418 (set (match_operand:V8HF 0 "s_register_operand" "=w")
4419 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
4420 (match_operand:V4SF 2 "s_register_operand" "w")
4421 (match_operand:HI 3 "vpr_register_operand" "Up")]
4424 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4425 "vpst\;vcvttt.f16.f32 %q0, %q2"
4426 [(set_attr "type" "mve_move")
4427 (set_attr "length""8")])
4430 ;; [vcvttq_m_f32_f16])
4432 (define_insn "mve_vcvttq_m_f32_f16v4sf"
4434 (set (match_operand:V4SF 0 "s_register_operand" "=w")
4435 (unspec:V4SF [(match_operand:V4SF 1 "s_register_operand" "0")
4436 (match_operand:V8HF 2 "s_register_operand" "w")
4437 (match_operand:HI 3 "vpr_register_operand" "Up")]
4440 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4441 "vpst\;vcvttt.f32.f16 %q0, %q2"
4442 [(set_attr "type" "mve_move")
4443 (set_attr "length""8")])
4448 (define_insn "mve_vdupq_m_n_f<mode>"
4450 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4451 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4452 (match_operand:<V_elem> 2 "s_register_operand" "r")
4453 (match_operand:HI 3 "vpr_register_operand" "Up")]
4456 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4457 "vpst\;vdupt.%#<V_sz_elem> %q0, %2"
4458 [(set_attr "type" "mve_move")
4459 (set_attr "length""8")])
4464 (define_insn "mve_vfmaq_f<mode>"
4466 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4467 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4468 (match_operand:MVE_0 2 "s_register_operand" "w")
4469 (match_operand:MVE_0 3 "s_register_operand" "w")]
4472 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4473 "vfma.f%#<V_sz_elem> %q0, %q2, %q3"
4474 [(set_attr "type" "mve_move")
4480 (define_insn "mve_vfmaq_n_f<mode>"
4482 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4483 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4484 (match_operand:MVE_0 2 "s_register_operand" "w")
4485 (match_operand:<V_elem> 3 "s_register_operand" "r")]
4488 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4489 "vfma.f%#<V_sz_elem> %q0, %q2, %3"
4490 [(set_attr "type" "mve_move")
4496 (define_insn "mve_vfmasq_n_f<mode>"
4498 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4499 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4500 (match_operand:MVE_0 2 "s_register_operand" "w")
4501 (match_operand:<V_elem> 3 "s_register_operand" "r")]
4504 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4505 "vfmas.f%#<V_sz_elem> %q0, %q2, %3"
4506 [(set_attr "type" "mve_move")
4511 (define_insn "mve_vfmsq_f<mode>"
4513 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4514 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4515 (match_operand:MVE_0 2 "s_register_operand" "w")
4516 (match_operand:MVE_0 3 "s_register_operand" "w")]
4519 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4520 "vfms.f%#<V_sz_elem> %q0, %q2, %q3"
4521 [(set_attr "type" "mve_move")
4527 (define_insn "mve_vmaxnmaq_m_f<mode>"
4529 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4530 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4531 (match_operand:MVE_0 2 "s_register_operand" "w")
4532 (match_operand:HI 3 "vpr_register_operand" "Up")]
4535 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4536 "vpst\;vmaxnmat.f%#<V_sz_elem> %q0, %q2"
4537 [(set_attr "type" "mve_move")
4538 (set_attr "length""8")])
4542 (define_insn "mve_vmaxnmavq_p_f<mode>"
4544 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
4545 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
4546 (match_operand:MVE_0 2 "s_register_operand" "w")
4547 (match_operand:HI 3 "vpr_register_operand" "Up")]
4550 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4551 "vpst\;vmaxnmavt.f%#<V_sz_elem> %0, %q2"
4552 [(set_attr "type" "mve_move")
4553 (set_attr "length""8")])
4558 (define_insn "mve_vmaxnmvq_p_f<mode>"
4560 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
4561 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
4562 (match_operand:MVE_0 2 "s_register_operand" "w")
4563 (match_operand:HI 3 "vpr_register_operand" "Up")]
4566 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4567 "vpst\;vmaxnmvt.f%#<V_sz_elem> %0, %q2"
4568 [(set_attr "type" "mve_move")
4569 (set_attr "length""8")])
4573 (define_insn "mve_vminnmaq_m_f<mode>"
4575 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4576 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4577 (match_operand:MVE_0 2 "s_register_operand" "w")
4578 (match_operand:HI 3 "vpr_register_operand" "Up")]
4581 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4582 "vpst\;vminnmat.f%#<V_sz_elem> %q0, %q2"
4583 [(set_attr "type" "mve_move")
4584 (set_attr "length""8")])
4589 (define_insn "mve_vminnmavq_p_f<mode>"
4591 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
4592 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
4593 (match_operand:MVE_0 2 "s_register_operand" "w")
4594 (match_operand:HI 3 "vpr_register_operand" "Up")]
4597 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4598 "vpst\;vminnmavt.f%#<V_sz_elem> %0, %q2"
4599 [(set_attr "type" "mve_move")
4600 (set_attr "length""8")])
4604 (define_insn "mve_vminnmvq_p_f<mode>"
4606 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
4607 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
4608 (match_operand:MVE_0 2 "s_register_operand" "w")
4609 (match_operand:HI 3 "vpr_register_operand" "Up")]
4612 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4613 "vpst\;vminnmvt.f%#<V_sz_elem> %0, %q2"
4614 [(set_attr "type" "mve_move")
4615 (set_attr "length""8")])
4618 ;; [vmlaldavaq_s, vmlaldavaq_u])
4620 (define_insn "mve_vmlaldavaq_<supf><mode>"
4622 (set (match_operand:DI 0 "s_register_operand" "=r")
4623 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
4624 (match_operand:MVE_5 2 "s_register_operand" "w")
4625 (match_operand:MVE_5 3 "s_register_operand" "w")]
4629 "vmlaldava.<supf>%#<V_sz_elem> %Q0, %R0, %q2, %q3"
4630 [(set_attr "type" "mve_move")
4636 (define_insn "mve_vmlaldavaxq_s<mode>"
4638 (set (match_operand:DI 0 "s_register_operand" "=r")
4639 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
4640 (match_operand:MVE_5 2 "s_register_operand" "w")
4641 (match_operand:MVE_5 3 "s_register_operand" "w")]
4645 "vmlaldavax.s%#<V_sz_elem> %Q0, %R0, %q2, %q3"
4646 [(set_attr "type" "mve_move")
4650 ;; [vmlaldavq_p_u, vmlaldavq_p_s])
4652 (define_insn "mve_vmlaldavq_p_<supf><mode>"
4654 (set (match_operand:DI 0 "s_register_operand" "=r")
4655 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
4656 (match_operand:MVE_5 2 "s_register_operand" "w")
4657 (match_operand:HI 3 "vpr_register_operand" "Up")]
4661 "vpst\;vmlaldavt.<supf>%#<V_sz_elem> %Q0, %R0, %q1, %q2"
4662 [(set_attr "type" "mve_move")
4663 (set_attr "length""8")])
4666 ;; [vmlaldavxq_p_s])
4668 (define_insn "mve_vmlaldavxq_p_s<mode>"
4670 (set (match_operand:DI 0 "s_register_operand" "=r")
4671 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
4672 (match_operand:MVE_5 2 "s_register_operand" "w")
4673 (match_operand:HI 3 "vpr_register_operand" "Up")]
4677 "vpst\;vmlaldavxt.s%#<V_sz_elem>\t%Q0, %R0, %q1, %q2"
4678 [(set_attr "type" "mve_move")
4679 (set_attr "length""8")])
4683 (define_insn "mve_vmlsldavaq_s<mode>"
4685 (set (match_operand:DI 0 "s_register_operand" "=r")
4686 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
4687 (match_operand:MVE_5 2 "s_register_operand" "w")
4688 (match_operand:MVE_5 3 "s_register_operand" "w")]
4692 "vmlsldava.s%#<V_sz_elem> %Q0, %R0, %q2, %q3"
4693 [(set_attr "type" "mve_move")
4699 (define_insn "mve_vmlsldavaxq_s<mode>"
4701 (set (match_operand:DI 0 "s_register_operand" "=r")
4702 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
4703 (match_operand:MVE_5 2 "s_register_operand" "w")
4704 (match_operand:MVE_5 3 "s_register_operand" "w")]
4708 "vmlsldavax.s%#<V_sz_elem> %Q0, %R0, %q2, %q3"
4709 [(set_attr "type" "mve_move")
4715 (define_insn "mve_vmlsldavq_p_s<mode>"
4717 (set (match_operand:DI 0 "s_register_operand" "=r")
4718 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
4719 (match_operand:MVE_5 2 "s_register_operand" "w")
4720 (match_operand:HI 3 "vpr_register_operand" "Up")]
4724 "vpst\;vmlsldavt.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
4725 [(set_attr "type" "mve_move")
4726 (set_attr "length""8")])
4729 ;; [vmlsldavxq_p_s])
4731 (define_insn "mve_vmlsldavxq_p_s<mode>"
4733 (set (match_operand:DI 0 "s_register_operand" "=r")
4734 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
4735 (match_operand:MVE_5 2 "s_register_operand" "w")
4736 (match_operand:HI 3 "vpr_register_operand" "Up")]
4740 "vpst\;vmlsldavxt.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
4741 [(set_attr "type" "mve_move")
4742 (set_attr "length""8")])
4744 ;; [vmovlbq_m_u, vmovlbq_m_s])
4746 (define_insn "mve_vmovlbq_m_<supf><mode>"
4748 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
4749 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
4750 (match_operand:MVE_3 2 "s_register_operand" "w")
4751 (match_operand:HI 3 "vpr_register_operand" "Up")]
4755 "vpst\;vmovlbt.<supf>%#<V_sz_elem> %q0, %q2"
4756 [(set_attr "type" "mve_move")
4757 (set_attr "length""8")])
4759 ;; [vmovltq_m_u, vmovltq_m_s])
4761 (define_insn "mve_vmovltq_m_<supf><mode>"
4763 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
4764 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
4765 (match_operand:MVE_3 2 "s_register_operand" "w")
4766 (match_operand:HI 3 "vpr_register_operand" "Up")]
4770 "vpst\;vmovltt.<supf>%#<V_sz_elem> %q0, %q2"
4771 [(set_attr "type" "mve_move")
4772 (set_attr "length""8")])
4774 ;; [vmovnbq_m_u, vmovnbq_m_s])
4776 (define_insn "mve_vmovnbq_m_<supf><mode>"
4778 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
4779 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
4780 (match_operand:MVE_5 2 "s_register_operand" "w")
4781 (match_operand:HI 3 "vpr_register_operand" "Up")]
4785 "vpst\;vmovnbt.i%#<V_sz_elem> %q0, %q2"
4786 [(set_attr "type" "mve_move")
4787 (set_attr "length""8")])
4790 ;; [vmovntq_m_u, vmovntq_m_s])
4792 (define_insn "mve_vmovntq_m_<supf><mode>"
4794 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
4795 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
4796 (match_operand:MVE_5 2 "s_register_operand" "w")
4797 (match_operand:HI 3 "vpr_register_operand" "Up")]
4801 "vpst\;vmovntt.i%#<V_sz_elem> %q0, %q2"
4802 [(set_attr "type" "mve_move")
4803 (set_attr "length""8")])
4806 ;; [vmvnq_m_n_u, vmvnq_m_n_s])
4808 (define_insn "mve_vmvnq_m_n_<supf><mode>"
4810 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
4811 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
4812 (match_operand:SI 2 "immediate_operand" "i")
4813 (match_operand:HI 3 "vpr_register_operand" "Up")]
4817 "vpst\;vmvnt.i%#<V_sz_elem> %q0, %2"
4818 [(set_attr "type" "mve_move")
4819 (set_attr "length""8")])
4823 (define_insn "mve_vnegq_m_f<mode>"
4825 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4826 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4827 (match_operand:MVE_0 2 "s_register_operand" "w")
4828 (match_operand:HI 3 "vpr_register_operand" "Up")]
4831 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4832 "vpst\;vnegt.f%#<V_sz_elem> %q0, %q2"
4833 [(set_attr "type" "mve_move")
4834 (set_attr "length""8")])
4837 ;; [vorrq_m_n_s, vorrq_m_n_u])
4839 (define_insn "mve_vorrq_m_n_<supf><mode>"
4841 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
4842 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
4843 (match_operand:SI 2 "immediate_operand" "i")
4844 (match_operand:HI 3 "vpr_register_operand" "Up")]
4848 "vpst\;vorrt.i%#<V_sz_elem> %q0, %2"
4849 [(set_attr "type" "mve_move")
4850 (set_attr "length""8")])
4854 (define_insn "mve_vpselq_f<mode>"
4856 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4857 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
4858 (match_operand:MVE_0 2 "s_register_operand" "w")
4859 (match_operand:HI 3 "vpr_register_operand" "Up")]
4862 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4863 "vpsel %q0, %q1, %q2"
4864 [(set_attr "type" "mve_move")
4868 ;; [vqmovnbq_m_s, vqmovnbq_m_u])
4870 (define_insn "mve_vqmovnbq_m_<supf><mode>"
4872 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
4873 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
4874 (match_operand:MVE_5 2 "s_register_operand" "w")
4875 (match_operand:HI 3 "vpr_register_operand" "Up")]
4879 "vpst\;vqmovnbt.<supf>%#<V_sz_elem> %q0, %q2"
4880 [(set_attr "type" "mve_move")
4881 (set_attr "length""8")])
4884 ;; [vqmovntq_m_u, vqmovntq_m_s])
4886 (define_insn "mve_vqmovntq_m_<supf><mode>"
4888 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
4889 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
4890 (match_operand:MVE_5 2 "s_register_operand" "w")
4891 (match_operand:HI 3 "vpr_register_operand" "Up")]
4895 "vpst\;vqmovntt.<supf>%#<V_sz_elem> %q0, %q2"
4896 [(set_attr "type" "mve_move")
4897 (set_attr "length""8")])
4902 (define_insn "mve_vqmovunbq_m_s<mode>"
4904 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
4905 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
4906 (match_operand:MVE_5 2 "s_register_operand" "w")
4907 (match_operand:HI 3 "vpr_register_operand" "Up")]
4911 "vpst\;vqmovunbt.s%#<V_sz_elem> %q0, %q2"
4912 [(set_attr "type" "mve_move")
4913 (set_attr "length""8")])
4918 (define_insn "mve_vqmovuntq_m_s<mode>"
4920 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
4921 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
4922 (match_operand:MVE_5 2 "s_register_operand" "w")
4923 (match_operand:HI 3 "vpr_register_operand" "Up")]
4927 "vpst\;vqmovuntt.s%#<V_sz_elem> %q0, %q2"
4928 [(set_attr "type" "mve_move")
4929 (set_attr "length""8")])
4932 ;; [vqrshrntq_n_u, vqrshrntq_n_s])
4934 (define_insn "mve_vqrshrntq_n_<supf><mode>"
4936 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
4937 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
4938 (match_operand:MVE_5 2 "s_register_operand" "w")
4939 (match_operand:SI 3 "mve_imm_8" "Rb")]
4943 "vqrshrnt.<supf>%#<V_sz_elem> %q0, %q2, %3"
4944 [(set_attr "type" "mve_move")
4948 ;; [vqrshruntq_n_s])
4950 (define_insn "mve_vqrshruntq_n_s<mode>"
4952 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
4953 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
4954 (match_operand:MVE_5 2 "s_register_operand" "w")
4955 (match_operand:SI 3 "mve_imm_8" "Rb")]
4959 "vqrshrunt.s%#<V_sz_elem> %q0, %q2, %3"
4960 [(set_attr "type" "mve_move")
4964 ;; [vqshrnbq_n_u, vqshrnbq_n_s])
4966 (define_insn "mve_vqshrnbq_n_<supf><mode>"
4968 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
4969 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
4970 (match_operand:MVE_5 2 "s_register_operand" "w")
4971 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")]
4975 "vqshrnb.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
4976 [(set_attr "type" "mve_move")
4980 ;; [vqshrntq_n_u, vqshrntq_n_s])
4982 (define_insn "mve_vqshrntq_n_<supf><mode>"
4984 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
4985 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
4986 (match_operand:MVE_5 2 "s_register_operand" "w")
4987 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")]
4991 "vqshrnt.<supf>%#<V_sz_elem> %q0, %q2, %3"
4992 [(set_attr "type" "mve_move")
4998 (define_insn "mve_vqshrunbq_n_s<mode>"
5000 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5001 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5002 (match_operand:MVE_5 2 "s_register_operand" "w")
5003 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")]
5007 "vqshrunb.s%#<V_sz_elem> %q0, %q2, %3"
5008 [(set_attr "type" "mve_move")
5014 (define_insn "mve_vqshruntq_n_s<mode>"
5016 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5017 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5018 (match_operand:MVE_5 2 "s_register_operand" "w")
5019 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")]
5023 "vqshrunt.s%#<V_sz_elem> %q0, %q2, %3"
5024 [(set_attr "type" "mve_move")
5030 (define_insn "mve_vrev32q_m_fv8hf"
5032 (set (match_operand:V8HF 0 "s_register_operand" "=w")
5033 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
5034 (match_operand:V8HF 2 "s_register_operand" "w")
5035 (match_operand:HI 3 "vpr_register_operand" "Up")]
5038 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5039 "vpst\;vrev32t.16 %q0, %q2"
5040 [(set_attr "type" "mve_move")
5041 (set_attr "length""8")])
5044 ;; [vrev32q_m_s, vrev32q_m_u])
5046 (define_insn "mve_vrev32q_m_<supf><mode>"
5048 (set (match_operand:MVE_3 0 "s_register_operand" "=w")
5049 (unspec:MVE_3 [(match_operand:MVE_3 1 "s_register_operand" "0")
5050 (match_operand:MVE_3 2 "s_register_operand" "w")
5051 (match_operand:HI 3 "vpr_register_operand" "Up")]
5055 "vpst\;vrev32t.%#<V_sz_elem> %q0, %q2"
5056 [(set_attr "type" "mve_move")
5057 (set_attr "length""8")])
5062 (define_insn "mve_vrev64q_m_f<mode>"
5064 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5065 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5066 (match_operand:MVE_0 2 "s_register_operand" "w")
5067 (match_operand:HI 3 "vpr_register_operand" "Up")]
5070 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5071 "vpst\;vrev64t.%#<V_sz_elem> %q0, %q2"
5072 [(set_attr "type" "mve_move")
5073 (set_attr "length""8")])
5076 ;; [vrmlaldavhaxq_s])
5078 (define_insn "mve_vrmlaldavhaxq_sv4si"
5080 (set (match_operand:DI 0 "s_register_operand" "=r")
5081 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
5082 (match_operand:V4SI 2 "s_register_operand" "w")
5083 (match_operand:V4SI 3 "s_register_operand" "w")]
5087 "vrmlaldavhax.s32 %Q0, %R0, %q2, %q3"
5088 [(set_attr "type" "mve_move")
5092 ;; [vrmlaldavhxq_p_s])
5094 (define_insn "mve_vrmlaldavhxq_p_sv4si"
5096 (set (match_operand:DI 0 "s_register_operand" "=r")
5097 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
5098 (match_operand:V4SI 2 "s_register_operand" "w")
5099 (match_operand:HI 3 "vpr_register_operand" "Up")]
5103 "vpst\;vrmlaldavhxt.s32 %Q0, %R0, %q1, %q2"
5104 [(set_attr "type" "mve_move")
5105 (set_attr "length""8")])
5108 ;; [vrmlsldavhaxq_s])
5110 (define_insn "mve_vrmlsldavhaxq_sv4si"
5112 (set (match_operand:DI 0 "s_register_operand" "=r")
5113 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
5114 (match_operand:V4SI 2 "s_register_operand" "w")
5115 (match_operand:V4SI 3 "s_register_operand" "w")]
5119 "vrmlsldavhax.s32 %Q0, %R0, %q2, %q3"
5120 [(set_attr "type" "mve_move")
5124 ;; [vrmlsldavhq_p_s])
5126 (define_insn "mve_vrmlsldavhq_p_sv4si"
5128 (set (match_operand:DI 0 "s_register_operand" "=r")
5129 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
5130 (match_operand:V4SI 2 "s_register_operand" "w")
5131 (match_operand:HI 3 "vpr_register_operand" "Up")]
5135 "vpst\;vrmlsldavht.s32 %Q0, %R0, %q1, %q2"
5136 [(set_attr "type" "mve_move")
5137 (set_attr "length""8")])
5140 ;; [vrmlsldavhxq_p_s])
5142 (define_insn "mve_vrmlsldavhxq_p_sv4si"
5144 (set (match_operand:DI 0 "s_register_operand" "=r")
5145 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
5146 (match_operand:V4SI 2 "s_register_operand" "w")
5147 (match_operand:HI 3 "vpr_register_operand" "Up")]
5151 "vpst\;vrmlsldavhxt.s32 %Q0, %R0, %q1, %q2"
5152 [(set_attr "type" "mve_move")
5153 (set_attr "length""8")])
5158 (define_insn "mve_vrndaq_m_f<mode>"
5160 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5161 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5162 (match_operand:MVE_0 2 "s_register_operand" "w")
5163 (match_operand:HI 3 "vpr_register_operand" "Up")]
5166 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5167 "vpst\;vrintat.f%#<V_sz_elem> %q0, %q2"
5168 [(set_attr "type" "mve_move")
5169 (set_attr "length""8")])
5174 (define_insn "mve_vrndmq_m_f<mode>"
5176 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5177 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5178 (match_operand:MVE_0 2 "s_register_operand" "w")
5179 (match_operand:HI 3 "vpr_register_operand" "Up")]
5182 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5183 "vpst\;vrintmt.f%#<V_sz_elem> %q0, %q2"
5184 [(set_attr "type" "mve_move")
5185 (set_attr "length""8")])
5190 (define_insn "mve_vrndnq_m_f<mode>"
5192 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5193 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5194 (match_operand:MVE_0 2 "s_register_operand" "w")
5195 (match_operand:HI 3 "vpr_register_operand" "Up")]
5198 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5199 "vpst\;vrintnt.f%#<V_sz_elem> %q0, %q2"
5200 [(set_attr "type" "mve_move")
5201 (set_attr "length""8")])
5206 (define_insn "mve_vrndpq_m_f<mode>"
5208 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5209 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5210 (match_operand:MVE_0 2 "s_register_operand" "w")
5211 (match_operand:HI 3 "vpr_register_operand" "Up")]
5214 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5215 "vpst\;vrintpt.f%#<V_sz_elem> %q0, %q2"
5216 [(set_attr "type" "mve_move")
5217 (set_attr "length""8")])
5222 (define_insn "mve_vrndxq_m_f<mode>"
5224 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5225 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5226 (match_operand:MVE_0 2 "s_register_operand" "w")
5227 (match_operand:HI 3 "vpr_register_operand" "Up")]
5230 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5231 "vpst\;vrintxt.f%#<V_sz_elem> %q0, %q2"
5232 [(set_attr "type" "mve_move")
5233 (set_attr "length""8")])
5236 ;; [vrshrnbq_n_s, vrshrnbq_n_u])
5238 (define_insn "mve_vrshrnbq_n_<supf><mode>"
5240 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5241 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5242 (match_operand:MVE_5 2 "s_register_operand" "w")
5243 (match_operand:SI 3 "mve_imm_8" "Rb")]
5247 "vrshrnb.i%#<V_sz_elem> %q0, %q2, %3"
5248 [(set_attr "type" "mve_move")
5252 ;; [vrshrntq_n_u, vrshrntq_n_s])
5254 (define_insn "mve_vrshrntq_n_<supf><mode>"
5256 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5257 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5258 (match_operand:MVE_5 2 "s_register_operand" "w")
5259 (match_operand:SI 3 "mve_imm_8" "Rb")]
5263 "vrshrnt.i%#<V_sz_elem> %q0, %q2, %3"
5264 [(set_attr "type" "mve_move")
5268 ;; [vshrnbq_n_u, vshrnbq_n_s])
5270 (define_insn "mve_vshrnbq_n_<supf><mode>"
5272 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5273 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5274 (match_operand:MVE_5 2 "s_register_operand" "w")
5275 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")]
5279 "vshrnb.i%#<V_sz_elem> %q0, %q2, %3"
5280 [(set_attr "type" "mve_move")
5284 ;; [vshrntq_n_s, vshrntq_n_u])
5286 (define_insn "mve_vshrntq_n_<supf><mode>"
5288 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5289 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5290 (match_operand:MVE_5 2 "s_register_operand" "w")
5291 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")]
5295 "vshrnt.i%#<V_sz_elem>\t%q0, %q2, %3"
5296 [(set_attr "type" "mve_move")
5300 ;; [vcvtmq_m_s, vcvtmq_m_u])
5302 (define_insn "mve_vcvtmq_m_<supf><mode>"
5304 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5305 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5306 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
5307 (match_operand:HI 3 "vpr_register_operand" "Up")]
5310 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5311 "vpst\;vcvtmt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
5312 [(set_attr "type" "mve_move")
5313 (set_attr "length""8")])
5316 ;; [vcvtpq_m_u, vcvtpq_m_s])
5318 (define_insn "mve_vcvtpq_m_<supf><mode>"
5320 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5321 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5322 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
5323 (match_operand:HI 3 "vpr_register_operand" "Up")]
5326 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5327 "vpst\;vcvtpt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
5328 [(set_attr "type" "mve_move")
5329 (set_attr "length""8")])
5332 ;; [vcvtnq_m_s, vcvtnq_m_u])
5334 (define_insn "mve_vcvtnq_m_<supf><mode>"
5336 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5337 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5338 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
5339 (match_operand:HI 3 "vpr_register_operand" "Up")]
5342 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5343 "vpst\;vcvtnt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
5344 [(set_attr "type" "mve_move")
5345 (set_attr "length""8")])
5348 ;; [vcvtq_m_n_from_f_s, vcvtq_m_n_from_f_u])
5350 (define_insn "mve_vcvtq_m_n_from_f_<supf><mode>"
5352 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5353 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5354 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
5355 (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>")
5356 (match_operand:HI 4 "vpr_register_operand" "Up")]
5359 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5360 "vpst\;vcvtt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2, %3"
5361 [(set_attr "type" "mve_move")
5362 (set_attr "length""8")])
5365 ;; [vrev16q_m_u, vrev16q_m_s])
5367 (define_insn "mve_vrev16q_m_<supf>v16qi"
5369 (set (match_operand:V16QI 0 "s_register_operand" "=w")
5370 (unspec:V16QI [(match_operand:V16QI 1 "s_register_operand" "0")
5371 (match_operand:V16QI 2 "s_register_operand" "w")
5372 (match_operand:HI 3 "vpr_register_operand" "Up")]
5376 "vpst\;vrev16t.8 %q0, %q2"
5377 [(set_attr "type" "mve_move")
5378 (set_attr "length""8")])
5381 ;; [vcvtq_m_from_f_u, vcvtq_m_from_f_s])
5383 (define_insn "mve_vcvtq_m_from_f_<supf><mode>"
5385 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5386 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5387 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
5388 (match_operand:HI 3 "vpr_register_operand" "Up")]
5391 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5392 "vpst\;vcvtt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
5393 [(set_attr "type" "mve_move")
5394 (set_attr "length""8")])
5397 ;; [vrmlaldavhq_p_u vrmlaldavhq_p_s])
5399 (define_insn "mve_vrmlaldavhq_p_<supf>v4si"
5401 (set (match_operand:DI 0 "s_register_operand" "=r")
5402 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
5403 (match_operand:V4SI 2 "s_register_operand" "w")
5404 (match_operand:HI 3 "vpr_register_operand" "Up")]
5408 "vpst\;vrmlaldavht.<supf>32 %Q0, %R0, %q1, %q2"
5409 [(set_attr "type" "mve_move")
5410 (set_attr "length""8")])
5413 ;; [vrmlsldavhaq_s])
5415 (define_insn "mve_vrmlsldavhaq_sv4si"
5417 (set (match_operand:DI 0 "s_register_operand" "=r")
5418 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
5419 (match_operand:V4SI 2 "s_register_operand" "w")
5420 (match_operand:V4SI 3 "s_register_operand" "w")]
5424 "vrmlsldavha.s32 %Q0, %R0, %q2, %q3"
5425 [(set_attr "type" "mve_move")
5429 ;; [vabavq_p_s, vabavq_p_u])
5431 (define_insn "mve_vabavq_p_<supf><mode>"
5433 (set (match_operand:SI 0 "s_register_operand" "=r")
5434 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
5435 (match_operand:MVE_2 2 "s_register_operand" "w")
5436 (match_operand:MVE_2 3 "s_register_operand" "w")
5437 (match_operand:HI 4 "vpr_register_operand" "Up")]
5441 "vpst\;vabavt.<supf>%#<V_sz_elem>\t%0, %q2, %q3"
5442 [(set_attr "type" "mve_move")
5448 (define_insn "mve_vqshluq_m_n_s<mode>"
5450 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5451 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5452 (match_operand:MVE_2 2 "s_register_operand" "w")
5453 (match_operand:SI 3 "mve_imm_7" "Ra")
5454 (match_operand:HI 4 "vpr_register_operand" "Up")]
5458 "vpst\n\tvqshlut.s%#<V_sz_elem>\t%q0, %q2, %3"
5459 [(set_attr "type" "mve_move")])
5462 ;; [vshlq_m_s, vshlq_m_u])
5464 (define_insn "mve_vshlq_m_<supf><mode>"
5466 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5467 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5468 (match_operand:MVE_2 2 "s_register_operand" "w")
5469 (match_operand:MVE_2 3 "s_register_operand" "w")
5470 (match_operand:HI 4 "vpr_register_operand" "Up")]
5474 "vpst\;vshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
5475 [(set_attr "type" "mve_move")])
5478 ;; [vsriq_m_n_s, vsriq_m_n_u])
5480 (define_insn "mve_vsriq_m_n_<supf><mode>"
5482 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5483 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5484 (match_operand:MVE_2 2 "s_register_operand" "w")
5485 (match_operand:SI 3 "mve_imm_selective_upto_8" "Rg")
5486 (match_operand:HI 4 "vpr_register_operand" "Up")]
5490 "vpst\;vsrit.%#<V_sz_elem>\t%q0, %q2, %3"
5491 [(set_attr "type" "mve_move")])
5494 ;; [vsubq_m_u, vsubq_m_s])
5496 (define_insn "mve_vsubq_m_<supf><mode>"
5498 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5499 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5500 (match_operand:MVE_2 2 "s_register_operand" "w")
5501 (match_operand:MVE_2 3 "s_register_operand" "w")
5502 (match_operand:HI 4 "vpr_register_operand" "Up")]
5506 "vpst\;vsubt.i%#<V_sz_elem>\t%q0, %q2, %q3"
5507 [(set_attr "type" "mve_move")])
5510 ;; [vcvtq_m_n_to_f_u, vcvtq_m_n_to_f_s])
5512 (define_insn "mve_vcvtq_m_n_to_f_<supf><mode>"
5514 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5515 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5516 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
5517 (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>")
5518 (match_operand:HI 4 "vpr_register_operand" "Up")]
5521 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5522 "vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
5523 [(set_attr "type" "mve_move")
5524 (set_attr "length""8")])
5526 ;; [vabdq_m_s, vabdq_m_u])
5528 (define_insn "mve_vabdq_m_<supf><mode>"
5530 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5531 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5532 (match_operand:MVE_2 2 "s_register_operand" "w")
5533 (match_operand:MVE_2 3 "s_register_operand" "w")
5534 (match_operand:HI 4 "vpr_register_operand" "Up")]
5538 "vpst\;vabdt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
5539 [(set_attr "type" "mve_move")
5540 (set_attr "length""8")])
5543 ;; [vaddq_m_n_s, vaddq_m_n_u])
5545 (define_insn "mve_vaddq_m_n_<supf><mode>"
5547 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5548 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5549 (match_operand:MVE_2 2 "s_register_operand" "w")
5550 (match_operand:<V_elem> 3 "s_register_operand" "r")
5551 (match_operand:HI 4 "vpr_register_operand" "Up")]
5555 "vpst\;vaddt.i%#<V_sz_elem> %q0, %q2, %3"
5556 [(set_attr "type" "mve_move")
5557 (set_attr "length""8")])
5560 ;; [vaddq_m_u, vaddq_m_s])
5562 (define_insn "mve_vaddq_m_<supf><mode>"
5564 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5565 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5566 (match_operand:MVE_2 2 "s_register_operand" "w")
5567 (match_operand:MVE_2 3 "s_register_operand" "w")
5568 (match_operand:HI 4 "vpr_register_operand" "Up")]
5572 "vpst\;vaddt.i%#<V_sz_elem> %q0, %q2, %q3"
5573 [(set_attr "type" "mve_move")
5574 (set_attr "length""8")])
5577 ;; [vandq_m_u, vandq_m_s])
5579 (define_insn "mve_vandq_m_<supf><mode>"
5581 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5582 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5583 (match_operand:MVE_2 2 "s_register_operand" "w")
5584 (match_operand:MVE_2 3 "s_register_operand" "w")
5585 (match_operand:HI 4 "vpr_register_operand" "Up")]
5589 "vpst\;vandt %q0, %q2, %q3"
5590 [(set_attr "type" "mve_move")
5591 (set_attr "length""8")])
5594 ;; [vbicq_m_u, vbicq_m_s])
5596 (define_insn "mve_vbicq_m_<supf><mode>"
5598 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5599 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5600 (match_operand:MVE_2 2 "s_register_operand" "w")
5601 (match_operand:MVE_2 3 "s_register_operand" "w")
5602 (match_operand:HI 4 "vpr_register_operand" "Up")]
5606 "vpst\;vbict %q0, %q2, %q3"
5607 [(set_attr "type" "mve_move")
5608 (set_attr "length""8")])
5611 ;; [vbrsrq_m_n_u, vbrsrq_m_n_s])
5613 (define_insn "mve_vbrsrq_m_n_<supf><mode>"
5615 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5616 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5617 (match_operand:MVE_2 2 "s_register_operand" "w")
5618 (match_operand:SI 3 "s_register_operand" "r")
5619 (match_operand:HI 4 "vpr_register_operand" "Up")]
5623 "vpst\;vbrsrt.%#<V_sz_elem> %q0, %q2, %3"
5624 [(set_attr "type" "mve_move")
5625 (set_attr "length""8")])
5628 ;; [vcaddq_rot270_m_u, vcaddq_rot270_m_s])
5630 (define_insn "mve_vcaddq_rot270_m_<supf><mode>"
5632 (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
5633 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5634 (match_operand:MVE_2 2 "s_register_operand" "w")
5635 (match_operand:MVE_2 3 "s_register_operand" "w")
5636 (match_operand:HI 4 "vpr_register_operand" "Up")]
5640 "vpst\;vcaddt.i%#<V_sz_elem> %q0, %q2, %q3, #270"
5641 [(set_attr "type" "mve_move")
5642 (set_attr "length""8")])
5645 ;; [vcaddq_rot90_m_u, vcaddq_rot90_m_s])
5647 (define_insn "mve_vcaddq_rot90_m_<supf><mode>"
5649 (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
5650 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5651 (match_operand:MVE_2 2 "s_register_operand" "w")
5652 (match_operand:MVE_2 3 "s_register_operand" "w")
5653 (match_operand:HI 4 "vpr_register_operand" "Up")]
5657 "vpst\;vcaddt.i%#<V_sz_elem> %q0, %q2, %q3, #90"
5658 [(set_attr "type" "mve_move")
5659 (set_attr "length""8")])
5662 ;; [veorq_m_s, veorq_m_u])
5664 (define_insn "mve_veorq_m_<supf><mode>"
5666 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5667 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5668 (match_operand:MVE_2 2 "s_register_operand" "w")
5669 (match_operand:MVE_2 3 "s_register_operand" "w")
5670 (match_operand:HI 4 "vpr_register_operand" "Up")]
5674 "vpst\;veort %q0, %q2, %q3"
5675 [(set_attr "type" "mve_move")
5676 (set_attr "length""8")])
5679 ;; [vhaddq_m_n_s, vhaddq_m_n_u])
5681 (define_insn "mve_vhaddq_m_n_<supf><mode>"
5683 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5684 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5685 (match_operand:MVE_2 2 "s_register_operand" "w")
5686 (match_operand:<V_elem> 3 "s_register_operand" "r")
5687 (match_operand:HI 4 "vpr_register_operand" "Up")]
5691 "vpst\;vhaddt.<supf>%#<V_sz_elem> %q0, %q2, %3"
5692 [(set_attr "type" "mve_move")
5693 (set_attr "length""8")])
5696 ;; [vhaddq_m_s, vhaddq_m_u])
5698 (define_insn "mve_vhaddq_m_<supf><mode>"
5700 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5701 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5702 (match_operand:MVE_2 2 "s_register_operand" "w")
5703 (match_operand:MVE_2 3 "s_register_operand" "w")
5704 (match_operand:HI 4 "vpr_register_operand" "Up")]
5708 "vpst\;vhaddt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
5709 [(set_attr "type" "mve_move")
5710 (set_attr "length""8")])
5713 ;; [vhsubq_m_n_s, vhsubq_m_n_u])
5715 (define_insn "mve_vhsubq_m_n_<supf><mode>"
5717 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5718 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5719 (match_operand:MVE_2 2 "s_register_operand" "w")
5720 (match_operand:<V_elem> 3 "s_register_operand" "r")
5721 (match_operand:HI 4 "vpr_register_operand" "Up")]
5725 "vpst\;vhsubt.<supf>%#<V_sz_elem> %q0, %q2, %3"
5726 [(set_attr "type" "mve_move")
5727 (set_attr "length""8")])
5730 ;; [vhsubq_m_s, vhsubq_m_u])
5732 (define_insn "mve_vhsubq_m_<supf><mode>"
5734 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5735 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5736 (match_operand:MVE_2 2 "s_register_operand" "w")
5737 (match_operand:MVE_2 3 "s_register_operand" "w")
5738 (match_operand:HI 4 "vpr_register_operand" "Up")]
5742 "vpst\;vhsubt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
5743 [(set_attr "type" "mve_move")
5744 (set_attr "length""8")])
5747 ;; [vmaxq_m_s, vmaxq_m_u])
5749 (define_insn "mve_vmaxq_m_<supf><mode>"
5751 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5752 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5753 (match_operand:MVE_2 2 "s_register_operand" "w")
5754 (match_operand:MVE_2 3 "s_register_operand" "w")
5755 (match_operand:HI 4 "vpr_register_operand" "Up")]
5759 "vpst\;vmaxt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
5760 [(set_attr "type" "mve_move")
5761 (set_attr "length""8")])
5764 ;; [vminq_m_s, vminq_m_u])
5766 (define_insn "mve_vminq_m_<supf><mode>"
5768 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5769 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5770 (match_operand:MVE_2 2 "s_register_operand" "w")
5771 (match_operand:MVE_2 3 "s_register_operand" "w")
5772 (match_operand:HI 4 "vpr_register_operand" "Up")]
5776 "vpst\;vmint.<supf>%#<V_sz_elem> %q0, %q2, %q3"
5777 [(set_attr "type" "mve_move")
5778 (set_attr "length""8")])
5781 ;; [vmladavaq_p_u, vmladavaq_p_s])
5783 (define_insn "mve_vmladavaq_p_<supf><mode>"
5785 (set (match_operand:SI 0 "s_register_operand" "=Te")
5786 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
5787 (match_operand:MVE_2 2 "s_register_operand" "w")
5788 (match_operand:MVE_2 3 "s_register_operand" "w")
5789 (match_operand:HI 4 "vpr_register_operand" "Up")]
5793 "vpst\;vmladavat.<supf>%#<V_sz_elem> %0, %q2, %q3"
5794 [(set_attr "type" "mve_move")
5795 (set_attr "length""8")])
5798 ;; [vmlaq_m_n_s, vmlaq_m_n_u])
5800 (define_insn "mve_vmlaq_m_n_<supf><mode>"
5802 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5803 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5804 (match_operand:MVE_2 2 "s_register_operand" "w")
5805 (match_operand:<V_elem> 3 "s_register_operand" "r")
5806 (match_operand:HI 4 "vpr_register_operand" "Up")]
5810 "vpst\;vmlat.<supf>%#<V_sz_elem> %q0, %q2, %3"
5811 [(set_attr "type" "mve_move")
5812 (set_attr "length""8")])
5815 ;; [vmlasq_m_n_u, vmlasq_m_n_s])
5817 (define_insn "mve_vmlasq_m_n_<supf><mode>"
5819 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5820 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5821 (match_operand:MVE_2 2 "s_register_operand" "w")
5822 (match_operand:<V_elem> 3 "s_register_operand" "r")
5823 (match_operand:HI 4 "vpr_register_operand" "Up")]
5827 "vpst\;vmlast.<supf>%#<V_sz_elem> %q0, %q2, %3"
5828 [(set_attr "type" "mve_move")
5829 (set_attr "length""8")])
5832 ;; [vmulhq_m_s, vmulhq_m_u])
5834 (define_insn "mve_vmulhq_m_<supf><mode>"
5836 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5837 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5838 (match_operand:MVE_2 2 "s_register_operand" "w")
5839 (match_operand:MVE_2 3 "s_register_operand" "w")
5840 (match_operand:HI 4 "vpr_register_operand" "Up")]
5844 "vpst\;vmulht.<supf>%#<V_sz_elem> %q0, %q2, %q3"
5845 [(set_attr "type" "mve_move")
5846 (set_attr "length""8")])
5849 ;; [vmullbq_int_m_u, vmullbq_int_m_s])
5851 (define_insn "mve_vmullbq_int_m_<supf><mode>"
5853 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
5854 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
5855 (match_operand:MVE_2 2 "s_register_operand" "w")
5856 (match_operand:MVE_2 3 "s_register_operand" "w")
5857 (match_operand:HI 4 "vpr_register_operand" "Up")]
5861 "vpst\;vmullbt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
5862 [(set_attr "type" "mve_move")
5863 (set_attr "length""8")])
5866 ;; [vmulltq_int_m_s, vmulltq_int_m_u])
5868 (define_insn "mve_vmulltq_int_m_<supf><mode>"
5870 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
5871 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
5872 (match_operand:MVE_2 2 "s_register_operand" "w")
5873 (match_operand:MVE_2 3 "s_register_operand" "w")
5874 (match_operand:HI 4 "vpr_register_operand" "Up")]
5878 "vpst\;vmulltt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
5879 [(set_attr "type" "mve_move")
5880 (set_attr "length""8")])
5883 ;; [vmulq_m_n_u, vmulq_m_n_s])
5885 (define_insn "mve_vmulq_m_n_<supf><mode>"
5887 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5888 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5889 (match_operand:MVE_2 2 "s_register_operand" "w")
5890 (match_operand:<V_elem> 3 "s_register_operand" "r")
5891 (match_operand:HI 4 "vpr_register_operand" "Up")]
5895 "vpst\;vmult.i%#<V_sz_elem> %q0, %q2, %3"
5896 [(set_attr "type" "mve_move")
5897 (set_attr "length""8")])
5900 ;; [vmulq_m_s, vmulq_m_u])
5902 (define_insn "mve_vmulq_m_<supf><mode>"
5904 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5905 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5906 (match_operand:MVE_2 2 "s_register_operand" "w")
5907 (match_operand:MVE_2 3 "s_register_operand" "w")
5908 (match_operand:HI 4 "vpr_register_operand" "Up")]
5912 "vpst\;vmult.i%#<V_sz_elem> %q0, %q2, %q3"
5913 [(set_attr "type" "mve_move")
5914 (set_attr "length""8")])
5917 ;; [vornq_m_u, vornq_m_s])
5919 (define_insn "mve_vornq_m_<supf><mode>"
5921 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5922 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5923 (match_operand:MVE_2 2 "s_register_operand" "w")
5924 (match_operand:MVE_2 3 "s_register_operand" "w")
5925 (match_operand:HI 4 "vpr_register_operand" "Up")]
5929 "vpst\;vornt %q0, %q2, %q3"
5930 [(set_attr "type" "mve_move")
5931 (set_attr "length""8")])
5934 ;; [vorrq_m_s, vorrq_m_u])
5936 (define_insn "mve_vorrq_m_<supf><mode>"
5938 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5939 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5940 (match_operand:MVE_2 2 "s_register_operand" "w")
5941 (match_operand:MVE_2 3 "s_register_operand" "w")
5942 (match_operand:HI 4 "vpr_register_operand" "Up")]
5946 "vpst\;vorrt %q0, %q2, %q3"
5947 [(set_attr "type" "mve_move")
5948 (set_attr "length""8")])
5951 ;; [vqaddq_m_n_u, vqaddq_m_n_s])
5953 (define_insn "mve_vqaddq_m_n_<supf><mode>"
5955 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5956 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5957 (match_operand:MVE_2 2 "s_register_operand" "w")
5958 (match_operand:<V_elem> 3 "s_register_operand" "r")
5959 (match_operand:HI 4 "vpr_register_operand" "Up")]
5963 "vpst\;vqaddt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
5964 [(set_attr "type" "mve_move")
5965 (set_attr "length""8")])
5968 ;; [vqaddq_m_u, vqaddq_m_s])
5970 (define_insn "mve_vqaddq_m_<supf><mode>"
5972 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5973 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5974 (match_operand:MVE_2 2 "s_register_operand" "w")
5975 (match_operand:MVE_2 3 "s_register_operand" "w")
5976 (match_operand:HI 4 "vpr_register_operand" "Up")]
5980 "vpst\;vqaddt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
5981 [(set_attr "type" "mve_move")
5982 (set_attr "length""8")])
5985 ;; [vqdmlahq_m_n_s])
5987 (define_insn "mve_vqdmlahq_m_n_s<mode>"
5989 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5990 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5991 (match_operand:MVE_2 2 "s_register_operand" "w")
5992 (match_operand:<V_elem> 3 "s_register_operand" "r")
5993 (match_operand:HI 4 "vpr_register_operand" "Up")]
5997 "vpst\;vqdmlaht.s%#<V_sz_elem>\t%q0, %q2, %3"
5998 [(set_attr "type" "mve_move")
5999 (set_attr "length""8")])
6002 ;; [vqdmlashq_m_n_s])
6004 (define_insn "mve_vqdmlashq_m_n_s<mode>"
6006 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6007 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6008 (match_operand:MVE_2 2 "s_register_operand" "w")
6009 (match_operand:<V_elem> 3 "s_register_operand" "r")
6010 (match_operand:HI 4 "vpr_register_operand" "Up")]
6014 "vpst\;vqdmlasht.s%#<V_sz_elem>\t%q0, %q2, %3"
6015 [(set_attr "type" "mve_move")
6016 (set_attr "length""8")])
6019 ;; [vqrdmlahq_m_n_s])
6021 (define_insn "mve_vqrdmlahq_m_n_s<mode>"
6023 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6024 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6025 (match_operand:MVE_2 2 "s_register_operand" "w")
6026 (match_operand:<V_elem> 3 "s_register_operand" "r")
6027 (match_operand:HI 4 "vpr_register_operand" "Up")]
6031 "vpst\;vqrdmlaht.s%#<V_sz_elem>\t%q0, %q2, %3"
6032 [(set_attr "type" "mve_move")
6033 (set_attr "length""8")])
6036 ;; [vqrdmlashq_m_n_s])
6038 (define_insn "mve_vqrdmlashq_m_n_s<mode>"
6040 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6041 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6042 (match_operand:MVE_2 2 "s_register_operand" "w")
6043 (match_operand:<V_elem> 3 "s_register_operand" "r")
6044 (match_operand:HI 4 "vpr_register_operand" "Up")]
6048 "vpst\;vqrdmlasht.s%#<V_sz_elem>\t%q0, %q2, %3"
6049 [(set_attr "type" "mve_move")
6050 (set_attr "length""8")])
6053 ;; [vqrshlq_m_u, vqrshlq_m_s])
6055 (define_insn "mve_vqrshlq_m_<supf><mode>"
6057 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6058 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6059 (match_operand:MVE_2 2 "s_register_operand" "w")
6060 (match_operand:MVE_2 3 "s_register_operand" "w")
6061 (match_operand:HI 4 "vpr_register_operand" "Up")]
6065 "vpst\;vqrshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
6066 [(set_attr "type" "mve_move")
6067 (set_attr "length""8")])
6070 ;; [vqshlq_m_n_s, vqshlq_m_n_u])
6072 (define_insn "mve_vqshlq_m_n_<supf><mode>"
6074 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6075 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6076 (match_operand:MVE_2 2 "s_register_operand" "w")
6077 (match_operand:SI 3 "immediate_operand" "i")
6078 (match_operand:HI 4 "vpr_register_operand" "Up")]
6082 "vpst\;vqshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
6083 [(set_attr "type" "mve_move")
6084 (set_attr "length""8")])
6087 ;; [vqshlq_m_u, vqshlq_m_s])
6089 (define_insn "mve_vqshlq_m_<supf><mode>"
6091 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6092 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6093 (match_operand:MVE_2 2 "s_register_operand" "w")
6094 (match_operand:MVE_2 3 "s_register_operand" "w")
6095 (match_operand:HI 4 "vpr_register_operand" "Up")]
6099 "vpst\;vqshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
6100 [(set_attr "type" "mve_move")
6101 (set_attr "length""8")])
6104 ;; [vqsubq_m_n_u, vqsubq_m_n_s])
6106 (define_insn "mve_vqsubq_m_n_<supf><mode>"
6108 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6109 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6110 (match_operand:MVE_2 2 "s_register_operand" "w")
6111 (match_operand:<V_elem> 3 "s_register_operand" "r")
6112 (match_operand:HI 4 "vpr_register_operand" "Up")]
6116 "vpst\;vqsubt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
6117 [(set_attr "type" "mve_move")
6118 (set_attr "length""8")])
6121 ;; [vqsubq_m_u, vqsubq_m_s])
6123 (define_insn "mve_vqsubq_m_<supf><mode>"
6125 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6126 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6127 (match_operand:MVE_2 2 "s_register_operand" "w")
6128 (match_operand:MVE_2 3 "s_register_operand" "w")
6129 (match_operand:HI 4 "vpr_register_operand" "Up")]
6133 "vpst\;vqsubt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
6134 [(set_attr "type" "mve_move")
6135 (set_attr "length""8")])
6138 ;; [vrhaddq_m_u, vrhaddq_m_s])
6140 (define_insn "mve_vrhaddq_m_<supf><mode>"
6142 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6143 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6144 (match_operand:MVE_2 2 "s_register_operand" "w")
6145 (match_operand:MVE_2 3 "s_register_operand" "w")
6146 (match_operand:HI 4 "vpr_register_operand" "Up")]
6150 "vpst\;vrhaddt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
6151 [(set_attr "type" "mve_move")
6152 (set_attr "length""8")])
6155 ;; [vrmulhq_m_u, vrmulhq_m_s])
6157 (define_insn "mve_vrmulhq_m_<supf><mode>"
6159 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6160 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6161 (match_operand:MVE_2 2 "s_register_operand" "w")
6162 (match_operand:MVE_2 3 "s_register_operand" "w")
6163 (match_operand:HI 4 "vpr_register_operand" "Up")]
6167 "vpst\;vrmulht.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
6168 [(set_attr "type" "mve_move")
6169 (set_attr "length""8")])
6172 ;; [vrshlq_m_s, vrshlq_m_u])
6174 (define_insn "mve_vrshlq_m_<supf><mode>"
6176 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6177 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6178 (match_operand:MVE_2 2 "s_register_operand" "w")
6179 (match_operand:MVE_2 3 "s_register_operand" "w")
6180 (match_operand:HI 4 "vpr_register_operand" "Up")]
6184 "vpst\;vrshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
6185 [(set_attr "type" "mve_move")
6186 (set_attr "length""8")])
6189 ;; [vrshrq_m_n_s, vrshrq_m_n_u])
6191 (define_insn "mve_vrshrq_m_n_<supf><mode>"
6193 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6194 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6195 (match_operand:MVE_2 2 "s_register_operand" "w")
6196 (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>")
6197 (match_operand:HI 4 "vpr_register_operand" "Up")]
6201 "vpst\;vrshrt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
6202 [(set_attr "type" "mve_move")
6203 (set_attr "length""8")])
6206 ;; [vshlq_m_n_s, vshlq_m_n_u])
6208 (define_insn "mve_vshlq_m_n_<supf><mode>"
6210 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6211 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6212 (match_operand:MVE_2 2 "s_register_operand" "w")
6213 (match_operand:SI 3 "immediate_operand" "i")
6214 (match_operand:HI 4 "vpr_register_operand" "Up")]
6218 "vpst\;vshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
6219 [(set_attr "type" "mve_move")
6220 (set_attr "length""8")])
6223 ;; [vshrq_m_n_s, vshrq_m_n_u])
6225 (define_insn "mve_vshrq_m_n_<supf><mode>"
6227 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6228 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6229 (match_operand:MVE_2 2 "s_register_operand" "w")
6230 (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>")
6231 (match_operand:HI 4 "vpr_register_operand" "Up")]
6235 "vpst\;vshrt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
6236 [(set_attr "type" "mve_move")
6237 (set_attr "length""8")])
6240 ;; [vsliq_m_n_u, vsliq_m_n_s])
6242 (define_insn "mve_vsliq_m_n_<supf><mode>"
6244 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6245 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6246 (match_operand:MVE_2 2 "s_register_operand" "w")
6247 (match_operand:SI 3 "<MVE_pred>" "<MVE_constraint>")
6248 (match_operand:HI 4 "vpr_register_operand" "Up")]
6252 "vpst\;vslit.%#<V_sz_elem>\t%q0, %q2, %3"
6253 [(set_attr "type" "mve_move")
6254 (set_attr "length""8")])
6257 ;; [vsubq_m_n_s, vsubq_m_n_u])
6259 (define_insn "mve_vsubq_m_n_<supf><mode>"
6261 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6262 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6263 (match_operand:MVE_2 2 "s_register_operand" "w")
6264 (match_operand:<V_elem> 3 "s_register_operand" "r")
6265 (match_operand:HI 4 "vpr_register_operand" "Up")]
6269 "vpst\;vsubt.i%#<V_sz_elem>\t%q0, %q2, %3"
6270 [(set_attr "type" "mve_move")
6271 (set_attr "length""8")])
6274 ;; [vhcaddq_rot270_m_s])
6276 (define_insn "mve_vhcaddq_rot270_m_s<mode>"
6278 (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
6279 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6280 (match_operand:MVE_2 2 "s_register_operand" "w")
6281 (match_operand:MVE_2 3 "s_register_operand" "w")
6282 (match_operand:HI 4 "vpr_register_operand" "Up")]
6283 VHCADDQ_ROT270_M_S))
6286 "vpst\;vhcaddt.s%#<V_sz_elem>\t%q0, %q2, %q3, #270"
6287 [(set_attr "type" "mve_move")
6288 (set_attr "length""8")])
6291 ;; [vhcaddq_rot90_m_s])
6293 (define_insn "mve_vhcaddq_rot90_m_s<mode>"
6295 (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
6296 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6297 (match_operand:MVE_2 2 "s_register_operand" "w")
6298 (match_operand:MVE_2 3 "s_register_operand" "w")
6299 (match_operand:HI 4 "vpr_register_operand" "Up")]
6303 "vpst\;vhcaddt.s%#<V_sz_elem>\t%q0, %q2, %q3, #90"
6304 [(set_attr "type" "mve_move")
6305 (set_attr "length""8")])
6308 ;; [vmladavaxq_p_s])
6310 (define_insn "mve_vmladavaxq_p_s<mode>"
6312 (set (match_operand:SI 0 "s_register_operand" "=Te")
6313 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
6314 (match_operand:MVE_2 2 "s_register_operand" "w")
6315 (match_operand:MVE_2 3 "s_register_operand" "w")
6316 (match_operand:HI 4 "vpr_register_operand" "Up")]
6320 "vpst\;vmladavaxt.s%#<V_sz_elem>\t%0, %q2, %q3"
6321 [(set_attr "type" "mve_move")
6322 (set_attr "length""8")])
6327 (define_insn "mve_vmlsdavaq_p_s<mode>"
6329 (set (match_operand:SI 0 "s_register_operand" "=Te")
6330 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
6331 (match_operand:MVE_2 2 "s_register_operand" "w")
6332 (match_operand:MVE_2 3 "s_register_operand" "w")
6333 (match_operand:HI 4 "vpr_register_operand" "Up")]
6337 "vpst\;vmlsdavat.s%#<V_sz_elem>\t%0, %q2, %q3"
6338 [(set_attr "type" "mve_move")
6339 (set_attr "length""8")])
6342 ;; [vmlsdavaxq_p_s])
6344 (define_insn "mve_vmlsdavaxq_p_s<mode>"
6346 (set (match_operand:SI 0 "s_register_operand" "=Te")
6347 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
6348 (match_operand:MVE_2 2 "s_register_operand" "w")
6349 (match_operand:MVE_2 3 "s_register_operand" "w")
6350 (match_operand:HI 4 "vpr_register_operand" "Up")]
6354 "vpst\;vmlsdavaxt.s%#<V_sz_elem>\t%0, %q2, %q3"
6355 [(set_attr "type" "mve_move")
6356 (set_attr "length""8")])
6361 (define_insn "mve_vqdmladhq_m_s<mode>"
6363 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6364 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6365 (match_operand:MVE_2 2 "s_register_operand" "w")
6366 (match_operand:MVE_2 3 "s_register_operand" "w")
6367 (match_operand:HI 4 "vpr_register_operand" "Up")]
6371 "vpst\;vqdmladht.s%#<V_sz_elem>\t%q0, %q2, %q3"
6372 [(set_attr "type" "mve_move")
6373 (set_attr "length""8")])
6376 ;; [vqdmladhxq_m_s])
6378 (define_insn "mve_vqdmladhxq_m_s<mode>"
6380 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6381 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6382 (match_operand:MVE_2 2 "s_register_operand" "w")
6383 (match_operand:MVE_2 3 "s_register_operand" "w")
6384 (match_operand:HI 4 "vpr_register_operand" "Up")]
6388 "vpst\;vqdmladhxt.s%#<V_sz_elem>\t%q0, %q2, %q3"
6389 [(set_attr "type" "mve_move")
6390 (set_attr "length""8")])
6395 (define_insn "mve_vqdmlsdhq_m_s<mode>"
6397 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6398 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6399 (match_operand:MVE_2 2 "s_register_operand" "w")
6400 (match_operand:MVE_2 3 "s_register_operand" "w")
6401 (match_operand:HI 4 "vpr_register_operand" "Up")]
6405 "vpst\;vqdmlsdht.s%#<V_sz_elem>\t%q0, %q2, %q3"
6406 [(set_attr "type" "mve_move")
6407 (set_attr "length""8")])
6410 ;; [vqdmlsdhxq_m_s])
6412 (define_insn "mve_vqdmlsdhxq_m_s<mode>"
6414 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6415 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6416 (match_operand:MVE_2 2 "s_register_operand" "w")
6417 (match_operand:MVE_2 3 "s_register_operand" "w")
6418 (match_operand:HI 4 "vpr_register_operand" "Up")]
6422 "vpst\;vqdmlsdhxt.s%#<V_sz_elem>\t%q0, %q2, %q3"
6423 [(set_attr "type" "mve_move")
6424 (set_attr "length""8")])
6427 ;; [vqdmulhq_m_n_s])
6429 (define_insn "mve_vqdmulhq_m_n_s<mode>"
6431 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6432 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6433 (match_operand:MVE_2 2 "s_register_operand" "w")
6434 (match_operand:<V_elem> 3 "s_register_operand" "r")
6435 (match_operand:HI 4 "vpr_register_operand" "Up")]
6439 "vpst\;vqdmulht.s%#<V_sz_elem>\t%q0, %q2, %3"
6440 [(set_attr "type" "mve_move")
6441 (set_attr "length""8")])
6446 (define_insn "mve_vqdmulhq_m_s<mode>"
6448 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6449 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6450 (match_operand:MVE_2 2 "s_register_operand" "w")
6451 (match_operand:MVE_2 3 "s_register_operand" "w")
6452 (match_operand:HI 4 "vpr_register_operand" "Up")]
6456 "vpst\;vqdmulht.s%#<V_sz_elem>\t%q0, %q2, %q3"
6457 [(set_attr "type" "mve_move")
6458 (set_attr "length""8")])
6461 ;; [vqrdmladhq_m_s])
6463 (define_insn "mve_vqrdmladhq_m_s<mode>"
6465 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6466 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6467 (match_operand:MVE_2 2 "s_register_operand" "w")
6468 (match_operand:MVE_2 3 "s_register_operand" "w")
6469 (match_operand:HI 4 "vpr_register_operand" "Up")]
6473 "vpst\;vqrdmladht.s%#<V_sz_elem>\t%q0, %q2, %q3"
6474 [(set_attr "type" "mve_move")
6475 (set_attr "length""8")])
6478 ;; [vqrdmladhxq_m_s])
6480 (define_insn "mve_vqrdmladhxq_m_s<mode>"
6482 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6483 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6484 (match_operand:MVE_2 2 "s_register_operand" "w")
6485 (match_operand:MVE_2 3 "s_register_operand" "w")
6486 (match_operand:HI 4 "vpr_register_operand" "Up")]
6490 "vpst\;vqrdmladhxt.s%#<V_sz_elem>\t%q0, %q2, %q3"
6491 [(set_attr "type" "mve_move")
6492 (set_attr "length""8")])
6495 ;; [vqrdmlsdhq_m_s])
6497 (define_insn "mve_vqrdmlsdhq_m_s<mode>"
6499 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6500 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6501 (match_operand:MVE_2 2 "s_register_operand" "w")
6502 (match_operand:MVE_2 3 "s_register_operand" "w")
6503 (match_operand:HI 4 "vpr_register_operand" "Up")]
6507 "vpst\;vqrdmlsdht.s%#<V_sz_elem>\t%q0, %q2, %q3"
6508 [(set_attr "type" "mve_move")
6509 (set_attr "length""8")])
6512 ;; [vqrdmlsdhxq_m_s])
6514 (define_insn "mve_vqrdmlsdhxq_m_s<mode>"
6516 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6517 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6518 (match_operand:MVE_2 2 "s_register_operand" "w")
6519 (match_operand:MVE_2 3 "s_register_operand" "w")
6520 (match_operand:HI 4 "vpr_register_operand" "Up")]
6524 "vpst\;vqrdmlsdhxt.s%#<V_sz_elem>\t%q0, %q2, %q3"
6525 [(set_attr "type" "mve_move")
6526 (set_attr "length""8")])
6529 ;; [vqrdmulhq_m_n_s])
6531 (define_insn "mve_vqrdmulhq_m_n_s<mode>"
6533 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6534 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6535 (match_operand:MVE_2 2 "s_register_operand" "w")
6536 (match_operand:<V_elem> 3 "s_register_operand" "r")
6537 (match_operand:HI 4 "vpr_register_operand" "Up")]
6541 "vpst\;vqrdmulht.s%#<V_sz_elem>\t%q0, %q2, %3"
6542 [(set_attr "type" "mve_move")
6543 (set_attr "length""8")])
6548 (define_insn "mve_vqrdmulhq_m_s<mode>"
6550 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6551 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6552 (match_operand:MVE_2 2 "s_register_operand" "w")
6553 (match_operand:MVE_2 3 "s_register_operand" "w")
6554 (match_operand:HI 4 "vpr_register_operand" "Up")]
6558 "vpst\;vqrdmulht.s%#<V_sz_elem>\t%q0, %q2, %q3"
6559 [(set_attr "type" "mve_move")
6560 (set_attr "length""8")])
6563 ;; [vmlaldavaq_p_u, vmlaldavaq_p_s])
6565 (define_insn "mve_vmlaldavaq_p_<supf><mode>"
6567 (set (match_operand:DI 0 "s_register_operand" "=r")
6568 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
6569 (match_operand:MVE_5 2 "s_register_operand" "w")
6570 (match_operand:MVE_5 3 "s_register_operand" "w")
6571 (match_operand:HI 4 "vpr_register_operand" "Up")]
6575 "vpst\;vmlaldavat.<supf>%#<V_sz_elem> %Q0, %R0, %q2, %q3"
6576 [(set_attr "type" "mve_move")
6577 (set_attr "length""8")])
6580 ;; [vmlaldavaxq_p_s])
6582 (define_insn "mve_vmlaldavaxq_p_<supf><mode>"
6584 (set (match_operand:DI 0 "s_register_operand" "=r")
6585 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
6586 (match_operand:MVE_5 2 "s_register_operand" "w")
6587 (match_operand:MVE_5 3 "s_register_operand" "w")
6588 (match_operand:HI 4 "vpr_register_operand" "Up")]
6592 "vpst\;vmlaldavaxt.<supf>%#<V_sz_elem> %Q0, %R0, %q2, %q3"
6593 [(set_attr "type" "mve_move")
6594 (set_attr "length""8")])
6597 ;; [vqrshrnbq_m_n_u, vqrshrnbq_m_n_s])
6599 (define_insn "mve_vqrshrnbq_m_n_<supf><mode>"
6601 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
6602 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
6603 (match_operand:MVE_5 2 "s_register_operand" "w")
6604 (match_operand:SI 3 "mve_imm_8" "Rb")
6605 (match_operand:HI 4 "vpr_register_operand" "Up")]
6609 "vpst\;vqrshrnbt.<supf>%#<V_sz_elem> %q0, %q2, %3"
6610 [(set_attr "type" "mve_move")
6611 (set_attr "length""8")])
6614 ;; [vqrshrntq_m_n_s, vqrshrntq_m_n_u])
6616 (define_insn "mve_vqrshrntq_m_n_<supf><mode>"
6618 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
6619 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
6620 (match_operand:MVE_5 2 "s_register_operand" "w")
6621 (match_operand:SI 3 "mve_imm_8" "Rb")
6622 (match_operand:HI 4 "vpr_register_operand" "Up")]
6626 "vpst\;vqrshrntt.<supf>%#<V_sz_elem> %q0, %q2, %3"
6627 [(set_attr "type" "mve_move")
6628 (set_attr "length""8")])
6631 ;; [vqshrnbq_m_n_u, vqshrnbq_m_n_s])
6633 (define_insn "mve_vqshrnbq_m_n_<supf><mode>"
6635 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
6636 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
6637 (match_operand:MVE_5 2 "s_register_operand" "w")
6638 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")
6639 (match_operand:HI 4 "vpr_register_operand" "Up")]
6643 "vpst\n\tvqshrnbt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
6644 [(set_attr "type" "mve_move")
6645 (set_attr "length""8")])
6648 ;; [vqshrntq_m_n_s, vqshrntq_m_n_u])
6650 (define_insn "mve_vqshrntq_m_n_<supf><mode>"
6652 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
6653 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
6654 (match_operand:MVE_5 2 "s_register_operand" "w")
6655 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")
6656 (match_operand:HI 4 "vpr_register_operand" "Up")]
6660 "vpst\;vqshrntt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
6661 [(set_attr "type" "mve_move")
6662 (set_attr "length""8")])
6665 ;; [vrmlaldavhaq_p_s])
6667 (define_insn "mve_vrmlaldavhaq_p_sv4si"
6669 (set (match_operand:DI 0 "s_register_operand" "=r")
6670 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
6671 (match_operand:V4SI 2 "s_register_operand" "w")
6672 (match_operand:V4SI 3 "s_register_operand" "w")
6673 (match_operand:HI 4 "vpr_register_operand" "Up")]
6677 "vpst\;vrmlaldavhat.s32\t%Q0, %R0, %q2, %q3"
6678 [(set_attr "type" "mve_move")
6679 (set_attr "length""8")])
6682 ;; [vrshrnbq_m_n_u, vrshrnbq_m_n_s])
6684 (define_insn "mve_vrshrnbq_m_n_<supf><mode>"
6686 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
6687 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
6688 (match_operand:MVE_5 2 "s_register_operand" "w")
6689 (match_operand:SI 3 "mve_imm_8" "Rb")
6690 (match_operand:HI 4 "vpr_register_operand" "Up")]
6694 "vpst\;vrshrnbt.i%#<V_sz_elem>\t%q0, %q2, %3"
6695 [(set_attr "type" "mve_move")
6696 (set_attr "length""8")])
6699 ;; [vrshrntq_m_n_u, vrshrntq_m_n_s])
6701 (define_insn "mve_vrshrntq_m_n_<supf><mode>"
6703 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
6704 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
6705 (match_operand:MVE_5 2 "s_register_operand" "w")
6706 (match_operand:SI 3 "mve_imm_8" "Rb")
6707 (match_operand:HI 4 "vpr_register_operand" "Up")]
6711 "vpst\;vrshrntt.i%#<V_sz_elem>\t%q0, %q2, %3"
6712 [(set_attr "type" "mve_move")
6713 (set_attr "length""8")])
6716 ;; [vshllbq_m_n_u, vshllbq_m_n_s])
6718 (define_insn "mve_vshllbq_m_n_<supf><mode>"
6720 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
6721 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
6722 (match_operand:MVE_3 2 "s_register_operand" "w")
6723 (match_operand:SI 3 "immediate_operand" "i")
6724 (match_operand:HI 4 "vpr_register_operand" "Up")]
6728 "vpst\;vshllbt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
6729 [(set_attr "type" "mve_move")
6730 (set_attr "length""8")])
6733 ;; [vshlltq_m_n_u, vshlltq_m_n_s])
6735 (define_insn "mve_vshlltq_m_n_<supf><mode>"
6737 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
6738 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
6739 (match_operand:MVE_3 2 "s_register_operand" "w")
6740 (match_operand:SI 3 "immediate_operand" "i")
6741 (match_operand:HI 4 "vpr_register_operand" "Up")]
6745 "vpst\;vshlltt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
6746 [(set_attr "type" "mve_move")
6747 (set_attr "length""8")])
6750 ;; [vshrnbq_m_n_s, vshrnbq_m_n_u])
6752 (define_insn "mve_vshrnbq_m_n_<supf><mode>"
6754 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
6755 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
6756 (match_operand:MVE_5 2 "s_register_operand" "w")
6757 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")
6758 (match_operand:HI 4 "vpr_register_operand" "Up")]
6762 "vpst\;vshrnbt.i%#<V_sz_elem>\t%q0, %q2, %3"
6763 [(set_attr "type" "mve_move")
6764 (set_attr "length""8")])
6767 ;; [vshrntq_m_n_s, vshrntq_m_n_u])
6769 (define_insn "mve_vshrntq_m_n_<supf><mode>"
6771 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
6772 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
6773 (match_operand:MVE_5 2 "s_register_operand" "w")
6774 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")
6775 (match_operand:HI 4 "vpr_register_operand" "Up")]
6779 "vpst\;vshrntt.i%#<V_sz_elem>\t%q0, %q2, %3"
6780 [(set_attr "type" "mve_move")
6781 (set_attr "length""8")])
6784 ;; [vmlsldavaq_p_s])
6786 (define_insn "mve_vmlsldavaq_p_s<mode>"
6788 (set (match_operand:DI 0 "s_register_operand" "=r")
6789 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
6790 (match_operand:MVE_5 2 "s_register_operand" "w")
6791 (match_operand:MVE_5 3 "s_register_operand" "w")
6792 (match_operand:HI 4 "vpr_register_operand" "Up")]
6796 "vpst\;vmlsldavat.s%#<V_sz_elem>\t%Q0, %R0, %q2, %q3"
6797 [(set_attr "type" "mve_move")
6798 (set_attr "length""8")])
6801 ;; [vmlsldavaxq_p_s])
6803 (define_insn "mve_vmlsldavaxq_p_s<mode>"
6805 (set (match_operand:DI 0 "s_register_operand" "=r")
6806 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
6807 (match_operand:MVE_5 2 "s_register_operand" "w")
6808 (match_operand:MVE_5 3 "s_register_operand" "w")
6809 (match_operand:HI 4 "vpr_register_operand" "Up")]
6813 "vpst\;vmlsldavaxt.s%#<V_sz_elem>\t%Q0, %R0, %q2, %q3"
6814 [(set_attr "type" "mve_move")
6815 (set_attr "length""8")])
6818 ;; [vmullbq_poly_m_p])
6820 (define_insn "mve_vmullbq_poly_m_p<mode>"
6822 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
6823 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
6824 (match_operand:MVE_3 2 "s_register_operand" "w")
6825 (match_operand:MVE_3 3 "s_register_operand" "w")
6826 (match_operand:HI 4 "vpr_register_operand" "Up")]
6830 "vpst\;vmullbt.p%#<V_sz_elem>\t%q0, %q2, %q3"
6831 [(set_attr "type" "mve_move")
6832 (set_attr "length""8")])
6835 ;; [vmulltq_poly_m_p])
6837 (define_insn "mve_vmulltq_poly_m_p<mode>"
6839 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
6840 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
6841 (match_operand:MVE_3 2 "s_register_operand" "w")
6842 (match_operand:MVE_3 3 "s_register_operand" "w")
6843 (match_operand:HI 4 "vpr_register_operand" "Up")]
6847 "vpst\;vmulltt.p%#<V_sz_elem>\t%q0, %q2, %q3"
6848 [(set_attr "type" "mve_move")
6849 (set_attr "length""8")])
6852 ;; [vqdmullbq_m_n_s])
6854 (define_insn "mve_vqdmullbq_m_n_s<mode>"
6856 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
6857 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
6858 (match_operand:MVE_5 2 "s_register_operand" "w")
6859 (match_operand:<V_elem> 3 "s_register_operand" "r")
6860 (match_operand:HI 4 "vpr_register_operand" "Up")]
6864 "vpst\;vqdmullbt.s%#<V_sz_elem>\t%q0, %q2, %3"
6865 [(set_attr "type" "mve_move")
6866 (set_attr "length""8")])
6871 (define_insn "mve_vqdmullbq_m_s<mode>"
6873 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
6874 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
6875 (match_operand:MVE_5 2 "s_register_operand" "w")
6876 (match_operand:MVE_5 3 "s_register_operand" "w")
6877 (match_operand:HI 4 "vpr_register_operand" "Up")]
6881 "vpst\;vqdmullbt.s%#<V_sz_elem>\t%q0, %q2, %q3"
6882 [(set_attr "type" "mve_move")
6883 (set_attr "length""8")])
6886 ;; [vqdmulltq_m_n_s])
6888 (define_insn "mve_vqdmulltq_m_n_s<mode>"
6890 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
6891 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
6892 (match_operand:MVE_5 2 "s_register_operand" "w")
6893 (match_operand:<V_elem> 3 "s_register_operand" "r")
6894 (match_operand:HI 4 "vpr_register_operand" "Up")]
6898 "vpst\;vqdmulltt.s%#<V_sz_elem>\t%q0, %q2, %3"
6899 [(set_attr "type" "mve_move")
6900 (set_attr "length""8")])
6905 (define_insn "mve_vqdmulltq_m_s<mode>"
6907 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
6908 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
6909 (match_operand:MVE_5 2 "s_register_operand" "w")
6910 (match_operand:MVE_5 3 "s_register_operand" "w")
6911 (match_operand:HI 4 "vpr_register_operand" "Up")]
6915 "vpst\;vqdmulltt.s%#<V_sz_elem>\t%q0, %q2, %q3"
6916 [(set_attr "type" "mve_move")
6917 (set_attr "length""8")])
6920 ;; [vqrshrunbq_m_n_s])
6922 (define_insn "mve_vqrshrunbq_m_n_s<mode>"
6924 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
6925 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
6926 (match_operand:MVE_5 2 "s_register_operand" "w")
6927 (match_operand:SI 3 "mve_imm_8" "Rb")
6928 (match_operand:HI 4 "vpr_register_operand" "Up")]
6932 "vpst\;vqrshrunbt.s%#<V_sz_elem>\t%q0, %q2, %3"
6933 [(set_attr "type" "mve_move")
6934 (set_attr "length""8")])
6937 ;; [vqrshruntq_m_n_s])
6939 (define_insn "mve_vqrshruntq_m_n_s<mode>"
6941 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
6942 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
6943 (match_operand:MVE_5 2 "s_register_operand" "w")
6944 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")
6945 (match_operand:HI 4 "vpr_register_operand" "Up")]
6949 "vpst\;vqrshruntt.s%#<V_sz_elem>\t%q0, %q2, %3"
6950 [(set_attr "type" "mve_move")
6951 (set_attr "length""8")])
6954 ;; [vqshrunbq_m_n_s])
6956 (define_insn "mve_vqshrunbq_m_n_s<mode>"
6958 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
6959 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
6960 (match_operand:MVE_5 2 "s_register_operand" "w")
6961 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")
6962 (match_operand:HI 4 "vpr_register_operand" "Up")]
6966 "vpst\;vqshrunbt.s%#<V_sz_elem>\t%q0, %q2, %3"
6967 [(set_attr "type" "mve_move")
6968 (set_attr "length""8")])
6971 ;; [vqshruntq_m_n_s])
6973 (define_insn "mve_vqshruntq_m_n_s<mode>"
6975 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
6976 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
6977 (match_operand:MVE_5 2 "s_register_operand" "w")
6978 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")
6979 (match_operand:HI 4 "vpr_register_operand" "Up")]
6983 "vpst\;vqshruntt.s%#<V_sz_elem>\t%q0, %q2, %3"
6984 [(set_attr "type" "mve_move")
6985 (set_attr "length""8")])
6988 ;; [vrmlaldavhaq_p_u])
6990 (define_insn "mve_vrmlaldavhaq_p_uv4si"
6992 (set (match_operand:DI 0 "s_register_operand" "=r")
6993 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
6994 (match_operand:V4SI 2 "s_register_operand" "w")
6995 (match_operand:V4SI 3 "s_register_operand" "w")
6996 (match_operand:HI 4 "vpr_register_operand" "Up")]
7000 "vpst\;vrmlaldavhat.u32\t%Q0, %R0, %q2, %q3"
7001 [(set_attr "type" "mve_move")
7002 (set_attr "length""8")])
7005 ;; [vrmlaldavhaxq_p_s])
7007 (define_insn "mve_vrmlaldavhaxq_p_sv4si"
7009 (set (match_operand:DI 0 "s_register_operand" "=r")
7010 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
7011 (match_operand:V4SI 2 "s_register_operand" "w")
7012 (match_operand:V4SI 3 "s_register_operand" "w")
7013 (match_operand:HI 4 "vpr_register_operand" "Up")]
7017 "vpst\;vrmlaldavhaxt.s32\t%Q0, %R0, %q2, %q3"
7018 [(set_attr "type" "mve_move")
7019 (set_attr "length""8")])
7022 ;; [vrmlsldavhaq_p_s])
7024 (define_insn "mve_vrmlsldavhaq_p_sv4si"
7026 (set (match_operand:DI 0 "s_register_operand" "=r")
7027 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
7028 (match_operand:V4SI 2 "s_register_operand" "w")
7029 (match_operand:V4SI 3 "s_register_operand" "w")
7030 (match_operand:HI 4 "vpr_register_operand" "Up")]
7034 "vpst\;vrmlsldavhat.s32\t%Q0, %R0, %q2, %q3"
7035 [(set_attr "type" "mve_move")
7036 (set_attr "length""8")])
7039 ;; [vrmlsldavhaxq_p_s])
7041 (define_insn "mve_vrmlsldavhaxq_p_sv4si"
7043 (set (match_operand:DI 0 "s_register_operand" "=r")
7044 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
7045 (match_operand:V4SI 2 "s_register_operand" "w")
7046 (match_operand:V4SI 3 "s_register_operand" "w")
7047 (match_operand:HI 4 "vpr_register_operand" "Up")]
7051 "vpst\;vrmlsldavhaxt.s32\t%Q0, %R0, %q2, %q3"
7052 [(set_attr "type" "mve_move")
7053 (set_attr "length""8")])
7057 (define_insn "mve_vabdq_m_f<mode>"
7059 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7060 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7061 (match_operand:MVE_0 2 "s_register_operand" "w")
7062 (match_operand:MVE_0 3 "s_register_operand" "w")
7063 (match_operand:HI 4 "vpr_register_operand" "Up")]
7066 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7067 "vpst\;vabdt.f%#<V_sz_elem> %q0, %q2, %q3"
7068 [(set_attr "type" "mve_move")
7069 (set_attr "length""8")])
7074 (define_insn "mve_vaddq_m_f<mode>"
7076 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7077 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7078 (match_operand:MVE_0 2 "s_register_operand" "w")
7079 (match_operand:MVE_0 3 "s_register_operand" "w")
7080 (match_operand:HI 4 "vpr_register_operand" "Up")]
7083 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7084 "vpst\;vaddt.f%#<V_sz_elem> %q0, %q2, %q3"
7085 [(set_attr "type" "mve_move")
7086 (set_attr "length""8")])
7091 (define_insn "mve_vaddq_m_n_f<mode>"
7093 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7094 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7095 (match_operand:MVE_0 2 "s_register_operand" "w")
7096 (match_operand:<V_elem> 3 "s_register_operand" "r")
7097 (match_operand:HI 4 "vpr_register_operand" "Up")]
7100 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7101 "vpst\;vaddt.f%#<V_sz_elem> %q0, %q2, %3"
7102 [(set_attr "type" "mve_move")
7103 (set_attr "length""8")])
7108 (define_insn "mve_vandq_m_f<mode>"
7110 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7111 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7112 (match_operand:MVE_0 2 "s_register_operand" "w")
7113 (match_operand:MVE_0 3 "s_register_operand" "w")
7114 (match_operand:HI 4 "vpr_register_operand" "Up")]
7117 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7118 "vpst\;vandt %q0, %q2, %q3"
7119 [(set_attr "type" "mve_move")
7120 (set_attr "length""8")])
7125 (define_insn "mve_vbicq_m_f<mode>"
7127 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7128 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7129 (match_operand:MVE_0 2 "s_register_operand" "w")
7130 (match_operand:MVE_0 3 "s_register_operand" "w")
7131 (match_operand:HI 4 "vpr_register_operand" "Up")]
7134 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7135 "vpst\;vbict %q0, %q2, %q3"
7136 [(set_attr "type" "mve_move")
7137 (set_attr "length""8")])
7142 (define_insn "mve_vbrsrq_m_n_f<mode>"
7144 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7145 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7146 (match_operand:MVE_0 2 "s_register_operand" "w")
7147 (match_operand:SI 3 "s_register_operand" "r")
7148 (match_operand:HI 4 "vpr_register_operand" "Up")]
7151 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7152 "vpst\;vbrsrt.%#<V_sz_elem> %q0, %q2, %3"
7153 [(set_attr "type" "mve_move")
7154 (set_attr "length""8")])
7157 ;; [vcaddq_rot270_m_f])
7159 (define_insn "mve_vcaddq_rot270_m_f<mode>"
7161 (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
7162 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7163 (match_operand:MVE_0 2 "s_register_operand" "w")
7164 (match_operand:MVE_0 3 "s_register_operand" "w")
7165 (match_operand:HI 4 "vpr_register_operand" "Up")]
7168 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7169 "vpst\;vcaddt.f%#<V_sz_elem> %q0, %q2, %q3, #270"
7170 [(set_attr "type" "mve_move")
7171 (set_attr "length""8")])
7174 ;; [vcaddq_rot90_m_f])
7176 (define_insn "mve_vcaddq_rot90_m_f<mode>"
7178 (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
7179 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7180 (match_operand:MVE_0 2 "s_register_operand" "w")
7181 (match_operand:MVE_0 3 "s_register_operand" "w")
7182 (match_operand:HI 4 "vpr_register_operand" "Up")]
7185 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7186 "vpst\;vcaddt.f%#<V_sz_elem> %q0, %q2, %q3, #90"
7187 [(set_attr "type" "mve_move")
7188 (set_attr "length""8")])
7193 (define_insn "mve_vcmlaq_m_f<mode>"
7195 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7196 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7197 (match_operand:MVE_0 2 "s_register_operand" "w")
7198 (match_operand:MVE_0 3 "s_register_operand" "w")
7199 (match_operand:HI 4 "vpr_register_operand" "Up")]
7202 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7203 "vpst\;vcmlat.f%#<V_sz_elem> %q0, %q2, %q3, #0"
7204 [(set_attr "type" "mve_move")
7205 (set_attr "length""8")])
7208 ;; [vcmlaq_rot180_m_f])
7210 (define_insn "mve_vcmlaq_rot180_m_f<mode>"
7212 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7213 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7214 (match_operand:MVE_0 2 "s_register_operand" "w")
7215 (match_operand:MVE_0 3 "s_register_operand" "w")
7216 (match_operand:HI 4 "vpr_register_operand" "Up")]
7219 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7220 "vpst\;vcmlat.f%#<V_sz_elem> %q0, %q2, %q3, #180"
7221 [(set_attr "type" "mve_move")
7222 (set_attr "length""8")])
7225 ;; [vcmlaq_rot270_m_f])
7227 (define_insn "mve_vcmlaq_rot270_m_f<mode>"
7229 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7230 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7231 (match_operand:MVE_0 2 "s_register_operand" "w")
7232 (match_operand:MVE_0 3 "s_register_operand" "w")
7233 (match_operand:HI 4 "vpr_register_operand" "Up")]
7236 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7237 "vpst\;vcmlat.f%#<V_sz_elem> %q0, %q2, %q3, #270"
7238 [(set_attr "type" "mve_move")
7239 (set_attr "length""8")])
7242 ;; [vcmlaq_rot90_m_f])
7244 (define_insn "mve_vcmlaq_rot90_m_f<mode>"
7246 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7247 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7248 (match_operand:MVE_0 2 "s_register_operand" "w")
7249 (match_operand:MVE_0 3 "s_register_operand" "w")
7250 (match_operand:HI 4 "vpr_register_operand" "Up")]
7253 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7254 "vpst\;vcmlat.f%#<V_sz_elem> %q0, %q2, %q3, #90"
7255 [(set_attr "type" "mve_move")
7256 (set_attr "length""8")])
7261 (define_insn "mve_vcmulq_m_f<mode>"
7263 (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
7264 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7265 (match_operand:MVE_0 2 "s_register_operand" "w")
7266 (match_operand:MVE_0 3 "s_register_operand" "w")
7267 (match_operand:HI 4 "vpr_register_operand" "Up")]
7270 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7271 "vpst\;vcmult.f%#<V_sz_elem> %q0, %q2, %q3, #0"
7272 [(set_attr "type" "mve_move")
7273 (set_attr "length""8")])
7276 ;; [vcmulq_rot180_m_f])
7278 (define_insn "mve_vcmulq_rot180_m_f<mode>"
7280 (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
7281 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7282 (match_operand:MVE_0 2 "s_register_operand" "w")
7283 (match_operand:MVE_0 3 "s_register_operand" "w")
7284 (match_operand:HI 4 "vpr_register_operand" "Up")]
7287 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7288 "vpst\;vcmult.f%#<V_sz_elem> %q0, %q2, %q3, #180"
7289 [(set_attr "type" "mve_move")
7290 (set_attr "length""8")])
7293 ;; [vcmulq_rot270_m_f])
7295 (define_insn "mve_vcmulq_rot270_m_f<mode>"
7297 (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
7298 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7299 (match_operand:MVE_0 2 "s_register_operand" "w")
7300 (match_operand:MVE_0 3 "s_register_operand" "w")
7301 (match_operand:HI 4 "vpr_register_operand" "Up")]
7304 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7305 "vpst\;vcmult.f%#<V_sz_elem> %q0, %q2, %q3, #270"
7306 [(set_attr "type" "mve_move")
7307 (set_attr "length""8")])
7310 ;; [vcmulq_rot90_m_f])
7312 (define_insn "mve_vcmulq_rot90_m_f<mode>"
7314 (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
7315 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7316 (match_operand:MVE_0 2 "s_register_operand" "w")
7317 (match_operand:MVE_0 3 "s_register_operand" "w")
7318 (match_operand:HI 4 "vpr_register_operand" "Up")]
7321 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7322 "vpst\;vcmult.f%#<V_sz_elem> %q0, %q2, %q3, #90"
7323 [(set_attr "type" "mve_move")
7324 (set_attr "length""8")])
7329 (define_insn "mve_veorq_m_f<mode>"
7331 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7332 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7333 (match_operand:MVE_0 2 "s_register_operand" "w")
7334 (match_operand:MVE_0 3 "s_register_operand" "w")
7335 (match_operand:HI 4 "vpr_register_operand" "Up")]
7338 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7339 "vpst\;veort %q0, %q2, %q3"
7340 [(set_attr "type" "mve_move")
7341 (set_attr "length""8")])
7346 (define_insn "mve_vfmaq_m_f<mode>"
7348 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7349 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7350 (match_operand:MVE_0 2 "s_register_operand" "w")
7351 (match_operand:MVE_0 3 "s_register_operand" "w")
7352 (match_operand:HI 4 "vpr_register_operand" "Up")]
7355 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7356 "vpst\;vfmat.f%#<V_sz_elem> %q0, %q2, %q3"
7357 [(set_attr "type" "mve_move")
7358 (set_attr "length""8")])
7363 (define_insn "mve_vfmaq_m_n_f<mode>"
7365 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7366 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7367 (match_operand:MVE_0 2 "s_register_operand" "w")
7368 (match_operand:<V_elem> 3 "s_register_operand" "r")
7369 (match_operand:HI 4 "vpr_register_operand" "Up")]
7372 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7373 "vpst\;vfmat.f%#<V_sz_elem> %q0, %q2, %3"
7374 [(set_attr "type" "mve_move")
7375 (set_attr "length""8")])
7380 (define_insn "mve_vfmasq_m_n_f<mode>"
7382 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7383 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7384 (match_operand:MVE_0 2 "s_register_operand" "w")
7385 (match_operand:<V_elem> 3 "s_register_operand" "r")
7386 (match_operand:HI 4 "vpr_register_operand" "Up")]
7389 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7390 "vpst\;vfmast.f%#<V_sz_elem> %q0, %q2, %3"
7391 [(set_attr "type" "mve_move")
7392 (set_attr "length""8")])
7397 (define_insn "mve_vfmsq_m_f<mode>"
7399 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7400 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7401 (match_operand:MVE_0 2 "s_register_operand" "w")
7402 (match_operand:MVE_0 3 "s_register_operand" "w")
7403 (match_operand:HI 4 "vpr_register_operand" "Up")]
7406 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7407 "vpst\;vfmst.f%#<V_sz_elem> %q0, %q2, %q3"
7408 [(set_attr "type" "mve_move")
7409 (set_attr "length""8")])
7414 (define_insn "mve_vmaxnmq_m_f<mode>"
7416 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7417 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7418 (match_operand:MVE_0 2 "s_register_operand" "w")
7419 (match_operand:MVE_0 3 "s_register_operand" "w")
7420 (match_operand:HI 4 "vpr_register_operand" "Up")]
7423 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7424 "vpst\;vmaxnmt.f%#<V_sz_elem> %q0, %q2, %q3"
7425 [(set_attr "type" "mve_move")
7426 (set_attr "length""8")])
7431 (define_insn "mve_vminnmq_m_f<mode>"
7433 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7434 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7435 (match_operand:MVE_0 2 "s_register_operand" "w")
7436 (match_operand:MVE_0 3 "s_register_operand" "w")
7437 (match_operand:HI 4 "vpr_register_operand" "Up")]
7440 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7441 "vpst\;vminnmt.f%#<V_sz_elem> %q0, %q2, %q3"
7442 [(set_attr "type" "mve_move")
7443 (set_attr "length""8")])
7448 (define_insn "mve_vmulq_m_f<mode>"
7450 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7451 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7452 (match_operand:MVE_0 2 "s_register_operand" "w")
7453 (match_operand:MVE_0 3 "s_register_operand" "w")
7454 (match_operand:HI 4 "vpr_register_operand" "Up")]
7457 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7458 "vpst\;vmult.f%#<V_sz_elem> %q0, %q2, %q3"
7459 [(set_attr "type" "mve_move")
7460 (set_attr "length""8")])
7465 (define_insn "mve_vmulq_m_n_f<mode>"
7467 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7468 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7469 (match_operand:MVE_0 2 "s_register_operand" "w")
7470 (match_operand:<V_elem> 3 "s_register_operand" "r")
7471 (match_operand:HI 4 "vpr_register_operand" "Up")]
7474 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7475 "vpst\;vmult.f%#<V_sz_elem> %q0, %q2, %3"
7476 [(set_attr "type" "mve_move")
7477 (set_attr "length""8")])
7482 (define_insn "mve_vornq_m_f<mode>"
7484 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7485 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7486 (match_operand:MVE_0 2 "s_register_operand" "w")
7487 (match_operand:MVE_0 3 "s_register_operand" "w")
7488 (match_operand:HI 4 "vpr_register_operand" "Up")]
7491 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7492 "vpst\;vornt %q0, %q2, %q3"
7493 [(set_attr "type" "mve_move")
7494 (set_attr "length""8")])
7499 (define_insn "mve_vorrq_m_f<mode>"
7501 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7502 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7503 (match_operand:MVE_0 2 "s_register_operand" "w")
7504 (match_operand:MVE_0 3 "s_register_operand" "w")
7505 (match_operand:HI 4 "vpr_register_operand" "Up")]
7508 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7509 "vpst\;vorrt %q0, %q2, %q3"
7510 [(set_attr "type" "mve_move")
7511 (set_attr "length""8")])
7516 (define_insn "mve_vsubq_m_f<mode>"
7518 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7519 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7520 (match_operand:MVE_0 2 "s_register_operand" "w")
7521 (match_operand:MVE_0 3 "s_register_operand" "w")
7522 (match_operand:HI 4 "vpr_register_operand" "Up")]
7525 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7526 "vpst\;vsubt.f%#<V_sz_elem>\t%q0, %q2, %q3"
7527 [(set_attr "type" "mve_move")
7528 (set_attr "length""8")])
7533 (define_insn "mve_vsubq_m_n_f<mode>"
7535 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7536 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7537 (match_operand:MVE_0 2 "s_register_operand" "w")
7538 (match_operand:<V_elem> 3 "s_register_operand" "r")
7539 (match_operand:HI 4 "vpr_register_operand" "Up")]
7542 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7543 "vpst\;vsubt.f%#<V_sz_elem>\t%q0, %q2, %3"
7544 [(set_attr "type" "mve_move")
7545 (set_attr "length""8")])
7548 ;; [vstrbq_s vstrbq_u]
7550 (define_insn "mve_vstrbq_<supf><mode>"
7551 [(set (match_operand:<MVE_B_ELEM> 0 "mve_memory_operand" "=Ux")
7552 (unspec:<MVE_B_ELEM> [(match_operand:MVE_2 1 "s_register_operand" "w")]
7558 int regno = REGNO (operands[1]);
7559 ops[1] = gen_rtx_REG (TImode, regno);
7560 ops[0] = operands[0];
7561 output_asm_insn("vstrb.<V_sz_elem>\t%q1, %E0",ops);
7564 [(set_attr "length" "4")])
7567 ;; [vstrbq_scatter_offset_s vstrbq_scatter_offset_u]
7569 (define_expand "mve_vstrbq_scatter_offset_<supf><mode>"
7570 [(match_operand:<MVE_B_ELEM> 0 "mve_scatter_memory")
7571 (match_operand:MVE_2 1 "s_register_operand")
7572 (match_operand:MVE_2 2 "s_register_operand")
7573 (unspec:V4SI [(const_int 0)] VSTRBSOQ)]
7576 rtx ind = XEXP (operands[0], 0);
7577 gcc_assert (REG_P (ind));
7578 emit_insn (gen_mve_vstrbq_scatter_offset_<supf><mode>_insn (ind, operands[1],
7583 (define_insn "mve_vstrbq_scatter_offset_<supf><mode>_insn"
7584 [(set (mem:BLK (scratch))
7586 [(match_operand:SI 0 "register_operand" "r")
7587 (match_operand:MVE_2 1 "s_register_operand" "w")
7588 (match_operand:MVE_2 2 "s_register_operand" "w")]
7591 "vstrb.<V_sz_elem>\t%q2, [%0, %q1]"
7592 [(set_attr "length" "4")])
7595 ;; [vstrwq_scatter_base_s vstrwq_scatter_base_u]
7597 (define_insn "mve_vstrwq_scatter_base_<supf>v4si"
7598 [(set (mem:BLK (scratch))
7600 [(match_operand:V4SI 0 "s_register_operand" "w")
7601 (match_operand:SI 1 "immediate_operand" "i")
7602 (match_operand:V4SI 2 "s_register_operand" "w")]
7608 ops[0] = operands[0];
7609 ops[1] = operands[1];
7610 ops[2] = operands[2];
7611 output_asm_insn("vstrw.u32\t%q2, [%q0, %1]",ops);
7614 [(set_attr "length" "4")])
7617 ;; [vldrbq_gather_offset_s vldrbq_gather_offset_u]
7619 (define_insn "mve_vldrbq_gather_offset_<supf><mode>"
7620 [(set (match_operand:MVE_2 0 "s_register_operand" "=&w")
7621 (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "memory_operand" "Us")
7622 (match_operand:MVE_2 2 "s_register_operand" "w")]
7628 ops[0] = operands[0];
7629 ops[1] = operands[1];
7630 ops[2] = operands[2];
7631 if (!strcmp ("<supf>","s") && <V_sz_elem> == 8)
7632 output_asm_insn ("vldrb.u8\t%q0, [%m1, %q2]",ops);
7634 output_asm_insn ("vldrb.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops);
7637 [(set_attr "length" "4")])
7640 ;; [vldrbq_s vldrbq_u]
7642 (define_insn "mve_vldrbq_<supf><mode>"
7643 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
7644 (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "mve_memory_operand" "Ux")]
7650 int regno = REGNO (operands[0]);
7651 ops[0] = gen_rtx_REG (TImode, regno);
7652 ops[1] = operands[1];
7653 if (<V_sz_elem> == 8)
7654 output_asm_insn ("vldrb.<V_sz_elem>\t%q0, %E1",ops);
7656 output_asm_insn ("vldrb.<supf><V_sz_elem>\t%q0, %E1",ops);
7659 [(set_attr "length" "4")])
7662 ;; [vldrwq_gather_base_s vldrwq_gather_base_u]
7664 (define_insn "mve_vldrwq_gather_base_<supf>v4si"
7665 [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
7666 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
7667 (match_operand:SI 2 "immediate_operand" "i")]
7673 ops[0] = operands[0];
7674 ops[1] = operands[1];
7675 ops[2] = operands[2];
7676 output_asm_insn ("vldrw.u32\t%q0, [%q1, %2]",ops);
7679 [(set_attr "length" "4")])
7682 ;; [vstrbq_scatter_offset_p_s vstrbq_scatter_offset_p_u]
7684 (define_expand "mve_vstrbq_scatter_offset_p_<supf><mode>"
7685 [(match_operand:<MVE_B_ELEM> 0 "mve_scatter_memory")
7686 (match_operand:MVE_2 1 "s_register_operand")
7687 (match_operand:MVE_2 2 "s_register_operand")
7688 (match_operand:HI 3 "vpr_register_operand" "Up")
7689 (unspec:V4SI [(const_int 0)] VSTRBSOQ)]
7692 rtx ind = XEXP (operands[0], 0);
7693 gcc_assert (REG_P (ind));
7695 gen_mve_vstrbq_scatter_offset_p_<supf><mode>_insn (ind, operands[1],
7701 (define_insn "mve_vstrbq_scatter_offset_p_<supf><mode>_insn"
7702 [(set (mem:BLK (scratch))
7704 [(match_operand:SI 0 "register_operand" "r")
7705 (match_operand:MVE_2 1 "s_register_operand" "w")
7706 (match_operand:MVE_2 2 "s_register_operand" "w")
7707 (match_operand:HI 3 "vpr_register_operand" "Up")]
7710 "vpst\;vstrbt.<V_sz_elem>\t%q2, [%0, %q1]"
7711 [(set_attr "length" "8")])
7714 ;; [vstrwq_scatter_base_p_s vstrwq_scatter_base_p_u]
7716 (define_insn "mve_vstrwq_scatter_base_p_<supf>v4si"
7717 [(set (mem:BLK (scratch))
7719 [(match_operand:V4SI 0 "s_register_operand" "w")
7720 (match_operand:SI 1 "immediate_operand" "i")
7721 (match_operand:V4SI 2 "s_register_operand" "w")
7722 (match_operand:HI 3 "vpr_register_operand" "Up")]
7728 ops[0] = operands[0];
7729 ops[1] = operands[1];
7730 ops[2] = operands[2];
7731 output_asm_insn ("vpst\n\tvstrwt.u32\t%q2, [%q0, %1]",ops);
7734 [(set_attr "length" "8")])
7737 ;; [vstrbq_p_s vstrbq_p_u]
7739 (define_insn "mve_vstrbq_p_<supf><mode>"
7740 [(set (match_operand:<MVE_B_ELEM> 0 "mve_memory_operand" "=Ux")
7741 (unspec:<MVE_B_ELEM> [(match_operand:MVE_2 1 "s_register_operand" "w")
7742 (match_operand:HI 2 "vpr_register_operand" "Up")]
7748 int regno = REGNO (operands[1]);
7749 ops[1] = gen_rtx_REG (TImode, regno);
7750 ops[0] = operands[0];
7751 output_asm_insn ("vpst\;vstrbt.<V_sz_elem>\t%q1, %E0",ops);
7754 [(set_attr "length" "8")])
7757 ;; [vldrbq_gather_offset_z_s vldrbq_gather_offset_z_u]
7759 (define_insn "mve_vldrbq_gather_offset_z_<supf><mode>"
7760 [(set (match_operand:MVE_2 0 "s_register_operand" "=&w")
7761 (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "memory_operand" "Us")
7762 (match_operand:MVE_2 2 "s_register_operand" "w")
7763 (match_operand:HI 3 "vpr_register_operand" "Up")]
7769 ops[0] = operands[0];
7770 ops[1] = operands[1];
7771 ops[2] = operands[2];
7772 ops[3] = operands[3];
7773 if (!strcmp ("<supf>","s") && <V_sz_elem> == 8)
7774 output_asm_insn ("vpst\n\tvldrbt.u8\t%q0, [%m1, %q2]",ops);
7776 output_asm_insn ("vpst\n\tvldrbt.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops);
7779 [(set_attr "length" "8")])
7782 ;; [vldrbq_z_s vldrbq_z_u]
7784 (define_insn "mve_vldrbq_z_<supf><mode>"
7785 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
7786 (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "mve_memory_operand" "Ux")
7787 (match_operand:HI 2 "vpr_register_operand" "Up")]
7793 int regno = REGNO (operands[0]);
7794 ops[0] = gen_rtx_REG (TImode, regno);
7795 ops[1] = operands[1];
7796 if (<V_sz_elem> == 8)
7797 output_asm_insn ("vpst\;vldrbt.<V_sz_elem>\t%q0, %E1",ops);
7799 output_asm_insn ("vpst\;vldrbt.<supf><V_sz_elem>\t%q0, %E1",ops);
7802 [(set_attr "length" "8")])
7805 ;; [vldrwq_gather_base_z_s vldrwq_gather_base_z_u]
7807 (define_insn "mve_vldrwq_gather_base_z_<supf>v4si"
7808 [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
7809 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
7810 (match_operand:SI 2 "immediate_operand" "i")
7811 (match_operand:HI 3 "vpr_register_operand" "Up")]
7817 ops[0] = operands[0];
7818 ops[1] = operands[1];
7819 ops[2] = operands[2];
7820 output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%q1, %2]",ops);
7823 [(set_attr "length" "8")])
7828 (define_insn "mve_vldrhq_fv8hf"
7829 [(set (match_operand:V8HF 0 "s_register_operand" "=w")
7830 (unspec:V8HF [(match_operand:V8HI 1 "mve_memory_operand" "Ux")]
7833 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7836 int regno = REGNO (operands[0]);
7837 ops[0] = gen_rtx_REG (TImode, regno);
7838 ops[1] = operands[1];
7839 output_asm_insn ("vldrh.16\t%q0, %E1",ops);
7842 [(set_attr "length" "4")])
7845 ;; [vldrhq_gather_offset_s vldrhq_gather_offset_u]
7847 (define_insn "mve_vldrhq_gather_offset_<supf><mode>"
7848 [(set (match_operand:MVE_6 0 "s_register_operand" "=&w")
7849 (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
7850 (match_operand:MVE_6 2 "s_register_operand" "w")]
7856 ops[0] = operands[0];
7857 ops[1] = operands[1];
7858 ops[2] = operands[2];
7859 if (!strcmp ("<supf>","s") && <V_sz_elem> == 16)
7860 output_asm_insn ("vldrh.u16\t%q0, [%m1, %q2]",ops);
7862 output_asm_insn ("vldrh.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops);
7865 [(set_attr "length" "4")])
7868 ;; [vldrhq_gather_offset_z_s vldrhq_gather_offset_z_u]
7870 (define_insn "mve_vldrhq_gather_offset_z_<supf><mode>"
7871 [(set (match_operand:MVE_6 0 "s_register_operand" "=&w")
7872 (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
7873 (match_operand:MVE_6 2 "s_register_operand" "w")
7874 (match_operand:HI 3 "vpr_register_operand" "Up")
7880 ops[0] = operands[0];
7881 ops[1] = operands[1];
7882 ops[2] = operands[2];
7883 ops[3] = operands[3];
7884 if (!strcmp ("<supf>","s") && <V_sz_elem> == 16)
7885 output_asm_insn ("vpst\n\tvldrht.u16\t%q0, [%m1, %q2]",ops);
7887 output_asm_insn ("vpst\n\tvldrht.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops);
7890 [(set_attr "length" "8")])
7893 ;; [vldrhq_gather_shifted_offset_s vldrhq_gather_shifted_offset_u]
7895 (define_insn "mve_vldrhq_gather_shifted_offset_<supf><mode>"
7896 [(set (match_operand:MVE_6 0 "s_register_operand" "=&w")
7897 (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
7898 (match_operand:MVE_6 2 "s_register_operand" "w")]
7904 ops[0] = operands[0];
7905 ops[1] = operands[1];
7906 ops[2] = operands[2];
7907 if (!strcmp ("<supf>","s") && <V_sz_elem> == 16)
7908 output_asm_insn ("vldrh.u16\t%q0, [%m1, %q2, uxtw #1]",ops);
7910 output_asm_insn ("vldrh.<supf><V_sz_elem>\t%q0, [%m1, %q2, uxtw #1]",ops);
7913 [(set_attr "length" "4")])
7916 ;; [vldrhq_gather_shifted_offset_z_s vldrhq_gather_shited_offset_z_u]
7918 (define_insn "mve_vldrhq_gather_shifted_offset_z_<supf><mode>"
7919 [(set (match_operand:MVE_6 0 "s_register_operand" "=&w")
7920 (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
7921 (match_operand:MVE_6 2 "s_register_operand" "w")
7922 (match_operand:HI 3 "vpr_register_operand" "Up")
7928 ops[0] = operands[0];
7929 ops[1] = operands[1];
7930 ops[2] = operands[2];
7931 ops[3] = operands[3];
7932 if (!strcmp ("<supf>","s") && <V_sz_elem> == 16)
7933 output_asm_insn ("vpst\n\tvldrht.u16\t%q0, [%m1, %q2, uxtw #1]",ops);
7935 output_asm_insn ("vpst\n\tvldrht.<supf><V_sz_elem>\t%q0, [%m1, %q2, uxtw #1]",ops);
7938 [(set_attr "length" "8")])
7941 ;; [vldrhq_s, vldrhq_u]
7943 (define_insn "mve_vldrhq_<supf><mode>"
7944 [(set (match_operand:MVE_6 0 "s_register_operand" "=w")
7945 (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "mve_memory_operand" "Ux")]
7951 int regno = REGNO (operands[0]);
7952 ops[0] = gen_rtx_REG (TImode, regno);
7953 ops[1] = operands[1];
7954 if (<V_sz_elem> == 16)
7955 output_asm_insn ("vldrh.16\t%q0, %E1",ops);
7957 output_asm_insn ("vldrh.<supf><V_sz_elem>\t%q0, %E1",ops);
7960 [(set_attr "length" "4")])
7965 (define_insn "mve_vldrhq_z_fv8hf"
7966 [(set (match_operand:V8HF 0 "s_register_operand" "=w")
7967 (unspec:V8HF [(match_operand:V8HI 1 "mve_memory_operand" "Ux")
7968 (match_operand:HI 2 "vpr_register_operand" "Up")]
7971 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7974 int regno = REGNO (operands[0]);
7975 ops[0] = gen_rtx_REG (TImode, regno);
7976 ops[1] = operands[1];
7977 output_asm_insn ("vpst\;vldrht.16\t%q0, %E1",ops);
7980 [(set_attr "length" "8")])
7983 ;; [vldrhq_z_s vldrhq_z_u]
7985 (define_insn "mve_vldrhq_z_<supf><mode>"
7986 [(set (match_operand:MVE_6 0 "s_register_operand" "=w")
7987 (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "mve_memory_operand" "Ux")
7988 (match_operand:HI 2 "vpr_register_operand" "Up")]
7994 int regno = REGNO (operands[0]);
7995 ops[0] = gen_rtx_REG (TImode, regno);
7996 ops[1] = operands[1];
7997 if (<V_sz_elem> == 16)
7998 output_asm_insn ("vpst\;vldrht.16\t%q0, %E1",ops);
8000 output_asm_insn ("vpst\;vldrht.<supf><V_sz_elem>\t%q0, %E1",ops);
8003 [(set_attr "length" "8")])
8008 (define_insn "mve_vldrwq_fv4sf"
8009 [(set (match_operand:V4SF 0 "s_register_operand" "=w")
8010 (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Ux")]
8013 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8016 int regno = REGNO (operands[0]);
8017 ops[0] = gen_rtx_REG (TImode, regno);
8018 ops[1] = operands[1];
8019 output_asm_insn ("vldrw.32\t%q0, %E1",ops);
8022 [(set_attr "length" "4")])
8025 ;; [vldrwq_s vldrwq_u]
8027 (define_insn "mve_vldrwq_<supf>v4si"
8028 [(set (match_operand:V4SI 0 "s_register_operand" "=w")
8029 (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Ux")]
8035 int regno = REGNO (operands[0]);
8036 ops[0] = gen_rtx_REG (TImode, regno);
8037 ops[1] = operands[1];
8038 output_asm_insn ("vldrw.32\t%q0, %E1",ops);
8041 [(set_attr "length" "4")])
8046 (define_insn "mve_vldrwq_z_fv4sf"
8047 [(set (match_operand:V4SF 0 "s_register_operand" "=w")
8048 (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Ux")
8049 (match_operand:HI 2 "vpr_register_operand" "Up")]
8052 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8055 int regno = REGNO (operands[0]);
8056 ops[0] = gen_rtx_REG (TImode, regno);
8057 ops[1] = operands[1];
8058 output_asm_insn ("vpst\;vldrwt.32\t%q0, %E1",ops);
8061 [(set_attr "length" "8")])
8064 ;; [vldrwq_z_s vldrwq_z_u]
8066 (define_insn "mve_vldrwq_z_<supf>v4si"
8067 [(set (match_operand:V4SI 0 "s_register_operand" "=w")
8068 (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Ux")
8069 (match_operand:HI 2 "vpr_register_operand" "Up")]
8075 int regno = REGNO (operands[0]);
8076 ops[0] = gen_rtx_REG (TImode, regno);
8077 ops[1] = operands[1];
8078 output_asm_insn ("vpst\;vldrwt.32\t%q0, %E1",ops);
8081 [(set_attr "length" "8")])
8083 (define_expand "mve_vld1q_f<mode>"
8084 [(match_operand:MVE_0 0 "s_register_operand")
8085 (unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "mve_memory_operand")] VLD1Q_F)
8087 "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT"
8089 emit_insn (gen_mve_vldr<V_sz_elem1>q_f<mode>(operands[0],operands[1]));
8093 (define_expand "mve_vld1q_<supf><mode>"
8094 [(match_operand:MVE_2 0 "s_register_operand")
8095 (unspec:MVE_2 [(match_operand:MVE_2 1 "mve_memory_operand")] VLD1Q)
8099 emit_insn (gen_mve_vldr<V_sz_elem1>q_<supf><mode>(operands[0],operands[1]));
8104 ;; [vldrdq_gather_base_s vldrdq_gather_base_u]
8106 (define_insn "mve_vldrdq_gather_base_<supf>v2di"
8107 [(set (match_operand:V2DI 0 "s_register_operand" "=&w")
8108 (unspec:V2DI [(match_operand:V2DI 1 "s_register_operand" "w")
8109 (match_operand:SI 2 "immediate_operand" "i")]
8115 ops[0] = operands[0];
8116 ops[1] = operands[1];
8117 ops[2] = operands[2];
8118 output_asm_insn ("vldrd.64\t%q0, [%q1, %2]",ops);
8121 [(set_attr "length" "4")])
8124 ;; [vldrdq_gather_base_z_s vldrdq_gather_base_z_u]
8126 (define_insn "mve_vldrdq_gather_base_z_<supf>v2di"
8127 [(set (match_operand:V2DI 0 "s_register_operand" "=&w")
8128 (unspec:V2DI [(match_operand:V2DI 1 "s_register_operand" "w")
8129 (match_operand:SI 2 "immediate_operand" "i")
8130 (match_operand:HI 3 "vpr_register_operand" "Up")]
8136 ops[0] = operands[0];
8137 ops[1] = operands[1];
8138 ops[2] = operands[2];
8139 output_asm_insn ("vpst\n\tvldrdt.u64\t%q0, [%q1, %2]",ops);
8142 [(set_attr "length" "8")])
8145 ;; [vldrdq_gather_offset_s vldrdq_gather_offset_u]
8147 (define_insn "mve_vldrdq_gather_offset_<supf>v2di"
8148 [(set (match_operand:V2DI 0 "s_register_operand" "=&w")
8149 (unspec:V2DI [(match_operand:V2DI 1 "memory_operand" "Us")
8150 (match_operand:V2DI 2 "s_register_operand" "w")]
8156 ops[0] = operands[0];
8157 ops[1] = operands[1];
8158 ops[2] = operands[2];
8159 output_asm_insn ("vldrd.u64\t%q0, [%m1, %q2]",ops);
8162 [(set_attr "length" "4")])
8165 ;; [vldrdq_gather_offset_z_s vldrdq_gather_offset_z_u]
8167 (define_insn "mve_vldrdq_gather_offset_z_<supf>v2di"
8168 [(set (match_operand:V2DI 0 "s_register_operand" "=&w")
8169 (unspec:V2DI [(match_operand:V2DI 1 "memory_operand" "Us")
8170 (match_operand:V2DI 2 "s_register_operand" "w")
8171 (match_operand:HI 3 "vpr_register_operand" "Up")]
8177 ops[0] = operands[0];
8178 ops[1] = operands[1];
8179 ops[2] = operands[2];
8180 output_asm_insn ("vpst\n\tvldrdt.u64\t%q0, [%m1, %q2]",ops);
8183 [(set_attr "length" "8")])
8186 ;; [vldrdq_gather_shifted_offset_s vldrdq_gather_shifted_offset_u]
8188 (define_insn "mve_vldrdq_gather_shifted_offset_<supf>v2di"
8189 [(set (match_operand:V2DI 0 "s_register_operand" "=&w")
8190 (unspec:V2DI [(match_operand:V2DI 1 "memory_operand" "Us")
8191 (match_operand:V2DI 2 "s_register_operand" "w")]
8197 ops[0] = operands[0];
8198 ops[1] = operands[1];
8199 ops[2] = operands[2];
8200 output_asm_insn ("vldrd.u64\t%q0, [%m1, %q2, uxtw #3]",ops);
8203 [(set_attr "length" "4")])
8206 ;; [vldrdq_gather_shifted_offset_z_s vldrdq_gather_shifted_offset_z_u]
8208 (define_insn "mve_vldrdq_gather_shifted_offset_z_<supf>v2di"
8209 [(set (match_operand:V2DI 0 "s_register_operand" "=&w")
8210 (unspec:V2DI [(match_operand:V2DI 1 "memory_operand" "Us")
8211 (match_operand:V2DI 2 "s_register_operand" "w")
8212 (match_operand:HI 3 "vpr_register_operand" "Up")]
8218 ops[0] = operands[0];
8219 ops[1] = operands[1];
8220 ops[2] = operands[2];
8221 output_asm_insn ("vpst\n\tvldrdt.u64\t%q0, [%m1, %q2, uxtw #3]",ops);
8224 [(set_attr "length" "8")])
8227 ;; [vldrhq_gather_offset_f]
8229 (define_insn "mve_vldrhq_gather_offset_fv8hf"
8230 [(set (match_operand:V8HF 0 "s_register_operand" "=&w")
8231 (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us")
8232 (match_operand:V8HI 2 "s_register_operand" "w")]
8235 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8238 ops[0] = operands[0];
8239 ops[1] = operands[1];
8240 ops[2] = operands[2];
8241 output_asm_insn ("vldrh.f16\t%q0, [%m1, %q2]",ops);
8244 [(set_attr "length" "4")])
8247 ;; [vldrhq_gather_offset_z_f]
8249 (define_insn "mve_vldrhq_gather_offset_z_fv8hf"
8250 [(set (match_operand:V8HF 0 "s_register_operand" "=&w")
8251 (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us")
8252 (match_operand:V8HI 2 "s_register_operand" "w")
8253 (match_operand:HI 3 "vpr_register_operand" "Up")]
8256 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8259 ops[0] = operands[0];
8260 ops[1] = operands[1];
8261 ops[2] = operands[2];
8262 ops[3] = operands[3];
8263 output_asm_insn ("vpst\n\tvldrht.f16\t%q0, [%m1, %q2]",ops);
8266 [(set_attr "length" "8")])
8269 ;; [vldrhq_gather_shifted_offset_f]
8271 (define_insn "mve_vldrhq_gather_shifted_offset_fv8hf"
8272 [(set (match_operand:V8HF 0 "s_register_operand" "=&w")
8273 (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us")
8274 (match_operand:V8HI 2 "s_register_operand" "w")]
8277 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8280 ops[0] = operands[0];
8281 ops[1] = operands[1];
8282 ops[2] = operands[2];
8283 output_asm_insn ("vldrh.f16\t%q0, [%m1, %q2, uxtw #1]",ops);
8286 [(set_attr "length" "4")])
8289 ;; [vldrhq_gather_shifted_offset_z_f]
8291 (define_insn "mve_vldrhq_gather_shifted_offset_z_fv8hf"
8292 [(set (match_operand:V8HF 0 "s_register_operand" "=&w")
8293 (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us")
8294 (match_operand:V8HI 2 "s_register_operand" "w")
8295 (match_operand:HI 3 "vpr_register_operand" "Up")]
8298 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8301 ops[0] = operands[0];
8302 ops[1] = operands[1];
8303 ops[2] = operands[2];
8304 ops[3] = operands[3];
8305 output_asm_insn ("vpst\n\tvldrht.f16\t%q0, [%m1, %q2, uxtw #1]",ops);
8308 [(set_attr "length" "8")])
8311 ;; [vldrwq_gather_base_f]
8313 (define_insn "mve_vldrwq_gather_base_fv4sf"
8314 [(set (match_operand:V4SF 0 "s_register_operand" "=&w")
8315 (unspec:V4SF [(match_operand:V4SI 1 "s_register_operand" "w")
8316 (match_operand:SI 2 "immediate_operand" "i")]
8319 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8322 ops[0] = operands[0];
8323 ops[1] = operands[1];
8324 ops[2] = operands[2];
8325 output_asm_insn ("vldrw.u32\t%q0, [%q1, %2]",ops);
8328 [(set_attr "length" "4")])
8331 ;; [vldrwq_gather_base_z_f]
8333 (define_insn "mve_vldrwq_gather_base_z_fv4sf"
8334 [(set (match_operand:V4SF 0 "s_register_operand" "=&w")
8335 (unspec:V4SF [(match_operand:V4SI 1 "s_register_operand" "w")
8336 (match_operand:SI 2 "immediate_operand" "i")
8337 (match_operand:HI 3 "vpr_register_operand" "Up")]
8340 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8343 ops[0] = operands[0];
8344 ops[1] = operands[1];
8345 ops[2] = operands[2];
8346 output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%q1, %2]",ops);
8349 [(set_attr "length" "8")])
8352 ;; [vldrwq_gather_offset_f]
8354 (define_insn "mve_vldrwq_gather_offset_fv4sf"
8355 [(set (match_operand:V4SF 0 "s_register_operand" "=&w")
8356 (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us")
8357 (match_operand:V4SI 2 "s_register_operand" "w")]
8360 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8363 ops[0] = operands[0];
8364 ops[1] = operands[1];
8365 ops[2] = operands[2];
8366 output_asm_insn ("vldrw.u32\t%q0, [%m1, %q2]",ops);
8369 [(set_attr "length" "4")])
8372 ;; [vldrwq_gather_offset_s vldrwq_gather_offset_u]
8374 (define_insn "mve_vldrwq_gather_offset_<supf>v4si"
8375 [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
8376 (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us")
8377 (match_operand:V4SI 2 "s_register_operand" "w")]
8383 ops[0] = operands[0];
8384 ops[1] = operands[1];
8385 ops[2] = operands[2];
8386 output_asm_insn ("vldrw.u32\t%q0, [%m1, %q2]",ops);
8389 [(set_attr "length" "4")])
8392 ;; [vldrwq_gather_offset_z_f]
8394 (define_insn "mve_vldrwq_gather_offset_z_fv4sf"
8395 [(set (match_operand:V4SF 0 "s_register_operand" "=&w")
8396 (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us")
8397 (match_operand:V4SI 2 "s_register_operand" "w")
8398 (match_operand:HI 3 "vpr_register_operand" "Up")]
8401 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8404 ops[0] = operands[0];
8405 ops[1] = operands[1];
8406 ops[2] = operands[2];
8407 ops[3] = operands[3];
8408 output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%m1, %q2]",ops);
8411 [(set_attr "length" "8")])
8414 ;; [vldrwq_gather_offset_z_s vldrwq_gather_offset_z_u]
8416 (define_insn "mve_vldrwq_gather_offset_z_<supf>v4si"
8417 [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
8418 (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us")
8419 (match_operand:V4SI 2 "s_register_operand" "w")
8420 (match_operand:HI 3 "vpr_register_operand" "Up")]
8426 ops[0] = operands[0];
8427 ops[1] = operands[1];
8428 ops[2] = operands[2];
8429 ops[3] = operands[3];
8430 output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%m1, %q2]",ops);
8433 [(set_attr "length" "8")])
8436 ;; [vldrwq_gather_shifted_offset_f]
8438 (define_insn "mve_vldrwq_gather_shifted_offset_fv4sf"
8439 [(set (match_operand:V4SF 0 "s_register_operand" "=&w")
8440 (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us")
8441 (match_operand:V4SI 2 "s_register_operand" "w")]
8444 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8447 ops[0] = operands[0];
8448 ops[1] = operands[1];
8449 ops[2] = operands[2];
8450 output_asm_insn ("vldrw.u32\t%q0, [%m1, %q2, uxtw #2]",ops);
8453 [(set_attr "length" "4")])
8456 ;; [vldrwq_gather_shifted_offset_s vldrwq_gather_shifted_offset_u]
8458 (define_insn "mve_vldrwq_gather_shifted_offset_<supf>v4si"
8459 [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
8460 (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us")
8461 (match_operand:V4SI 2 "s_register_operand" "w")]
8467 ops[0] = operands[0];
8468 ops[1] = operands[1];
8469 ops[2] = operands[2];
8470 output_asm_insn ("vldrw.u32\t%q0, [%m1, %q2, uxtw #2]",ops);
8473 [(set_attr "length" "4")])
8476 ;; [vldrwq_gather_shifted_offset_z_f]
8478 (define_insn "mve_vldrwq_gather_shifted_offset_z_fv4sf"
8479 [(set (match_operand:V4SF 0 "s_register_operand" "=&w")
8480 (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us")
8481 (match_operand:V4SI 2 "s_register_operand" "w")
8482 (match_operand:HI 3 "vpr_register_operand" "Up")]
8485 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8488 ops[0] = operands[0];
8489 ops[1] = operands[1];
8490 ops[2] = operands[2];
8491 ops[3] = operands[3];
8492 output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%m1, %q2, uxtw #2]",ops);
8495 [(set_attr "length" "8")])
8498 ;; [vldrwq_gather_shifted_offset_z_s vldrwq_gather_shifted_offset_z_u]
8500 (define_insn "mve_vldrwq_gather_shifted_offset_z_<supf>v4si"
8501 [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
8502 (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us")
8503 (match_operand:V4SI 2 "s_register_operand" "w")
8504 (match_operand:HI 3 "vpr_register_operand" "Up")]
8510 ops[0] = operands[0];
8511 ops[1] = operands[1];
8512 ops[2] = operands[2];
8513 ops[3] = operands[3];
8514 output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%m1, %q2, uxtw #2]",ops);
8517 [(set_attr "length" "8")])
8522 (define_insn "mve_vstrhq_fv8hf"
8523 [(set (match_operand:V8HI 0 "mve_memory_operand" "=Ux")
8524 (unspec:V8HI [(match_operand:V8HF 1 "s_register_operand" "w")]
8527 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8530 int regno = REGNO (operands[1]);
8531 ops[1] = gen_rtx_REG (TImode, regno);
8532 ops[0] = operands[0];
8533 output_asm_insn ("vstrh.16\t%q1, %E0",ops);
8536 [(set_attr "length" "4")])
8541 (define_insn "mve_vstrhq_p_fv8hf"
8542 [(set (match_operand:V8HI 0 "mve_memory_operand" "=Ux")
8543 (unspec:V8HI [(match_operand:V8HF 1 "s_register_operand" "w")
8544 (match_operand:HI 2 "vpr_register_operand" "Up")]
8547 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8550 int regno = REGNO (operands[1]);
8551 ops[1] = gen_rtx_REG (TImode, regno);
8552 ops[0] = operands[0];
8553 output_asm_insn ("vpst\;vstrht.16\t%q1, %E0",ops);
8556 [(set_attr "length" "8")])
8559 ;; [vstrhq_p_s vstrhq_p_u]
8561 (define_insn "mve_vstrhq_p_<supf><mode>"
8562 [(set (match_operand:<MVE_H_ELEM> 0 "mve_memory_operand" "=Ux")
8563 (unspec:<MVE_H_ELEM> [(match_operand:MVE_6 1 "s_register_operand" "w")
8564 (match_operand:HI 2 "vpr_register_operand" "Up")]
8570 int regno = REGNO (operands[1]);
8571 ops[1] = gen_rtx_REG (TImode, regno);
8572 ops[0] = operands[0];
8573 output_asm_insn ("vpst\;vstrht.<V_sz_elem>\t%q1, %E0",ops);
8576 [(set_attr "length" "8")])
8579 ;; [vstrhq_scatter_offset_p_s vstrhq_scatter_offset_p_u]
8581 (define_expand "mve_vstrhq_scatter_offset_p_<supf><mode>"
8582 [(match_operand:<MVE_H_ELEM> 0 "mve_scatter_memory")
8583 (match_operand:MVE_6 1 "s_register_operand")
8584 (match_operand:MVE_6 2 "s_register_operand")
8585 (match_operand:HI 3 "vpr_register_operand")
8586 (unspec:V4SI [(const_int 0)] VSTRHSOQ)]
8589 rtx ind = XEXP (operands[0], 0);
8590 gcc_assert (REG_P (ind));
8592 gen_mve_vstrhq_scatter_offset_p_<supf><mode>_insn (ind, operands[1],
8598 (define_insn "mve_vstrhq_scatter_offset_p_<supf><mode>_insn"
8599 [(set (mem:BLK (scratch))
8601 [(match_operand:SI 0 "register_operand" "r")
8602 (match_operand:MVE_6 1 "s_register_operand" "w")
8603 (match_operand:MVE_6 2 "s_register_operand" "w")
8604 (match_operand:HI 3 "vpr_register_operand" "Up")]
8607 "vpst\;vstrht.<V_sz_elem>\t%q2, [%0, %q1]"
8608 [(set_attr "length" "8")])
8611 ;; [vstrhq_scatter_offset_s vstrhq_scatter_offset_u]
8613 (define_expand "mve_vstrhq_scatter_offset_<supf><mode>"
8614 [(match_operand:<MVE_H_ELEM> 0 "mve_scatter_memory")
8615 (match_operand:MVE_6 1 "s_register_operand")
8616 (match_operand:MVE_6 2 "s_register_operand")
8617 (unspec:V4SI [(const_int 0)] VSTRHSOQ)]
8620 rtx ind = XEXP (operands[0], 0);
8621 gcc_assert (REG_P (ind));
8622 emit_insn (gen_mve_vstrhq_scatter_offset_<supf><mode>_insn (ind, operands[1],
8627 (define_insn "mve_vstrhq_scatter_offset_<supf><mode>_insn"
8628 [(set (mem:BLK (scratch))
8630 [(match_operand:SI 0 "register_operand" "r")
8631 (match_operand:MVE_6 1 "s_register_operand" "w")
8632 (match_operand:MVE_6 2 "s_register_operand" "w")]
8635 "vstrh.<V_sz_elem>\t%q2, [%0, %q1]"
8636 [(set_attr "length" "4")])
8639 ;; [vstrhq_scatter_shifted_offset_p_s vstrhq_scatter_shifted_offset_p_u]
8641 (define_expand "mve_vstrhq_scatter_shifted_offset_p_<supf><mode>"
8642 [(match_operand:<MVE_H_ELEM> 0 "mve_scatter_memory")
8643 (match_operand:MVE_6 1 "s_register_operand")
8644 (match_operand:MVE_6 2 "s_register_operand")
8645 (match_operand:HI 3 "vpr_register_operand")
8646 (unspec:V4SI [(const_int 0)] VSTRHSSOQ)]
8649 rtx ind = XEXP (operands[0], 0);
8650 gcc_assert (REG_P (ind));
8652 gen_mve_vstrhq_scatter_shifted_offset_p_<supf><mode>_insn (ind, operands[1],
8658 (define_insn "mve_vstrhq_scatter_shifted_offset_p_<supf><mode>_insn"
8659 [(set (mem:BLK (scratch))
8661 [(match_operand:SI 0 "register_operand" "r")
8662 (match_operand:MVE_6 1 "s_register_operand" "w")
8663 (match_operand:MVE_6 2 "s_register_operand" "w")
8664 (match_operand:HI 3 "vpr_register_operand" "Up")]
8667 "vpst\;vstrht.<V_sz_elem>\t%q2, [%0, %q1, uxtw #1]"
8668 [(set_attr "length" "8")])
8671 ;; [vstrhq_scatter_shifted_offset_s vstrhq_scatter_shifted_offset_u]
8673 (define_expand "mve_vstrhq_scatter_shifted_offset_<supf><mode>"
8674 [(match_operand:<MVE_H_ELEM> 0 "mve_scatter_memory")
8675 (match_operand:MVE_6 1 "s_register_operand")
8676 (match_operand:MVE_6 2 "s_register_operand")
8677 (unspec:V4SI [(const_int 0)] VSTRHSSOQ)]
8680 rtx ind = XEXP (operands[0], 0);
8681 gcc_assert (REG_P (ind));
8683 gen_mve_vstrhq_scatter_shifted_offset_<supf><mode>_insn (ind, operands[1],
8688 (define_insn "mve_vstrhq_scatter_shifted_offset_<supf><mode>_insn"
8689 [(set (mem:BLK (scratch))
8691 [(match_operand:SI 0 "register_operand" "r")
8692 (match_operand:MVE_6 1 "s_register_operand" "w")
8693 (match_operand:MVE_6 2 "s_register_operand" "w")]
8696 "vstrh.<V_sz_elem>\t%q2, [%0, %q1, uxtw #1]"
8697 [(set_attr "length" "4")])
8700 ;; [vstrhq_s, vstrhq_u]
8702 (define_insn "mve_vstrhq_<supf><mode>"
8703 [(set (match_operand:<MVE_H_ELEM> 0 "mve_memory_operand" "=Ux")
8704 (unspec:<MVE_H_ELEM> [(match_operand:MVE_6 1 "s_register_operand" "w")]
8710 int regno = REGNO (operands[1]);
8711 ops[1] = gen_rtx_REG (TImode, regno);
8712 ops[0] = operands[0];
8713 output_asm_insn ("vstrh.<V_sz_elem>\t%q1, %E0",ops);
8716 [(set_attr "length" "4")])
8721 (define_insn "mve_vstrwq_fv4sf"
8722 [(set (match_operand:V4SI 0 "memory_operand" "=Ux")
8723 (unspec:V4SI [(match_operand:V4SF 1 "s_register_operand" "w")]
8726 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8729 int regno = REGNO (operands[1]);
8730 ops[1] = gen_rtx_REG (TImode, regno);
8731 ops[0] = operands[0];
8732 output_asm_insn ("vstrw.32\t%q1, %E0",ops);
8735 [(set_attr "length" "4")])
8740 (define_insn "mve_vstrwq_p_fv4sf"
8741 [(set (match_operand:V4SI 0 "memory_operand" "=Ux")
8742 (unspec:V4SI [(match_operand:V4SF 1 "s_register_operand" "w")
8743 (match_operand:HI 2 "vpr_register_operand" "Up")]
8746 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8749 int regno = REGNO (operands[1]);
8750 ops[1] = gen_rtx_REG (TImode, regno);
8751 ops[0] = operands[0];
8752 output_asm_insn ("vpst\;vstrwt.32\t%q1, %E0",ops);
8755 [(set_attr "length" "8")])
8758 ;; [vstrwq_p_s vstrwq_p_u]
8760 (define_insn "mve_vstrwq_p_<supf>v4si"
8761 [(set (match_operand:V4SI 0 "memory_operand" "=Ux")
8762 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
8763 (match_operand:HI 2 "vpr_register_operand" "Up")]
8769 int regno = REGNO (operands[1]);
8770 ops[1] = gen_rtx_REG (TImode, regno);
8771 ops[0] = operands[0];
8772 output_asm_insn ("vpst\;vstrwt.32\t%q1, %E0",ops);
8775 [(set_attr "length" "8")])
8778 ;; [vstrwq_s vstrwq_u]
8780 (define_insn "mve_vstrwq_<supf>v4si"
8781 [(set (match_operand:V4SI 0 "memory_operand" "=Ux")
8782 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")]
8788 int regno = REGNO (operands[1]);
8789 ops[1] = gen_rtx_REG (TImode, regno);
8790 ops[0] = operands[0];
8791 output_asm_insn ("vstrw.32\t%q1, %E0",ops);
8794 [(set_attr "length" "4")])
8796 (define_expand "mve_vst1q_f<mode>"
8797 [(match_operand:<MVE_CNVT> 0 "mve_memory_operand")
8798 (unspec:<MVE_CNVT> [(match_operand:MVE_0 1 "s_register_operand")] VST1Q_F)
8800 "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT"
8802 emit_insn (gen_mve_vstr<V_sz_elem1>q_f<mode>(operands[0],operands[1]));
8806 (define_expand "mve_vst1q_<supf><mode>"
8807 [(match_operand:MVE_2 0 "mve_memory_operand")
8808 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand")] VST1Q)
8812 emit_insn (gen_mve_vstr<V_sz_elem1>q_<supf><mode>(operands[0],operands[1]));
8817 ;; [vstrdq_scatter_base_p_s vstrdq_scatter_base_p_u]
8819 (define_insn "mve_vstrdq_scatter_base_p_<supf>v2di"
8820 [(set (mem:BLK (scratch))
8822 [(match_operand:V2DI 0 "s_register_operand" "w")
8823 (match_operand:SI 1 "mve_vldrd_immediate" "Ri")
8824 (match_operand:V2DI 2 "s_register_operand" "w")
8825 (match_operand:HI 3 "vpr_register_operand" "Up")]
8831 ops[0] = operands[0];
8832 ops[1] = operands[1];
8833 ops[2] = operands[2];
8834 output_asm_insn ("vpst\;\tvstrdt.u64\t%q2, [%q0, %1]",ops);
8837 [(set_attr "length" "8")])
8840 ;; [vstrdq_scatter_base_s vstrdq_scatter_base_u]
8842 (define_insn "mve_vstrdq_scatter_base_<supf>v2di"
8843 [(set (mem:BLK (scratch))
8845 [(match_operand:V2DI 0 "s_register_operand" "=w")
8846 (match_operand:SI 1 "mve_vldrd_immediate" "Ri")
8847 (match_operand:V2DI 2 "s_register_operand" "w")]
8853 ops[0] = operands[0];
8854 ops[1] = operands[1];
8855 ops[2] = operands[2];
8856 output_asm_insn ("vstrd.u64\t%q2, [%q0, %1]",ops);
8859 [(set_attr "length" "4")])
8862 ;; [vstrdq_scatter_offset_p_s vstrdq_scatter_offset_p_u]
8864 (define_expand "mve_vstrdq_scatter_offset_p_<supf>v2di"
8865 [(match_operand:V2DI 0 "mve_scatter_memory")
8866 (match_operand:V2DI 1 "s_register_operand")
8867 (match_operand:V2DI 2 "s_register_operand")
8868 (match_operand:HI 3 "vpr_register_operand")
8869 (unspec:V4SI [(const_int 0)] VSTRDSOQ)]
8872 rtx ind = XEXP (operands[0], 0);
8873 gcc_assert (REG_P (ind));
8874 emit_insn (gen_mve_vstrdq_scatter_offset_p_<supf>v2di_insn (ind, operands[1],
8880 (define_insn "mve_vstrdq_scatter_offset_p_<supf>v2di_insn"
8881 [(set (mem:BLK (scratch))
8883 [(match_operand:SI 0 "register_operand" "r")
8884 (match_operand:V2DI 1 "s_register_operand" "w")
8885 (match_operand:V2DI 2 "s_register_operand" "w")
8886 (match_operand:HI 3 "vpr_register_operand" "Up")]
8889 "vpst\;vstrdt.64\t%q2, [%0, %q1]"
8890 [(set_attr "length" "8")])
8893 ;; [vstrdq_scatter_offset_s vstrdq_scatter_offset_u]
8895 (define_expand "mve_vstrdq_scatter_offset_<supf>v2di"
8896 [(match_operand:V2DI 0 "mve_scatter_memory")
8897 (match_operand:V2DI 1 "s_register_operand")
8898 (match_operand:V2DI 2 "s_register_operand")
8899 (unspec:V4SI [(const_int 0)] VSTRDSOQ)]
8902 rtx ind = XEXP (operands[0], 0);
8903 gcc_assert (REG_P (ind));
8904 emit_insn (gen_mve_vstrdq_scatter_offset_<supf>v2di_insn (ind, operands[1],
8909 (define_insn "mve_vstrdq_scatter_offset_<supf>v2di_insn"
8910 [(set (mem:BLK (scratch))
8912 [(match_operand:SI 0 "register_operand" "r")
8913 (match_operand:V2DI 1 "s_register_operand" "w")
8914 (match_operand:V2DI 2 "s_register_operand" "w")]
8917 "vstrd.64\t%q2, [%0, %q1]"
8918 [(set_attr "length" "4")])
8921 ;; [vstrdq_scatter_shifted_offset_p_s vstrdq_scatter_shifted_offset_p_u]
8923 (define_expand "mve_vstrdq_scatter_shifted_offset_p_<supf>v2di"
8924 [(match_operand:V2DI 0 "mve_scatter_memory")
8925 (match_operand:V2DI 1 "s_register_operand")
8926 (match_operand:V2DI 2 "s_register_operand")
8927 (match_operand:HI 3 "vpr_register_operand")
8928 (unspec:V4SI [(const_int 0)] VSTRDSSOQ)]
8931 rtx ind = XEXP (operands[0], 0);
8932 gcc_assert (REG_P (ind));
8934 gen_mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn (ind, operands[1],
8940 (define_insn "mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn"
8941 [(set (mem:BLK (scratch))
8943 [(match_operand:SI 0 "register_operand" "r")
8944 (match_operand:V2DI 1 "s_register_operand" "w")
8945 (match_operand:V2DI 2 "s_register_operand" "w")
8946 (match_operand:HI 3 "vpr_register_operand" "Up")]
8949 "vpst\;vstrdt.64\t%q2, [%0, %q1, UXTW #3]"
8950 [(set_attr "length" "8")])
8953 ;; [vstrdq_scatter_shifted_offset_s vstrdq_scatter_shifted_offset_u]
8955 (define_expand "mve_vstrdq_scatter_shifted_offset_<supf>v2di"
8956 [(match_operand:V2DI 0 "mve_scatter_memory")
8957 (match_operand:V2DI 1 "s_register_operand")
8958 (match_operand:V2DI 2 "s_register_operand")
8959 (unspec:V4SI [(const_int 0)] VSTRDSSOQ)]
8962 rtx ind = XEXP (operands[0], 0);
8963 gcc_assert (REG_P (ind));
8965 gen_mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn (ind, operands[1],
8970 (define_insn "mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn"
8971 [(set (mem:BLK (scratch))
8973 [(match_operand:SI 0 "register_operand" "r")
8974 (match_operand:V2DI 1 "s_register_operand" "w")
8975 (match_operand:V2DI 2 "s_register_operand" "w")]
8978 "vstrd.64\t%q2, [%0, %q1, UXTW #3]"
8979 [(set_attr "length" "4")])
8982 ;; [vstrhq_scatter_offset_f]
8984 (define_expand "mve_vstrhq_scatter_offset_fv8hf"
8985 [(match_operand:V8HI 0 "mve_scatter_memory")
8986 (match_operand:V8HI 1 "s_register_operand")
8987 (match_operand:V8HF 2 "s_register_operand")
8988 (unspec:V4SI [(const_int 0)] VSTRHQSO_F)]
8989 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8991 rtx ind = XEXP (operands[0], 0);
8992 gcc_assert (REG_P (ind));
8993 emit_insn (gen_mve_vstrhq_scatter_offset_fv8hf_insn (ind, operands[1],
8998 (define_insn "mve_vstrhq_scatter_offset_fv8hf_insn"
8999 [(set (mem:BLK (scratch))
9001 [(match_operand:SI 0 "register_operand" "r")
9002 (match_operand:V8HI 1 "s_register_operand" "w")
9003 (match_operand:V8HF 2 "s_register_operand" "w")]
9005 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
9006 "vstrh.16\t%q2, [%0, %q1]"
9007 [(set_attr "length" "4")])
9010 ;; [vstrhq_scatter_offset_p_f]
9012 (define_expand "mve_vstrhq_scatter_offset_p_fv8hf"
9013 [(match_operand:V8HI 0 "mve_scatter_memory")
9014 (match_operand:V8HI 1 "s_register_operand")
9015 (match_operand:V8HF 2 "s_register_operand")
9016 (match_operand:HI 3 "vpr_register_operand")
9017 (unspec:V4SI [(const_int 0)] VSTRHQSO_F)]
9018 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
9020 rtx ind = XEXP (operands[0], 0);
9021 gcc_assert (REG_P (ind));
9022 emit_insn (gen_mve_vstrhq_scatter_offset_p_fv8hf_insn (ind, operands[1],
9028 (define_insn "mve_vstrhq_scatter_offset_p_fv8hf_insn"
9029 [(set (mem:BLK (scratch))
9031 [(match_operand:SI 0 "register_operand" "r")
9032 (match_operand:V8HI 1 "s_register_operand" "w")
9033 (match_operand:V8HF 2 "s_register_operand" "w")
9034 (match_operand:HI 3 "vpr_register_operand" "Up")]
9036 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
9037 "vpst\;vstrht.16\t%q2, [%0, %q1]"
9038 [(set_attr "length" "8")])
9041 ;; [vstrhq_scatter_shifted_offset_f]
9043 (define_expand "mve_vstrhq_scatter_shifted_offset_fv8hf"
9044 [(match_operand:V8HI 0 "memory_operand" "=Us")
9045 (match_operand:V8HI 1 "s_register_operand" "w")
9046 (match_operand:V8HF 2 "s_register_operand" "w")
9047 (unspec:V4SI [(const_int 0)] VSTRHQSSO_F)]
9048 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
9050 rtx ind = XEXP (operands[0], 0);
9051 gcc_assert (REG_P (ind));
9052 emit_insn (gen_mve_vstrhq_scatter_shifted_offset_fv8hf_insn (ind, operands[1],
9057 (define_insn "mve_vstrhq_scatter_shifted_offset_fv8hf_insn"
9058 [(set (mem:BLK (scratch))
9060 [(match_operand:SI 0 "register_operand" "r")
9061 (match_operand:V8HI 1 "s_register_operand" "w")
9062 (match_operand:V8HF 2 "s_register_operand" "w")]
9064 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
9065 "vstrh.16\t%q2, [%0, %q1, uxtw #1]"
9066 [(set_attr "length" "4")])
9069 ;; [vstrhq_scatter_shifted_offset_p_f]
9071 (define_expand "mve_vstrhq_scatter_shifted_offset_p_fv8hf"
9072 [(match_operand:V8HI 0 "memory_operand" "=Us")
9073 (match_operand:V8HI 1 "s_register_operand" "w")
9074 (match_operand:V8HF 2 "s_register_operand" "w")
9075 (match_operand:HI 3 "vpr_register_operand" "Up")
9076 (unspec:V4SI [(const_int 0)] VSTRHQSSO_F)]
9077 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
9079 rtx ind = XEXP (operands[0], 0);
9080 gcc_assert (REG_P (ind));
9082 gen_mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn (ind, operands[1],
9088 (define_insn "mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn"
9089 [(set (mem:BLK (scratch))
9091 [(match_operand:SI 0 "register_operand" "r")
9092 (match_operand:V8HI 1 "s_register_operand" "w")
9093 (match_operand:V8HF 2 "s_register_operand" "w")
9094 (match_operand:HI 3 "vpr_register_operand" "Up")]
9096 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
9097 "vpst\;vstrht.16\t%q2, [%0, %q1, uxtw #1]"
9098 [(set_attr "length" "8")])
9101 ;; [vstrwq_scatter_base_f]
9103 (define_insn "mve_vstrwq_scatter_base_fv4sf"
9104 [(set (mem:BLK (scratch))
9106 [(match_operand:V4SI 0 "s_register_operand" "w")
9107 (match_operand:SI 1 "immediate_operand" "i")
9108 (match_operand:V4SF 2 "s_register_operand" "w")]
9111 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
9114 ops[0] = operands[0];
9115 ops[1] = operands[1];
9116 ops[2] = operands[2];
9117 output_asm_insn ("vstrw.u32\t%q2, [%q0, %1]",ops);
9120 [(set_attr "length" "4")])
9123 ;; [vstrwq_scatter_base_p_f]
9125 (define_insn "mve_vstrwq_scatter_base_p_fv4sf"
9126 [(set (mem:BLK (scratch))
9128 [(match_operand:V4SI 0 "s_register_operand" "w")
9129 (match_operand:SI 1 "immediate_operand" "i")
9130 (match_operand:V4SF 2 "s_register_operand" "w")
9131 (match_operand:HI 3 "vpr_register_operand" "Up")]
9134 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
9137 ops[0] = operands[0];
9138 ops[1] = operands[1];
9139 ops[2] = operands[2];
9140 output_asm_insn ("vpst\n\tvstrwt.u32\t%q2, [%q0, %1]",ops);
9143 [(set_attr "length" "8")])
9146 ;; [vstrwq_scatter_offset_f]
9148 (define_expand "mve_vstrwq_scatter_offset_fv4sf"
9149 [(match_operand:V4SI 0 "mve_scatter_memory")
9150 (match_operand:V4SI 1 "s_register_operand")
9151 (match_operand:V4SF 2 "s_register_operand")
9152 (unspec:V4SI [(const_int 0)] VSTRWQSO_F)]
9153 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
9155 rtx ind = XEXP (operands[0], 0);
9156 gcc_assert (REG_P (ind));
9157 emit_insn (gen_mve_vstrwq_scatter_offset_fv4sf_insn (ind, operands[1],
9162 (define_insn "mve_vstrwq_scatter_offset_fv4sf_insn"
9163 [(set (mem:BLK (scratch))
9165 [(match_operand:SI 0 "register_operand" "r")
9166 (match_operand:V4SI 1 "s_register_operand" "w")
9167 (match_operand:V4SF 2 "s_register_operand" "w")]
9169 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
9170 "vstrw.32\t%q2, [%0, %q1]"
9171 [(set_attr "length" "4")])
9174 ;; [vstrwq_scatter_offset_p_f]
9176 (define_expand "mve_vstrwq_scatter_offset_p_fv4sf"
9177 [(match_operand:V4SI 0 "mve_scatter_memory")
9178 (match_operand:V4SI 1 "s_register_operand")
9179 (match_operand:V4SF 2 "s_register_operand")
9180 (match_operand:HI 3 "vpr_register_operand")
9181 (unspec:V4SI [(const_int 0)] VSTRWQSO_F)]
9182 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
9184 rtx ind = XEXP (operands[0], 0);
9185 gcc_assert (REG_P (ind));
9186 emit_insn (gen_mve_vstrwq_scatter_offset_p_fv4sf_insn (ind, operands[1],
9192 (define_insn "mve_vstrwq_scatter_offset_p_fv4sf_insn"
9193 [(set (mem:BLK (scratch))
9195 [(match_operand:SI 0 "register_operand" "r")
9196 (match_operand:V4SI 1 "s_register_operand" "w")
9197 (match_operand:V4SF 2 "s_register_operand" "w")
9198 (match_operand:HI 3 "vpr_register_operand" "Up")]
9200 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
9201 "vpst\;vstrwt.32\t%q2, [%0, %q1]"
9202 [(set_attr "length" "8")])
9205 ;; [vstrwq_scatter_offset_s vstrwq_scatter_offset_u]
9207 (define_expand "mve_vstrwq_scatter_offset_p_<supf>v4si"
9208 [(match_operand:V4SI 0 "mve_scatter_memory")
9209 (match_operand:V4SI 1 "s_register_operand")
9210 (match_operand:V4SI 2 "s_register_operand")
9211 (match_operand:HI 3 "vpr_register_operand")
9212 (unspec:V4SI [(const_int 0)] VSTRWSOQ)]
9215 rtx ind = XEXP (operands[0], 0);
9216 gcc_assert (REG_P (ind));
9217 emit_insn (gen_mve_vstrwq_scatter_offset_p_<supf>v4si_insn (ind, operands[1],
9223 (define_insn "mve_vstrwq_scatter_offset_p_<supf>v4si_insn"
9224 [(set (mem:BLK (scratch))
9226 [(match_operand:SI 0 "register_operand" "r")
9227 (match_operand:V4SI 1 "s_register_operand" "w")
9228 (match_operand:V4SI 2 "s_register_operand" "w")
9229 (match_operand:HI 3 "vpr_register_operand" "Up")]
9232 "vpst\;vstrwt.32\t%q2, [%0, %q1]"
9233 [(set_attr "length" "8")])
9236 ;; [vstrwq_scatter_offset_s vstrwq_scatter_offset_u]
9238 (define_expand "mve_vstrwq_scatter_offset_<supf>v4si"
9239 [(match_operand:V4SI 0 "mve_scatter_memory")
9240 (match_operand:V4SI 1 "s_register_operand")
9241 (match_operand:V4SI 2 "s_register_operand")
9242 (unspec:V4SI [(const_int 0)] VSTRWSOQ)]
9245 rtx ind = XEXP (operands[0], 0);
9246 gcc_assert (REG_P (ind));
9247 emit_insn (gen_mve_vstrwq_scatter_offset_<supf>v4si_insn (ind, operands[1],
9252 (define_insn "mve_vstrwq_scatter_offset_<supf>v4si_insn"
9253 [(set (mem:BLK (scratch))
9255 [(match_operand:SI 0 "register_operand" "r")
9256 (match_operand:V4SI 1 "s_register_operand" "w")
9257 (match_operand:V4SI 2 "s_register_operand" "w")]
9260 "vstrw.32\t%q2, [%0, %q1]"
9261 [(set_attr "length" "4")])
9264 ;; [vstrwq_scatter_shifted_offset_f]
9266 (define_expand "mve_vstrwq_scatter_shifted_offset_fv4sf"
9267 [(match_operand:V4SI 0 "mve_scatter_memory")
9268 (match_operand:V4SI 1 "s_register_operand")
9269 (match_operand:V4SF 2 "s_register_operand")
9270 (unspec:V4SI [(const_int 0)] VSTRWQSSO_F)]
9271 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
9273 rtx ind = XEXP (operands[0], 0);
9274 gcc_assert (REG_P (ind));
9275 emit_insn (gen_mve_vstrwq_scatter_shifted_offset_fv4sf_insn (ind, operands[1],
9280 (define_insn "mve_vstrwq_scatter_shifted_offset_fv4sf_insn"
9281 [(set (mem:BLK (scratch))
9283 [(match_operand:SI 0 "register_operand" "r")
9284 (match_operand:V4SI 1 "s_register_operand" "w")
9285 (match_operand:V4SF 2 "s_register_operand" "w")]
9287 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
9288 "vstrw.32\t%q2, [%0, %q1, uxtw #2]"
9289 [(set_attr "length" "8")])
9292 ;; [vstrwq_scatter_shifted_offset_p_f]
9294 (define_expand "mve_vstrwq_scatter_shifted_offset_p_fv4sf"
9295 [(match_operand:V4SI 0 "mve_scatter_memory")
9296 (match_operand:V4SI 1 "s_register_operand")
9297 (match_operand:V4SF 2 "s_register_operand")
9298 (match_operand:HI 3 "vpr_register_operand")
9299 (unspec:V4SI [(const_int 0)] VSTRWQSSO_F)]
9300 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
9302 rtx ind = XEXP (operands[0], 0);
9303 gcc_assert (REG_P (ind));
9305 gen_mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn (ind, operands[1],
9311 (define_insn "mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn"
9312 [(set (mem:BLK (scratch))
9314 [(match_operand:SI 0 "register_operand" "r")
9315 (match_operand:V4SI 1 "s_register_operand" "w")
9316 (match_operand:V4SF 2 "s_register_operand" "w")
9317 (match_operand:HI 3 "vpr_register_operand" "Up")]
9319 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
9320 "vpst\;vstrwt.32\t%q2, [%0, %q1, uxtw #2]"
9321 [(set_attr "length" "8")])
9324 ;; [vstrwq_scatter_shifted_offset_p_s vstrwq_scatter_shifted_offset_p_u]
9326 (define_expand "mve_vstrwq_scatter_shifted_offset_p_<supf>v4si"
9327 [(match_operand:V4SI 0 "mve_scatter_memory")
9328 (match_operand:V4SI 1 "s_register_operand")
9329 (match_operand:V4SI 2 "s_register_operand")
9330 (match_operand:HI 3 "vpr_register_operand")
9331 (unspec:V4SI [(const_int 0)] VSTRWSSOQ)]
9334 rtx ind = XEXP (operands[0], 0);
9335 gcc_assert (REG_P (ind));
9337 gen_mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn (ind, operands[1],
9343 (define_insn "mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn"
9344 [(set (mem:BLK (scratch))
9346 [(match_operand:SI 0 "register_operand" "r")
9347 (match_operand:V4SI 1 "s_register_operand" "w")
9348 (match_operand:V4SI 2 "s_register_operand" "w")
9349 (match_operand:HI 3 "vpr_register_operand" "Up")]
9352 "vpst\;vstrwt.32\t%q2, [%0, %q1, uxtw #2]"
9353 [(set_attr "length" "8")])
9356 ;; [vstrwq_scatter_shifted_offset_s vstrwq_scatter_shifted_offset_u]
9358 (define_expand "mve_vstrwq_scatter_shifted_offset_<supf>v4si"
9359 [(match_operand:V4SI 0 "mve_scatter_memory")
9360 (match_operand:V4SI 1 "s_register_operand")
9361 (match_operand:V4SI 2 "s_register_operand")
9362 (unspec:V4SI [(const_int 0)] VSTRWSSOQ)]
9365 rtx ind = XEXP (operands[0], 0);
9366 gcc_assert (REG_P (ind));
9368 gen_mve_vstrwq_scatter_shifted_offset_<supf>v4si_insn (ind, operands[1],
9373 (define_insn "mve_vstrwq_scatter_shifted_offset_<supf>v4si_insn"
9374 [(set (mem:BLK (scratch))
9376 [(match_operand:SI 0 "register_operand" "r")
9377 (match_operand:V4SI 1 "s_register_operand" "w")
9378 (match_operand:V4SI 2 "s_register_operand" "w")]
9381 "vstrw.32\t%q2, [%0, %q1, uxtw #2]"
9382 [(set_attr "length" "4")])
9385 ;; [vaddq_s, vaddq_u])
9387 (define_insn "mve_vaddq<mode>"
9389 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
9390 (plus:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
9391 (match_operand:MVE_2 2 "s_register_operand" "w")))
9394 "vadd.i%#<V_sz_elem> %q0, %q1, %q2"
9395 [(set_attr "type" "mve_move")
9401 (define_insn "mve_vaddq_f<mode>"
9403 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
9404 (plus:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")
9405 (match_operand:MVE_0 2 "s_register_operand" "w")))
9407 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
9408 "vadd.f%#<V_sz_elem> %q0, %q1, %q2"
9409 [(set_attr "type" "mve_move")
9415 (define_expand "mve_vidupq_n_u<mode>"
9416 [(match_operand:MVE_2 0 "s_register_operand")
9417 (match_operand:SI 1 "s_register_operand")
9418 (match_operand:SI 2 "mve_imm_selective_upto_8")]
9421 rtx temp = gen_reg_rtx (SImode);
9422 emit_move_insn (temp, operands[1]);
9423 rtx inc = gen_int_mode (INTVAL(operands[2]) * <MVE_LANES>, SImode);
9424 emit_insn (gen_mve_vidupq_u<mode>_insn (operands[0], temp, operands[1],
9432 (define_insn "mve_vidupq_u<mode>_insn"
9433 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
9434 (unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1")
9435 (match_operand:SI 3 "mve_imm_selective_upto_8" "Rg")]
9437 (set (match_operand:SI 1 "s_register_operand" "=Te")
9438 (plus:SI (match_dup 2)
9439 (match_operand:SI 4 "immediate_operand" "i")))]
9441 "vidup.u%#<V_sz_elem>\t%q0, %1, %3")
9446 (define_expand "mve_vidupq_m_n_u<mode>"
9447 [(match_operand:MVE_2 0 "s_register_operand")
9448 (match_operand:MVE_2 1 "s_register_operand")
9449 (match_operand:SI 2 "s_register_operand")
9450 (match_operand:SI 3 "mve_imm_selective_upto_8")
9451 (match_operand:HI 4 "vpr_register_operand")]
9454 rtx temp = gen_reg_rtx (SImode);
9455 emit_move_insn (temp, operands[2]);
9456 rtx inc = gen_int_mode (INTVAL(operands[3]) * <MVE_LANES>, SImode);
9457 emit_insn (gen_mve_vidupq_m_wb_u<mode>_insn(operands[0], operands[1], temp,
9458 operands[2], operands[3],
9464 ;; [vidupq_m_wb_u_insn])
9466 (define_insn "mve_vidupq_m_wb_u<mode>_insn"
9467 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
9468 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
9469 (match_operand:SI 3 "s_register_operand" "2")
9470 (match_operand:SI 4 "mve_imm_selective_upto_8" "Rg")
9471 (match_operand:HI 5 "vpr_register_operand" "Up")]
9473 (set (match_operand:SI 2 "s_register_operand" "=Te")
9474 (plus:SI (match_dup 3)
9475 (match_operand:SI 6 "immediate_operand" "i")))]
9477 "vpst\;\tvidupt.u%#<V_sz_elem>\t%q0, %2, %4"
9478 [(set_attr "length""8")])
9483 (define_expand "mve_vddupq_n_u<mode>"
9484 [(match_operand:MVE_2 0 "s_register_operand")
9485 (match_operand:SI 1 "s_register_operand")
9486 (match_operand:SI 2 "mve_imm_selective_upto_8")]
9489 rtx temp = gen_reg_rtx (SImode);
9490 emit_move_insn (temp, operands[1]);
9491 rtx inc = gen_int_mode (INTVAL(operands[2]) * <MVE_LANES>, SImode);
9492 emit_insn (gen_mve_vddupq_u<mode>_insn (operands[0], temp, operands[1],
9500 (define_insn "mve_vddupq_u<mode>_insn"
9501 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
9502 (unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1")
9503 (match_operand:SI 3 "immediate_operand" "i")]
9505 (set (match_operand:SI 1 "s_register_operand" "=Te")
9506 (minus:SI (match_dup 2)
9507 (match_operand:SI 4 "immediate_operand" "i")))]
9509 "vddup.u%#<V_sz_elem> %q0, %1, %3")
9514 (define_expand "mve_vddupq_m_n_u<mode>"
9515 [(match_operand:MVE_2 0 "s_register_operand")
9516 (match_operand:MVE_2 1 "s_register_operand")
9517 (match_operand:SI 2 "s_register_operand")
9518 (match_operand:SI 3 "mve_imm_selective_upto_8")
9519 (match_operand:HI 4 "vpr_register_operand")]
9522 rtx temp = gen_reg_rtx (SImode);
9523 emit_move_insn (temp, operands[2]);
9524 rtx inc = gen_int_mode (INTVAL(operands[3]) * <MVE_LANES>, SImode);
9525 emit_insn (gen_mve_vddupq_m_wb_u<mode>_insn(operands[0], operands[1], temp,
9526 operands[2], operands[3],
9532 ;; [vddupq_m_wb_u_insn])
9534 (define_insn "mve_vddupq_m_wb_u<mode>_insn"
9535 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
9536 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
9537 (match_operand:SI 3 "s_register_operand" "2")
9538 (match_operand:SI 4 "mve_imm_selective_upto_8" "Rg")
9539 (match_operand:HI 5 "vpr_register_operand" "Up")]
9541 (set (match_operand:SI 2 "s_register_operand" "=Te")
9542 (minus:SI (match_dup 3)
9543 (match_operand:SI 6 "immediate_operand" "i")))]
9545 "vpst\;\tvddupt.u%#<V_sz_elem>\t%q0, %2, %4"
9546 [(set_attr "length""8")])
9551 (define_expand "mve_vdwdupq_n_u<mode>"
9552 [(match_operand:MVE_2 0 "s_register_operand")
9553 (match_operand:SI 1 "s_register_operand")
9554 (match_operand:DI 2 "s_register_operand")
9555 (match_operand:SI 3 "mve_imm_selective_upto_8")]
9558 rtx ignore_wb = gen_reg_rtx (SImode);
9559 emit_insn (gen_mve_vdwdupq_wb_u<mode>_insn (operands[0], ignore_wb,
9560 operands[1], operands[2],
9568 (define_expand "mve_vdwdupq_wb_u<mode>"
9569 [(match_operand:SI 0 "s_register_operand")
9570 (match_operand:SI 1 "s_register_operand")
9571 (match_operand:DI 2 "s_register_operand")
9572 (match_operand:SI 3 "mve_imm_selective_upto_8")
9573 (unspec:MVE_2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
9576 rtx ignore_vec = gen_reg_rtx (<MODE>mode);
9577 emit_insn (gen_mve_vdwdupq_wb_u<mode>_insn (ignore_vec, operands[0],
9578 operands[1], operands[2],
9584 ;; [vdwdupq_wb_u_insn])
9586 (define_insn "mve_vdwdupq_wb_u<mode>_insn"
9587 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
9588 (unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1")
9589 (subreg:SI (match_operand:DI 3 "s_register_operand" "r") 4)
9590 (match_operand:SI 4 "mve_imm_selective_upto_8" "Rg")]
9592 (set (match_operand:SI 1 "s_register_operand" "=Te")
9593 (unspec:SI [(match_dup 2)
9594 (subreg:SI (match_dup 3) 4)
9598 "vdwdup.u%#<V_sz_elem>\t%q0, %2, %R3, %4"
9604 (define_expand "mve_vdwdupq_m_n_u<mode>"
9605 [(match_operand:MVE_2 0 "s_register_operand")
9606 (match_operand:MVE_2 1 "s_register_operand")
9607 (match_operand:SI 2 "s_register_operand")
9608 (match_operand:DI 3 "s_register_operand")
9609 (match_operand:SI 4 "mve_imm_selective_upto_8")
9610 (match_operand:HI 5 "vpr_register_operand")]
9613 rtx ignore_wb = gen_reg_rtx (SImode);
9614 emit_insn (gen_mve_vdwdupq_m_wb_u<mode>_insn (operands[0], ignore_wb,
9615 operands[1], operands[2],
9616 operands[3], operands[4],
9622 ;; [vdwdupq_m_wb_u])
9624 (define_expand "mve_vdwdupq_m_wb_u<mode>"
9625 [(match_operand:SI 0 "s_register_operand")
9626 (match_operand:MVE_2 1 "s_register_operand")
9627 (match_operand:SI 2 "s_register_operand")
9628 (match_operand:DI 3 "s_register_operand")
9629 (match_operand:SI 4 "mve_imm_selective_upto_8")
9630 (match_operand:HI 5 "vpr_register_operand")]
9633 rtx ignore_vec = gen_reg_rtx (<MODE>mode);
9634 emit_insn (gen_mve_vdwdupq_m_wb_u<mode>_insn (ignore_vec, operands[0],
9635 operands[1], operands[2],
9636 operands[3], operands[4],
9642 ;; [vdwdupq_m_wb_u_insn])
9644 (define_insn "mve_vdwdupq_m_wb_u<mode>_insn"
9645 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
9646 (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0")
9647 (match_operand:SI 3 "s_register_operand" "1")
9648 (subreg:SI (match_operand:DI 4 "s_register_operand" "r") 4)
9649 (match_operand:SI 5 "mve_imm_selective_upto_8" "Rg")
9650 (match_operand:HI 6 "vpr_register_operand" "Up")]
9652 (set (match_operand:SI 1 "s_register_operand" "=Te")
9653 (unspec:SI [(match_dup 2)
9655 (subreg:SI (match_dup 4) 4)
9661 "vpst\;\tvdwdupt.u%#<V_sz_elem>\t%q2, %3, %R4, %5"
9662 [(set_attr "type" "mve_move")
9663 (set_attr "length""8")])
9668 (define_expand "mve_viwdupq_n_u<mode>"
9669 [(match_operand:MVE_2 0 "s_register_operand")
9670 (match_operand:SI 1 "s_register_operand")
9671 (match_operand:DI 2 "s_register_operand")
9672 (match_operand:SI 3 "mve_imm_selective_upto_8")]
9675 rtx ignore_wb = gen_reg_rtx (SImode);
9676 emit_insn (gen_mve_viwdupq_wb_u<mode>_insn (operands[0], ignore_wb,
9677 operands[1], operands[2],
9685 (define_expand "mve_viwdupq_wb_u<mode>"
9686 [(match_operand:SI 0 "s_register_operand")
9687 (match_operand:SI 1 "s_register_operand")
9688 (match_operand:DI 2 "s_register_operand")
9689 (match_operand:SI 3 "mve_imm_selective_upto_8")
9690 (unspec:MVE_2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
9693 rtx ignore_vec = gen_reg_rtx (<MODE>mode);
9694 emit_insn (gen_mve_viwdupq_wb_u<mode>_insn (ignore_vec, operands[0],
9695 operands[1], operands[2],
9701 ;; [viwdupq_wb_u_insn])
9703 (define_insn "mve_viwdupq_wb_u<mode>_insn"
9704 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
9705 (unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1")
9706 (subreg:SI (match_operand:DI 3 "s_register_operand" "r") 4)
9707 (match_operand:SI 4 "mve_imm_selective_upto_8" "Rg")]
9709 (set (match_operand:SI 1 "s_register_operand" "=Te")
9710 (unspec:SI [(match_dup 2)
9711 (subreg:SI (match_dup 3) 4)
9715 "viwdup.u%#<V_sz_elem>\t%q0, %2, %R3, %4"
9721 (define_expand "mve_viwdupq_m_n_u<mode>"
9722 [(match_operand:MVE_2 0 "s_register_operand")
9723 (match_operand:MVE_2 1 "s_register_operand")
9724 (match_operand:SI 2 "s_register_operand")
9725 (match_operand:DI 3 "s_register_operand")
9726 (match_operand:SI 4 "mve_imm_selective_upto_8")
9727 (match_operand:HI 5 "vpr_register_operand")]
9730 rtx ignore_wb = gen_reg_rtx (SImode);
9731 emit_insn (gen_mve_viwdupq_m_wb_u<mode>_insn (operands[0], ignore_wb,
9732 operands[1], operands[2],
9733 operands[3], operands[4],
9739 ;; [viwdupq_m_wb_u])
9741 (define_expand "mve_viwdupq_m_wb_u<mode>"
9742 [(match_operand:SI 0 "s_register_operand")
9743 (match_operand:MVE_2 1 "s_register_operand")
9744 (match_operand:SI 2 "s_register_operand")
9745 (match_operand:DI 3 "s_register_operand")
9746 (match_operand:SI 4 "mve_imm_selective_upto_8")
9747 (match_operand:HI 5 "vpr_register_operand")]
9750 rtx ignore_vec = gen_reg_rtx (<MODE>mode);
9751 emit_insn (gen_mve_viwdupq_m_wb_u<mode>_insn (ignore_vec, operands[0],
9752 operands[1], operands[2],
9753 operands[3], operands[4],
9759 ;; [viwdupq_m_wb_u_insn])
9761 (define_insn "mve_viwdupq_m_wb_u<mode>_insn"
9762 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
9763 (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0")
9764 (match_operand:SI 3 "s_register_operand" "1")
9765 (subreg:SI (match_operand:DI 4 "s_register_operand" "r") 4)
9766 (match_operand:SI 5 "mve_imm_selective_upto_8" "Rg")
9767 (match_operand:HI 6 "vpr_register_operand" "Up")]
9769 (set (match_operand:SI 1 "s_register_operand" "=Te")
9770 (unspec:SI [(match_dup 2)
9772 (subreg:SI (match_dup 4) 4)
9778 "vpst\;\tviwdupt.u%#<V_sz_elem>\t%q2, %3, %R4, %5"
9779 [(set_attr "type" "mve_move")
9780 (set_attr "length""8")])
9783 ;; [vstrwq_scatter_base_wb_s vstrwq_scatter_base_wb_u]
9785 (define_insn "mve_vstrwq_scatter_base_wb_<supf>v4si"
9786 [(set (mem:BLK (scratch))
9788 [(match_operand:V4SI 1 "s_register_operand" "0")
9789 (match_operand:SI 2 "mve_vldrd_immediate" "Ri")
9790 (match_operand:V4SI 3 "s_register_operand" "w")]
9792 (set (match_operand:V4SI 0 "s_register_operand" "=w")
9793 (unspec:V4SI [(match_dup 1) (match_dup 2)]
9799 ops[0] = operands[1];
9800 ops[1] = operands[2];
9801 ops[2] = operands[3];
9802 output_asm_insn ("vstrw.u32\t%q2, [%q0, %1]!",ops);
9805 [(set_attr "length" "4")])
9808 ;; [vstrwq_scatter_base_wb_p_s vstrwq_scatter_base_wb_p_u]
9810 (define_insn "mve_vstrwq_scatter_base_wb_p_<supf>v4si"
9811 [(set (mem:BLK (scratch))
9813 [(match_operand:V4SI 1 "s_register_operand" "0")
9814 (match_operand:SI 2 "mve_vldrd_immediate" "Ri")
9815 (match_operand:V4SI 3 "s_register_operand" "w")
9816 (match_operand:HI 4 "vpr_register_operand")]
9818 (set (match_operand:V4SI 0 "s_register_operand" "=w")
9819 (unspec:V4SI [(match_dup 1) (match_dup 2)]
9825 ops[0] = operands[1];
9826 ops[1] = operands[2];
9827 ops[2] = operands[3];
9828 output_asm_insn ("vpst\;\tvstrwt.u32\t%q2, [%q0, %1]!",ops);
9831 [(set_attr "length" "8")])
9834 ;; [vstrwq_scatter_base_wb_f]
9836 (define_insn "mve_vstrwq_scatter_base_wb_fv4sf"
9837 [(set (mem:BLK (scratch))
9839 [(match_operand:V4SI 1 "s_register_operand" "0")
9840 (match_operand:SI 2 "mve_vldrd_immediate" "Ri")
9841 (match_operand:V4SF 3 "s_register_operand" "w")]
9843 (set (match_operand:V4SI 0 "s_register_operand" "=w")
9844 (unspec:V4SI [(match_dup 1) (match_dup 2)]
9847 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
9850 ops[0] = operands[1];
9851 ops[1] = operands[2];
9852 ops[2] = operands[3];
9853 output_asm_insn ("vstrw.u32\t%q2, [%q0, %1]!",ops);
9856 [(set_attr "length" "4")])
9859 ;; [vstrwq_scatter_base_wb_p_f]
9861 (define_insn "mve_vstrwq_scatter_base_wb_p_fv4sf"
9862 [(set (mem:BLK (scratch))
9864 [(match_operand:V4SI 1 "s_register_operand" "0")
9865 (match_operand:SI 2 "mve_vldrd_immediate" "Ri")
9866 (match_operand:V4SF 3 "s_register_operand" "w")
9867 (match_operand:HI 4 "vpr_register_operand")]
9869 (set (match_operand:V4SI 0 "s_register_operand" "=w")
9870 (unspec:V4SI [(match_dup 1) (match_dup 2)]
9873 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
9876 ops[0] = operands[1];
9877 ops[1] = operands[2];
9878 ops[2] = operands[3];
9879 output_asm_insn ("vpst\;\tvstrwt.u32\t%q2, [%q0, %1]!",ops);
9882 [(set_attr "length" "8")])
9885 ;; [vstrdq_scatter_base_wb_s vstrdq_scatter_base_wb_u]
9887 (define_insn "mve_vstrdq_scatter_base_wb_<supf>v2di"
9888 [(set (mem:BLK (scratch))
9890 [(match_operand:V2DI 1 "s_register_operand" "0")
9891 (match_operand:SI 2 "mve_vldrd_immediate" "Ri")
9892 (match_operand:V2DI 3 "s_register_operand" "w")]
9894 (set (match_operand:V2DI 0 "s_register_operand" "=&w")
9895 (unspec:V2DI [(match_dup 1) (match_dup 2)]
9901 ops[0] = operands[1];
9902 ops[1] = operands[2];
9903 ops[2] = operands[3];
9904 output_asm_insn ("vstrd.u64\t%q2, [%q0, %1]!",ops);
9907 [(set_attr "length" "4")])
9910 ;; [vstrdq_scatter_base_wb_p_s vstrdq_scatter_base_wb_p_u]
9912 (define_insn "mve_vstrdq_scatter_base_wb_p_<supf>v2di"
9913 [(set (mem:BLK (scratch))
9915 [(match_operand:V2DI 1 "s_register_operand" "0")
9916 (match_operand:SI 2 "mve_vldrd_immediate" "Ri")
9917 (match_operand:V2DI 3 "s_register_operand" "w")
9918 (match_operand:HI 4 "vpr_register_operand")]
9920 (set (match_operand:V2DI 0 "s_register_operand" "=w")
9921 (unspec:V2DI [(match_dup 1) (match_dup 2)]
9927 ops[0] = operands[1];
9928 ops[1] = operands[2];
9929 ops[2] = operands[3];
9930 output_asm_insn ("vpst;vstrdt.u64\t%q2, [%q0, %1]!",ops);
9933 [(set_attr "length" "8")])
9935 (define_expand "mve_vldrwq_gather_base_wb_<supf>v4si"
9936 [(match_operand:V4SI 0 "s_register_operand")
9937 (match_operand:V4SI 1 "s_register_operand")
9938 (match_operand:SI 2 "mve_vldrd_immediate")
9939 (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)]
9942 rtx ignore_result = gen_reg_rtx (V4SImode);
9944 gen_mve_vldrwq_gather_base_wb_<supf>v4si_insn (ignore_result, operands[0],
9945 operands[1], operands[2]));
9949 (define_expand "mve_vldrwq_gather_base_nowb_<supf>v4si"
9950 [(match_operand:V4SI 0 "s_register_operand")
9951 (match_operand:V4SI 1 "s_register_operand")
9952 (match_operand:SI 2 "mve_vldrd_immediate")
9953 (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)]
9956 rtx ignore_wb = gen_reg_rtx (V4SImode);
9958 gen_mve_vldrwq_gather_base_wb_<supf>v4si_insn (operands[0], ignore_wb,
9959 operands[1], operands[2]));
9964 ;; [vldrwq_gather_base_wb_s vldrwq_gather_base_wb_u]
9966 (define_insn "mve_vldrwq_gather_base_wb_<supf>v4si_insn"
9967 [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
9968 (unspec:V4SI [(match_operand:V4SI 2 "s_register_operand" "1")
9969 (match_operand:SI 3 "mve_vldrd_immediate" "Ri")
9970 (mem:BLK (scratch))]
9972 (set (match_operand:V4SI 1 "s_register_operand" "=&w")
9973 (unspec:V4SI [(match_dup 2) (match_dup 3)]
9979 ops[0] = operands[0];
9980 ops[1] = operands[2];
9981 ops[2] = operands[3];
9982 output_asm_insn ("vldrw.u32\t%q0, [%q1, %2]!",ops);
9985 [(set_attr "length" "4")])
9987 (define_expand "mve_vldrwq_gather_base_wb_z_<supf>v4si"
9988 [(match_operand:V4SI 0 "s_register_operand")
9989 (match_operand:V4SI 1 "s_register_operand")
9990 (match_operand:SI 2 "mve_vldrd_immediate")
9991 (match_operand:HI 3 "vpr_register_operand")
9992 (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)]
9995 rtx ignore_result = gen_reg_rtx (V4SImode);
9997 gen_mve_vldrwq_gather_base_wb_z_<supf>v4si_insn (ignore_result, operands[0],
9998 operands[1], operands[2],
10002 (define_expand "mve_vldrwq_gather_base_nowb_z_<supf>v4si"
10003 [(match_operand:V4SI 0 "s_register_operand")
10004 (match_operand:V4SI 1 "s_register_operand")
10005 (match_operand:SI 2 "mve_vldrd_immediate")
10006 (match_operand:HI 3 "vpr_register_operand")
10007 (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)]
10010 rtx ignore_wb = gen_reg_rtx (V4SImode);
10012 gen_mve_vldrwq_gather_base_wb_z_<supf>v4si_insn (operands[0], ignore_wb,
10013 operands[1], operands[2],
10019 ;; [vldrwq_gather_base_wb_z_s vldrwq_gather_base_wb_z_u]
10021 (define_insn "mve_vldrwq_gather_base_wb_z_<supf>v4si_insn"
10022 [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
10023 (unspec:V4SI [(match_operand:V4SI 2 "s_register_operand" "1")
10024 (match_operand:SI 3 "mve_vldrd_immediate" "Ri")
10025 (match_operand:HI 4 "vpr_register_operand" "Up")
10026 (mem:BLK (scratch))]
10028 (set (match_operand:V4SI 1 "s_register_operand" "=&w")
10029 (unspec:V4SI [(match_dup 2) (match_dup 3)]
10035 ops[0] = operands[0];
10036 ops[1] = operands[2];
10037 ops[2] = operands[3];
10038 output_asm_insn ("vpst\;vldrwt.u32\t%q0, [%q1, %2]!",ops);
10041 [(set_attr "length" "8")])
10043 (define_expand "mve_vldrwq_gather_base_wb_fv4sf"
10044 [(match_operand:V4SI 0 "s_register_operand")
10045 (match_operand:V4SI 1 "s_register_operand")
10046 (match_operand:SI 2 "mve_vldrd_immediate")
10047 (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)]
10048 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
10050 rtx ignore_result = gen_reg_rtx (V4SFmode);
10052 gen_mve_vldrwq_gather_base_wb_fv4sf_insn (ignore_result, operands[0],
10053 operands[1], operands[2]));
10057 (define_expand "mve_vldrwq_gather_base_nowb_fv4sf"
10058 [(match_operand:V4SF 0 "s_register_operand")
10059 (match_operand:V4SI 1 "s_register_operand")
10060 (match_operand:SI 2 "mve_vldrd_immediate")
10061 (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)]
10062 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
10064 rtx ignore_wb = gen_reg_rtx (V4SImode);
10066 gen_mve_vldrwq_gather_base_wb_fv4sf_insn (operands[0], ignore_wb,
10067 operands[1], operands[2]));
10072 ;; [vldrwq_gather_base_wb_f]
10074 (define_insn "mve_vldrwq_gather_base_wb_fv4sf_insn"
10075 [(set (match_operand:V4SF 0 "s_register_operand" "=&w")
10076 (unspec:V4SF [(match_operand:V4SI 2 "s_register_operand" "1")
10077 (match_operand:SI 3 "mve_vldrd_immediate" "Ri")
10078 (mem:BLK (scratch))]
10080 (set (match_operand:V4SI 1 "s_register_operand" "=&w")
10081 (unspec:V4SI [(match_dup 2) (match_dup 3)]
10084 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
10087 ops[0] = operands[0];
10088 ops[1] = operands[2];
10089 ops[2] = operands[3];
10090 output_asm_insn ("vldrw.u32\t%q0, [%q1, %2]!",ops);
10093 [(set_attr "length" "4")])
10095 (define_expand "mve_vldrwq_gather_base_wb_z_fv4sf"
10096 [(match_operand:V4SI 0 "s_register_operand")
10097 (match_operand:V4SI 1 "s_register_operand")
10098 (match_operand:SI 2 "mve_vldrd_immediate")
10099 (match_operand:HI 3 "vpr_register_operand")
10100 (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)]
10101 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
10103 rtx ignore_result = gen_reg_rtx (V4SFmode);
10105 gen_mve_vldrwq_gather_base_wb_z_fv4sf_insn (ignore_result, operands[0],
10106 operands[1], operands[2],
10111 (define_expand "mve_vldrwq_gather_base_nowb_z_fv4sf"
10112 [(match_operand:V4SF 0 "s_register_operand")
10113 (match_operand:V4SI 1 "s_register_operand")
10114 (match_operand:SI 2 "mve_vldrd_immediate")
10115 (match_operand:HI 3 "vpr_register_operand")
10116 (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)]
10117 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
10119 rtx ignore_wb = gen_reg_rtx (V4SImode);
10121 gen_mve_vldrwq_gather_base_wb_z_fv4sf_insn (operands[0], ignore_wb,
10122 operands[1], operands[2],
10128 ;; [vldrwq_gather_base_wb_z_f]
10130 (define_insn "mve_vldrwq_gather_base_wb_z_fv4sf_insn"
10131 [(set (match_operand:V4SF 0 "s_register_operand" "=&w")
10132 (unspec:V4SF [(match_operand:V4SI 2 "s_register_operand" "1")
10133 (match_operand:SI 3 "mve_vldrd_immediate" "Ri")
10134 (match_operand:HI 4 "vpr_register_operand" "Up")
10135 (mem:BLK (scratch))]
10137 (set (match_operand:V4SI 1 "s_register_operand" "=&w")
10138 (unspec:V4SI [(match_dup 2) (match_dup 3)]
10141 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
10144 ops[0] = operands[0];
10145 ops[1] = operands[2];
10146 ops[2] = operands[3];
10147 output_asm_insn ("vpst\;vldrwt.u32\t%q0, [%q1, %2]!",ops);
10150 [(set_attr "length" "8")])
10152 (define_expand "mve_vldrdq_gather_base_wb_<supf>v2di"
10153 [(match_operand:V2DI 0 "s_register_operand")
10154 (match_operand:V2DI 1 "s_register_operand")
10155 (match_operand:SI 2 "mve_vldrd_immediate")
10156 (unspec:V2DI [(const_int 0)] VLDRDGBWBQ)]
10159 rtx ignore_result = gen_reg_rtx (V2DImode);
10161 gen_mve_vldrdq_gather_base_wb_<supf>v2di_insn (ignore_result, operands[0],
10162 operands[1], operands[2]));
10166 (define_expand "mve_vldrdq_gather_base_nowb_<supf>v2di"
10167 [(match_operand:V2DI 0 "s_register_operand")
10168 (match_operand:V2DI 1 "s_register_operand")
10169 (match_operand:SI 2 "mve_vldrd_immediate")
10170 (unspec:V2DI [(const_int 0)] VLDRDGBWBQ)]
10173 rtx ignore_wb = gen_reg_rtx (V2DImode);
10175 gen_mve_vldrdq_gather_base_wb_<supf>v2di_insn (operands[0], ignore_wb,
10176 operands[1], operands[2]));
10182 ;; [vldrdq_gather_base_wb_s vldrdq_gather_base_wb_u]
10184 (define_insn "mve_vldrdq_gather_base_wb_<supf>v2di_insn"
10185 [(set (match_operand:V2DI 0 "s_register_operand" "=&w")
10186 (unspec:V2DI [(match_operand:V2DI 2 "s_register_operand" "1")
10187 (match_operand:SI 3 "mve_vldrd_immediate" "Ri")
10188 (mem:BLK (scratch))]
10190 (set (match_operand:V2DI 1 "s_register_operand" "=&w")
10191 (unspec:V2DI [(match_dup 2) (match_dup 3)]
10197 ops[0] = operands[0];
10198 ops[1] = operands[2];
10199 ops[2] = operands[3];
10200 output_asm_insn ("vldrd.64\t%q0, [%q1, %2]!",ops);
10203 [(set_attr "length" "4")])
10205 (define_expand "mve_vldrdq_gather_base_wb_z_<supf>v2di"
10206 [(match_operand:V2DI 0 "s_register_operand")
10207 (match_operand:V2DI 1 "s_register_operand")
10208 (match_operand:SI 2 "mve_vldrd_immediate")
10209 (match_operand:HI 3 "vpr_register_operand")
10210 (unspec:V2DI [(const_int 0)] VLDRDGBWBQ)]
10213 rtx ignore_result = gen_reg_rtx (V2DImode);
10215 gen_mve_vldrdq_gather_base_wb_z_<supf>v2di_insn (ignore_result, operands[0],
10216 operands[1], operands[2],
10221 (define_expand "mve_vldrdq_gather_base_nowb_z_<supf>v2di"
10222 [(match_operand:V2DI 0 "s_register_operand")
10223 (match_operand:V2DI 1 "s_register_operand")
10224 (match_operand:SI 2 "mve_vldrd_immediate")
10225 (match_operand:HI 3 "vpr_register_operand")
10226 (unspec:V2DI [(const_int 0)] VLDRDGBWBQ)]
10229 rtx ignore_wb = gen_reg_rtx (V2DImode);
10231 gen_mve_vldrdq_gather_base_wb_z_<supf>v2di_insn (operands[0], ignore_wb,
10232 operands[1], operands[2],
10237 (define_insn "get_fpscr_nzcvqc"
10238 [(set (match_operand:SI 0 "register_operand" "=r")
10239 (unspec:SI [(reg:SI VFPCC_REGNUM)] UNSPEC_GET_FPSCR_NZCVQC))]
10241 "vmrs\\t%0, FPSCR_nzcvqc"
10242 [(set_attr "type" "mve_move")])
10244 (define_insn "set_fpscr_nzcvqc"
10245 [(set (reg:SI VFPCC_REGNUM)
10246 (unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
10247 VUNSPEC_SET_FPSCR_NZCVQC))]
10249 "vmsr\\tFPSCR_nzcvqc, %0"
10250 [(set_attr "type" "mve_move")])
10253 ;; [vldrdq_gather_base_wb_z_s vldrdq_gather_base_wb_z_u]
10255 (define_insn "mve_vldrdq_gather_base_wb_z_<supf>v2di_insn"
10256 [(set (match_operand:V2DI 0 "s_register_operand" "=&w")
10257 (unspec:V2DI [(match_operand:V2DI 2 "s_register_operand" "1")
10258 (match_operand:SI 3 "mve_vldrd_immediate" "Ri")
10259 (match_operand:HI 4 "vpr_register_operand" "Up")
10260 (mem:BLK (scratch))]
10262 (set (match_operand:V2DI 1 "s_register_operand" "=&w")
10263 (unspec:V2DI [(match_dup 2) (match_dup 3)]
10269 ops[0] = operands[0];
10270 ops[1] = operands[2];
10271 ops[2] = operands[3];
10272 output_asm_insn ("vpst\;vldrdt.u64\t%q0, [%q1, %2]!",ops);
10275 [(set_attr "length" "8")])
10277 ;; [vadciq_m_s, vadciq_m_u])
10279 (define_insn "mve_vadciq_m_<supf>v4si"
10280 [(set (match_operand:V4SI 0 "s_register_operand" "=w")
10281 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "0")
10282 (match_operand:V4SI 2 "s_register_operand" "w")
10283 (match_operand:V4SI 3 "s_register_operand" "w")
10284 (match_operand:HI 4 "vpr_register_operand" "Up")]
10286 (set (reg:SI VFPCC_REGNUM)
10287 (unspec:SI [(const_int 0)]
10291 "vpst\;vadcit.i32\t%q0, %q2, %q3"
10292 [(set_attr "type" "mve_move")
10293 (set_attr "length" "8")])
10296 ;; [vadciq_u, vadciq_s])
10298 (define_insn "mve_vadciq_<supf>v4si"
10299 [(set (match_operand:V4SI 0 "s_register_operand" "=w")
10300 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
10301 (match_operand:V4SI 2 "s_register_operand" "w")]
10303 (set (reg:SI VFPCC_REGNUM)
10304 (unspec:SI [(const_int 0)]
10308 "vadci.i32\t%q0, %q1, %q2"
10309 [(set_attr "type" "mve_move")
10310 (set_attr "length" "4")])
10313 ;; [vadcq_m_s, vadcq_m_u])
10315 (define_insn "mve_vadcq_m_<supf>v4si"
10316 [(set (match_operand:V4SI 0 "s_register_operand" "=w")
10317 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "0")
10318 (match_operand:V4SI 2 "s_register_operand" "w")
10319 (match_operand:V4SI 3 "s_register_operand" "w")
10320 (match_operand:HI 4 "vpr_register_operand" "Up")]
10322 (set (reg:SI VFPCC_REGNUM)
10323 (unspec:SI [(reg:SI VFPCC_REGNUM)]
10327 "vpst\;vadct.i32\t%q0, %q2, %q3"
10328 [(set_attr "type" "mve_move")
10329 (set_attr "length" "8")])
10332 ;; [vadcq_u, vadcq_s])
10334 (define_insn "mve_vadcq_<supf>v4si"
10335 [(set (match_operand:V4SI 0 "s_register_operand" "=w")
10336 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
10337 (match_operand:V4SI 2 "s_register_operand" "w")]
10339 (set (reg:SI VFPCC_REGNUM)
10340 (unspec:SI [(reg:SI VFPCC_REGNUM)]
10344 "vadc.i32\t%q0, %q1, %q2"
10345 [(set_attr "type" "mve_move")
10346 (set_attr "length" "4")
10347 (set_attr "conds" "set")])
10350 ;; [vsbciq_m_u, vsbciq_m_s])
10352 (define_insn "mve_vsbciq_m_<supf>v4si"
10353 [(set (match_operand:V4SI 0 "s_register_operand" "=w")
10354 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
10355 (match_operand:V4SI 2 "s_register_operand" "w")
10356 (match_operand:V4SI 3 "s_register_operand" "w")
10357 (match_operand:HI 4 "vpr_register_operand" "Up")]
10359 (set (reg:SI VFPCC_REGNUM)
10360 (unspec:SI [(const_int 0)]
10364 "vpst\;vsbcit.i32\t%q0, %q2, %q3"
10365 [(set_attr "type" "mve_move")
10366 (set_attr "length" "8")])
10369 ;; [vsbciq_s, vsbciq_u])
10371 (define_insn "mve_vsbciq_<supf>v4si"
10372 [(set (match_operand:V4SI 0 "s_register_operand" "=w")
10373 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
10374 (match_operand:V4SI 2 "s_register_operand" "w")]
10376 (set (reg:SI VFPCC_REGNUM)
10377 (unspec:SI [(const_int 0)]
10381 "vsbci.i32\t%q0, %q1, %q2"
10382 [(set_attr "type" "mve_move")
10383 (set_attr "length" "4")])
10386 ;; [vsbcq_m_u, vsbcq_m_s])
10388 (define_insn "mve_vsbcq_m_<supf>v4si"
10389 [(set (match_operand:V4SI 0 "s_register_operand" "=w")
10390 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
10391 (match_operand:V4SI 2 "s_register_operand" "w")
10392 (match_operand:V4SI 3 "s_register_operand" "w")
10393 (match_operand:HI 4 "vpr_register_operand" "Up")]
10395 (set (reg:SI VFPCC_REGNUM)
10396 (unspec:SI [(reg:SI VFPCC_REGNUM)]
10400 "vpst\;vsbct.i32\t%q0, %q2, %q3"
10401 [(set_attr "type" "mve_move")
10402 (set_attr "length" "8")])
10405 ;; [vsbcq_s, vsbcq_u])
10407 (define_insn "mve_vsbcq_<supf>v4si"
10408 [(set (match_operand:V4SI 0 "s_register_operand" "=w")
10409 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
10410 (match_operand:V4SI 2 "s_register_operand" "w")]
10412 (set (reg:SI VFPCC_REGNUM)
10413 (unspec:SI [(reg:SI VFPCC_REGNUM)]
10417 "vsbc.i32\t%q0, %q1, %q2"
10418 [(set_attr "type" "mve_move")
10419 (set_attr "length" "4")])
10424 (define_insn "mve_vst2q<mode>"
10425 [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
10426 (unspec:OI [(match_operand:OI 1 "s_register_operand" "w")
10427 (unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
10430 "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode))
10431 || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))"
10434 int regno = REGNO (operands[1]);
10435 ops[0] = gen_rtx_REG (TImode, regno);
10436 ops[1] = gen_rtx_REG (TImode, regno + 4);
10437 rtx reg = operands[0];
10438 while (reg && !REG_P (reg))
10439 reg = XEXP (reg, 0);
10440 gcc_assert (REG_P (reg));
10442 ops[3] = operands[0];
10443 output_asm_insn ("vst20.<V_sz_elem>\t{%q0, %q1}, [%2]\n\t"
10444 "vst21.<V_sz_elem>\t{%q0, %q1}, %3", ops);
10447 [(set_attr "length" "8")])
10452 (define_insn "mve_vld2q<mode>"
10453 [(set (match_operand:OI 0 "s_register_operand" "=w")
10454 (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um")
10455 (unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
10458 "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode))
10459 || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))"
10462 int regno = REGNO (operands[0]);
10463 ops[0] = gen_rtx_REG (TImode, regno);
10464 ops[1] = gen_rtx_REG (TImode, regno + 4);
10465 rtx reg = operands[1];
10466 while (reg && !REG_P (reg))
10467 reg = XEXP (reg, 0);
10468 gcc_assert (REG_P (reg));
10470 ops[3] = operands[1];
10471 output_asm_insn ("vld20.<V_sz_elem>\t{%q0, %q1}, [%2]\n\t"
10472 "vld21.<V_sz_elem>\t{%q0, %q1}, %3", ops);
10475 [(set_attr "length" "8")])
10480 (define_insn "mve_vld4q<mode>"
10481 [(set (match_operand:XI 0 "s_register_operand" "=w")
10482 (unspec:XI [(match_operand:XI 1 "neon_struct_operand" "Um")
10483 (unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
10486 "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode))
10487 || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))"
10490 int regno = REGNO (operands[0]);
10491 ops[0] = gen_rtx_REG (TImode, regno);
10492 ops[1] = gen_rtx_REG (TImode, regno+4);
10493 ops[2] = gen_rtx_REG (TImode, regno+8);
10494 ops[3] = gen_rtx_REG (TImode, regno + 12);
10495 rtx reg = operands[1];
10496 while (reg && !REG_P (reg))
10497 reg = XEXP (reg, 0);
10498 gcc_assert (REG_P (reg));
10500 ops[5] = operands[1];
10501 output_asm_insn ("vld40.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t"
10502 "vld41.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t"
10503 "vld42.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t"
10504 "vld43.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, %5", ops);
10507 [(set_attr "length" "16")])
10509 ;; [vgetq_lane_u, vgetq_lane_s, vgetq_lane_f])
10511 (define_insn "mve_vec_extract<mode><V_elem_l>"
10512 [(set (match_operand:<V_elem> 0 "nonimmediate_operand" "=r")
10513 (vec_select:<V_elem>
10514 (match_operand:MVE_VLD_ST 1 "s_register_operand" "w")
10515 (parallel [(match_operand:SI 2 "immediate_operand" "i")])))]
10516 "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode))
10517 || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))"
10519 if (BYTES_BIG_ENDIAN)
10521 int elt = INTVAL (operands[2]);
10522 elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt;
10523 operands[2] = GEN_INT (elt);
10525 return "vmov.<V_extr_elem>\t%0, %q1[%c2]";
10527 [(set_attr "type" "mve_move")])
10529 (define_insn "mve_vec_extractv2didi"
10530 [(set (match_operand:DI 0 "nonimmediate_operand" "=r")
10532 (match_operand:V2DI 1 "s_register_operand" "w")
10533 (parallel [(match_operand:SI 2 "immediate_operand" "i")])))]
10536 int elt = INTVAL (operands[2]);
10537 if (BYTES_BIG_ENDIAN)
10541 return "vmov\t%Q0, %R0, %e1";
10543 return "vmov\t%Q0, %R0, %f1";
10545 [(set_attr "type" "mve_move")])
10547 (define_insn "*mve_vec_extract_sext_internal<mode>"
10548 [(set (match_operand:SI 0 "s_register_operand" "=r")
10550 (vec_select:<V_elem>
10551 (match_operand:MVE_2 1 "s_register_operand" "w")
10552 (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))]
10553 "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode))
10554 || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))"
10556 if (BYTES_BIG_ENDIAN)
10558 int elt = INTVAL (operands[2]);
10559 elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt;
10560 operands[2] = GEN_INT (elt);
10562 return "vmov.s<V_sz_elem>\t%0, %q1[%c2]";
10564 [(set_attr "type" "mve_move")])
10566 (define_insn "*mve_vec_extract_zext_internal<mode>"
10567 [(set (match_operand:SI 0 "s_register_operand" "=r")
10569 (vec_select:<V_elem>
10570 (match_operand:MVE_2 1 "s_register_operand" "w")
10571 (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))]
10572 "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode))
10573 || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))"
10575 if (BYTES_BIG_ENDIAN)
10577 int elt = INTVAL (operands[2]);
10578 elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt;
10579 operands[2] = GEN_INT (elt);
10581 return "vmov.u<V_sz_elem>\t%0, %q1[%c2]";
10583 [(set_attr "type" "mve_move")])
10586 ;; [vsetq_lane_u, vsetq_lane_s, vsetq_lane_f])
10588 (define_insn "mve_vec_set<mode>_internal"
10589 [(set (match_operand:VQ2 0 "s_register_operand" "=w")
10592 (match_operand:<V_elem> 1 "nonimmediate_operand" "r"))
10593 (match_operand:VQ2 3 "s_register_operand" "0")
10594 (match_operand:SI 2 "immediate_operand" "i")))]
10595 "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode))
10596 || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))"
10598 int elt = ffs ((int) INTVAL (operands[2])) - 1;
10599 if (BYTES_BIG_ENDIAN)
10600 elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt;
10601 operands[2] = GEN_INT (elt);
10603 return "vmov.<V_sz_elem>\t%q0[%c2], %1";
10605 [(set_attr "type" "mve_move")])
10607 (define_insn "mve_vec_setv2di_internal"
10608 [(set (match_operand:V2DI 0 "s_register_operand" "=w")
10610 (vec_duplicate:V2DI
10611 (match_operand:DI 1 "nonimmediate_operand" "r"))
10612 (match_operand:V2DI 3 "s_register_operand" "0")
10613 (match_operand:SI 2 "immediate_operand" "i")))]
10616 int elt = ffs ((int) INTVAL (operands[2])) - 1;
10617 if (BYTES_BIG_ENDIAN)
10621 return "vmov\t%e0, %Q1, %R1";
10623 return "vmov\t%f0, %J1, %K1";
10625 [(set_attr "type" "mve_move")])
10630 (define_insn "mve_uqrshll_sat<supf>_di"
10631 [(set (match_operand:DI 0 "arm_low_register_operand" "=l")
10632 (unspec:DI [(match_operand:DI 1 "arm_low_register_operand" "0")
10633 (match_operand:SI 2 "register_operand" "r")]
10636 "uqrshll%?\\t%Q1, %R1, #<supf>, %2"
10637 [(set_attr "predicable" "yes")])
10642 (define_insn "mve_sqrshrl_sat<supf>_di"
10643 [(set (match_operand:DI 0 "arm_low_register_operand" "=l")
10644 (unspec:DI [(match_operand:DI 1 "arm_low_register_operand" "0")
10645 (match_operand:SI 2 "register_operand" "r")]
10648 "sqrshrl%?\\t%Q1, %R1, #<supf>, %2"
10649 [(set_attr "predicable" "yes")])
10654 (define_insn "mve_uqrshl_si"
10655 [(set (match_operand:SI 0 "arm_general_register_operand" "=r")
10656 (unspec:SI [(match_operand:SI 1 "arm_general_register_operand" "0")
10657 (match_operand:SI 2 "register_operand" "r")]
10660 "uqrshl%?\\t%1, %2"
10661 [(set_attr "predicable" "yes")])
10666 (define_insn "mve_sqrshr_si"
10667 [(set (match_operand:SI 0 "arm_general_register_operand" "=r")
10668 (unspec:SI [(match_operand:SI 1 "arm_general_register_operand" "0")
10669 (match_operand:SI 2 "register_operand" "r")]
10672 "sqrshr%?\\t%1, %2"
10673 [(set_attr "predicable" "yes")])
10678 (define_insn "mve_uqshll_di"
10679 [(set (match_operand:DI 0 "arm_low_register_operand" "=l")
10680 (us_ashift:DI (match_operand:DI 1 "arm_low_register_operand" "0")
10681 (match_operand:SI 2 "immediate_operand" "Pg")))]
10683 "uqshll%?\\t%Q1, %R1, %2"
10684 [(set_attr "predicable" "yes")])
10689 (define_insn "mve_urshrl_di"
10690 [(set (match_operand:DI 0 "arm_low_register_operand" "=l")
10691 (unspec:DI [(match_operand:DI 1 "arm_low_register_operand" "0")
10692 (match_operand:SI 2 "immediate_operand" "Pg")]
10695 "urshrl%?\\t%Q1, %R1, %2"
10696 [(set_attr "predicable" "yes")])
10701 (define_insn "mve_uqshl_si"
10702 [(set (match_operand:SI 0 "arm_general_register_operand" "=r")
10703 (us_ashift:SI (match_operand:SI 1 "arm_general_register_operand" "0")
10704 (match_operand:SI 2 "immediate_operand" "Pg")))]
10707 [(set_attr "predicable" "yes")])
10712 (define_insn "mve_urshr_si"
10713 [(set (match_operand:SI 0 "arm_general_register_operand" "=r")
10714 (unspec:SI [(match_operand:SI 1 "arm_general_register_operand" "0")
10715 (match_operand:SI 2 "immediate_operand" "Pg")]
10719 [(set_attr "predicable" "yes")])
10724 (define_insn "mve_sqshl_si"
10725 [(set (match_operand:SI 0 "arm_general_register_operand" "=r")
10726 (ss_ashift:SI (match_operand:DI 1 "arm_general_register_operand" "0")
10727 (match_operand:SI 2 "immediate_operand" "Pg")))]
10730 [(set_attr "predicable" "yes")])
10735 (define_insn "mve_srshr_si"
10736 [(set (match_operand:SI 0 "arm_general_register_operand" "=r")
10737 (unspec:SI [(match_operand:DI 1 "arm_general_register_operand" "0")
10738 (match_operand:SI 2 "immediate_operand" "Pg")]
10742 [(set_attr "predicable" "yes")])
10747 (define_insn "mve_srshrl_di"
10748 [(set (match_operand:DI 0 "arm_low_register_operand" "=l")
10749 (unspec:DI [(match_operand:DI 1 "arm_low_register_operand" "0")
10750 (match_operand:SI 2 "immediate_operand" "Pg")]
10753 "srshrl%?\\t%Q1, %R1, %2"
10754 [(set_attr "predicable" "yes")])
10759 (define_insn "mve_sqshll_di"
10760 [(set (match_operand:DI 0 "arm_low_register_operand" "=l")
10761 (ss_ashift:DI (match_operand:DI 1 "arm_low_register_operand" "0")
10762 (match_operand:SI 2 "immediate_operand" "Pg")))]
10764 "sqshll%?\\t%Q1, %R1, %2"
10765 [(set_attr "predicable" "yes")])
10768 ;; [vshlcq_m_u vshlcq_m_s]
10770 (define_expand "mve_vshlcq_m_vec_<supf><mode>"
10771 [(match_operand:MVE_2 0 "s_register_operand")
10772 (match_operand:MVE_2 1 "s_register_operand")
10773 (match_operand:SI 2 "s_register_operand")
10774 (match_operand:SI 3 "mve_imm_32")
10775 (match_operand:HI 4 "vpr_register_operand")
10776 (unspec:MVE_2 [(const_int 0)] VSHLCQ_M)]
10779 rtx ignore_wb = gen_reg_rtx (SImode);
10780 emit_insn (gen_mve_vshlcq_m_<supf><mode> (operands[0], ignore_wb, operands[1],
10781 operands[2], operands[3],
10786 (define_expand "mve_vshlcq_m_carry_<supf><mode>"
10787 [(match_operand:SI 0 "s_register_operand")
10788 (match_operand:MVE_2 1 "s_register_operand")
10789 (match_operand:SI 2 "s_register_operand")
10790 (match_operand:SI 3 "mve_imm_32")
10791 (match_operand:HI 4 "vpr_register_operand")
10792 (unspec:MVE_2 [(const_int 0)] VSHLCQ_M)]
10795 rtx ignore_vec = gen_reg_rtx (<MODE>mode);
10796 emit_insn (gen_mve_vshlcq_m_<supf><mode> (ignore_vec, operands[0],
10797 operands[1], operands[2],
10798 operands[3], operands[4]));
10802 (define_insn "mve_vshlcq_m_<supf><mode>"
10803 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
10804 (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0")
10805 (match_operand:SI 3 "s_register_operand" "1")
10806 (match_operand:SI 4 "mve_imm_32" "Rf")
10807 (match_operand:HI 5 "vpr_register_operand" "Up")]
10809 (set (match_operand:SI 1 "s_register_operand" "=r")
10810 (unspec:SI [(match_dup 2)
10817 "vpst\;vshlct\t%q0, %1, %4"
10818 [(set_attr "type" "mve_move")
10819 (set_attr "length" "8")])
10821 (define_insn "*mve_vec_duplicate<mode>"
10822 [(set (match_operand:MVE_VLD_ST 0 "s_register_operand" "=w")
10823 (vec_duplicate:MVE_VLD_ST (match_operand:<V_elem> 1 "general_operand" "r")))]
10824 "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT"
10825 "vdup.<V_sz_elem>\t%q0, %1"
10826 [(set_attr "type" "mve_move")])
10828 ;; CDE instructions on MVE registers.
10830 (define_insn "arm_vcx1qv16qi"
10831 [(set (match_operand:V16QI 0 "register_operand" "=t")
10832 (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i")
10833 (match_operand:SI 2 "const_int_mve_cde1_operand" "i")]
10835 "TARGET_CDE && TARGET_HAVE_MVE"
10836 "vcx1\\tp%c1, %q0, #%c2"
10837 [(set_attr "type" "coproc")]
10840 (define_insn "arm_vcx1qav16qi"
10841 [(set (match_operand:V16QI 0 "register_operand" "=t")
10842 (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i")
10843 (match_operand:V16QI 2 "register_operand" "0")
10844 (match_operand:SI 3 "const_int_mve_cde1_operand" "i")]
10846 "TARGET_CDE && TARGET_HAVE_MVE"
10847 "vcx1a\\tp%c1, %q0, #%c3"
10848 [(set_attr "type" "coproc")]
10851 (define_insn "arm_vcx2qv16qi"
10852 [(set (match_operand:V16QI 0 "register_operand" "=t")
10853 (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i")
10854 (match_operand:V16QI 2 "register_operand" "t")
10855 (match_operand:SI 3 "const_int_mve_cde2_operand" "i")]
10857 "TARGET_CDE && TARGET_HAVE_MVE"
10858 "vcx2\\tp%c1, %q0, %q2, #%c3"
10859 [(set_attr "type" "coproc")]
10862 (define_insn "arm_vcx2qav16qi"
10863 [(set (match_operand:V16QI 0 "register_operand" "=t")
10864 (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i")
10865 (match_operand:V16QI 2 "register_operand" "0")
10866 (match_operand:V16QI 3 "register_operand" "t")
10867 (match_operand:SI 4 "const_int_mve_cde2_operand" "i")]
10869 "TARGET_CDE && TARGET_HAVE_MVE"
10870 "vcx2a\\tp%c1, %q0, %q3, #%c4"
10871 [(set_attr "type" "coproc")]
10874 (define_insn "arm_vcx3qv16qi"
10875 [(set (match_operand:V16QI 0 "register_operand" "=t")
10876 (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i")
10877 (match_operand:V16QI 2 "register_operand" "t")
10878 (match_operand:V16QI 3 "register_operand" "t")
10879 (match_operand:SI 4 "const_int_mve_cde3_operand" "i")]
10881 "TARGET_CDE && TARGET_HAVE_MVE"
10882 "vcx3\\tp%c1, %q0, %q2, %q3, #%c4"
10883 [(set_attr "type" "coproc")]
10886 (define_insn "arm_vcx3qav16qi"
10887 [(set (match_operand:V16QI 0 "register_operand" "=t")
10888 (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i")
10889 (match_operand:V16QI 2 "register_operand" "0")
10890 (match_operand:V16QI 3 "register_operand" "t")
10891 (match_operand:V16QI 4 "register_operand" "t")
10892 (match_operand:SI 5 "const_int_mve_cde3_operand" "i")]
10894 "TARGET_CDE && TARGET_HAVE_MVE"
10895 "vcx3a\\tp%c1, %q0, %q3, %q4, #%c5"
10896 [(set_attr "type" "coproc")]
10899 (define_insn "arm_vcx1q<a>_p_v16qi"
10900 [(set (match_operand:V16QI 0 "register_operand" "=t")
10901 (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i")
10902 (match_operand:V16QI 2 "register_operand" "0")
10903 (match_operand:SI 3 "const_int_mve_cde1_operand" "i")
10904 (match_operand:HI 4 "vpr_register_operand" "Up")]
10906 "TARGET_CDE && TARGET_HAVE_MVE"
10907 "vpst\;vcx1<a>t\\tp%c1, %q0, #%c3"
10908 [(set_attr "type" "coproc")
10909 (set_attr "length" "8")]
10912 (define_insn "arm_vcx2q<a>_p_v16qi"
10913 [(set (match_operand:V16QI 0 "register_operand" "=t")
10914 (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i")
10915 (match_operand:V16QI 2 "register_operand" "0")
10916 (match_operand:V16QI 3 "register_operand" "t")
10917 (match_operand:SI 4 "const_int_mve_cde2_operand" "i")
10918 (match_operand:HI 5 "vpr_register_operand" "Up")]
10920 "TARGET_CDE && TARGET_HAVE_MVE"
10921 "vpst\;vcx2<a>t\\tp%c1, %q0, %q3, #%c4"
10922 [(set_attr "type" "coproc")
10923 (set_attr "length" "8")]
10926 (define_insn "arm_vcx3q<a>_p_v16qi"
10927 [(set (match_operand:V16QI 0 "register_operand" "=t")
10928 (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i")
10929 (match_operand:V16QI 2 "register_operand" "0")
10930 (match_operand:V16QI 3 "register_operand" "t")
10931 (match_operand:V16QI 4 "register_operand" "t")
10932 (match_operand:SI 5 "const_int_mve_cde3_operand" "i")
10933 (match_operand:HI 6 "vpr_register_operand" "Up")]
10935 "TARGET_CDE && TARGET_HAVE_MVE"
10936 "vpst\;vcx3<a>t\\tp%c1, %q0, %q3, %q4, #%c5"
10937 [(set_attr "type" "coproc")
10938 (set_attr "length" "8")]