gcc/config/arm/mve.md

   1 ;; Arm M-profile Vector Extension Machine Description
   2 ;; Copyright (C) 2019-2020 Free Software Foundation, Inc.
   3 ;;
   4 ;; This file is part of GCC.
   5 ;;
   6 ;; GCC is free software; you can redistribute it and/or modify it
   7 ;; under the terms of the GNU General Public License as published by
   8 ;; the Free Software Foundation; either version 3, or (at your option)
   9 ;; any later version.
  10 ;;
  11 ;; GCC is distributed in the hope that it will be useful, but
  12 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 ;; General Public License for more details.
  15 ;;
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING3.  If not see
  18 ;; <http://www.gnu.org/licenses/>.
  19
  20 (define_mode_attr V_sz_elem2 [(V16QI "s8") (V8HI "u16") (V4SI "u32")
  21                               (V2DI "u64")])
  22 (define_mode_iterator MVE_types [V16QI V8HI V4SI V2DI TI V8HF V4SF V2DF])
  23 (define_mode_iterator MVE_VLD_ST [V16QI V8HI V4SI V8HF V4SF])
  24 (define_mode_iterator MVE_0 [V8HF V4SF])
  25 (define_mode_iterator MVE_1 [V16QI V8HI V4SI V2DI])
  26 (define_mode_iterator MVE_3 [V16QI V8HI])
  27 (define_mode_iterator MVE_2 [V16QI V8HI V4SI])
  28 (define_mode_iterator MVE_5 [V8HI V4SI])
  29
  30 (define_c_enum "unspec" [VST4Q VRNDXQ_F VRNDQ_F VRNDPQ_F VRNDNQ_F VRNDMQ_F
  31                          VRNDAQ_F VREV64Q_F VNEGQ_F VDUPQ_N_F VABSQ_F VREV32Q_F
  32                          VCVTTQ_F32_F16 VCVTBQ_F32_F16 VCVTQ_TO_F_S VQNEGQ_S
  33                          VCVTQ_TO_F_U VREV16Q_S VREV16Q_U VADDLVQ_S VMVNQ_N_S
  34                          VMVNQ_N_U VCVTAQ_S VCVTAQ_U VREV64Q_S VREV64Q_U
  35                          VQABSQ_S VNEGQ_S VMVNQ_S VMVNQ_U VDUPQ_N_U VDUPQ_N_S
  36                          VCLZQ_U VCLZQ_S VCLSQ_S VADDVQ_S VADDVQ_U VABSQ_S
  37                          VREV32Q_U VREV32Q_S VMOVLTQ_U VMOVLTQ_S VMOVLBQ_S
  38                          VMOVLBQ_U VCVTQ_FROM_F_S VCVTQ_FROM_F_U VCVTPQ_S
  39                          VCVTPQ_U VCVTNQ_S VCVTNQ_U VCVTMQ_S VCVTMQ_U
  40                          VADDLVQ_U VCTP8Q VCTP16Q VCTP32Q VCTP64Q VPNOT
  41                          VCREATEQ_F VCVTQ_N_TO_F_S VCVTQ_N_TO_F_U VBRSRQ_N_F
  42                          VSUBQ_N_F VCREATEQ_U VCREATEQ_S VSHRQ_N_S VSHRQ_N_U
  43                          VCVTQ_N_FROM_F_S VCVTQ_N_FROM_F_U VADDLVQ_P_S
  44                          VADDLVQ_P_U VCMPNEQ_U VCMPNEQ_S VSHLQ_S VSHLQ_U VABDQ_S
  45                          VADDQ_N_S VADDVAQ_S VADDVQ_P_S VANDQ_S VBICQ_S
  46                          VBRSRQ_N_S VCADDQ_ROT270_S VCADDQ_ROT90_S VCMPEQQ_S
  47                          VCMPEQQ_N_S VCMPNEQ_N_S VEORQ_S VHADDQ_S VHADDQ_N_S
  48                          VHSUBQ_S VHSUBQ_N_S VMAXQ_S VMAXVQ_S VMINQ_S VMINVQ_S
  49                          VMLADAVQ_S VMULHQ_S VMULLBQ_INT_S VMULLTQ_INT_S VMULQ_S
  50                          VMULQ_N_S VORNQ_S VORRQ_S VQADDQ_S VQADDQ_N_S VQRSHLQ_S
  51                          VQRSHLQ_N_S VQSHLQ_S VQSHLQ_N_S VQSHLQ_R_S VQSUBQ_S
  52                          VQSUBQ_N_S VRHADDQ_S VRMULHQ_S VRSHLQ_S VRSHLQ_N_S
  53                          VRSHRQ_N_S VSHLQ_N_S VSHLQ_R_S VSUBQ_S VSUBQ_N_S
  54                          VABDQ_U VADDQ_N_U VADDVAQ_U VADDVQ_P_U VANDQ_U VBICQ_U
  55                          VBRSRQ_N_U VCADDQ_ROT270_U VCADDQ_ROT90_U VCMPEQQ_U
  56                          VCMPEQQ_N_U VCMPNEQ_N_U VEORQ_U VHADDQ_U VHADDQ_N_U
  57                          VHSUBQ_U VHSUBQ_N_U VMAXQ_U VMAXVQ_U VMINQ_U VMINVQ_U
  58                          VMLADAVQ_U VMULHQ_U VMULLBQ_INT_U VMULLTQ_INT_U VMULQ_U
  59                          VMULQ_N_U VORNQ_U VORRQ_U VQADDQ_U VQADDQ_N_U VQRSHLQ_U
  60                          VQRSHLQ_N_U VQSHLQ_U VQSHLQ_N_U VQSHLQ_R_U VQSUBQ_U
  61                          VQSUBQ_N_U VRHADDQ_U VRMULHQ_U VRSHLQ_U VRSHLQ_N_U
  62                          VRSHRQ_N_U VSHLQ_N_U VSHLQ_R_U VSUBQ_U VSUBQ_N_U
  63                          VCMPGEQ_N_S VCMPGEQ_S VCMPGTQ_N_S VCMPGTQ_S VCMPLEQ_N_S
  64                          VCMPLEQ_S VCMPLTQ_N_S VCMPLTQ_S VHCADDQ_ROT270_S
  65                          VHCADDQ_ROT90_S VMAXAQ_S VMAXAVQ_S VMINAQ_S VMINAVQ_S
  66                          VMLADAVXQ_S VMLSDAVQ_S VMLSDAVXQ_S VQDMULHQ_N_S
  67                          VQDMULHQ_S VQRDMULHQ_N_S VQRDMULHQ_S VQSHLUQ_N_S
  68                          VCMPCSQ_N_U VCMPCSQ_U VCMPHIQ_N_U VCMPHIQ_U VABDQ_M_S
  69                          VABDQ_M_U VABDQ_F VADDQ_N_F VANDQ_F VBICQ_F
  70                          VCADDQ_ROT270_F VCADDQ_ROT90_F VCMPEQQ_F VCMPEQQ_N_F
  71                          VCMPGEQ_F VCMPGEQ_N_F VCMPGTQ_F VCMPGTQ_N_F VCMPLEQ_F
  72                          VCMPLEQ_N_F VCMPLTQ_F VCMPLTQ_N_F VCMPNEQ_F VCMPNEQ_N_F
  73                          VCMULQ_F VCMULQ_ROT180_F VCMULQ_ROT270_F VCMULQ_ROT90_F
  74                          VEORQ_F VMAXNMAQ_F VMAXNMAVQ_F VMAXNMQ_F VMAXNMVQ_F
  75                          VMINNMAQ_F VMINNMAVQ_F VMINNMQ_F VMINNMVQ_F VMULQ_F
  76                          VMULQ_N_F VORNQ_F VORRQ_F VSUBQ_F VADDLVAQ_U
  77                          VADDLVAQ_S VBICQ_N_U VBICQ_N_S VCTP8Q_M VCTP16Q_M
  78                          VCTP32Q_M VCTP64Q_M VCVTBQ_F16_F32 VCVTTQ_F16_F32
  79                          VMLALDAVQ_U VMLALDAVXQ_U VMLALDAVXQ_S VMLALDAVQ_S
  80                          VMLSLDAVQ_S VMLSLDAVXQ_S VMOVNBQ_U VMOVNBQ_S
  81                          VMOVNTQ_U VMOVNTQ_S VORRQ_N_S VORRQ_N_U VQDMULLBQ_N_S
  82                          VQDMULLBQ_S VQDMULLTQ_N_S VQDMULLTQ_S VQMOVNBQ_U
  83                          VQMOVNBQ_S VQMOVUNBQ_S VQMOVUNTQ_S VRMLALDAVHXQ_S
  84                          VRMLSLDAVHQ_S VRMLSLDAVHXQ_S VSHLLBQ_S
  85                          VSHLLBQ_U VSHLLTQ_U VSHLLTQ_S VQMOVNTQ_U VQMOVNTQ_S
  86                          VSHLLBQ_N_S VSHLLBQ_N_U VSHLLTQ_N_U VSHLLTQ_N_S
  87                          VRMLALDAVHQ_U VRMLALDAVHQ_S VMULLTQ_POLY_P
  88                          VMULLBQ_POLY_P VBICQ_M_N_S VBICQ_M_N_U VCMPEQQ_M_F
  89                          VCVTAQ_M_S VCVTAQ_M_U VCVTQ_M_TO_F_S VCVTQ_M_TO_F_U
  90                          VQRSHRNBQ_N_U VQRSHRNBQ_N_S VQRSHRUNBQ_N_S
  91                          VRMLALDAVHAQ_S VABAVQ_S VABAVQ_U VSHLCQ_S VSHLCQ_U
  92                          VRMLALDAVHAQ_U VABSQ_M_S VADDVAQ_P_S VADDVAQ_P_U
  93                          VCLSQ_M_S VCLZQ_M_S VCLZQ_M_U VCMPCSQ_M_N_U
  94                          VCMPCSQ_M_U VCMPEQQ_M_N_S VCMPEQQ_M_N_U VCMPEQQ_M_S
  95                          VCMPEQQ_M_U VCMPGEQ_M_N_S VCMPGEQ_M_S VCMPGTQ_M_N_S
  96                          VCMPGTQ_M_S VCMPHIQ_M_N_U VCMPHIQ_M_U VCMPLEQ_M_N_S
  97                          VCMPLEQ_M_S VCMPLTQ_M_N_S VCMPLTQ_M_S VCMPNEQ_M_N_S
  98                          VCMPNEQ_M_N_U VCMPNEQ_M_S VCMPNEQ_M_U VDUPQ_M_N_S
  99                          VDUPQ_M_N_U VDWDUPQ_N_U VDWDUPQ_WB_U VIWDUPQ_N_U
 100                          VIWDUPQ_WB_U VMAXAQ_M_S VMAXAVQ_P_S VMAXVQ_P_S
 101                          VMAXVQ_P_U VMINAQ_M_S VMINAVQ_P_S VMINVQ_P_S VMINVQ_P_U
 102                          VMLADAVAQ_S VMLADAVAQ_U VMLADAVQ_P_S VMLADAVQ_P_U
 103                          VMLADAVXQ_P_S VMLAQ_N_S VMLAQ_N_U VMLASQ_N_S VMLASQ_N_U
 104                          VMLSDAVQ_P_S VMLSDAVXQ_P_S VMVNQ_M_S VMVNQ_M_U
 105                          VNEGQ_M_S VPSELQ_S VPSELQ_U VQABSQ_M_S VQDMLAHQ_N_S
 106                          VQDMLAHQ_N_U VQNEGQ_M_S VQRDMLADHQ_S VQRDMLADHXQ_S
 107                          VQRDMLAHQ_N_S VQRDMLAHQ_N_U VQRDMLASHQ_N_S
 108                          VQRDMLASHQ_N_U VQRDMLSDHQ_S VQRDMLSDHXQ_S VQRSHLQ_M_N_S
 109                          VQRSHLQ_M_N_U VQSHLQ_M_R_S VQSHLQ_M_R_U VREV64Q_M_S
 110                          VREV64Q_M_U VRSHLQ_M_N_S VRSHLQ_M_N_U VSHLQ_M_R_S
 111                          VSHLQ_M_R_U VSLIQ_N_S VSLIQ_N_U VSRIQ_N_S VSRIQ_N_U
 112                          VQDMLSDHXQ_S VQDMLSDHQ_S VQDMLADHXQ_S VQDMLADHQ_S
 113                          VMLSDAVAXQ_S VMLSDAVAQ_S VMLADAVAXQ_S
 114                          VCMPGEQ_M_F VCMPGTQ_M_N_F VMLSLDAVQ_P_S VRMLALDAVHAXQ_S
 115                          VMLSLDAVXQ_P_S VFMAQ_F VMLSLDAVAQ_S VQSHRUNBQ_N_S
 116                          VQRSHRUNTQ_N_S VCMLAQ_F VMINNMAQ_M_F VFMASQ_N_F
 117                          VDUPQ_M_N_F VCMPGTQ_M_F VCMPLTQ_M_F VRMLSLDAVHQ_P_S
 118                          VQSHRUNTQ_N_S VABSQ_M_F VMAXNMAVQ_P_F VFMAQ_N_F
 119                          VRMLSLDAVHXQ_P_S VREV32Q_M_F VRMLSLDAVHAQ_S
 120                          VRMLSLDAVHAXQ_S VCMPLTQ_M_N_F VCMPNEQ_M_F VRNDAQ_M_F
 121                          VRNDPQ_M_F VADDLVAQ_P_S VQMOVUNBQ_M_S VCMPLEQ_M_F
 122                          VCMLAQ_ROT180_F VMLSLDAVAXQ_S VRNDXQ_M_F VFMSQ_F
 123                          VMINNMVQ_P_F VMAXNMVQ_P_F VPSELQ_F VCMLAQ_ROT90_F
 124                          VQMOVUNTQ_M_S VREV64Q_M_F VNEGQ_M_F VRNDMQ_M_F
 125                          VCMPLEQ_M_N_F VCMPGEQ_M_N_F VRNDNQ_M_F VMINNMAVQ_P_F
 126                          VCMPNEQ_M_N_F VRMLALDAVHQ_P_S VRMLALDAVHXQ_P_S
 127                          VCMPEQQ_M_N_F VCMLAQ_ROT270_F VMAXNMAQ_M_F VRNDQ_M_F
 128                          VMLALDAVQ_P_U VMLALDAVQ_P_S VQMOVNBQ_M_S VQMOVNBQ_M_U
 129                          VMOVLTQ_M_U VMOVLTQ_M_S VMOVNBQ_M_U VMOVNBQ_M_S
 130                          VRSHRNTQ_N_U VRSHRNTQ_N_S VORRQ_M_N_S VORRQ_M_N_U
 131                          VREV32Q_M_S VREV32Q_M_U VQRSHRNTQ_N_U VQRSHRNTQ_N_S
 132                          VMOVNTQ_M_U VMOVNTQ_M_S VMOVLBQ_M_U VMOVLBQ_M_S
 133                          VMLALDAVAQ_S VMLALDAVAQ_U VQSHRNBQ_N_U VQSHRNBQ_N_S
 134                          VSHRNBQ_N_U VSHRNBQ_N_S VRSHRNBQ_N_S VRSHRNBQ_N_U
 135                          VMLALDAVXQ_P_U VMLALDAVXQ_P_S VQMOVNTQ_M_U VQMOVNTQ_M_S
 136                          VMVNQ_M_N_U VMVNQ_M_N_S VQSHRNTQ_N_U VQSHRNTQ_N_S
 137                          VMLALDAVAXQ_S VMLALDAVAXQ_U VSHRNTQ_N_S VSHRNTQ_N_U
 138                          VCVTBQ_M_F16_F32 VCVTBQ_M_F32_F16 VCVTTQ_M_F16_F32
 139                          VCVTTQ_M_F32_F16 VCVTMQ_M_S VCVTMQ_M_U VCVTNQ_M_S
 140                          VCVTPQ_M_S VCVTPQ_M_U VCVTQ_M_N_FROM_F_S VCVTNQ_M_U
 141                          VREV16Q_M_S VREV16Q_M_U VREV32Q_M VCVTQ_M_FROM_F_U
 142                          VCVTQ_M_FROM_F_S VRMLALDAVHQ_P_U VADDLVAQ_P_U
 143                          VCVTQ_M_N_FROM_F_U VQSHLUQ_M_N_S VABAVQ_P_S
 144                          VABAVQ_P_U VSHLQ_M_S VSHLQ_M_U VSRIQ_M_N_S
 145                          VSRIQ_M_N_U VSUBQ_M_U VSUBQ_M_S VCVTQ_M_N_TO_F_U
 146                          VCVTQ_M_N_TO_F_S])
 147
 148 (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF")
 149                             (V8HF "V8HI") (V4SF "V4SI")])
 150
 151 (define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u") (VREV16Q_S "s")
 152                        (VREV16Q_U "u") (VMVNQ_N_S "s") (VMVNQ_N_U "u")
 153                        (VCVTAQ_U "u") (VCVTAQ_S "s") (VREV64Q_S "s")
 154                        (VREV64Q_U "u") (VMVNQ_S "s") (VMVNQ_U "u")
 155                        (VDUPQ_N_U "u") (VDUPQ_N_S"s") (VADDVQ_S "s")
 156                        (VADDVQ_U "u") (VADDVQ_S "s") (VADDVQ_U "u")
 157                        (VMOVLTQ_U "u") (VMOVLTQ_S "s") (VMOVLBQ_S "s")
 158                        (VMOVLBQ_U "u") (VCVTQ_FROM_F_S "s") (VCVTQ_FROM_F_U "u")
 159                        (VCVTPQ_S "s") (VCVTPQ_U "u") (VCVTNQ_S "s")
 160                        (VCVTNQ_U "u") (VCVTMQ_S "s") (VCVTMQ_U "u")
 161                        (VCLZQ_U "u") (VCLZQ_S "s") (VREV32Q_U "u")
 162                        (VREV32Q_S "s") (VADDLVQ_U "u") (VADDLVQ_S "s")
 163                        (VCVTQ_N_TO_F_S "s") (VCVTQ_N_TO_F_U "u")
 164                        (VCREATEQ_U "u") (VCREATEQ_S "s") (VSHRQ_N_S "s")
 165                        (VSHRQ_N_U "u") (VCVTQ_N_FROM_F_S "s") (VSHLQ_U "u")
 166                        (VCVTQ_N_FROM_F_U "u") (VADDLVQ_P_S "s") (VSHLQ_S "s")
 167                        (VADDLVQ_P_U "u") (VCMPNEQ_U "u") (VCMPNEQ_S "s")
 168                        (VABDQ_M_S "s") (VABDQ_M_U "u") (VABDQ_S "s")
 169                        (VABDQ_U "u") (VADDQ_N_S "s") (VADDQ_N_U "u")
 170                        (VADDVQ_P_S "s") (VADDVQ_P_U "u") (VANDQ_S "s")
 171                        (VANDQ_U "u") (VBICQ_S "s") (VBICQ_U "u")
 172                        (VBRSRQ_N_S "s") (VBRSRQ_N_U "u") (VCADDQ_ROT270_S "s")
 173                        (VCADDQ_ROT270_U "u") (VCADDQ_ROT90_S "s")
 174                        (VCMPEQQ_S "s") (VCMPEQQ_U "u") (VCADDQ_ROT90_U "u")
 175                        (VCMPEQQ_N_S "s") (VCMPEQQ_N_U "u") (VCMPNEQ_N_S "s")
 176                        (VCMPNEQ_N_U "u") (VEORQ_S "s") (VEORQ_U "u")
 177                        (VHADDQ_N_S "s") (VHADDQ_N_U "u") (VHADDQ_S "s")
 178                        (VHADDQ_U "u") (VHSUBQ_N_S "s")  (VHSUBQ_N_U "u")
 179                        (VHSUBQ_S "s") (VMAXQ_S "s") (VMAXQ_U "u") (VHSUBQ_U "u")
 180                        (VMAXVQ_S "s") (VMAXVQ_U "u") (VMINQ_S "s") (VMINQ_U "u")
 181                        (VMINVQ_S "s") (VMINVQ_U "u") (VMLADAVQ_S "s")
 182                        (VMLADAVQ_U "u") (VMULHQ_S "s") (VMULHQ_U "u")
 183                        (VMULLBQ_INT_S "s") (VMULLBQ_INT_U "u") (VQADDQ_S "s")
 184                        (VMULLTQ_INT_S "s") (VMULLTQ_INT_U "u") (VQADDQ_U "u")
 185                        (VMULQ_N_S "s") (VMULQ_N_U "u") (VMULQ_S "s")
 186                        (VMULQ_U "u") (VORNQ_S "s") (VORNQ_U "u") (VORRQ_S "s")
 187                        (VORRQ_U "u") (VQADDQ_N_S "s") (VQADDQ_N_U "u")
 188                        (VQRSHLQ_N_S "s") (VQRSHLQ_N_U "u") (VQRSHLQ_S "s")
 189                        (VQRSHLQ_U "u") (VQSHLQ_N_S "s") (VQSHLQ_N_U "u")
 190                        (VQSHLQ_R_S "s") (VQSHLQ_R_U "u") (VQSHLQ_S "s")
 191                        (VQSHLQ_U "u") (VQSUBQ_N_S "s") (VQSUBQ_N_U "u")
 192                        (VQSUBQ_S "s") (VQSUBQ_U "u") (VRHADDQ_S "s")
 193                        (VRHADDQ_U "u") (VRMULHQ_S "s") (VRMULHQ_U "u")
 194                        (VRSHLQ_N_S "s") (VRSHLQ_N_U "u") (VRSHLQ_S "s")
 195                        (VRSHLQ_U "u") (VRSHRQ_N_S "s") (VRSHRQ_N_U "u")
 196                        (VSHLQ_N_S "s") (VSHLQ_N_U "u") (VSHLQ_R_S "s")
 197                        (VSHLQ_R_U "u") (VSUBQ_N_S "s") (VSUBQ_N_U "u")
 198                        (VSUBQ_S "s") (VSUBQ_U "u") (VADDVAQ_S "s")
 199                        (VADDVAQ_U "u") (VADDLVAQ_S "s") (VADDLVAQ_U "u")
 200                        (VBICQ_N_S "s") (VBICQ_N_U "u") (VMLALDAVQ_U "u")
 201                        (VMLALDAVQ_S "s") (VMLALDAVXQ_U "u") (VMLALDAVXQ_S "s")
 202                        (VMOVNBQ_U "u") (VMOVNBQ_S "s") (VMOVNTQ_U "u")
 203                        (VMOVNTQ_S "s") (VORRQ_N_S "s") (VORRQ_N_U "u")
 204                        (VQMOVNBQ_U "u") (VQMOVNBQ_S "s") (VQMOVNTQ_S "s")
 205                        (VQMOVNTQ_U "u") (VSHLLBQ_N_U "u") (VSHLLBQ_N_S "s")
 206                        (VSHLLTQ_N_U "u") (VSHLLTQ_N_S "s") (VRMLALDAVHQ_U "u")
 207                        (VRMLALDAVHQ_S "s") (VBICQ_M_N_S "s") (VBICQ_M_N_U "u")
 208                        (VCVTAQ_M_S "s") (VCVTAQ_M_U "u") (VCVTQ_M_TO_F_S "s")
 209                        (VCVTQ_M_TO_F_U "u") (VQRSHRNBQ_N_S "s")
 210                        (VQRSHRNBQ_N_U "u") (VABAVQ_S "s") (VABAVQ_U "u")
 211                        (VRMLALDAVHAQ_U "u") (VRMLALDAVHAQ_S "s") (VSHLCQ_S "s")
 212                        (VSHLCQ_U "u") (VADDVAQ_P_S "s") (VADDVAQ_P_U "u")
 213                        (VCLZQ_M_S "s") (VCLZQ_M_U "u") (VCMPEQQ_M_N_S "s")
 214                        (VCMPEQQ_M_N_U "u") (VCMPEQQ_M_S "s") (VCMPEQQ_M_U "u")
 215                        (VCMPNEQ_M_N_S "s") (VCMPNEQ_M_N_U "u") (VCMPNEQ_M_S "s")
 216                        (VCMPNEQ_M_U "u") (VDUPQ_M_N_S "s") (VDUPQ_M_N_U "u")
 217                        (VMAXVQ_P_S "s") (VMAXVQ_P_U "u") (VMINVQ_P_S "s")
 218                        (VMINVQ_P_U "u") (VMLADAVAQ_S "s") (VMLADAVAQ_U "u")
 219                        (VMLADAVQ_P_S "s") (VMLADAVQ_P_U "u") (VMLAQ_N_S "s")
 220                        (VMLAQ_N_U "u") (VMLASQ_N_S "s") (VMLASQ_N_U "u")
 221                        (VMVNQ_M_S "s") (VMVNQ_M_U "u") (VPSELQ_S "s")
 222                        (VPSELQ_U "u") (VQDMLAHQ_N_S "s") (VQDMLAHQ_N_U "u")
 223                        (VQRDMLAHQ_N_S "s") (VQRDMLAHQ_N_U "u")
 224                        (VQRDMLASHQ_N_S "s") (VQRDMLASHQ_N_U "u")
 225                        (VQRSHLQ_M_N_S "s") (VQRSHLQ_M_N_U "u")
 226                        (VQSHLQ_M_R_S "s") (VQSHLQ_M_R_U "u") (VSRIQ_N_S "s")
 227                        (VREV64Q_M_S "s") (VREV64Q_M_U "u") (VSRIQ_N_U "u")
 228                        (VRSHLQ_M_N_S "s") (VRSHLQ_M_N_U "u") (VSHLQ_M_R_S "s")
 229                        (VSHLQ_M_R_U "u") (VSLIQ_N_S "s") (VSLIQ_N_U "u")
 230                        (VMLALDAVQ_P_S "s") (VQMOVNBQ_M_S "s") (VMOVLTQ_M_S "s")
 231                        (VMOVNBQ_M_S "s") (VRSHRNTQ_N_S "s") (VORRQ_M_N_S "s")
 232                        (VREV32Q_M_S "s") (VQRSHRNTQ_N_S "s") (VMOVNTQ_M_S "s")
 233                        (VMOVLBQ_M_S "s") (VMLALDAVAQ_S "s") (VQSHRNBQ_N_S "s")
 234                        (VSHRNBQ_N_S "s") (VRSHRNBQ_N_S "s") (VMLALDAVXQ_P_S "s")
 235                        (VQMOVNTQ_M_S "s") (VMVNQ_M_N_S "s") (VQSHRNTQ_N_S "s")
 236                        (VMLALDAVAXQ_S "s") (VSHRNTQ_N_S "s") (VMLALDAVQ_P_U "u")
 237                        (VQMOVNBQ_M_U "u") (VMOVLTQ_M_U "u") (VMOVNBQ_M_U "u")
 238                        (VRSHRNTQ_N_U "u") (VORRQ_M_N_U "u") (VREV32Q_M_U "u")
 239                        (VREV16Q_M_S "s") (VREV16Q_M_U "u")
 240                        (VQRSHRNTQ_N_U "u") (VMOVNTQ_M_U "u") (VMOVLBQ_M_U "u")
 241                        (VMLALDAVAQ_U "u") (VQSHRNBQ_N_U "u") (VSHRNBQ_N_U "u")
 242                        (VRSHRNBQ_N_U "u") (VMLALDAVXQ_P_U "u")
 243                        (VMVNQ_M_N_U "u") (VQSHRNTQ_N_U "u") (VMLALDAVAXQ_U "u")
 244                        (VQMOVNTQ_M_U "u") (VSHRNTQ_N_U "u") (VCVTMQ_M_S "s")
 245                        (VCVTMQ_M_U "u") (VCVTNQ_M_S "s") (VCVTNQ_M_U "u")
 246                        (VCVTPQ_M_S "s") (VCVTPQ_M_U "u") (VADDLVAQ_P_S "s")
 247                        (VCVTQ_M_N_FROM_F_U "u") (VCVTQ_M_FROM_F_S "s")
 248                        (VCVTQ_M_FROM_F_U "u") (VRMLALDAVHQ_P_U "u")
 249                        (VRMLALDAVHQ_P_S "s") (VADDLVAQ_P_U "u")
 250                        (VCVTQ_M_N_FROM_F_S "s") (VABAVQ_P_U "u")
 251                        (VABAVQ_P_S "s") (VSHLQ_M_S "s") (VSHLQ_M_U "u")
 252                        (VSRIQ_M_N_S "s") (VSRIQ_M_N_U "u") (VSUBQ_M_S "s")
 253                        (VSUBQ_M_U "u") (VCVTQ_M_N_TO_F_S "s")
 254                        (VCVTQ_M_N_TO_F_U "u")])
 255
 256 (define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32")
 257                         (VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16")
 258                         (VCTP32Q_M "32") (VCTP64Q_M "64")])
 259 (define_mode_attr MVE_pred2 [(V16QI "mve_imm_8") (V8HI "mve_imm_16")
 260                              (V4SI "mve_imm_32")])
 261 (define_mode_attr MVE_constraint2 [(V16QI "Rb") (V8HI "Rd") (V4SI "Rf")])
 262 (define_mode_attr MVE_LANES [(V16QI "16") (V8HI "8") (V4SI "4")])
 263 (define_mode_attr MVE_constraint [ (V16QI "Ra") (V8HI "Rc") (V4SI "Re")])
 264 (define_mode_attr MVE_pred [ (V16QI "mve_imm_7") (V8HI "mve_imm_15")
 265                                    (V4SI "mve_imm_31")])
 266 (define_mode_attr MVE_constraint3 [ (V8HI "Rb") (V4SI "Rd")])
 267 (define_mode_attr MVE_pred3 [ (V8HI "mve_imm_8") (V4SI "mve_imm_16")])
 268
 269 (define_mode_attr MVE_constraint1 [ (V8HI "Ra") (V4SI "Rc")])
 270 (define_mode_attr MVE_pred1 [ (V8HI "mve_imm_7") (V4SI "mve_imm_15")])
 271
 272 (define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U])
 273 (define_int_iterator VMVNQ_N [VMVNQ_N_U VMVNQ_N_S])
 274 (define_int_iterator VREV64Q [VREV64Q_S VREV64Q_U])
 275 (define_int_iterator VCVTQ_FROM_F [VCVTQ_FROM_F_S VCVTQ_FROM_F_U])
 276 (define_int_iterator VREV16Q [VREV16Q_U VREV16Q_S])
 277 (define_int_iterator VCVTAQ [VCVTAQ_U VCVTAQ_S])
 278 (define_int_iterator VMVNQ [VMVNQ_U VMVNQ_S])
 279 (define_int_iterator VDUPQ_N [VDUPQ_N_U VDUPQ_N_S])
 280 (define_int_iterator VCLZQ [VCLZQ_U VCLZQ_S])
 281 (define_int_iterator VADDVQ [VADDVQ_U VADDVQ_S])
 282 (define_int_iterator VREV32Q [VREV32Q_U VREV32Q_S])
 283 (define_int_iterator VMOVLBQ [VMOVLBQ_S VMOVLBQ_U])
 284 (define_int_iterator VMOVLTQ [VMOVLTQ_U VMOVLTQ_S])
 285 (define_int_iterator VCVTPQ [VCVTPQ_S VCVTPQ_U])
 286 (define_int_iterator VCVTNQ [VCVTNQ_S VCVTNQ_U])
 287 (define_int_iterator VCVTMQ [VCVTMQ_S VCVTMQ_U])
 288 (define_int_iterator VADDLVQ [VADDLVQ_U VADDLVQ_S])
 289 (define_int_iterator VCTPQ [VCTP8Q VCTP16Q VCTP32Q VCTP64Q])
 290 (define_int_iterator VCTPQ_M [VCTP8Q_M VCTP16Q_M VCTP32Q_M VCTP64Q_M])
 291 (define_int_iterator VCVTQ_N_TO_F [VCVTQ_N_TO_F_S VCVTQ_N_TO_F_U])
 292 (define_int_iterator VCREATEQ [VCREATEQ_U VCREATEQ_S])
 293 (define_int_iterator VSHRQ_N [VSHRQ_N_S VSHRQ_N_U])
 294 (define_int_iterator VCVTQ_N_FROM_F [VCVTQ_N_FROM_F_S VCVTQ_N_FROM_F_U])
 295 (define_int_iterator VADDLVQ_P [VADDLVQ_P_S VADDLVQ_P_U])
 296 (define_int_iterator VCMPNEQ [VCMPNEQ_U VCMPNEQ_S])
 297 (define_int_iterator VSHLQ [VSHLQ_S VSHLQ_U])
 298 (define_int_iterator VABDQ [VABDQ_S VABDQ_U])
 299 (define_int_iterator VADDQ_N [VADDQ_N_S VADDQ_N_U])
 300 (define_int_iterator VADDVAQ [VADDVAQ_S VADDVAQ_U])
 301 (define_int_iterator VADDVQ_P [VADDVQ_P_U VADDVQ_P_S])
 302 (define_int_iterator VANDQ [VANDQ_U VANDQ_S])
 303 (define_int_iterator VBICQ [VBICQ_S VBICQ_U])
 304 (define_int_iterator VBRSRQ_N [VBRSRQ_N_U VBRSRQ_N_S])
 305 (define_int_iterator VCADDQ_ROT270 [VCADDQ_ROT270_S VCADDQ_ROT270_U])
 306 (define_int_iterator VCADDQ_ROT90 [VCADDQ_ROT90_U VCADDQ_ROT90_S])
 307 (define_int_iterator VCMPEQQ [VCMPEQQ_U VCMPEQQ_S])
 308 (define_int_iterator VCMPEQQ_N [VCMPEQQ_N_S VCMPEQQ_N_U])
 309 (define_int_iterator VCMPNEQ_N [VCMPNEQ_N_U VCMPNEQ_N_S])
 310 (define_int_iterator VEORQ [VEORQ_U VEORQ_S])
 311 (define_int_iterator VHADDQ [VHADDQ_S VHADDQ_U])
 312 (define_int_iterator VHADDQ_N [VHADDQ_N_U VHADDQ_N_S])
 313 (define_int_iterator VHSUBQ [VHSUBQ_S VHSUBQ_U])
 314 (define_int_iterator VHSUBQ_N [VHSUBQ_N_U VHSUBQ_N_S])
 315 (define_int_iterator VMAXQ [VMAXQ_U VMAXQ_S])
 316 (define_int_iterator VMAXVQ [VMAXVQ_U VMAXVQ_S])
 317 (define_int_iterator VMINQ [VMINQ_S VMINQ_U])
 318 (define_int_iterator VMINVQ [VMINVQ_U VMINVQ_S])
 319 (define_int_iterator VMLADAVQ [VMLADAVQ_U VMLADAVQ_S])
 320 (define_int_iterator VMULHQ [VMULHQ_S VMULHQ_U])
 321 (define_int_iterator VMULLBQ_INT [VMULLBQ_INT_U VMULLBQ_INT_S])
 322 (define_int_iterator VMULLTQ_INT [VMULLTQ_INT_U VMULLTQ_INT_S])
 323 (define_int_iterator VMULQ [VMULQ_U VMULQ_S])
 324 (define_int_iterator VMULQ_N [VMULQ_N_U VMULQ_N_S])
 325 (define_int_iterator VORNQ [VORNQ_U VORNQ_S])
 326 (define_int_iterator VORRQ [VORRQ_S VORRQ_U])
 327 (define_int_iterator VQADDQ [VQADDQ_U VQADDQ_S])
 328 (define_int_iterator VQADDQ_N [VQADDQ_N_S VQADDQ_N_U])
 329 (define_int_iterator VQRSHLQ [VQRSHLQ_S VQRSHLQ_U])
 330 (define_int_iterator VQRSHLQ_N [VQRSHLQ_N_S VQRSHLQ_N_U])
 331 (define_int_iterator VQSHLQ [VQSHLQ_S VQSHLQ_U])
 332 (define_int_iterator VQSHLQ_N [VQSHLQ_N_S VQSHLQ_N_U])
 333 (define_int_iterator VQSHLQ_R [VQSHLQ_R_U VQSHLQ_R_S])
 334 (define_int_iterator VQSUBQ [VQSUBQ_U VQSUBQ_S])
 335 (define_int_iterator VQSUBQ_N [VQSUBQ_N_S VQSUBQ_N_U])
 336 (define_int_iterator VRHADDQ [VRHADDQ_S VRHADDQ_U])
 337 (define_int_iterator VRMULHQ [VRMULHQ_S VRMULHQ_U])
 338 (define_int_iterator VRSHLQ [VRSHLQ_S VRSHLQ_U])
 339 (define_int_iterator VRSHLQ_N [VRSHLQ_N_U VRSHLQ_N_S])
 340 (define_int_iterator VRSHRQ_N [VRSHRQ_N_S VRSHRQ_N_U])
 341 (define_int_iterator VSHLQ_N [VSHLQ_N_U VSHLQ_N_S])
 342 (define_int_iterator VSHLQ_R [VSHLQ_R_S VSHLQ_R_U])
 343 (define_int_iterator VSUBQ [VSUBQ_S VSUBQ_U])
 344 (define_int_iterator VSUBQ_N [VSUBQ_N_S VSUBQ_N_U])
 345 (define_int_iterator VADDLVAQ [VADDLVAQ_S VADDLVAQ_U])
 346 (define_int_iterator VBICQ_N [VBICQ_N_S VBICQ_N_U])
 347 (define_int_iterator VMLALDAVQ [VMLALDAVQ_U VMLALDAVQ_S])
 348 (define_int_iterator VMLALDAVXQ [VMLALDAVXQ_U VMLALDAVXQ_S])
 349 (define_int_iterator VMOVNBQ [VMOVNBQ_U VMOVNBQ_S])
 350 (define_int_iterator VMOVNTQ [VMOVNTQ_S VMOVNTQ_U])
 351 (define_int_iterator VORRQ_N [VORRQ_N_U VORRQ_N_S])
 352 (define_int_iterator VQMOVNBQ [VQMOVNBQ_U VQMOVNBQ_S])
 353 (define_int_iterator VQMOVNTQ [VQMOVNTQ_U VQMOVNTQ_S])
 354 (define_int_iterator VSHLLBQ_N [VSHLLBQ_N_S VSHLLBQ_N_U])
 355 (define_int_iterator VSHLLTQ_N [VSHLLTQ_N_U VSHLLTQ_N_S])
 356 (define_int_iterator VRMLALDAVHQ [VRMLALDAVHQ_U VRMLALDAVHQ_S])
 357 (define_int_iterator VBICQ_M_N [VBICQ_M_N_S VBICQ_M_N_U])
 358 (define_int_iterator VCVTAQ_M [VCVTAQ_M_S VCVTAQ_M_U])
 359 (define_int_iterator VCVTQ_M_TO_F [VCVTQ_M_TO_F_S VCVTQ_M_TO_F_U])
 360 (define_int_iterator VQRSHRNBQ_N [VQRSHRNBQ_N_U VQRSHRNBQ_N_S])
 361 (define_int_iterator VABAVQ [VABAVQ_S VABAVQ_U])
 362 (define_int_iterator VSHLCQ [VSHLCQ_S VSHLCQ_U])
 363 (define_int_iterator VRMLALDAVHAQ [VRMLALDAVHAQ_S VRMLALDAVHAQ_U])
 364 (define_int_iterator VADDVAQ_P [VADDVAQ_P_S VADDVAQ_P_U])
 365 (define_int_iterator VCLZQ_M [VCLZQ_M_S VCLZQ_M_U])
 366 (define_int_iterator VCMPEQQ_M_N [VCMPEQQ_M_N_S VCMPEQQ_M_N_U])
 367 (define_int_iterator VCMPEQQ_M [VCMPEQQ_M_S VCMPEQQ_M_U])
 368 (define_int_iterator VCMPNEQ_M_N [VCMPNEQ_M_N_S VCMPNEQ_M_N_U])
 369 (define_int_iterator VCMPNEQ_M [VCMPNEQ_M_S VCMPNEQ_M_U])
 370 (define_int_iterator VDUPQ_M_N [VDUPQ_M_N_S VDUPQ_M_N_U])
 371 (define_int_iterator VMAXVQ_P [VMAXVQ_P_S VMAXVQ_P_U])
 372 (define_int_iterator VMINVQ_P [VMINVQ_P_S VMINVQ_P_U])
 373 (define_int_iterator VMLADAVAQ [VMLADAVAQ_S VMLADAVAQ_U])
 374 (define_int_iterator VMLADAVQ_P [VMLADAVQ_P_S VMLADAVQ_P_U])
 375 (define_int_iterator VMLAQ_N [VMLAQ_N_S VMLAQ_N_U])
 376 (define_int_iterator VMLASQ_N [VMLASQ_N_S VMLASQ_N_U])
 377 (define_int_iterator VMVNQ_M [VMVNQ_M_S VMVNQ_M_U])
 378 (define_int_iterator VPSELQ [VPSELQ_S VPSELQ_U])
 379 (define_int_iterator VQDMLAHQ_N [VQDMLAHQ_N_S VQDMLAHQ_N_U])
 380 (define_int_iterator VQRDMLAHQ_N [VQRDMLAHQ_N_S VQRDMLAHQ_N_U])
 381 (define_int_iterator VQRDMLASHQ_N [VQRDMLASHQ_N_S VQRDMLASHQ_N_U])
 382 (define_int_iterator VQRSHLQ_M_N [VQRSHLQ_M_N_S VQRSHLQ_M_N_U])
 383 (define_int_iterator VQSHLQ_M_R [VQSHLQ_M_R_S VQSHLQ_M_R_U])
 384 (define_int_iterator VREV64Q_M [VREV64Q_M_S VREV64Q_M_U])
 385 (define_int_iterator VRSHLQ_M_N [VRSHLQ_M_N_S VRSHLQ_M_N_U])
 386 (define_int_iterator VSHLQ_M_R [VSHLQ_M_R_S VSHLQ_M_R_U])
 387 (define_int_iterator VSLIQ_N [VSLIQ_N_S VSLIQ_N_U])
 388 (define_int_iterator VSRIQ_N [VSRIQ_N_S VSRIQ_N_U])
 389 (define_int_iterator VMLALDAVQ_P [VMLALDAVQ_P_U VMLALDAVQ_P_S])
 390 (define_int_iterator VQMOVNBQ_M [VQMOVNBQ_M_S VQMOVNBQ_M_U])
 391 (define_int_iterator VMOVLTQ_M [VMOVLTQ_M_U VMOVLTQ_M_S])
 392 (define_int_iterator VMOVNBQ_M [VMOVNBQ_M_U VMOVNBQ_M_S])
 393 (define_int_iterator VRSHRNTQ_N [VRSHRNTQ_N_U VRSHRNTQ_N_S])
 394 (define_int_iterator VORRQ_M_N [VORRQ_M_N_S VORRQ_M_N_U])
 395 (define_int_iterator VREV32Q_M [VREV32Q_M_S VREV32Q_M_U])
 396 (define_int_iterator VREV16Q_M [VREV16Q_M_S VREV16Q_M_U])
 397 (define_int_iterator VQRSHRNTQ_N [VQRSHRNTQ_N_U VQRSHRNTQ_N_S])
 398 (define_int_iterator VMOVNTQ_M [VMOVNTQ_M_U VMOVNTQ_M_S])
 399 (define_int_iterator VMOVLBQ_M [VMOVLBQ_M_U VMOVLBQ_M_S])
 400 (define_int_iterator VMLALDAVAQ [VMLALDAVAQ_S VMLALDAVAQ_U])
 401 (define_int_iterator VQSHRNBQ_N [VQSHRNBQ_N_U VQSHRNBQ_N_S])
 402 (define_int_iterator VSHRNBQ_N [VSHRNBQ_N_U VSHRNBQ_N_S])
 403 (define_int_iterator VRSHRNBQ_N [VRSHRNBQ_N_S VRSHRNBQ_N_U])
 404 (define_int_iterator VMLALDAVXQ_P [VMLALDAVXQ_P_U VMLALDAVXQ_P_S])
 405 (define_int_iterator VQMOVNTQ_M [VQMOVNTQ_M_U VQMOVNTQ_M_S])
 406 (define_int_iterator VMVNQ_M_N [VMVNQ_M_N_U VMVNQ_M_N_S])
 407 (define_int_iterator VQSHRNTQ_N [VQSHRNTQ_N_U VQSHRNTQ_N_S])
 408 (define_int_iterator VMLALDAVAXQ [VMLALDAVAXQ_S VMLALDAVAXQ_U])
 409 (define_int_iterator VSHRNTQ_N [VSHRNTQ_N_S VSHRNTQ_N_U])
 410 (define_int_iterator VCVTMQ_M [VCVTMQ_M_S VCVTMQ_M_U])
 411 (define_int_iterator VCVTNQ_M [VCVTNQ_M_S VCVTNQ_M_U])
 412 (define_int_iterator VCVTPQ_M [VCVTPQ_M_S VCVTPQ_M_U])
 413 (define_int_iterator VCVTQ_M_N_FROM_F [VCVTQ_M_N_FROM_F_S VCVTQ_M_N_FROM_F_U])
 414 (define_int_iterator VCVTQ_M_FROM_F [VCVTQ_M_FROM_F_U VCVTQ_M_FROM_F_S])
 415 (define_int_iterator VRMLALDAVHQ_P [VRMLALDAVHQ_P_S VRMLALDAVHQ_P_U])
 416 (define_int_iterator VADDLVAQ_P [VADDLVAQ_P_U VADDLVAQ_P_S])
 417 (define_int_iterator VABAVQ_P [VABAVQ_P_S VABAVQ_P_U])
 418 (define_int_iterator VSHLQ_M [VSHLQ_M_S VSHLQ_M_U])
 419 (define_int_iterator VSRIQ_M_N [VSRIQ_M_N_S VSRIQ_M_N_U])
 420 (define_int_iterator VSUBQ_M [VSUBQ_M_U VSUBQ_M_S])
 421 (define_int_iterator VCVTQ_M_N_TO_F [VCVTQ_M_N_TO_F_U VCVTQ_M_N_TO_F_S])
 422
 423 (define_insn "*mve_mov<mode>"
 424   [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us")
 425         (match_operand:MVE_types 1 "general_operand" "w,r,w,Dn,Usi,r,Dm,w"))]
 426   "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT"
 427 {
 428   if (which_alternative == 3 || which_alternative == 6)
 429     {
 430       int width, is_valid;
 431       static char templ[40];
 432
 433       is_valid = simd_immediate_valid_for_move (operands[1], <MODE>mode,
 434         &operands[1], &width);
 435
 436       gcc_assert (is_valid != 0);
 437
 438       if (width == 0)
 439         return "vmov.f32\t%q0, %1  @ <mode>";
 440       else
 441         sprintf (templ, "vmov.i%d\t%%q0, %%x1  @ <mode>", width);
 442       return templ;
 443     }
 444   switch (which_alternative)
 445     {
 446     case 0:
 447       return "vmov\t%q0, %q1";
 448     case 1:
 449       return "vmov\t%e0, %Q1, %R1  @ <mode>\;vmov\t%f0, %J1, %K1";
 450     case 2:
 451       return "vmov\t%Q0, %R0, %e1  @ <mode>\;vmov\t%J0, %K0, %f1";
 452     case 4:
 453       if ((TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))
 454           || (MEM_P (operands[1])
 455               && GET_CODE (XEXP (operands[1], 0)) == LABEL_REF))
 456         return output_move_neon (operands);
 457       else
 458         return "vldrb.8 %q0, %E1";
 459     case 5:
 460       return output_move_neon (operands);
 461     case 7:
 462       return "vstrb.8 %q1, %E0";
 463     default:
 464       gcc_unreachable ();
 465       return "";
 466     }
 467 }
 468   [(set_attr "type" "mve_move,mve_move,mve_move,mve_move,mve_load,mve_move,mve_move,mve_store")
 469    (set_attr "length" "4,8,8,4,8,8,4,4")
 470    (set_attr "thumb2_pool_range" "*,*,*,*,1018,*,*,*")
 471    (set_attr "neg_pool_range" "*,*,*,*,996,*,*,*")])
 472
 473 (define_insn "*mve_mov<mode>"
 474   [(set (match_operand:MVE_types 0 "s_register_operand" "=w,w")
 475         (vec_duplicate:MVE_types
 476           (match_operand:SI 1 "nonmemory_operand" "r,i")))]
 477   "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT"
 478 {
 479   if (which_alternative == 0)
 480     return "vdup.<V_sz_elem>\t%q0, %1";
 481   return "vmov.<V_sz_elem>\t%q0, %1";
 482 }
 483   [(set_attr "length" "4,4")
 484    (set_attr "type" "mve_move,mve_move")])
 485
 486 ;;
 487 ;; [vst4q])
 488 ;;
 489 (define_insn "mve_vst4q<mode>"
 490   [(set (match_operand:XI 0 "neon_struct_operand" "=Um")
 491         (unspec:XI [(match_operand:XI 1 "s_register_operand" "w")
 492                     (unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
 493          VST4Q))
 494   ]
 495   "TARGET_HAVE_MVE"
 496 {
 497    rtx ops[6];
 498    int regno = REGNO (operands[1]);
 499    ops[0] = gen_rtx_REG (TImode, regno);
 500    ops[1] = gen_rtx_REG (TImode, regno+4);
 501    ops[2] = gen_rtx_REG (TImode, regno+8);
 502    ops[3] = gen_rtx_REG (TImode, regno+12);
 503    rtx reg  = operands[0];
 504    while (reg && !REG_P (reg))
 505     reg = XEXP (reg, 0);
 506    gcc_assert (REG_P (reg));
 507    ops[4] = reg;
 508    ops[5] = operands[0];
 509    /* Here in first three instructions data is stored to ops[4]'s location but
 510       in the fourth instruction data is stored to operands[0], this is to
 511       support the writeback.  */
 512    output_asm_insn ("vst40.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t"
 513                     "vst41.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t"
 514                     "vst42.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t"
 515                     "vst43.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, %5", ops);
 516    return "";
 517 }
 518   [(set_attr "length" "16")])
 519
 520 ;;
 521 ;; [vrndq_m_f])
 522 ;;
 523 (define_insn "mve_vrndq_m_f<mode>"
 524   [
 525    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
 526         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
 527                        (match_operand:MVE_0 2 "s_register_operand" "w")
 528                        (match_operand:HI 3 "vpr_register_operand" "Up")]
 529          VRNDQ_M_F))
 530   ]
 531   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
 532   "vpst\;vrintzt.f%#<V_sz_elem> %q0, %q2"
 533   [(set_attr "type" "mve_move")
 534    (set_attr "length""8")])
 535
 536 ;;
 537 ;; [vrndxq_f])
 538 ;;
 539 (define_insn "mve_vrndxq_f<mode>"
 540   [
 541    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
 542         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
 543          VRNDXQ_F))
 544   ]
 545   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
 546   "vrintx.f%#<V_sz_elem>        %q0, %q1"
 547   [(set_attr "type" "mve_move")
 548 ])
 549
 550 ;;
 551 ;; [vrndq_f])
 552 ;;
 553 (define_insn "mve_vrndq_f<mode>"
 554   [
 555    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
 556         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
 557          VRNDQ_F))
 558   ]
 559   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
 560   "vrintz.f%#<V_sz_elem>        %q0, %q1"
 561   [(set_attr "type" "mve_move")
 562 ])
 563
 564 ;;
 565 ;; [vrndpq_f])
 566 ;;
 567 (define_insn "mve_vrndpq_f<mode>"
 568   [
 569    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
 570         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
 571          VRNDPQ_F))
 572   ]
 573   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
 574   "vrintp.f%#<V_sz_elem>        %q0, %q1"
 575   [(set_attr "type" "mve_move")
 576 ])
 577
 578 ;;
 579 ;; [vrndnq_f])
 580 ;;
 581 (define_insn "mve_vrndnq_f<mode>"
 582   [
 583    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
 584         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
 585          VRNDNQ_F))
 586   ]
 587   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
 588   "vrintn.f%#<V_sz_elem>        %q0, %q1"
 589   [(set_attr "type" "mve_move")
 590 ])
 591
 592 ;;
 593 ;; [vrndmq_f])
 594 ;;
 595 (define_insn "mve_vrndmq_f<mode>"
 596   [
 597    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
 598         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
 599          VRNDMQ_F))
 600   ]
 601   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
 602   "vrintm.f%#<V_sz_elem>        %q0, %q1"
 603   [(set_attr "type" "mve_move")
 604 ])
 605
 606 ;;
 607 ;; [vrndaq_f])
 608 ;;
 609 (define_insn "mve_vrndaq_f<mode>"
 610   [
 611    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
 612         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
 613          VRNDAQ_F))
 614   ]
 615   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
 616   "vrinta.f%#<V_sz_elem>        %q0, %q1"
 617   [(set_attr "type" "mve_move")
 618 ])
 619
 620 ;;
 621 ;; [vrev64q_f])
 622 ;;
 623 (define_insn "mve_vrev64q_f<mode>"
 624   [
 625    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
 626         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
 627          VREV64Q_F))
 628   ]
 629   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
 630   "vrev64.%#<V_sz_elem> %q0, %q1"
 631   [(set_attr "type" "mve_move")
 632 ])
 633
 634 ;;
 635 ;; [vnegq_f])
 636 ;;
 637 (define_insn "mve_vnegq_f<mode>"
 638   [
 639    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
 640         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
 641          VNEGQ_F))
 642   ]
 643   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
 644   "vneg.f%#<V_sz_elem>  %q0, %q1"
 645   [(set_attr "type" "mve_move")
 646 ])
 647
 648 ;;
 649 ;; [vdupq_n_f])
 650 ;;
 651 (define_insn "mve_vdupq_n_f<mode>"
 652   [
 653    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
 654         (unspec:MVE_0 [(match_operand:<V_elem> 1 "s_register_operand" "r")]
 655          VDUPQ_N_F))
 656   ]
 657   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
 658   "vdup.%#<V_sz_elem>   %q0, %1"
 659   [(set_attr "type" "mve_move")
 660 ])
 661
 662 ;;
 663 ;; [vabsq_f])
 664 ;;
 665 (define_insn "mve_vabsq_f<mode>"
 666   [
 667    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
 668         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
 669          VABSQ_F))
 670   ]
 671   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
 672   "vabs.f%#<V_sz_elem>  %q0, %q1"
 673   [(set_attr "type" "mve_move")
 674 ])
 675
 676 ;;
 677 ;; [vrev32q_f])
 678 ;;
 679 (define_insn "mve_vrev32q_fv8hf"
 680   [
 681    (set (match_operand:V8HF 0 "s_register_operand" "=w")
 682         (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "w")]
 683          VREV32Q_F))
 684   ]
 685   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
 686   "vrev32.16 %q0, %q1"
 687   [(set_attr "type" "mve_move")
 688 ])
 689 ;;
 690 ;; [vcvttq_f32_f16])
 691 ;;
 692 (define_insn "mve_vcvttq_f32_f16v4sf"
 693   [
 694    (set (match_operand:V4SF 0 "s_register_operand" "=w")
 695         (unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")]
 696          VCVTTQ_F32_F16))
 697   ]
 698   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
 699   "vcvtt.f32.f16 %q0, %q1"
 700   [(set_attr "type" "mve_move")
 701 ])
 702
 703 ;;
 704 ;; [vcvtbq_f32_f16])
 705 ;;
 706 (define_insn "mve_vcvtbq_f32_f16v4sf"
 707   [
 708    (set (match_operand:V4SF 0 "s_register_operand" "=w")
 709         (unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")]
 710          VCVTBQ_F32_F16))
 711   ]
 712   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
 713   "vcvtb.f32.f16 %q0, %q1"
 714   [(set_attr "type" "mve_move")
 715 ])
 716
 717 ;;
 718 ;; [vcvtq_to_f_s, vcvtq_to_f_u])
 719 ;;
 720 (define_insn "mve_vcvtq_to_f_<supf><mode>"
 721   [
 722    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
 723         (unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
 724          VCVTQ_TO_F))
 725   ]
 726   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
 727   "vcvt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>       %q0, %q1"
 728   [(set_attr "type" "mve_move")
 729 ])
 730
 731 ;;
 732 ;; [vrev64q_u, vrev64q_s])
 733 ;;
 734 (define_insn "mve_vrev64q_<supf><mode>"
 735   [
 736    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
 737         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
 738          VREV64Q))
 739   ]
 740   "TARGET_HAVE_MVE"
 741   "vrev64.%#<V_sz_elem> %q0, %q1"
 742   [(set_attr "type" "mve_move")
 743 ])
 744
 745 ;;
 746 ;; [vcvtq_from_f_s, vcvtq_from_f_u])
 747 ;;
 748 (define_insn "mve_vcvtq_from_f_<supf><mode>"
 749   [
 750    (set (match_operand:MVE_5 0 "s_register_operand" "=w")
 751         (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
 752          VCVTQ_FROM_F))
 753   ]
 754   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
 755   "vcvt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>       %q0, %q1"
 756   [(set_attr "type" "mve_move")
 757 ])
 758 ;; [vqnegq_s])
 759 ;;
 760 (define_insn "mve_vqnegq_s<mode>"
 761   [
 762    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
 763         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
 764          VQNEGQ_S))
 765   ]
 766   "TARGET_HAVE_MVE"
 767   "vqneg.s%#<V_sz_elem> %q0, %q1"
 768   [(set_attr "type" "mve_move")
 769 ])
 770
 771 ;;
 772 ;; [vqabsq_s])
 773 ;;
 774 (define_insn "mve_vqabsq_s<mode>"
 775   [
 776    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
 777         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
 778          VQABSQ_S))
 779   ]
 780   "TARGET_HAVE_MVE"
 781   "vqabs.s%#<V_sz_elem> %q0, %q1"
 782   [(set_attr "type" "mve_move")
 783 ])
 784
 785 ;;
 786 ;; [vnegq_s])
 787 ;;
 788 (define_insn "mve_vnegq_s<mode>"
 789   [
 790    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
 791         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
 792          VNEGQ_S))
 793   ]
 794   "TARGET_HAVE_MVE"
 795   "vneg.s%#<V_sz_elem>  %q0, %q1"
 796   [(set_attr "type" "mve_move")
 797 ])
 798
 799 ;;
 800 ;; [vmvnq_u, vmvnq_s])
 801 ;;
 802 (define_insn "mve_vmvnq_<supf><mode>"
 803   [
 804    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
 805         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
 806          VMVNQ))
 807   ]
 808   "TARGET_HAVE_MVE"
 809   "vmvn %q0, %q1"
 810   [(set_attr "type" "mve_move")
 811 ])
 812
 813 ;;
 814 ;; [vdupq_n_u, vdupq_n_s])
 815 ;;
 816 (define_insn "mve_vdupq_n_<supf><mode>"
 817   [
 818    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
 819         (unspec:MVE_2 [(match_operand:<V_elem> 1 "s_register_operand" "r")]
 820          VDUPQ_N))
 821   ]
 822   "TARGET_HAVE_MVE"
 823   "vdup.%#<V_sz_elem>   %q0, %1"
 824   [(set_attr "type" "mve_move")
 825 ])
 826
 827 ;;
 828 ;; [vclzq_u, vclzq_s])
 829 ;;
 830 (define_insn "mve_vclzq_<supf><mode>"
 831   [
 832    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
 833         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
 834          VCLZQ))
 835   ]
 836   "TARGET_HAVE_MVE"
 837   "vclz.i%#<V_sz_elem>  %q0, %q1"
 838   [(set_attr "type" "mve_move")
 839 ])
 840
 841 ;;
 842 ;; [vclsq_s])
 843 ;;
 844 (define_insn "mve_vclsq_s<mode>"
 845   [
 846    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
 847         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
 848          VCLSQ_S))
 849   ]
 850   "TARGET_HAVE_MVE"
 851   "vcls.s%#<V_sz_elem>  %q0, %q1"
 852   [(set_attr "type" "mve_move")
 853 ])
 854
 855 ;;
 856 ;; [vaddvq_s, vaddvq_u])
 857 ;;
 858 (define_insn "mve_vaddvq_<supf><mode>"
 859   [
 860    (set (match_operand:SI 0 "s_register_operand" "=e")
 861         (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")]
 862          VADDVQ))
 863   ]
 864   "TARGET_HAVE_MVE"
 865   "vaddv.<supf>%#<V_sz_elem>\t%0, %q1"
 866   [(set_attr "type" "mve_move")
 867 ])
 868
 869 ;;
 870 ;; [vabsq_s])
 871 ;;
 872 (define_insn "mve_vabsq_s<mode>"
 873   [
 874    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
 875         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
 876          VABSQ_S))
 877   ]
 878   "TARGET_HAVE_MVE"
 879   "vabs.s%#<V_sz_elem>\t%q0, %q1"
 880   [(set_attr "type" "mve_move")
 881 ])
 882
 883 ;;
 884 ;; [vrev32q_u, vrev32q_s])
 885 ;;
 886 (define_insn "mve_vrev32q_<supf><mode>"
 887   [
 888    (set (match_operand:MVE_3 0 "s_register_operand" "=w")
 889         (unspec:MVE_3 [(match_operand:MVE_3 1 "s_register_operand" "w")]
 890          VREV32Q))
 891   ]
 892   "TARGET_HAVE_MVE"
 893   "vrev32.%#<V_sz_elem>\t%q0, %q1"
 894   [(set_attr "type" "mve_move")
 895 ])
 896
 897 ;;
 898 ;; [vmovltq_u, vmovltq_s])
 899 ;;
 900 (define_insn "mve_vmovltq_<supf><mode>"
 901   [
 902    (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
 903         (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")]
 904          VMOVLTQ))
 905   ]
 906   "TARGET_HAVE_MVE"
 907   "vmovlt.<supf>%#<V_sz_elem>   %q0, %q1"
 908   [(set_attr "type" "mve_move")
 909 ])
 910
 911 ;;
 912 ;; [vmovlbq_s, vmovlbq_u])
 913 ;;
 914 (define_insn "mve_vmovlbq_<supf><mode>"
 915   [
 916    (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
 917         (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")]
 918          VMOVLBQ))
 919   ]
 920   "TARGET_HAVE_MVE"
 921   "vmovlb.<supf>%#<V_sz_elem>   %q0, %q1"
 922   [(set_attr "type" "mve_move")
 923 ])
 924
 925 ;;
 926 ;; [vcvtpq_s, vcvtpq_u])
 927 ;;
 928 (define_insn "mve_vcvtpq_<supf><mode>"
 929   [
 930    (set (match_operand:MVE_5 0 "s_register_operand" "=w")
 931         (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
 932          VCVTPQ))
 933   ]
 934   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
 935   "vcvtp.<supf>%#<V_sz_elem>.f%#<V_sz_elem>      %q0, %q1"
 936   [(set_attr "type" "mve_move")
 937 ])
 938
 939 ;;
 940 ;; [vcvtnq_s, vcvtnq_u])
 941 ;;
 942 (define_insn "mve_vcvtnq_<supf><mode>"
 943   [
 944    (set (match_operand:MVE_5 0 "s_register_operand" "=w")
 945         (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
 946          VCVTNQ))
 947   ]
 948   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
 949   "vcvtn.<supf>%#<V_sz_elem>.f%#<V_sz_elem>      %q0, %q1"
 950   [(set_attr "type" "mve_move")
 951 ])
 952
 953 ;;
 954 ;; [vcvtmq_s, vcvtmq_u])
 955 ;;
 956 (define_insn "mve_vcvtmq_<supf><mode>"
 957   [
 958    (set (match_operand:MVE_5 0 "s_register_operand" "=w")
 959         (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
 960          VCVTMQ))
 961   ]
 962   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
 963   "vcvtm.<supf>%#<V_sz_elem>.f%#<V_sz_elem>      %q0, %q1"
 964   [(set_attr "type" "mve_move")
 965 ])
 966
 967 ;;
 968 ;; [vcvtaq_u, vcvtaq_s])
 969 ;;
 970 (define_insn "mve_vcvtaq_<supf><mode>"
 971   [
 972    (set (match_operand:MVE_5 0 "s_register_operand" "=w")
 973         (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
 974          VCVTAQ))
 975   ]
 976   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
 977   "vcvta.<supf>%#<V_sz_elem>.f%#<V_sz_elem>      %q0, %q1"
 978   [(set_attr "type" "mve_move")
 979 ])
 980
 981 ;;
 982 ;; [vmvnq_n_u, vmvnq_n_s])
 983 ;;
 984 (define_insn "mve_vmvnq_n_<supf><mode>"
 985   [
 986    (set (match_operand:MVE_5 0 "s_register_operand" "=w")
 987         (unspec:MVE_5 [(match_operand:HI 1 "immediate_operand" "i")]
 988          VMVNQ_N))
 989   ]
 990   "TARGET_HAVE_MVE"
 991   "vmvn.i%#<V_sz_elem>  %q0, %1"
 992   [(set_attr "type" "mve_move")
 993 ])
 994
 995 ;;
 996 ;; [vrev16q_u, vrev16q_s])
 997 ;;
 998 (define_insn "mve_vrev16q_<supf>v16qi"
 999   [
1000    (set (match_operand:V16QI 0 "s_register_operand" "=w")
1001         (unspec:V16QI [(match_operand:V16QI 1 "s_register_operand" "w")]
1002          VREV16Q))
1003   ]
1004   "TARGET_HAVE_MVE"
1005   "vrev16.8 %q0, %q1"
1006   [(set_attr "type" "mve_move")
1007 ])
1008
1009 ;;
1010 ;; [vaddlvq_s vaddlvq_u])
1011 ;;
1012 (define_insn "mve_vaddlvq_<supf>v4si"
1013   [
1014    (set (match_operand:DI 0 "s_register_operand" "=r")
1015         (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")]
1016          VADDLVQ))
1017   ]
1018   "TARGET_HAVE_MVE"
1019   "vaddlv.<supf>32 %Q0, %R0, %q1"
1020   [(set_attr "type" "mve_move")
1021 ])
1022
1023 ;;
1024 ;; [vctp8q vctp16q vctp32q vctp64q])
1025 ;;
1026 (define_insn "mve_vctp<mode1>qhi"
1027   [
1028    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1029         (unspec:HI [(match_operand:SI 1 "s_register_operand" "r")]
1030         VCTPQ))
1031   ]
1032   "TARGET_HAVE_MVE"
1033   "vctp.<mode1> %1"
1034   [(set_attr "type" "mve_move")
1035 ])
1036
1037 ;;
1038 ;; [vpnot])
1039 ;;
1040 (define_insn "mve_vpnothi"
1041   [
1042    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1043         (unspec:HI [(match_operand:HI 1 "vpr_register_operand" "0")]
1044          VPNOT))
1045   ]
1046   "TARGET_HAVE_MVE"
1047   "vpnot"
1048   [(set_attr "type" "mve_move")
1049 ])
1050
1051 ;;
1052 ;; [vsubq_n_f])
1053 ;;
1054 (define_insn "mve_vsubq_n_f<mode>"
1055   [
1056    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
1057         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
1058                        (match_operand:<V_elem> 2 "s_register_operand" "r")]
1059          VSUBQ_N_F))
1060   ]
1061   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1062   "vsub.f<V_sz_elem>  %q0, %q1, %2"
1063   [(set_attr "type" "mve_move")
1064 ])
1065
1066 ;;
1067 ;; [vbrsrq_n_f])
1068 ;;
1069 (define_insn "mve_vbrsrq_n_f<mode>"
1070   [
1071    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
1072         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
1073                        (match_operand:SI 2 "s_register_operand" "r")]
1074          VBRSRQ_N_F))
1075   ]
1076   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1077   "vbrsr.<V_sz_elem>  %q0, %q1, %2"
1078   [(set_attr "type" "mve_move")
1079 ])
1080
1081 ;;
1082 ;; [vcvtq_n_to_f_s, vcvtq_n_to_f_u])
1083 ;;
1084 (define_insn "mve_vcvtq_n_to_f_<supf><mode>"
1085   [
1086    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
1087         (unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")
1088                        (match_operand:SI 2 "mve_imm_16" "Rd")]
1089          VCVTQ_N_TO_F))
1090   ]
1091   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1092   "vcvt.f<V_sz_elem>.<supf><V_sz_elem>\t%q0, %q1, %2"
1093   [(set_attr "type" "mve_move")
1094 ])
1095
1096 ;; [vcreateq_f])
1097 ;;
1098 (define_insn "mve_vcreateq_f<mode>"
1099   [
1100    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
1101         (unspec:MVE_0 [(match_operand:DI 1 "s_register_operand" "r")
1102                        (match_operand:DI 2 "s_register_operand" "r")]
1103          VCREATEQ_F))
1104   ]
1105   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1106   "vmov %q0[2], %q0[0], %Q2, %Q1\;vmov %q0[3], %q0[1], %R2, %R1"
1107   [(set_attr "type" "mve_move")
1108    (set_attr "length""8")])
1109
1110 ;;
1111 ;; [vcreateq_u, vcreateq_s])
1112 ;;
1113 (define_insn "mve_vcreateq_<supf><mode>"
1114   [
1115    (set (match_operand:MVE_1 0 "s_register_operand" "=w")
1116         (unspec:MVE_1 [(match_operand:DI 1 "s_register_operand" "r")
1117                        (match_operand:DI 2 "s_register_operand" "r")]
1118          VCREATEQ))
1119   ]
1120   "TARGET_HAVE_MVE"
1121   "vmov %q0[2], %q0[0], %Q2, %Q1\;vmov %q0[3], %q0[1], %R2, %R1"
1122   [(set_attr "type" "mve_move")
1123    (set_attr "length""8")])
1124
1125 ;;
1126 ;; [vshrq_n_s, vshrq_n_u])
1127 ;;
1128 (define_insn "mve_vshrq_n_<supf><mode>"
1129   [
1130    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1131         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1132                        (match_operand:SI 2 "<MVE_pred2>" "<MVE_constraint2>")]
1133          VSHRQ_N))
1134   ]
1135   "TARGET_HAVE_MVE"
1136   "vshr.<supf><V_sz_elem>\t%q0, %q1, %2"
1137   [(set_attr "type" "mve_move")
1138 ])
1139
1140 ;;
1141 ;; [vcvtq_n_from_f_s, vcvtq_n_from_f_u])
1142 ;;
1143 (define_insn "mve_vcvtq_n_from_f_<supf><mode>"
1144   [
1145    (set (match_operand:MVE_5 0 "s_register_operand" "=w")
1146         (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")
1147                        (match_operand:SI 2 "mve_imm_16" "Rd")]
1148          VCVTQ_N_FROM_F))
1149   ]
1150   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1151   "vcvt.<supf><V_sz_elem>.f<V_sz_elem>\t%q0, %q1, %2"
1152   [(set_attr "type" "mve_move")
1153 ])
1154
1155 ;;
1156 ;; [vaddlvq_p_s])
1157 ;;
1158 (define_insn "mve_vaddlvq_p_<supf>v4si"
1159   [
1160    (set (match_operand:DI 0 "s_register_operand" "=r")
1161         (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
1162                     (match_operand:HI 2 "vpr_register_operand" "Up")]
1163          VADDLVQ_P))
1164   ]
1165   "TARGET_HAVE_MVE"
1166   "vpst\;vaddlvt.<supf>32 %Q0, %R0, %q1"
1167   [(set_attr "type" "mve_move")
1168    (set_attr "length""8")])
1169
1170 ;;
1171 ;; [vcmpneq_u, vcmpneq_s])
1172 ;;
1173 (define_insn "mve_vcmpneq_<supf><mode>"
1174   [
1175    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1176         (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1177                     (match_operand:MVE_2 2 "s_register_operand" "w")]
1178          VCMPNEQ))
1179   ]
1180   "TARGET_HAVE_MVE"
1181   "vcmp.i%#<V_sz_elem>  ne, %q1, %q2"
1182   [(set_attr "type" "mve_move")
1183 ])
1184
1185 ;;
1186 ;; [vshlq_s, vshlq_u])
1187 ;;
1188 (define_insn "mve_vshlq_<supf><mode>"
1189   [
1190    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1191         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1192                        (match_operand:MVE_2 2 "s_register_operand" "w")]
1193          VSHLQ))
1194   ]
1195   "TARGET_HAVE_MVE"
1196   "vshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1197   [(set_attr "type" "mve_move")
1198 ])
1199
1200 ;;
1201 ;; [vabdq_s, vabdq_u])
1202 ;;
1203 (define_insn "mve_vabdq_<supf><mode>"
1204   [
1205    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1206         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1207                        (match_operand:MVE_2 2 "s_register_operand" "w")]
1208          VABDQ))
1209   ]
1210   "TARGET_HAVE_MVE"
1211   "vabd.<supf>%#<V_sz_elem>     %q0, %q1, %q2"
1212   [(set_attr "type" "mve_move")
1213 ])
1214
1215 ;;
1216 ;; [vaddq_n_s, vaddq_n_u])
1217 ;;
1218 (define_insn "mve_vaddq_n_<supf><mode>"
1219   [
1220    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1221         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1222                        (match_operand:<V_elem> 2 "s_register_operand" "r")]
1223          VADDQ_N))
1224   ]
1225   "TARGET_HAVE_MVE"
1226   "vadd.i%#<V_sz_elem>  %q0, %q1, %2"
1227   [(set_attr "type" "mve_move")
1228 ])
1229
1230 ;;
1231 ;; [vaddvaq_s, vaddvaq_u])
1232 ;;
1233 (define_insn "mve_vaddvaq_<supf><mode>"
1234   [
1235    (set (match_operand:SI 0 "s_register_operand" "=e")
1236         (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
1237                     (match_operand:MVE_2 2 "s_register_operand" "w")]
1238          VADDVAQ))
1239   ]
1240   "TARGET_HAVE_MVE"
1241   "vaddva.<supf>%#<V_sz_elem>   %0, %q2"
1242   [(set_attr "type" "mve_move")
1243 ])
1244
1245 ;;
1246 ;; [vaddvq_p_u, vaddvq_p_s])
1247 ;;
1248 (define_insn "mve_vaddvq_p_<supf><mode>"
1249   [
1250    (set (match_operand:SI 0 "s_register_operand" "=e")
1251         (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
1252                     (match_operand:HI 2 "vpr_register_operand" "Up")]
1253          VADDVQ_P))
1254   ]
1255   "TARGET_HAVE_MVE"
1256   "vpst\;vaddvt.<supf>%#<V_sz_elem>     %0, %q1"
1257   [(set_attr "type" "mve_move")
1258    (set_attr "length""8")])
1259
1260 ;;
1261 ;; [vandq_u, vandq_s])
1262 ;;
1263 (define_insn "mve_vandq_<supf><mode>"
1264   [
1265    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1266         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1267                        (match_operand:MVE_2 2 "s_register_operand" "w")]
1268          VANDQ))
1269   ]
1270   "TARGET_HAVE_MVE"
1271   "vand %q0, %q1, %q2"
1272   [(set_attr "type" "mve_move")
1273 ])
1274
1275 ;;
1276 ;; [vbicq_s, vbicq_u])
1277 ;;
1278 (define_insn "mve_vbicq_<supf><mode>"
1279   [
1280    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1281         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1282                        (match_operand:MVE_2 2 "s_register_operand" "w")]
1283          VBICQ))
1284   ]
1285   "TARGET_HAVE_MVE"
1286   "vbic %q0, %q1, %q2"
1287   [(set_attr "type" "mve_move")
1288 ])
1289
1290 ;;
1291 ;; [vbrsrq_n_u, vbrsrq_n_s])
1292 ;;
1293 (define_insn "mve_vbrsrq_n_<supf><mode>"
1294   [
1295    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1296         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1297                        (match_operand:SI 2 "s_register_operand" "r")]
1298          VBRSRQ_N))
1299   ]
1300   "TARGET_HAVE_MVE"
1301   "vbrsr.%#<V_sz_elem>  %q0, %q1, %2"
1302   [(set_attr "type" "mve_move")
1303 ])
1304
1305 ;;
1306 ;; [vcaddq_rot270_s, vcaddq_rot270_u])
1307 ;;
1308 (define_insn "mve_vcaddq_rot270_<supf><mode>"
1309   [
1310    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1311         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1312                        (match_operand:MVE_2 2 "s_register_operand" "w")]
1313          VCADDQ_ROT270))
1314   ]
1315   "TARGET_HAVE_MVE"
1316   "vcadd.i%#<V_sz_elem> %q0, %q1, %q2, #270"
1317   [(set_attr "type" "mve_move")
1318 ])
1319
1320 ;;
1321 ;; [vcaddq_rot90_u, vcaddq_rot90_s])
1322 ;;
1323 (define_insn "mve_vcaddq_rot90_<supf><mode>"
1324   [
1325    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1326         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1327                        (match_operand:MVE_2 2 "s_register_operand" "w")]
1328          VCADDQ_ROT90))
1329   ]
1330   "TARGET_HAVE_MVE"
1331   "vcadd.i%#<V_sz_elem> %q0, %q1, %q2, #90"
1332   [(set_attr "type" "mve_move")
1333 ])
1334
1335 ;;
1336 ;; [vcmpcsq_n_u])
1337 ;;
1338 (define_insn "mve_vcmpcsq_n_u<mode>"
1339   [
1340    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1341         (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1342                     (match_operand:<V_elem> 2 "s_register_operand" "r")]
1343          VCMPCSQ_N_U))
1344   ]
1345   "TARGET_HAVE_MVE"
1346   "vcmp.u%#<V_sz_elem>  cs, %q1, %2"
1347   [(set_attr "type" "mve_move")
1348 ])
1349
1350 ;;
1351 ;; [vcmpcsq_u])
1352 ;;
1353 (define_insn "mve_vcmpcsq_u<mode>"
1354   [
1355    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1356         (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1357                     (match_operand:MVE_2 2 "s_register_operand" "w")]
1358          VCMPCSQ_U))
1359   ]
1360   "TARGET_HAVE_MVE"
1361   "vcmp.u%#<V_sz_elem>  cs, %q1, %q2"
1362   [(set_attr "type" "mve_move")
1363 ])
1364
1365 ;;
1366 ;; [vcmpeqq_n_s, vcmpeqq_n_u])
1367 ;;
1368 (define_insn "mve_vcmpeqq_n_<supf><mode>"
1369   [
1370    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1371         (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1372                     (match_operand:<V_elem> 2 "s_register_operand" "r")]
1373          VCMPEQQ_N))
1374   ]
1375   "TARGET_HAVE_MVE"
1376   "vcmp.i%#<V_sz_elem>  eq, %q1, %2"
1377   [(set_attr "type" "mve_move")
1378 ])
1379
1380 ;;
1381 ;; [vcmpeqq_u, vcmpeqq_s])
1382 ;;
1383 (define_insn "mve_vcmpeqq_<supf><mode>"
1384   [
1385    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1386         (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1387                     (match_operand:MVE_2 2 "s_register_operand" "w")]
1388          VCMPEQQ))
1389   ]
1390   "TARGET_HAVE_MVE"
1391   "vcmp.i%#<V_sz_elem>  eq, %q1, %q2"
1392   [(set_attr "type" "mve_move")
1393 ])
1394
1395 ;;
1396 ;; [vcmpgeq_n_s])
1397 ;;
1398 (define_insn "mve_vcmpgeq_n_s<mode>"
1399   [
1400    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1401         (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1402                     (match_operand:<V_elem> 2 "s_register_operand" "r")]
1403          VCMPGEQ_N_S))
1404   ]
1405   "TARGET_HAVE_MVE"
1406   "vcmp.s%#<V_sz_elem>  ge, %q1, %2"
1407   [(set_attr "type" "mve_move")
1408 ])
1409
1410 ;;
1411 ;; [vcmpgeq_s])
1412 ;;
1413 (define_insn "mve_vcmpgeq_s<mode>"
1414   [
1415    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1416         (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1417                     (match_operand:MVE_2 2 "s_register_operand" "w")]
1418          VCMPGEQ_S))
1419   ]
1420   "TARGET_HAVE_MVE"
1421   "vcmp.s%#<V_sz_elem>  ge, %q1, %q2"
1422   [(set_attr "type" "mve_move")
1423 ])
1424
1425 ;;
1426 ;; [vcmpgtq_n_s])
1427 ;;
1428 (define_insn "mve_vcmpgtq_n_s<mode>"
1429   [
1430    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1431         (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1432                     (match_operand:<V_elem> 2 "s_register_operand" "r")]
1433          VCMPGTQ_N_S))
1434   ]
1435   "TARGET_HAVE_MVE"
1436   "vcmp.s%#<V_sz_elem>  gt, %q1, %2"
1437   [(set_attr "type" "mve_move")
1438 ])
1439
1440 ;;
1441 ;; [vcmpgtq_s])
1442 ;;
1443 (define_insn "mve_vcmpgtq_s<mode>"
1444   [
1445    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1446         (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1447                     (match_operand:MVE_2 2 "s_register_operand" "w")]
1448          VCMPGTQ_S))
1449   ]
1450   "TARGET_HAVE_MVE"
1451   "vcmp.s%#<V_sz_elem>  gt, %q1, %q2"
1452   [(set_attr "type" "mve_move")
1453 ])
1454
1455 ;;
1456 ;; [vcmphiq_n_u])
1457 ;;
1458 (define_insn "mve_vcmphiq_n_u<mode>"
1459   [
1460    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1461         (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1462                     (match_operand:<V_elem> 2 "s_register_operand" "r")]
1463          VCMPHIQ_N_U))
1464   ]
1465   "TARGET_HAVE_MVE"
1466   "vcmp.u%#<V_sz_elem>  hi, %q1, %2"
1467   [(set_attr "type" "mve_move")
1468 ])
1469
1470 ;;
1471 ;; [vcmphiq_u])
1472 ;;
1473 (define_insn "mve_vcmphiq_u<mode>"
1474   [
1475    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1476         (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1477                     (match_operand:MVE_2 2 "s_register_operand" "w")]
1478          VCMPHIQ_U))
1479   ]
1480   "TARGET_HAVE_MVE"
1481   "vcmp.u%#<V_sz_elem>  hi, %q1, %q2"
1482   [(set_attr "type" "mve_move")
1483 ])
1484
1485 ;;
1486 ;; [vcmpleq_n_s])
1487 ;;
1488 (define_insn "mve_vcmpleq_n_s<mode>"
1489   [
1490    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1491         (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1492                     (match_operand:<V_elem> 2 "s_register_operand" "r")]
1493          VCMPLEQ_N_S))
1494   ]
1495   "TARGET_HAVE_MVE"
1496   "vcmp.s%#<V_sz_elem>  le, %q1, %2"
1497   [(set_attr "type" "mve_move")
1498 ])
1499
1500 ;;
1501 ;; [vcmpleq_s])
1502 ;;
1503 (define_insn "mve_vcmpleq_s<mode>"
1504   [
1505    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1506         (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1507                     (match_operand:MVE_2 2 "s_register_operand" "w")]
1508          VCMPLEQ_S))
1509   ]
1510   "TARGET_HAVE_MVE"
1511   "vcmp.s%#<V_sz_elem>  le, %q1, %q2"
1512   [(set_attr "type" "mve_move")
1513 ])
1514
1515 ;;
1516 ;; [vcmpltq_n_s])
1517 ;;
1518 (define_insn "mve_vcmpltq_n_s<mode>"
1519   [
1520    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1521         (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1522                     (match_operand:<V_elem> 2 "s_register_operand" "r")]
1523          VCMPLTQ_N_S))
1524   ]
1525   "TARGET_HAVE_MVE"
1526   "vcmp.s%#<V_sz_elem>  lt, %q1, %2"
1527   [(set_attr "type" "mve_move")
1528 ])
1529
1530 ;;
1531 ;; [vcmpltq_s])
1532 ;;
1533 (define_insn "mve_vcmpltq_s<mode>"
1534   [
1535    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1536         (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1537                     (match_operand:MVE_2 2 "s_register_operand" "w")]
1538          VCMPLTQ_S))
1539   ]
1540   "TARGET_HAVE_MVE"
1541   "vcmp.s%#<V_sz_elem>  lt, %q1, %q2"
1542   [(set_attr "type" "mve_move")
1543 ])
1544
1545 ;;
1546 ;; [vcmpneq_n_u, vcmpneq_n_s])
1547 ;;
1548 (define_insn "mve_vcmpneq_n_<supf><mode>"
1549   [
1550    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1551         (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1552                     (match_operand:<V_elem> 2 "s_register_operand" "r")]
1553          VCMPNEQ_N))
1554   ]
1555   "TARGET_HAVE_MVE"
1556   "vcmp.i%#<V_sz_elem>  ne, %q1, %2"
1557   [(set_attr "type" "mve_move")
1558 ])
1559
1560 ;;
1561 ;; [veorq_u, veorq_s])
1562 ;;
1563 (define_insn "mve_veorq_<supf><mode>"
1564   [
1565    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1566         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1567                        (match_operand:MVE_2 2 "s_register_operand" "w")]
1568          VEORQ))
1569   ]
1570   "TARGET_HAVE_MVE"
1571   "veor %q0, %q1, %q2"
1572   [(set_attr "type" "mve_move")
1573 ])
1574
1575 ;;
1576 ;; [vhaddq_n_u, vhaddq_n_s])
1577 ;;
1578 (define_insn "mve_vhaddq_n_<supf><mode>"
1579   [
1580    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1581         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1582                        (match_operand:<V_elem> 2 "s_register_operand" "r")]
1583          VHADDQ_N))
1584   ]
1585   "TARGET_HAVE_MVE"
1586   "vhadd.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
1587   [(set_attr "type" "mve_move")
1588 ])
1589
1590 ;;
1591 ;; [vhaddq_s, vhaddq_u])
1592 ;;
1593 (define_insn "mve_vhaddq_<supf><mode>"
1594   [
1595    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1596         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1597                        (match_operand:MVE_2 2 "s_register_operand" "w")]
1598          VHADDQ))
1599   ]
1600   "TARGET_HAVE_MVE"
1601   "vhadd.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1602   [(set_attr "type" "mve_move")
1603 ])
1604
1605 ;;
1606 ;; [vhcaddq_rot270_s])
1607 ;;
1608 (define_insn "mve_vhcaddq_rot270_s<mode>"
1609   [
1610    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1611         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1612                        (match_operand:MVE_2 2 "s_register_operand" "w")]
1613          VHCADDQ_ROT270_S))
1614   ]
1615   "TARGET_HAVE_MVE"
1616   "vhcadd.s%#<V_sz_elem>\t%q0, %q1, %q2, #270"
1617   [(set_attr "type" "mve_move")
1618 ])
1619
1620 ;;
1621 ;; [vhcaddq_rot90_s])
1622 ;;
1623 (define_insn "mve_vhcaddq_rot90_s<mode>"
1624   [
1625    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1626         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1627                        (match_operand:MVE_2 2 "s_register_operand" "w")]
1628          VHCADDQ_ROT90_S))
1629   ]
1630   "TARGET_HAVE_MVE"
1631   "vhcadd.s%#<V_sz_elem>\t%q0, %q1, %q2, #90"
1632   [(set_attr "type" "mve_move")
1633 ])
1634
1635 ;;
1636 ;; [vhsubq_n_u, vhsubq_n_s])
1637 ;;
1638 (define_insn "mve_vhsubq_n_<supf><mode>"
1639   [
1640    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1641         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1642                        (match_operand:<V_elem> 2 "s_register_operand" "r")]
1643          VHSUBQ_N))
1644   ]
1645   "TARGET_HAVE_MVE"
1646   "vhsub.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
1647   [(set_attr "type" "mve_move")
1648 ])
1649
1650 ;;
1651 ;; [vhsubq_s, vhsubq_u])
1652 ;;
1653 (define_insn "mve_vhsubq_<supf><mode>"
1654   [
1655    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1656         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1657                        (match_operand:MVE_2 2 "s_register_operand" "w")]
1658          VHSUBQ))
1659   ]
1660   "TARGET_HAVE_MVE"
1661   "vhsub.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1662   [(set_attr "type" "mve_move")
1663 ])
1664
1665 ;;
1666 ;; [vmaxaq_s])
1667 ;;
1668 (define_insn "mve_vmaxaq_s<mode>"
1669   [
1670    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1671         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
1672                        (match_operand:MVE_2 2 "s_register_operand" "w")]
1673          VMAXAQ_S))
1674   ]
1675   "TARGET_HAVE_MVE"
1676   "vmaxa.s%#<V_sz_elem> %q0, %q2"
1677   [(set_attr "type" "mve_move")
1678 ])
1679
1680 ;;
1681 ;; [vmaxavq_s])
1682 ;;
1683 (define_insn "mve_vmaxavq_s<mode>"
1684   [
1685    (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
1686         (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
1687                           (match_operand:MVE_2 2 "s_register_operand" "w")]
1688          VMAXAVQ_S))
1689   ]
1690   "TARGET_HAVE_MVE"
1691   "vmaxav.s%#<V_sz_elem>\t%0, %q2"
1692   [(set_attr "type" "mve_move")
1693 ])
1694
1695 ;;
1696 ;; [vmaxq_u, vmaxq_s])
1697 ;;
1698 (define_insn "mve_vmaxq_<supf><mode>"
1699   [
1700    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1701         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1702                        (match_operand:MVE_2 2 "s_register_operand" "w")]
1703          VMAXQ))
1704   ]
1705   "TARGET_HAVE_MVE"
1706   "vmax.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1707   [(set_attr "type" "mve_move")
1708 ])
1709
1710 ;;
1711 ;; [vmaxvq_u, vmaxvq_s])
1712 ;;
1713 (define_insn "mve_vmaxvq_<supf><mode>"
1714   [
1715    (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
1716         (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
1717                           (match_operand:MVE_2 2 "s_register_operand" "w")]
1718          VMAXVQ))
1719   ]
1720   "TARGET_HAVE_MVE"
1721   "vmaxv.<supf>%#<V_sz_elem>\t%0, %q2"
1722   [(set_attr "type" "mve_move")
1723 ])
1724
1725 ;;
1726 ;; [vminaq_s])
1727 ;;
1728 (define_insn "mve_vminaq_s<mode>"
1729   [
1730    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1731         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
1732                        (match_operand:MVE_2 2 "s_register_operand" "w")]
1733          VMINAQ_S))
1734   ]
1735   "TARGET_HAVE_MVE"
1736   "vmina.s%#<V_sz_elem>\t%q0, %q2"
1737   [(set_attr "type" "mve_move")
1738 ])
1739
1740 ;;
1741 ;; [vminavq_s])
1742 ;;
1743 (define_insn "mve_vminavq_s<mode>"
1744   [
1745    (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
1746         (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
1747                           (match_operand:MVE_2 2 "s_register_operand" "w")]
1748          VMINAVQ_S))
1749   ]
1750   "TARGET_HAVE_MVE"
1751   "vminav.s%#<V_sz_elem>\t%0, %q2"
1752   [(set_attr "type" "mve_move")
1753 ])
1754
1755 ;;
1756 ;; [vminq_s, vminq_u])
1757 ;;
1758 (define_insn "mve_vminq_<supf><mode>"
1759   [
1760    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1761         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1762                        (match_operand:MVE_2 2 "s_register_operand" "w")]
1763          VMINQ))
1764   ]
1765   "TARGET_HAVE_MVE"
1766   "vmin.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1767   [(set_attr "type" "mve_move")
1768 ])
1769
1770 ;;
1771 ;; [vminvq_u, vminvq_s])
1772 ;;
1773 (define_insn "mve_vminvq_<supf><mode>"
1774   [
1775    (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
1776         (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
1777                           (match_operand:MVE_2 2 "s_register_operand" "w")]
1778          VMINVQ))
1779   ]
1780   "TARGET_HAVE_MVE"
1781   "vminv.<supf>%#<V_sz_elem>\t%0, %q2"
1782   [(set_attr "type" "mve_move")
1783 ])
1784
1785 ;;
1786 ;; [vmladavq_u, vmladavq_s])
1787 ;;
1788 (define_insn "mve_vmladavq_<supf><mode>"
1789   [
1790    (set (match_operand:SI 0 "s_register_operand" "=e")
1791         (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
1792                     (match_operand:MVE_2 2 "s_register_operand" "w")]
1793          VMLADAVQ))
1794   ]
1795   "TARGET_HAVE_MVE"
1796   "vmladav.<supf>%#<V_sz_elem>\t%0, %q1, %q2"
1797   [(set_attr "type" "mve_move")
1798 ])
1799
1800 ;;
1801 ;; [vmladavxq_s])
1802 ;;
1803 (define_insn "mve_vmladavxq_s<mode>"
1804   [
1805    (set (match_operand:SI 0 "s_register_operand" "=e")
1806         (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
1807                     (match_operand:MVE_2 2 "s_register_operand" "w")]
1808          VMLADAVXQ_S))
1809   ]
1810   "TARGET_HAVE_MVE"
1811   "vmladavx.s%#<V_sz_elem>\t%0, %q1, %q2"
1812   [(set_attr "type" "mve_move")
1813 ])
1814
1815 ;;
1816 ;; [vmlsdavq_s])
1817 ;;
1818 (define_insn "mve_vmlsdavq_s<mode>"
1819   [
1820    (set (match_operand:SI 0 "s_register_operand" "=e")
1821         (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
1822                     (match_operand:MVE_2 2 "s_register_operand" "w")]
1823          VMLSDAVQ_S))
1824   ]
1825   "TARGET_HAVE_MVE"
1826   "vmlsdav.s%#<V_sz_elem>\t%0, %q1, %q2"
1827   [(set_attr "type" "mve_move")
1828 ])
1829
1830 ;;
1831 ;; [vmlsdavxq_s])
1832 ;;
1833 (define_insn "mve_vmlsdavxq_s<mode>"
1834   [
1835    (set (match_operand:SI 0 "s_register_operand" "=e")
1836         (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
1837                     (match_operand:MVE_2 2 "s_register_operand" "w")]
1838          VMLSDAVXQ_S))
1839   ]
1840   "TARGET_HAVE_MVE"
1841   "vmlsdavx.s%#<V_sz_elem>\t%0, %q1, %q2"
1842   [(set_attr "type" "mve_move")
1843 ])
1844
1845 ;;
1846 ;; [vmulhq_s, vmulhq_u])
1847 ;;
1848 (define_insn "mve_vmulhq_<supf><mode>"
1849   [
1850    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1851         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1852                        (match_operand:MVE_2 2 "s_register_operand" "w")]
1853          VMULHQ))
1854   ]
1855   "TARGET_HAVE_MVE"
1856   "vmulh.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1857   [(set_attr "type" "mve_move")
1858 ])
1859
1860 ;;
1861 ;; [vmullbq_int_u, vmullbq_int_s])
1862 ;;
1863 (define_insn "mve_vmullbq_int_<supf><mode>"
1864   [
1865    (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
1866         (unspec:<V_double_width> [(match_operand:MVE_2 1 "s_register_operand" "w")
1867                                   (match_operand:MVE_2 2 "s_register_operand" "w")]
1868          VMULLBQ_INT))
1869   ]
1870   "TARGET_HAVE_MVE"
1871   "vmullb.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1872   [(set_attr "type" "mve_move")
1873 ])
1874
1875 ;;
1876 ;; [vmulltq_int_u, vmulltq_int_s])
1877 ;;
1878 (define_insn "mve_vmulltq_int_<supf><mode>"
1879   [
1880    (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
1881         (unspec:<V_double_width> [(match_operand:MVE_2 1 "s_register_operand" "w")
1882                                   (match_operand:MVE_2 2 "s_register_operand" "w")]
1883          VMULLTQ_INT))
1884   ]
1885   "TARGET_HAVE_MVE"
1886   "vmullt.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1887   [(set_attr "type" "mve_move")
1888 ])
1889
1890 ;;
1891 ;; [vmulq_n_u, vmulq_n_s])
1892 ;;
1893 (define_insn "mve_vmulq_n_<supf><mode>"
1894   [
1895    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1896         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1897                        (match_operand:<V_elem> 2 "s_register_operand" "r")]
1898          VMULQ_N))
1899   ]
1900   "TARGET_HAVE_MVE"
1901   "vmul.i%#<V_sz_elem>\t%q0, %q1, %2"
1902   [(set_attr "type" "mve_move")
1903 ])
1904
1905 ;;
1906 ;; [vmulq_u, vmulq_s])
1907 ;;
1908 (define_insn "mve_vmulq_<supf><mode>"
1909   [
1910    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1911         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1912                        (match_operand:MVE_2 2 "s_register_operand" "w")]
1913          VMULQ))
1914   ]
1915   "TARGET_HAVE_MVE"
1916   "vmul.i%#<V_sz_elem>\t%q0, %q1, %q2"
1917   [(set_attr "type" "mve_move")
1918 ])
1919
1920 ;;
1921 ;; [vornq_u, vornq_s])
1922 ;;
1923 (define_insn "mve_vornq_<supf><mode>"
1924   [
1925    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1926         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1927                        (match_operand:MVE_2 2 "s_register_operand" "w")]
1928          VORNQ))
1929   ]
1930   "TARGET_HAVE_MVE"
1931   "vorn %q0, %q1, %q2"
1932   [(set_attr "type" "mve_move")
1933 ])
1934
1935 ;;
1936 ;; [vorrq_s, vorrq_u])
1937 ;;
1938 (define_insn "mve_vorrq_<supf><mode>"
1939   [
1940    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1941         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1942                        (match_operand:MVE_2 2 "s_register_operand" "w")]
1943          VORRQ))
1944   ]
1945   "TARGET_HAVE_MVE"
1946   "vorr %q0, %q1, %q2"
1947   [(set_attr "type" "mve_move")
1948 ])
1949
1950 ;;
1951 ;; [vqaddq_n_s, vqaddq_n_u])
1952 ;;
1953 (define_insn "mve_vqaddq_n_<supf><mode>"
1954   [
1955    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1956         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1957                        (match_operand:<V_elem> 2 "s_register_operand" "r")]
1958          VQADDQ_N))
1959   ]
1960   "TARGET_HAVE_MVE"
1961   "vqadd.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
1962   [(set_attr "type" "mve_move")
1963 ])
1964
1965 ;;
1966 ;; [vqaddq_u, vqaddq_s])
1967 ;;
1968 (define_insn "mve_vqaddq_<supf><mode>"
1969   [
1970    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1971         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1972                        (match_operand:MVE_2 2 "s_register_operand" "w")]
1973          VQADDQ))
1974   ]
1975   "TARGET_HAVE_MVE"
1976   "vqadd.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1977   [(set_attr "type" "mve_move")
1978 ])
1979
1980 ;;
1981 ;; [vqdmulhq_n_s])
1982 ;;
1983 (define_insn "mve_vqdmulhq_n_s<mode>"
1984   [
1985    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1986         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1987                        (match_operand:<V_elem> 2 "s_register_operand" "r")]
1988          VQDMULHQ_N_S))
1989   ]
1990   "TARGET_HAVE_MVE"
1991   "vqdmulh.s%#<V_sz_elem>\t%q0, %q1, %2"
1992   [(set_attr "type" "mve_move")
1993 ])
1994
1995 ;;
1996 ;; [vqdmulhq_s])
1997 ;;
1998 (define_insn "mve_vqdmulhq_s<mode>"
1999   [
2000    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2001         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2002                        (match_operand:MVE_2 2 "s_register_operand" "w")]
2003          VQDMULHQ_S))
2004   ]
2005   "TARGET_HAVE_MVE"
2006   "vqdmulh.s%#<V_sz_elem>\t%q0, %q1, %q2"
2007   [(set_attr "type" "mve_move")
2008 ])
2009
2010 ;;
2011 ;; [vqrdmulhq_n_s])
2012 ;;
2013 (define_insn "mve_vqrdmulhq_n_s<mode>"
2014   [
2015    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2016         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2017                        (match_operand:<V_elem> 2 "s_register_operand" "r")]
2018          VQRDMULHQ_N_S))
2019   ]
2020   "TARGET_HAVE_MVE"
2021   "vqrdmulh.s%#<V_sz_elem>\t%q0, %q1, %2"
2022   [(set_attr "type" "mve_move")
2023 ])
2024
2025 ;;
2026 ;; [vqrdmulhq_s])
2027 ;;
2028 (define_insn "mve_vqrdmulhq_s<mode>"
2029   [
2030    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2031         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2032                        (match_operand:MVE_2 2 "s_register_operand" "w")]
2033          VQRDMULHQ_S))
2034   ]
2035   "TARGET_HAVE_MVE"
2036   "vqrdmulh.s%#<V_sz_elem>\t%q0, %q1, %q2"
2037   [(set_attr "type" "mve_move")
2038 ])
2039
2040 ;;
2041 ;; [vqrshlq_n_s, vqrshlq_n_u])
2042 ;;
2043 (define_insn "mve_vqrshlq_n_<supf><mode>"
2044   [
2045    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2046         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
2047                        (match_operand:SI 2 "s_register_operand" "r")]
2048          VQRSHLQ_N))
2049   ]
2050   "TARGET_HAVE_MVE"
2051   "vqrshl.<supf>%#<V_sz_elem>\t%q0, %2"
2052   [(set_attr "type" "mve_move")
2053 ])
2054
2055 ;;
2056 ;; [vqrshlq_s, vqrshlq_u])
2057 ;;
2058 (define_insn "mve_vqrshlq_<supf><mode>"
2059   [
2060    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2061         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2062                        (match_operand:MVE_2 2 "s_register_operand" "w")]
2063          VQRSHLQ))
2064   ]
2065   "TARGET_HAVE_MVE"
2066   "vqrshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2067   [(set_attr "type" "mve_move")
2068 ])
2069
2070 ;;
2071 ;; [vqshlq_n_s, vqshlq_n_u])
2072 ;;
2073 (define_insn "mve_vqshlq_n_<supf><mode>"
2074   [
2075    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2076         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2077                        (match_operand:SI 2 "immediate_operand" "i")]
2078          VQSHLQ_N))
2079   ]
2080   "TARGET_HAVE_MVE"
2081   "vqshl.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
2082   [(set_attr "type" "mve_move")
2083 ])
2084
2085 ;;
2086 ;; [vqshlq_r_u, vqshlq_r_s])
2087 ;;
2088 (define_insn "mve_vqshlq_r_<supf><mode>"
2089   [
2090    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2091         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
2092                        (match_operand:SI 2 "s_register_operand" "r")]
2093          VQSHLQ_R))
2094   ]
2095   "TARGET_HAVE_MVE"
2096   "vqshl.<supf>%#<V_sz_elem>\t%q0, %2"
2097   [(set_attr "type" "mve_move")
2098 ])
2099
2100 ;;
2101 ;; [vqshlq_s, vqshlq_u])
2102 ;;
2103 (define_insn "mve_vqshlq_<supf><mode>"
2104   [
2105    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2106         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2107                        (match_operand:MVE_2 2 "s_register_operand" "w")]
2108          VQSHLQ))
2109   ]
2110   "TARGET_HAVE_MVE"
2111   "vqshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2112   [(set_attr "type" "mve_move")
2113 ])
2114
2115 ;;
2116 ;; [vqshluq_n_s])
2117 ;;
2118 (define_insn "mve_vqshluq_n_s<mode>"
2119   [
2120    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2121         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2122                        (match_operand:SI 2 "mve_imm_7" "Ra")]
2123          VQSHLUQ_N_S))
2124   ]
2125   "TARGET_HAVE_MVE"
2126   "vqshlu.s%#<V_sz_elem>\t%q0, %q1, %2"
2127   [(set_attr "type" "mve_move")
2128 ])
2129
2130 ;;
2131 ;; [vqsubq_n_s, vqsubq_n_u])
2132 ;;
2133 (define_insn "mve_vqsubq_n_<supf><mode>"
2134   [
2135    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2136         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2137                        (match_operand:<V_elem> 2 "s_register_operand" "r")]
2138          VQSUBQ_N))
2139   ]
2140   "TARGET_HAVE_MVE"
2141   "vqsub.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
2142   [(set_attr "type" "mve_move")
2143 ])
2144
2145 ;;
2146 ;; [vqsubq_u, vqsubq_s])
2147 ;;
2148 (define_insn "mve_vqsubq_<supf><mode>"
2149   [
2150    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2151         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2152                        (match_operand:MVE_2 2 "s_register_operand" "w")]
2153          VQSUBQ))
2154   ]
2155   "TARGET_HAVE_MVE"
2156   "vqsub.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2157   [(set_attr "type" "mve_move")
2158 ])
2159
2160 ;;
2161 ;; [vrhaddq_s, vrhaddq_u])
2162 ;;
2163 (define_insn "mve_vrhaddq_<supf><mode>"
2164   [
2165    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2166         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2167                        (match_operand:MVE_2 2 "s_register_operand" "w")]
2168          VRHADDQ))
2169   ]
2170   "TARGET_HAVE_MVE"
2171   "vrhadd.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2172   [(set_attr "type" "mve_move")
2173 ])
2174
2175 ;;
2176 ;; [vrmulhq_s, vrmulhq_u])
2177 ;;
2178 (define_insn "mve_vrmulhq_<supf><mode>"
2179   [
2180    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2181         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2182                        (match_operand:MVE_2 2 "s_register_operand" "w")]
2183          VRMULHQ))
2184   ]
2185   "TARGET_HAVE_MVE"
2186   "vrmulh.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2187   [(set_attr "type" "mve_move")
2188 ])
2189
2190 ;;
2191 ;; [vrshlq_n_u, vrshlq_n_s])
2192 ;;
2193 (define_insn "mve_vrshlq_n_<supf><mode>"
2194   [
2195    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2196         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
2197                        (match_operand:SI 2 "s_register_operand" "r")]
2198          VRSHLQ_N))
2199   ]
2200   "TARGET_HAVE_MVE"
2201   "vrshl.<supf>%#<V_sz_elem>\t%q0, %2"
2202   [(set_attr "type" "mve_move")
2203 ])
2204
2205 ;;
2206 ;; [vrshlq_s, vrshlq_u])
2207 ;;
2208 (define_insn "mve_vrshlq_<supf><mode>"
2209   [
2210    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2211         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2212                        (match_operand:MVE_2 2 "s_register_operand" "w")]
2213          VRSHLQ))
2214   ]
2215   "TARGET_HAVE_MVE"
2216   "vrshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2217   [(set_attr "type" "mve_move")
2218 ])
2219
2220 ;;
2221 ;; [vrshrq_n_s, vrshrq_n_u])
2222 ;;
2223 (define_insn "mve_vrshrq_n_<supf><mode>"
2224   [
2225    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2226         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2227                        (match_operand:SI 2 "<MVE_pred2>" "<MVE_constraint2>")]
2228          VRSHRQ_N))
2229   ]
2230   "TARGET_HAVE_MVE"
2231   "vrshr.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
2232   [(set_attr "type" "mve_move")
2233 ])
2234
2235 ;;
2236 ;; [vshlq_n_u, vshlq_n_s])
2237 ;;
2238 (define_insn "mve_vshlq_n_<supf><mode>"
2239   [
2240    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2241         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2242                        (match_operand:SI 2 "immediate_operand" "i")]
2243          VSHLQ_N))
2244   ]
2245   "TARGET_HAVE_MVE"
2246   "vshl.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
2247   [(set_attr "type" "mve_move")
2248 ])
2249
2250 ;;
2251 ;; [vshlq_r_s, vshlq_r_u])
2252 ;;
2253 (define_insn "mve_vshlq_r_<supf><mode>"
2254   [
2255    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2256         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
2257                        (match_operand:SI 2 "s_register_operand" "r")]
2258          VSHLQ_R))
2259   ]
2260   "TARGET_HAVE_MVE"
2261   "vshl.<supf>%#<V_sz_elem>\t%q0, %2"
2262   [(set_attr "type" "mve_move")
2263 ])
2264
2265 ;;
2266 ;; [vsubq_n_s, vsubq_n_u])
2267 ;;
2268 (define_insn "mve_vsubq_n_<supf><mode>"
2269   [
2270    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2271         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2272                        (match_operand:<V_elem> 2 "s_register_operand" "r")]
2273          VSUBQ_N))
2274   ]
2275   "TARGET_HAVE_MVE"
2276   "vsub.i%#<V_sz_elem>\t%q0, %q1, %2"
2277   [(set_attr "type" "mve_move")
2278 ])
2279
2280 ;;
2281 ;; [vsubq_s, vsubq_u])
2282 ;;
2283 (define_insn "mve_vsubq_<supf><mode>"
2284   [
2285    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2286         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2287                        (match_operand:MVE_2 2 "s_register_operand" "w")]
2288          VSUBQ))
2289   ]
2290   "TARGET_HAVE_MVE"
2291   "vsub.i%#<V_sz_elem>\t%q0, %q1, %q2"
2292   [(set_attr "type" "mve_move")
2293 ])
2294
2295 ;;
2296 ;; [vabdq_f])
2297 ;;
2298 (define_insn "mve_vabdq_f<mode>"
2299   [
2300    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2301         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2302                        (match_operand:MVE_0 2 "s_register_operand" "w")]
2303          VABDQ_F))
2304   ]
2305   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2306   "vabd.f%#<V_sz_elem>  %q0, %q1, %q2"
2307   [(set_attr "type" "mve_move")
2308 ])
2309
2310 ;;
2311 ;; [vaddlvaq_s vaddlvaq_u])
2312 ;;
2313 (define_insn "mve_vaddlvaq_<supf>v4si"
2314   [
2315    (set (match_operand:DI 0 "s_register_operand" "=r")
2316         (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
2317                     (match_operand:V4SI 2 "s_register_operand" "w")]
2318          VADDLVAQ))
2319   ]
2320   "TARGET_HAVE_MVE"
2321   "vaddlva.<supf>32 %Q0, %R0, %q2"
2322   [(set_attr "type" "mve_move")
2323 ])
2324
2325 ;;
2326 ;; [vaddq_n_f])
2327 ;;
2328 (define_insn "mve_vaddq_n_f<mode>"
2329   [
2330    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2331         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2332                        (match_operand:<V_elem> 2 "s_register_operand" "r")]
2333          VADDQ_N_F))
2334   ]
2335   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2336   "vadd.f%#<V_sz_elem>  %q0, %q1, %2"
2337   [(set_attr "type" "mve_move")
2338 ])
2339
2340 ;;
2341 ;; [vandq_f])
2342 ;;
2343 (define_insn "mve_vandq_f<mode>"
2344   [
2345    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2346         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2347                        (match_operand:MVE_0 2 "s_register_operand" "w")]
2348          VANDQ_F))
2349   ]
2350   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2351   "vand %q0, %q1, %q2"
2352   [(set_attr "type" "mve_move")
2353 ])
2354
2355 ;;
2356 ;; [vbicq_f])
2357 ;;
2358 (define_insn "mve_vbicq_f<mode>"
2359   [
2360    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2361         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2362                        (match_operand:MVE_0 2 "s_register_operand" "w")]
2363          VBICQ_F))
2364   ]
2365   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2366   "vbic %q0, %q1, %q2"
2367   [(set_attr "type" "mve_move")
2368 ])
2369
2370 ;;
2371 ;; [vbicq_n_s, vbicq_n_u])
2372 ;;
2373 (define_insn "mve_vbicq_n_<supf><mode>"
2374   [
2375    (set (match_operand:MVE_5 0 "s_register_operand" "=w")
2376         (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
2377                        (match_operand:SI 2 "immediate_operand" "i")]
2378          VBICQ_N))
2379   ]
2380   "TARGET_HAVE_MVE"
2381   "vbic.i%#<V_sz_elem>  %q0, %2"
2382   [(set_attr "type" "mve_move")
2383 ])
2384
2385 ;;
2386 ;; [vcaddq_rot270_f])
2387 ;;
2388 (define_insn "mve_vcaddq_rot270_f<mode>"
2389   [
2390    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2391         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2392                        (match_operand:MVE_0 2 "s_register_operand" "w")]
2393          VCADDQ_ROT270_F))
2394   ]
2395   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2396   "vcadd.f%#<V_sz_elem> %q0, %q1, %q2, #270"
2397   [(set_attr "type" "mve_move")
2398 ])
2399
2400 ;;
2401 ;; [vcaddq_rot90_f])
2402 ;;
2403 (define_insn "mve_vcaddq_rot90_f<mode>"
2404   [
2405    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2406         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2407                        (match_operand:MVE_0 2 "s_register_operand" "w")]
2408          VCADDQ_ROT90_F))
2409   ]
2410   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2411   "vcadd.f%#<V_sz_elem> %q0, %q1, %q2, #90"
2412   [(set_attr "type" "mve_move")
2413 ])
2414
2415 ;;
2416 ;; [vcmpeqq_f])
2417 ;;
2418 (define_insn "mve_vcmpeqq_f<mode>"
2419   [
2420    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2421         (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2422                     (match_operand:MVE_0 2 "s_register_operand" "w")]
2423          VCMPEQQ_F))
2424   ]
2425   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2426   "vcmp.f%#<V_sz_elem>  eq, %q1, %q2"
2427   [(set_attr "type" "mve_move")
2428 ])
2429
2430 ;;
2431 ;; [vcmpeqq_n_f])
2432 ;;
2433 (define_insn "mve_vcmpeqq_n_f<mode>"
2434   [
2435    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2436         (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2437                     (match_operand:<V_elem> 2 "s_register_operand" "r")]
2438          VCMPEQQ_N_F))
2439   ]
2440   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2441   "vcmp.f%#<V_sz_elem>  eq, %q1, %2"
2442   [(set_attr "type" "mve_move")
2443 ])
2444
2445 ;;
2446 ;; [vcmpgeq_f])
2447 ;;
2448 (define_insn "mve_vcmpgeq_f<mode>"
2449   [
2450    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2451         (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2452                     (match_operand:MVE_0 2 "s_register_operand" "w")]
2453          VCMPGEQ_F))
2454   ]
2455   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2456   "vcmp.f%#<V_sz_elem>  ge, %q1, %q2"
2457   [(set_attr "type" "mve_move")
2458 ])
2459
2460 ;;
2461 ;; [vcmpgeq_n_f])
2462 ;;
2463 (define_insn "mve_vcmpgeq_n_f<mode>"
2464   [
2465    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2466         (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2467                     (match_operand:<V_elem> 2 "s_register_operand" "r")]
2468          VCMPGEQ_N_F))
2469   ]
2470   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2471   "vcmp.f%#<V_sz_elem>  ge, %q1, %2"
2472   [(set_attr "type" "mve_move")
2473 ])
2474
2475 ;;
2476 ;; [vcmpgtq_f])
2477 ;;
2478 (define_insn "mve_vcmpgtq_f<mode>"
2479   [
2480    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2481         (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2482                     (match_operand:MVE_0 2 "s_register_operand" "w")]
2483          VCMPGTQ_F))
2484   ]
2485   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2486   "vcmp.f%#<V_sz_elem>  gt, %q1, %q2"
2487   [(set_attr "type" "mve_move")
2488 ])
2489
2490 ;;
2491 ;; [vcmpgtq_n_f])
2492 ;;
2493 (define_insn "mve_vcmpgtq_n_f<mode>"
2494   [
2495    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2496         (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2497                     (match_operand:<V_elem> 2 "s_register_operand" "r")]
2498          VCMPGTQ_N_F))
2499   ]
2500   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2501   "vcmp.f%#<V_sz_elem>  gt, %q1, %2"
2502   [(set_attr "type" "mve_move")
2503 ])
2504
2505 ;;
2506 ;; [vcmpleq_f])
2507 ;;
2508 (define_insn "mve_vcmpleq_f<mode>"
2509   [
2510    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2511         (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2512                     (match_operand:MVE_0 2 "s_register_operand" "w")]
2513          VCMPLEQ_F))
2514   ]
2515   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2516   "vcmp.f%#<V_sz_elem>  le, %q1, %q2"
2517   [(set_attr "type" "mve_move")
2518 ])
2519
2520 ;;
2521 ;; [vcmpleq_n_f])
2522 ;;
2523 (define_insn "mve_vcmpleq_n_f<mode>"
2524   [
2525    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2526         (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2527                     (match_operand:<V_elem> 2 "s_register_operand" "r")]
2528          VCMPLEQ_N_F))
2529   ]
2530   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2531   "vcmp.f%#<V_sz_elem>  le, %q1, %2"
2532   [(set_attr "type" "mve_move")
2533 ])
2534
2535 ;;
2536 ;; [vcmpltq_f])
2537 ;;
2538 (define_insn "mve_vcmpltq_f<mode>"
2539   [
2540    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2541         (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2542                     (match_operand:MVE_0 2 "s_register_operand" "w")]
2543          VCMPLTQ_F))
2544   ]
2545   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2546   "vcmp.f%#<V_sz_elem>  lt, %q1, %q2"
2547   [(set_attr "type" "mve_move")
2548 ])
2549
2550 ;;
2551 ;; [vcmpltq_n_f])
2552 ;;
2553 (define_insn "mve_vcmpltq_n_f<mode>"
2554   [
2555    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2556         (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2557                     (match_operand:<V_elem> 2 "s_register_operand" "r")]
2558          VCMPLTQ_N_F))
2559   ]
2560   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2561   "vcmp.f%#<V_sz_elem>  lt, %q1, %2"
2562   [(set_attr "type" "mve_move")
2563 ])
2564
2565 ;;
2566 ;; [vcmpneq_f])
2567 ;;
2568 (define_insn "mve_vcmpneq_f<mode>"
2569   [
2570    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2571         (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2572                     (match_operand:MVE_0 2 "s_register_operand" "w")]
2573          VCMPNEQ_F))
2574   ]
2575   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2576   "vcmp.f%#<V_sz_elem>  ne, %q1, %q2"
2577   [(set_attr "type" "mve_move")
2578 ])
2579
2580 ;;
2581 ;; [vcmpneq_n_f])
2582 ;;
2583 (define_insn "mve_vcmpneq_n_f<mode>"
2584   [
2585    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2586         (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2587                     (match_operand:<V_elem> 2 "s_register_operand" "r")]
2588          VCMPNEQ_N_F))
2589   ]
2590   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2591   "vcmp.f%#<V_sz_elem>  ne, %q1, %2"
2592   [(set_attr "type" "mve_move")
2593 ])
2594
2595 ;;
2596 ;; [vcmulq_f])
2597 ;;
2598 (define_insn "mve_vcmulq_f<mode>"
2599   [
2600    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2601         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2602                        (match_operand:MVE_0 2 "s_register_operand" "w")]
2603          VCMULQ_F))
2604   ]
2605   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2606   "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #0"
2607   [(set_attr "type" "mve_move")
2608 ])
2609
2610 ;;
2611 ;; [vcmulq_rot180_f])
2612 ;;
2613 (define_insn "mve_vcmulq_rot180_f<mode>"
2614   [
2615    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2616         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2617                        (match_operand:MVE_0 2 "s_register_operand" "w")]
2618          VCMULQ_ROT180_F))
2619   ]
2620   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2621   "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #180"
2622   [(set_attr "type" "mve_move")
2623 ])
2624
2625 ;;
2626 ;; [vcmulq_rot270_f])
2627 ;;
2628 (define_insn "mve_vcmulq_rot270_f<mode>"
2629   [
2630    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2631         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2632                        (match_operand:MVE_0 2 "s_register_operand" "w")]
2633          VCMULQ_ROT270_F))
2634   ]
2635   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2636   "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #270"
2637   [(set_attr "type" "mve_move")
2638 ])
2639
2640 ;;
2641 ;; [vcmulq_rot90_f])
2642 ;;
2643 (define_insn "mve_vcmulq_rot90_f<mode>"
2644   [
2645    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2646         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2647                        (match_operand:MVE_0 2 "s_register_operand" "w")]
2648          VCMULQ_ROT90_F))
2649   ]
2650   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2651   "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #90"
2652   [(set_attr "type" "mve_move")
2653 ])
2654
2655 ;;
2656 ;; [vctp8q_m vctp16q_m vctp32q_m vctp64q_m])
2657 ;;
2658 (define_insn "mve_vctp<mode1>q_mhi"
2659   [
2660    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2661         (unspec:HI [(match_operand:SI 1 "s_register_operand" "r")
2662                     (match_operand:HI 2 "vpr_register_operand" "Up")]
2663          VCTPQ_M))
2664   ]
2665   "TARGET_HAVE_MVE"
2666   "vpst\;vctpt.<mode1> %1"
2667   [(set_attr "type" "mve_move")
2668    (set_attr "length""8")])
2669
2670 ;;
2671 ;; [vcvtbq_f16_f32])
2672 ;;
2673 (define_insn "mve_vcvtbq_f16_f32v8hf"
2674   [
2675    (set (match_operand:V8HF 0 "s_register_operand" "=w")
2676         (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
2677                       (match_operand:V4SF 2 "s_register_operand" "w")]
2678          VCVTBQ_F16_F32))
2679   ]
2680   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2681   "vcvtb.f16.f32 %q0, %q2"
2682   [(set_attr "type" "mve_move")
2683 ])
2684
2685 ;;
2686 ;; [vcvttq_f16_f32])
2687 ;;
2688 (define_insn "mve_vcvttq_f16_f32v8hf"
2689   [
2690    (set (match_operand:V8HF 0 "s_register_operand" "=w")
2691         (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
2692                       (match_operand:V4SF 2 "s_register_operand" "w")]
2693          VCVTTQ_F16_F32))
2694   ]
2695   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2696   "vcvtt.f16.f32 %q0, %q2"
2697   [(set_attr "type" "mve_move")
2698 ])
2699
2700 ;;
2701 ;; [veorq_f])
2702 ;;
2703 (define_insn "mve_veorq_f<mode>"
2704   [
2705    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2706         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2707                        (match_operand:MVE_0 2 "s_register_operand" "w")]
2708          VEORQ_F))
2709   ]
2710   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2711   "veor %q0, %q1, %q2"
2712   [(set_attr "type" "mve_move")
2713 ])
2714
2715 ;;
2716 ;; [vmaxnmaq_f])
2717 ;;
2718 (define_insn "mve_vmaxnmaq_f<mode>"
2719   [
2720    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2721         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
2722                        (match_operand:MVE_0 2 "s_register_operand" "w")]
2723          VMAXNMAQ_F))
2724   ]
2725   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2726   "vmaxnma.f%#<V_sz_elem>       %q0, %q2"
2727   [(set_attr "type" "mve_move")
2728 ])
2729
2730 ;;
2731 ;; [vmaxnmavq_f])
2732 ;;
2733 (define_insn "mve_vmaxnmavq_f<mode>"
2734   [
2735    (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
2736         (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
2737                           (match_operand:MVE_0 2 "s_register_operand" "w")]
2738          VMAXNMAVQ_F))
2739   ]
2740   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2741   "vmaxnmav.f%#<V_sz_elem>      %0, %q2"
2742   [(set_attr "type" "mve_move")
2743 ])
2744
2745 ;;
2746 ;; [vmaxnmq_f])
2747 ;;
2748 (define_insn "mve_vmaxnmq_f<mode>"
2749   [
2750    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2751         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2752                        (match_operand:MVE_0 2 "s_register_operand" "w")]
2753          VMAXNMQ_F))
2754   ]
2755   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2756   "vmaxnm.f%#<V_sz_elem>        %q0, %q1, %q2"
2757   [(set_attr "type" "mve_move")
2758 ])
2759
2760 ;;
2761 ;; [vmaxnmvq_f])
2762 ;;
2763 (define_insn "mve_vmaxnmvq_f<mode>"
2764   [
2765    (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
2766         (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
2767                           (match_operand:MVE_0 2 "s_register_operand" "w")]
2768          VMAXNMVQ_F))
2769   ]
2770   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2771   "vmaxnmv.f%#<V_sz_elem>       %0, %q2"
2772   [(set_attr "type" "mve_move")
2773 ])
2774
2775 ;;
2776 ;; [vminnmaq_f])
2777 ;;
2778 (define_insn "mve_vminnmaq_f<mode>"
2779   [
2780    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2781         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
2782                        (match_operand:MVE_0 2 "s_register_operand" "w")]
2783          VMINNMAQ_F))
2784   ]
2785   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2786   "vminnma.f%#<V_sz_elem>       %q0, %q2"
2787   [(set_attr "type" "mve_move")
2788 ])
2789
2790 ;;
2791 ;; [vminnmavq_f])
2792 ;;
2793 (define_insn "mve_vminnmavq_f<mode>"
2794   [
2795    (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
2796         (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
2797                           (match_operand:MVE_0 2 "s_register_operand" "w")]
2798          VMINNMAVQ_F))
2799   ]
2800   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2801   "vminnmav.f%#<V_sz_elem>      %0, %q2"
2802   [(set_attr "type" "mve_move")
2803 ])
2804
2805 ;;
2806 ;; [vminnmq_f])
2807 ;;
2808 (define_insn "mve_vminnmq_f<mode>"
2809   [
2810    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2811         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2812                        (match_operand:MVE_0 2 "s_register_operand" "w")]
2813          VMINNMQ_F))
2814   ]
2815   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2816   "vminnm.f%#<V_sz_elem>        %q0, %q1, %q2"
2817   [(set_attr "type" "mve_move")
2818 ])
2819
2820 ;;
2821 ;; [vminnmvq_f])
2822 ;;
2823 (define_insn "mve_vminnmvq_f<mode>"
2824   [
2825    (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
2826         (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
2827                           (match_operand:MVE_0 2 "s_register_operand" "w")]
2828          VMINNMVQ_F))
2829   ]
2830   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2831   "vminnmv.f%#<V_sz_elem>       %0, %q2"
2832   [(set_attr "type" "mve_move")
2833 ])
2834
2835 ;;
2836 ;; [vmlaldavq_u, vmlaldavq_s])
2837 ;;
2838 (define_insn "mve_vmlaldavq_<supf><mode>"
2839   [
2840    (set (match_operand:DI 0 "s_register_operand" "=r")
2841         (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
2842                     (match_operand:MVE_5 2 "s_register_operand" "w")]
2843          VMLALDAVQ))
2844   ]
2845   "TARGET_HAVE_MVE"
2846   "vmlaldav.<supf>%#<V_sz_elem> %Q0, %R0, %q1, %q2"
2847   [(set_attr "type" "mve_move")
2848 ])
2849
2850 ;;
2851 ;; [vmlaldavxq_s])
2852 ;;
2853 (define_insn "mve_vmlaldavxq_s<mode>"
2854   [
2855    (set (match_operand:DI 0 "s_register_operand" "=r")
2856         (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
2857                     (match_operand:MVE_5 2 "s_register_operand" "w")]
2858          VMLALDAVXQ_S))
2859   ]
2860   "TARGET_HAVE_MVE"
2861   "vmlaldavx.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
2862   [(set_attr "type" "mve_move")
2863 ])
2864
2865 ;;
2866 ;; [vmlsldavq_s])
2867 ;;
2868 (define_insn "mve_vmlsldavq_s<mode>"
2869   [
2870    (set (match_operand:DI 0 "s_register_operand" "=r")
2871         (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
2872                     (match_operand:MVE_5 2 "s_register_operand" "w")]
2873          VMLSLDAVQ_S))
2874   ]
2875   "TARGET_HAVE_MVE"
2876   "vmlsldav.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
2877   [(set_attr "type" "mve_move")
2878 ])
2879
2880 ;;
2881 ;; [vmlsldavxq_s])
2882 ;;
2883 (define_insn "mve_vmlsldavxq_s<mode>"
2884   [
2885    (set (match_operand:DI 0 "s_register_operand" "=r")
2886         (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
2887                     (match_operand:MVE_5 2 "s_register_operand" "w")]
2888          VMLSLDAVXQ_S))
2889   ]
2890   "TARGET_HAVE_MVE"
2891   "vmlsldavx.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
2892   [(set_attr "type" "mve_move")
2893 ])
2894
2895 ;;
2896 ;; [vmovnbq_u, vmovnbq_s])
2897 ;;
2898 (define_insn "mve_vmovnbq_<supf><mode>"
2899   [
2900    (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
2901         (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
2902                                  (match_operand:MVE_5 2 "s_register_operand" "w")]
2903          VMOVNBQ))
2904   ]
2905   "TARGET_HAVE_MVE"
2906   "vmovnb.i%#<V_sz_elem>        %q0, %q2"
2907   [(set_attr "type" "mve_move")
2908 ])
2909
2910 ;;
2911 ;; [vmovntq_s, vmovntq_u])
2912 ;;
2913 (define_insn "mve_vmovntq_<supf><mode>"
2914   [
2915    (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
2916         (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
2917                                  (match_operand:MVE_5 2 "s_register_operand" "w")]
2918          VMOVNTQ))
2919   ]
2920   "TARGET_HAVE_MVE"
2921   "vmovnt.i%#<V_sz_elem>        %q0, %q2"
2922   [(set_attr "type" "mve_move")
2923 ])
2924
2925 ;;
2926 ;; [vmulq_f])
2927 ;;
2928 (define_insn "mve_vmulq_f<mode>"
2929   [
2930    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2931         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2932                        (match_operand:MVE_0 2 "s_register_operand" "w")]
2933          VMULQ_F))
2934   ]
2935   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2936   "vmul.f%#<V_sz_elem>  %q0, %q1, %q2"
2937   [(set_attr "type" "mve_move")
2938 ])
2939
2940 ;;
2941 ;; [vmulq_n_f])
2942 ;;
2943 (define_insn "mve_vmulq_n_f<mode>"
2944   [
2945    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2946         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2947                        (match_operand:<V_elem> 2 "s_register_operand" "r")]
2948          VMULQ_N_F))
2949   ]
2950   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2951   "vmul.f%#<V_sz_elem>  %q0, %q1, %2"
2952   [(set_attr "type" "mve_move")
2953 ])
2954
2955 ;;
2956 ;; [vornq_f])
2957 ;;
2958 (define_insn "mve_vornq_f<mode>"
2959   [
2960    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2961         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2962                        (match_operand:MVE_0 2 "s_register_operand" "w")]
2963          VORNQ_F))
2964   ]
2965   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2966   "vorn %q0, %q1, %q2"
2967   [(set_attr "type" "mve_move")
2968 ])
2969
2970 ;;
2971 ;; [vorrq_f])
2972 ;;
2973 (define_insn "mve_vorrq_f<mode>"
2974   [
2975    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2976         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2977                        (match_operand:MVE_0 2 "s_register_operand" "w")]
2978          VORRQ_F))
2979   ]
2980   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2981   "vorr %q0, %q1, %q2"
2982   [(set_attr "type" "mve_move")
2983 ])
2984
2985 ;;
2986 ;; [vorrq_n_u, vorrq_n_s])
2987 ;;
2988 (define_insn "mve_vorrq_n_<supf><mode>"
2989   [
2990    (set (match_operand:MVE_5 0 "s_register_operand" "=w")
2991         (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
2992                        (match_operand:SI 2 "immediate_operand" "i")]
2993          VORRQ_N))
2994   ]
2995   "TARGET_HAVE_MVE"
2996   "vorr.i%#<V_sz_elem>  %q0, %2"
2997   [(set_attr "type" "mve_move")
2998 ])
2999
3000 ;;
3001 ;; [vqdmullbq_n_s])
3002 ;;
3003 (define_insn "mve_vqdmullbq_n_s<mode>"
3004   [
3005    (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
3006         (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w")
3007                                   (match_operand:<V_elem> 2 "s_register_operand" "r")]
3008          VQDMULLBQ_N_S))
3009   ]
3010   "TARGET_HAVE_MVE"
3011   "vqdmullb.s%#<V_sz_elem>      %q0, %q1, %2"
3012   [(set_attr "type" "mve_move")
3013 ])
3014
3015 ;;
3016 ;; [vqdmullbq_s])
3017 ;;
3018 (define_insn "mve_vqdmullbq_s<mode>"
3019   [
3020    (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
3021         (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w")
3022                                   (match_operand:MVE_5 2 "s_register_operand" "w")]
3023          VQDMULLBQ_S))
3024   ]
3025   "TARGET_HAVE_MVE"
3026   "vqdmullb.s%#<V_sz_elem>      %q0, %q1, %q2"
3027   [(set_attr "type" "mve_move")
3028 ])
3029
3030 ;;
3031 ;; [vqdmulltq_n_s])
3032 ;;
3033 (define_insn "mve_vqdmulltq_n_s<mode>"
3034   [
3035    (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
3036         (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w")
3037                                   (match_operand:<V_elem> 2 "s_register_operand" "r")]
3038          VQDMULLTQ_N_S))
3039   ]
3040   "TARGET_HAVE_MVE"
3041   "vqdmullt.s%#<V_sz_elem>      %q0, %q1, %2"
3042   [(set_attr "type" "mve_move")
3043 ])
3044
3045 ;;
3046 ;; [vqdmulltq_s])
3047 ;;
3048 (define_insn "mve_vqdmulltq_s<mode>"
3049   [
3050    (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
3051         (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w")
3052                                   (match_operand:MVE_5 2 "s_register_operand" "w")]
3053          VQDMULLTQ_S))
3054   ]
3055   "TARGET_HAVE_MVE"
3056   "vqdmullt.s%#<V_sz_elem>      %q0, %q1, %q2"
3057   [(set_attr "type" "mve_move")
3058 ])
3059
3060 ;;
3061 ;; [vqmovnbq_u, vqmovnbq_s])
3062 ;;
3063 (define_insn "mve_vqmovnbq_<supf><mode>"
3064   [
3065    (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3066         (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3067                                  (match_operand:MVE_5 2 "s_register_operand" "w")]
3068          VQMOVNBQ))
3069   ]
3070   "TARGET_HAVE_MVE"
3071   "vqmovnb.<supf>%#<V_sz_elem>  %q0, %q2"
3072   [(set_attr "type" "mve_move")
3073 ])
3074
3075 ;;
3076 ;; [vqmovntq_u, vqmovntq_s])
3077 ;;
3078 (define_insn "mve_vqmovntq_<supf><mode>"
3079   [
3080    (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3081         (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3082                                  (match_operand:MVE_5 2 "s_register_operand" "w")]
3083          VQMOVNTQ))
3084   ]
3085   "TARGET_HAVE_MVE"
3086   "vqmovnt.<supf>%#<V_sz_elem>  %q0, %q2"
3087   [(set_attr "type" "mve_move")
3088 ])
3089
3090 ;;
3091 ;; [vqmovunbq_s])
3092 ;;
3093 (define_insn "mve_vqmovunbq_s<mode>"
3094   [
3095    (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3096         (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3097                                  (match_operand:MVE_5 2 "s_register_operand" "w")]
3098          VQMOVUNBQ_S))
3099   ]
3100   "TARGET_HAVE_MVE"
3101   "vqmovunb.s%#<V_sz_elem>      %q0, %q2"
3102   [(set_attr "type" "mve_move")
3103 ])
3104
3105 ;;
3106 ;; [vqmovuntq_s])
3107 ;;
3108 (define_insn "mve_vqmovuntq_s<mode>"
3109   [
3110    (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3111         (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3112                                  (match_operand:MVE_5 2 "s_register_operand" "w")]
3113          VQMOVUNTQ_S))
3114   ]
3115   "TARGET_HAVE_MVE"
3116   "vqmovunt.s%#<V_sz_elem>      %q0, %q2"
3117   [(set_attr "type" "mve_move")
3118 ])
3119
3120 ;;
3121 ;; [vrmlaldavhxq_s])
3122 ;;
3123 (define_insn "mve_vrmlaldavhxq_sv4si"
3124   [
3125    (set (match_operand:DI 0 "s_register_operand" "=r")
3126         (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
3127                     (match_operand:V4SI 2 "s_register_operand" "w")]
3128          VRMLALDAVHXQ_S))
3129   ]
3130   "TARGET_HAVE_MVE"
3131   "vrmlaldavhx.s32 %Q0, %R0, %q1, %q2"
3132   [(set_attr "type" "mve_move")
3133 ])
3134
3135 ;;
3136 ;; [vrmlsldavhq_s])
3137 ;;
3138 (define_insn "mve_vrmlsldavhq_sv4si"
3139   [
3140    (set (match_operand:DI 0 "s_register_operand" "=r")
3141         (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
3142                     (match_operand:V4SI 2 "s_register_operand" "w")]
3143          VRMLSLDAVHQ_S))
3144   ]
3145   "TARGET_HAVE_MVE"
3146   "vrmlsldavh.s32\t%Q0, %R0, %q1, %q2"
3147   [(set_attr "type" "mve_move")
3148 ])
3149
3150 ;;
3151 ;; [vrmlsldavhxq_s])
3152 ;;
3153 (define_insn "mve_vrmlsldavhxq_sv4si"
3154   [
3155    (set (match_operand:DI 0 "s_register_operand" "=r")
3156         (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
3157                     (match_operand:V4SI 2 "s_register_operand" "w")]
3158          VRMLSLDAVHXQ_S))
3159   ]
3160   "TARGET_HAVE_MVE"
3161   "vrmlsldavhx.s32\t%Q0, %R0, %q1, %q2"
3162   [(set_attr "type" "mve_move")
3163 ])
3164
3165 ;;
3166 ;; [vshllbq_n_s, vshllbq_n_u])
3167 ;;
3168 (define_insn "mve_vshllbq_n_<supf><mode>"
3169   [
3170    (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
3171         (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")
3172                                   (match_operand:SI 2 "immediate_operand" "i")]
3173          VSHLLBQ_N))
3174   ]
3175   "TARGET_HAVE_MVE"
3176   "vshllb.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
3177   [(set_attr "type" "mve_move")
3178 ])
3179
3180 ;;
3181 ;; [vshlltq_n_u, vshlltq_n_s])
3182 ;;
3183 (define_insn "mve_vshlltq_n_<supf><mode>"
3184   [
3185    (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
3186         (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")
3187                                   (match_operand:SI 2 "immediate_operand" "i")]
3188          VSHLLTQ_N))
3189   ]
3190   "TARGET_HAVE_MVE"
3191   "vshllt.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
3192   [(set_attr "type" "mve_move")
3193 ])
3194
3195 ;;
3196 ;; [vsubq_f])
3197 ;;
3198 (define_insn "mve_vsubq_f<mode>"
3199   [
3200    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
3201         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
3202                        (match_operand:MVE_0 2 "s_register_operand" "w")]
3203          VSUBQ_F))
3204   ]
3205   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3206   "vsub.f%#<V_sz_elem>\t%q0, %q1, %q2"
3207   [(set_attr "type" "mve_move")
3208 ])
3209
3210 ;;
3211 ;; [vmulltq_poly_p])
3212 ;;
3213 (define_insn "mve_vmulltq_poly_p<mode>"
3214   [
3215    (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
3216         (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")
3217                                   (match_operand:MVE_3 2 "s_register_operand" "w")]
3218          VMULLTQ_POLY_P))
3219   ]
3220   "TARGET_HAVE_MVE"
3221   "vmullt.p%#<V_sz_elem>\t%q0, %q1, %q2"
3222   [(set_attr "type" "mve_move")
3223 ])
3224
3225 ;;
3226 ;; [vmullbq_poly_p])
3227 ;;
3228 (define_insn "mve_vmullbq_poly_p<mode>"
3229   [
3230    (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
3231         (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")
3232                                   (match_operand:MVE_3 2 "s_register_operand" "w")]
3233          VMULLBQ_POLY_P))
3234   ]
3235   "TARGET_HAVE_MVE"
3236   "vmullb.p%#<V_sz_elem>\t%q0, %q1, %q2"
3237   [(set_attr "type" "mve_move")
3238 ])
3239
3240 ;;
3241 ;; [vrmlaldavhq_u vrmlaldavhq_s])
3242 ;;
3243 (define_insn "mve_vrmlaldavhq_<supf>v4si"
3244   [
3245    (set (match_operand:DI 0 "s_register_operand" "=r")
3246         (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
3247                     (match_operand:V4SI 2 "s_register_operand" "w")]
3248          VRMLALDAVHQ))
3249   ]
3250   "TARGET_HAVE_MVE"
3251   "vrmlaldavh.<supf>32 %Q0, %R0, %q1, %q2"
3252   [(set_attr "type" "mve_move")
3253 ])
3254
3255 ;;
3256 ;; [vbicq_m_n_s, vbicq_m_n_u])
3257 ;;
3258 (define_insn "mve_vbicq_m_n_<supf><mode>"
3259   [
3260    (set (match_operand:MVE_5 0 "s_register_operand" "=w")
3261         (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
3262                        (match_operand:SI 2 "immediate_operand" "i")
3263                        (match_operand:HI 3 "vpr_register_operand" "Up")]
3264          VBICQ_M_N))
3265   ]
3266   "TARGET_HAVE_MVE"
3267   "vpst\;vbict.i%#<V_sz_elem>   %q0, %2"
3268   [(set_attr "type" "mve_move")
3269    (set_attr "length""8")])
3270 ;;
3271 ;; [vcmpeqq_m_f])
3272 ;;
3273 (define_insn "mve_vcmpeqq_m_f<mode>"
3274   [
3275    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3276         (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
3277                     (match_operand:MVE_0 2 "s_register_operand" "w")
3278                     (match_operand:HI 3 "vpr_register_operand" "Up")]
3279          VCMPEQQ_M_F))
3280   ]
3281   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3282   "vpst\;vcmpt.f%#<V_sz_elem>   eq, %q1, %q2"
3283   [(set_attr "type" "mve_move")
3284    (set_attr "length""8")])
3285 ;;
3286 ;; [vcvtaq_m_u, vcvtaq_m_s])
3287 ;;
3288 (define_insn "mve_vcvtaq_m_<supf><mode>"
3289   [
3290    (set (match_operand:MVE_5 0 "s_register_operand" "=w")
3291         (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
3292                        (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
3293                        (match_operand:HI 3 "vpr_register_operand" "Up")]
3294          VCVTAQ_M))
3295   ]
3296   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3297   "vpst\;vcvtat.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
3298   [(set_attr "type" "mve_move")
3299    (set_attr "length""8")])
3300 ;;
3301 ;; [vcvtq_m_to_f_s, vcvtq_m_to_f_u])
3302 ;;
3303 (define_insn "mve_vcvtq_m_to_f_<supf><mode>"
3304   [
3305    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
3306         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
3307                        (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
3308                        (match_operand:HI 3 "vpr_register_operand" "Up")]
3309          VCVTQ_M_TO_F))
3310   ]
3311   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3312   "vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>        %q0, %q2"
3313   [(set_attr "type" "mve_move")
3314    (set_attr "length""8")])
3315 ;;
3316 ;; [vqrshrnbq_n_u, vqrshrnbq_n_s])
3317 ;;
3318 (define_insn "mve_vqrshrnbq_n_<supf><mode>"
3319   [
3320    (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3321         (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3322                                  (match_operand:MVE_5 2 "s_register_operand" "w")
3323                                  (match_operand:SI 3 "mve_imm_8" "Rb")]
3324          VQRSHRNBQ_N))
3325   ]
3326   "TARGET_HAVE_MVE"
3327   "vqrshrnb.<supf>%#<V_sz_elem> %q0, %q2, %3"
3328   [(set_attr "type" "mve_move")
3329 ])
3330 ;;
3331 ;; [vqrshrunbq_n_s])
3332 ;;
3333 (define_insn "mve_vqrshrunbq_n_s<mode>"
3334   [
3335    (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3336         (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3337                                  (match_operand:MVE_5 2 "s_register_operand" "w")
3338                                  (match_operand:SI 3 "mve_imm_8" "Rb")]
3339          VQRSHRUNBQ_N_S))
3340   ]
3341   "TARGET_HAVE_MVE"
3342   "vqrshrunb.s%#<V_sz_elem>\t%q0, %q2, %3"
3343   [(set_attr "type" "mve_move")
3344 ])
3345 ;;
3346 ;; [vrmlaldavhaq_s vrmlaldavhaq_u])
3347 ;;
3348 (define_insn "mve_vrmlaldavhaq_<supf>v4si"
3349   [
3350    (set (match_operand:DI 0 "s_register_operand" "=r")
3351         (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
3352                     (match_operand:V4SI 2 "s_register_operand" "w")
3353                     (match_operand:V4SI 3 "s_register_operand" "w")]
3354          VRMLALDAVHAQ))
3355   ]
3356   "TARGET_HAVE_MVE"
3357   "vrmlaldavha.<supf>32 %Q0, %R0, %q2, %q3"
3358   [(set_attr "type" "mve_move")
3359 ])
3360
3361 ;;
3362 ;; [vabavq_s, vabavq_u])
3363 ;;
3364 (define_insn "mve_vabavq_<supf><mode>"
3365   [
3366    (set (match_operand:SI 0 "s_register_operand" "=r")
3367         (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
3368                     (match_operand:MVE_2 2 "s_register_operand" "w")
3369                     (match_operand:MVE_2 3 "s_register_operand" "w")]
3370          VABAVQ))
3371   ]
3372   "TARGET_HAVE_MVE"
3373   "vabav.<supf>%#<V_sz_elem>\t%0, %q2, %q3"
3374   [(set_attr "type" "mve_move")
3375 ])
3376
3377 ;;
3378 ;; [vshlcq_u vshlcq_s]
3379 ;;
3380 (define_expand "mve_vshlcq_vec_<supf><mode>"
3381  [(match_operand:MVE_2 0 "s_register_operand")
3382   (match_operand:MVE_2 1 "s_register_operand")
3383   (match_operand:SI 2 "s_register_operand")
3384   (match_operand:SI 3 "mve_imm_32")
3385   (unspec:MVE_2 [(const_int 0)] VSHLCQ)]
3386  "TARGET_HAVE_MVE"
3387 {
3388   rtx ignore_wb = gen_reg_rtx (SImode);
3389   emit_insn(gen_mve_vshlcq_<supf><mode>(operands[0], ignore_wb, operands[1],
3390                                       operands[2], operands[3]));
3391   DONE;
3392 })
3393
3394 (define_expand "mve_vshlcq_carry_<supf><mode>"
3395  [(match_operand:SI 0 "s_register_operand")
3396   (match_operand:MVE_2 1 "s_register_operand")
3397   (match_operand:SI 2 "s_register_operand")
3398   (match_operand:SI 3 "mve_imm_32")
3399   (unspec:MVE_2 [(const_int 0)] VSHLCQ)]
3400  "TARGET_HAVE_MVE"
3401 {
3402   rtx ignore_vec = gen_reg_rtx (<MODE>mode);
3403   emit_insn(gen_mve_vshlcq_<supf><mode>(ignore_vec, operands[0], operands[1],
3404                                       operands[2], operands[3]));
3405   DONE;
3406 })
3407
3408 (define_insn "mve_vshlcq_<supf><mode>"
3409  [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
3410        (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0")
3411                       (match_operand:SI 3 "s_register_operand" "1")
3412                       (match_operand:SI 4 "mve_imm_32" "Rf")]
3413         VSHLCQ))
3414   (set (match_operand:SI  1 "s_register_operand" "=r")
3415        (unspec:SI [(match_dup 2)
3416                    (match_dup 3)
3417                    (match_dup 4)]
3418         VSHLCQ))]
3419  "TARGET_HAVE_MVE"
3420  "vshlc %q0, %1, %4")
3421
3422 ;;
3423 ;; [vabsq_m_s])
3424 ;;
3425 (define_insn "mve_vabsq_m_s<mode>"
3426   [
3427    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3428         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3429                        (match_operand:MVE_2 2 "s_register_operand" "w")
3430                        (match_operand:HI 3 "vpr_register_operand" "Up")]
3431          VABSQ_M_S))
3432   ]
3433   "TARGET_HAVE_MVE"
3434   "vpst\;vabst.s%#<V_sz_elem>   %q0, %q2"
3435   [(set_attr "type" "mve_move")
3436    (set_attr "length""8")])
3437
3438 ;;
3439 ;; [vaddvaq_p_u, vaddvaq_p_s])
3440 ;;
3441 (define_insn "mve_vaddvaq_p_<supf><mode>"
3442   [
3443    (set (match_operand:SI 0 "s_register_operand" "=e")
3444         (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
3445                        (match_operand:MVE_2 2 "s_register_operand" "w")
3446                        (match_operand:HI 3 "vpr_register_operand" "Up")]
3447          VADDVAQ_P))
3448   ]
3449   "TARGET_HAVE_MVE"
3450   "vpst\;vaddvat.<supf>%#<V_sz_elem>    %0, %q2"
3451   [(set_attr "type" "mve_move")
3452    (set_attr "length""8")])
3453
3454 ;;
3455 ;; [vclsq_m_s])
3456 ;;
3457 (define_insn "mve_vclsq_m_s<mode>"
3458   [
3459    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3460         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3461                        (match_operand:MVE_2 2 "s_register_operand" "w")
3462                        (match_operand:HI 3 "vpr_register_operand" "Up")]
3463          VCLSQ_M_S))
3464   ]
3465   "TARGET_HAVE_MVE"
3466   "vpst\;vclst.s%#<V_sz_elem>   %q0, %q2"
3467   [(set_attr "type" "mve_move")
3468    (set_attr "length""8")])
3469
3470 ;;
3471 ;; [vclzq_m_s, vclzq_m_u])
3472 ;;
3473 (define_insn "mve_vclzq_m_<supf><mode>"
3474   [
3475    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3476         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3477                        (match_operand:MVE_2 2 "s_register_operand" "w")
3478                        (match_operand:HI 3 "vpr_register_operand" "Up")]
3479          VCLZQ_M))
3480   ]
3481   "TARGET_HAVE_MVE"
3482   "vpst\;vclzt.i%#<V_sz_elem>   %q0, %q2"
3483   [(set_attr "type" "mve_move")
3484    (set_attr "length""8")])
3485
3486 ;;
3487 ;; [vcmpcsq_m_n_u])
3488 ;;
3489 (define_insn "mve_vcmpcsq_m_n_u<mode>"
3490   [
3491    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3492         (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3493                        (match_operand:<V_elem> 2 "s_register_operand" "r")
3494                        (match_operand:HI 3 "vpr_register_operand" "Up")]
3495          VCMPCSQ_M_N_U))
3496   ]
3497   "TARGET_HAVE_MVE"
3498   "vpst\;vcmpt.u%#<V_sz_elem>   cs, %q1, %2"
3499   [(set_attr "type" "mve_move")
3500    (set_attr "length""8")])
3501
3502 ;;
3503 ;; [vcmpcsq_m_u])
3504 ;;
3505 (define_insn "mve_vcmpcsq_m_u<mode>"
3506   [
3507    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3508         (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3509                        (match_operand:MVE_2 2 "s_register_operand" "w")
3510                        (match_operand:HI 3 "vpr_register_operand" "Up")]
3511          VCMPCSQ_M_U))
3512   ]
3513   "TARGET_HAVE_MVE"
3514   "vpst\;vcmpt.u%#<V_sz_elem>   cs, %q1, %q2"
3515   [(set_attr "type" "mve_move")
3516    (set_attr "length""8")])
3517
3518 ;;
3519 ;; [vcmpeqq_m_n_u, vcmpeqq_m_n_s])
3520 ;;
3521 (define_insn "mve_vcmpeqq_m_n_<supf><mode>"
3522   [
3523    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3524         (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3525                        (match_operand:<V_elem> 2 "s_register_operand" "r")
3526                        (match_operand:HI 3 "vpr_register_operand" "Up")]
3527          VCMPEQQ_M_N))
3528   ]
3529   "TARGET_HAVE_MVE"
3530   "vpst\;vcmpt.i%#<V_sz_elem>   eq, %q1, %2"
3531   [(set_attr "type" "mve_move")
3532    (set_attr "length""8")])
3533
3534 ;;
3535 ;; [vcmpeqq_m_u, vcmpeqq_m_s])
3536 ;;
3537 (define_insn "mve_vcmpeqq_m_<supf><mode>"
3538   [
3539    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3540         (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3541                        (match_operand:MVE_2 2 "s_register_operand" "w")
3542                        (match_operand:HI 3 "vpr_register_operand" "Up")]
3543          VCMPEQQ_M))
3544   ]
3545   "TARGET_HAVE_MVE"
3546   "vpst\;vcmpt.i%#<V_sz_elem>   eq, %q1, %q2"
3547   [(set_attr "type" "mve_move")
3548    (set_attr "length""8")])
3549
3550 ;;
3551 ;; [vcmpgeq_m_n_s])
3552 ;;
3553 (define_insn "mve_vcmpgeq_m_n_s<mode>"
3554   [
3555    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3556         (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3557                        (match_operand:<V_elem> 2 "s_register_operand" "r")
3558                        (match_operand:HI 3 "vpr_register_operand" "Up")]
3559          VCMPGEQ_M_N_S))
3560   ]
3561   "TARGET_HAVE_MVE"
3562   "vpst\;vcmpt.s%#<V_sz_elem>   ge, %q1, %2"
3563   [(set_attr "type" "mve_move")
3564    (set_attr "length""8")])
3565
3566 ;;
3567 ;; [vcmpgeq_m_s])
3568 ;;
3569 (define_insn "mve_vcmpgeq_m_s<mode>"
3570   [
3571    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3572         (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3573                        (match_operand:MVE_2 2 "s_register_operand" "w")
3574                        (match_operand:HI 3 "vpr_register_operand" "Up")]
3575          VCMPGEQ_M_S))
3576   ]
3577   "TARGET_HAVE_MVE"
3578   "vpst\;vcmpt.s%#<V_sz_elem>   ge, %q1, %q2"
3579   [(set_attr "type" "mve_move")
3580    (set_attr "length""8")])
3581
3582 ;;
3583 ;; [vcmpgtq_m_n_s])
3584 ;;
3585 (define_insn "mve_vcmpgtq_m_n_s<mode>"
3586   [
3587    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3588         (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3589                        (match_operand:<V_elem> 2 "s_register_operand" "r")
3590                        (match_operand:HI 3 "vpr_register_operand" "Up")]
3591          VCMPGTQ_M_N_S))
3592   ]
3593   "TARGET_HAVE_MVE"
3594   "vpst\;vcmpt.s%#<V_sz_elem>   gt, %q1, %2"
3595   [(set_attr "type" "mve_move")
3596    (set_attr "length""8")])
3597
3598 ;;
3599 ;; [vcmpgtq_m_s])
3600 ;;
3601 (define_insn "mve_vcmpgtq_m_s<mode>"
3602   [
3603    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3604         (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3605                        (match_operand:MVE_2 2 "s_register_operand" "w")
3606                        (match_operand:HI 3 "vpr_register_operand" "Up")]
3607          VCMPGTQ_M_S))
3608   ]
3609   "TARGET_HAVE_MVE"
3610   "vpst\;vcmpt.s%#<V_sz_elem>   gt, %q1, %q2"
3611   [(set_attr "type" "mve_move")
3612    (set_attr "length""8")])
3613
3614 ;;
3615 ;; [vcmphiq_m_n_u])
3616 ;;
3617 (define_insn "mve_vcmphiq_m_n_u<mode>"
3618   [
3619    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3620         (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3621                        (match_operand:<V_elem> 2 "s_register_operand" "r")
3622                        (match_operand:HI 3 "vpr_register_operand" "Up")]
3623          VCMPHIQ_M_N_U))
3624   ]
3625   "TARGET_HAVE_MVE"
3626   "vpst\;vcmpt.u%#<V_sz_elem>   hi, %q1, %2"
3627   [(set_attr "type" "mve_move")
3628    (set_attr "length""8")])
3629
3630 ;;
3631 ;; [vcmphiq_m_u])
3632 ;;
3633 (define_insn "mve_vcmphiq_m_u<mode>"
3634   [
3635    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3636         (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3637                        (match_operand:MVE_2 2 "s_register_operand" "w")
3638                        (match_operand:HI 3 "vpr_register_operand" "Up")]
3639          VCMPHIQ_M_U))
3640   ]
3641   "TARGET_HAVE_MVE"
3642   "vpst\;vcmpt.u%#<V_sz_elem>   hi, %q1, %q2"
3643   [(set_attr "type" "mve_move")
3644    (set_attr "length""8")])
3645
3646 ;;
3647 ;; [vcmpleq_m_n_s])
3648 ;;
3649 (define_insn "mve_vcmpleq_m_n_s<mode>"
3650   [
3651    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3652         (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3653                        (match_operand:<V_elem> 2 "s_register_operand" "r")
3654                        (match_operand:HI 3 "vpr_register_operand" "Up")]
3655          VCMPLEQ_M_N_S))
3656   ]
3657   "TARGET_HAVE_MVE"
3658   "vpst\;vcmpt.s%#<V_sz_elem>   le, %q1, %2"
3659   [(set_attr "type" "mve_move")
3660    (set_attr "length""8")])
3661
3662 ;;
3663 ;; [vcmpleq_m_s])
3664 ;;
3665 (define_insn "mve_vcmpleq_m_s<mode>"
3666   [
3667    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3668         (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3669                        (match_operand:MVE_2 2 "s_register_operand" "w")
3670                        (match_operand:HI 3 "vpr_register_operand" "Up")]
3671          VCMPLEQ_M_S))
3672   ]
3673   "TARGET_HAVE_MVE"
3674   "vpst\;vcmpt.s%#<V_sz_elem>   le, %q1, %q2"
3675   [(set_attr "type" "mve_move")
3676    (set_attr "length""8")])
3677
3678 ;;
3679 ;; [vcmpltq_m_n_s])
3680 ;;
3681 (define_insn "mve_vcmpltq_m_n_s<mode>"
3682   [
3683    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3684         (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3685                        (match_operand:<V_elem> 2 "s_register_operand" "r")
3686                        (match_operand:HI 3 "vpr_register_operand" "Up")]
3687          VCMPLTQ_M_N_S))
3688   ]
3689   "TARGET_HAVE_MVE"
3690   "vpst\;vcmpt.s%#<V_sz_elem>   lt, %q1, %2"
3691   [(set_attr "type" "mve_move")
3692    (set_attr "length""8")])
3693
3694 ;;
3695 ;; [vcmpltq_m_s])
3696 ;;
3697 (define_insn "mve_vcmpltq_m_s<mode>"
3698   [
3699    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3700         (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3701                        (match_operand:MVE_2 2 "s_register_operand" "w")
3702                        (match_operand:HI 3 "vpr_register_operand" "Up")]
3703          VCMPLTQ_M_S))
3704   ]
3705   "TARGET_HAVE_MVE"
3706   "vpst\;vcmpt.s%#<V_sz_elem>   lt, %q1, %q2"
3707   [(set_attr "type" "mve_move")
3708    (set_attr "length""8")])
3709
3710 ;;
3711 ;; [vcmpneq_m_n_u, vcmpneq_m_n_s])
3712 ;;
3713 (define_insn "mve_vcmpneq_m_n_<supf><mode>"
3714   [
3715    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3716         (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3717                        (match_operand:<V_elem> 2 "s_register_operand" "r")
3718                        (match_operand:HI 3 "vpr_register_operand" "Up")]
3719          VCMPNEQ_M_N))
3720   ]
3721   "TARGET_HAVE_MVE"
3722   "vpst\;vcmpt.i%#<V_sz_elem>   ne, %q1, %2"
3723   [(set_attr "type" "mve_move")
3724    (set_attr "length""8")])
3725
3726 ;;
3727 ;; [vcmpneq_m_s, vcmpneq_m_u])
3728 ;;
3729 (define_insn "mve_vcmpneq_m_<supf><mode>"
3730   [
3731    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3732         (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3733                        (match_operand:MVE_2 2 "s_register_operand" "w")
3734                        (match_operand:HI 3 "vpr_register_operand" "Up")]
3735          VCMPNEQ_M))
3736   ]
3737   "TARGET_HAVE_MVE"
3738   "vpst\;vcmpt.i%#<V_sz_elem>   ne, %q1, %q2"
3739   [(set_attr "type" "mve_move")
3740    (set_attr "length""8")])
3741
3742 ;;
3743 ;; [vdupq_m_n_s, vdupq_m_n_u])
3744 ;;
3745 (define_insn "mve_vdupq_m_n_<supf><mode>"
3746   [
3747    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3748         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3749                        (match_operand:<V_elem> 2 "s_register_operand" "r")
3750                        (match_operand:HI 3 "vpr_register_operand" "Up")]
3751          VDUPQ_M_N))
3752   ]
3753   "TARGET_HAVE_MVE"
3754   "vpst\;vdupt.%#<V_sz_elem>    %q0, %2"
3755   [(set_attr "type" "mve_move")
3756    (set_attr "length""8")])
3757
3758 ;;
3759 ;; [vmaxaq_m_s])
3760 ;;
3761 (define_insn "mve_vmaxaq_m_s<mode>"
3762   [
3763    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3764         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3765                        (match_operand:MVE_2 2 "s_register_operand" "w")
3766                        (match_operand:HI 3 "vpr_register_operand" "Up")]
3767          VMAXAQ_M_S))
3768   ]
3769   "TARGET_HAVE_MVE"
3770   "vpst\;vmaxat.s%#<V_sz_elem>  %q0, %q2"
3771   [(set_attr "type" "mve_move")
3772    (set_attr "length""8")])
3773
3774 ;;
3775 ;; [vmaxavq_p_s])
3776 ;;
3777 (define_insn "mve_vmaxavq_p_s<mode>"
3778   [
3779    (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
3780         (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
3781                        (match_operand:MVE_2 2 "s_register_operand" "w")
3782                        (match_operand:HI 3 "vpr_register_operand" "Up")]
3783          VMAXAVQ_P_S))
3784   ]
3785   "TARGET_HAVE_MVE"
3786   "vpst\;vmaxavt.s%#<V_sz_elem> %0, %q2"
3787   [(set_attr "type" "mve_move")
3788    (set_attr "length""8")])
3789
3790 ;;
3791 ;; [vmaxvq_p_u, vmaxvq_p_s])
3792 ;;
3793 (define_insn "mve_vmaxvq_p_<supf><mode>"
3794   [
3795    (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
3796         (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
3797                        (match_operand:MVE_2 2 "s_register_operand" "w")
3798                        (match_operand:HI 3 "vpr_register_operand" "Up")]
3799          VMAXVQ_P))
3800   ]
3801   "TARGET_HAVE_MVE"
3802   "vpst\;vmaxvt.<supf>%#<V_sz_elem>     %0, %q2"
3803   [(set_attr "type" "mve_move")
3804    (set_attr "length""8")])
3805
3806 ;;
3807 ;; [vminaq_m_s])
3808 ;;
3809 (define_insn "mve_vminaq_m_s<mode>"
3810   [
3811    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3812         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3813                        (match_operand:MVE_2 2 "s_register_operand" "w")
3814                        (match_operand:HI 3 "vpr_register_operand" "Up")]
3815          VMINAQ_M_S))
3816   ]
3817   "TARGET_HAVE_MVE"
3818   "vpst\;vminat.s%#<V_sz_elem>  %q0, %q2"
3819   [(set_attr "type" "mve_move")
3820    (set_attr "length""8")])
3821
3822 ;;
3823 ;; [vminavq_p_s])
3824 ;;
3825 (define_insn "mve_vminavq_p_s<mode>"
3826   [
3827    (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
3828         (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
3829                        (match_operand:MVE_2 2 "s_register_operand" "w")
3830                        (match_operand:HI 3 "vpr_register_operand" "Up")]
3831          VMINAVQ_P_S))
3832   ]
3833   "TARGET_HAVE_MVE"
3834   "vpst\;vminavt.s%#<V_sz_elem> %0, %q2"
3835   [(set_attr "type" "mve_move")
3836    (set_attr "length""8")])
3837
3838 ;;
3839 ;; [vminvq_p_s, vminvq_p_u])
3840 ;;
3841 (define_insn "mve_vminvq_p_<supf><mode>"
3842   [
3843    (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
3844         (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
3845                        (match_operand:MVE_2 2 "s_register_operand" "w")
3846                        (match_operand:HI 3 "vpr_register_operand" "Up")]
3847          VMINVQ_P))
3848   ]
3849   "TARGET_HAVE_MVE"
3850   "vpst\;vminvt.<supf>%#<V_sz_elem>\t%0, %q2"
3851   [(set_attr "type" "mve_move")
3852    (set_attr "length""8")])
3853
3854 ;;
3855 ;; [vmladavaq_u, vmladavaq_s])
3856 ;;
3857 (define_insn "mve_vmladavaq_<supf><mode>"
3858   [
3859    (set (match_operand:SI 0 "s_register_operand" "=e")
3860         (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
3861                        (match_operand:MVE_2 2 "s_register_operand" "w")
3862                        (match_operand:MVE_2 3 "s_register_operand" "w")]
3863          VMLADAVAQ))
3864   ]
3865   "TARGET_HAVE_MVE"
3866   "vmladava.<supf>%#<V_sz_elem> %0, %q2, %q3"
3867   [(set_attr "type" "mve_move")
3868 ])
3869
3870 ;;
3871 ;; [vmladavq_p_u, vmladavq_p_s])
3872 ;;
3873 (define_insn "mve_vmladavq_p_<supf><mode>"
3874   [
3875    (set (match_operand:SI 0 "s_register_operand" "=e")
3876         (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
3877                        (match_operand:MVE_2 2 "s_register_operand" "w")
3878                        (match_operand:HI 3 "vpr_register_operand" "Up")]
3879          VMLADAVQ_P))
3880   ]
3881   "TARGET_HAVE_MVE"
3882   "vpst\;vmladavt.<supf>%#<V_sz_elem>\t%0, %q1, %q2"
3883   [(set_attr "type" "mve_move")
3884    (set_attr "length""8")])
3885
3886 ;;
3887 ;; [vmladavxq_p_s])
3888 ;;
3889 (define_insn "mve_vmladavxq_p_s<mode>"
3890   [
3891    (set (match_operand:SI 0 "s_register_operand" "=e")
3892         (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
3893                        (match_operand:MVE_2 2 "s_register_operand" "w")
3894                        (match_operand:HI 3 "vpr_register_operand" "Up")]
3895          VMLADAVXQ_P_S))
3896   ]
3897   "TARGET_HAVE_MVE"
3898   "vpst\;vmladavxt.s%#<V_sz_elem>\t%0, %q1, %q2"
3899   [(set_attr "type" "mve_move")
3900    (set_attr "length""8")])
3901
3902 ;;
3903 ;; [vmlaq_n_u, vmlaq_n_s])
3904 ;;
3905 (define_insn "mve_vmlaq_n_<supf><mode>"
3906   [
3907    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3908         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3909                        (match_operand:MVE_2 2 "s_register_operand" "w")
3910                        (match_operand:<V_elem> 3 "s_register_operand" "r")]
3911          VMLAQ_N))
3912   ]
3913   "TARGET_HAVE_MVE"
3914   "vmla.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
3915   [(set_attr "type" "mve_move")
3916 ])
3917
3918 ;;
3919 ;; [vmlasq_n_u, vmlasq_n_s])
3920 ;;
3921 (define_insn "mve_vmlasq_n_<supf><mode>"
3922   [
3923    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3924         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3925                        (match_operand:MVE_2 2 "s_register_operand" "w")
3926                        (match_operand:<V_elem> 3 "s_register_operand" "r")]
3927          VMLASQ_N))
3928   ]
3929   "TARGET_HAVE_MVE"
3930   "vmlas.<supf>%#<V_sz_elem>    %q0, %q2, %3"
3931   [(set_attr "type" "mve_move")
3932 ])
3933
3934 ;;
3935 ;; [vmlsdavq_p_s])
3936 ;;
3937 (define_insn "mve_vmlsdavq_p_s<mode>"
3938   [
3939    (set (match_operand:SI 0 "s_register_operand" "=e")
3940         (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
3941                        (match_operand:MVE_2 2 "s_register_operand" "w")
3942                        (match_operand:HI 3 "vpr_register_operand" "Up")]
3943          VMLSDAVQ_P_S))
3944   ]
3945   "TARGET_HAVE_MVE"
3946   "vpst\;vmlsdavt.s%#<V_sz_elem>        %0, %q1, %q2"
3947   [(set_attr "type" "mve_move")
3948    (set_attr "length""8")])
3949
3950 ;;
3951 ;; [vmlsdavxq_p_s])
3952 ;;
3953 (define_insn "mve_vmlsdavxq_p_s<mode>"
3954   [
3955    (set (match_operand:SI 0 "s_register_operand" "=e")
3956         (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
3957                        (match_operand:MVE_2 2 "s_register_operand" "w")
3958                        (match_operand:HI 3 "vpr_register_operand" "Up")]
3959          VMLSDAVXQ_P_S))
3960   ]
3961   "TARGET_HAVE_MVE"
3962   "vpst\;vmlsdavxt.s%#<V_sz_elem>       %0, %q1, %q2"
3963   [(set_attr "type" "mve_move")
3964    (set_attr "length""8")])
3965
3966 ;;
3967 ;; [vmvnq_m_s, vmvnq_m_u])
3968 ;;
3969 (define_insn "mve_vmvnq_m_<supf><mode>"
3970   [
3971    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3972         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3973                        (match_operand:MVE_2 2 "s_register_operand" "w")
3974                        (match_operand:HI 3 "vpr_register_operand" "Up")]
3975          VMVNQ_M))
3976   ]
3977   "TARGET_HAVE_MVE"
3978   "vpst\;vmvnt %q0, %q2"
3979   [(set_attr "type" "mve_move")
3980    (set_attr "length""8")])
3981
3982 ;;
3983 ;; [vnegq_m_s])
3984 ;;
3985 (define_insn "mve_vnegq_m_s<mode>"
3986   [
3987    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3988         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3989                        (match_operand:MVE_2 2 "s_register_operand" "w")
3990                        (match_operand:HI 3 "vpr_register_operand" "Up")]
3991          VNEGQ_M_S))
3992   ]
3993   "TARGET_HAVE_MVE"
3994   "vpst\;vnegt.s%#<V_sz_elem>\t%q0, %q2"
3995   [(set_attr "type" "mve_move")
3996    (set_attr "length""8")])
3997
3998 ;;
3999 ;; [vpselq_u, vpselq_s])
4000 ;;
4001 (define_insn "mve_vpselq_<supf><mode>"
4002   [
4003    (set (match_operand:MVE_1 0 "s_register_operand" "=w")
4004         (unspec:MVE_1 [(match_operand:MVE_1 1 "s_register_operand" "w")
4005                        (match_operand:MVE_1 2 "s_register_operand" "w")
4006                        (match_operand:HI 3 "vpr_register_operand" "Up")]
4007          VPSELQ))
4008   ]
4009   "TARGET_HAVE_MVE"
4010   "vpsel %q0, %q1, %q2"
4011   [(set_attr "type" "mve_move")
4012 ])
4013
4014 ;;
4015 ;; [vqabsq_m_s])
4016 ;;
4017 (define_insn "mve_vqabsq_m_s<mode>"
4018   [
4019    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4020         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4021                        (match_operand:MVE_2 2 "s_register_operand" "w")
4022                        (match_operand:HI 3 "vpr_register_operand" "Up")]
4023          VQABSQ_M_S))
4024   ]
4025   "TARGET_HAVE_MVE"
4026   "vpst\;vqabst.s%#<V_sz_elem>\t%q0, %q2"
4027   [(set_attr "type" "mve_move")
4028    (set_attr "length""8")])
4029
4030 ;;
4031 ;; [vqdmlahq_n_s, vqdmlahq_n_u])
4032 ;;
4033 (define_insn "mve_vqdmlahq_n_<supf><mode>"
4034   [
4035    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4036         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4037                        (match_operand:MVE_2 2 "s_register_operand" "w")
4038                        (match_operand:<V_elem> 3 "s_register_operand" "r")]
4039          VQDMLAHQ_N))
4040   ]
4041   "TARGET_HAVE_MVE"
4042   "vqdmlah.s%#<V_sz_elem>\t%q0, %q2, %3"
4043   [(set_attr "type" "mve_move")
4044 ])
4045
4046 ;;
4047 ;; [vqnegq_m_s])
4048 ;;
4049 (define_insn "mve_vqnegq_m_s<mode>"
4050   [
4051    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4052         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4053                        (match_operand:MVE_2 2 "s_register_operand" "w")
4054                        (match_operand:HI 3 "vpr_register_operand" "Up")]
4055          VQNEGQ_M_S))
4056   ]
4057   "TARGET_HAVE_MVE"
4058   "vpst\;vqnegt.s%#<V_sz_elem>  %q0, %q2"
4059   [(set_attr "type" "mve_move")
4060    (set_attr "length""8")])
4061
4062 ;;
4063 ;; [vqrdmladhq_s])
4064 ;;
4065 (define_insn "mve_vqrdmladhq_s<mode>"
4066   [
4067    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4068         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4069                        (match_operand:MVE_2 2 "s_register_operand" "w")
4070                        (match_operand:MVE_2 3 "s_register_operand" "w")]
4071          VQRDMLADHQ_S))
4072   ]
4073   "TARGET_HAVE_MVE"
4074   "vqrdmladh.s%#<V_sz_elem>\t%q0, %q2, %q3"
4075   [(set_attr "type" "mve_move")
4076 ])
4077
4078 ;;
4079 ;; [vqrdmladhxq_s])
4080 ;;
4081 (define_insn "mve_vqrdmladhxq_s<mode>"
4082   [
4083    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4084         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4085                        (match_operand:MVE_2 2 "s_register_operand" "w")
4086                        (match_operand:MVE_2 3 "s_register_operand" "w")]
4087          VQRDMLADHXQ_S))
4088   ]
4089   "TARGET_HAVE_MVE"
4090   "vqrdmladhx.s%#<V_sz_elem>\t%q0, %q2, %q3"
4091   [(set_attr "type" "mve_move")
4092 ])
4093
4094 ;;
4095 ;; [vqrdmlahq_n_s, vqrdmlahq_n_u])
4096 ;;
4097 (define_insn "mve_vqrdmlahq_n_<supf><mode>"
4098   [
4099    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4100         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4101                        (match_operand:MVE_2 2 "s_register_operand" "w")
4102                        (match_operand:<V_elem> 3 "s_register_operand" "r")]
4103          VQRDMLAHQ_N))
4104   ]
4105   "TARGET_HAVE_MVE"
4106   "vqrdmlah.s%#<V_sz_elem>\t%q0, %q2, %3"
4107   [(set_attr "type" "mve_move")
4108 ])
4109
4110 ;;
4111 ;; [vqrdmlashq_n_s, vqrdmlashq_n_u])
4112 ;;
4113 (define_insn "mve_vqrdmlashq_n_<supf><mode>"
4114   [
4115    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4116         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4117                        (match_operand:MVE_2 2 "s_register_operand" "w")
4118                        (match_operand:<V_elem> 3 "s_register_operand" "r")]
4119          VQRDMLASHQ_N))
4120   ]
4121   "TARGET_HAVE_MVE"
4122   "vqrdmlash.s%#<V_sz_elem>\t%q0, %q2, %3"
4123   [(set_attr "type" "mve_move")
4124 ])
4125
4126 ;;
4127 ;; [vqrdmlsdhq_s])
4128 ;;
4129 (define_insn "mve_vqrdmlsdhq_s<mode>"
4130   [
4131    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4132         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4133                        (match_operand:MVE_2 2 "s_register_operand" "w")
4134                        (match_operand:MVE_2 3 "s_register_operand" "w")]
4135          VQRDMLSDHQ_S))
4136   ]
4137   "TARGET_HAVE_MVE"
4138   "vqrdmlsdh.s%#<V_sz_elem>\t%q0, %q2, %q3"
4139   [(set_attr "type" "mve_move")
4140 ])
4141
4142 ;;
4143 ;; [vqrdmlsdhxq_s])
4144 ;;
4145 (define_insn "mve_vqrdmlsdhxq_s<mode>"
4146   [
4147    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4148         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4149                        (match_operand:MVE_2 2 "s_register_operand" "w")
4150                        (match_operand:MVE_2 3 "s_register_operand" "w")]
4151          VQRDMLSDHXQ_S))
4152   ]
4153   "TARGET_HAVE_MVE"
4154   "vqrdmlsdhx.s%#<V_sz_elem>\t%q0, %q2, %q3"
4155   [(set_attr "type" "mve_move")
4156 ])
4157
4158 ;;
4159 ;; [vqrshlq_m_n_s, vqrshlq_m_n_u])
4160 ;;
4161 (define_insn "mve_vqrshlq_m_n_<supf><mode>"
4162   [
4163    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4164         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4165                        (match_operand:SI 2 "s_register_operand" "r")
4166                        (match_operand:HI 3 "vpr_register_operand" "Up")]
4167          VQRSHLQ_M_N))
4168   ]
4169   "TARGET_HAVE_MVE"
4170   "vpst\;vqrshlt.<supf>%#<V_sz_elem>    %q0, %2"
4171   [(set_attr "type" "mve_move")
4172    (set_attr "length""8")])
4173
4174 ;;
4175 ;; [vqshlq_m_r_u, vqshlq_m_r_s])
4176 ;;
4177 (define_insn "mve_vqshlq_m_r_<supf><mode>"
4178   [
4179    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4180         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4181                        (match_operand:SI 2 "s_register_operand" "r")
4182                        (match_operand:HI 3 "vpr_register_operand" "Up")]
4183          VQSHLQ_M_R))
4184   ]
4185   "TARGET_HAVE_MVE"
4186   "vpst\;vqshlt.<supf>%#<V_sz_elem>\t%q0, %2"
4187   [(set_attr "type" "mve_move")
4188    (set_attr "length""8")])
4189
4190 ;;
4191 ;; [vrev64q_m_u, vrev64q_m_s])
4192 ;;
4193 (define_insn "mve_vrev64q_m_<supf><mode>"
4194   [
4195    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4196         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4197                        (match_operand:MVE_2 2 "s_register_operand" "w")
4198                        (match_operand:HI 3 "vpr_register_operand" "Up")]
4199          VREV64Q_M))
4200   ]
4201   "TARGET_HAVE_MVE"
4202   "vpst\;vrev64t.%#<V_sz_elem>\t%q0, %q2"
4203   [(set_attr "type" "mve_move")
4204    (set_attr "length""8")])
4205
4206 ;;
4207 ;; [vrshlq_m_n_s, vrshlq_m_n_u])
4208 ;;
4209 (define_insn "mve_vrshlq_m_n_<supf><mode>"
4210   [
4211    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4212         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4213                        (match_operand:SI 2 "s_register_operand" "r")
4214                        (match_operand:HI 3 "vpr_register_operand" "Up")]
4215          VRSHLQ_M_N))
4216   ]
4217   "TARGET_HAVE_MVE"
4218   "vpst\;vrshlt.<supf>%#<V_sz_elem>\t%q0, %2"
4219   [(set_attr "type" "mve_move")
4220    (set_attr "length""8")])
4221
4222 ;;
4223 ;; [vshlq_m_r_u, vshlq_m_r_s])
4224 ;;
4225 (define_insn "mve_vshlq_m_r_<supf><mode>"
4226   [
4227    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4228         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4229                        (match_operand:SI 2 "s_register_operand" "r")
4230                        (match_operand:HI 3 "vpr_register_operand" "Up")]
4231          VSHLQ_M_R))
4232   ]
4233   "TARGET_HAVE_MVE"
4234   "vpst\;vshlt.<supf>%#<V_sz_elem>\t%q0, %2"
4235   [(set_attr "type" "mve_move")
4236    (set_attr "length""8")])
4237
4238 ;;
4239 ;; [vsliq_n_u, vsliq_n_s])
4240 ;;
4241 (define_insn "mve_vsliq_n_<supf><mode>"
4242   [
4243    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4244         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4245                        (match_operand:MVE_2 2 "s_register_operand" "w")
4246                        (match_operand:SI 3 "<MVE_pred>" "<MVE_constraint>")]
4247          VSLIQ_N))
4248   ]
4249   "TARGET_HAVE_MVE"
4250   "vsli.%#<V_sz_elem>\t%q0, %q2, %3"
4251   [(set_attr "type" "mve_move")
4252 ])
4253
4254 ;;
4255 ;; [vsriq_n_u, vsriq_n_s])
4256 ;;
4257 (define_insn "mve_vsriq_n_<supf><mode>"
4258   [
4259    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4260         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4261                        (match_operand:MVE_2 2 "s_register_operand" "w")
4262                        (match_operand:SI 3 "mve_imm_selective_upto_8" "Rg")]
4263          VSRIQ_N))
4264   ]
4265   "TARGET_HAVE_MVE"
4266   "vsri.%#<V_sz_elem>\t%q0, %q2, %3"
4267   [(set_attr "type" "mve_move")
4268 ])
4269
4270 ;;
4271 ;; [vqdmlsdhxq_s])
4272 ;;
4273 (define_insn "mve_vqdmlsdhxq_s<mode>"
4274   [
4275    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4276         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4277                        (match_operand:MVE_2 2 "s_register_operand" "w")
4278                        (match_operand:MVE_2 3 "s_register_operand" "w")]
4279          VQDMLSDHXQ_S))
4280   ]
4281   "TARGET_HAVE_MVE"
4282   "vqdmlsdhx.s%#<V_sz_elem>\t%q0, %q2, %q3"
4283   [(set_attr "type" "mve_move")
4284 ])
4285
4286 ;;
4287 ;; [vqdmlsdhq_s])
4288 ;;
4289 (define_insn "mve_vqdmlsdhq_s<mode>"
4290   [
4291    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4292         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4293                        (match_operand:MVE_2 2 "s_register_operand" "w")
4294                        (match_operand:MVE_2 3 "s_register_operand" "w")]
4295          VQDMLSDHQ_S))
4296   ]
4297   "TARGET_HAVE_MVE"
4298   "vqdmlsdh.s%#<V_sz_elem>\t%q0, %q2, %q3"
4299   [(set_attr "type" "mve_move")
4300 ])
4301
4302 ;;
4303 ;; [vqdmladhxq_s])
4304 ;;
4305 (define_insn "mve_vqdmladhxq_s<mode>"
4306   [
4307    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4308         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4309                        (match_operand:MVE_2 2 "s_register_operand" "w")
4310                        (match_operand:MVE_2 3 "s_register_operand" "w")]
4311          VQDMLADHXQ_S))
4312   ]
4313   "TARGET_HAVE_MVE"
4314   "vqdmladhx.s%#<V_sz_elem>\t%q0, %q2, %q3"
4315   [(set_attr "type" "mve_move")
4316 ])
4317
4318 ;;
4319 ;; [vqdmladhq_s])
4320 ;;
4321 (define_insn "mve_vqdmladhq_s<mode>"
4322   [
4323    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4324         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4325                        (match_operand:MVE_2 2 "s_register_operand" "w")
4326                        (match_operand:MVE_2 3 "s_register_operand" "w")]
4327          VQDMLADHQ_S))
4328   ]
4329   "TARGET_HAVE_MVE"
4330   "vqdmladh.s%#<V_sz_elem>\t%q0, %q2, %q3"
4331   [(set_attr "type" "mve_move")
4332 ])
4333
4334 ;;
4335 ;; [vmlsdavaxq_s])
4336 ;;
4337 (define_insn "mve_vmlsdavaxq_s<mode>"
4338   [
4339    (set (match_operand:SI 0 "s_register_operand" "=e")
4340         (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
4341                     (match_operand:MVE_2 2 "s_register_operand" "w")
4342                     (match_operand:MVE_2 3 "s_register_operand" "w")]
4343          VMLSDAVAXQ_S))
4344   ]
4345   "TARGET_HAVE_MVE"
4346   "vmlsdavax.s%#<V_sz_elem>\t%0, %q2, %q3"
4347   [(set_attr "type" "mve_move")
4348 ])
4349
4350 ;;
4351 ;; [vmlsdavaq_s])
4352 ;;
4353 (define_insn "mve_vmlsdavaq_s<mode>"
4354   [
4355    (set (match_operand:SI 0 "s_register_operand" "=e")
4356         (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
4357                     (match_operand:MVE_2 2 "s_register_operand" "w")
4358                     (match_operand:MVE_2 3 "s_register_operand" "w")]
4359          VMLSDAVAQ_S))
4360   ]
4361   "TARGET_HAVE_MVE"
4362   "vmlsdava.s%#<V_sz_elem>\t%0, %q2, %q3"
4363   [(set_attr "type" "mve_move")
4364 ])
4365
4366 ;;
4367 ;; [vmladavaxq_s])
4368 ;;
4369 (define_insn "mve_vmladavaxq_s<mode>"
4370   [
4371    (set (match_operand:SI 0 "s_register_operand" "=e")
4372         (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
4373                     (match_operand:MVE_2 2 "s_register_operand" "w")
4374                     (match_operand:MVE_2 3 "s_register_operand" "w")]
4375          VMLADAVAXQ_S))
4376   ]
4377   "TARGET_HAVE_MVE"
4378   "vmladavax.s%#<V_sz_elem>\t%0, %q2, %q3"
4379   [(set_attr "type" "mve_move")
4380 ])
4381 ;;
4382 ;; [vabsq_m_f])
4383 ;;
4384 (define_insn "mve_vabsq_m_f<mode>"
4385   [
4386    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4387         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4388                        (match_operand:MVE_0 2 "s_register_operand" "w")
4389                        (match_operand:HI 3 "vpr_register_operand" "Up")]
4390          VABSQ_M_F))
4391   ]
4392   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4393   "vpst\;vabst.f%#<V_sz_elem>   %q0, %q2"
4394   [(set_attr "type" "mve_move")
4395    (set_attr "length""8")])
4396
4397 ;;
4398 ;; [vaddlvaq_p_s vaddlvaq_p_u])
4399 ;;
4400 (define_insn "mve_vaddlvaq_p_<supf>v4si"
4401   [
4402    (set (match_operand:DI 0 "s_register_operand" "=r")
4403         (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
4404                        (match_operand:V4SI 2 "s_register_operand" "w")
4405                        (match_operand:HI 3 "vpr_register_operand" "Up")]
4406          VADDLVAQ_P))
4407   ]
4408   "TARGET_HAVE_MVE"
4409   "vpst\;vaddlvat.<supf>32 %Q0, %R0, %q2"
4410   [(set_attr "type" "mve_move")
4411    (set_attr "length""8")])
4412 ;;
4413 ;; [vcmlaq_f])
4414 ;;
4415 (define_insn "mve_vcmlaq_f<mode>"
4416   [
4417    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4418         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4419                        (match_operand:MVE_0 2 "s_register_operand" "w")
4420                        (match_operand:MVE_0 3 "s_register_operand" "w")]
4421          VCMLAQ_F))
4422   ]
4423   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4424   "vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #0"
4425   [(set_attr "type" "mve_move")
4426 ])
4427
4428 ;;
4429 ;; [vcmlaq_rot180_f])
4430 ;;
4431 (define_insn "mve_vcmlaq_rot180_f<mode>"
4432   [
4433    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4434         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4435                        (match_operand:MVE_0 2 "s_register_operand" "w")
4436                        (match_operand:MVE_0 3 "s_register_operand" "w")]
4437          VCMLAQ_ROT180_F))
4438   ]
4439   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4440   "vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #180"
4441   [(set_attr "type" "mve_move")
4442 ])
4443
4444 ;;
4445 ;; [vcmlaq_rot270_f])
4446 ;;
4447 (define_insn "mve_vcmlaq_rot270_f<mode>"
4448   [
4449    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4450         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4451                        (match_operand:MVE_0 2 "s_register_operand" "w")
4452                        (match_operand:MVE_0 3 "s_register_operand" "w")]
4453          VCMLAQ_ROT270_F))
4454   ]
4455   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4456   "vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #270"
4457   [(set_attr "type" "mve_move")
4458 ])
4459
4460 ;;
4461 ;; [vcmlaq_rot90_f])
4462 ;;
4463 (define_insn "mve_vcmlaq_rot90_f<mode>"
4464   [
4465    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4466         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4467                        (match_operand:MVE_0 2 "s_register_operand" "w")
4468                        (match_operand:MVE_0 3 "s_register_operand" "w")]
4469          VCMLAQ_ROT90_F))
4470   ]
4471   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4472   "vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #90"
4473   [(set_attr "type" "mve_move")
4474 ])
4475
4476 ;;
4477 ;; [vcmpeqq_m_n_f])
4478 ;;
4479 (define_insn "mve_vcmpeqq_m_n_f<mode>"
4480   [
4481    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4482         (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4483                        (match_operand:<V_elem> 2 "s_register_operand" "r")
4484                        (match_operand:HI 3 "vpr_register_operand" "Up")]
4485          VCMPEQQ_M_N_F))
4486   ]
4487   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4488   "vpst\;vcmpt.f%#<V_sz_elem>   eq, %q1, %2"
4489   [(set_attr "type" "mve_move")
4490    (set_attr "length""8")])
4491
4492 ;;
4493 ;; [vcmpgeq_m_f])
4494 ;;
4495 (define_insn "mve_vcmpgeq_m_f<mode>"
4496   [
4497    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4498         (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4499                        (match_operand:MVE_0 2 "s_register_operand" "w")
4500                        (match_operand:HI 3 "vpr_register_operand" "Up")]
4501          VCMPGEQ_M_F))
4502   ]
4503   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4504   "vpst\;vcmpt.f%#<V_sz_elem>   ge, %q1, %q2"
4505   [(set_attr "type" "mve_move")
4506    (set_attr "length""8")])
4507
4508 ;;
4509 ;; [vcmpgeq_m_n_f])
4510 ;;
4511 (define_insn "mve_vcmpgeq_m_n_f<mode>"
4512   [
4513    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4514         (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4515                        (match_operand:<V_elem> 2 "s_register_operand" "r")
4516                        (match_operand:HI 3 "vpr_register_operand" "Up")]
4517          VCMPGEQ_M_N_F))
4518   ]
4519   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4520   "vpst\;vcmpt.f%#<V_sz_elem>   ge, %q1, %2"
4521   [(set_attr "type" "mve_move")
4522    (set_attr "length""8")])
4523
4524 ;;
4525 ;; [vcmpgtq_m_f])
4526 ;;
4527 (define_insn "mve_vcmpgtq_m_f<mode>"
4528   [
4529    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4530         (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4531                        (match_operand:MVE_0 2 "s_register_operand" "w")
4532                        (match_operand:HI 3 "vpr_register_operand" "Up")]
4533          VCMPGTQ_M_F))
4534   ]
4535   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4536   "vpst\;vcmpt.f%#<V_sz_elem>   gt, %q1, %q2"
4537   [(set_attr "type" "mve_move")
4538    (set_attr "length""8")])
4539
4540 ;;
4541 ;; [vcmpgtq_m_n_f])
4542 ;;
4543 (define_insn "mve_vcmpgtq_m_n_f<mode>"
4544   [
4545    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4546         (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4547                        (match_operand:<V_elem> 2 "s_register_operand" "r")
4548                        (match_operand:HI 3 "vpr_register_operand" "Up")]
4549          VCMPGTQ_M_N_F))
4550   ]
4551   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4552   "vpst\;vcmpt.f%#<V_sz_elem>   gt, %q1, %2"
4553   [(set_attr "type" "mve_move")
4554    (set_attr "length""8")])
4555
4556 ;;
4557 ;; [vcmpleq_m_f])
4558 ;;
4559 (define_insn "mve_vcmpleq_m_f<mode>"
4560   [
4561    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4562         (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4563                        (match_operand:MVE_0 2 "s_register_operand" "w")
4564                        (match_operand:HI 3 "vpr_register_operand" "Up")]
4565          VCMPLEQ_M_F))
4566   ]
4567   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4568   "vpst\;vcmpt.f%#<V_sz_elem>   le, %q1, %q2"
4569   [(set_attr "type" "mve_move")
4570    (set_attr "length""8")])
4571
4572 ;;
4573 ;; [vcmpleq_m_n_f])
4574 ;;
4575 (define_insn "mve_vcmpleq_m_n_f<mode>"
4576   [
4577    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4578         (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4579                        (match_operand:<V_elem> 2 "s_register_operand" "r")
4580                        (match_operand:HI 3 "vpr_register_operand" "Up")]
4581          VCMPLEQ_M_N_F))
4582   ]
4583   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4584   "vpst\;vcmpt.f%#<V_sz_elem>   le, %q1, %2"
4585   [(set_attr "type" "mve_move")
4586    (set_attr "length""8")])
4587
4588 ;;
4589 ;; [vcmpltq_m_f])
4590 ;;
4591 (define_insn "mve_vcmpltq_m_f<mode>"
4592   [
4593    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4594         (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4595                        (match_operand:MVE_0 2 "s_register_operand" "w")
4596                        (match_operand:HI 3 "vpr_register_operand" "Up")]
4597          VCMPLTQ_M_F))
4598   ]
4599   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4600   "vpst\;vcmpt.f%#<V_sz_elem>   lt, %q1, %q2"
4601   [(set_attr "type" "mve_move")
4602    (set_attr "length""8")])
4603
4604 ;;
4605 ;; [vcmpltq_m_n_f])
4606 ;;
4607 (define_insn "mve_vcmpltq_m_n_f<mode>"
4608   [
4609    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4610         (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4611                        (match_operand:<V_elem> 2 "s_register_operand" "r")
4612                        (match_operand:HI 3 "vpr_register_operand" "Up")]
4613          VCMPLTQ_M_N_F))
4614   ]
4615   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4616   "vpst\;vcmpt.f%#<V_sz_elem>   lt, %q1, %2"
4617   [(set_attr "type" "mve_move")
4618    (set_attr "length""8")])
4619
4620 ;;
4621 ;; [vcmpneq_m_f])
4622 ;;
4623 (define_insn "mve_vcmpneq_m_f<mode>"
4624   [
4625    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4626         (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4627                        (match_operand:MVE_0 2 "s_register_operand" "w")
4628                        (match_operand:HI 3 "vpr_register_operand" "Up")]
4629          VCMPNEQ_M_F))
4630   ]
4631   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4632   "vpst\;vcmpt.f%#<V_sz_elem>   ne, %q1, %q2"
4633   [(set_attr "type" "mve_move")
4634    (set_attr "length""8")])
4635
4636 ;;
4637 ;; [vcmpneq_m_n_f])
4638 ;;
4639 (define_insn "mve_vcmpneq_m_n_f<mode>"
4640   [
4641    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4642         (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4643                        (match_operand:<V_elem> 2 "s_register_operand" "r")
4644                        (match_operand:HI 3 "vpr_register_operand" "Up")]
4645          VCMPNEQ_M_N_F))
4646   ]
4647   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4648   "vpst\;vcmpt.f%#<V_sz_elem>   ne, %q1, %2"
4649   [(set_attr "type" "mve_move")
4650    (set_attr "length""8")])
4651
4652 ;;
4653 ;; [vcvtbq_m_f16_f32])
4654 ;;
4655 (define_insn "mve_vcvtbq_m_f16_f32v8hf"
4656   [
4657    (set (match_operand:V8HF 0 "s_register_operand" "=w")
4658         (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
4659                        (match_operand:V4SF 2 "s_register_operand" "w")
4660                        (match_operand:HI 3 "vpr_register_operand" "Up")]
4661          VCVTBQ_M_F16_F32))
4662   ]
4663   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4664   "vpst\;vcvtbt.f16.f32 %q0, %q2"
4665   [(set_attr "type" "mve_move")
4666    (set_attr "length""8")])
4667
4668 ;;
4669 ;; [vcvtbq_m_f32_f16])
4670 ;;
4671 (define_insn "mve_vcvtbq_m_f32_f16v4sf"
4672   [
4673    (set (match_operand:V4SF 0 "s_register_operand" "=w")
4674         (unspec:V4SF [(match_operand:V4SF 1 "s_register_operand" "0")
4675                        (match_operand:V8HF 2 "s_register_operand" "w")
4676                        (match_operand:HI 3 "vpr_register_operand" "Up")]
4677          VCVTBQ_M_F32_F16))
4678   ]
4679   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4680   "vpst\;vcvtbt.f32.f16 %q0, %q2"
4681   [(set_attr "type" "mve_move")
4682    (set_attr "length""8")])
4683
4684 ;;
4685 ;; [vcvttq_m_f16_f32])
4686 ;;
4687 (define_insn "mve_vcvttq_m_f16_f32v8hf"
4688   [
4689    (set (match_operand:V8HF 0 "s_register_operand" "=w")
4690         (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
4691                        (match_operand:V4SF 2 "s_register_operand" "w")
4692                        (match_operand:HI 3 "vpr_register_operand" "Up")]
4693          VCVTTQ_M_F16_F32))
4694   ]
4695   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4696   "vpst\;vcvttt.f16.f32 %q0, %q2"
4697   [(set_attr "type" "mve_move")
4698    (set_attr "length""8")])
4699
4700 ;;
4701 ;; [vcvttq_m_f32_f16])
4702 ;;
4703 (define_insn "mve_vcvttq_m_f32_f16v4sf"
4704   [
4705    (set (match_operand:V4SF 0 "s_register_operand" "=w")
4706         (unspec:V4SF [(match_operand:V4SF 1 "s_register_operand" "0")
4707                        (match_operand:V8HF 2 "s_register_operand" "w")
4708                        (match_operand:HI 3 "vpr_register_operand" "Up")]
4709          VCVTTQ_M_F32_F16))
4710   ]
4711   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4712   "vpst\;vcvttt.f32.f16 %q0, %q2"
4713   [(set_attr "type" "mve_move")
4714    (set_attr "length""8")])
4715
4716 ;;
4717 ;; [vdupq_m_n_f])
4718 ;;
4719 (define_insn "mve_vdupq_m_n_f<mode>"
4720   [
4721    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4722         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4723                        (match_operand:<V_elem> 2 "s_register_operand" "r")
4724                        (match_operand:HI 3 "vpr_register_operand" "Up")]
4725          VDUPQ_M_N_F))
4726   ]
4727   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4728   "vpst\;vdupt.%#<V_sz_elem>    %q0, %2"
4729   [(set_attr "type" "mve_move")
4730    (set_attr "length""8")])
4731
4732 ;;
4733 ;; [vfmaq_f])
4734 ;;
4735 (define_insn "mve_vfmaq_f<mode>"
4736   [
4737    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4738         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4739                        (match_operand:MVE_0 2 "s_register_operand" "w")
4740                        (match_operand:MVE_0 3 "s_register_operand" "w")]
4741          VFMAQ_F))
4742   ]
4743   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4744   "vfma.f%#<V_sz_elem>  %q0, %q2, %q3"
4745   [(set_attr "type" "mve_move")
4746 ])
4747
4748 ;;
4749 ;; [vfmaq_n_f])
4750 ;;
4751 (define_insn "mve_vfmaq_n_f<mode>"
4752   [
4753    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4754         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4755                        (match_operand:MVE_0 2 "s_register_operand" "w")
4756                        (match_operand:<V_elem> 3 "s_register_operand" "r")]
4757          VFMAQ_N_F))
4758   ]
4759   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4760   "vfma.f%#<V_sz_elem>  %q0, %q2, %3"
4761   [(set_attr "type" "mve_move")
4762 ])
4763
4764 ;;
4765 ;; [vfmasq_n_f])
4766 ;;
4767 (define_insn "mve_vfmasq_n_f<mode>"
4768   [
4769    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4770         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4771                        (match_operand:MVE_0 2 "s_register_operand" "w")
4772                        (match_operand:<V_elem> 3 "s_register_operand" "r")]
4773          VFMASQ_N_F))
4774   ]
4775   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4776   "vfmas.f%#<V_sz_elem> %q0, %q2, %3"
4777   [(set_attr "type" "mve_move")
4778 ])
4779 ;;
4780 ;; [vfmsq_f])
4781 ;;
4782 (define_insn "mve_vfmsq_f<mode>"
4783   [
4784    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4785         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4786                        (match_operand:MVE_0 2 "s_register_operand" "w")
4787                        (match_operand:MVE_0 3 "s_register_operand" "w")]
4788          VFMSQ_F))
4789   ]
4790   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4791   "vfms.f%#<V_sz_elem>  %q0, %q2, %q3"
4792   [(set_attr "type" "mve_move")
4793 ])
4794
4795 ;;
4796 ;; [vmaxnmaq_m_f])
4797 ;;
4798 (define_insn "mve_vmaxnmaq_m_f<mode>"
4799   [
4800    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4801         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4802                        (match_operand:MVE_0 2 "s_register_operand" "w")
4803                        (match_operand:HI 3 "vpr_register_operand" "Up")]
4804          VMAXNMAQ_M_F))
4805   ]
4806   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4807   "vpst\;vmaxnmat.f%#<V_sz_elem>        %q0, %q2"
4808   [(set_attr "type" "mve_move")
4809    (set_attr "length""8")])
4810 ;;
4811 ;; [vmaxnmavq_p_f])
4812 ;;
4813 (define_insn "mve_vmaxnmavq_p_f<mode>"
4814   [
4815    (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
4816         (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
4817                        (match_operand:MVE_0 2 "s_register_operand" "w")
4818                        (match_operand:HI 3 "vpr_register_operand" "Up")]
4819          VMAXNMAVQ_P_F))
4820   ]
4821   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4822   "vpst\;vmaxnmavt.f%#<V_sz_elem>       %0, %q2"
4823   [(set_attr "type" "mve_move")
4824    (set_attr "length""8")])
4825
4826 ;;
4827 ;; [vmaxnmvq_p_f])
4828 ;;
4829 (define_insn "mve_vmaxnmvq_p_f<mode>"
4830   [
4831    (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
4832         (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
4833                        (match_operand:MVE_0 2 "s_register_operand" "w")
4834                        (match_operand:HI 3 "vpr_register_operand" "Up")]
4835          VMAXNMVQ_P_F))
4836   ]
4837   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4838   "vpst\;vmaxnmvt.f%#<V_sz_elem>        %0, %q2"
4839   [(set_attr "type" "mve_move")
4840    (set_attr "length""8")])
4841 ;;
4842 ;; [vminnmaq_m_f])
4843 ;;
4844 (define_insn "mve_vminnmaq_m_f<mode>"
4845   [
4846    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4847         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4848                        (match_operand:MVE_0 2 "s_register_operand" "w")
4849                        (match_operand:HI 3 "vpr_register_operand" "Up")]
4850          VMINNMAQ_M_F))
4851   ]
4852   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4853   "vpst\;vminnmat.f%#<V_sz_elem>        %q0, %q2"
4854   [(set_attr "type" "mve_move")
4855    (set_attr "length""8")])
4856
4857 ;;
4858 ;; [vminnmavq_p_f])
4859 ;;
4860 (define_insn "mve_vminnmavq_p_f<mode>"
4861   [
4862    (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
4863         (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
4864                        (match_operand:MVE_0 2 "s_register_operand" "w")
4865                        (match_operand:HI 3 "vpr_register_operand" "Up")]
4866          VMINNMAVQ_P_F))
4867   ]
4868   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4869   "vpst\;vminnmavt.f%#<V_sz_elem>       %0, %q2"
4870   [(set_attr "type" "mve_move")
4871    (set_attr "length""8")])
4872 ;;
4873 ;; [vminnmvq_p_f])
4874 ;;
4875 (define_insn "mve_vminnmvq_p_f<mode>"
4876   [
4877    (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
4878         (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
4879                        (match_operand:MVE_0 2 "s_register_operand" "w")
4880                        (match_operand:HI 3 "vpr_register_operand" "Up")]
4881          VMINNMVQ_P_F))
4882   ]
4883   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4884   "vpst\;vminnmvt.f%#<V_sz_elem>        %0, %q2"
4885   [(set_attr "type" "mve_move")
4886    (set_attr "length""8")])
4887
4888 ;;
4889 ;; [vmlaldavaq_s, vmlaldavaq_u])
4890 ;;
4891 (define_insn "mve_vmlaldavaq_<supf><mode>"
4892   [
4893    (set (match_operand:DI 0 "s_register_operand" "=r")
4894         (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
4895                        (match_operand:MVE_5 2 "s_register_operand" "w")
4896                        (match_operand:MVE_5 3 "s_register_operand" "w")]
4897          VMLALDAVAQ))
4898   ]
4899   "TARGET_HAVE_MVE"
4900   "vmlaldava.<supf>%#<V_sz_elem> %Q0, %R0, %q2, %q3"
4901   [(set_attr "type" "mve_move")
4902 ])
4903
4904 ;;
4905 ;; [vmlaldavaxq_s])
4906 ;;
4907 (define_insn "mve_vmlaldavaxq_s<mode>"
4908   [
4909    (set (match_operand:DI 0 "s_register_operand" "=r")
4910         (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
4911                        (match_operand:MVE_5 2 "s_register_operand" "w")
4912                        (match_operand:MVE_5 3 "s_register_operand" "w")]
4913          VMLALDAVAXQ_S))
4914   ]
4915   "TARGET_HAVE_MVE"
4916   "vmlaldavax.s%#<V_sz_elem> %Q0, %R0, %q2, %q3"
4917   [(set_attr "type" "mve_move")
4918 ])
4919
4920 ;;
4921 ;; [vmlaldavq_p_u, vmlaldavq_p_s])
4922 ;;
4923 (define_insn "mve_vmlaldavq_p_<supf><mode>"
4924   [
4925    (set (match_operand:DI 0 "s_register_operand" "=r")
4926         (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
4927                        (match_operand:MVE_5 2 "s_register_operand" "w")
4928                        (match_operand:HI 3 "vpr_register_operand" "Up")]
4929          VMLALDAVQ_P))
4930   ]
4931   "TARGET_HAVE_MVE"
4932   "vpst\;vmlaldavt.<supf>%#<V_sz_elem> %Q0, %R0, %q1, %q2"
4933   [(set_attr "type" "mve_move")
4934    (set_attr "length""8")])
4935
4936 ;;
4937 ;; [vmlaldavxq_p_s])
4938 ;;
4939 (define_insn "mve_vmlaldavxq_p_s<mode>"
4940   [
4941    (set (match_operand:DI 0 "s_register_operand" "=r")
4942         (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
4943                        (match_operand:MVE_5 2 "s_register_operand" "w")
4944                        (match_operand:HI 3 "vpr_register_operand" "Up")]
4945          VMLALDAVXQ_P_S))
4946   ]
4947   "TARGET_HAVE_MVE"
4948   "vpst\;vmlaldavxt.s%#<V_sz_elem>\t%Q0, %R0, %q1, %q2"
4949   [(set_attr "type" "mve_move")
4950    (set_attr "length""8")])
4951 ;;
4952 ;; [vmlsldavaq_s])
4953 ;;
4954 (define_insn "mve_vmlsldavaq_s<mode>"
4955   [
4956    (set (match_operand:DI 0 "s_register_operand" "=r")
4957         (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
4958                        (match_operand:MVE_5 2 "s_register_operand" "w")
4959                        (match_operand:MVE_5 3 "s_register_operand" "w")]
4960          VMLSLDAVAQ_S))
4961   ]
4962   "TARGET_HAVE_MVE"
4963   "vmlsldava.s%#<V_sz_elem> %Q0, %R0, %q2, %q3"
4964   [(set_attr "type" "mve_move")
4965 ])
4966
4967 ;;
4968 ;; [vmlsldavaxq_s])
4969 ;;
4970 (define_insn "mve_vmlsldavaxq_s<mode>"
4971   [
4972    (set (match_operand:DI 0 "s_register_operand" "=r")
4973         (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
4974                        (match_operand:MVE_5 2 "s_register_operand" "w")
4975                        (match_operand:MVE_5 3 "s_register_operand" "w")]
4976          VMLSLDAVAXQ_S))
4977   ]
4978   "TARGET_HAVE_MVE"
4979   "vmlsldavax.s%#<V_sz_elem> %Q0, %R0, %q2, %q3"
4980   [(set_attr "type" "mve_move")
4981 ])
4982
4983 ;;
4984 ;; [vmlsldavq_p_s])
4985 ;;
4986 (define_insn "mve_vmlsldavq_p_s<mode>"
4987   [
4988    (set (match_operand:DI 0 "s_register_operand" "=r")
4989         (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
4990                        (match_operand:MVE_5 2 "s_register_operand" "w")
4991                        (match_operand:HI 3 "vpr_register_operand" "Up")]
4992          VMLSLDAVQ_P_S))
4993   ]
4994   "TARGET_HAVE_MVE"
4995   "vpst\;vmlsldavt.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
4996   [(set_attr "type" "mve_move")
4997    (set_attr "length""8")])
4998
4999 ;;
5000 ;; [vmlsldavxq_p_s])
5001 ;;
5002 (define_insn "mve_vmlsldavxq_p_s<mode>"
5003   [
5004    (set (match_operand:DI 0 "s_register_operand" "=r")
5005         (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
5006                        (match_operand:MVE_5 2 "s_register_operand" "w")
5007                        (match_operand:HI 3 "vpr_register_operand" "Up")]
5008          VMLSLDAVXQ_P_S))
5009   ]
5010   "TARGET_HAVE_MVE"
5011   "vpst\;vmlsldavxt.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
5012   [(set_attr "type" "mve_move")
5013    (set_attr "length""8")])
5014 ;;
5015 ;; [vmovlbq_m_u, vmovlbq_m_s])
5016 ;;
5017 (define_insn "mve_vmovlbq_m_<supf><mode>"
5018   [
5019    (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
5020         (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
5021                        (match_operand:MVE_3 2 "s_register_operand" "w")
5022                        (match_operand:HI 3 "vpr_register_operand" "Up")]
5023          VMOVLBQ_M))
5024   ]
5025   "TARGET_HAVE_MVE"
5026   "vpst\;vmovlbt.<supf>%#<V_sz_elem>    %q0, %q2"
5027   [(set_attr "type" "mve_move")
5028    (set_attr "length""8")])
5029 ;;
5030 ;; [vmovltq_m_u, vmovltq_m_s])
5031 ;;
5032 (define_insn "mve_vmovltq_m_<supf><mode>"
5033   [
5034    (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
5035         (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
5036                        (match_operand:MVE_3 2 "s_register_operand" "w")
5037                        (match_operand:HI 3 "vpr_register_operand" "Up")]
5038          VMOVLTQ_M))
5039   ]
5040   "TARGET_HAVE_MVE"
5041   "vpst\;vmovltt.<supf>%#<V_sz_elem>    %q0, %q2"
5042   [(set_attr "type" "mve_move")
5043    (set_attr "length""8")])
5044 ;;
5045 ;; [vmovnbq_m_u, vmovnbq_m_s])
5046 ;;
5047 (define_insn "mve_vmovnbq_m_<supf><mode>"
5048   [
5049    (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5050         (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5051                        (match_operand:MVE_5 2 "s_register_operand" "w")
5052                        (match_operand:HI 3 "vpr_register_operand" "Up")]
5053          VMOVNBQ_M))
5054   ]
5055   "TARGET_HAVE_MVE"
5056   "vpst\;vmovnbt.i%#<V_sz_elem> %q0, %q2"
5057   [(set_attr "type" "mve_move")
5058    (set_attr "length""8")])
5059
5060 ;;
5061 ;; [vmovntq_m_u, vmovntq_m_s])
5062 ;;
5063 (define_insn "mve_vmovntq_m_<supf><mode>"
5064   [
5065    (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5066         (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5067                        (match_operand:MVE_5 2 "s_register_operand" "w")
5068                        (match_operand:HI 3 "vpr_register_operand" "Up")]
5069          VMOVNTQ_M))
5070   ]
5071   "TARGET_HAVE_MVE"
5072   "vpst\;vmovntt.i%#<V_sz_elem> %q0, %q2"
5073   [(set_attr "type" "mve_move")
5074    (set_attr "length""8")])
5075
5076 ;;
5077 ;; [vmvnq_m_n_u, vmvnq_m_n_s])
5078 ;;
5079 (define_insn "mve_vmvnq_m_n_<supf><mode>"
5080   [
5081    (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5082         (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5083                        (match_operand:SI 2 "immediate_operand" "i")
5084                        (match_operand:HI 3 "vpr_register_operand" "Up")]
5085          VMVNQ_M_N))
5086   ]
5087   "TARGET_HAVE_MVE"
5088   "vpst\;vmvnt.i%#<V_sz_elem>   %q0, %2"
5089   [(set_attr "type" "mve_move")
5090    (set_attr "length""8")])
5091 ;;
5092 ;; [vnegq_m_f])
5093 ;;
5094 (define_insn "mve_vnegq_m_f<mode>"
5095   [
5096    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5097         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5098                        (match_operand:MVE_0 2 "s_register_operand" "w")
5099                        (match_operand:HI 3 "vpr_register_operand" "Up")]
5100          VNEGQ_M_F))
5101   ]
5102   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5103   "vpst\;vnegt.f%#<V_sz_elem>   %q0, %q2"
5104   [(set_attr "type" "mve_move")
5105    (set_attr "length""8")])
5106
5107 ;;
5108 ;; [vorrq_m_n_s, vorrq_m_n_u])
5109 ;;
5110 (define_insn "mve_vorrq_m_n_<supf><mode>"
5111   [
5112    (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5113         (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5114                        (match_operand:SI 2 "immediate_operand" "i")
5115                        (match_operand:HI 3 "vpr_register_operand" "Up")]
5116          VORRQ_M_N))
5117   ]
5118   "TARGET_HAVE_MVE"
5119   "vpst\;vorrt.i%#<V_sz_elem>   %q0, %2"
5120   [(set_attr "type" "mve_move")
5121    (set_attr "length""8")])
5122 ;;
5123 ;; [vpselq_f])
5124 ;;
5125 (define_insn "mve_vpselq_f<mode>"
5126   [
5127    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5128         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
5129                        (match_operand:MVE_0 2 "s_register_operand" "w")
5130                        (match_operand:HI 3 "vpr_register_operand" "Up")]
5131          VPSELQ_F))
5132   ]
5133   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5134   "vpsel %q0, %q1, %q2"
5135   [(set_attr "type" "mve_move")
5136 ])
5137
5138 ;;
5139 ;; [vqmovnbq_m_s, vqmovnbq_m_u])
5140 ;;
5141 (define_insn "mve_vqmovnbq_m_<supf><mode>"
5142   [
5143    (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5144         (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5145                        (match_operand:MVE_5 2 "s_register_operand" "w")
5146                        (match_operand:HI 3 "vpr_register_operand" "Up")]
5147          VQMOVNBQ_M))
5148   ]
5149   "TARGET_HAVE_MVE"
5150   "vpst\;vqmovnbt.<supf>%#<V_sz_elem>   %q0, %q2"
5151   [(set_attr "type" "mve_move")
5152    (set_attr "length""8")])
5153
5154 ;;
5155 ;; [vqmovntq_m_u, vqmovntq_m_s])
5156 ;;
5157 (define_insn "mve_vqmovntq_m_<supf><mode>"
5158   [
5159    (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5160         (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5161                        (match_operand:MVE_5 2 "s_register_operand" "w")
5162                        (match_operand:HI 3 "vpr_register_operand" "Up")]
5163          VQMOVNTQ_M))
5164   ]
5165   "TARGET_HAVE_MVE"
5166   "vpst\;vqmovntt.<supf>%#<V_sz_elem>   %q0, %q2"
5167   [(set_attr "type" "mve_move")
5168    (set_attr "length""8")])
5169
5170 ;;
5171 ;; [vqmovunbq_m_s])
5172 ;;
5173 (define_insn "mve_vqmovunbq_m_s<mode>"
5174   [
5175    (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5176         (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5177                        (match_operand:MVE_5 2 "s_register_operand" "w")
5178                        (match_operand:HI 3 "vpr_register_operand" "Up")]
5179          VQMOVUNBQ_M_S))
5180   ]
5181   "TARGET_HAVE_MVE"
5182   "vpst\;vqmovunbt.s%#<V_sz_elem>       %q0, %q2"
5183   [(set_attr "type" "mve_move")
5184    (set_attr "length""8")])
5185
5186 ;;
5187 ;; [vqmovuntq_m_s])
5188 ;;
5189 (define_insn "mve_vqmovuntq_m_s<mode>"
5190   [
5191    (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5192         (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5193                        (match_operand:MVE_5 2 "s_register_operand" "w")
5194                        (match_operand:HI 3 "vpr_register_operand" "Up")]
5195          VQMOVUNTQ_M_S))
5196   ]
5197   "TARGET_HAVE_MVE"
5198   "vpst\;vqmovuntt.s%#<V_sz_elem>       %q0, %q2"
5199   [(set_attr "type" "mve_move")
5200    (set_attr "length""8")])
5201
5202 ;;
5203 ;; [vqrshrntq_n_u, vqrshrntq_n_s])
5204 ;;
5205 (define_insn "mve_vqrshrntq_n_<supf><mode>"
5206   [
5207    (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5208         (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5209                        (match_operand:MVE_5 2 "s_register_operand" "w")
5210                        (match_operand:SI 3 "mve_imm_8" "Rb")]
5211          VQRSHRNTQ_N))
5212   ]
5213   "TARGET_HAVE_MVE"
5214   "vqrshrnt.<supf>%#<V_sz_elem> %q0, %q2, %3"
5215   [(set_attr "type" "mve_move")
5216 ])
5217
5218 ;;
5219 ;; [vqrshruntq_n_s])
5220 ;;
5221 (define_insn "mve_vqrshruntq_n_s<mode>"
5222   [
5223    (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5224         (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5225                        (match_operand:MVE_5 2 "s_register_operand" "w")
5226                        (match_operand:SI 3 "mve_imm_8" "Rb")]
5227          VQRSHRUNTQ_N_S))
5228   ]
5229   "TARGET_HAVE_MVE"
5230   "vqrshrunt.s%#<V_sz_elem>     %q0, %q2, %3"
5231   [(set_attr "type" "mve_move")
5232 ])
5233
5234 ;;
5235 ;; [vqshrnbq_n_u, vqshrnbq_n_s])
5236 ;;
5237 (define_insn "mve_vqshrnbq_n_<supf><mode>"
5238   [
5239    (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5240         (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5241                        (match_operand:MVE_5 2 "s_register_operand" "w")
5242                        (match_operand:SI 3 "<MVE_pred1>" "<MVE_constraint1>")]
5243          VQSHRNBQ_N))
5244   ]
5245   "TARGET_HAVE_MVE"
5246   "vqshrnb.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
5247   [(set_attr "type" "mve_move")
5248 ])
5249
5250 ;;
5251 ;; [vqshrntq_n_u, vqshrntq_n_s])
5252 ;;
5253 (define_insn "mve_vqshrntq_n_<supf><mode>"
5254   [
5255    (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5256         (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5257                        (match_operand:MVE_5 2 "s_register_operand" "w")
5258                        (match_operand:SI 3 "mve_imm_8" "Rb")]
5259          VQSHRNTQ_N))
5260   ]
5261   "TARGET_HAVE_MVE"
5262   "vqshrnt.<supf>%#<V_sz_elem>  %q0, %q2, %3"
5263   [(set_attr "type" "mve_move")
5264 ])
5265
5266 ;;
5267 ;; [vqshrunbq_n_s])
5268 ;;
5269 (define_insn "mve_vqshrunbq_n_s<mode>"
5270   [
5271    (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5272         (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5273                        (match_operand:MVE_5 2 "s_register_operand" "w")
5274                        (match_operand:SI 3 "immediate_operand" "i")]
5275          VQSHRUNBQ_N_S))
5276   ]
5277   "TARGET_HAVE_MVE"
5278   "vqshrunb.s%#<V_sz_elem>      %q0, %q2, %3"
5279   [(set_attr "type" "mve_move")
5280 ])
5281
5282 ;;
5283 ;; [vqshruntq_n_s])
5284 ;;
5285 (define_insn "mve_vqshruntq_n_s<mode>"
5286   [
5287    (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5288         (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5289                        (match_operand:MVE_5 2 "s_register_operand" "w")
5290                        (match_operand:SI 3 "mve_imm_8" "Rb")]
5291          VQSHRUNTQ_N_S))
5292   ]
5293   "TARGET_HAVE_MVE"
5294   "vqshrunt.s%#<V_sz_elem>      %q0, %q2, %3"
5295   [(set_attr "type" "mve_move")
5296 ])
5297
5298 ;;
5299 ;; [vrev32q_m_f])
5300 ;;
5301 (define_insn "mve_vrev32q_m_fv8hf"
5302   [
5303    (set (match_operand:V8HF 0 "s_register_operand" "=w")
5304         (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
5305                        (match_operand:V8HF 2 "s_register_operand" "w")
5306                        (match_operand:HI 3 "vpr_register_operand" "Up")]
5307          VREV32Q_M_F))
5308   ]
5309   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5310   "vpst\;vrev32t.16 %q0, %q2"
5311   [(set_attr "type" "mve_move")
5312    (set_attr "length""8")])
5313
5314 ;;
5315 ;; [vrev32q_m_s, vrev32q_m_u])
5316 ;;
5317 (define_insn "mve_vrev32q_m_<supf><mode>"
5318   [
5319    (set (match_operand:MVE_3 0 "s_register_operand" "=w")
5320         (unspec:MVE_3 [(match_operand:MVE_3 1 "s_register_operand" "0")
5321                        (match_operand:MVE_3 2 "s_register_operand" "w")
5322                        (match_operand:HI 3 "vpr_register_operand" "Up")]
5323          VREV32Q_M))
5324   ]
5325   "TARGET_HAVE_MVE"
5326   "vpst\;vrev32t.%#<V_sz_elem>  %q0, %q2"
5327   [(set_attr "type" "mve_move")
5328    (set_attr "length""8")])
5329
5330 ;;
5331 ;; [vrev64q_m_f])
5332 ;;
5333 (define_insn "mve_vrev64q_m_f<mode>"
5334   [
5335    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5336         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5337                        (match_operand:MVE_0 2 "s_register_operand" "w")
5338                        (match_operand:HI 3 "vpr_register_operand" "Up")]
5339          VREV64Q_M_F))
5340   ]
5341   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5342   "vpst\;vrev64t.%#<V_sz_elem>  %q0, %q2"
5343   [(set_attr "type" "mve_move")
5344    (set_attr "length""8")])
5345
5346 ;;
5347 ;; [vrmlaldavhaxq_s])
5348 ;;
5349 (define_insn "mve_vrmlaldavhaxq_sv4si"
5350   [
5351    (set (match_operand:DI 0 "s_register_operand" "=r")
5352         (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
5353                        (match_operand:V4SI 2 "s_register_operand" "w")
5354                        (match_operand:V4SI 3 "s_register_operand" "w")]
5355          VRMLALDAVHAXQ_S))
5356   ]
5357   "TARGET_HAVE_MVE"
5358   "vrmlaldavhax.s32 %Q0, %R0, %q2, %q3"
5359   [(set_attr "type" "mve_move")
5360 ])
5361
5362 ;;
5363 ;; [vrmlaldavhxq_p_s])
5364 ;;
5365 (define_insn "mve_vrmlaldavhxq_p_sv4si"
5366   [
5367    (set (match_operand:DI 0 "s_register_operand" "=r")
5368         (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
5369                        (match_operand:V4SI 2 "s_register_operand" "w")
5370                        (match_operand:HI 3 "vpr_register_operand" "Up")]
5371          VRMLALDAVHXQ_P_S))
5372   ]
5373   "TARGET_HAVE_MVE"
5374   "vpst\;vrmlaldavhxt.s32 %Q0, %R0, %q1, %q2"
5375   [(set_attr "type" "mve_move")
5376    (set_attr "length""8")])
5377
5378 ;;
5379 ;; [vrmlsldavhaxq_s])
5380 ;;
5381 (define_insn "mve_vrmlsldavhaxq_sv4si"
5382   [
5383    (set (match_operand:DI 0 "s_register_operand" "=r")
5384         (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
5385                        (match_operand:V4SI 2 "s_register_operand" "w")
5386                        (match_operand:V4SI 3 "s_register_operand" "w")]
5387          VRMLSLDAVHAXQ_S))
5388   ]
5389   "TARGET_HAVE_MVE"
5390   "vrmlsldavhax.s32 %Q0, %R0, %q2, %q3"
5391   [(set_attr "type" "mve_move")
5392 ])
5393
5394 ;;
5395 ;; [vrmlsldavhq_p_s])
5396 ;;
5397 (define_insn "mve_vrmlsldavhq_p_sv4si"
5398   [
5399    (set (match_operand:DI 0 "s_register_operand" "=r")
5400         (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
5401                        (match_operand:V4SI 2 "s_register_operand" "w")
5402                        (match_operand:HI 3 "vpr_register_operand" "Up")]
5403          VRMLSLDAVHQ_P_S))
5404   ]
5405   "TARGET_HAVE_MVE"
5406   "vpst\;vrmlsldavht.s32 %Q0, %R0, %q1, %q2"
5407   [(set_attr "type" "mve_move")
5408    (set_attr "length""8")])
5409
5410 ;;
5411 ;; [vrmlsldavhxq_p_s])
5412 ;;
5413 (define_insn "mve_vrmlsldavhxq_p_sv4si"
5414   [
5415    (set (match_operand:DI 0 "s_register_operand" "=r")
5416         (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
5417                        (match_operand:V4SI 2 "s_register_operand" "w")
5418                        (match_operand:HI 3 "vpr_register_operand" "Up")]
5419          VRMLSLDAVHXQ_P_S))
5420   ]
5421   "TARGET_HAVE_MVE"
5422   "vpst\;vrmlsldavhxt.s32 %Q0, %R0, %q1, %q2"
5423   [(set_attr "type" "mve_move")
5424    (set_attr "length""8")])
5425
5426 ;;
5427 ;; [vrndaq_m_f])
5428 ;;
5429 (define_insn "mve_vrndaq_m_f<mode>"
5430   [
5431    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5432         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5433                        (match_operand:MVE_0 2 "s_register_operand" "w")
5434                        (match_operand:HI 3 "vpr_register_operand" "Up")]
5435          VRNDAQ_M_F))
5436   ]
5437   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5438   "vpst\;vrintat.f%#<V_sz_elem> %q0, %q2"
5439   [(set_attr "type" "mve_move")
5440    (set_attr "length""8")])
5441
5442 ;;
5443 ;; [vrndmq_m_f])
5444 ;;
5445 (define_insn "mve_vrndmq_m_f<mode>"
5446   [
5447    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5448         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5449                        (match_operand:MVE_0 2 "s_register_operand" "w")
5450                        (match_operand:HI 3 "vpr_register_operand" "Up")]
5451          VRNDMQ_M_F))
5452   ]
5453   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5454   "vpst\;vrintmt.f%#<V_sz_elem> %q0, %q2"
5455   [(set_attr "type" "mve_move")
5456    (set_attr "length""8")])
5457
5458 ;;
5459 ;; [vrndnq_m_f])
5460 ;;
5461 (define_insn "mve_vrndnq_m_f<mode>"
5462   [
5463    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5464         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5465                        (match_operand:MVE_0 2 "s_register_operand" "w")
5466                        (match_operand:HI 3 "vpr_register_operand" "Up")]
5467          VRNDNQ_M_F))
5468   ]
5469   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5470   "vpst\;vrintnt.f%#<V_sz_elem> %q0, %q2"
5471   [(set_attr "type" "mve_move")
5472    (set_attr "length""8")])
5473
5474 ;;
5475 ;; [vrndpq_m_f])
5476 ;;
5477 (define_insn "mve_vrndpq_m_f<mode>"
5478   [
5479    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5480         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5481                        (match_operand:MVE_0 2 "s_register_operand" "w")
5482                        (match_operand:HI 3 "vpr_register_operand" "Up")]
5483          VRNDPQ_M_F))
5484   ]
5485   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5486   "vpst\;vrintpt.f%#<V_sz_elem> %q0, %q2"
5487   [(set_attr "type" "mve_move")
5488    (set_attr "length""8")])
5489
5490 ;;
5491 ;; [vrndxq_m_f])
5492 ;;
5493 (define_insn "mve_vrndxq_m_f<mode>"
5494   [
5495    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5496         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5497                        (match_operand:MVE_0 2 "s_register_operand" "w")
5498                        (match_operand:HI 3 "vpr_register_operand" "Up")]
5499          VRNDXQ_M_F))
5500   ]
5501   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5502   "vpst\;vrintxt.f%#<V_sz_elem> %q0, %q2"
5503   [(set_attr "type" "mve_move")
5504    (set_attr "length""8")])
5505
5506 ;;
5507 ;; [vrshrnbq_n_s, vrshrnbq_n_u])
5508 ;;
5509 (define_insn "mve_vrshrnbq_n_<supf><mode>"
5510   [
5511    (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5512         (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5513                        (match_operand:MVE_5 2 "s_register_operand" "w")
5514                        (match_operand:SI 3 "mve_imm_8" "Rb")]
5515          VRSHRNBQ_N))
5516   ]
5517   "TARGET_HAVE_MVE"
5518   "vrshrnb.i%#<V_sz_elem>       %q0, %q2, %3"
5519   [(set_attr "type" "mve_move")
5520 ])
5521
5522 ;;
5523 ;; [vrshrntq_n_u, vrshrntq_n_s])
5524 ;;
5525 (define_insn "mve_vrshrntq_n_<supf><mode>"
5526   [
5527    (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5528         (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5529                        (match_operand:MVE_5 2 "s_register_operand" "w")
5530                        (match_operand:SI 3 "mve_imm_8" "Rb")]
5531          VRSHRNTQ_N))
5532   ]
5533   "TARGET_HAVE_MVE"
5534   "vrshrnt.i%#<V_sz_elem>       %q0, %q2, %3"
5535   [(set_attr "type" "mve_move")
5536 ])
5537
5538 ;;
5539 ;; [vshrnbq_n_u, vshrnbq_n_s])
5540 ;;
5541 (define_insn "mve_vshrnbq_n_<supf><mode>"
5542   [
5543    (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5544         (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5545                        (match_operand:MVE_5 2 "s_register_operand" "w")
5546                        (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")]
5547          VSHRNBQ_N))
5548   ]
5549   "TARGET_HAVE_MVE"
5550   "vshrnb.i%#<V_sz_elem>        %q0, %q2, %3"
5551   [(set_attr "type" "mve_move")
5552 ])
5553
5554 ;;
5555 ;; [vshrntq_n_s, vshrntq_n_u])
5556 ;;
5557 (define_insn "mve_vshrntq_n_<supf><mode>"
5558   [
5559    (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5560         (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5561                                  (match_operand:MVE_5 2 "s_register_operand" "w")
5562                                  (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")]
5563          VSHRNTQ_N))
5564   ]
5565   "TARGET_HAVE_MVE"
5566   "vshrnt.i%#<V_sz_elem>\t%q0, %q2, %3"
5567   [(set_attr "type" "mve_move")
5568 ])
5569
5570 ;;
5571 ;; [vcvtmq_m_s, vcvtmq_m_u])
5572 ;;
5573 (define_insn "mve_vcvtmq_m_<supf><mode>"
5574   [
5575    (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5576         (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5577                        (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
5578                        (match_operand:HI 3 "vpr_register_operand" "Up")]
5579          VCVTMQ_M))
5580   ]
5581   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5582   "vpst\;vcvtmt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
5583   [(set_attr "type" "mve_move")
5584    (set_attr "length""8")])
5585
5586 ;;
5587 ;; [vcvtpq_m_u, vcvtpq_m_s])
5588 ;;
5589 (define_insn "mve_vcvtpq_m_<supf><mode>"
5590   [
5591    (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5592         (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5593                        (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
5594                        (match_operand:HI 3 "vpr_register_operand" "Up")]
5595          VCVTPQ_M))
5596   ]
5597   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5598   "vpst\;vcvtpt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
5599   [(set_attr "type" "mve_move")
5600    (set_attr "length""8")])
5601
5602 ;;
5603 ;; [vcvtnq_m_s, vcvtnq_m_u])
5604 ;;
5605 (define_insn "mve_vcvtnq_m_<supf><mode>"
5606   [
5607    (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5608         (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5609                        (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
5610                        (match_operand:HI 3 "vpr_register_operand" "Up")]
5611          VCVTNQ_M))
5612   ]
5613   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5614   "vpst\;vcvtnt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
5615   [(set_attr "type" "mve_move")
5616    (set_attr "length""8")])
5617
5618 ;;
5619 ;; [vcvtq_m_n_from_f_s, vcvtq_m_n_from_f_u])
5620 ;;
5621 (define_insn "mve_vcvtq_m_n_from_f_<supf><mode>"
5622   [
5623    (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5624         (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5625                        (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
5626                        (match_operand:SI 3 "mve_imm_16" "Rd")
5627                        (match_operand:HI 4 "vpr_register_operand" "Up")]
5628          VCVTQ_M_N_FROM_F))
5629   ]
5630   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5631   "vpst\;vcvtt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2, %3"
5632   [(set_attr "type" "mve_move")
5633    (set_attr "length""8")])
5634
5635 ;;
5636 ;; [vrev16q_m_u, vrev16q_m_s])
5637 ;;
5638 (define_insn "mve_vrev16q_m_<supf>v16qi"
5639   [
5640    (set (match_operand:V16QI 0 "s_register_operand" "=w")
5641         (unspec:V16QI [(match_operand:V16QI 1 "s_register_operand" "0")
5642                        (match_operand:V16QI 2 "s_register_operand" "w")
5643                        (match_operand:HI 3 "vpr_register_operand" "Up")]
5644          VREV16Q_M))
5645   ]
5646   "TARGET_HAVE_MVE"
5647   "vpst\;vrev16t.8 %q0, %q2"
5648   [(set_attr "type" "mve_move")
5649    (set_attr "length""8")])
5650
5651 ;;
5652 ;; [vcvtq_m_from_f_u, vcvtq_m_from_f_s])
5653 ;;
5654 (define_insn "mve_vcvtq_m_from_f_<supf><mode>"
5655   [
5656    (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5657         (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5658                        (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
5659                        (match_operand:HI 3 "vpr_register_operand" "Up")]
5660          VCVTQ_M_FROM_F))
5661   ]
5662   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5663   "vpst\;vcvtt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
5664   [(set_attr "type" "mve_move")
5665    (set_attr "length""8")])
5666
5667 ;;
5668 ;; [vrmlaldavhq_p_u vrmlaldavhq_p_s])
5669 ;;
5670 (define_insn "mve_vrmlaldavhq_p_<supf>v4si"
5671   [
5672    (set (match_operand:DI 0 "s_register_operand" "=r")
5673         (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
5674                     (match_operand:V4SI 2 "s_register_operand" "w")
5675                     (match_operand:HI 3 "vpr_register_operand" "Up")]
5676          VRMLALDAVHQ_P))
5677   ]
5678   "TARGET_HAVE_MVE"
5679   "vpst\;vrmlaldavht.<supf>32 %Q0, %R0, %q1, %q2"
5680   [(set_attr "type" "mve_move")
5681    (set_attr "length""8")])
5682
5683 ;;
5684 ;; [vrmlsldavhaq_s])
5685 ;;
5686 (define_insn "mve_vrmlsldavhaq_sv4si"
5687   [
5688    (set (match_operand:DI 0 "s_register_operand" "=r")
5689         (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
5690                     (match_operand:V4SI 2 "s_register_operand" "w")
5691                     (match_operand:V4SI 3 "s_register_operand" "w")]
5692          VRMLSLDAVHAQ_S))
5693   ]
5694   "TARGET_HAVE_MVE"
5695   "vrmlsldavha.s32 %Q0, %R0, %q2, %q3"
5696   [(set_attr "type" "mve_move")
5697 ])
5698
5699 ;;
5700 ;; [vabavq_p_s, vabavq_p_u])
5701 ;;
5702 (define_insn "mve_vabavq_p_<supf><mode>"
5703   [
5704    (set (match_operand:SI 0 "s_register_operand" "=r")
5705         (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
5706                     (match_operand:MVE_2 2 "s_register_operand" "w")
5707                     (match_operand:MVE_2 3 "s_register_operand" "w")
5708                     (match_operand:HI 4 "vpr_register_operand" "Up")]
5709          VABAVQ_P))
5710   ]
5711   "TARGET_HAVE_MVE"
5712   "vpst\;vabavt.<supf>%#<V_sz_elem>\t%0, %q2, %q3"
5713   [(set_attr "type" "mve_move")
5714 ])
5715
5716 ;;
5717 ;; [vqshluq_m_n_s])
5718 ;;
5719 (define_insn "mve_vqshluq_m_n_s<mode>"
5720   [
5721    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5722         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5723                        (match_operand:MVE_2 2 "s_register_operand" "w")
5724                        (match_operand:SI 3 "mve_imm_7" "Ra")
5725                        (match_operand:HI 4 "vpr_register_operand" "Up")]
5726          VQSHLUQ_M_N_S))
5727   ]
5728   "TARGET_HAVE_MVE"
5729   "vpst\n\tvqshlut.s%#<V_sz_elem>\t%q0, %q2, %3"
5730   [(set_attr "type" "mve_move")])
5731
5732 ;;
5733 ;; [vshlq_m_s, vshlq_m_u])
5734 ;;
5735 (define_insn "mve_vshlq_m_<supf><mode>"
5736   [
5737    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5738         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5739                        (match_operand:MVE_2 2 "s_register_operand" "w")
5740                        (match_operand:MVE_2 3 "s_register_operand" "w")
5741                        (match_operand:HI 4 "vpr_register_operand" "Up")]
5742          VSHLQ_M))
5743   ]
5744   "TARGET_HAVE_MVE"
5745   "vpst\;vshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
5746   [(set_attr "type" "mve_move")])
5747
5748 ;;
5749 ;; [vsriq_m_n_s, vsriq_m_n_u])
5750 ;;
5751 (define_insn "mve_vsriq_m_n_<supf><mode>"
5752   [
5753    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5754         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5755                        (match_operand:MVE_2 2 "s_register_operand" "w")
5756                        (match_operand:SI 3 "mve_imm_selective_upto_8" "Rg")
5757                        (match_operand:HI 4 "vpr_register_operand" "Up")]
5758          VSRIQ_M_N))
5759   ]
5760   "TARGET_HAVE_MVE"
5761   "vpst\;vsrit.%#<V_sz_elem>\t%q0, %q2, %3"
5762   [(set_attr "type" "mve_move")])
5763
5764 ;;
5765 ;; [vsubq_m_u, vsubq_m_s])
5766 ;;
5767 (define_insn "mve_vsubq_m_<supf><mode>"
5768   [
5769    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5770         (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5771                        (match_operand:MVE_2 2 "s_register_operand" "w")
5772                        (match_operand:MVE_2 3 "s_register_operand" "w")
5773                        (match_operand:HI 4 "vpr_register_operand" "Up")]
5774          VSUBQ_M))
5775   ]
5776   "TARGET_HAVE_MVE"
5777   "vpst\;vsubt.i%#<V_sz_elem>\t%q0, %q2, %q3"
5778   [(set_attr "type" "mve_move")])
5779
5780 ;;
5781 ;; [vcvtq_m_n_to_f_u, vcvtq_m_n_to_f_s])
5782 ;;
5783 (define_insn "mve_vcvtq_m_n_to_f_<supf><mode>"
5784   [
5785    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5786         (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5787                        (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
5788                        (match_operand:SI 3 "mve_imm_16" "Rd")
5789                        (match_operand:HI 4 "vpr_register_operand" "Up")]
5790          VCVTQ_M_N_TO_F))
5791   ]
5792   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5793   "vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
5794   [(set_attr "type" "mve_move")
5795    (set_attr "length""8")])