1 ;; Arm M-profile Vector Extension Machine Description
2 ;; Copyright (C) 2019-2020 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify it
7 ;; under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful, but
12 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 ;; General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 (define_mode_attr V_sz_elem2 [(V16QI "s8") (V8HI "u16") (V4SI "u32")
22 (define_mode_iterator MVE_types [V16QI V8HI V4SI V2DI TI V8HF V4SF V2DF])
23 (define_mode_iterator MVE_VLD_ST [V16QI V8HI V4SI V8HF V4SF])
24 (define_mode_iterator MVE_0 [V8HF V4SF])
25 (define_mode_iterator MVE_1 [V16QI V8HI V4SI V2DI])
26 (define_mode_iterator MVE_3 [V16QI V8HI])
27 (define_mode_iterator MVE_2 [V16QI V8HI V4SI])
28 (define_mode_iterator MVE_5 [V8HI V4SI])
29 (define_mode_iterator MVE_6 [V8HI V4SI])
31 (define_c_enum "unspec" [VST4Q VRNDXQ_F VRNDQ_F VRNDPQ_F VRNDNQ_F VRNDMQ_F
32 VRNDAQ_F VREV64Q_F VNEGQ_F VDUPQ_N_F VABSQ_F VREV32Q_F
33 VCVTTQ_F32_F16 VCVTBQ_F32_F16 VCVTQ_TO_F_S VQNEGQ_S
34 VCVTQ_TO_F_U VREV16Q_S VREV16Q_U VADDLVQ_S VMVNQ_N_S
35 VMVNQ_N_U VCVTAQ_S VCVTAQ_U VREV64Q_S VREV64Q_U
36 VQABSQ_S VNEGQ_S VMVNQ_S VMVNQ_U VDUPQ_N_U VDUPQ_N_S
37 VCLZQ_U VCLZQ_S VCLSQ_S VADDVQ_S VADDVQ_U VABSQ_S
38 VREV32Q_U VREV32Q_S VMOVLTQ_U VMOVLTQ_S VMOVLBQ_S
39 VMOVLBQ_U VCVTQ_FROM_F_S VCVTQ_FROM_F_U VCVTPQ_S
40 VCVTPQ_U VCVTNQ_S VCVTNQ_U VCVTMQ_S VCVTMQ_U
41 VADDLVQ_U VCTP8Q VCTP16Q VCTP32Q VCTP64Q VPNOT
42 VCREATEQ_F VCVTQ_N_TO_F_S VCVTQ_N_TO_F_U VBRSRQ_N_F
43 VSUBQ_N_F VCREATEQ_U VCREATEQ_S VSHRQ_N_S VSHRQ_N_U
44 VCVTQ_N_FROM_F_S VCVTQ_N_FROM_F_U VADDLVQ_P_S
45 VADDLVQ_P_U VCMPNEQ_U VCMPNEQ_S VSHLQ_S VSHLQ_U VABDQ_S
46 VADDQ_N_S VADDVAQ_S VADDVQ_P_S VANDQ_S VBICQ_S
47 VBRSRQ_N_S VCADDQ_ROT270_S VCADDQ_ROT90_S VCMPEQQ_S
48 VCMPEQQ_N_S VCMPNEQ_N_S VEORQ_S VHADDQ_S VHADDQ_N_S
49 VHSUBQ_S VHSUBQ_N_S VMAXQ_S VMAXVQ_S VMINQ_S VMINVQ_S
50 VMLADAVQ_S VMULHQ_S VMULLBQ_INT_S VMULLTQ_INT_S VMULQ_S
51 VMULQ_N_S VORNQ_S VORRQ_S VQADDQ_S VQADDQ_N_S VQRSHLQ_S
52 VQRSHLQ_N_S VQSHLQ_S VQSHLQ_N_S VQSHLQ_R_S VQSUBQ_S
53 VQSUBQ_N_S VRHADDQ_S VRMULHQ_S VRSHLQ_S VRSHLQ_N_S
54 VRSHRQ_N_S VSHLQ_N_S VSHLQ_R_S VSUBQ_S VSUBQ_N_S
55 VABDQ_U VADDQ_N_U VADDVAQ_U VADDVQ_P_U VANDQ_U VBICQ_U
56 VBRSRQ_N_U VCADDQ_ROT270_U VCADDQ_ROT90_U VCMPEQQ_U
57 VCMPEQQ_N_U VCMPNEQ_N_U VEORQ_U VHADDQ_U VHADDQ_N_U
58 VHSUBQ_U VHSUBQ_N_U VMAXQ_U VMAXVQ_U VMINQ_U VMINVQ_U
59 VMLADAVQ_U VMULHQ_U VMULLBQ_INT_U VMULLTQ_INT_U VMULQ_U
60 VMULQ_N_U VORNQ_U VORRQ_U VQADDQ_U VQADDQ_N_U VQRSHLQ_U
61 VQRSHLQ_N_U VQSHLQ_U VQSHLQ_N_U VQSHLQ_R_U VQSUBQ_U
62 VQSUBQ_N_U VRHADDQ_U VRMULHQ_U VRSHLQ_U VRSHLQ_N_U
63 VRSHRQ_N_U VSHLQ_N_U VSHLQ_R_U VSUBQ_U VSUBQ_N_U
64 VCMPGEQ_N_S VCMPGEQ_S VCMPGTQ_N_S VCMPGTQ_S VCMPLEQ_N_S
65 VCMPLEQ_S VCMPLTQ_N_S VCMPLTQ_S VHCADDQ_ROT270_S
66 VHCADDQ_ROT90_S VMAXAQ_S VMAXAVQ_S VMINAQ_S VMINAVQ_S
67 VMLADAVXQ_S VMLSDAVQ_S VMLSDAVXQ_S VQDMULHQ_N_S
68 VQDMULHQ_S VQRDMULHQ_N_S VQRDMULHQ_S VQSHLUQ_N_S
69 VCMPCSQ_N_U VCMPCSQ_U VCMPHIQ_N_U VCMPHIQ_U VABDQ_M_S
70 VABDQ_M_U VABDQ_F VADDQ_N_F VANDQ_F VBICQ_F
71 VCADDQ_ROT270_F VCADDQ_ROT90_F VCMPEQQ_F VCMPEQQ_N_F
72 VCMPGEQ_F VCMPGEQ_N_F VCMPGTQ_F VCMPGTQ_N_F VCMPLEQ_F
73 VCMPLEQ_N_F VCMPLTQ_F VCMPLTQ_N_F VCMPNEQ_F VCMPNEQ_N_F
74 VCMULQ_F VCMULQ_ROT180_F VCMULQ_ROT270_F VCMULQ_ROT90_F
75 VEORQ_F VMAXNMAQ_F VMAXNMAVQ_F VMAXNMQ_F VMAXNMVQ_F
76 VMINNMAQ_F VMINNMAVQ_F VMINNMQ_F VMINNMVQ_F VMULQ_F
77 VMULQ_N_F VORNQ_F VORRQ_F VSUBQ_F VADDLVAQ_U
78 VADDLVAQ_S VBICQ_N_U VBICQ_N_S VCTP8Q_M VCTP16Q_M
79 VCTP32Q_M VCTP64Q_M VCVTBQ_F16_F32 VCVTTQ_F16_F32
80 VMLALDAVQ_U VMLALDAVXQ_U VMLALDAVXQ_S VMLALDAVQ_S
81 VMLSLDAVQ_S VMLSLDAVXQ_S VMOVNBQ_U VMOVNBQ_S
82 VMOVNTQ_U VMOVNTQ_S VORRQ_N_S VORRQ_N_U VQDMULLBQ_N_S
83 VQDMULLBQ_S VQDMULLTQ_N_S VQDMULLTQ_S VQMOVNBQ_U
84 VQMOVNBQ_S VQMOVUNBQ_S VQMOVUNTQ_S VRMLALDAVHXQ_S
85 VRMLSLDAVHQ_S VRMLSLDAVHXQ_S VSHLLBQ_S
86 VSHLLBQ_U VSHLLTQ_U VSHLLTQ_S VQMOVNTQ_U VQMOVNTQ_S
87 VSHLLBQ_N_S VSHLLBQ_N_U VSHLLTQ_N_U VSHLLTQ_N_S
88 VRMLALDAVHQ_U VRMLALDAVHQ_S VMULLTQ_POLY_P
89 VMULLBQ_POLY_P VBICQ_M_N_S VBICQ_M_N_U VCMPEQQ_M_F
90 VCVTAQ_M_S VCVTAQ_M_U VCVTQ_M_TO_F_S VCVTQ_M_TO_F_U
91 VQRSHRNBQ_N_U VQRSHRNBQ_N_S VQRSHRUNBQ_N_S
92 VRMLALDAVHAQ_S VABAVQ_S VABAVQ_U VSHLCQ_S VSHLCQ_U
93 VRMLALDAVHAQ_U VABSQ_M_S VADDVAQ_P_S VADDVAQ_P_U
94 VCLSQ_M_S VCLZQ_M_S VCLZQ_M_U VCMPCSQ_M_N_U
95 VCMPCSQ_M_U VCMPEQQ_M_N_S VCMPEQQ_M_N_U VCMPEQQ_M_S
96 VCMPEQQ_M_U VCMPGEQ_M_N_S VCMPGEQ_M_S VCMPGTQ_M_N_S
97 VCMPGTQ_M_S VCMPHIQ_M_N_U VCMPHIQ_M_U VCMPLEQ_M_N_S
98 VCMPLEQ_M_S VCMPLTQ_M_N_S VCMPLTQ_M_S VCMPNEQ_M_N_S
99 VCMPNEQ_M_N_U VCMPNEQ_M_S VCMPNEQ_M_U VDUPQ_M_N_S
100 VDUPQ_M_N_U VDWDUPQ_N_U VDWDUPQ_WB_U VIWDUPQ_N_U
101 VIWDUPQ_WB_U VMAXAQ_M_S VMAXAVQ_P_S VMAXVQ_P_S
102 VMAXVQ_P_U VMINAQ_M_S VMINAVQ_P_S VMINVQ_P_S VMINVQ_P_U
103 VMLADAVAQ_S VMLADAVAQ_U VMLADAVQ_P_S VMLADAVQ_P_U
104 VMLADAVXQ_P_S VMLAQ_N_S VMLAQ_N_U VMLASQ_N_S VMLASQ_N_U
105 VMLSDAVQ_P_S VMLSDAVXQ_P_S VMVNQ_M_S VMVNQ_M_U
106 VNEGQ_M_S VPSELQ_S VPSELQ_U VQABSQ_M_S VQDMLAHQ_N_S
107 VQDMLAHQ_N_U VQNEGQ_M_S VQRDMLADHQ_S VQRDMLADHXQ_S
108 VQRDMLAHQ_N_S VQRDMLAHQ_N_U VQRDMLASHQ_N_S
109 VQRDMLASHQ_N_U VQRDMLSDHQ_S VQRDMLSDHXQ_S VQRSHLQ_M_N_S
110 VQRSHLQ_M_N_U VQSHLQ_M_R_S VQSHLQ_M_R_U VREV64Q_M_S
111 VREV64Q_M_U VRSHLQ_M_N_S VRSHLQ_M_N_U VSHLQ_M_R_S
112 VSHLQ_M_R_U VSLIQ_N_S VSLIQ_N_U VSRIQ_N_S VSRIQ_N_U
113 VQDMLSDHXQ_S VQDMLSDHQ_S VQDMLADHXQ_S VQDMLADHQ_S
114 VMLSDAVAXQ_S VMLSDAVAQ_S VMLADAVAXQ_S
115 VCMPGEQ_M_F VCMPGTQ_M_N_F VMLSLDAVQ_P_S VRMLALDAVHAXQ_S
116 VMLSLDAVXQ_P_S VFMAQ_F VMLSLDAVAQ_S VQSHRUNBQ_N_S
117 VQRSHRUNTQ_N_S VCMLAQ_F VMINNMAQ_M_F VFMASQ_N_F
118 VDUPQ_M_N_F VCMPGTQ_M_F VCMPLTQ_M_F VRMLSLDAVHQ_P_S
119 VQSHRUNTQ_N_S VABSQ_M_F VMAXNMAVQ_P_F VFMAQ_N_F
120 VRMLSLDAVHXQ_P_S VREV32Q_M_F VRMLSLDAVHAQ_S
121 VRMLSLDAVHAXQ_S VCMPLTQ_M_N_F VCMPNEQ_M_F VRNDAQ_M_F
122 VRNDPQ_M_F VADDLVAQ_P_S VQMOVUNBQ_M_S VCMPLEQ_M_F
123 VCMLAQ_ROT180_F VMLSLDAVAXQ_S VRNDXQ_M_F VFMSQ_F
124 VMINNMVQ_P_F VMAXNMVQ_P_F VPSELQ_F VCMLAQ_ROT90_F
125 VQMOVUNTQ_M_S VREV64Q_M_F VNEGQ_M_F VRNDMQ_M_F
126 VCMPLEQ_M_N_F VCMPGEQ_M_N_F VRNDNQ_M_F VMINNMAVQ_P_F
127 VCMPNEQ_M_N_F VRMLALDAVHQ_P_S VRMLALDAVHXQ_P_S
128 VCMPEQQ_M_N_F VCMLAQ_ROT270_F VMAXNMAQ_M_F VRNDQ_M_F
129 VMLALDAVQ_P_U VMLALDAVQ_P_S VQMOVNBQ_M_S VQMOVNBQ_M_U
130 VMOVLTQ_M_U VMOVLTQ_M_S VMOVNBQ_M_U VMOVNBQ_M_S
131 VRSHRNTQ_N_U VRSHRNTQ_N_S VORRQ_M_N_S VORRQ_M_N_U
132 VREV32Q_M_S VREV32Q_M_U VQRSHRNTQ_N_U VQRSHRNTQ_N_S
133 VMOVNTQ_M_U VMOVNTQ_M_S VMOVLBQ_M_U VMOVLBQ_M_S
134 VMLALDAVAQ_S VMLALDAVAQ_U VQSHRNBQ_N_U VQSHRNBQ_N_S
135 VSHRNBQ_N_U VSHRNBQ_N_S VRSHRNBQ_N_S VRSHRNBQ_N_U
136 VMLALDAVXQ_P_U VMLALDAVXQ_P_S VQMOVNTQ_M_U VQMOVNTQ_M_S
137 VMVNQ_M_N_U VMVNQ_M_N_S VQSHRNTQ_N_U VQSHRNTQ_N_S
138 VMLALDAVAXQ_S VMLALDAVAXQ_U VSHRNTQ_N_S VSHRNTQ_N_U
139 VCVTBQ_M_F16_F32 VCVTBQ_M_F32_F16 VCVTTQ_M_F16_F32
140 VCVTTQ_M_F32_F16 VCVTMQ_M_S VCVTMQ_M_U VCVTNQ_M_S
141 VCVTPQ_M_S VCVTPQ_M_U VCVTQ_M_N_FROM_F_S VCVTNQ_M_U
142 VREV16Q_M_S VREV16Q_M_U VREV32Q_M VCVTQ_M_FROM_F_U
143 VCVTQ_M_FROM_F_S VRMLALDAVHQ_P_U VADDLVAQ_P_U
144 VCVTQ_M_N_FROM_F_U VQSHLUQ_M_N_S VABAVQ_P_S
145 VABAVQ_P_U VSHLQ_M_S VSHLQ_M_U VSRIQ_M_N_S
146 VSRIQ_M_N_U VSUBQ_M_U VSUBQ_M_S VCVTQ_M_N_TO_F_U
147 VCVTQ_M_N_TO_F_S VQADDQ_M_U VQADDQ_M_S
148 VRSHRQ_M_N_S VSUBQ_M_N_S VSUBQ_M_N_U VBRSRQ_M_N_S
149 VSUBQ_M_N_F VBICQ_M_F VHADDQ_M_U VBICQ_M_U VBICQ_M_S
150 VMULQ_M_N_U VHADDQ_M_S VORNQ_M_F VMLAQ_M_N_S VQSUBQ_M_U
151 VQSUBQ_M_S VMLAQ_M_N_U VQSUBQ_M_N_U VQSUBQ_M_N_S
152 VMULLTQ_INT_M_S VMULLTQ_INT_M_U VMULQ_M_N_S VMULQ_M_N_F
153 VMLASQ_M_N_U VMLASQ_M_N_S VMAXQ_M_U VQRDMLAHQ_M_N_U
154 VCADDQ_ROT270_M_F VCADDQ_ROT270_M_U VCADDQ_ROT270_M_S
155 VQRSHLQ_M_S VMULQ_M_F VRHADDQ_M_U VSHRQ_M_N_U
156 VRHADDQ_M_S VMULQ_M_S VMULQ_M_U VQRDMLASHQ_M_N_S
157 VRSHLQ_M_S VRSHLQ_M_U VRSHRQ_M_N_U VADDQ_M_N_F
158 VADDQ_M_N_S VADDQ_M_N_U VQRDMLASHQ_M_N_U VMAXQ_M_S
159 VQRDMLAHQ_M_N_S VORRQ_M_S VORRQ_M_U VORRQ_M_F
160 VQRSHLQ_M_U VRMULHQ_M_U VRMULHQ_M_S VMINQ_M_S VMINQ_M_U
161 VANDQ_M_F VANDQ_M_U VANDQ_M_S VHSUBQ_M_N_S VHSUBQ_M_N_U
162 VMULHQ_M_S VMULHQ_M_U VMULLBQ_INT_M_U
163 VMULLBQ_INT_M_S VCADDQ_ROT90_M_F
164 VSHRQ_M_N_S VADDQ_M_U VSLIQ_M_N_U
165 VQADDQ_M_N_S VBRSRQ_M_N_F VABDQ_M_F VBRSRQ_M_N_U
166 VEORQ_M_F VSHLQ_M_N_S VQDMLAHQ_M_N_U VQDMLAHQ_M_N_S
167 VSHLQ_M_N_U VMLADAVAQ_P_U VMLADAVAQ_P_S VSLIQ_M_N_S
168 VQSHLQ_M_U VQSHLQ_M_S VCADDQ_ROT90_M_U VCADDQ_ROT90_M_S
169 VORNQ_M_U VORNQ_M_S VQSHLQ_M_N_S VQSHLQ_M_N_U VADDQ_M_S
170 VHADDQ_M_N_S VADDQ_M_F VQADDQ_M_N_U VEORQ_M_S VEORQ_M_U
171 VHSUBQ_M_S VHSUBQ_M_U VHADDQ_M_N_U VHCADDQ_ROT90_M_S
172 VQRDMLSDHQ_M_S VQRDMLSDHXQ_M_S VQRDMLADHXQ_M_S
173 VQDMULHQ_M_S VMLADAVAXQ_P_S VQDMLADHXQ_M_S
174 VQRDMULHQ_M_S VMLSDAVAXQ_P_S VQDMULHQ_M_N_S
175 VHCADDQ_ROT270_M_S VQDMLSDHQ_M_S VQDMLSDHXQ_M_S
176 VMLSDAVAQ_P_S VQRDMLADHQ_M_S VQDMLADHQ_M_S
177 VMLALDAVAQ_P_U VMLALDAVAQ_P_S VMLALDAVAXQ_P_U
178 VQRSHRNBQ_M_N_U VQRSHRNBQ_M_N_S VQRSHRNTQ_M_N_S
179 VQSHRNBQ_M_N_U VQSHRNBQ_M_N_S VQSHRNTQ_M_N_S
180 VRSHRNBQ_M_N_U VRSHRNBQ_M_N_S VRSHRNTQ_M_N_U
181 VSHLLBQ_M_N_U VSHLLBQ_M_N_S VSHLLTQ_M_N_U VSHLLTQ_M_N_S
182 VSHRNBQ_M_N_S VSHRNBQ_M_N_U VSHRNTQ_M_N_S VSHRNTQ_M_N_U
183 VMLALDAVAXQ_P_S VQRSHRNTQ_M_N_U VQSHRNTQ_M_N_U
184 VRSHRNTQ_M_N_S VQRDMULHQ_M_N_S VRMLALDAVHAQ_P_S
185 VMLSLDAVAQ_P_S VMLSLDAVAXQ_P_S VMULLBQ_POLY_M_P
186 VMULLTQ_POLY_M_P VQDMULLBQ_M_N_S VQDMULLBQ_M_S
187 VQDMULLTQ_M_N_S VQDMULLTQ_M_S VQRSHRUNBQ_M_N_S
188 VQRSHRUNTQ_M_N_SVQSHRUNBQ_M_N_S VQSHRUNTQ_M_N_S
189 VRMLALDAVHAQ_P_U VRMLALDAVHAXQ_P_S VRMLSLDAVHAQ_P_S
190 VRMLSLDAVHAXQ_P_S VQRSHRUNTQ_M_N_S VQSHRUNBQ_M_N_S
191 VCMLAQ_M_F VCMLAQ_ROT180_M_F VCMLAQ_ROT270_M_F
192 VCMLAQ_ROT90_M_F VCMULQ_M_F VCMULQ_ROT180_M_F
193 VCMULQ_ROT270_M_F VCMULQ_ROT90_M_F VFMAQ_M_F
194 VFMAQ_M_N_F VFMASQ_M_N_F VFMSQ_M_F VMAXNMQ_M_F
195 VMINNMQ_M_F VSUBQ_M_F VSTRWQSB_S VSTRWQSB_U
196 VSTRBQSO_S VSTRBQSO_U VSTRBQ_S VSTRBQ_U VLDRBQGO_S
197 VLDRBQGO_U VLDRBQ_S VLDRBQ_U VLDRWQGB_S VLDRWQGB_U
198 VLD1Q_F VLD1Q_S VLD1Q_U VLDRHQ_F VLDRHQGO_S
199 VLDRHQGO_U VLDRHQGSO_S VLDRHQGSO_U VLDRHQ_S VLDRHQ_U
200 VLDRWQ_F VLDRWQ_S VLDRWQ_U VLDRDQGB_S VLDRDQGB_U
201 VLDRDQGO_S VLDRDQGO_U VLDRDQGSO_S VLDRDQGSO_U
202 VLDRHQGO_F VLDRHQGSO_F VLDRWQGB_F VLDRWQGO_F
203 VLDRWQGO_S VLDRWQGO_U VLDRWQGSO_F VLDRWQGSO_S
204 VLDRWQGSO_U VSTRHQ_F VST1Q_S VST1Q_U VSTRHQSO_S
205 VSTRHQSO_U VSTRHQSSO_S VSTRHQSSO_U VSTRHQ_S
206 VSTRHQ_U VSTRWQ_S VSTRWQ_U VSTRWQ_F VST1Q_F VSTRDQSB_S
207 VSTRDQSB_U VSTRDQSO_S VSTRDQSO_U VSTRDQSSO_S
208 VSTRDQSSO_U VSTRWQSO_S VSTRWQSO_U VSTRWQSSO_S
209 VSTRWQSSO_U VSTRHQSO_F VSTRHQSSO_F VSTRWQSB_F
210 VSTRWQSO_F VSTRWQSSO_F VDDUPQ VDDUPQ_M VDWDUPQ
211 VDWDUPQ_M VIDUPQ VIDUPQ_M VIWDUPQ VIWDUPQ_M
212 VSTRWQSBWB_S VSTRWQSBWB_U VLDRWQGBWB_S VLDRWQGBWB_U
213 VSTRWQSBWB_F VLDRWQGBWB_F VSTRDQSBWB_S VSTRDQSBWB_U
214 VLDRDQGBWB_S VLDRDQGBWB_U VADCQ_U VADCQ_M_U VADCQ_S
215 VADCQ_M_S VSBCIQ_U VSBCIQ_S VSBCIQ_M_U VSBCIQ_M_S
216 VSBCQ_U VSBCQ_S VSBCQ_M_U VSBCQ_M_S VADCIQ_U VADCIQ_M_U
217 VADCIQ_S VADCIQ_M_S VLD2Q VLD4Q VST2Q SRSHRL SRSHR
218 URSHR URSHRL SQRSHR UQRSHL UQRSHLL_64 VSHLCQ_M_U
219 UQRSHLL_48 SQRSHRL_64 SQRSHRL_48 VSHLCQ_M_S])
221 (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI")
224 (define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u") (VREV16Q_S "s")
225 (VREV16Q_U "u") (VMVNQ_N_S "s") (VMVNQ_N_U "u")
226 (VCVTAQ_U "u") (VCVTAQ_S "s") (VREV64Q_S "s")
227 (VREV64Q_U "u") (VMVNQ_S "s") (VMVNQ_U "u")
228 (VDUPQ_N_U "u") (VDUPQ_N_S"s") (VADDVQ_S "s")
229 (VADDVQ_U "u") (VADDVQ_S "s") (VADDVQ_U "u")
230 (VMOVLTQ_U "u") (VMOVLTQ_S "s") (VMOVLBQ_S "s")
231 (VMOVLBQ_U "u") (VCVTQ_FROM_F_S "s") (VCVTQ_FROM_F_U "u")
232 (VCVTPQ_S "s") (VCVTPQ_U "u") (VCVTNQ_S "s")
233 (VCVTNQ_U "u") (VCVTMQ_S "s") (VCVTMQ_U "u")
234 (VCLZQ_U "u") (VCLZQ_S "s") (VREV32Q_U "u")
235 (VREV32Q_S "s") (VADDLVQ_U "u") (VADDLVQ_S "s")
236 (VCVTQ_N_TO_F_S "s") (VCVTQ_N_TO_F_U "u")
237 (VCREATEQ_U "u") (VCREATEQ_S "s") (VSHRQ_N_S "s")
238 (VSHRQ_N_U "u") (VCVTQ_N_FROM_F_S "s") (VSHLQ_U "u")
239 (VCVTQ_N_FROM_F_U "u") (VADDLVQ_P_S "s") (VSHLQ_S "s")
240 (VADDLVQ_P_U "u") (VCMPNEQ_U "u") (VCMPNEQ_S "s")
241 (VABDQ_M_S "s") (VABDQ_M_U "u") (VABDQ_S "s")
242 (VABDQ_U "u") (VADDQ_N_S "s") (VADDQ_N_U "u")
243 (VADDVQ_P_S "s") (VADDVQ_P_U "u") (VANDQ_S "s")
244 (VANDQ_U "u") (VBICQ_S "s") (VBICQ_U "u")
245 (VBRSRQ_N_S "s") (VBRSRQ_N_U "u") (VCADDQ_ROT270_S "s")
246 (VCADDQ_ROT270_U "u") (VCADDQ_ROT90_S "s")
247 (VCMPEQQ_S "s") (VCMPEQQ_U "u") (VCADDQ_ROT90_U "u")
248 (VCMPEQQ_N_S "s") (VCMPEQQ_N_U "u") (VCMPNEQ_N_S "s")
249 (VCMPNEQ_N_U "u") (VEORQ_S "s") (VEORQ_U "u")
250 (VHADDQ_N_S "s") (VHADDQ_N_U "u") (VHADDQ_S "s")
251 (VHADDQ_U "u") (VHSUBQ_N_S "s") (VHSUBQ_N_U "u")
252 (VHSUBQ_S "s") (VMAXQ_S "s") (VMAXQ_U "u") (VHSUBQ_U "u")
253 (VMAXVQ_S "s") (VMAXVQ_U "u") (VMINQ_S "s") (VMINQ_U "u")
254 (VMINVQ_S "s") (VMINVQ_U "u") (VMLADAVQ_S "s")
255 (VMLADAVQ_U "u") (VMULHQ_S "s") (VMULHQ_U "u")
256 (VMULLBQ_INT_S "s") (VMULLBQ_INT_U "u") (VQADDQ_S "s")
257 (VMULLTQ_INT_S "s") (VMULLTQ_INT_U "u") (VQADDQ_U "u")
258 (VMULQ_N_S "s") (VMULQ_N_U "u") (VMULQ_S "s")
259 (VMULQ_U "u") (VORNQ_S "s") (VORNQ_U "u") (VORRQ_S "s")
260 (VORRQ_U "u") (VQADDQ_N_S "s") (VQADDQ_N_U "u")
261 (VQRSHLQ_N_S "s") (VQRSHLQ_N_U "u") (VQRSHLQ_S "s")
262 (VQRSHLQ_U "u") (VQSHLQ_N_S "s") (VQSHLQ_N_U "u")
263 (VQSHLQ_R_S "s") (VQSHLQ_R_U "u") (VQSHLQ_S "s")
264 (VQSHLQ_U "u") (VQSUBQ_N_S "s") (VQSUBQ_N_U "u")
265 (VQSUBQ_S "s") (VQSUBQ_U "u") (VRHADDQ_S "s")
266 (VRHADDQ_U "u") (VRMULHQ_S "s") (VRMULHQ_U "u")
267 (VRSHLQ_N_S "s") (VRSHLQ_N_U "u") (VRSHLQ_S "s")
268 (VRSHLQ_U "u") (VRSHRQ_N_S "s") (VRSHRQ_N_U "u")
269 (VSHLQ_N_S "s") (VSHLQ_N_U "u") (VSHLQ_R_S "s")
270 (VSHLQ_R_U "u") (VSUBQ_N_S "s") (VSUBQ_N_U "u")
271 (VSUBQ_S "s") (VSUBQ_U "u") (VADDVAQ_S "s")
272 (VADDVAQ_U "u") (VADDLVAQ_S "s") (VADDLVAQ_U "u")
273 (VBICQ_N_S "s") (VBICQ_N_U "u") (VMLALDAVQ_U "u")
274 (VMLALDAVQ_S "s") (VMLALDAVXQ_U "u") (VMLALDAVXQ_S "s")
275 (VMOVNBQ_U "u") (VMOVNBQ_S "s") (VMOVNTQ_U "u")
276 (VMOVNTQ_S "s") (VORRQ_N_S "s") (VORRQ_N_U "u")
277 (VQMOVNBQ_U "u") (VQMOVNBQ_S "s") (VQMOVNTQ_S "s")
278 (VQMOVNTQ_U "u") (VSHLLBQ_N_U "u") (VSHLLBQ_N_S "s")
279 (VSHLLTQ_N_U "u") (VSHLLTQ_N_S "s") (VRMLALDAVHQ_U "u")
280 (VRMLALDAVHQ_S "s") (VBICQ_M_N_S "s") (VBICQ_M_N_U "u")
281 (VCVTAQ_M_S "s") (VCVTAQ_M_U "u") (VCVTQ_M_TO_F_S "s")
282 (VCVTQ_M_TO_F_U "u") (VQRSHRNBQ_N_S "s")
283 (VQRSHRNBQ_N_U "u") (VABAVQ_S "s") (VABAVQ_U "u")
284 (VRMLALDAVHAQ_U "u") (VRMLALDAVHAQ_S "s") (VSHLCQ_S "s")
285 (VSHLCQ_U "u") (VADDVAQ_P_S "s") (VADDVAQ_P_U "u")
286 (VCLZQ_M_S "s") (VCLZQ_M_U "u") (VCMPEQQ_M_N_S "s")
287 (VCMPEQQ_M_N_U "u") (VCMPEQQ_M_S "s") (VCMPEQQ_M_U "u")
288 (VCMPNEQ_M_N_S "s") (VCMPNEQ_M_N_U "u") (VCMPNEQ_M_S "s")
289 (VCMPNEQ_M_U "u") (VDUPQ_M_N_S "s") (VDUPQ_M_N_U "u")
290 (VMAXVQ_P_S "s") (VMAXVQ_P_U "u") (VMINVQ_P_S "s")
291 (VMINVQ_P_U "u") (VMLADAVAQ_S "s") (VMLADAVAQ_U "u")
292 (VMLADAVQ_P_S "s") (VMLADAVQ_P_U "u") (VMLAQ_N_S "s")
293 (VMLAQ_N_U "u") (VMLASQ_N_S "s") (VMLASQ_N_U "u")
294 (VMVNQ_M_S "s") (VMVNQ_M_U "u") (VPSELQ_S "s")
295 (VPSELQ_U "u") (VQDMLAHQ_N_S "s") (VQDMLAHQ_N_U "u")
296 (VQRDMLAHQ_N_S "s") (VQRDMLAHQ_N_U "u")
297 (VQRDMLASHQ_N_S "s") (VQRDMLASHQ_N_U "u")
298 (VQRSHLQ_M_N_S "s") (VQRSHLQ_M_N_U "u")
299 (VQSHLQ_M_R_S "s") (VQSHLQ_M_R_U "u") (VSRIQ_N_S "s")
300 (VREV64Q_M_S "s") (VREV64Q_M_U "u") (VSRIQ_N_U "u")
301 (VRSHLQ_M_N_S "s") (VRSHLQ_M_N_U "u") (VSHLQ_M_R_S "s")
302 (VSHLQ_M_R_U "u") (VSLIQ_N_S "s") (VSLIQ_N_U "u")
303 (VMLALDAVQ_P_S "s") (VQMOVNBQ_M_S "s") (VMOVLTQ_M_S "s")
304 (VMOVNBQ_M_S "s") (VRSHRNTQ_N_S "s") (VORRQ_M_N_S "s")
305 (VREV32Q_M_S "s") (VQRSHRNTQ_N_S "s") (VMOVNTQ_M_S "s")
306 (VMOVLBQ_M_S "s") (VMLALDAVAQ_S "s") (VQSHRNBQ_N_S "s")
307 (VSHRNBQ_N_S "s") (VRSHRNBQ_N_S "s") (VMLALDAVXQ_P_S "s")
308 (VQMOVNTQ_M_S "s") (VMVNQ_M_N_S "s") (VQSHRNTQ_N_S "s")
309 (VMLALDAVAXQ_S "s") (VSHRNTQ_N_S "s") (VMLALDAVQ_P_U "u")
310 (VQMOVNBQ_M_U "u") (VMOVLTQ_M_U "u") (VMOVNBQ_M_U "u")
311 (VRSHRNTQ_N_U "u") (VORRQ_M_N_U "u") (VREV32Q_M_U "u")
312 (VREV16Q_M_S "s") (VREV16Q_M_U "u")
313 (VQRSHRNTQ_N_U "u") (VMOVNTQ_M_U "u") (VMOVLBQ_M_U "u")
314 (VMLALDAVAQ_U "u") (VQSHRNBQ_N_U "u") (VSHRNBQ_N_U "u")
315 (VRSHRNBQ_N_U "u") (VMLALDAVXQ_P_U "u")
316 (VMVNQ_M_N_U "u") (VQSHRNTQ_N_U "u") (VMLALDAVAXQ_U "u")
317 (VQMOVNTQ_M_U "u") (VSHRNTQ_N_U "u") (VCVTMQ_M_S "s")
318 (VCVTMQ_M_U "u") (VCVTNQ_M_S "s") (VCVTNQ_M_U "u")
319 (VCVTPQ_M_S "s") (VCVTPQ_M_U "u") (VADDLVAQ_P_S "s")
320 (VCVTQ_M_N_FROM_F_U "u") (VCVTQ_M_FROM_F_S "s")
321 (VCVTQ_M_FROM_F_U "u") (VRMLALDAVHQ_P_U "u")
322 (VRMLALDAVHQ_P_S "s") (VADDLVAQ_P_U "u")
323 (VCVTQ_M_N_FROM_F_S "s") (VABAVQ_P_U "u")
324 (VABAVQ_P_S "s") (VSHLQ_M_S "s") (VSHLQ_M_U "u")
325 (VSRIQ_M_N_S "s") (VSRIQ_M_N_U "u") (VSUBQ_M_S "s")
326 (VSUBQ_M_U "u") (VCVTQ_M_N_TO_F_S "s")
327 (VCVTQ_M_N_TO_F_U "u") (VADDQ_M_N_U "u")
328 (VSHLQ_M_N_S "s") (VMAXQ_M_U "u") (VHSUBQ_M_N_U "u")
329 (VMULQ_M_N_S "s") (VQSHLQ_M_U "u") (VRHADDQ_M_S "s")
330 (VEORQ_M_U "u") (VSHRQ_M_N_U "u") (VCADDQ_ROT90_M_U "u")
331 (VMLADAVAQ_P_U "u") (VEORQ_M_S "s") (VBRSRQ_M_N_S "s")
332 (VMULQ_M_U "u") (VQRDMLAHQ_M_N_S "s") (VHSUBQ_M_N_S "s")
333 (VQRSHLQ_M_S "s") (VMULQ_M_N_U "u")
334 (VMULQ_M_S "s") (VQSHLQ_M_N_U "u") (VSLIQ_M_N_U "u")
335 (VMLADAVAQ_P_S "s") (VQRSHLQ_M_U "u")
336 (VMULLBQ_INT_M_U "u") (VSHLQ_M_N_U "u") (VQSUBQ_M_U "u")
337 (VQRDMLASHQ_M_N_U "u") (VRSHRQ_M_N_S "s")
338 (VORNQ_M_S "s") (VCADDQ_ROT270_M_S "s") (VRHADDQ_M_U "u")
339 (VRSHRQ_M_N_U "u") (VMLASQ_M_N_U "u") (VHSUBQ_M_U "u")
340 (VQSUBQ_M_N_S "s") (VMULLTQ_INT_M_S "s")
341 (VORRQ_M_S "s") (VQDMLAHQ_M_N_U "u") (VRSHLQ_M_S "s")
342 (VHADDQ_M_U "u") (VHADDQ_M_N_S "s") (VMULLTQ_INT_M_U "u")
343 (VORRQ_M_U "u") (VHADDQ_M_S "s") (VHADDQ_M_N_U "u")
344 (VQDMLAHQ_M_N_S "s") (VMAXQ_M_S "s") (VORNQ_M_U "u")
345 (VCADDQ_ROT270_M_U "u") (VQADDQ_M_U "u")
346 (VQRDMLASHQ_M_N_S "s") (VBICQ_M_U "u") (VMINQ_M_U "u")
347 (VSUBQ_M_N_S "s") (VMULLBQ_INT_M_S "s") (VQSUBQ_M_S "s")
348 (VCADDQ_ROT90_M_S "s") (VRMULHQ_M_S "s") (VANDQ_M_U "u")
349 (VMULHQ_M_S "s") (VADDQ_M_S "s") (VQRDMLAHQ_M_N_U "u")
350 (VMLASQ_M_N_S "s") (VHSUBQ_M_S "s") (VRMULHQ_M_U "u")
351 (VQADDQ_M_N_S "s") (VSHRQ_M_N_S "s") (VANDQ_M_S "s")
352 (VABDQ_M_U "u") (VQSHLQ_M_S "s") (VABDQ_M_S "s")
353 (VSUBQ_M_N_U "u") (VMLAQ_M_N_S "s") (VBRSRQ_M_N_U "u")
354 (VADDQ_M_U "u") (VRSHLQ_M_U "u") (VSLIQ_M_N_S "s")
355 (VQADDQ_M_N_U "u") (VADDQ_M_N_S "s") (VQSUBQ_M_N_U "u")
356 (VMLAQ_M_N_U "u") (VMINQ_M_S "s") (VMULHQ_M_U "u")
357 (VQADDQ_M_S "s") (VBICQ_M_S "s") (VQSHLQ_M_N_S "s")
358 (VQSHRNTQ_M_N_S "s") (VQSHRNTQ_M_N_U "u")
359 (VSHRNTQ_M_N_U "u") (VSHRNTQ_M_N_S "s")
360 (VSHRNBQ_M_N_S "s") (VSHRNBQ_M_N_U "u")
361 (VSHLLTQ_M_N_S "s") (VSHLLTQ_M_N_U "u")
362 (VSHLLBQ_M_N_S "s") (VSHLLBQ_M_N_U "u")
363 (VRSHRNTQ_M_N_S "s") (VRSHRNTQ_M_N_U "u")
364 (VRSHRNBQ_M_N_U "u") (VRSHRNBQ_M_N_S "s")
365 (VQSHRNTQ_M_N_U "u") (VQSHRNTQ_M_N_S "s")
366 (VQSHRNBQ_M_N_S "s") (VQSHRNBQ_M_N_U "u")
367 (VQRSHRNTQ_M_N_S "s") (VQRSHRNTQ_M_N_U "u")
368 (VQRSHRNBQ_M_N_S "s") (VQRSHRNBQ_M_N_U "u")
369 (VMLALDAVAXQ_P_S "s") (VMLALDAVAXQ_P_U "u")
370 (VMLALDAVAQ_P_S "s") (VMLALDAVAQ_P_U "u")
371 (VSTRWQSB_S "s") (VSTRWQSB_U "u") (VSTRBQSO_S "s")
372 (VSTRBQSO_U "u") (VSTRBQ_S "s") (VSTRBQ_U "u")
373 (VLDRBQGO_S "s") (VLDRBQGO_U "u") (VLDRBQ_S "s")
374 (VLDRBQ_U "u") (VLDRWQGB_S "s") (VLDRWQGB_U "u")
375 (VLD1Q_S "s") (VLD1Q_U "u") (VLDRHQGO_S "s")
376 (VLDRHQGO_U "u") (VLDRHQGSO_S "s") (VLDRHQGSO_U "u")
377 (VLDRHQ_S "s") (VLDRHQ_U "u") (VLDRWQ_S "s")
378 (VLDRWQ_U "u") (VLDRDQGB_S "s") (VLDRDQGB_U "u")
379 (VLDRDQGO_S "s") (VLDRDQGO_U "u") (VLDRDQGSO_S "s")
380 (VLDRDQGSO_U "u") (VLDRWQGO_S "s") (VLDRWQGO_U "u")
381 (VLDRWQGSO_S "s") (VLDRWQGSO_U "u") (VST1Q_S "s")
382 (VST1Q_U "u") (VSTRHQSO_S "s") (VSTRHQSO_U "u")
383 (VSTRHQSSO_S "s") (VSTRHQSSO_U "u") (VSTRHQ_S "s")
384 (VSTRHQ_U "u") (VSTRWQ_S "s") (VSTRWQ_U "u")
385 (VSTRDQSB_S "s") (VSTRDQSB_U "u") (VSTRDQSO_S "s")
386 (VSTRDQSO_U "u") (VSTRDQSSO_S "s") (VSTRDQSSO_U "u")
387 (VSTRWQSO_U "u") (VSTRWQSO_S "s") (VSTRWQSSO_U "u")
388 (VSTRWQSSO_S "s") (VSTRWQSBWB_S "s") (VSTRWQSBWB_U "u")
389 (VLDRWQGBWB_S "s") (VLDRWQGBWB_U "u") (VLDRDQGBWB_S "s")
390 (VLDRDQGBWB_U "u") (VSTRDQSBWB_S "s") (VADCQ_M_S "s")
391 (VSTRDQSBWB_U "u") (VSBCQ_U "u") (VSBCQ_M_U "u")
392 (VSBCQ_S "s") (VSBCQ_M_S "s") (VSBCIQ_U "u")
393 (VSBCIQ_M_U "u") (VSBCIQ_S "s") (VSBCIQ_M_S "s")
394 (VADCQ_U "u") (VADCQ_M_U "u") (VADCQ_S "s")
395 (VADCIQ_U "u") (VADCIQ_M_U "u") (VADCIQ_S "s")
396 (VADCIQ_M_S "s") (SQRSHRL_64 "64") (SQRSHRL_48 "48")
397 (UQRSHLL_64 "64") (UQRSHLL_48 "48") (VSHLCQ_M_S "s")
400 (define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32")
401 (VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16")
402 (VCTP32Q_M "32") (VCTP64Q_M "64")])
403 (define_mode_attr MVE_pred2 [(V16QI "mve_imm_8") (V8HI "mve_imm_16")
404 (V4SI "mve_imm_32")])
405 (define_mode_attr MVE_constraint2 [(V16QI "Rb") (V8HI "Rd") (V4SI "Rf")])
406 (define_mode_attr MVE_LANES [(V16QI "16") (V8HI "8") (V4SI "4")])
407 (define_mode_attr MVE_constraint [ (V16QI "Ra") (V8HI "Rc") (V4SI "Re")])
408 (define_mode_attr MVE_pred [ (V16QI "mve_imm_7") (V8HI "mve_imm_15")
409 (V4SI "mve_imm_31")])
410 (define_mode_attr MVE_constraint3 [ (V8HI "Rb") (V4SI "Rd")])
411 (define_mode_attr MVE_pred3 [ (V8HI "mve_imm_8") (V4SI "mve_imm_16")])
412 (define_mode_attr MVE_constraint1 [ (V8HI "Ra") (V4SI "Rc")])
413 (define_mode_attr MVE_pred1 [ (V8HI "mve_imm_7") (V4SI "mve_imm_15")])
414 (define_mode_attr MVE_B_ELEM [ (V16QI "V16QI") (V8HI "V8QI") (V4SI "V4QI")])
415 (define_mode_attr MVE_H_ELEM [ (V8HI "V8HI") (V4SI "V4HI")])
416 (define_mode_attr V_sz_elem1 [(V16QI "b") (V8HI "h") (V4SI "w") (V8HF "h")
418 (define_mode_attr V_extr_elem [(V16QI "u8") (V8HI "u16") (V4SI "32")
419 (V8HF "u16") (V4SF "32")])
421 (define_mode_attr earlyclobber_32 [(V16QI "=w") (V8HI "=w") (V4SI "=&w")
422 (V8HF "=w") (V4SF "=&w")])
424 (define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U])
425 (define_int_iterator VMVNQ_N [VMVNQ_N_U VMVNQ_N_S])
426 (define_int_iterator VREV64Q [VREV64Q_S VREV64Q_U])
427 (define_int_iterator VCVTQ_FROM_F [VCVTQ_FROM_F_S VCVTQ_FROM_F_U])
428 (define_int_iterator VREV16Q [VREV16Q_U VREV16Q_S])
429 (define_int_iterator VCVTAQ [VCVTAQ_U VCVTAQ_S])
430 (define_int_iterator VMVNQ [VMVNQ_U VMVNQ_S])
431 (define_int_iterator VDUPQ_N [VDUPQ_N_U VDUPQ_N_S])
432 (define_int_iterator VCLZQ [VCLZQ_U VCLZQ_S])
433 (define_int_iterator VADDVQ [VADDVQ_U VADDVQ_S])
434 (define_int_iterator VREV32Q [VREV32Q_U VREV32Q_S])
435 (define_int_iterator VMOVLBQ [VMOVLBQ_S VMOVLBQ_U])
436 (define_int_iterator VMOVLTQ [VMOVLTQ_U VMOVLTQ_S])
437 (define_int_iterator VCVTPQ [VCVTPQ_S VCVTPQ_U])
438 (define_int_iterator VCVTNQ [VCVTNQ_S VCVTNQ_U])
439 (define_int_iterator VCVTMQ [VCVTMQ_S VCVTMQ_U])
440 (define_int_iterator VADDLVQ [VADDLVQ_U VADDLVQ_S])
441 (define_int_iterator VCTPQ [VCTP8Q VCTP16Q VCTP32Q VCTP64Q])
442 (define_int_iterator VCTPQ_M [VCTP8Q_M VCTP16Q_M VCTP32Q_M VCTP64Q_M])
443 (define_int_iterator VCVTQ_N_TO_F [VCVTQ_N_TO_F_S VCVTQ_N_TO_F_U])
444 (define_int_iterator VCREATEQ [VCREATEQ_U VCREATEQ_S])
445 (define_int_iterator VSHRQ_N [VSHRQ_N_S VSHRQ_N_U])
446 (define_int_iterator VCVTQ_N_FROM_F [VCVTQ_N_FROM_F_S VCVTQ_N_FROM_F_U])
447 (define_int_iterator VADDLVQ_P [VADDLVQ_P_S VADDLVQ_P_U])
448 (define_int_iterator VCMPNEQ [VCMPNEQ_U VCMPNEQ_S])
449 (define_int_iterator VSHLQ [VSHLQ_S VSHLQ_U])
450 (define_int_iterator VABDQ [VABDQ_S VABDQ_U])
451 (define_int_iterator VADDQ_N [VADDQ_N_S VADDQ_N_U])
452 (define_int_iterator VADDVAQ [VADDVAQ_S VADDVAQ_U])
453 (define_int_iterator VADDVQ_P [VADDVQ_P_U VADDVQ_P_S])
454 (define_int_iterator VANDQ [VANDQ_U VANDQ_S])
455 (define_int_iterator VBICQ [VBICQ_S VBICQ_U])
456 (define_int_iterator VBRSRQ_N [VBRSRQ_N_U VBRSRQ_N_S])
457 (define_int_iterator VCADDQ_ROT270 [VCADDQ_ROT270_S VCADDQ_ROT270_U])
458 (define_int_iterator VCADDQ_ROT90 [VCADDQ_ROT90_U VCADDQ_ROT90_S])
459 (define_int_iterator VCMPEQQ [VCMPEQQ_U VCMPEQQ_S])
460 (define_int_iterator VCMPEQQ_N [VCMPEQQ_N_S VCMPEQQ_N_U])
461 (define_int_iterator VCMPNEQ_N [VCMPNEQ_N_U VCMPNEQ_N_S])
462 (define_int_iterator VEORQ [VEORQ_U VEORQ_S])
463 (define_int_iterator VHADDQ [VHADDQ_S VHADDQ_U])
464 (define_int_iterator VHADDQ_N [VHADDQ_N_U VHADDQ_N_S])
465 (define_int_iterator VHSUBQ [VHSUBQ_S VHSUBQ_U])
466 (define_int_iterator VHSUBQ_N [VHSUBQ_N_U VHSUBQ_N_S])
467 (define_int_iterator VMAXQ [VMAXQ_U VMAXQ_S])
468 (define_int_iterator VMAXVQ [VMAXVQ_U VMAXVQ_S])
469 (define_int_iterator VMINQ [VMINQ_S VMINQ_U])
470 (define_int_iterator VMINVQ [VMINVQ_U VMINVQ_S])
471 (define_int_iterator VMLADAVQ [VMLADAVQ_U VMLADAVQ_S])
472 (define_int_iterator VMULHQ [VMULHQ_S VMULHQ_U])
473 (define_int_iterator VMULLBQ_INT [VMULLBQ_INT_U VMULLBQ_INT_S])
474 (define_int_iterator VMULLTQ_INT [VMULLTQ_INT_U VMULLTQ_INT_S])
475 (define_int_iterator VMULQ [VMULQ_U VMULQ_S])
476 (define_int_iterator VMULQ_N [VMULQ_N_U VMULQ_N_S])
477 (define_int_iterator VORNQ [VORNQ_U VORNQ_S])
478 (define_int_iterator VORRQ [VORRQ_S VORRQ_U])
479 (define_int_iterator VQADDQ [VQADDQ_U VQADDQ_S])
480 (define_int_iterator VQADDQ_N [VQADDQ_N_S VQADDQ_N_U])
481 (define_int_iterator VQRSHLQ [VQRSHLQ_S VQRSHLQ_U])
482 (define_int_iterator VQRSHLQ_N [VQRSHLQ_N_S VQRSHLQ_N_U])
483 (define_int_iterator VQSHLQ [VQSHLQ_S VQSHLQ_U])
484 (define_int_iterator VQSHLQ_N [VQSHLQ_N_S VQSHLQ_N_U])
485 (define_int_iterator VQSHLQ_R [VQSHLQ_R_U VQSHLQ_R_S])
486 (define_int_iterator VQSUBQ [VQSUBQ_U VQSUBQ_S])
487 (define_int_iterator VQSUBQ_N [VQSUBQ_N_S VQSUBQ_N_U])
488 (define_int_iterator VRHADDQ [VRHADDQ_S VRHADDQ_U])
489 (define_int_iterator VRMULHQ [VRMULHQ_S VRMULHQ_U])
490 (define_int_iterator VRSHLQ [VRSHLQ_S VRSHLQ_U])
491 (define_int_iterator VRSHLQ_N [VRSHLQ_N_U VRSHLQ_N_S])
492 (define_int_iterator VRSHRQ_N [VRSHRQ_N_S VRSHRQ_N_U])
493 (define_int_iterator VSHLQ_N [VSHLQ_N_U VSHLQ_N_S])
494 (define_int_iterator VSHLQ_R [VSHLQ_R_S VSHLQ_R_U])
495 (define_int_iterator VSUBQ [VSUBQ_S VSUBQ_U])
496 (define_int_iterator VSUBQ_N [VSUBQ_N_S VSUBQ_N_U])
497 (define_int_iterator VADDLVAQ [VADDLVAQ_S VADDLVAQ_U])
498 (define_int_iterator VBICQ_N [VBICQ_N_S VBICQ_N_U])
499 (define_int_iterator VMLALDAVQ [VMLALDAVQ_U VMLALDAVQ_S])
500 (define_int_iterator VMLALDAVXQ [VMLALDAVXQ_U VMLALDAVXQ_S])
501 (define_int_iterator VMOVNBQ [VMOVNBQ_U VMOVNBQ_S])
502 (define_int_iterator VMOVNTQ [VMOVNTQ_S VMOVNTQ_U])
503 (define_int_iterator VORRQ_N [VORRQ_N_U VORRQ_N_S])
504 (define_int_iterator VQMOVNBQ [VQMOVNBQ_U VQMOVNBQ_S])
505 (define_int_iterator VQMOVNTQ [VQMOVNTQ_U VQMOVNTQ_S])
506 (define_int_iterator VSHLLBQ_N [VSHLLBQ_N_S VSHLLBQ_N_U])
507 (define_int_iterator VSHLLTQ_N [VSHLLTQ_N_U VSHLLTQ_N_S])
508 (define_int_iterator VRMLALDAVHQ [VRMLALDAVHQ_U VRMLALDAVHQ_S])
509 (define_int_iterator VBICQ_M_N [VBICQ_M_N_S VBICQ_M_N_U])
510 (define_int_iterator VCVTAQ_M [VCVTAQ_M_S VCVTAQ_M_U])
511 (define_int_iterator VCVTQ_M_TO_F [VCVTQ_M_TO_F_S VCVTQ_M_TO_F_U])
512 (define_int_iterator VQRSHRNBQ_N [VQRSHRNBQ_N_U VQRSHRNBQ_N_S])
513 (define_int_iterator VABAVQ [VABAVQ_S VABAVQ_U])
514 (define_int_iterator VSHLCQ [VSHLCQ_S VSHLCQ_U])
515 (define_int_iterator VRMLALDAVHAQ [VRMLALDAVHAQ_S VRMLALDAVHAQ_U])
516 (define_int_iterator VADDVAQ_P [VADDVAQ_P_S VADDVAQ_P_U])
517 (define_int_iterator VCLZQ_M [VCLZQ_M_S VCLZQ_M_U])
518 (define_int_iterator VCMPEQQ_M_N [VCMPEQQ_M_N_S VCMPEQQ_M_N_U])
519 (define_int_iterator VCMPEQQ_M [VCMPEQQ_M_S VCMPEQQ_M_U])
520 (define_int_iterator VCMPNEQ_M_N [VCMPNEQ_M_N_S VCMPNEQ_M_N_U])
521 (define_int_iterator VCMPNEQ_M [VCMPNEQ_M_S VCMPNEQ_M_U])
522 (define_int_iterator VDUPQ_M_N [VDUPQ_M_N_S VDUPQ_M_N_U])
523 (define_int_iterator VMAXVQ_P [VMAXVQ_P_S VMAXVQ_P_U])
524 (define_int_iterator VMINVQ_P [VMINVQ_P_S VMINVQ_P_U])
525 (define_int_iterator VMLADAVAQ [VMLADAVAQ_S VMLADAVAQ_U])
526 (define_int_iterator VMLADAVQ_P [VMLADAVQ_P_S VMLADAVQ_P_U])
527 (define_int_iterator VMLAQ_N [VMLAQ_N_S VMLAQ_N_U])
528 (define_int_iterator VMLASQ_N [VMLASQ_N_S VMLASQ_N_U])
529 (define_int_iterator VMVNQ_M [VMVNQ_M_S VMVNQ_M_U])
530 (define_int_iterator VPSELQ [VPSELQ_S VPSELQ_U])
531 (define_int_iterator VQDMLAHQ_N [VQDMLAHQ_N_S VQDMLAHQ_N_U])
532 (define_int_iterator VQRDMLAHQ_N [VQRDMLAHQ_N_S VQRDMLAHQ_N_U])
533 (define_int_iterator VQRDMLASHQ_N [VQRDMLASHQ_N_S VQRDMLASHQ_N_U])
534 (define_int_iterator VQRSHLQ_M_N [VQRSHLQ_M_N_S VQRSHLQ_M_N_U])
535 (define_int_iterator VQSHLQ_M_R [VQSHLQ_M_R_S VQSHLQ_M_R_U])
536 (define_int_iterator VREV64Q_M [VREV64Q_M_S VREV64Q_M_U])
537 (define_int_iterator VRSHLQ_M_N [VRSHLQ_M_N_S VRSHLQ_M_N_U])
538 (define_int_iterator VSHLQ_M_R [VSHLQ_M_R_S VSHLQ_M_R_U])
539 (define_int_iterator VSLIQ_N [VSLIQ_N_S VSLIQ_N_U])
540 (define_int_iterator VSRIQ_N [VSRIQ_N_S VSRIQ_N_U])
541 (define_int_iterator VMLALDAVQ_P [VMLALDAVQ_P_U VMLALDAVQ_P_S])
542 (define_int_iterator VQMOVNBQ_M [VQMOVNBQ_M_S VQMOVNBQ_M_U])
543 (define_int_iterator VMOVLTQ_M [VMOVLTQ_M_U VMOVLTQ_M_S])
544 (define_int_iterator VMOVNBQ_M [VMOVNBQ_M_U VMOVNBQ_M_S])
545 (define_int_iterator VRSHRNTQ_N [VRSHRNTQ_N_U VRSHRNTQ_N_S])
546 (define_int_iterator VORRQ_M_N [VORRQ_M_N_S VORRQ_M_N_U])
547 (define_int_iterator VREV32Q_M [VREV32Q_M_S VREV32Q_M_U])
548 (define_int_iterator VREV16Q_M [VREV16Q_M_S VREV16Q_M_U])
549 (define_int_iterator VQRSHRNTQ_N [VQRSHRNTQ_N_U VQRSHRNTQ_N_S])
550 (define_int_iterator VMOVNTQ_M [VMOVNTQ_M_U VMOVNTQ_M_S])
551 (define_int_iterator VMOVLBQ_M [VMOVLBQ_M_U VMOVLBQ_M_S])
552 (define_int_iterator VMLALDAVAQ [VMLALDAVAQ_S VMLALDAVAQ_U])
553 (define_int_iterator VQSHRNBQ_N [VQSHRNBQ_N_U VQSHRNBQ_N_S])
554 (define_int_iterator VSHRNBQ_N [VSHRNBQ_N_U VSHRNBQ_N_S])
555 (define_int_iterator VRSHRNBQ_N [VRSHRNBQ_N_S VRSHRNBQ_N_U])
556 (define_int_iterator VMLALDAVXQ_P [VMLALDAVXQ_P_U VMLALDAVXQ_P_S])
557 (define_int_iterator VQMOVNTQ_M [VQMOVNTQ_M_U VQMOVNTQ_M_S])
558 (define_int_iterator VMVNQ_M_N [VMVNQ_M_N_U VMVNQ_M_N_S])
559 (define_int_iterator VQSHRNTQ_N [VQSHRNTQ_N_U VQSHRNTQ_N_S])
560 (define_int_iterator VMLALDAVAXQ [VMLALDAVAXQ_S VMLALDAVAXQ_U])
561 (define_int_iterator VSHRNTQ_N [VSHRNTQ_N_S VSHRNTQ_N_U])
562 (define_int_iterator VCVTMQ_M [VCVTMQ_M_S VCVTMQ_M_U])
563 (define_int_iterator VCVTNQ_M [VCVTNQ_M_S VCVTNQ_M_U])
564 (define_int_iterator VCVTPQ_M [VCVTPQ_M_S VCVTPQ_M_U])
565 (define_int_iterator VCVTQ_M_N_FROM_F [VCVTQ_M_N_FROM_F_S VCVTQ_M_N_FROM_F_U])
566 (define_int_iterator VCVTQ_M_FROM_F [VCVTQ_M_FROM_F_U VCVTQ_M_FROM_F_S])
567 (define_int_iterator VRMLALDAVHQ_P [VRMLALDAVHQ_P_S VRMLALDAVHQ_P_U])
568 (define_int_iterator VADDLVAQ_P [VADDLVAQ_P_U VADDLVAQ_P_S])
569 (define_int_iterator VABAVQ_P [VABAVQ_P_S VABAVQ_P_U])
570 (define_int_iterator VSHLQ_M [VSHLQ_M_S VSHLQ_M_U])
571 (define_int_iterator VSRIQ_M_N [VSRIQ_M_N_S VSRIQ_M_N_U])
572 (define_int_iterator VSUBQ_M [VSUBQ_M_U VSUBQ_M_S])
573 (define_int_iterator VCVTQ_M_N_TO_F [VCVTQ_M_N_TO_F_U VCVTQ_M_N_TO_F_S])
574 (define_int_iterator VHSUBQ_M [VHSUBQ_M_S VHSUBQ_M_U])
575 (define_int_iterator VSLIQ_M_N [VSLIQ_M_N_U VSLIQ_M_N_S])
576 (define_int_iterator VRSHLQ_M [VRSHLQ_M_S VRSHLQ_M_U])
577 (define_int_iterator VMINQ_M [VMINQ_M_S VMINQ_M_U])
578 (define_int_iterator VMULLBQ_INT_M [VMULLBQ_INT_M_U VMULLBQ_INT_M_S])
579 (define_int_iterator VMULHQ_M [VMULHQ_M_S VMULHQ_M_U])
580 (define_int_iterator VMULQ_M [VMULQ_M_S VMULQ_M_U])
581 (define_int_iterator VHSUBQ_M_N [VHSUBQ_M_N_S VHSUBQ_M_N_U])
582 (define_int_iterator VHADDQ_M_N [VHADDQ_M_N_S VHADDQ_M_N_U])
583 (define_int_iterator VORRQ_M [VORRQ_M_S VORRQ_M_U])
584 (define_int_iterator VRMULHQ_M [VRMULHQ_M_U VRMULHQ_M_S])
585 (define_int_iterator VQADDQ_M [VQADDQ_M_U VQADDQ_M_S])
586 (define_int_iterator VRSHRQ_M_N [VRSHRQ_M_N_S VRSHRQ_M_N_U])
587 (define_int_iterator VQSUBQ_M_N [VQSUBQ_M_N_U VQSUBQ_M_N_S])
588 (define_int_iterator VADDQ_M [VADDQ_M_U VADDQ_M_S])
589 (define_int_iterator VORNQ_M [VORNQ_M_U VORNQ_M_S])
590 (define_int_iterator VRHADDQ_M [VRHADDQ_M_U VRHADDQ_M_S])
591 (define_int_iterator VQSHLQ_M [VQSHLQ_M_U VQSHLQ_M_S])
592 (define_int_iterator VANDQ_M [VANDQ_M_U VANDQ_M_S])
593 (define_int_iterator VBICQ_M [VBICQ_M_U VBICQ_M_S])
594 (define_int_iterator VSHLQ_M_N [VSHLQ_M_N_S VSHLQ_M_N_U])
595 (define_int_iterator VCADDQ_ROT270_M [VCADDQ_ROT270_M_U VCADDQ_ROT270_M_S])
596 (define_int_iterator VQRSHLQ_M [VQRSHLQ_M_U VQRSHLQ_M_S])
597 (define_int_iterator VQADDQ_M_N [VQADDQ_M_N_U VQADDQ_M_N_S])
598 (define_int_iterator VADDQ_M_N [VADDQ_M_N_S VADDQ_M_N_U])
599 (define_int_iterator VMAXQ_M [VMAXQ_M_S VMAXQ_M_U])
600 (define_int_iterator VQSUBQ_M [VQSUBQ_M_U VQSUBQ_M_S])
601 (define_int_iterator VMLASQ_M_N [VMLASQ_M_N_U VMLASQ_M_N_S])
602 (define_int_iterator VMLADAVAQ_P [VMLADAVAQ_P_U VMLADAVAQ_P_S])
603 (define_int_iterator VBRSRQ_M_N [VBRSRQ_M_N_U VBRSRQ_M_N_S])
604 (define_int_iterator VMULQ_M_N [VMULQ_M_N_U VMULQ_M_N_S])
605 (define_int_iterator VCADDQ_ROT90_M [VCADDQ_ROT90_M_U VCADDQ_ROT90_M_S])
606 (define_int_iterator VMULLTQ_INT_M [VMULLTQ_INT_M_S VMULLTQ_INT_M_U])
607 (define_int_iterator VEORQ_M [VEORQ_M_S VEORQ_M_U])
608 (define_int_iterator VSHRQ_M_N [VSHRQ_M_N_S VSHRQ_M_N_U])
609 (define_int_iterator VSUBQ_M_N [VSUBQ_M_N_S VSUBQ_M_N_U])
610 (define_int_iterator VHADDQ_M [VHADDQ_M_S VHADDQ_M_U])
611 (define_int_iterator VABDQ_M [VABDQ_M_S VABDQ_M_U])
612 (define_int_iterator VMLAQ_M_N [VMLAQ_M_N_S VMLAQ_M_N_U])
613 (define_int_iterator VQSHLQ_M_N [VQSHLQ_M_N_S VQSHLQ_M_N_U])
614 (define_int_iterator VMLALDAVAQ_P [VMLALDAVAQ_P_U VMLALDAVAQ_P_S])
615 (define_int_iterator VMLALDAVAXQ_P [VMLALDAVAXQ_P_U VMLALDAVAXQ_P_S])
616 (define_int_iterator VQRSHRNBQ_M_N [VQRSHRNBQ_M_N_U VQRSHRNBQ_M_N_S])
617 (define_int_iterator VQRSHRNTQ_M_N [VQRSHRNTQ_M_N_S VQRSHRNTQ_M_N_U])
618 (define_int_iterator VQSHRNBQ_M_N [VQSHRNBQ_M_N_U VQSHRNBQ_M_N_S])
619 (define_int_iterator VQSHRNTQ_M_N [VQSHRNTQ_M_N_S VQSHRNTQ_M_N_U])
620 (define_int_iterator VRSHRNBQ_M_N [VRSHRNBQ_M_N_U VRSHRNBQ_M_N_S])
621 (define_int_iterator VRSHRNTQ_M_N [VRSHRNTQ_M_N_U VRSHRNTQ_M_N_S])
622 (define_int_iterator VSHLLBQ_M_N [VSHLLBQ_M_N_U VSHLLBQ_M_N_S])
623 (define_int_iterator VSHLLTQ_M_N [VSHLLTQ_M_N_U VSHLLTQ_M_N_S])
624 (define_int_iterator VSHRNBQ_M_N [VSHRNBQ_M_N_S VSHRNBQ_M_N_U])
625 (define_int_iterator VSHRNTQ_M_N [VSHRNTQ_M_N_S VSHRNTQ_M_N_U])
626 (define_int_iterator VSTRWSBQ [VSTRWQSB_S VSTRWQSB_U])
627 (define_int_iterator VSTRBSOQ [VSTRBQSO_S VSTRBQSO_U])
628 (define_int_iterator VSTRBQ [VSTRBQ_S VSTRBQ_U])
629 (define_int_iterator VLDRBGOQ [VLDRBQGO_S VLDRBQGO_U])
630 (define_int_iterator VLDRBQ [VLDRBQ_S VLDRBQ_U])
631 (define_int_iterator VLDRWGBQ [VLDRWQGB_S VLDRWQGB_U])
632 (define_int_iterator VLD1Q [VLD1Q_S VLD1Q_U])
633 (define_int_iterator VLDRHGOQ [VLDRHQGO_S VLDRHQGO_U])
634 (define_int_iterator VLDRHGSOQ [VLDRHQGSO_S VLDRHQGSO_U])
635 (define_int_iterator VLDRHQ [VLDRHQ_S VLDRHQ_U])
636 (define_int_iterator VLDRWQ [VLDRWQ_S VLDRWQ_U])
637 (define_int_iterator VLDRDGBQ [VLDRDQGB_S VLDRDQGB_U])
638 (define_int_iterator VLDRDGOQ [VLDRDQGO_S VLDRDQGO_U])
639 (define_int_iterator VLDRDGSOQ [VLDRDQGSO_S VLDRDQGSO_U])
640 (define_int_iterator VLDRWGOQ [VLDRWQGO_S VLDRWQGO_U])
641 (define_int_iterator VLDRWGSOQ [VLDRWQGSO_S VLDRWQGSO_U])
642 (define_int_iterator VST1Q [VST1Q_S VST1Q_U])
643 (define_int_iterator VSTRHSOQ [VSTRHQSO_S VSTRHQSO_U])
644 (define_int_iterator VSTRHSSOQ [VSTRHQSSO_S VSTRHQSSO_U])
645 (define_int_iterator VSTRHQ [VSTRHQ_S VSTRHQ_U])
646 (define_int_iterator VSTRWQ [VSTRWQ_S VSTRWQ_U])
647 (define_int_iterator VSTRDSBQ [VSTRDQSB_S VSTRDQSB_U])
648 (define_int_iterator VSTRDSOQ [VSTRDQSO_S VSTRDQSO_U])
649 (define_int_iterator VSTRDSSOQ [VSTRDQSSO_S VSTRDQSSO_U])
650 (define_int_iterator VSTRWSOQ [VSTRWQSO_S VSTRWQSO_U])
651 (define_int_iterator VSTRWSSOQ [VSTRWQSSO_S VSTRWQSSO_U])
652 (define_int_iterator VSTRWSBWBQ [VSTRWQSBWB_S VSTRWQSBWB_U])
653 (define_int_iterator VLDRWGBWBQ [VLDRWQGBWB_S VLDRWQGBWB_U])
654 (define_int_iterator VSTRDSBWBQ [VSTRDQSBWB_S VSTRDQSBWB_U])
655 (define_int_iterator VLDRDGBWBQ [VLDRDQGBWB_S VLDRDQGBWB_U])
656 (define_int_iterator VADCIQ [VADCIQ_U VADCIQ_S])
657 (define_int_iterator VADCIQ_M [VADCIQ_M_U VADCIQ_M_S])
658 (define_int_iterator VSBCQ [VSBCQ_U VSBCQ_S])
659 (define_int_iterator VSBCQ_M [VSBCQ_M_U VSBCQ_M_S])
660 (define_int_iterator VSBCIQ [VSBCIQ_U VSBCIQ_S])
661 (define_int_iterator VSBCIQ_M [VSBCIQ_M_U VSBCIQ_M_S])
662 (define_int_iterator VADCQ [VADCQ_U VADCQ_S])
663 (define_int_iterator VADCQ_M [VADCQ_M_U VADCQ_M_S])
664 (define_int_iterator UQRSHLLQ [UQRSHLL_64 UQRSHLL_48])
665 (define_int_iterator SQRSHRLQ [SQRSHRL_64 SQRSHRL_48])
666 (define_int_iterator VSHLCQ_M [VSHLCQ_M_S VSHLCQ_M_U])
668 (define_insn "*mve_mov<mode>"
669 [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us")
670 (match_operand:MVE_types 1 "general_operand" "w,r,w,Dn,Usi,r,Dm,w"))]
671 "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT"
673 if (which_alternative == 3 || which_alternative == 6)
676 static char templ[40];
678 is_valid = simd_immediate_valid_for_move (operands[1], <MODE>mode,
679 &operands[1], &width);
681 gcc_assert (is_valid != 0);
684 return "vmov.f32\t%q0, %1 @ <mode>";
686 sprintf (templ, "vmov.i%d\t%%q0, %%x1 @ <mode>", width);
689 switch (which_alternative)
692 return "vmov\t%q0, %q1";
694 return "vmov\t%e0, %Q1, %R1 @ <mode>\;vmov\t%f0, %J1, %K1";
696 return "vmov\t%Q0, %R0, %e1 @ <mode>\;vmov\t%J0, %K0, %f1";
698 if ((TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))
699 || (MEM_P (operands[1])
700 && GET_CODE (XEXP (operands[1], 0)) == LABEL_REF))
701 return output_move_neon (operands);
703 return "vldrb.8 %q0, %E1";
705 return output_move_quad (operands);
707 return "vstrb.8 %q1, %E0";
713 [(set_attr "type" "mve_move,mve_move,mve_move,mve_move,mve_load,multiple,mve_move,mve_store")
714 (set_attr "length" "4,8,8,4,8,8,4,4")
715 (set_attr "thumb2_pool_range" "*,*,*,*,1018,*,*,*")
716 (set_attr "neg_pool_range" "*,*,*,*,996,*,*,*")])
718 (define_insn "*mve_mov<mode>"
719 [(set (match_operand:MVE_types 0 "s_register_operand" "=w,w")
720 (vec_duplicate:MVE_types
721 (match_operand:SI 1 "nonmemory_operand" "r,i")))]
722 "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT"
724 if (which_alternative == 0)
725 return "vdup.<V_sz_elem>\t%q0, %1";
726 return "vmov.<V_sz_elem>\t%q0, %1";
728 [(set_attr "length" "4,4")
729 (set_attr "type" "mve_move,mve_move")])
734 (define_insn "mve_vst4q<mode>"
735 [(set (match_operand:XI 0 "neon_struct_operand" "=Um")
736 (unspec:XI [(match_operand:XI 1 "s_register_operand" "w")
737 (unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
743 int regno = REGNO (operands[1]);
744 ops[0] = gen_rtx_REG (TImode, regno);
745 ops[1] = gen_rtx_REG (TImode, regno+4);
746 ops[2] = gen_rtx_REG (TImode, regno+8);
747 ops[3] = gen_rtx_REG (TImode, regno+12);
748 rtx reg = operands[0];
749 while (reg && !REG_P (reg))
751 gcc_assert (REG_P (reg));
753 ops[5] = operands[0];
754 /* Here in first three instructions data is stored to ops[4]'s location but
755 in the fourth instruction data is stored to operands[0], this is to
756 support the writeback. */
757 output_asm_insn ("vst40.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t"
758 "vst41.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t"
759 "vst42.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t"
760 "vst43.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, %5", ops);
763 [(set_attr "length" "16")])
768 (define_insn "mve_vrndq_m_f<mode>"
770 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
771 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
772 (match_operand:MVE_0 2 "s_register_operand" "w")
773 (match_operand:HI 3 "vpr_register_operand" "Up")]
776 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
777 "vpst\;vrintzt.f%#<V_sz_elem> %q0, %q2"
778 [(set_attr "type" "mve_move")
779 (set_attr "length""8")])
784 (define_insn "mve_vrndxq_f<mode>"
786 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
787 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
790 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
791 "vrintx.f%#<V_sz_elem> %q0, %q1"
792 [(set_attr "type" "mve_move")
798 (define_insn "mve_vrndq_f<mode>"
800 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
801 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
804 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
805 "vrintz.f%#<V_sz_elem> %q0, %q1"
806 [(set_attr "type" "mve_move")
812 (define_insn "mve_vrndpq_f<mode>"
814 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
815 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
818 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
819 "vrintp.f%#<V_sz_elem> %q0, %q1"
820 [(set_attr "type" "mve_move")
826 (define_insn "mve_vrndnq_f<mode>"
828 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
829 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
832 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
833 "vrintn.f%#<V_sz_elem> %q0, %q1"
834 [(set_attr "type" "mve_move")
840 (define_insn "mve_vrndmq_f<mode>"
842 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
843 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
846 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
847 "vrintm.f%#<V_sz_elem> %q0, %q1"
848 [(set_attr "type" "mve_move")
854 (define_insn "mve_vrndaq_f<mode>"
856 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
857 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
860 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
861 "vrinta.f%#<V_sz_elem> %q0, %q1"
862 [(set_attr "type" "mve_move")
868 (define_insn "mve_vrev64q_f<mode>"
870 (set (match_operand:MVE_0 0 "s_register_operand" "=&w")
871 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
874 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
875 "vrev64.%#<V_sz_elem> %q0, %q1"
876 [(set_attr "type" "mve_move")
882 (define_insn "mve_vnegq_f<mode>"
884 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
885 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
888 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
889 "vneg.f%#<V_sz_elem> %q0, %q1"
890 [(set_attr "type" "mve_move")
896 (define_insn "mve_vdupq_n_f<mode>"
898 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
899 (unspec:MVE_0 [(match_operand:<V_elem> 1 "s_register_operand" "r")]
902 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
903 "vdup.%#<V_sz_elem> %q0, %1"
904 [(set_attr "type" "mve_move")
910 (define_insn "mve_vabsq_f<mode>"
912 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
913 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
916 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
917 "vabs.f%#<V_sz_elem> %q0, %q1"
918 [(set_attr "type" "mve_move")
924 (define_insn "mve_vrev32q_fv8hf"
926 (set (match_operand:V8HF 0 "s_register_operand" "=w")
927 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "w")]
930 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
932 [(set_attr "type" "mve_move")
937 (define_insn "mve_vcvttq_f32_f16v4sf"
939 (set (match_operand:V4SF 0 "s_register_operand" "=w")
940 (unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")]
943 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
944 "vcvtt.f32.f16 %q0, %q1"
945 [(set_attr "type" "mve_move")
951 (define_insn "mve_vcvtbq_f32_f16v4sf"
953 (set (match_operand:V4SF 0 "s_register_operand" "=w")
954 (unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")]
957 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
958 "vcvtb.f32.f16 %q0, %q1"
959 [(set_attr "type" "mve_move")
963 ;; [vcvtq_to_f_s, vcvtq_to_f_u])
965 (define_insn "mve_vcvtq_to_f_<supf><mode>"
967 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
968 (unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
971 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
972 "vcvt.f%#<V_sz_elem>.<supf>%#<V_sz_elem> %q0, %q1"
973 [(set_attr "type" "mve_move")
977 ;; [vrev64q_u, vrev64q_s])
979 (define_insn "mve_vrev64q_<supf><mode>"
981 (set (match_operand:MVE_2 0 "s_register_operand" "=&w")
982 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
986 "vrev64.%#<V_sz_elem> %q0, %q1"
987 [(set_attr "type" "mve_move")
991 ;; [vcvtq_from_f_s, vcvtq_from_f_u])
993 (define_insn "mve_vcvtq_from_f_<supf><mode>"
995 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
996 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
999 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1000 "vcvt.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
1001 [(set_attr "type" "mve_move")
1005 (define_insn "mve_vqnegq_s<mode>"
1007 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1008 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
1012 "vqneg.s%#<V_sz_elem> %q0, %q1"
1013 [(set_attr "type" "mve_move")
1019 (define_insn "mve_vqabsq_s<mode>"
1021 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1022 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
1026 "vqabs.s%#<V_sz_elem> %q0, %q1"
1027 [(set_attr "type" "mve_move")
1033 (define_insn "mve_vnegq_s<mode>"
1035 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1036 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
1040 "vneg.s%#<V_sz_elem> %q0, %q1"
1041 [(set_attr "type" "mve_move")
1045 ;; [vmvnq_u, vmvnq_s])
1047 (define_insn "mve_vmvnq_<supf><mode>"
1049 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1050 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
1055 [(set_attr "type" "mve_move")
1059 ;; [vdupq_n_u, vdupq_n_s])
1061 (define_insn "mve_vdupq_n_<supf><mode>"
1063 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1064 (unspec:MVE_2 [(match_operand:<V_elem> 1 "s_register_operand" "r")]
1068 "vdup.%#<V_sz_elem> %q0, %1"
1069 [(set_attr "type" "mve_move")
1073 ;; [vclzq_u, vclzq_s])
1075 (define_insn "mve_vclzq_<supf><mode>"
1077 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1078 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
1082 "vclz.i%#<V_sz_elem> %q0, %q1"
1083 [(set_attr "type" "mve_move")
1089 (define_insn "mve_vclsq_s<mode>"
1091 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1092 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
1096 "vcls.s%#<V_sz_elem> %q0, %q1"
1097 [(set_attr "type" "mve_move")
1101 ;; [vaddvq_s, vaddvq_u])
1103 (define_insn "mve_vaddvq_<supf><mode>"
1105 (set (match_operand:SI 0 "s_register_operand" "=e")
1106 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")]
1110 "vaddv.<supf>%#<V_sz_elem>\t%0, %q1"
1111 [(set_attr "type" "mve_move")
1117 (define_insn "mve_vabsq_s<mode>"
1119 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1120 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
1124 "vabs.s%#<V_sz_elem>\t%q0, %q1"
1125 [(set_attr "type" "mve_move")
1129 ;; [vrev32q_u, vrev32q_s])
1131 (define_insn "mve_vrev32q_<supf><mode>"
1133 (set (match_operand:MVE_3 0 "s_register_operand" "=w")
1134 (unspec:MVE_3 [(match_operand:MVE_3 1 "s_register_operand" "w")]
1138 "vrev32.%#<V_sz_elem>\t%q0, %q1"
1139 [(set_attr "type" "mve_move")
1143 ;; [vmovltq_u, vmovltq_s])
1145 (define_insn "mve_vmovltq_<supf><mode>"
1147 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
1148 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")]
1152 "vmovlt.<supf>%#<V_sz_elem> %q0, %q1"
1153 [(set_attr "type" "mve_move")
1157 ;; [vmovlbq_s, vmovlbq_u])
1159 (define_insn "mve_vmovlbq_<supf><mode>"
1161 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
1162 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")]
1166 "vmovlb.<supf>%#<V_sz_elem> %q0, %q1"
1167 [(set_attr "type" "mve_move")
1171 ;; [vcvtpq_s, vcvtpq_u])
1173 (define_insn "mve_vcvtpq_<supf><mode>"
1175 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
1176 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
1179 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1180 "vcvtp.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
1181 [(set_attr "type" "mve_move")
1185 ;; [vcvtnq_s, vcvtnq_u])
1187 (define_insn "mve_vcvtnq_<supf><mode>"
1189 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
1190 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
1193 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1194 "vcvtn.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
1195 [(set_attr "type" "mve_move")
1199 ;; [vcvtmq_s, vcvtmq_u])
1201 (define_insn "mve_vcvtmq_<supf><mode>"
1203 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
1204 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
1207 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1208 "vcvtm.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
1209 [(set_attr "type" "mve_move")
1213 ;; [vcvtaq_u, vcvtaq_s])
1215 (define_insn "mve_vcvtaq_<supf><mode>"
1217 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
1218 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
1221 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1222 "vcvta.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
1223 [(set_attr "type" "mve_move")
1227 ;; [vmvnq_n_u, vmvnq_n_s])
1229 (define_insn "mve_vmvnq_n_<supf><mode>"
1231 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
1232 (unspec:MVE_5 [(match_operand:HI 1 "immediate_operand" "i")]
1236 "vmvn.i%#<V_sz_elem> %q0, %1"
1237 [(set_attr "type" "mve_move")
1241 ;; [vrev16q_u, vrev16q_s])
1243 (define_insn "mve_vrev16q_<supf>v16qi"
1245 (set (match_operand:V16QI 0 "s_register_operand" "=w")
1246 (unspec:V16QI [(match_operand:V16QI 1 "s_register_operand" "w")]
1251 [(set_attr "type" "mve_move")
1255 ;; [vaddlvq_s vaddlvq_u])
1257 (define_insn "mve_vaddlvq_<supf>v4si"
1259 (set (match_operand:DI 0 "s_register_operand" "=r")
1260 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")]
1264 "vaddlv.<supf>32 %Q0, %R0, %q1"
1265 [(set_attr "type" "mve_move")
1269 ;; [vctp8q vctp16q vctp32q vctp64q])
1271 (define_insn "mve_vctp<mode1>qhi"
1273 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1274 (unspec:HI [(match_operand:SI 1 "s_register_operand" "r")]
1279 [(set_attr "type" "mve_move")
1285 (define_insn "mve_vpnothi"
1287 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1288 (unspec:HI [(match_operand:HI 1 "vpr_register_operand" "0")]
1293 [(set_attr "type" "mve_move")
1299 (define_insn "mve_vsubq_n_f<mode>"
1301 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
1302 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
1303 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1306 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1307 "vsub.f<V_sz_elem> %q0, %q1, %2"
1308 [(set_attr "type" "mve_move")
1314 (define_insn "mve_vbrsrq_n_f<mode>"
1316 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
1317 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
1318 (match_operand:SI 2 "s_register_operand" "r")]
1321 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1322 "vbrsr.<V_sz_elem> %q0, %q1, %2"
1323 [(set_attr "type" "mve_move")
1327 ;; [vcvtq_n_to_f_s, vcvtq_n_to_f_u])
1329 (define_insn "mve_vcvtq_n_to_f_<supf><mode>"
1331 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
1332 (unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")
1333 (match_operand:SI 2 "mve_imm_16" "Rd")]
1336 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1337 "vcvt.f<V_sz_elem>.<supf><V_sz_elem>\t%q0, %q1, %2"
1338 [(set_attr "type" "mve_move")
1343 (define_insn "mve_vcreateq_f<mode>"
1345 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
1346 (unspec:MVE_0 [(match_operand:DI 1 "s_register_operand" "r")
1347 (match_operand:DI 2 "s_register_operand" "r")]
1350 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1351 "vmov %q0[2], %q0[0], %Q2, %Q1\;vmov %q0[3], %q0[1], %R2, %R1"
1352 [(set_attr "type" "mve_move")
1353 (set_attr "length""8")])
1356 ;; [vcreateq_u, vcreateq_s])
1358 (define_insn "mve_vcreateq_<supf><mode>"
1360 (set (match_operand:MVE_1 0 "s_register_operand" "=w")
1361 (unspec:MVE_1 [(match_operand:DI 1 "s_register_operand" "r")
1362 (match_operand:DI 2 "s_register_operand" "r")]
1366 "vmov %q0[2], %q0[0], %Q2, %Q1\;vmov %q0[3], %q0[1], %R2, %R1"
1367 [(set_attr "type" "mve_move")
1368 (set_attr "length""8")])
1371 ;; [vshrq_n_s, vshrq_n_u])
1373 (define_insn "mve_vshrq_n_<supf><mode>"
1375 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1376 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1377 (match_operand:SI 2 "<MVE_pred2>" "<MVE_constraint2>")]
1381 "vshr.<supf><V_sz_elem>\t%q0, %q1, %2"
1382 [(set_attr "type" "mve_move")
1386 ;; [vcvtq_n_from_f_s, vcvtq_n_from_f_u])
1388 (define_insn "mve_vcvtq_n_from_f_<supf><mode>"
1390 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
1391 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")
1392 (match_operand:SI 2 "mve_imm_16" "Rd")]
1395 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1396 "vcvt.<supf><V_sz_elem>.f<V_sz_elem>\t%q0, %q1, %2"
1397 [(set_attr "type" "mve_move")
1403 (define_insn "mve_vaddlvq_p_<supf>v4si"
1405 (set (match_operand:DI 0 "s_register_operand" "=r")
1406 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
1407 (match_operand:HI 2 "vpr_register_operand" "Up")]
1411 "vpst\;vaddlvt.<supf>32 %Q0, %R0, %q1"
1412 [(set_attr "type" "mve_move")
1413 (set_attr "length""8")])
1416 ;; [vcmpneq_u, vcmpneq_s])
1418 (define_insn "mve_vcmpneq_<supf><mode>"
1420 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1421 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1422 (match_operand:MVE_2 2 "s_register_operand" "w")]
1426 "vcmp.i%#<V_sz_elem> ne, %q1, %q2"
1427 [(set_attr "type" "mve_move")
1431 ;; [vshlq_s, vshlq_u])
1433 (define_insn "mve_vshlq_<supf><mode>"
1435 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1436 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1437 (match_operand:MVE_2 2 "s_register_operand" "w")]
1441 "vshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1442 [(set_attr "type" "mve_move")
1446 ;; [vabdq_s, vabdq_u])
1448 (define_insn "mve_vabdq_<supf><mode>"
1450 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1451 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1452 (match_operand:MVE_2 2 "s_register_operand" "w")]
1456 "vabd.<supf>%#<V_sz_elem> %q0, %q1, %q2"
1457 [(set_attr "type" "mve_move")
1461 ;; [vaddq_n_s, vaddq_n_u])
1463 (define_insn "mve_vaddq_n_<supf><mode>"
1465 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1466 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1467 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1471 "vadd.i%#<V_sz_elem> %q0, %q1, %2"
1472 [(set_attr "type" "mve_move")
1476 ;; [vaddvaq_s, vaddvaq_u])
1478 (define_insn "mve_vaddvaq_<supf><mode>"
1480 (set (match_operand:SI 0 "s_register_operand" "=e")
1481 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
1482 (match_operand:MVE_2 2 "s_register_operand" "w")]
1486 "vaddva.<supf>%#<V_sz_elem> %0, %q2"
1487 [(set_attr "type" "mve_move")
1491 ;; [vaddvq_p_u, vaddvq_p_s])
1493 (define_insn "mve_vaddvq_p_<supf><mode>"
1495 (set (match_operand:SI 0 "s_register_operand" "=e")
1496 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
1497 (match_operand:HI 2 "vpr_register_operand" "Up")]
1501 "vpst\;vaddvt.<supf>%#<V_sz_elem> %0, %q1"
1502 [(set_attr "type" "mve_move")
1503 (set_attr "length""8")])
1506 ;; [vandq_u, vandq_s])
1508 (define_insn "mve_vandq_<supf><mode>"
1510 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1511 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1512 (match_operand:MVE_2 2 "s_register_operand" "w")]
1516 "vand %q0, %q1, %q2"
1517 [(set_attr "type" "mve_move")
1521 ;; [vbicq_s, vbicq_u])
1523 (define_insn "mve_vbicq_<supf><mode>"
1525 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1526 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1527 (match_operand:MVE_2 2 "s_register_operand" "w")]
1531 "vbic %q0, %q1, %q2"
1532 [(set_attr "type" "mve_move")
1536 ;; [vbrsrq_n_u, vbrsrq_n_s])
1538 (define_insn "mve_vbrsrq_n_<supf><mode>"
1540 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1541 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1542 (match_operand:SI 2 "s_register_operand" "r")]
1546 "vbrsr.%#<V_sz_elem> %q0, %q1, %2"
1547 [(set_attr "type" "mve_move")
1551 ;; [vcaddq_rot270_s, vcaddq_rot270_u])
1553 (define_insn "mve_vcaddq_rot270_<supf><mode>"
1555 (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
1556 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1557 (match_operand:MVE_2 2 "s_register_operand" "w")]
1561 "vcadd.i%#<V_sz_elem> %q0, %q1, %q2, #270"
1562 [(set_attr "type" "mve_move")
1566 ;; [vcaddq_rot90_u, vcaddq_rot90_s])
1568 (define_insn "mve_vcaddq_rot90_<supf><mode>"
1570 (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
1571 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1572 (match_operand:MVE_2 2 "s_register_operand" "w")]
1576 "vcadd.i%#<V_sz_elem> %q0, %q1, %q2, #90"
1577 [(set_attr "type" "mve_move")
1583 (define_insn "mve_vcmpcsq_n_u<mode>"
1585 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1586 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1587 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1591 "vcmp.u%#<V_sz_elem> cs, %q1, %2"
1592 [(set_attr "type" "mve_move")
1598 (define_insn "mve_vcmpcsq_u<mode>"
1600 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1601 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1602 (match_operand:MVE_2 2 "s_register_operand" "w")]
1606 "vcmp.u%#<V_sz_elem> cs, %q1, %q2"
1607 [(set_attr "type" "mve_move")
1611 ;; [vcmpeqq_n_s, vcmpeqq_n_u])
1613 (define_insn "mve_vcmpeqq_n_<supf><mode>"
1615 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1616 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1617 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1621 "vcmp.i%#<V_sz_elem> eq, %q1, %2"
1622 [(set_attr "type" "mve_move")
1626 ;; [vcmpeqq_u, vcmpeqq_s])
1628 (define_insn "mve_vcmpeqq_<supf><mode>"
1630 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1631 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1632 (match_operand:MVE_2 2 "s_register_operand" "w")]
1636 "vcmp.i%#<V_sz_elem> eq, %q1, %q2"
1637 [(set_attr "type" "mve_move")
1643 (define_insn "mve_vcmpgeq_n_s<mode>"
1645 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1646 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1647 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1651 "vcmp.s%#<V_sz_elem> ge, %q1, %2"
1652 [(set_attr "type" "mve_move")
1658 (define_insn "mve_vcmpgeq_s<mode>"
1660 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1661 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1662 (match_operand:MVE_2 2 "s_register_operand" "w")]
1666 "vcmp.s%#<V_sz_elem> ge, %q1, %q2"
1667 [(set_attr "type" "mve_move")
1673 (define_insn "mve_vcmpgtq_n_s<mode>"
1675 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1676 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1677 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1681 "vcmp.s%#<V_sz_elem> gt, %q1, %2"
1682 [(set_attr "type" "mve_move")
1688 (define_insn "mve_vcmpgtq_s<mode>"
1690 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1691 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1692 (match_operand:MVE_2 2 "s_register_operand" "w")]
1696 "vcmp.s%#<V_sz_elem> gt, %q1, %q2"
1697 [(set_attr "type" "mve_move")
1703 (define_insn "mve_vcmphiq_n_u<mode>"
1705 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1706 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1707 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1711 "vcmp.u%#<V_sz_elem> hi, %q1, %2"
1712 [(set_attr "type" "mve_move")
1718 (define_insn "mve_vcmphiq_u<mode>"
1720 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1721 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1722 (match_operand:MVE_2 2 "s_register_operand" "w")]
1726 "vcmp.u%#<V_sz_elem> hi, %q1, %q2"
1727 [(set_attr "type" "mve_move")
1733 (define_insn "mve_vcmpleq_n_s<mode>"
1735 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1736 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1737 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1741 "vcmp.s%#<V_sz_elem> le, %q1, %2"
1742 [(set_attr "type" "mve_move")
1748 (define_insn "mve_vcmpleq_s<mode>"
1750 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1751 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1752 (match_operand:MVE_2 2 "s_register_operand" "w")]
1756 "vcmp.s%#<V_sz_elem> le, %q1, %q2"
1757 [(set_attr "type" "mve_move")
1763 (define_insn "mve_vcmpltq_n_s<mode>"
1765 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1766 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1767 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1771 "vcmp.s%#<V_sz_elem> lt, %q1, %2"
1772 [(set_attr "type" "mve_move")
1778 (define_insn "mve_vcmpltq_s<mode>"
1780 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1781 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1782 (match_operand:MVE_2 2 "s_register_operand" "w")]
1786 "vcmp.s%#<V_sz_elem> lt, %q1, %q2"
1787 [(set_attr "type" "mve_move")
1791 ;; [vcmpneq_n_u, vcmpneq_n_s])
1793 (define_insn "mve_vcmpneq_n_<supf><mode>"
1795 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1796 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1797 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1801 "vcmp.i%#<V_sz_elem> ne, %q1, %2"
1802 [(set_attr "type" "mve_move")
1806 ;; [veorq_u, veorq_s])
1808 (define_insn "mve_veorq_<supf><mode>"
1810 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1811 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1812 (match_operand:MVE_2 2 "s_register_operand" "w")]
1816 "veor %q0, %q1, %q2"
1817 [(set_attr "type" "mve_move")
1821 ;; [vhaddq_n_u, vhaddq_n_s])
1823 (define_insn "mve_vhaddq_n_<supf><mode>"
1825 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1826 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1827 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1831 "vhadd.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
1832 [(set_attr "type" "mve_move")
1836 ;; [vhaddq_s, vhaddq_u])
1838 (define_insn "mve_vhaddq_<supf><mode>"
1840 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1841 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1842 (match_operand:MVE_2 2 "s_register_operand" "w")]
1846 "vhadd.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1847 [(set_attr "type" "mve_move")
1851 ;; [vhcaddq_rot270_s])
1853 (define_insn "mve_vhcaddq_rot270_s<mode>"
1855 (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
1856 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1857 (match_operand:MVE_2 2 "s_register_operand" "w")]
1861 "vhcadd.s%#<V_sz_elem>\t%q0, %q1, %q2, #270"
1862 [(set_attr "type" "mve_move")
1866 ;; [vhcaddq_rot90_s])
1868 (define_insn "mve_vhcaddq_rot90_s<mode>"
1870 (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
1871 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1872 (match_operand:MVE_2 2 "s_register_operand" "w")]
1876 "vhcadd.s%#<V_sz_elem>\t%q0, %q1, %q2, #90"
1877 [(set_attr "type" "mve_move")
1881 ;; [vhsubq_n_u, vhsubq_n_s])
1883 (define_insn "mve_vhsubq_n_<supf><mode>"
1885 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1886 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1887 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1891 "vhsub.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
1892 [(set_attr "type" "mve_move")
1896 ;; [vhsubq_s, vhsubq_u])
1898 (define_insn "mve_vhsubq_<supf><mode>"
1900 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1901 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1902 (match_operand:MVE_2 2 "s_register_operand" "w")]
1906 "vhsub.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1907 [(set_attr "type" "mve_move")
1913 (define_insn "mve_vmaxaq_s<mode>"
1915 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1916 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
1917 (match_operand:MVE_2 2 "s_register_operand" "w")]
1921 "vmaxa.s%#<V_sz_elem> %q0, %q2"
1922 [(set_attr "type" "mve_move")
1928 (define_insn "mve_vmaxavq_s<mode>"
1930 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
1931 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
1932 (match_operand:MVE_2 2 "s_register_operand" "w")]
1936 "vmaxav.s%#<V_sz_elem>\t%0, %q2"
1937 [(set_attr "type" "mve_move")
1941 ;; [vmaxq_u, vmaxq_s])
1943 (define_insn "mve_vmaxq_<supf><mode>"
1945 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1946 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1947 (match_operand:MVE_2 2 "s_register_operand" "w")]
1951 "vmax.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1952 [(set_attr "type" "mve_move")
1956 ;; [vmaxvq_u, vmaxvq_s])
1958 (define_insn "mve_vmaxvq_<supf><mode>"
1960 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
1961 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
1962 (match_operand:MVE_2 2 "s_register_operand" "w")]
1966 "vmaxv.<supf>%#<V_sz_elem>\t%0, %q2"
1967 [(set_attr "type" "mve_move")
1973 (define_insn "mve_vminaq_s<mode>"
1975 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1976 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
1977 (match_operand:MVE_2 2 "s_register_operand" "w")]
1981 "vmina.s%#<V_sz_elem>\t%q0, %q2"
1982 [(set_attr "type" "mve_move")
1988 (define_insn "mve_vminavq_s<mode>"
1990 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
1991 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
1992 (match_operand:MVE_2 2 "s_register_operand" "w")]
1996 "vminav.s%#<V_sz_elem>\t%0, %q2"
1997 [(set_attr "type" "mve_move")
2001 ;; [vminq_s, vminq_u])
2003 (define_insn "mve_vminq_<supf><mode>"
2005 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2006 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2007 (match_operand:MVE_2 2 "s_register_operand" "w")]
2011 "vmin.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2012 [(set_attr "type" "mve_move")
2016 ;; [vminvq_u, vminvq_s])
2018 (define_insn "mve_vminvq_<supf><mode>"
2020 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
2021 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
2022 (match_operand:MVE_2 2 "s_register_operand" "w")]
2026 "vminv.<supf>%#<V_sz_elem>\t%0, %q2"
2027 [(set_attr "type" "mve_move")
2031 ;; [vmladavq_u, vmladavq_s])
2033 (define_insn "mve_vmladavq_<supf><mode>"
2035 (set (match_operand:SI 0 "s_register_operand" "=e")
2036 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
2037 (match_operand:MVE_2 2 "s_register_operand" "w")]
2041 "vmladav.<supf>%#<V_sz_elem>\t%0, %q1, %q2"
2042 [(set_attr "type" "mve_move")
2048 (define_insn "mve_vmladavxq_s<mode>"
2050 (set (match_operand:SI 0 "s_register_operand" "=e")
2051 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
2052 (match_operand:MVE_2 2 "s_register_operand" "w")]
2056 "vmladavx.s%#<V_sz_elem>\t%0, %q1, %q2"
2057 [(set_attr "type" "mve_move")
2063 (define_insn "mve_vmlsdavq_s<mode>"
2065 (set (match_operand:SI 0 "s_register_operand" "=e")
2066 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
2067 (match_operand:MVE_2 2 "s_register_operand" "w")]
2071 "vmlsdav.s%#<V_sz_elem>\t%0, %q1, %q2"
2072 [(set_attr "type" "mve_move")
2078 (define_insn "mve_vmlsdavxq_s<mode>"
2080 (set (match_operand:SI 0 "s_register_operand" "=e")
2081 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
2082 (match_operand:MVE_2 2 "s_register_operand" "w")]
2086 "vmlsdavx.s%#<V_sz_elem>\t%0, %q1, %q2"
2087 [(set_attr "type" "mve_move")
2091 ;; [vmulhq_s, vmulhq_u])
2093 (define_insn "mve_vmulhq_<supf><mode>"
2095 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2096 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2097 (match_operand:MVE_2 2 "s_register_operand" "w")]
2101 "vmulh.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2102 [(set_attr "type" "mve_move")
2106 ;; [vmullbq_int_u, vmullbq_int_s])
2108 (define_insn "mve_vmullbq_int_<supf><mode>"
2110 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
2111 (unspec:<V_double_width> [(match_operand:MVE_2 1 "s_register_operand" "w")
2112 (match_operand:MVE_2 2 "s_register_operand" "w")]
2116 "vmullb.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2117 [(set_attr "type" "mve_move")
2121 ;; [vmulltq_int_u, vmulltq_int_s])
2123 (define_insn "mve_vmulltq_int_<supf><mode>"
2125 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
2126 (unspec:<V_double_width> [(match_operand:MVE_2 1 "s_register_operand" "w")
2127 (match_operand:MVE_2 2 "s_register_operand" "w")]
2131 "vmullt.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2132 [(set_attr "type" "mve_move")
2136 ;; [vmulq_n_u, vmulq_n_s])
2138 (define_insn "mve_vmulq_n_<supf><mode>"
2140 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2141 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2142 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2146 "vmul.i%#<V_sz_elem>\t%q0, %q1, %2"
2147 [(set_attr "type" "mve_move")
2151 ;; [vmulq_u, vmulq_s])
2153 (define_insn "mve_vmulq_<supf><mode>"
2155 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2156 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2157 (match_operand:MVE_2 2 "s_register_operand" "w")]
2161 "vmul.i%#<V_sz_elem>\t%q0, %q1, %q2"
2162 [(set_attr "type" "mve_move")
2166 ;; [vornq_u, vornq_s])
2168 (define_insn "mve_vornq_<supf><mode>"
2170 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2171 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2172 (match_operand:MVE_2 2 "s_register_operand" "w")]
2176 "vorn %q0, %q1, %q2"
2177 [(set_attr "type" "mve_move")
2181 ;; [vorrq_s, vorrq_u])
2183 (define_insn "mve_vorrq_<supf><mode>"
2185 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2186 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2187 (match_operand:MVE_2 2 "s_register_operand" "w")]
2191 "vorr %q0, %q1, %q2"
2192 [(set_attr "type" "mve_move")
2196 ;; [vqaddq_n_s, vqaddq_n_u])
2198 (define_insn "mve_vqaddq_n_<supf><mode>"
2200 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2201 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2202 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2206 "vqadd.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
2207 [(set_attr "type" "mve_move")
2211 ;; [vqaddq_u, vqaddq_s])
2213 (define_insn "mve_vqaddq_<supf><mode>"
2215 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2216 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2217 (match_operand:MVE_2 2 "s_register_operand" "w")]
2221 "vqadd.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2222 [(set_attr "type" "mve_move")
2228 (define_insn "mve_vqdmulhq_n_s<mode>"
2230 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2231 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2232 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2236 "vqdmulh.s%#<V_sz_elem>\t%q0, %q1, %2"
2237 [(set_attr "type" "mve_move")
2243 (define_insn "mve_vqdmulhq_s<mode>"
2245 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2246 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2247 (match_operand:MVE_2 2 "s_register_operand" "w")]
2251 "vqdmulh.s%#<V_sz_elem>\t%q0, %q1, %q2"
2252 [(set_attr "type" "mve_move")
2258 (define_insn "mve_vqrdmulhq_n_s<mode>"
2260 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2261 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2262 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2266 "vqrdmulh.s%#<V_sz_elem>\t%q0, %q1, %2"
2267 [(set_attr "type" "mve_move")
2273 (define_insn "mve_vqrdmulhq_s<mode>"
2275 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2276 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2277 (match_operand:MVE_2 2 "s_register_operand" "w")]
2281 "vqrdmulh.s%#<V_sz_elem>\t%q0, %q1, %q2"
2282 [(set_attr "type" "mve_move")
2286 ;; [vqrshlq_n_s, vqrshlq_n_u])
2288 (define_insn "mve_vqrshlq_n_<supf><mode>"
2290 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2291 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
2292 (match_operand:SI 2 "s_register_operand" "r")]
2296 "vqrshl.<supf>%#<V_sz_elem>\t%q0, %2"
2297 [(set_attr "type" "mve_move")
2301 ;; [vqrshlq_s, vqrshlq_u])
2303 (define_insn "mve_vqrshlq_<supf><mode>"
2305 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2306 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2307 (match_operand:MVE_2 2 "s_register_operand" "w")]
2311 "vqrshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2312 [(set_attr "type" "mve_move")
2316 ;; [vqshlq_n_s, vqshlq_n_u])
2318 (define_insn "mve_vqshlq_n_<supf><mode>"
2320 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2321 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2322 (match_operand:SI 2 "immediate_operand" "i")]
2326 "vqshl.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
2327 [(set_attr "type" "mve_move")
2331 ;; [vqshlq_r_u, vqshlq_r_s])
2333 (define_insn "mve_vqshlq_r_<supf><mode>"
2335 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2336 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
2337 (match_operand:SI 2 "s_register_operand" "r")]
2341 "vqshl.<supf>%#<V_sz_elem>\t%q0, %2"
2342 [(set_attr "type" "mve_move")
2346 ;; [vqshlq_s, vqshlq_u])
2348 (define_insn "mve_vqshlq_<supf><mode>"
2350 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2351 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2352 (match_operand:MVE_2 2 "s_register_operand" "w")]
2356 "vqshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2357 [(set_attr "type" "mve_move")
2363 (define_insn "mve_vqshluq_n_s<mode>"
2365 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2366 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2367 (match_operand:SI 2 "mve_imm_7" "Ra")]
2371 "vqshlu.s%#<V_sz_elem>\t%q0, %q1, %2"
2372 [(set_attr "type" "mve_move")
2376 ;; [vqsubq_n_s, vqsubq_n_u])
2378 (define_insn "mve_vqsubq_n_<supf><mode>"
2380 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2381 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2382 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2386 "vqsub.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
2387 [(set_attr "type" "mve_move")
2391 ;; [vqsubq_u, vqsubq_s])
2393 (define_insn "mve_vqsubq_<supf><mode>"
2395 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2396 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2397 (match_operand:MVE_2 2 "s_register_operand" "w")]
2401 "vqsub.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2402 [(set_attr "type" "mve_move")
2406 ;; [vrhaddq_s, vrhaddq_u])
2408 (define_insn "mve_vrhaddq_<supf><mode>"
2410 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2411 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2412 (match_operand:MVE_2 2 "s_register_operand" "w")]
2416 "vrhadd.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2417 [(set_attr "type" "mve_move")
2421 ;; [vrmulhq_s, vrmulhq_u])
2423 (define_insn "mve_vrmulhq_<supf><mode>"
2425 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2426 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2427 (match_operand:MVE_2 2 "s_register_operand" "w")]
2431 "vrmulh.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2432 [(set_attr "type" "mve_move")
2436 ;; [vrshlq_n_u, vrshlq_n_s])
2438 (define_insn "mve_vrshlq_n_<supf><mode>"
2440 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2441 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
2442 (match_operand:SI 2 "s_register_operand" "r")]
2446 "vrshl.<supf>%#<V_sz_elem>\t%q0, %2"
2447 [(set_attr "type" "mve_move")
2451 ;; [vrshlq_s, vrshlq_u])
2453 (define_insn "mve_vrshlq_<supf><mode>"
2455 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2456 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2457 (match_operand:MVE_2 2 "s_register_operand" "w")]
2461 "vrshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2462 [(set_attr "type" "mve_move")
2466 ;; [vrshrq_n_s, vrshrq_n_u])
2468 (define_insn "mve_vrshrq_n_<supf><mode>"
2470 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2471 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2472 (match_operand:SI 2 "<MVE_pred2>" "<MVE_constraint2>")]
2476 "vrshr.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
2477 [(set_attr "type" "mve_move")
2481 ;; [vshlq_n_u, vshlq_n_s])
2483 (define_insn "mve_vshlq_n_<supf><mode>"
2485 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2486 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2487 (match_operand:SI 2 "immediate_operand" "i")]
2491 "vshl.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
2492 [(set_attr "type" "mve_move")
2496 ;; [vshlq_r_s, vshlq_r_u])
2498 (define_insn "mve_vshlq_r_<supf><mode>"
2500 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2501 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
2502 (match_operand:SI 2 "s_register_operand" "r")]
2506 "vshl.<supf>%#<V_sz_elem>\t%q0, %2"
2507 [(set_attr "type" "mve_move")
2511 ;; [vsubq_n_s, vsubq_n_u])
2513 (define_insn "mve_vsubq_n_<supf><mode>"
2515 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2516 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2517 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2521 "vsub.i%#<V_sz_elem>\t%q0, %q1, %2"
2522 [(set_attr "type" "mve_move")
2526 ;; [vsubq_s, vsubq_u])
2528 (define_insn "mve_vsubq_<supf><mode>"
2530 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2531 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2532 (match_operand:MVE_2 2 "s_register_operand" "w")]
2536 "vsub.i%#<V_sz_elem>\t%q0, %q1, %q2"
2537 [(set_attr "type" "mve_move")
2543 (define_insn "mve_vabdq_f<mode>"
2545 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2546 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2547 (match_operand:MVE_0 2 "s_register_operand" "w")]
2550 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2551 "vabd.f%#<V_sz_elem> %q0, %q1, %q2"
2552 [(set_attr "type" "mve_move")
2556 ;; [vaddlvaq_s vaddlvaq_u])
2558 (define_insn "mve_vaddlvaq_<supf>v4si"
2560 (set (match_operand:DI 0 "s_register_operand" "=r")
2561 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
2562 (match_operand:V4SI 2 "s_register_operand" "w")]
2566 "vaddlva.<supf>32 %Q0, %R0, %q2"
2567 [(set_attr "type" "mve_move")
2573 (define_insn "mve_vaddq_n_f<mode>"
2575 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2576 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2577 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2580 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2581 "vadd.f%#<V_sz_elem> %q0, %q1, %2"
2582 [(set_attr "type" "mve_move")
2588 (define_insn "mve_vandq_f<mode>"
2590 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2591 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2592 (match_operand:MVE_0 2 "s_register_operand" "w")]
2595 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2596 "vand %q0, %q1, %q2"
2597 [(set_attr "type" "mve_move")
2603 (define_insn "mve_vbicq_f<mode>"
2605 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2606 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2607 (match_operand:MVE_0 2 "s_register_operand" "w")]
2610 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2611 "vbic %q0, %q1, %q2"
2612 [(set_attr "type" "mve_move")
2616 ;; [vbicq_n_s, vbicq_n_u])
2618 (define_insn "mve_vbicq_n_<supf><mode>"
2620 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
2621 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
2622 (match_operand:SI 2 "immediate_operand" "i")]
2626 "vbic.i%#<V_sz_elem> %q0, %2"
2627 [(set_attr "type" "mve_move")
2631 ;; [vcaddq_rot270_f])
2633 (define_insn "mve_vcaddq_rot270_f<mode>"
2635 (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
2636 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2637 (match_operand:MVE_0 2 "s_register_operand" "w")]
2640 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2641 "vcadd.f%#<V_sz_elem> %q0, %q1, %q2, #270"
2642 [(set_attr "type" "mve_move")
2646 ;; [vcaddq_rot90_f])
2648 (define_insn "mve_vcaddq_rot90_f<mode>"
2650 (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
2651 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2652 (match_operand:MVE_0 2 "s_register_operand" "w")]
2655 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2656 "vcadd.f%#<V_sz_elem> %q0, %q1, %q2, #90"
2657 [(set_attr "type" "mve_move")
2663 (define_insn "mve_vcmpeqq_f<mode>"
2665 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2666 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2667 (match_operand:MVE_0 2 "s_register_operand" "w")]
2670 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2671 "vcmp.f%#<V_sz_elem> eq, %q1, %q2"
2672 [(set_attr "type" "mve_move")
2678 (define_insn "mve_vcmpeqq_n_f<mode>"
2680 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2681 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2682 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2685 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2686 "vcmp.f%#<V_sz_elem> eq, %q1, %2"
2687 [(set_attr "type" "mve_move")
2693 (define_insn "mve_vcmpgeq_f<mode>"
2695 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2696 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2697 (match_operand:MVE_0 2 "s_register_operand" "w")]
2700 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2701 "vcmp.f%#<V_sz_elem> ge, %q1, %q2"
2702 [(set_attr "type" "mve_move")
2708 (define_insn "mve_vcmpgeq_n_f<mode>"
2710 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2711 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2712 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2715 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2716 "vcmp.f%#<V_sz_elem> ge, %q1, %2"
2717 [(set_attr "type" "mve_move")
2723 (define_insn "mve_vcmpgtq_f<mode>"
2725 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2726 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2727 (match_operand:MVE_0 2 "s_register_operand" "w")]
2730 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2731 "vcmp.f%#<V_sz_elem> gt, %q1, %q2"
2732 [(set_attr "type" "mve_move")
2738 (define_insn "mve_vcmpgtq_n_f<mode>"
2740 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2741 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2742 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2745 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2746 "vcmp.f%#<V_sz_elem> gt, %q1, %2"
2747 [(set_attr "type" "mve_move")
2753 (define_insn "mve_vcmpleq_f<mode>"
2755 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2756 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2757 (match_operand:MVE_0 2 "s_register_operand" "w")]
2760 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2761 "vcmp.f%#<V_sz_elem> le, %q1, %q2"
2762 [(set_attr "type" "mve_move")
2768 (define_insn "mve_vcmpleq_n_f<mode>"
2770 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2771 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2772 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2775 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2776 "vcmp.f%#<V_sz_elem> le, %q1, %2"
2777 [(set_attr "type" "mve_move")
2783 (define_insn "mve_vcmpltq_f<mode>"
2785 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2786 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2787 (match_operand:MVE_0 2 "s_register_operand" "w")]
2790 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2791 "vcmp.f%#<V_sz_elem> lt, %q1, %q2"
2792 [(set_attr "type" "mve_move")
2798 (define_insn "mve_vcmpltq_n_f<mode>"
2800 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2801 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2802 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2805 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2806 "vcmp.f%#<V_sz_elem> lt, %q1, %2"
2807 [(set_attr "type" "mve_move")
2813 (define_insn "mve_vcmpneq_f<mode>"
2815 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2816 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2817 (match_operand:MVE_0 2 "s_register_operand" "w")]
2820 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2821 "vcmp.f%#<V_sz_elem> ne, %q1, %q2"
2822 [(set_attr "type" "mve_move")
2828 (define_insn "mve_vcmpneq_n_f<mode>"
2830 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2831 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2832 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2835 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2836 "vcmp.f%#<V_sz_elem> ne, %q1, %2"
2837 [(set_attr "type" "mve_move")
2843 (define_insn "mve_vcmulq_f<mode>"
2845 (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
2846 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2847 (match_operand:MVE_0 2 "s_register_operand" "w")]
2850 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2851 "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #0"
2852 [(set_attr "type" "mve_move")
2856 ;; [vcmulq_rot180_f])
2858 (define_insn "mve_vcmulq_rot180_f<mode>"
2860 (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
2861 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2862 (match_operand:MVE_0 2 "s_register_operand" "w")]
2865 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2866 "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #180"
2867 [(set_attr "type" "mve_move")
2871 ;; [vcmulq_rot270_f])
2873 (define_insn "mve_vcmulq_rot270_f<mode>"
2875 (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
2876 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2877 (match_operand:MVE_0 2 "s_register_operand" "w")]
2880 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2881 "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #270"
2882 [(set_attr "type" "mve_move")
2886 ;; [vcmulq_rot90_f])
2888 (define_insn "mve_vcmulq_rot90_f<mode>"
2890 (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
2891 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2892 (match_operand:MVE_0 2 "s_register_operand" "w")]
2895 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2896 "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #90"
2897 [(set_attr "type" "mve_move")
2901 ;; [vctp8q_m vctp16q_m vctp32q_m vctp64q_m])
2903 (define_insn "mve_vctp<mode1>q_mhi"
2905 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2906 (unspec:HI [(match_operand:SI 1 "s_register_operand" "r")
2907 (match_operand:HI 2 "vpr_register_operand" "Up")]
2911 "vpst\;vctpt.<mode1> %1"
2912 [(set_attr "type" "mve_move")
2913 (set_attr "length""8")])
2916 ;; [vcvtbq_f16_f32])
2918 (define_insn "mve_vcvtbq_f16_f32v8hf"
2920 (set (match_operand:V8HF 0 "s_register_operand" "=w")
2921 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
2922 (match_operand:V4SF 2 "s_register_operand" "w")]
2925 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2926 "vcvtb.f16.f32 %q0, %q2"
2927 [(set_attr "type" "mve_move")
2931 ;; [vcvttq_f16_f32])
2933 (define_insn "mve_vcvttq_f16_f32v8hf"
2935 (set (match_operand:V8HF 0 "s_register_operand" "=w")
2936 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
2937 (match_operand:V4SF 2 "s_register_operand" "w")]
2940 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2941 "vcvtt.f16.f32 %q0, %q2"
2942 [(set_attr "type" "mve_move")
2948 (define_insn "mve_veorq_f<mode>"
2950 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2951 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2952 (match_operand:MVE_0 2 "s_register_operand" "w")]
2955 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2956 "veor %q0, %q1, %q2"
2957 [(set_attr "type" "mve_move")
2963 (define_insn "mve_vmaxnmaq_f<mode>"
2965 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2966 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
2967 (match_operand:MVE_0 2 "s_register_operand" "w")]
2970 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2971 "vmaxnma.f%#<V_sz_elem> %q0, %q2"
2972 [(set_attr "type" "mve_move")
2978 (define_insn "mve_vmaxnmavq_f<mode>"
2980 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
2981 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
2982 (match_operand:MVE_0 2 "s_register_operand" "w")]
2985 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2986 "vmaxnmav.f%#<V_sz_elem> %0, %q2"
2987 [(set_attr "type" "mve_move")
2993 (define_insn "mve_vmaxnmq_f<mode>"
2995 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2996 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2997 (match_operand:MVE_0 2 "s_register_operand" "w")]
3000 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3001 "vmaxnm.f%#<V_sz_elem> %q0, %q1, %q2"
3002 [(set_attr "type" "mve_move")
3008 (define_insn "mve_vmaxnmvq_f<mode>"
3010 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
3011 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
3012 (match_operand:MVE_0 2 "s_register_operand" "w")]
3015 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3016 "vmaxnmv.f%#<V_sz_elem> %0, %q2"
3017 [(set_attr "type" "mve_move")
3023 (define_insn "mve_vminnmaq_f<mode>"
3025 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
3026 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
3027 (match_operand:MVE_0 2 "s_register_operand" "w")]
3030 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3031 "vminnma.f%#<V_sz_elem> %q0, %q2"
3032 [(set_attr "type" "mve_move")
3038 (define_insn "mve_vminnmavq_f<mode>"
3040 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
3041 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
3042 (match_operand:MVE_0 2 "s_register_operand" "w")]
3045 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3046 "vminnmav.f%#<V_sz_elem> %0, %q2"
3047 [(set_attr "type" "mve_move")
3053 (define_insn "mve_vminnmq_f<mode>"
3055 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
3056 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
3057 (match_operand:MVE_0 2 "s_register_operand" "w")]
3060 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3061 "vminnm.f%#<V_sz_elem> %q0, %q1, %q2"
3062 [(set_attr "type" "mve_move")
3068 (define_insn "mve_vminnmvq_f<mode>"
3070 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
3071 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
3072 (match_operand:MVE_0 2 "s_register_operand" "w")]
3075 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3076 "vminnmv.f%#<V_sz_elem> %0, %q2"
3077 [(set_attr "type" "mve_move")
3081 ;; [vmlaldavq_u, vmlaldavq_s])
3083 (define_insn "mve_vmlaldavq_<supf><mode>"
3085 (set (match_operand:DI 0 "s_register_operand" "=r")
3086 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
3087 (match_operand:MVE_5 2 "s_register_operand" "w")]
3091 "vmlaldav.<supf>%#<V_sz_elem> %Q0, %R0, %q1, %q2"
3092 [(set_attr "type" "mve_move")
3098 (define_insn "mve_vmlaldavxq_s<mode>"
3100 (set (match_operand:DI 0 "s_register_operand" "=r")
3101 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
3102 (match_operand:MVE_5 2 "s_register_operand" "w")]
3106 "vmlaldavx.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
3107 [(set_attr "type" "mve_move")
3113 (define_insn "mve_vmlsldavq_s<mode>"
3115 (set (match_operand:DI 0 "s_register_operand" "=r")
3116 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
3117 (match_operand:MVE_5 2 "s_register_operand" "w")]
3121 "vmlsldav.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
3122 [(set_attr "type" "mve_move")
3128 (define_insn "mve_vmlsldavxq_s<mode>"
3130 (set (match_operand:DI 0 "s_register_operand" "=r")
3131 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
3132 (match_operand:MVE_5 2 "s_register_operand" "w")]
3136 "vmlsldavx.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
3137 [(set_attr "type" "mve_move")
3141 ;; [vmovnbq_u, vmovnbq_s])
3143 (define_insn "mve_vmovnbq_<supf><mode>"
3145 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3146 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3147 (match_operand:MVE_5 2 "s_register_operand" "w")]
3151 "vmovnb.i%#<V_sz_elem> %q0, %q2"
3152 [(set_attr "type" "mve_move")
3156 ;; [vmovntq_s, vmovntq_u])
3158 (define_insn "mve_vmovntq_<supf><mode>"
3160 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3161 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3162 (match_operand:MVE_5 2 "s_register_operand" "w")]
3166 "vmovnt.i%#<V_sz_elem> %q0, %q2"
3167 [(set_attr "type" "mve_move")
3173 (define_insn "mve_vmulq_f<mode>"
3175 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
3176 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
3177 (match_operand:MVE_0 2 "s_register_operand" "w")]
3180 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3181 "vmul.f%#<V_sz_elem> %q0, %q1, %q2"
3182 [(set_attr "type" "mve_move")
3188 (define_insn "mve_vmulq_n_f<mode>"
3190 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
3191 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
3192 (match_operand:<V_elem> 2 "s_register_operand" "r")]
3195 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3196 "vmul.f%#<V_sz_elem> %q0, %q1, %2"
3197 [(set_attr "type" "mve_move")
3203 (define_insn "mve_vornq_f<mode>"
3205 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
3206 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
3207 (match_operand:MVE_0 2 "s_register_operand" "w")]
3210 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3211 "vorn %q0, %q1, %q2"
3212 [(set_attr "type" "mve_move")
3218 (define_insn "mve_vorrq_f<mode>"
3220 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
3221 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
3222 (match_operand:MVE_0 2 "s_register_operand" "w")]
3225 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3226 "vorr %q0, %q1, %q2"
3227 [(set_attr "type" "mve_move")
3231 ;; [vorrq_n_u, vorrq_n_s])
3233 (define_insn "mve_vorrq_n_<supf><mode>"
3235 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
3236 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
3237 (match_operand:SI 2 "immediate_operand" "i")]
3241 "vorr.i%#<V_sz_elem> %q0, %2"
3242 [(set_attr "type" "mve_move")
3248 (define_insn "mve_vqdmullbq_n_s<mode>"
3250 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
3251 (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w")
3252 (match_operand:<V_elem> 2 "s_register_operand" "r")]
3256 "vqdmullb.s%#<V_sz_elem> %q0, %q1, %2"
3257 [(set_attr "type" "mve_move")
3263 (define_insn "mve_vqdmullbq_s<mode>"
3265 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
3266 (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w")
3267 (match_operand:MVE_5 2 "s_register_operand" "w")]
3271 "vqdmullb.s%#<V_sz_elem> %q0, %q1, %q2"
3272 [(set_attr "type" "mve_move")
3278 (define_insn "mve_vqdmulltq_n_s<mode>"
3280 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
3281 (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w")
3282 (match_operand:<V_elem> 2 "s_register_operand" "r")]
3286 "vqdmullt.s%#<V_sz_elem> %q0, %q1, %2"
3287 [(set_attr "type" "mve_move")
3293 (define_insn "mve_vqdmulltq_s<mode>"
3295 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
3296 (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w")
3297 (match_operand:MVE_5 2 "s_register_operand" "w")]
3301 "vqdmullt.s%#<V_sz_elem> %q0, %q1, %q2"
3302 [(set_attr "type" "mve_move")
3306 ;; [vqmovnbq_u, vqmovnbq_s])
3308 (define_insn "mve_vqmovnbq_<supf><mode>"
3310 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3311 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3312 (match_operand:MVE_5 2 "s_register_operand" "w")]
3316 "vqmovnb.<supf>%#<V_sz_elem> %q0, %q2"
3317 [(set_attr "type" "mve_move")
3321 ;; [vqmovntq_u, vqmovntq_s])
3323 (define_insn "mve_vqmovntq_<supf><mode>"
3325 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3326 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3327 (match_operand:MVE_5 2 "s_register_operand" "w")]
3331 "vqmovnt.<supf>%#<V_sz_elem> %q0, %q2"
3332 [(set_attr "type" "mve_move")
3338 (define_insn "mve_vqmovunbq_s<mode>"
3340 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3341 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3342 (match_operand:MVE_5 2 "s_register_operand" "w")]
3346 "vqmovunb.s%#<V_sz_elem> %q0, %q2"
3347 [(set_attr "type" "mve_move")
3353 (define_insn "mve_vqmovuntq_s<mode>"
3355 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3356 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3357 (match_operand:MVE_5 2 "s_register_operand" "w")]
3361 "vqmovunt.s%#<V_sz_elem> %q0, %q2"
3362 [(set_attr "type" "mve_move")
3366 ;; [vrmlaldavhxq_s])
3368 (define_insn "mve_vrmlaldavhxq_sv4si"
3370 (set (match_operand:DI 0 "s_register_operand" "=r")
3371 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
3372 (match_operand:V4SI 2 "s_register_operand" "w")]
3376 "vrmlaldavhx.s32 %Q0, %R0, %q1, %q2"
3377 [(set_attr "type" "mve_move")
3383 (define_insn "mve_vrmlsldavhq_sv4si"
3385 (set (match_operand:DI 0 "s_register_operand" "=r")
3386 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
3387 (match_operand:V4SI 2 "s_register_operand" "w")]
3391 "vrmlsldavh.s32\t%Q0, %R0, %q1, %q2"
3392 [(set_attr "type" "mve_move")
3396 ;; [vrmlsldavhxq_s])
3398 (define_insn "mve_vrmlsldavhxq_sv4si"
3400 (set (match_operand:DI 0 "s_register_operand" "=r")
3401 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
3402 (match_operand:V4SI 2 "s_register_operand" "w")]
3406 "vrmlsldavhx.s32\t%Q0, %R0, %q1, %q2"
3407 [(set_attr "type" "mve_move")
3411 ;; [vshllbq_n_s, vshllbq_n_u])
3413 (define_insn "mve_vshllbq_n_<supf><mode>"
3415 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
3416 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")
3417 (match_operand:SI 2 "immediate_operand" "i")]
3421 "vshllb.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
3422 [(set_attr "type" "mve_move")
3426 ;; [vshlltq_n_u, vshlltq_n_s])
3428 (define_insn "mve_vshlltq_n_<supf><mode>"
3430 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
3431 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")
3432 (match_operand:SI 2 "immediate_operand" "i")]
3436 "vshllt.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
3437 [(set_attr "type" "mve_move")
3443 (define_insn "mve_vsubq_f<mode>"
3445 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
3446 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
3447 (match_operand:MVE_0 2 "s_register_operand" "w")]
3450 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3451 "vsub.f%#<V_sz_elem>\t%q0, %q1, %q2"
3452 [(set_attr "type" "mve_move")
3456 ;; [vmulltq_poly_p])
3458 (define_insn "mve_vmulltq_poly_p<mode>"
3460 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
3461 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")
3462 (match_operand:MVE_3 2 "s_register_operand" "w")]
3466 "vmullt.p%#<V_sz_elem>\t%q0, %q1, %q2"
3467 [(set_attr "type" "mve_move")
3471 ;; [vmullbq_poly_p])
3473 (define_insn "mve_vmullbq_poly_p<mode>"
3475 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
3476 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")
3477 (match_operand:MVE_3 2 "s_register_operand" "w")]
3481 "vmullb.p%#<V_sz_elem>\t%q0, %q1, %q2"
3482 [(set_attr "type" "mve_move")
3486 ;; [vrmlaldavhq_u vrmlaldavhq_s])
3488 (define_insn "mve_vrmlaldavhq_<supf>v4si"
3490 (set (match_operand:DI 0 "s_register_operand" "=r")
3491 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
3492 (match_operand:V4SI 2 "s_register_operand" "w")]
3496 "vrmlaldavh.<supf>32 %Q0, %R0, %q1, %q2"
3497 [(set_attr "type" "mve_move")
3501 ;; [vbicq_m_n_s, vbicq_m_n_u])
3503 (define_insn "mve_vbicq_m_n_<supf><mode>"
3505 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
3506 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
3507 (match_operand:SI 2 "immediate_operand" "i")
3508 (match_operand:HI 3 "vpr_register_operand" "Up")]
3512 "vpst\;vbict.i%#<V_sz_elem> %q0, %2"
3513 [(set_attr "type" "mve_move")
3514 (set_attr "length""8")])
3518 (define_insn "mve_vcmpeqq_m_f<mode>"
3520 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3521 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
3522 (match_operand:MVE_0 2 "s_register_operand" "w")
3523 (match_operand:HI 3 "vpr_register_operand" "Up")]
3526 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3527 "vpst\;vcmpt.f%#<V_sz_elem> eq, %q1, %q2"
3528 [(set_attr "type" "mve_move")
3529 (set_attr "length""8")])
3531 ;; [vcvtaq_m_u, vcvtaq_m_s])
3533 (define_insn "mve_vcvtaq_m_<supf><mode>"
3535 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
3536 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
3537 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
3538 (match_operand:HI 3 "vpr_register_operand" "Up")]
3541 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3542 "vpst\;vcvtat.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
3543 [(set_attr "type" "mve_move")
3544 (set_attr "length""8")])
3546 ;; [vcvtq_m_to_f_s, vcvtq_m_to_f_u])
3548 (define_insn "mve_vcvtq_m_to_f_<supf><mode>"
3550 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
3551 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
3552 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
3553 (match_operand:HI 3 "vpr_register_operand" "Up")]
3556 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3557 "vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem> %q0, %q2"
3558 [(set_attr "type" "mve_move")
3559 (set_attr "length""8")])
3561 ;; [vqrshrnbq_n_u, vqrshrnbq_n_s])
3563 (define_insn "mve_vqrshrnbq_n_<supf><mode>"
3565 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3566 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3567 (match_operand:MVE_5 2 "s_register_operand" "w")
3568 (match_operand:SI 3 "mve_imm_8" "Rb")]
3572 "vqrshrnb.<supf>%#<V_sz_elem> %q0, %q2, %3"
3573 [(set_attr "type" "mve_move")
3576 ;; [vqrshrunbq_n_s])
3578 (define_insn "mve_vqrshrunbq_n_s<mode>"
3580 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3581 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3582 (match_operand:MVE_5 2 "s_register_operand" "w")
3583 (match_operand:SI 3 "mve_imm_8" "Rb")]
3587 "vqrshrunb.s%#<V_sz_elem>\t%q0, %q2, %3"
3588 [(set_attr "type" "mve_move")
3591 ;; [vrmlaldavhaq_s vrmlaldavhaq_u])
3593 (define_insn "mve_vrmlaldavhaq_<supf>v4si"
3595 (set (match_operand:DI 0 "s_register_operand" "=r")
3596 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
3597 (match_operand:V4SI 2 "s_register_operand" "w")
3598 (match_operand:V4SI 3 "s_register_operand" "w")]
3602 "vrmlaldavha.<supf>32 %Q0, %R0, %q2, %q3"
3603 [(set_attr "type" "mve_move")
3607 ;; [vabavq_s, vabavq_u])
3609 (define_insn "mve_vabavq_<supf><mode>"
3611 (set (match_operand:SI 0 "s_register_operand" "=r")
3612 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
3613 (match_operand:MVE_2 2 "s_register_operand" "w")
3614 (match_operand:MVE_2 3 "s_register_operand" "w")]
3618 "vabav.<supf>%#<V_sz_elem>\t%0, %q2, %q3"
3619 [(set_attr "type" "mve_move")
3623 ;; [vshlcq_u vshlcq_s]
3625 (define_expand "mve_vshlcq_vec_<supf><mode>"
3626 [(match_operand:MVE_2 0 "s_register_operand")
3627 (match_operand:MVE_2 1 "s_register_operand")
3628 (match_operand:SI 2 "s_register_operand")
3629 (match_operand:SI 3 "mve_imm_32")
3630 (unspec:MVE_2 [(const_int 0)] VSHLCQ)]
3633 rtx ignore_wb = gen_reg_rtx (SImode);
3634 emit_insn(gen_mve_vshlcq_<supf><mode>(operands[0], ignore_wb, operands[1],
3635 operands[2], operands[3]));
3639 (define_expand "mve_vshlcq_carry_<supf><mode>"
3640 [(match_operand:SI 0 "s_register_operand")
3641 (match_operand:MVE_2 1 "s_register_operand")
3642 (match_operand:SI 2 "s_register_operand")
3643 (match_operand:SI 3 "mve_imm_32")
3644 (unspec:MVE_2 [(const_int 0)] VSHLCQ)]
3647 rtx ignore_vec = gen_reg_rtx (<MODE>mode);
3648 emit_insn(gen_mve_vshlcq_<supf><mode>(ignore_vec, operands[0], operands[1],
3649 operands[2], operands[3]));
3653 (define_insn "mve_vshlcq_<supf><mode>"
3654 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
3655 (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0")
3656 (match_operand:SI 3 "s_register_operand" "1")
3657 (match_operand:SI 4 "mve_imm_32" "Rf")]
3659 (set (match_operand:SI 1 "s_register_operand" "=r")
3660 (unspec:SI [(match_dup 2)
3665 "vshlc %q0, %1, %4")
3670 (define_insn "mve_vabsq_m_s<mode>"
3672 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3673 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3674 (match_operand:MVE_2 2 "s_register_operand" "w")
3675 (match_operand:HI 3 "vpr_register_operand" "Up")]
3679 "vpst\;vabst.s%#<V_sz_elem> %q0, %q2"
3680 [(set_attr "type" "mve_move")
3681 (set_attr "length""8")])
3684 ;; [vaddvaq_p_u, vaddvaq_p_s])
3686 (define_insn "mve_vaddvaq_p_<supf><mode>"
3688 (set (match_operand:SI 0 "s_register_operand" "=e")
3689 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
3690 (match_operand:MVE_2 2 "s_register_operand" "w")
3691 (match_operand:HI 3 "vpr_register_operand" "Up")]
3695 "vpst\;vaddvat.<supf>%#<V_sz_elem> %0, %q2"
3696 [(set_attr "type" "mve_move")
3697 (set_attr "length""8")])
3702 (define_insn "mve_vclsq_m_s<mode>"
3704 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3705 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3706 (match_operand:MVE_2 2 "s_register_operand" "w")
3707 (match_operand:HI 3 "vpr_register_operand" "Up")]
3711 "vpst\;vclst.s%#<V_sz_elem> %q0, %q2"
3712 [(set_attr "type" "mve_move")
3713 (set_attr "length""8")])
3716 ;; [vclzq_m_s, vclzq_m_u])
3718 (define_insn "mve_vclzq_m_<supf><mode>"
3720 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3721 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3722 (match_operand:MVE_2 2 "s_register_operand" "w")
3723 (match_operand:HI 3 "vpr_register_operand" "Up")]
3727 "vpst\;vclzt.i%#<V_sz_elem> %q0, %q2"
3728 [(set_attr "type" "mve_move")
3729 (set_attr "length""8")])
3734 (define_insn "mve_vcmpcsq_m_n_u<mode>"
3736 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3737 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3738 (match_operand:<V_elem> 2 "s_register_operand" "r")
3739 (match_operand:HI 3 "vpr_register_operand" "Up")]
3743 "vpst\;vcmpt.u%#<V_sz_elem> cs, %q1, %2"
3744 [(set_attr "type" "mve_move")
3745 (set_attr "length""8")])
3750 (define_insn "mve_vcmpcsq_m_u<mode>"
3752 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3753 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3754 (match_operand:MVE_2 2 "s_register_operand" "w")
3755 (match_operand:HI 3 "vpr_register_operand" "Up")]
3759 "vpst\;vcmpt.u%#<V_sz_elem> cs, %q1, %q2"
3760 [(set_attr "type" "mve_move")
3761 (set_attr "length""8")])
3764 ;; [vcmpeqq_m_n_u, vcmpeqq_m_n_s])
3766 (define_insn "mve_vcmpeqq_m_n_<supf><mode>"
3768 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3769 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3770 (match_operand:<V_elem> 2 "s_register_operand" "r")
3771 (match_operand:HI 3 "vpr_register_operand" "Up")]
3775 "vpst\;vcmpt.i%#<V_sz_elem> eq, %q1, %2"
3776 [(set_attr "type" "mve_move")
3777 (set_attr "length""8")])
3780 ;; [vcmpeqq_m_u, vcmpeqq_m_s])
3782 (define_insn "mve_vcmpeqq_m_<supf><mode>"
3784 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3785 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3786 (match_operand:MVE_2 2 "s_register_operand" "w")
3787 (match_operand:HI 3 "vpr_register_operand" "Up")]
3791 "vpst\;vcmpt.i%#<V_sz_elem> eq, %q1, %q2"
3792 [(set_attr "type" "mve_move")
3793 (set_attr "length""8")])
3798 (define_insn "mve_vcmpgeq_m_n_s<mode>"
3800 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3801 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3802 (match_operand:<V_elem> 2 "s_register_operand" "r")
3803 (match_operand:HI 3 "vpr_register_operand" "Up")]
3807 "vpst\;vcmpt.s%#<V_sz_elem> ge, %q1, %2"
3808 [(set_attr "type" "mve_move")
3809 (set_attr "length""8")])
3814 (define_insn "mve_vcmpgeq_m_s<mode>"
3816 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3817 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3818 (match_operand:MVE_2 2 "s_register_operand" "w")
3819 (match_operand:HI 3 "vpr_register_operand" "Up")]
3823 "vpst\;vcmpt.s%#<V_sz_elem> ge, %q1, %q2"
3824 [(set_attr "type" "mve_move")
3825 (set_attr "length""8")])
3830 (define_insn "mve_vcmpgtq_m_n_s<mode>"
3832 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3833 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3834 (match_operand:<V_elem> 2 "s_register_operand" "r")
3835 (match_operand:HI 3 "vpr_register_operand" "Up")]
3839 "vpst\;vcmpt.s%#<V_sz_elem> gt, %q1, %2"
3840 [(set_attr "type" "mve_move")
3841 (set_attr "length""8")])
3846 (define_insn "mve_vcmpgtq_m_s<mode>"
3848 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3849 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3850 (match_operand:MVE_2 2 "s_register_operand" "w")
3851 (match_operand:HI 3 "vpr_register_operand" "Up")]
3855 "vpst\;vcmpt.s%#<V_sz_elem> gt, %q1, %q2"
3856 [(set_attr "type" "mve_move")
3857 (set_attr "length""8")])
3862 (define_insn "mve_vcmphiq_m_n_u<mode>"
3864 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3865 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3866 (match_operand:<V_elem> 2 "s_register_operand" "r")
3867 (match_operand:HI 3 "vpr_register_operand" "Up")]
3871 "vpst\;vcmpt.u%#<V_sz_elem> hi, %q1, %2"
3872 [(set_attr "type" "mve_move")
3873 (set_attr "length""8")])
3878 (define_insn "mve_vcmphiq_m_u<mode>"
3880 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3881 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3882 (match_operand:MVE_2 2 "s_register_operand" "w")
3883 (match_operand:HI 3 "vpr_register_operand" "Up")]
3887 "vpst\;vcmpt.u%#<V_sz_elem> hi, %q1, %q2"
3888 [(set_attr "type" "mve_move")
3889 (set_attr "length""8")])
3894 (define_insn "mve_vcmpleq_m_n_s<mode>"
3896 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3897 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3898 (match_operand:<V_elem> 2 "s_register_operand" "r")
3899 (match_operand:HI 3 "vpr_register_operand" "Up")]
3903 "vpst\;vcmpt.s%#<V_sz_elem> le, %q1, %2"
3904 [(set_attr "type" "mve_move")
3905 (set_attr "length""8")])
3910 (define_insn "mve_vcmpleq_m_s<mode>"
3912 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3913 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3914 (match_operand:MVE_2 2 "s_register_operand" "w")
3915 (match_operand:HI 3 "vpr_register_operand" "Up")]
3919 "vpst\;vcmpt.s%#<V_sz_elem> le, %q1, %q2"
3920 [(set_attr "type" "mve_move")
3921 (set_attr "length""8")])
3926 (define_insn "mve_vcmpltq_m_n_s<mode>"
3928 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3929 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3930 (match_operand:<V_elem> 2 "s_register_operand" "r")
3931 (match_operand:HI 3 "vpr_register_operand" "Up")]
3935 "vpst\;vcmpt.s%#<V_sz_elem> lt, %q1, %2"
3936 [(set_attr "type" "mve_move")
3937 (set_attr "length""8")])
3942 (define_insn "mve_vcmpltq_m_s<mode>"
3944 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3945 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3946 (match_operand:MVE_2 2 "s_register_operand" "w")
3947 (match_operand:HI 3 "vpr_register_operand" "Up")]
3951 "vpst\;vcmpt.s%#<V_sz_elem> lt, %q1, %q2"
3952 [(set_attr "type" "mve_move")
3953 (set_attr "length""8")])
3956 ;; [vcmpneq_m_n_u, vcmpneq_m_n_s])
3958 (define_insn "mve_vcmpneq_m_n_<supf><mode>"
3960 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3961 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3962 (match_operand:<V_elem> 2 "s_register_operand" "r")
3963 (match_operand:HI 3 "vpr_register_operand" "Up")]
3967 "vpst\;vcmpt.i%#<V_sz_elem> ne, %q1, %2"
3968 [(set_attr "type" "mve_move")
3969 (set_attr "length""8")])
3972 ;; [vcmpneq_m_s, vcmpneq_m_u])
3974 (define_insn "mve_vcmpneq_m_<supf><mode>"
3976 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3977 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3978 (match_operand:MVE_2 2 "s_register_operand" "w")
3979 (match_operand:HI 3 "vpr_register_operand" "Up")]
3983 "vpst\;vcmpt.i%#<V_sz_elem> ne, %q1, %q2"
3984 [(set_attr "type" "mve_move")
3985 (set_attr "length""8")])
3988 ;; [vdupq_m_n_s, vdupq_m_n_u])
3990 (define_insn "mve_vdupq_m_n_<supf><mode>"
3992 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3993 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3994 (match_operand:<V_elem> 2 "s_register_operand" "r")
3995 (match_operand:HI 3 "vpr_register_operand" "Up")]
3999 "vpst\;vdupt.%#<V_sz_elem> %q0, %2"
4000 [(set_attr "type" "mve_move")
4001 (set_attr "length""8")])
4006 (define_insn "mve_vmaxaq_m_s<mode>"
4008 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4009 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4010 (match_operand:MVE_2 2 "s_register_operand" "w")
4011 (match_operand:HI 3 "vpr_register_operand" "Up")]
4015 "vpst\;vmaxat.s%#<V_sz_elem> %q0, %q2"
4016 [(set_attr "type" "mve_move")
4017 (set_attr "length""8")])
4022 (define_insn "mve_vmaxavq_p_s<mode>"
4024 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
4025 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
4026 (match_operand:MVE_2 2 "s_register_operand" "w")
4027 (match_operand:HI 3 "vpr_register_operand" "Up")]
4031 "vpst\;vmaxavt.s%#<V_sz_elem> %0, %q2"
4032 [(set_attr "type" "mve_move")
4033 (set_attr "length""8")])
4036 ;; [vmaxvq_p_u, vmaxvq_p_s])
4038 (define_insn "mve_vmaxvq_p_<supf><mode>"
4040 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
4041 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
4042 (match_operand:MVE_2 2 "s_register_operand" "w")
4043 (match_operand:HI 3 "vpr_register_operand" "Up")]
4047 "vpst\;vmaxvt.<supf>%#<V_sz_elem> %0, %q2"
4048 [(set_attr "type" "mve_move")
4049 (set_attr "length""8")])
4054 (define_insn "mve_vminaq_m_s<mode>"
4056 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4057 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4058 (match_operand:MVE_2 2 "s_register_operand" "w")
4059 (match_operand:HI 3 "vpr_register_operand" "Up")]
4063 "vpst\;vminat.s%#<V_sz_elem> %q0, %q2"
4064 [(set_attr "type" "mve_move")
4065 (set_attr "length""8")])
4070 (define_insn "mve_vminavq_p_s<mode>"
4072 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
4073 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
4074 (match_operand:MVE_2 2 "s_register_operand" "w")
4075 (match_operand:HI 3 "vpr_register_operand" "Up")]
4079 "vpst\;vminavt.s%#<V_sz_elem> %0, %q2"
4080 [(set_attr "type" "mve_move")
4081 (set_attr "length""8")])
4084 ;; [vminvq_p_s, vminvq_p_u])
4086 (define_insn "mve_vminvq_p_<supf><mode>"
4088 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
4089 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
4090 (match_operand:MVE_2 2 "s_register_operand" "w")
4091 (match_operand:HI 3 "vpr_register_operand" "Up")]
4095 "vpst\;vminvt.<supf>%#<V_sz_elem>\t%0, %q2"
4096 [(set_attr "type" "mve_move")
4097 (set_attr "length""8")])
4100 ;; [vmladavaq_u, vmladavaq_s])
4102 (define_insn "mve_vmladavaq_<supf><mode>"
4104 (set (match_operand:SI 0 "s_register_operand" "=e")
4105 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
4106 (match_operand:MVE_2 2 "s_register_operand" "w")
4107 (match_operand:MVE_2 3 "s_register_operand" "w")]
4111 "vmladava.<supf>%#<V_sz_elem> %0, %q2, %q3"
4112 [(set_attr "type" "mve_move")
4116 ;; [vmladavq_p_u, vmladavq_p_s])
4118 (define_insn "mve_vmladavq_p_<supf><mode>"
4120 (set (match_operand:SI 0 "s_register_operand" "=e")
4121 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
4122 (match_operand:MVE_2 2 "s_register_operand" "w")
4123 (match_operand:HI 3 "vpr_register_operand" "Up")]
4127 "vpst\;vmladavt.<supf>%#<V_sz_elem>\t%0, %q1, %q2"
4128 [(set_attr "type" "mve_move")
4129 (set_attr "length""8")])
4134 (define_insn "mve_vmladavxq_p_s<mode>"
4136 (set (match_operand:SI 0 "s_register_operand" "=e")
4137 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
4138 (match_operand:MVE_2 2 "s_register_operand" "w")
4139 (match_operand:HI 3 "vpr_register_operand" "Up")]
4143 "vpst\;vmladavxt.s%#<V_sz_elem>\t%0, %q1, %q2"
4144 [(set_attr "type" "mve_move")
4145 (set_attr "length""8")])
4148 ;; [vmlaq_n_u, vmlaq_n_s])
4150 (define_insn "mve_vmlaq_n_<supf><mode>"
4152 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4153 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4154 (match_operand:MVE_2 2 "s_register_operand" "w")
4155 (match_operand:<V_elem> 3 "s_register_operand" "r")]
4159 "vmla.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
4160 [(set_attr "type" "mve_move")
4164 ;; [vmlasq_n_u, vmlasq_n_s])
4166 (define_insn "mve_vmlasq_n_<supf><mode>"
4168 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4169 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4170 (match_operand:MVE_2 2 "s_register_operand" "w")
4171 (match_operand:<V_elem> 3 "s_register_operand" "r")]
4175 "vmlas.<supf>%#<V_sz_elem> %q0, %q2, %3"
4176 [(set_attr "type" "mve_move")
4182 (define_insn "mve_vmlsdavq_p_s<mode>"
4184 (set (match_operand:SI 0 "s_register_operand" "=e")
4185 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
4186 (match_operand:MVE_2 2 "s_register_operand" "w")
4187 (match_operand:HI 3 "vpr_register_operand" "Up")]
4191 "vpst\;vmlsdavt.s%#<V_sz_elem> %0, %q1, %q2"
4192 [(set_attr "type" "mve_move")
4193 (set_attr "length""8")])
4198 (define_insn "mve_vmlsdavxq_p_s<mode>"
4200 (set (match_operand:SI 0 "s_register_operand" "=e")
4201 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
4202 (match_operand:MVE_2 2 "s_register_operand" "w")
4203 (match_operand:HI 3 "vpr_register_operand" "Up")]
4207 "vpst\;vmlsdavxt.s%#<V_sz_elem> %0, %q1, %q2"
4208 [(set_attr "type" "mve_move")
4209 (set_attr "length""8")])
4212 ;; [vmvnq_m_s, vmvnq_m_u])
4214 (define_insn "mve_vmvnq_m_<supf><mode>"
4216 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4217 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4218 (match_operand:MVE_2 2 "s_register_operand" "w")
4219 (match_operand:HI 3 "vpr_register_operand" "Up")]
4223 "vpst\;vmvnt %q0, %q2"
4224 [(set_attr "type" "mve_move")
4225 (set_attr "length""8")])
4230 (define_insn "mve_vnegq_m_s<mode>"
4232 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4233 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4234 (match_operand:MVE_2 2 "s_register_operand" "w")
4235 (match_operand:HI 3 "vpr_register_operand" "Up")]
4239 "vpst\;vnegt.s%#<V_sz_elem>\t%q0, %q2"
4240 [(set_attr "type" "mve_move")
4241 (set_attr "length""8")])
4244 ;; [vpselq_u, vpselq_s])
4246 (define_insn "mve_vpselq_<supf><mode>"
4248 (set (match_operand:MVE_1 0 "s_register_operand" "=w")
4249 (unspec:MVE_1 [(match_operand:MVE_1 1 "s_register_operand" "w")
4250 (match_operand:MVE_1 2 "s_register_operand" "w")
4251 (match_operand:HI 3 "vpr_register_operand" "Up")]
4255 "vpsel %q0, %q1, %q2"
4256 [(set_attr "type" "mve_move")
4262 (define_insn "mve_vqabsq_m_s<mode>"
4264 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4265 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4266 (match_operand:MVE_2 2 "s_register_operand" "w")
4267 (match_operand:HI 3 "vpr_register_operand" "Up")]
4271 "vpst\;vqabst.s%#<V_sz_elem>\t%q0, %q2"
4272 [(set_attr "type" "mve_move")
4273 (set_attr "length""8")])
4276 ;; [vqdmlahq_n_s, vqdmlahq_n_u])
4278 (define_insn "mve_vqdmlahq_n_<supf><mode>"
4280 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4281 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4282 (match_operand:MVE_2 2 "s_register_operand" "w")
4283 (match_operand:<V_elem> 3 "s_register_operand" "r")]
4287 "vqdmlah.s%#<V_sz_elem>\t%q0, %q2, %3"
4288 [(set_attr "type" "mve_move")
4294 (define_insn "mve_vqnegq_m_s<mode>"
4296 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4297 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4298 (match_operand:MVE_2 2 "s_register_operand" "w")
4299 (match_operand:HI 3 "vpr_register_operand" "Up")]
4303 "vpst\;vqnegt.s%#<V_sz_elem> %q0, %q2"
4304 [(set_attr "type" "mve_move")
4305 (set_attr "length""8")])
4310 (define_insn "mve_vqrdmladhq_s<mode>"
4312 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4313 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4314 (match_operand:MVE_2 2 "s_register_operand" "w")
4315 (match_operand:MVE_2 3 "s_register_operand" "w")]
4319 "vqrdmladh.s%#<V_sz_elem>\t%q0, %q2, %q3"
4320 [(set_attr "type" "mve_move")
4326 (define_insn "mve_vqrdmladhxq_s<mode>"
4328 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4329 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4330 (match_operand:MVE_2 2 "s_register_operand" "w")
4331 (match_operand:MVE_2 3 "s_register_operand" "w")]
4335 "vqrdmladhx.s%#<V_sz_elem>\t%q0, %q2, %q3"
4336 [(set_attr "type" "mve_move")
4340 ;; [vqrdmlahq_n_s, vqrdmlahq_n_u])
4342 (define_insn "mve_vqrdmlahq_n_<supf><mode>"
4344 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4345 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4346 (match_operand:MVE_2 2 "s_register_operand" "w")
4347 (match_operand:<V_elem> 3 "s_register_operand" "r")]
4351 "vqrdmlah.s%#<V_sz_elem>\t%q0, %q2, %3"
4352 [(set_attr "type" "mve_move")
4356 ;; [vqrdmlashq_n_s, vqrdmlashq_n_u])
4358 (define_insn "mve_vqrdmlashq_n_<supf><mode>"
4360 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4361 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4362 (match_operand:MVE_2 2 "s_register_operand" "w")
4363 (match_operand:<V_elem> 3 "s_register_operand" "r")]
4367 "vqrdmlash.s%#<V_sz_elem>\t%q0, %q2, %3"
4368 [(set_attr "type" "mve_move")
4374 (define_insn "mve_vqrdmlsdhq_s<mode>"
4376 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4377 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4378 (match_operand:MVE_2 2 "s_register_operand" "w")
4379 (match_operand:MVE_2 3 "s_register_operand" "w")]
4383 "vqrdmlsdh.s%#<V_sz_elem>\t%q0, %q2, %q3"
4384 [(set_attr "type" "mve_move")
4390 (define_insn "mve_vqrdmlsdhxq_s<mode>"
4392 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4393 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4394 (match_operand:MVE_2 2 "s_register_operand" "w")
4395 (match_operand:MVE_2 3 "s_register_operand" "w")]
4399 "vqrdmlsdhx.s%#<V_sz_elem>\t%q0, %q2, %q3"
4400 [(set_attr "type" "mve_move")
4404 ;; [vqrshlq_m_n_s, vqrshlq_m_n_u])
4406 (define_insn "mve_vqrshlq_m_n_<supf><mode>"
4408 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4409 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4410 (match_operand:SI 2 "s_register_operand" "r")
4411 (match_operand:HI 3 "vpr_register_operand" "Up")]
4415 "vpst\;vqrshlt.<supf>%#<V_sz_elem> %q0, %2"
4416 [(set_attr "type" "mve_move")
4417 (set_attr "length""8")])
4420 ;; [vqshlq_m_r_u, vqshlq_m_r_s])
4422 (define_insn "mve_vqshlq_m_r_<supf><mode>"
4424 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4425 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4426 (match_operand:SI 2 "s_register_operand" "r")
4427 (match_operand:HI 3 "vpr_register_operand" "Up")]
4431 "vpst\;vqshlt.<supf>%#<V_sz_elem>\t%q0, %2"
4432 [(set_attr "type" "mve_move")
4433 (set_attr "length""8")])
4436 ;; [vrev64q_m_u, vrev64q_m_s])
4438 (define_insn "mve_vrev64q_m_<supf><mode>"
4440 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4441 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4442 (match_operand:MVE_2 2 "s_register_operand" "w")
4443 (match_operand:HI 3 "vpr_register_operand" "Up")]
4447 "vpst\;vrev64t.%#<V_sz_elem>\t%q0, %q2"
4448 [(set_attr "type" "mve_move")
4449 (set_attr "length""8")])
4452 ;; [vrshlq_m_n_s, vrshlq_m_n_u])
4454 (define_insn "mve_vrshlq_m_n_<supf><mode>"
4456 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4457 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4458 (match_operand:SI 2 "s_register_operand" "r")
4459 (match_operand:HI 3 "vpr_register_operand" "Up")]
4463 "vpst\;vrshlt.<supf>%#<V_sz_elem>\t%q0, %2"
4464 [(set_attr "type" "mve_move")
4465 (set_attr "length""8")])
4468 ;; [vshlq_m_r_u, vshlq_m_r_s])
4470 (define_insn "mve_vshlq_m_r_<supf><mode>"
4472 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4473 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4474 (match_operand:SI 2 "s_register_operand" "r")
4475 (match_operand:HI 3 "vpr_register_operand" "Up")]
4479 "vpst\;vshlt.<supf>%#<V_sz_elem>\t%q0, %2"
4480 [(set_attr "type" "mve_move")
4481 (set_attr "length""8")])
4484 ;; [vsliq_n_u, vsliq_n_s])
4486 (define_insn "mve_vsliq_n_<supf><mode>"
4488 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4489 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4490 (match_operand:MVE_2 2 "s_register_operand" "w")
4491 (match_operand:SI 3 "<MVE_pred>" "<MVE_constraint>")]
4495 "vsli.%#<V_sz_elem>\t%q0, %q2, %3"
4496 [(set_attr "type" "mve_move")
4500 ;; [vsriq_n_u, vsriq_n_s])
4502 (define_insn "mve_vsriq_n_<supf><mode>"
4504 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4505 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4506 (match_operand:MVE_2 2 "s_register_operand" "w")
4507 (match_operand:SI 3 "mve_imm_selective_upto_8" "Rg")]
4511 "vsri.%#<V_sz_elem>\t%q0, %q2, %3"
4512 [(set_attr "type" "mve_move")
4518 (define_insn "mve_vqdmlsdhxq_s<mode>"
4520 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4521 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4522 (match_operand:MVE_2 2 "s_register_operand" "w")
4523 (match_operand:MVE_2 3 "s_register_operand" "w")]
4527 "vqdmlsdhx.s%#<V_sz_elem>\t%q0, %q2, %q3"
4528 [(set_attr "type" "mve_move")
4534 (define_insn "mve_vqdmlsdhq_s<mode>"
4536 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4537 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4538 (match_operand:MVE_2 2 "s_register_operand" "w")
4539 (match_operand:MVE_2 3 "s_register_operand" "w")]
4543 "vqdmlsdh.s%#<V_sz_elem>\t%q0, %q2, %q3"
4544 [(set_attr "type" "mve_move")
4550 (define_insn "mve_vqdmladhxq_s<mode>"
4552 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4553 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4554 (match_operand:MVE_2 2 "s_register_operand" "w")
4555 (match_operand:MVE_2 3 "s_register_operand" "w")]
4559 "vqdmladhx.s%#<V_sz_elem>\t%q0, %q2, %q3"
4560 [(set_attr "type" "mve_move")
4566 (define_insn "mve_vqdmladhq_s<mode>"
4568 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4569 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4570 (match_operand:MVE_2 2 "s_register_operand" "w")
4571 (match_operand:MVE_2 3 "s_register_operand" "w")]
4575 "vqdmladh.s%#<V_sz_elem>\t%q0, %q2, %q3"
4576 [(set_attr "type" "mve_move")
4582 (define_insn "mve_vmlsdavaxq_s<mode>"
4584 (set (match_operand:SI 0 "s_register_operand" "=e")
4585 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
4586 (match_operand:MVE_2 2 "s_register_operand" "w")
4587 (match_operand:MVE_2 3 "s_register_operand" "w")]
4591 "vmlsdavax.s%#<V_sz_elem>\t%0, %q2, %q3"
4592 [(set_attr "type" "mve_move")
4598 (define_insn "mve_vmlsdavaq_s<mode>"
4600 (set (match_operand:SI 0 "s_register_operand" "=e")
4601 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
4602 (match_operand:MVE_2 2 "s_register_operand" "w")
4603 (match_operand:MVE_2 3 "s_register_operand" "w")]
4607 "vmlsdava.s%#<V_sz_elem>\t%0, %q2, %q3"
4608 [(set_attr "type" "mve_move")
4614 (define_insn "mve_vmladavaxq_s<mode>"
4616 (set (match_operand:SI 0 "s_register_operand" "=e")
4617 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
4618 (match_operand:MVE_2 2 "s_register_operand" "w")
4619 (match_operand:MVE_2 3 "s_register_operand" "w")]
4623 "vmladavax.s%#<V_sz_elem>\t%0, %q2, %q3"
4624 [(set_attr "type" "mve_move")
4629 (define_insn "mve_vabsq_m_f<mode>"
4631 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4632 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4633 (match_operand:MVE_0 2 "s_register_operand" "w")
4634 (match_operand:HI 3 "vpr_register_operand" "Up")]
4637 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4638 "vpst\;vabst.f%#<V_sz_elem> %q0, %q2"
4639 [(set_attr "type" "mve_move")
4640 (set_attr "length""8")])
4643 ;; [vaddlvaq_p_s vaddlvaq_p_u])
4645 (define_insn "mve_vaddlvaq_p_<supf>v4si"
4647 (set (match_operand:DI 0 "s_register_operand" "=r")
4648 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
4649 (match_operand:V4SI 2 "s_register_operand" "w")
4650 (match_operand:HI 3 "vpr_register_operand" "Up")]
4654 "vpst\;vaddlvat.<supf>32 %Q0, %R0, %q2"
4655 [(set_attr "type" "mve_move")
4656 (set_attr "length""8")])
4660 (define_insn "mve_vcmlaq_f<mode>"
4662 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4663 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4664 (match_operand:MVE_0 2 "s_register_operand" "w")
4665 (match_operand:MVE_0 3 "s_register_operand" "w")]
4668 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4669 "vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #0"
4670 [(set_attr "type" "mve_move")
4674 ;; [vcmlaq_rot180_f])
4676 (define_insn "mve_vcmlaq_rot180_f<mode>"
4678 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4679 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4680 (match_operand:MVE_0 2 "s_register_operand" "w")
4681 (match_operand:MVE_0 3 "s_register_operand" "w")]
4684 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4685 "vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #180"
4686 [(set_attr "type" "mve_move")
4690 ;; [vcmlaq_rot270_f])
4692 (define_insn "mve_vcmlaq_rot270_f<mode>"
4694 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4695 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4696 (match_operand:MVE_0 2 "s_register_operand" "w")
4697 (match_operand:MVE_0 3 "s_register_operand" "w")]
4700 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4701 "vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #270"
4702 [(set_attr "type" "mve_move")
4706 ;; [vcmlaq_rot90_f])
4708 (define_insn "mve_vcmlaq_rot90_f<mode>"
4710 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4711 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4712 (match_operand:MVE_0 2 "s_register_operand" "w")
4713 (match_operand:MVE_0 3 "s_register_operand" "w")]
4716 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4717 "vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #90"
4718 [(set_attr "type" "mve_move")
4724 (define_insn "mve_vcmpeqq_m_n_f<mode>"
4726 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4727 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4728 (match_operand:<V_elem> 2 "s_register_operand" "r")
4729 (match_operand:HI 3 "vpr_register_operand" "Up")]
4732 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4733 "vpst\;vcmpt.f%#<V_sz_elem> eq, %q1, %2"
4734 [(set_attr "type" "mve_move")
4735 (set_attr "length""8")])
4740 (define_insn "mve_vcmpgeq_m_f<mode>"
4742 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4743 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4744 (match_operand:MVE_0 2 "s_register_operand" "w")
4745 (match_operand:HI 3 "vpr_register_operand" "Up")]
4748 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4749 "vpst\;vcmpt.f%#<V_sz_elem> ge, %q1, %q2"
4750 [(set_attr "type" "mve_move")
4751 (set_attr "length""8")])
4756 (define_insn "mve_vcmpgeq_m_n_f<mode>"
4758 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4759 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4760 (match_operand:<V_elem> 2 "s_register_operand" "r")
4761 (match_operand:HI 3 "vpr_register_operand" "Up")]
4764 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4765 "vpst\;vcmpt.f%#<V_sz_elem> ge, %q1, %2"
4766 [(set_attr "type" "mve_move")
4767 (set_attr "length""8")])
4772 (define_insn "mve_vcmpgtq_m_f<mode>"
4774 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4775 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4776 (match_operand:MVE_0 2 "s_register_operand" "w")
4777 (match_operand:HI 3 "vpr_register_operand" "Up")]
4780 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4781 "vpst\;vcmpt.f%#<V_sz_elem> gt, %q1, %q2"
4782 [(set_attr "type" "mve_move")
4783 (set_attr "length""8")])
4788 (define_insn "mve_vcmpgtq_m_n_f<mode>"
4790 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4791 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4792 (match_operand:<V_elem> 2 "s_register_operand" "r")
4793 (match_operand:HI 3 "vpr_register_operand" "Up")]
4796 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4797 "vpst\;vcmpt.f%#<V_sz_elem> gt, %q1, %2"
4798 [(set_attr "type" "mve_move")
4799 (set_attr "length""8")])
4804 (define_insn "mve_vcmpleq_m_f<mode>"
4806 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4807 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4808 (match_operand:MVE_0 2 "s_register_operand" "w")
4809 (match_operand:HI 3 "vpr_register_operand" "Up")]
4812 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4813 "vpst\;vcmpt.f%#<V_sz_elem> le, %q1, %q2"
4814 [(set_attr "type" "mve_move")
4815 (set_attr "length""8")])
4820 (define_insn "mve_vcmpleq_m_n_f<mode>"
4822 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4823 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4824 (match_operand:<V_elem> 2 "s_register_operand" "r")
4825 (match_operand:HI 3 "vpr_register_operand" "Up")]
4828 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4829 "vpst\;vcmpt.f%#<V_sz_elem> le, %q1, %2"
4830 [(set_attr "type" "mve_move")
4831 (set_attr "length""8")])
4836 (define_insn "mve_vcmpltq_m_f<mode>"
4838 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4839 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4840 (match_operand:MVE_0 2 "s_register_operand" "w")
4841 (match_operand:HI 3 "vpr_register_operand" "Up")]
4844 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4845 "vpst\;vcmpt.f%#<V_sz_elem> lt, %q1, %q2"
4846 [(set_attr "type" "mve_move")
4847 (set_attr "length""8")])
4852 (define_insn "mve_vcmpltq_m_n_f<mode>"
4854 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4855 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4856 (match_operand:<V_elem> 2 "s_register_operand" "r")
4857 (match_operand:HI 3 "vpr_register_operand" "Up")]
4860 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4861 "vpst\;vcmpt.f%#<V_sz_elem> lt, %q1, %2"
4862 [(set_attr "type" "mve_move")
4863 (set_attr "length""8")])
4868 (define_insn "mve_vcmpneq_m_f<mode>"
4870 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4871 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4872 (match_operand:MVE_0 2 "s_register_operand" "w")
4873 (match_operand:HI 3 "vpr_register_operand" "Up")]
4876 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4877 "vpst\;vcmpt.f%#<V_sz_elem> ne, %q1, %q2"
4878 [(set_attr "type" "mve_move")
4879 (set_attr "length""8")])
4884 (define_insn "mve_vcmpneq_m_n_f<mode>"
4886 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4887 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4888 (match_operand:<V_elem> 2 "s_register_operand" "r")
4889 (match_operand:HI 3 "vpr_register_operand" "Up")]
4892 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4893 "vpst\;vcmpt.f%#<V_sz_elem> ne, %q1, %2"
4894 [(set_attr "type" "mve_move")
4895 (set_attr "length""8")])
4898 ;; [vcvtbq_m_f16_f32])
4900 (define_insn "mve_vcvtbq_m_f16_f32v8hf"
4902 (set (match_operand:V8HF 0 "s_register_operand" "=w")
4903 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
4904 (match_operand:V4SF 2 "s_register_operand" "w")
4905 (match_operand:HI 3 "vpr_register_operand" "Up")]
4908 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4909 "vpst\;vcvtbt.f16.f32 %q0, %q2"
4910 [(set_attr "type" "mve_move")
4911 (set_attr "length""8")])
4914 ;; [vcvtbq_m_f32_f16])
4916 (define_insn "mve_vcvtbq_m_f32_f16v4sf"
4918 (set (match_operand:V4SF 0 "s_register_operand" "=w")
4919 (unspec:V4SF [(match_operand:V4SF 1 "s_register_operand" "0")
4920 (match_operand:V8HF 2 "s_register_operand" "w")
4921 (match_operand:HI 3 "vpr_register_operand" "Up")]
4924 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4925 "vpst\;vcvtbt.f32.f16 %q0, %q2"
4926 [(set_attr "type" "mve_move")
4927 (set_attr "length""8")])
4930 ;; [vcvttq_m_f16_f32])
4932 (define_insn "mve_vcvttq_m_f16_f32v8hf"
4934 (set (match_operand:V8HF 0 "s_register_operand" "=w")
4935 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
4936 (match_operand:V4SF 2 "s_register_operand" "w")
4937 (match_operand:HI 3 "vpr_register_operand" "Up")]
4940 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4941 "vpst\;vcvttt.f16.f32 %q0, %q2"
4942 [(set_attr "type" "mve_move")
4943 (set_attr "length""8")])
4946 ;; [vcvttq_m_f32_f16])
4948 (define_insn "mve_vcvttq_m_f32_f16v4sf"
4950 (set (match_operand:V4SF 0 "s_register_operand" "=w")
4951 (unspec:V4SF [(match_operand:V4SF 1 "s_register_operand" "0")
4952 (match_operand:V8HF 2 "s_register_operand" "w")
4953 (match_operand:HI 3 "vpr_register_operand" "Up")]
4956 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4957 "vpst\;vcvttt.f32.f16 %q0, %q2"
4958 [(set_attr "type" "mve_move")
4959 (set_attr "length""8")])
4964 (define_insn "mve_vdupq_m_n_f<mode>"
4966 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4967 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4968 (match_operand:<V_elem> 2 "s_register_operand" "r")
4969 (match_operand:HI 3 "vpr_register_operand" "Up")]
4972 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4973 "vpst\;vdupt.%#<V_sz_elem> %q0, %2"
4974 [(set_attr "type" "mve_move")
4975 (set_attr "length""8")])
4980 (define_insn "mve_vfmaq_f<mode>"
4982 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4983 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4984 (match_operand:MVE_0 2 "s_register_operand" "w")
4985 (match_operand:MVE_0 3 "s_register_operand" "w")]
4988 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4989 "vfma.f%#<V_sz_elem> %q0, %q2, %q3"
4990 [(set_attr "type" "mve_move")
4996 (define_insn "mve_vfmaq_n_f<mode>"
4998 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4999 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5000 (match_operand:MVE_0 2 "s_register_operand" "w")
5001 (match_operand:<V_elem> 3 "s_register_operand" "r")]
5004 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5005 "vfma.f%#<V_sz_elem> %q0, %q2, %3"
5006 [(set_attr "type" "mve_move")
5012 (define_insn "mve_vfmasq_n_f<mode>"
5014 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5015 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5016 (match_operand:MVE_0 2 "s_register_operand" "w")
5017 (match_operand:<V_elem> 3 "s_register_operand" "r")]
5020 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5021 "vfmas.f%#<V_sz_elem> %q0, %q2, %3"
5022 [(set_attr "type" "mve_move")
5027 (define_insn "mve_vfmsq_f<mode>"
5029 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5030 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5031 (match_operand:MVE_0 2 "s_register_operand" "w")
5032 (match_operand:MVE_0 3 "s_register_operand" "w")]
5035 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5036 "vfms.f%#<V_sz_elem> %q0, %q2, %q3"
5037 [(set_attr "type" "mve_move")
5043 (define_insn "mve_vmaxnmaq_m_f<mode>"
5045 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5046 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5047 (match_operand:MVE_0 2 "s_register_operand" "w")
5048 (match_operand:HI 3 "vpr_register_operand" "Up")]
5051 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5052 "vpst\;vmaxnmat.f%#<V_sz_elem> %q0, %q2"
5053 [(set_attr "type" "mve_move")
5054 (set_attr "length""8")])
5058 (define_insn "mve_vmaxnmavq_p_f<mode>"
5060 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
5061 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
5062 (match_operand:MVE_0 2 "s_register_operand" "w")
5063 (match_operand:HI 3 "vpr_register_operand" "Up")]
5066 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5067 "vpst\;vmaxnmavt.f%#<V_sz_elem> %0, %q2"
5068 [(set_attr "type" "mve_move")
5069 (set_attr "length""8")])
5074 (define_insn "mve_vmaxnmvq_p_f<mode>"
5076 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
5077 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
5078 (match_operand:MVE_0 2 "s_register_operand" "w")
5079 (match_operand:HI 3 "vpr_register_operand" "Up")]
5082 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5083 "vpst\;vmaxnmvt.f%#<V_sz_elem> %0, %q2"
5084 [(set_attr "type" "mve_move")
5085 (set_attr "length""8")])
5089 (define_insn "mve_vminnmaq_m_f<mode>"
5091 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5092 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5093 (match_operand:MVE_0 2 "s_register_operand" "w")
5094 (match_operand:HI 3 "vpr_register_operand" "Up")]
5097 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5098 "vpst\;vminnmat.f%#<V_sz_elem> %q0, %q2"
5099 [(set_attr "type" "mve_move")
5100 (set_attr "length""8")])
5105 (define_insn "mve_vminnmavq_p_f<mode>"
5107 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
5108 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
5109 (match_operand:MVE_0 2 "s_register_operand" "w")
5110 (match_operand:HI 3 "vpr_register_operand" "Up")]
5113 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5114 "vpst\;vminnmavt.f%#<V_sz_elem> %0, %q2"
5115 [(set_attr "type" "mve_move")
5116 (set_attr "length""8")])
5120 (define_insn "mve_vminnmvq_p_f<mode>"
5122 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
5123 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
5124 (match_operand:MVE_0 2 "s_register_operand" "w")
5125 (match_operand:HI 3 "vpr_register_operand" "Up")]
5128 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5129 "vpst\;vminnmvt.f%#<V_sz_elem> %0, %q2"
5130 [(set_attr "type" "mve_move")
5131 (set_attr "length""8")])
5134 ;; [vmlaldavaq_s, vmlaldavaq_u])
5136 (define_insn "mve_vmlaldavaq_<supf><mode>"
5138 (set (match_operand:DI 0 "s_register_operand" "=r")
5139 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
5140 (match_operand:MVE_5 2 "s_register_operand" "w")
5141 (match_operand:MVE_5 3 "s_register_operand" "w")]
5145 "vmlaldava.<supf>%#<V_sz_elem> %Q0, %R0, %q2, %q3"
5146 [(set_attr "type" "mve_move")
5152 (define_insn "mve_vmlaldavaxq_s<mode>"
5154 (set (match_operand:DI 0 "s_register_operand" "=r")
5155 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
5156 (match_operand:MVE_5 2 "s_register_operand" "w")
5157 (match_operand:MVE_5 3 "s_register_operand" "w")]
5161 "vmlaldavax.s%#<V_sz_elem> %Q0, %R0, %q2, %q3"
5162 [(set_attr "type" "mve_move")
5166 ;; [vmlaldavq_p_u, vmlaldavq_p_s])
5168 (define_insn "mve_vmlaldavq_p_<supf><mode>"
5170 (set (match_operand:DI 0 "s_register_operand" "=r")
5171 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
5172 (match_operand:MVE_5 2 "s_register_operand" "w")
5173 (match_operand:HI 3 "vpr_register_operand" "Up")]
5177 "vpst\;vmlaldavt.<supf>%#<V_sz_elem> %Q0, %R0, %q1, %q2"
5178 [(set_attr "type" "mve_move")
5179 (set_attr "length""8")])
5182 ;; [vmlaldavxq_p_s])
5184 (define_insn "mve_vmlaldavxq_p_s<mode>"
5186 (set (match_operand:DI 0 "s_register_operand" "=r")
5187 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
5188 (match_operand:MVE_5 2 "s_register_operand" "w")
5189 (match_operand:HI 3 "vpr_register_operand" "Up")]
5193 "vpst\;vmlaldavxt.s%#<V_sz_elem>\t%Q0, %R0, %q1, %q2"
5194 [(set_attr "type" "mve_move")
5195 (set_attr "length""8")])
5199 (define_insn "mve_vmlsldavaq_s<mode>"
5201 (set (match_operand:DI 0 "s_register_operand" "=r")
5202 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
5203 (match_operand:MVE_5 2 "s_register_operand" "w")
5204 (match_operand:MVE_5 3 "s_register_operand" "w")]
5208 "vmlsldava.s%#<V_sz_elem> %Q0, %R0, %q2, %q3"
5209 [(set_attr "type" "mve_move")
5215 (define_insn "mve_vmlsldavaxq_s<mode>"
5217 (set (match_operand:DI 0 "s_register_operand" "=r")
5218 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
5219 (match_operand:MVE_5 2 "s_register_operand" "w")
5220 (match_operand:MVE_5 3 "s_register_operand" "w")]
5224 "vmlsldavax.s%#<V_sz_elem> %Q0, %R0, %q2, %q3"
5225 [(set_attr "type" "mve_move")
5231 (define_insn "mve_vmlsldavq_p_s<mode>"
5233 (set (match_operand:DI 0 "s_register_operand" "=r")
5234 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
5235 (match_operand:MVE_5 2 "s_register_operand" "w")
5236 (match_operand:HI 3 "vpr_register_operand" "Up")]
5240 "vpst\;vmlsldavt.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
5241 [(set_attr "type" "mve_move")
5242 (set_attr "length""8")])
5245 ;; [vmlsldavxq_p_s])
5247 (define_insn "mve_vmlsldavxq_p_s<mode>"
5249 (set (match_operand:DI 0 "s_register_operand" "=r")
5250 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
5251 (match_operand:MVE_5 2 "s_register_operand" "w")
5252 (match_operand:HI 3 "vpr_register_operand" "Up")]
5256 "vpst\;vmlsldavxt.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
5257 [(set_attr "type" "mve_move")
5258 (set_attr "length""8")])
5260 ;; [vmovlbq_m_u, vmovlbq_m_s])
5262 (define_insn "mve_vmovlbq_m_<supf><mode>"
5264 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
5265 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
5266 (match_operand:MVE_3 2 "s_register_operand" "w")
5267 (match_operand:HI 3 "vpr_register_operand" "Up")]
5271 "vpst\;vmovlbt.<supf>%#<V_sz_elem> %q0, %q2"
5272 [(set_attr "type" "mve_move")
5273 (set_attr "length""8")])
5275 ;; [vmovltq_m_u, vmovltq_m_s])
5277 (define_insn "mve_vmovltq_m_<supf><mode>"
5279 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
5280 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
5281 (match_operand:MVE_3 2 "s_register_operand" "w")
5282 (match_operand:HI 3 "vpr_register_operand" "Up")]
5286 "vpst\;vmovltt.<supf>%#<V_sz_elem> %q0, %q2"
5287 [(set_attr "type" "mve_move")
5288 (set_attr "length""8")])
5290 ;; [vmovnbq_m_u, vmovnbq_m_s])
5292 (define_insn "mve_vmovnbq_m_<supf><mode>"
5294 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5295 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5296 (match_operand:MVE_5 2 "s_register_operand" "w")
5297 (match_operand:HI 3 "vpr_register_operand" "Up")]
5301 "vpst\;vmovnbt.i%#<V_sz_elem> %q0, %q2"
5302 [(set_attr "type" "mve_move")
5303 (set_attr "length""8")])
5306 ;; [vmovntq_m_u, vmovntq_m_s])
5308 (define_insn "mve_vmovntq_m_<supf><mode>"
5310 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5311 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5312 (match_operand:MVE_5 2 "s_register_operand" "w")
5313 (match_operand:HI 3 "vpr_register_operand" "Up")]
5317 "vpst\;vmovntt.i%#<V_sz_elem> %q0, %q2"
5318 [(set_attr "type" "mve_move")
5319 (set_attr "length""8")])
5322 ;; [vmvnq_m_n_u, vmvnq_m_n_s])
5324 (define_insn "mve_vmvnq_m_n_<supf><mode>"
5326 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5327 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5328 (match_operand:SI 2 "immediate_operand" "i")
5329 (match_operand:HI 3 "vpr_register_operand" "Up")]
5333 "vpst\;vmvnt.i%#<V_sz_elem> %q0, %2"
5334 [(set_attr "type" "mve_move")
5335 (set_attr "length""8")])
5339 (define_insn "mve_vnegq_m_f<mode>"
5341 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5342 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5343 (match_operand:MVE_0 2 "s_register_operand" "w")
5344 (match_operand:HI 3 "vpr_register_operand" "Up")]
5347 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5348 "vpst\;vnegt.f%#<V_sz_elem> %q0, %q2"
5349 [(set_attr "type" "mve_move")
5350 (set_attr "length""8")])
5353 ;; [vorrq_m_n_s, vorrq_m_n_u])
5355 (define_insn "mve_vorrq_m_n_<supf><mode>"
5357 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5358 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5359 (match_operand:SI 2 "immediate_operand" "i")
5360 (match_operand:HI 3 "vpr_register_operand" "Up")]
5364 "vpst\;vorrt.i%#<V_sz_elem> %q0, %2"
5365 [(set_attr "type" "mve_move")
5366 (set_attr "length""8")])
5370 (define_insn "mve_vpselq_f<mode>"
5372 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5373 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
5374 (match_operand:MVE_0 2 "s_register_operand" "w")
5375 (match_operand:HI 3 "vpr_register_operand" "Up")]
5378 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5379 "vpsel %q0, %q1, %q2"
5380 [(set_attr "type" "mve_move")
5384 ;; [vqmovnbq_m_s, vqmovnbq_m_u])
5386 (define_insn "mve_vqmovnbq_m_<supf><mode>"
5388 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5389 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5390 (match_operand:MVE_5 2 "s_register_operand" "w")
5391 (match_operand:HI 3 "vpr_register_operand" "Up")]
5395 "vpst\;vqmovnbt.<supf>%#<V_sz_elem> %q0, %q2"
5396 [(set_attr "type" "mve_move")
5397 (set_attr "length""8")])
5400 ;; [vqmovntq_m_u, vqmovntq_m_s])
5402 (define_insn "mve_vqmovntq_m_<supf><mode>"
5404 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5405 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5406 (match_operand:MVE_5 2 "s_register_operand" "w")
5407 (match_operand:HI 3 "vpr_register_operand" "Up")]
5411 "vpst\;vqmovntt.<supf>%#<V_sz_elem> %q0, %q2"
5412 [(set_attr "type" "mve_move")
5413 (set_attr "length""8")])
5418 (define_insn "mve_vqmovunbq_m_s<mode>"
5420 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5421 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5422 (match_operand:MVE_5 2 "s_register_operand" "w")
5423 (match_operand:HI 3 "vpr_register_operand" "Up")]
5427 "vpst\;vqmovunbt.s%#<V_sz_elem> %q0, %q2"
5428 [(set_attr "type" "mve_move")
5429 (set_attr "length""8")])
5434 (define_insn "mve_vqmovuntq_m_s<mode>"
5436 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5437 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5438 (match_operand:MVE_5 2 "s_register_operand" "w")
5439 (match_operand:HI 3 "vpr_register_operand" "Up")]
5443 "vpst\;vqmovuntt.s%#<V_sz_elem> %q0, %q2"
5444 [(set_attr "type" "mve_move")
5445 (set_attr "length""8")])
5448 ;; [vqrshrntq_n_u, vqrshrntq_n_s])
5450 (define_insn "mve_vqrshrntq_n_<supf><mode>"
5452 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5453 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5454 (match_operand:MVE_5 2 "s_register_operand" "w")
5455 (match_operand:SI 3 "mve_imm_8" "Rb")]
5459 "vqrshrnt.<supf>%#<V_sz_elem> %q0, %q2, %3"
5460 [(set_attr "type" "mve_move")
5464 ;; [vqrshruntq_n_s])
5466 (define_insn "mve_vqrshruntq_n_s<mode>"
5468 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5469 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5470 (match_operand:MVE_5 2 "s_register_operand" "w")
5471 (match_operand:SI 3 "mve_imm_8" "Rb")]
5475 "vqrshrunt.s%#<V_sz_elem> %q0, %q2, %3"
5476 [(set_attr "type" "mve_move")
5480 ;; [vqshrnbq_n_u, vqshrnbq_n_s])
5482 (define_insn "mve_vqshrnbq_n_<supf><mode>"
5484 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5485 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5486 (match_operand:MVE_5 2 "s_register_operand" "w")
5487 (match_operand:SI 3 "<MVE_pred1>" "<MVE_constraint1>")]
5491 "vqshrnb.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
5492 [(set_attr "type" "mve_move")
5496 ;; [vqshrntq_n_u, vqshrntq_n_s])
5498 (define_insn "mve_vqshrntq_n_<supf><mode>"
5500 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5501 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5502 (match_operand:MVE_5 2 "s_register_operand" "w")
5503 (match_operand:SI 3 "mve_imm_8" "Rb")]
5507 "vqshrnt.<supf>%#<V_sz_elem> %q0, %q2, %3"
5508 [(set_attr "type" "mve_move")
5514 (define_insn "mve_vqshrunbq_n_s<mode>"
5516 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5517 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5518 (match_operand:MVE_5 2 "s_register_operand" "w")
5519 (match_operand:SI 3 "immediate_operand" "i")]
5523 "vqshrunb.s%#<V_sz_elem> %q0, %q2, %3"
5524 [(set_attr "type" "mve_move")
5530 (define_insn "mve_vqshruntq_n_s<mode>"
5532 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5533 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5534 (match_operand:MVE_5 2 "s_register_operand" "w")
5535 (match_operand:SI 3 "mve_imm_8" "Rb")]
5539 "vqshrunt.s%#<V_sz_elem> %q0, %q2, %3"
5540 [(set_attr "type" "mve_move")
5546 (define_insn "mve_vrev32q_m_fv8hf"
5548 (set (match_operand:V8HF 0 "s_register_operand" "=w")
5549 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
5550 (match_operand:V8HF 2 "s_register_operand" "w")
5551 (match_operand:HI 3 "vpr_register_operand" "Up")]
5554 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5555 "vpst\;vrev32t.16 %q0, %q2"
5556 [(set_attr "type" "mve_move")
5557 (set_attr "length""8")])
5560 ;; [vrev32q_m_s, vrev32q_m_u])
5562 (define_insn "mve_vrev32q_m_<supf><mode>"
5564 (set (match_operand:MVE_3 0 "s_register_operand" "=w")
5565 (unspec:MVE_3 [(match_operand:MVE_3 1 "s_register_operand" "0")
5566 (match_operand:MVE_3 2 "s_register_operand" "w")
5567 (match_operand:HI 3 "vpr_register_operand" "Up")]
5571 "vpst\;vrev32t.%#<V_sz_elem> %q0, %q2"
5572 [(set_attr "type" "mve_move")
5573 (set_attr "length""8")])
5578 (define_insn "mve_vrev64q_m_f<mode>"
5580 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5581 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5582 (match_operand:MVE_0 2 "s_register_operand" "w")
5583 (match_operand:HI 3 "vpr_register_operand" "Up")]
5586 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5587 "vpst\;vrev64t.%#<V_sz_elem> %q0, %q2"
5588 [(set_attr "type" "mve_move")
5589 (set_attr "length""8")])
5592 ;; [vrmlaldavhaxq_s])
5594 (define_insn "mve_vrmlaldavhaxq_sv4si"
5596 (set (match_operand:DI 0 "s_register_operand" "=r")
5597 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
5598 (match_operand:V4SI 2 "s_register_operand" "w")
5599 (match_operand:V4SI 3 "s_register_operand" "w")]
5603 "vrmlaldavhax.s32 %Q0, %R0, %q2, %q3"
5604 [(set_attr "type" "mve_move")
5608 ;; [vrmlaldavhxq_p_s])
5610 (define_insn "mve_vrmlaldavhxq_p_sv4si"
5612 (set (match_operand:DI 0 "s_register_operand" "=r")
5613 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
5614 (match_operand:V4SI 2 "s_register_operand" "w")
5615 (match_operand:HI 3 "vpr_register_operand" "Up")]
5619 "vpst\;vrmlaldavhxt.s32 %Q0, %R0, %q1, %q2"
5620 [(set_attr "type" "mve_move")
5621 (set_attr "length""8")])
5624 ;; [vrmlsldavhaxq_s])
5626 (define_insn "mve_vrmlsldavhaxq_sv4si"
5628 (set (match_operand:DI 0 "s_register_operand" "=r")
5629 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
5630 (match_operand:V4SI 2 "s_register_operand" "w")
5631 (match_operand:V4SI 3 "s_register_operand" "w")]
5635 "vrmlsldavhax.s32 %Q0, %R0, %q2, %q3"
5636 [(set_attr "type" "mve_move")
5640 ;; [vrmlsldavhq_p_s])
5642 (define_insn "mve_vrmlsldavhq_p_sv4si"
5644 (set (match_operand:DI 0 "s_register_operand" "=r")
5645 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
5646 (match_operand:V4SI 2 "s_register_operand" "w")
5647 (match_operand:HI 3 "vpr_register_operand" "Up")]
5651 "vpst\;vrmlsldavht.s32 %Q0, %R0, %q1, %q2"
5652 [(set_attr "type" "mve_move")
5653 (set_attr "length""8")])
5656 ;; [vrmlsldavhxq_p_s])
5658 (define_insn "mve_vrmlsldavhxq_p_sv4si"
5660 (set (match_operand:DI 0 "s_register_operand" "=r")
5661 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
5662 (match_operand:V4SI 2 "s_register_operand" "w")
5663 (match_operand:HI 3 "vpr_register_operand" "Up")]
5667 "vpst\;vrmlsldavhxt.s32 %Q0, %R0, %q1, %q2"
5668 [(set_attr "type" "mve_move")
5669 (set_attr "length""8")])
5674 (define_insn "mve_vrndaq_m_f<mode>"
5676 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5677 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5678 (match_operand:MVE_0 2 "s_register_operand" "w")
5679 (match_operand:HI 3 "vpr_register_operand" "Up")]
5682 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5683 "vpst\;vrintat.f%#<V_sz_elem> %q0, %q2"
5684 [(set_attr "type" "mve_move")
5685 (set_attr "length""8")])
5690 (define_insn "mve_vrndmq_m_f<mode>"
5692 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5693 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5694 (match_operand:MVE_0 2 "s_register_operand" "w")
5695 (match_operand:HI 3 "vpr_register_operand" "Up")]
5698 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5699 "vpst\;vrintmt.f%#<V_sz_elem> %q0, %q2"
5700 [(set_attr "type" "mve_move")
5701 (set_attr "length""8")])
5706 (define_insn "mve_vrndnq_m_f<mode>"
5708 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5709 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5710 (match_operand:MVE_0 2 "s_register_operand" "w")
5711 (match_operand:HI 3 "vpr_register_operand" "Up")]
5714 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5715 "vpst\;vrintnt.f%#<V_sz_elem> %q0, %q2"
5716 [(set_attr "type" "mve_move")
5717 (set_attr "length""8")])
5722 (define_insn "mve_vrndpq_m_f<mode>"
5724 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5725 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5726 (match_operand:MVE_0 2 "s_register_operand" "w")
5727 (match_operand:HI 3 "vpr_register_operand" "Up")]
5730 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5731 "vpst\;vrintpt.f%#<V_sz_elem> %q0, %q2"
5732 [(set_attr "type" "mve_move")
5733 (set_attr "length""8")])
5738 (define_insn "mve_vrndxq_m_f<mode>"
5740 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5741 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5742 (match_operand:MVE_0 2 "s_register_operand" "w")
5743 (match_operand:HI 3 "vpr_register_operand" "Up")]
5746 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5747 "vpst\;vrintxt.f%#<V_sz_elem> %q0, %q2"
5748 [(set_attr "type" "mve_move")
5749 (set_attr "length""8")])
5752 ;; [vrshrnbq_n_s, vrshrnbq_n_u])
5754 (define_insn "mve_vrshrnbq_n_<supf><mode>"
5756 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5757 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5758 (match_operand:MVE_5 2 "s_register_operand" "w")
5759 (match_operand:SI 3 "mve_imm_8" "Rb")]
5763 "vrshrnb.i%#<V_sz_elem> %q0, %q2, %3"
5764 [(set_attr "type" "mve_move")
5768 ;; [vrshrntq_n_u, vrshrntq_n_s])
5770 (define_insn "mve_vrshrntq_n_<supf><mode>"
5772 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5773 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5774 (match_operand:MVE_5 2 "s_register_operand" "w")
5775 (match_operand:SI 3 "mve_imm_8" "Rb")]
5779 "vrshrnt.i%#<V_sz_elem> %q0, %q2, %3"
5780 [(set_attr "type" "mve_move")
5784 ;; [vshrnbq_n_u, vshrnbq_n_s])
5786 (define_insn "mve_vshrnbq_n_<supf><mode>"
5788 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5789 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5790 (match_operand:MVE_5 2 "s_register_operand" "w")
5791 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")]
5795 "vshrnb.i%#<V_sz_elem> %q0, %q2, %3"
5796 [(set_attr "type" "mve_move")
5800 ;; [vshrntq_n_s, vshrntq_n_u])
5802 (define_insn "mve_vshrntq_n_<supf><mode>"
5804 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5805 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5806 (match_operand:MVE_5 2 "s_register_operand" "w")
5807 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")]
5811 "vshrnt.i%#<V_sz_elem>\t%q0, %q2, %3"
5812 [(set_attr "type" "mve_move")
5816 ;; [vcvtmq_m_s, vcvtmq_m_u])
5818 (define_insn "mve_vcvtmq_m_<supf><mode>"
5820 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5821 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5822 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
5823 (match_operand:HI 3 "vpr_register_operand" "Up")]
5826 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5827 "vpst\;vcvtmt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
5828 [(set_attr "type" "mve_move")
5829 (set_attr "length""8")])
5832 ;; [vcvtpq_m_u, vcvtpq_m_s])
5834 (define_insn "mve_vcvtpq_m_<supf><mode>"
5836 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5837 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5838 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
5839 (match_operand:HI 3 "vpr_register_operand" "Up")]
5842 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5843 "vpst\;vcvtpt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
5844 [(set_attr "type" "mve_move")
5845 (set_attr "length""8")])
5848 ;; [vcvtnq_m_s, vcvtnq_m_u])
5850 (define_insn "mve_vcvtnq_m_<supf><mode>"
5852 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5853 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5854 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
5855 (match_operand:HI 3 "vpr_register_operand" "Up")]
5858 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5859 "vpst\;vcvtnt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
5860 [(set_attr "type" "mve_move")
5861 (set_attr "length""8")])
5864 ;; [vcvtq_m_n_from_f_s, vcvtq_m_n_from_f_u])
5866 (define_insn "mve_vcvtq_m_n_from_f_<supf><mode>"
5868 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5869 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5870 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
5871 (match_operand:SI 3 "mve_imm_16" "Rd")
5872 (match_operand:HI 4 "vpr_register_operand" "Up")]
5875 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5876 "vpst\;vcvtt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2, %3"
5877 [(set_attr "type" "mve_move")
5878 (set_attr "length""8")])
5881 ;; [vrev16q_m_u, vrev16q_m_s])
5883 (define_insn "mve_vrev16q_m_<supf>v16qi"
5885 (set (match_operand:V16QI 0 "s_register_operand" "=w")
5886 (unspec:V16QI [(match_operand:V16QI 1 "s_register_operand" "0")
5887 (match_operand:V16QI 2 "s_register_operand" "w")
5888 (match_operand:HI 3 "vpr_register_operand" "Up")]
5892 "vpst\;vrev16t.8 %q0, %q2"
5893 [(set_attr "type" "mve_move")
5894 (set_attr "length""8")])
5897 ;; [vcvtq_m_from_f_u, vcvtq_m_from_f_s])
5899 (define_insn "mve_vcvtq_m_from_f_<supf><mode>"
5901 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5902 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5903 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
5904 (match_operand:HI 3 "vpr_register_operand" "Up")]
5907 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5908 "vpst\;vcvtt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
5909 [(set_attr "type" "mve_move")
5910 (set_attr "length""8")])
5913 ;; [vrmlaldavhq_p_u vrmlaldavhq_p_s])
5915 (define_insn "mve_vrmlaldavhq_p_<supf>v4si"
5917 (set (match_operand:DI 0 "s_register_operand" "=r")
5918 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
5919 (match_operand:V4SI 2 "s_register_operand" "w")
5920 (match_operand:HI 3 "vpr_register_operand" "Up")]
5924 "vpst\;vrmlaldavht.<supf>32 %Q0, %R0, %q1, %q2"
5925 [(set_attr "type" "mve_move")
5926 (set_attr "length""8")])
5929 ;; [vrmlsldavhaq_s])
5931 (define_insn "mve_vrmlsldavhaq_sv4si"
5933 (set (match_operand:DI 0 "s_register_operand" "=r")
5934 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
5935 (match_operand:V4SI 2 "s_register_operand" "w")
5936 (match_operand:V4SI 3 "s_register_operand" "w")]
5940 "vrmlsldavha.s32 %Q0, %R0, %q2, %q3"
5941 [(set_attr "type" "mve_move")
5945 ;; [vabavq_p_s, vabavq_p_u])
5947 (define_insn "mve_vabavq_p_<supf><mode>"
5949 (set (match_operand:SI 0 "s_register_operand" "=r")
5950 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
5951 (match_operand:MVE_2 2 "s_register_operand" "w")
5952 (match_operand:MVE_2 3 "s_register_operand" "w")
5953 (match_operand:HI 4 "vpr_register_operand" "Up")]
5957 "vpst\;vabavt.<supf>%#<V_sz_elem>\t%0, %q2, %q3"
5958 [(set_attr "type" "mve_move")
5964 (define_insn "mve_vqshluq_m_n_s<mode>"
5966 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5967 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5968 (match_operand:MVE_2 2 "s_register_operand" "w")
5969 (match_operand:SI 3 "mve_imm_7" "Ra")
5970 (match_operand:HI 4 "vpr_register_operand" "Up")]
5974 "vpst\n\tvqshlut.s%#<V_sz_elem>\t%q0, %q2, %3"
5975 [(set_attr "type" "mve_move")])
5978 ;; [vshlq_m_s, vshlq_m_u])
5980 (define_insn "mve_vshlq_m_<supf><mode>"
5982 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5983 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5984 (match_operand:MVE_2 2 "s_register_operand" "w")
5985 (match_operand:MVE_2 3 "s_register_operand" "w")
5986 (match_operand:HI 4 "vpr_register_operand" "Up")]
5990 "vpst\;vshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
5991 [(set_attr "type" "mve_move")])
5994 ;; [vsriq_m_n_s, vsriq_m_n_u])
5996 (define_insn "mve_vsriq_m_n_<supf><mode>"
5998 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5999 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6000 (match_operand:MVE_2 2 "s_register_operand" "w")
6001 (match_operand:SI 3 "mve_imm_selective_upto_8" "Rg")
6002 (match_operand:HI 4 "vpr_register_operand" "Up")]
6006 "vpst\;vsrit.%#<V_sz_elem>\t%q0, %q2, %3"
6007 [(set_attr "type" "mve_move")])
6010 ;; [vsubq_m_u, vsubq_m_s])
6012 (define_insn "mve_vsubq_m_<supf><mode>"
6014 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6015 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6016 (match_operand:MVE_2 2 "s_register_operand" "w")
6017 (match_operand:MVE_2 3 "s_register_operand" "w")
6018 (match_operand:HI 4 "vpr_register_operand" "Up")]
6022 "vpst\;vsubt.i%#<V_sz_elem>\t%q0, %q2, %q3"
6023 [(set_attr "type" "mve_move")])
6026 ;; [vcvtq_m_n_to_f_u, vcvtq_m_n_to_f_s])
6028 (define_insn "mve_vcvtq_m_n_to_f_<supf><mode>"
6030 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
6031 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
6032 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
6033 (match_operand:SI 3 "mve_imm_16" "Rd")
6034 (match_operand:HI 4 "vpr_register_operand" "Up")]
6037 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
6038 "vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
6039 [(set_attr "type" "mve_move")
6040 (set_attr "length""8")])
6042 ;; [vabdq_m_s, vabdq_m_u])
6044 (define_insn "mve_vabdq_m_<supf><mode>"
6046 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6047 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6048 (match_operand:MVE_2 2 "s_register_operand" "w")
6049 (match_operand:MVE_2 3 "s_register_operand" "w")
6050 (match_operand:HI 4 "vpr_register_operand" "Up")]
6054 "vpst\;vabdt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
6055 [(set_attr "type" "mve_move")
6056 (set_attr "length""8")])
6059 ;; [vaddq_m_n_s, vaddq_m_n_u])
6061 (define_insn "mve_vaddq_m_n_<supf><mode>"
6063 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6064 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6065 (match_operand:MVE_2 2 "s_register_operand" "w")
6066 (match_operand:<V_elem> 3 "s_register_operand" "r")
6067 (match_operand:HI 4 "vpr_register_operand" "Up")]
6071 "vpst\;vaddt.i%#<V_sz_elem> %q0, %q2, %3"
6072 [(set_attr "type" "mve_move")
6073 (set_attr "length""8")])
6076 ;; [vaddq_m_u, vaddq_m_s])
6078 (define_insn "mve_vaddq_m_<supf><mode>"
6080 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6081 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6082 (match_operand:MVE_2 2 "s_register_operand" "w")
6083 (match_operand:MVE_2 3 "s_register_operand" "w")
6084 (match_operand:HI 4 "vpr_register_operand" "Up")]
6088 "vpst\;vaddt.i%#<V_sz_elem> %q0, %q2, %q3"
6089 [(set_attr "type" "mve_move")
6090 (set_attr "length""8")])
6093 ;; [vandq_m_u, vandq_m_s])
6095 (define_insn "mve_vandq_m_<supf><mode>"
6097 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6098 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6099 (match_operand:MVE_2 2 "s_register_operand" "w")
6100 (match_operand:MVE_2 3 "s_register_operand" "w")
6101 (match_operand:HI 4 "vpr_register_operand" "Up")]
6105 "vpst\;vandt %q0, %q2, %q3"
6106 [(set_attr "type" "mve_move")
6107 (set_attr "length""8")])
6110 ;; [vbicq_m_u, vbicq_m_s])
6112 (define_insn "mve_vbicq_m_<supf><mode>"
6114 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6115 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6116 (match_operand:MVE_2 2 "s_register_operand" "w")
6117 (match_operand:MVE_2 3 "s_register_operand" "w")
6118 (match_operand:HI 4 "vpr_register_operand" "Up")]
6122 "vpst\;vbict %q0, %q2, %q3"
6123 [(set_attr "type" "mve_move")
6124 (set_attr "length""8")])
6127 ;; [vbrsrq_m_n_u, vbrsrq_m_n_s])
6129 (define_insn "mve_vbrsrq_m_n_<supf><mode>"
6131 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6132 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6133 (match_operand:MVE_2 2 "s_register_operand" "w")
6134 (match_operand:SI 3 "s_register_operand" "r")
6135 (match_operand:HI 4 "vpr_register_operand" "Up")]
6139 "vpst\;vbrsrt.%#<V_sz_elem> %q0, %q2, %3"
6140 [(set_attr "type" "mve_move")
6141 (set_attr "length""8")])
6144 ;; [vcaddq_rot270_m_u, vcaddq_rot270_m_s])
6146 (define_insn "mve_vcaddq_rot270_m_<supf><mode>"
6148 (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
6149 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6150 (match_operand:MVE_2 2 "s_register_operand" "w")
6151 (match_operand:MVE_2 3 "s_register_operand" "w")
6152 (match_operand:HI 4 "vpr_register_operand" "Up")]
6156 "vpst\;vcaddt.i%#<V_sz_elem> %q0, %q2, %q3, #270"
6157 [(set_attr "type" "mve_move")
6158 (set_attr "length""8")])
6161 ;; [vcaddq_rot90_m_u, vcaddq_rot90_m_s])
6163 (define_insn "mve_vcaddq_rot90_m_<supf><mode>"
6165 (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
6166 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6167 (match_operand:MVE_2 2 "s_register_operand" "w")
6168 (match_operand:MVE_2 3 "s_register_operand" "w")
6169 (match_operand:HI 4 "vpr_register_operand" "Up")]
6173 "vpst\;vcaddt.i%#<V_sz_elem> %q0, %q2, %q3, #90"
6174 [(set_attr "type" "mve_move")
6175 (set_attr "length""8")])
6178 ;; [veorq_m_s, veorq_m_u])
6180 (define_insn "mve_veorq_m_<supf><mode>"
6182 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6183 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6184 (match_operand:MVE_2 2 "s_register_operand" "w")
6185 (match_operand:MVE_2 3 "s_register_operand" "w")
6186 (match_operand:HI 4 "vpr_register_operand" "Up")]
6190 "vpst\;veort %q0, %q2, %q3"
6191 [(set_attr "type" "mve_move")
6192 (set_attr "length""8")])
6195 ;; [vhaddq_m_n_s, vhaddq_m_n_u])
6197 (define_insn "mve_vhaddq_m_n_<supf><mode>"
6199 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6200 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6201 (match_operand:MVE_2 2 "s_register_operand" "w")
6202 (match_operand:<V_elem> 3 "s_register_operand" "r")
6203 (match_operand:HI 4 "vpr_register_operand" "Up")]
6207 "vpst\;vhaddt.<supf>%#<V_sz_elem> %q0, %q2, %3"
6208 [(set_attr "type" "mve_move")
6209 (set_attr "length""8")])
6212 ;; [vhaddq_m_s, vhaddq_m_u])
6214 (define_insn "mve_vhaddq_m_<supf><mode>"
6216 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6217 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6218 (match_operand:MVE_2 2 "s_register_operand" "w")
6219 (match_operand:MVE_2 3 "s_register_operand" "w")
6220 (match_operand:HI 4 "vpr_register_operand" "Up")]
6224 "vpst\;vhaddt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
6225 [(set_attr "type" "mve_move")
6226 (set_attr "length""8")])
6229 ;; [vhsubq_m_n_s, vhsubq_m_n_u])
6231 (define_insn "mve_vhsubq_m_n_<supf><mode>"
6233 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6234 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6235 (match_operand:MVE_2 2 "s_register_operand" "w")
6236 (match_operand:<V_elem> 3 "s_register_operand" "r")
6237 (match_operand:HI 4 "vpr_register_operand" "Up")]
6241 "vpst\;vhsubt.<supf>%#<V_sz_elem> %q0, %q2, %3"
6242 [(set_attr "type" "mve_move")
6243 (set_attr "length""8")])
6246 ;; [vhsubq_m_s, vhsubq_m_u])
6248 (define_insn "mve_vhsubq_m_<supf><mode>"
6250 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6251 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6252 (match_operand:MVE_2 2 "s_register_operand" "w")
6253 (match_operand:MVE_2 3 "s_register_operand" "w")
6254 (match_operand:HI 4 "vpr_register_operand" "Up")]
6258 "vpst\;vhsubt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
6259 [(set_attr "type" "mve_move")
6260 (set_attr "length""8")])
6263 ;; [vmaxq_m_s, vmaxq_m_u])
6265 (define_insn "mve_vmaxq_m_<supf><mode>"
6267 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6268 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6269 (match_operand:MVE_2 2 "s_register_operand" "w")
6270 (match_operand:MVE_2 3 "s_register_operand" "w")
6271 (match_operand:HI 4 "vpr_register_operand" "Up")]
6275 "vpst\;vmaxt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
6276 [(set_attr "type" "mve_move")
6277 (set_attr "length""8")])
6280 ;; [vminq_m_s, vminq_m_u])
6282 (define_insn "mve_vminq_m_<supf><mode>"
6284 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6285 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6286 (match_operand:MVE_2 2 "s_register_operand" "w")
6287 (match_operand:MVE_2 3 "s_register_operand" "w")
6288 (match_operand:HI 4 "vpr_register_operand" "Up")]
6292 "vpst\;vmint.<supf>%#<V_sz_elem> %q0, %q2, %q3"
6293 [(set_attr "type" "mve_move")
6294 (set_attr "length""8")])
6297 ;; [vmladavaq_p_u, vmladavaq_p_s])
6299 (define_insn "mve_vmladavaq_p_<supf><mode>"
6301 (set (match_operand:SI 0 "s_register_operand" "=e")
6302 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
6303 (match_operand:MVE_2 2 "s_register_operand" "w")
6304 (match_operand:MVE_2 3 "s_register_operand" "w")
6305 (match_operand:HI 4 "vpr_register_operand" "Up")]
6309 "vpst\;vmladavat.<supf>%#<V_sz_elem> %0, %q2, %q3"
6310 [(set_attr "type" "mve_move")
6311 (set_attr "length""8")])
6314 ;; [vmlaq_m_n_s, vmlaq_m_n_u])
6316 (define_insn "mve_vmlaq_m_n_<supf><mode>"
6318 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6319 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6320 (match_operand:MVE_2 2 "s_register_operand" "w")
6321 (match_operand:<V_elem> 3 "s_register_operand" "r")
6322 (match_operand:HI 4 "vpr_register_operand" "Up")]
6326 "vpst\;vmlat.<supf>%#<V_sz_elem> %q0, %q2, %3"
6327 [(set_attr "type" "mve_move")
6328 (set_attr "length""8")])
6331 ;; [vmlasq_m_n_u, vmlasq_m_n_s])
6333 (define_insn "mve_vmlasq_m_n_<supf><mode>"
6335 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6336 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6337 (match_operand:MVE_2 2 "s_register_operand" "w")
6338 (match_operand:<V_elem> 3 "s_register_operand" "r")
6339 (match_operand:HI 4 "vpr_register_operand" "Up")]
6343 "vpst\;vmlast.<supf>%#<V_sz_elem> %q0, %q2, %3"
6344 [(set_attr "type" "mve_move")
6345 (set_attr "length""8")])
6348 ;; [vmulhq_m_s, vmulhq_m_u])
6350 (define_insn "mve_vmulhq_m_<supf><mode>"
6352 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6353 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6354 (match_operand:MVE_2 2 "s_register_operand" "w")
6355 (match_operand:MVE_2 3 "s_register_operand" "w")
6356 (match_operand:HI 4 "vpr_register_operand" "Up")]
6360 "vpst\;vmulht.<supf>%#<V_sz_elem> %q0, %q2, %q3"
6361 [(set_attr "type" "mve_move")
6362 (set_attr "length""8")])
6365 ;; [vmullbq_int_m_u, vmullbq_int_m_s])
6367 (define_insn "mve_vmullbq_int_m_<supf><mode>"
6369 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
6370 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
6371 (match_operand:MVE_2 2 "s_register_operand" "w")
6372 (match_operand:MVE_2 3 "s_register_operand" "w")
6373 (match_operand:HI 4 "vpr_register_operand" "Up")]
6377 "vpst\;vmullbt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
6378 [(set_attr "type" "mve_move")
6379 (set_attr "length""8")])
6382 ;; [vmulltq_int_m_s, vmulltq_int_m_u])
6384 (define_insn "mve_vmulltq_int_m_<supf><mode>"
6386 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
6387 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
6388 (match_operand:MVE_2 2 "s_register_operand" "w")
6389 (match_operand:MVE_2 3 "s_register_operand" "w")
6390 (match_operand:HI 4 "vpr_register_operand" "Up")]
6394 "vpst\;vmulltt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
6395 [(set_attr "type" "mve_move")
6396 (set_attr "length""8")])
6399 ;; [vmulq_m_n_u, vmulq_m_n_s])
6401 (define_insn "mve_vmulq_m_n_<supf><mode>"
6403 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6404 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6405 (match_operand:MVE_2 2 "s_register_operand" "w")
6406 (match_operand:<V_elem> 3 "s_register_operand" "r")
6407 (match_operand:HI 4 "vpr_register_operand" "Up")]
6411 "vpst\;vmult.i%#<V_sz_elem> %q0, %q2, %3"
6412 [(set_attr "type" "mve_move")
6413 (set_attr "length""8")])
6416 ;; [vmulq_m_s, vmulq_m_u])
6418 (define_insn "mve_vmulq_m_<supf><mode>"
6420 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6421 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6422 (match_operand:MVE_2 2 "s_register_operand" "w")
6423 (match_operand:MVE_2 3 "s_register_operand" "w")
6424 (match_operand:HI 4 "vpr_register_operand" "Up")]
6428 "vpst\;vmult.i%#<V_sz_elem> %q0, %q2, %q3"
6429 [(set_attr "type" "mve_move")
6430 (set_attr "length""8")])
6433 ;; [vornq_m_u, vornq_m_s])
6435 (define_insn "mve_vornq_m_<supf><mode>"
6437 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6438 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6439 (match_operand:MVE_2 2 "s_register_operand" "w")
6440 (match_operand:MVE_2 3 "s_register_operand" "w")
6441 (match_operand:HI 4 "vpr_register_operand" "Up")]
6445 "vpst\;vornt %q0, %q2, %q3"
6446 [(set_attr "type" "mve_move")
6447 (set_attr "length""8")])
6450 ;; [vorrq_m_s, vorrq_m_u])
6452 (define_insn "mve_vorrq_m_<supf><mode>"
6454 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6455 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6456 (match_operand:MVE_2 2 "s_register_operand" "w")
6457 (match_operand:MVE_2 3 "s_register_operand" "w")
6458 (match_operand:HI 4 "vpr_register_operand" "Up")]
6462 "vpst\;vorrt %q0, %q2, %q3"
6463 [(set_attr "type" "mve_move")
6464 (set_attr "length""8")])
6467 ;; [vqaddq_m_n_u, vqaddq_m_n_s])
6469 (define_insn "mve_vqaddq_m_n_<supf><mode>"
6471 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6472 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6473 (match_operand:MVE_2 2 "s_register_operand" "w")
6474 (match_operand:<V_elem> 3 "s_register_operand" "r")
6475 (match_operand:HI 4 "vpr_register_operand" "Up")]
6479 "vpst\;vqaddt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
6480 [(set_attr "type" "mve_move")
6481 (set_attr "length""8")])
6484 ;; [vqaddq_m_u, vqaddq_m_s])
6486 (define_insn "mve_vqaddq_m_<supf><mode>"
6488 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6489 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6490 (match_operand:MVE_2 2 "s_register_operand" "w")
6491 (match_operand:MVE_2 3 "s_register_operand" "w")
6492 (match_operand:HI 4 "vpr_register_operand" "Up")]
6496 "vpst\;vqaddt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
6497 [(set_attr "type" "mve_move")
6498 (set_attr "length""8")])
6501 ;; [vqdmlahq_m_n_s])
6503 (define_insn "mve_vqdmlahq_m_n_s<mode>"
6505 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6506 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6507 (match_operand:MVE_2 2 "s_register_operand" "w")
6508 (match_operand:<V_elem> 3 "s_register_operand" "r")
6509 (match_operand:HI 4 "vpr_register_operand" "Up")]
6513 "vpst\;vqdmlaht.s%#<V_sz_elem>\t%q0, %q2, %3"
6514 [(set_attr "type" "mve_move")
6515 (set_attr "length""8")])
6518 ;; [vqrdmlahq_m_n_s])
6520 (define_insn "mve_vqrdmlahq_m_n_s<mode>"
6522 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6523 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6524 (match_operand:MVE_2 2 "s_register_operand" "w")
6525 (match_operand:<V_elem> 3 "s_register_operand" "r")
6526 (match_operand:HI 4 "vpr_register_operand" "Up")]
6530 "vpst\;vqrdmlaht.s%#<V_sz_elem>\t%q0, %q2, %3"
6531 [(set_attr "type" "mve_move")
6532 (set_attr "length""8")])
6535 ;; [vqrdmlashq_m_n_s])
6537 (define_insn "mve_vqrdmlashq_m_n_s<mode>"
6539 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6540 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6541 (match_operand:MVE_2 2 "s_register_operand" "w")
6542 (match_operand:<V_elem> 3 "s_register_operand" "r")
6543 (match_operand:HI 4 "vpr_register_operand" "Up")]
6547 "vpst\;vqrdmlasht.s%#<V_sz_elem>\t%q0, %q2, %3"
6548 [(set_attr "type" "mve_move")
6549 (set_attr "length""8")])
6552 ;; [vqrshlq_m_u, vqrshlq_m_s])
6554 (define_insn "mve_vqrshlq_m_<supf><mode>"
6556 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6557 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6558 (match_operand:MVE_2 2 "s_register_operand" "w")
6559 (match_operand:MVE_2 3 "s_register_operand" "w")
6560 (match_operand:HI 4 "vpr_register_operand" "Up")]
6564 "vpst\;vqrshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
6565 [(set_attr "type" "mve_move")
6566 (set_attr "length""8")])
6569 ;; [vqshlq_m_n_s, vqshlq_m_n_u])
6571 (define_insn "mve_vqshlq_m_n_<supf><mode>"
6573 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6574 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6575 (match_operand:MVE_2 2 "s_register_operand" "w")
6576 (match_operand:SI 3 "immediate_operand" "i")
6577 (match_operand:HI 4 "vpr_register_operand" "Up")]
6581 "vpst\;vqshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
6582 [(set_attr "type" "mve_move")
6583 (set_attr "length""8")])
6586 ;; [vqshlq_m_u, vqshlq_m_s])
6588 (define_insn "mve_vqshlq_m_<supf><mode>"
6590 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6591 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6592 (match_operand:MVE_2 2 "s_register_operand" "w")
6593 (match_operand:MVE_2 3 "s_register_operand" "w")
6594 (match_operand:HI 4 "vpr_register_operand" "Up")]
6598 "vpst\;vqshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
6599 [(set_attr "type" "mve_move")
6600 (set_attr "length""8")])
6603 ;; [vqsubq_m_n_u, vqsubq_m_n_s])
6605 (define_insn "mve_vqsubq_m_n_<supf><mode>"
6607 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6608 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6609 (match_operand:MVE_2 2 "s_register_operand" "w")
6610 (match_operand:<V_elem> 3 "s_register_operand" "r")
6611 (match_operand:HI 4 "vpr_register_operand" "Up")]
6615 "vpst\;vqsubt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
6616 [(set_attr "type" "mve_move")
6617 (set_attr "length""8")])
6620 ;; [vqsubq_m_u, vqsubq_m_s])
6622 (define_insn "mve_vqsubq_m_<supf><mode>"
6624 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6625 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6626 (match_operand:MVE_2 2 "s_register_operand" "w")
6627 (match_operand:MVE_2 3 "s_register_operand" "w")
6628 (match_operand:HI 4 "vpr_register_operand" "Up")]
6632 "vpst\;vqsubt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
6633 [(set_attr "type" "mve_move")
6634 (set_attr "length""8")])
6637 ;; [vrhaddq_m_u, vrhaddq_m_s])
6639 (define_insn "mve_vrhaddq_m_<supf><mode>"
6641 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6642 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6643 (match_operand:MVE_2 2 "s_register_operand" "w")
6644 (match_operand:MVE_2 3 "s_register_operand" "w")
6645 (match_operand:HI 4 "vpr_register_operand" "Up")]
6649 "vpst\;vrhaddt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
6650 [(set_attr "type" "mve_move")
6651 (set_attr "length""8")])
6654 ;; [vrmulhq_m_u, vrmulhq_m_s])
6656 (define_insn "mve_vrmulhq_m_<supf><mode>"
6658 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6659 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6660 (match_operand:MVE_2 2 "s_register_operand" "w")
6661 (match_operand:MVE_2 3 "s_register_operand" "w")
6662 (match_operand:HI 4 "vpr_register_operand" "Up")]
6666 "vpst\;vrmulht.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
6667 [(set_attr "type" "mve_move")
6668 (set_attr "length""8")])
6671 ;; [vrshlq_m_s, vrshlq_m_u])
6673 (define_insn "mve_vrshlq_m_<supf><mode>"
6675 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6676 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6677 (match_operand:MVE_2 2 "s_register_operand" "w")
6678 (match_operand:MVE_2 3 "s_register_operand" "w")
6679 (match_operand:HI 4 "vpr_register_operand" "Up")]
6683 "vpst\;vrshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
6684 [(set_attr "type" "mve_move")
6685 (set_attr "length""8")])
6688 ;; [vrshrq_m_n_s, vrshrq_m_n_u])
6690 (define_insn "mve_vrshrq_m_n_<supf><mode>"
6692 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6693 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6694 (match_operand:MVE_2 2 "s_register_operand" "w")
6695 (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>")
6696 (match_operand:HI 4 "vpr_register_operand" "Up")]
6700 "vpst\;vrshrt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
6701 [(set_attr "type" "mve_move")
6702 (set_attr "length""8")])
6705 ;; [vshlq_m_n_s, vshlq_m_n_u])
6707 (define_insn "mve_vshlq_m_n_<supf><mode>"
6709 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6710 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6711 (match_operand:MVE_2 2 "s_register_operand" "w")
6712 (match_operand:SI 3 "immediate_operand" "i")
6713 (match_operand:HI 4 "vpr_register_operand" "Up")]
6717 "vpst\;vshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
6718 [(set_attr "type" "mve_move")
6719 (set_attr "length""8")])
6722 ;; [vshrq_m_n_s, vshrq_m_n_u])
6724 (define_insn "mve_vshrq_m_n_<supf><mode>"
6726 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6727 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6728 (match_operand:MVE_2 2 "s_register_operand" "w")
6729 (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>")
6730 (match_operand:HI 4 "vpr_register_operand" "Up")]
6734 "vpst\;vshrt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
6735 [(set_attr "type" "mve_move")
6736 (set_attr "length""8")])
6739 ;; [vsliq_m_n_u, vsliq_m_n_s])
6741 (define_insn "mve_vsliq_m_n_<supf><mode>"
6743 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6744 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6745 (match_operand:MVE_2 2 "s_register_operand" "w")
6746 (match_operand:SI 3 "<MVE_pred>" "<MVE_constraint>")
6747 (match_operand:HI 4 "vpr_register_operand" "Up")]
6751 "vpst\;vslit.%#<V_sz_elem>\t%q0, %q2, %3"
6752 [(set_attr "type" "mve_move")
6753 (set_attr "length""8")])
6756 ;; [vsubq_m_n_s, vsubq_m_n_u])
6758 (define_insn "mve_vsubq_m_n_<supf><mode>"
6760 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6761 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6762 (match_operand:MVE_2 2 "s_register_operand" "w")
6763 (match_operand:<V_elem> 3 "s_register_operand" "r")
6764 (match_operand:HI 4 "vpr_register_operand" "Up")]
6768 "vpst\;vsubt.i%#<V_sz_elem>\t%q0, %q2, %3"
6769 [(set_attr "type" "mve_move")
6770 (set_attr "length""8")])
6773 ;; [vhcaddq_rot270_m_s])
6775 (define_insn "mve_vhcaddq_rot270_m_s<mode>"
6777 (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
6778 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6779 (match_operand:MVE_2 2 "s_register_operand" "w")
6780 (match_operand:MVE_2 3 "s_register_operand" "w")
6781 (match_operand:HI 4 "vpr_register_operand" "Up")]
6782 VHCADDQ_ROT270_M_S))
6785 "vpst\;vhcaddt.s%#<V_sz_elem>\t%q0, %q2, %q3, #270"
6786 [(set_attr "type" "mve_move")
6787 (set_attr "length""8")])
6790 ;; [vhcaddq_rot90_m_s])
6792 (define_insn "mve_vhcaddq_rot90_m_s<mode>"
6794 (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
6795 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6796 (match_operand:MVE_2 2 "s_register_operand" "w")
6797 (match_operand:MVE_2 3 "s_register_operand" "w")
6798 (match_operand:HI 4 "vpr_register_operand" "Up")]
6802 "vpst\;vhcaddt.s%#<V_sz_elem>\t%q0, %q2, %q3, #90"
6803 [(set_attr "type" "mve_move")
6804 (set_attr "length""8")])
6807 ;; [vmladavaxq_p_s])
6809 (define_insn "mve_vmladavaxq_p_s<mode>"
6811 (set (match_operand:SI 0 "s_register_operand" "=e")
6812 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
6813 (match_operand:MVE_2 2 "s_register_operand" "w")
6814 (match_operand:MVE_2 3 "s_register_operand" "w")
6815 (match_operand:HI 4 "vpr_register_operand" "Up")]
6819 "vpst\;vmladavaxt.s%#<V_sz_elem>\t%0, %q2, %q3"
6820 [(set_attr "type" "mve_move")
6821 (set_attr "length""8")])
6826 (define_insn "mve_vmlsdavaq_p_s<mode>"
6828 (set (match_operand:SI 0 "s_register_operand" "=e")
6829 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
6830 (match_operand:MVE_2 2 "s_register_operand" "w")
6831 (match_operand:MVE_2 3 "s_register_operand" "w")
6832 (match_operand:HI 4 "vpr_register_operand" "Up")]
6836 "vpst\;vmlsdavat.s%#<V_sz_elem>\t%0, %q2, %q3"
6837 [(set_attr "type" "mve_move")
6838 (set_attr "length""8")])
6841 ;; [vmlsdavaxq_p_s])
6843 (define_insn "mve_vmlsdavaxq_p_s<mode>"
6845 (set (match_operand:SI 0 "s_register_operand" "=e")
6846 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
6847 (match_operand:MVE_2 2 "s_register_operand" "w")
6848 (match_operand:MVE_2 3 "s_register_operand" "w")
6849 (match_operand:HI 4 "vpr_register_operand" "Up")]
6853 "vpst\;vmlsdavaxt.s%#<V_sz_elem>\t%0, %q2, %q3"
6854 [(set_attr "type" "mve_move")
6855 (set_attr "length""8")])
6860 (define_insn "mve_vqdmladhq_m_s<mode>"
6862 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6863 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6864 (match_operand:MVE_2 2 "s_register_operand" "w")
6865 (match_operand:MVE_2 3 "s_register_operand" "w")
6866 (match_operand:HI 4 "vpr_register_operand" "Up")]
6870 "vpst\;vqdmladht.s%#<V_sz_elem>\t%q0, %q2, %q3"
6871 [(set_attr "type" "mve_move")
6872 (set_attr "length""8")])
6875 ;; [vqdmladhxq_m_s])
6877 (define_insn "mve_vqdmladhxq_m_s<mode>"
6879 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6880 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6881 (match_operand:MVE_2 2 "s_register_operand" "w")
6882 (match_operand:MVE_2 3 "s_register_operand" "w")
6883 (match_operand:HI 4 "vpr_register_operand" "Up")]
6887 "vpst\;vqdmladhxt.s%#<V_sz_elem>\t%q0, %q2, %q3"
6888 [(set_attr "type" "mve_move")
6889 (set_attr "length""8")])
6894 (define_insn "mve_vqdmlsdhq_m_s<mode>"
6896 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6897 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6898 (match_operand:MVE_2 2 "s_register_operand" "w")
6899 (match_operand:MVE_2 3 "s_register_operand" "w")
6900 (match_operand:HI 4 "vpr_register_operand" "Up")]
6904 "vpst\;vqdmlsdht.s%#<V_sz_elem>\t%q0, %q2, %q3"
6905 [(set_attr "type" "mve_move")
6906 (set_attr "length""8")])
6909 ;; [vqdmlsdhxq_m_s])
6911 (define_insn "mve_vqdmlsdhxq_m_s<mode>"
6913 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6914 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6915 (match_operand:MVE_2 2 "s_register_operand" "w")
6916 (match_operand:MVE_2 3 "s_register_operand" "w")
6917 (match_operand:HI 4 "vpr_register_operand" "Up")]
6921 "vpst\;vqdmlsdhxt.s%#<V_sz_elem>\t%q0, %q2, %q3"
6922 [(set_attr "type" "mve_move")
6923 (set_attr "length""8")])
6926 ;; [vqdmulhq_m_n_s])
6928 (define_insn "mve_vqdmulhq_m_n_s<mode>"
6930 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6931 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6932 (match_operand:MVE_2 2 "s_register_operand" "w")
6933 (match_operand:<V_elem> 3 "s_register_operand" "r")
6934 (match_operand:HI 4 "vpr_register_operand" "Up")]
6938 "vpst\;vqdmulht.s%#<V_sz_elem>\t%q0, %q2, %3"
6939 [(set_attr "type" "mve_move")
6940 (set_attr "length""8")])
6945 (define_insn "mve_vqdmulhq_m_s<mode>"
6947 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6948 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6949 (match_operand:MVE_2 2 "s_register_operand" "w")
6950 (match_operand:MVE_2 3 "s_register_operand" "w")
6951 (match_operand:HI 4 "vpr_register_operand" "Up")]
6955 "vpst\;vqdmulht.s%#<V_sz_elem>\t%q0, %q2, %q3"
6956 [(set_attr "type" "mve_move")
6957 (set_attr "length""8")])
6960 ;; [vqrdmladhq_m_s])
6962 (define_insn "mve_vqrdmladhq_m_s<mode>"
6964 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6965 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6966 (match_operand:MVE_2 2 "s_register_operand" "w")
6967 (match_operand:MVE_2 3 "s_register_operand" "w")
6968 (match_operand:HI 4 "vpr_register_operand" "Up")]
6972 "vpst\;vqrdmladht.s%#<V_sz_elem>\t%q0, %q2, %q3"
6973 [(set_attr "type" "mve_move")
6974 (set_attr "length""8")])
6977 ;; [vqrdmladhxq_m_s])
6979 (define_insn "mve_vqrdmladhxq_m_s<mode>"
6981 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6982 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6983 (match_operand:MVE_2 2 "s_register_operand" "w")
6984 (match_operand:MVE_2 3 "s_register_operand" "w")
6985 (match_operand:HI 4 "vpr_register_operand" "Up")]
6989 "vpst\;vqrdmladhxt.s%#<V_sz_elem>\t%q0, %q2, %q3"
6990 [(set_attr "type" "mve_move")
6991 (set_attr "length""8")])
6994 ;; [vqrdmlsdhq_m_s])
6996 (define_insn "mve_vqrdmlsdhq_m_s<mode>"
6998 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6999 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
7000 (match_operand:MVE_2 2 "s_register_operand" "w")
7001 (match_operand:MVE_2 3 "s_register_operand" "w")
7002 (match_operand:HI 4 "vpr_register_operand" "Up")]
7006 "vpst\;vqrdmlsdht.s%#<V_sz_elem>\t%q0, %q2, %q3"
7007 [(set_attr "type" "mve_move")
7008 (set_attr "length""8")])
7011 ;; [vqrdmlsdhxq_m_s])
7013 (define_insn "mve_vqrdmlsdhxq_m_s<mode>"
7015 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
7016 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
7017 (match_operand:MVE_2 2 "s_register_operand" "w")
7018 (match_operand:MVE_2 3 "s_register_operand" "w")
7019 (match_operand:HI 4 "vpr_register_operand" "Up")]
7023 "vpst\;vqrdmlsdhxt.s%#<V_sz_elem>\t%q0, %q2, %q3"
7024 [(set_attr "type" "mve_move")
7025 (set_attr "length""8")])
7028 ;; [vqrdmulhq_m_n_s])
7030 (define_insn "mve_vqrdmulhq_m_n_s<mode>"
7032 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
7033 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
7034 (match_operand:MVE_2 2 "s_register_operand" "w")
7035 (match_operand:<V_elem> 3 "s_register_operand" "r")
7036 (match_operand:HI 4 "vpr_register_operand" "Up")]
7040 "vpst\;vqrdmulht.s%#<V_sz_elem>\t%q0, %q2, %3"
7041 [(set_attr "type" "mve_move")
7042 (set_attr "length""8")])
7047 (define_insn "mve_vqrdmulhq_m_s<mode>"
7049 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
7050 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
7051 (match_operand:MVE_2 2 "s_register_operand" "w")
7052 (match_operand:MVE_2 3 "s_register_operand" "w")
7053 (match_operand:HI 4 "vpr_register_operand" "Up")]
7057 "vpst\;vqrdmulht.s%#<V_sz_elem>\t%q0, %q2, %q3"
7058 [(set_attr "type" "mve_move")
7059 (set_attr "length""8")])
7062 ;; [vmlaldavaq_p_u, vmlaldavaq_p_s])
7064 (define_insn "mve_vmlaldavaq_p_<supf><mode>"
7066 (set (match_operand:DI 0 "s_register_operand" "=r")
7067 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
7068 (match_operand:MVE_5 2 "s_register_operand" "w")
7069 (match_operand:MVE_5 3 "s_register_operand" "w")
7070 (match_operand:HI 4 "vpr_register_operand" "Up")]
7074 "vpst\;vmlaldavat.<supf>%#<V_sz_elem> %Q0, %R0, %q2, %q3"
7075 [(set_attr "type" "mve_move")
7076 (set_attr "length""8")])
7079 ;; [vmlaldavaxq_p_u, vmlaldavaxq_p_s])
7081 (define_insn "mve_vmlaldavaxq_p_<supf><mode>"
7083 (set (match_operand:DI 0 "s_register_operand" "=r")
7084 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
7085 (match_operand:MVE_5 2 "s_register_operand" "w")
7086 (match_operand:MVE_5 3 "s_register_operand" "w")
7087 (match_operand:HI 4 "vpr_register_operand" "Up")]
7091 "vpst\;vmlaldavaxt.<supf>%#<V_sz_elem> %Q0, %R0, %q2, %q3"
7092 [(set_attr "type" "mve_move")
7093 (set_attr "length""8")])
7096 ;; [vqrshrnbq_m_n_u, vqrshrnbq_m_n_s])
7098 (define_insn "mve_vqrshrnbq_m_n_<supf><mode>"
7100 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7101 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7102 (match_operand:MVE_5 2 "s_register_operand" "w")
7103 (match_operand:SI 3 "mve_imm_8" "Rb")
7104 (match_operand:HI 4 "vpr_register_operand" "Up")]
7108 "vpst\;vqrshrnbt.<supf>%#<V_sz_elem> %q0, %q2, %3"
7109 [(set_attr "type" "mve_move")
7110 (set_attr "length""8")])
7113 ;; [vqrshrntq_m_n_s, vqrshrntq_m_n_u])
7115 (define_insn "mve_vqrshrntq_m_n_<supf><mode>"
7117 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7118 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7119 (match_operand:MVE_5 2 "s_register_operand" "w")
7120 (match_operand:SI 3 "mve_imm_8" "Rb")
7121 (match_operand:HI 4 "vpr_register_operand" "Up")]
7125 "vpst\;vqrshrntt.<supf>%#<V_sz_elem> %q0, %q2, %3"
7126 [(set_attr "type" "mve_move")
7127 (set_attr "length""8")])
7130 ;; [vqshrnbq_m_n_u, vqshrnbq_m_n_s])
7132 (define_insn "mve_vqshrnbq_m_n_<supf><mode>"
7134 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7135 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7136 (match_operand:MVE_5 2 "s_register_operand" "w")
7137 (match_operand:SI 3 "<MVE_pred1>" "<MVE_constraint1>")
7138 (match_operand:HI 4 "vpr_register_operand" "Up")]
7141 "TARGET_HAVE_MVE && arm_mve_immediate_check (operands[3], <MODE>mode, 0)"
7142 "vpst\n\tvqshrnbt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
7143 [(set_attr "type" "mve_move")
7144 (set_attr "length""8")])
7147 ;; [vqshrntq_m_n_s, vqshrntq_m_n_u])
7149 (define_insn "mve_vqshrntq_m_n_<supf><mode>"
7151 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7152 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7153 (match_operand:MVE_5 2 "s_register_operand" "w")
7154 (match_operand:SI 3 "mve_imm_8" "Rb")
7155 (match_operand:HI 4 "vpr_register_operand" "Up")]
7159 "vpst\;vqshrntt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
7160 [(set_attr "type" "mve_move")
7161 (set_attr "length""8")])
7164 ;; [vrmlaldavhaq_p_s])
7166 (define_insn "mve_vrmlaldavhaq_p_sv4si"
7168 (set (match_operand:DI 0 "s_register_operand" "=r")
7169 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
7170 (match_operand:V4SI 2 "s_register_operand" "w")
7171 (match_operand:V4SI 3 "s_register_operand" "w")
7172 (match_operand:HI 4 "vpr_register_operand" "Up")]
7176 "vpst\;vrmlaldavhat.s32\t%Q0, %R0, %q2, %q3"
7177 [(set_attr "type" "mve_move")
7178 (set_attr "length""8")])
7181 ;; [vrshrnbq_m_n_u, vrshrnbq_m_n_s])
7183 (define_insn "mve_vrshrnbq_m_n_<supf><mode>"
7185 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7186 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7187 (match_operand:MVE_5 2 "s_register_operand" "w")
7188 (match_operand:SI 3 "mve_imm_8" "Rb")
7189 (match_operand:HI 4 "vpr_register_operand" "Up")]
7193 "vpst\;vrshrnbt.i%#<V_sz_elem>\t%q0, %q2, %3"
7194 [(set_attr "type" "mve_move")
7195 (set_attr "length""8")])
7198 ;; [vrshrntq_m_n_u, vrshrntq_m_n_s])
7200 (define_insn "mve_vrshrntq_m_n_<supf><mode>"
7202 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7203 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7204 (match_operand:MVE_5 2 "s_register_operand" "w")
7205 (match_operand:SI 3 "mve_imm_8" "Rb")
7206 (match_operand:HI 4 "vpr_register_operand" "Up")]
7210 "vpst\;vrshrntt.i%#<V_sz_elem>\t%q0, %q2, %3"
7211 [(set_attr "type" "mve_move")
7212 (set_attr "length""8")])
7215 ;; [vshllbq_m_n_u, vshllbq_m_n_s])
7217 (define_insn "mve_vshllbq_m_n_<supf><mode>"
7219 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
7220 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
7221 (match_operand:MVE_3 2 "s_register_operand" "w")
7222 (match_operand:SI 3 "immediate_operand" "i")
7223 (match_operand:HI 4 "vpr_register_operand" "Up")]
7227 "vpst\;vshllbt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
7228 [(set_attr "type" "mve_move")
7229 (set_attr "length""8")])
7232 ;; [vshlltq_m_n_u, vshlltq_m_n_s])
7234 (define_insn "mve_vshlltq_m_n_<supf><mode>"
7236 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
7237 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
7238 (match_operand:MVE_3 2 "s_register_operand" "w")
7239 (match_operand:SI 3 "immediate_operand" "i")
7240 (match_operand:HI 4 "vpr_register_operand" "Up")]
7244 "vpst\;vshlltt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
7245 [(set_attr "type" "mve_move")
7246 (set_attr "length""8")])
7249 ;; [vshrnbq_m_n_s, vshrnbq_m_n_u])
7251 (define_insn "mve_vshrnbq_m_n_<supf><mode>"
7253 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7254 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7255 (match_operand:MVE_5 2 "s_register_operand" "w")
7256 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")
7257 (match_operand:HI 4 "vpr_register_operand" "Up")]
7261 "vpst\;vshrnbt.i%#<V_sz_elem>\t%q0, %q2, %3"
7262 [(set_attr "type" "mve_move")
7263 (set_attr "length""8")])
7266 ;; [vshrntq_m_n_s, vshrntq_m_n_u])
7268 (define_insn "mve_vshrntq_m_n_<supf><mode>"
7270 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7271 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7272 (match_operand:MVE_5 2 "s_register_operand" "w")
7273 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")
7274 (match_operand:HI 4 "vpr_register_operand" "Up")]
7278 "vpst\;vshrntt.i%#<V_sz_elem>\t%q0, %q2, %3"
7279 [(set_attr "type" "mve_move")
7280 (set_attr "length""8")])
7283 ;; [vmlsldavaq_p_s])
7285 (define_insn "mve_vmlsldavaq_p_s<mode>"
7287 (set (match_operand:DI 0 "s_register_operand" "=r")
7288 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
7289 (match_operand:MVE_5 2 "s_register_operand" "w")
7290 (match_operand:MVE_5 3 "s_register_operand" "w")
7291 (match_operand:HI 4 "vpr_register_operand" "Up")]
7295 "vpst\;vmlsldavat.s%#<V_sz_elem>\t%Q0, %R0, %q2, %q3"
7296 [(set_attr "type" "mve_move")
7297 (set_attr "length""8")])
7300 ;; [vmlsldavaxq_p_s])
7302 (define_insn "mve_vmlsldavaxq_p_s<mode>"
7304 (set (match_operand:DI 0 "s_register_operand" "=r")
7305 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
7306 (match_operand:MVE_5 2 "s_register_operand" "w")
7307 (match_operand:MVE_5 3 "s_register_operand" "w")
7308 (match_operand:HI 4 "vpr_register_operand" "Up")]
7312 "vpst\;vmlsldavaxt.s%#<V_sz_elem>\t%Q0, %R0, %q2, %q3"
7313 [(set_attr "type" "mve_move")
7314 (set_attr "length""8")])
7317 ;; [vmullbq_poly_m_p])
7319 (define_insn "mve_vmullbq_poly_m_p<mode>"
7321 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
7322 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
7323 (match_operand:MVE_3 2 "s_register_operand" "w")
7324 (match_operand:MVE_3 3 "s_register_operand" "w")
7325 (match_operand:HI 4 "vpr_register_operand" "Up")]
7329 "vpst\;vmullbt.p%#<V_sz_elem>\t%q0, %q2, %q3"
7330 [(set_attr "type" "mve_move")
7331 (set_attr "length""8")])
7334 ;; [vmulltq_poly_m_p])
7336 (define_insn "mve_vmulltq_poly_m_p<mode>"
7338 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
7339 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
7340 (match_operand:MVE_3 2 "s_register_operand" "w")
7341 (match_operand:MVE_3 3 "s_register_operand" "w")
7342 (match_operand:HI 4 "vpr_register_operand" "Up")]
7346 "vpst\;vmulltt.p%#<V_sz_elem>\t%q0, %q2, %q3"
7347 [(set_attr "type" "mve_move")
7348 (set_attr "length""8")])
7351 ;; [vqdmullbq_m_n_s])
7353 (define_insn "mve_vqdmullbq_m_n_s<mode>"
7355 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
7356 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
7357 (match_operand:MVE_5 2 "s_register_operand" "w")
7358 (match_operand:<V_elem> 3 "s_register_operand" "r")
7359 (match_operand:HI 4 "vpr_register_operand" "Up")]
7363 "vpst\;vqdmullbt.s%#<V_sz_elem>\t%q0, %q2, %3"
7364 [(set_attr "type" "mve_move")
7365 (set_attr "length""8")])
7370 (define_insn "mve_vqdmullbq_m_s<mode>"
7372 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
7373 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
7374 (match_operand:MVE_5 2 "s_register_operand" "w")
7375 (match_operand:MVE_5 3 "s_register_operand" "w")
7376 (match_operand:HI 4 "vpr_register_operand" "Up")]
7380 "vpst\;vqdmullbt.s%#<V_sz_elem>\t%q0, %q2, %q3"
7381 [(set_attr "type" "mve_move")
7382 (set_attr "length""8")])
7385 ;; [vqdmulltq_m_n_s])
7387 (define_insn "mve_vqdmulltq_m_n_s<mode>"
7389 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
7390 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
7391 (match_operand:MVE_5 2 "s_register_operand" "w")
7392 (match_operand:<V_elem> 3 "s_register_operand" "r")
7393 (match_operand:HI 4 "vpr_register_operand" "Up")]
7397 "vpst\;vqdmulltt.s%#<V_sz_elem>\t%q0, %q2, %3"
7398 [(set_attr "type" "mve_move")
7399 (set_attr "length""8")])
7404 (define_insn "mve_vqdmulltq_m_s<mode>"
7406 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
7407 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
7408 (match_operand:MVE_5 2 "s_register_operand" "w")
7409 (match_operand:MVE_5 3 "s_register_operand" "w")
7410 (match_operand:HI 4 "vpr_register_operand" "Up")]
7414 "vpst\;vqdmulltt.s%#<V_sz_elem>\t%q0, %q2, %q3"
7415 [(set_attr "type" "mve_move")
7416 (set_attr "length""8")])
7419 ;; [vqrshrunbq_m_n_s])
7421 (define_insn "mve_vqrshrunbq_m_n_s<mode>"
7423 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7424 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7425 (match_operand:MVE_5 2 "s_register_operand" "w")
7426 (match_operand:SI 3 "mve_imm_8" "Rb")
7427 (match_operand:HI 4 "vpr_register_operand" "Up")]
7431 "vpst\;vqrshrunbt.s%#<V_sz_elem>\t%q0, %q2, %3"
7432 [(set_attr "type" "mve_move")
7433 (set_attr "length""8")])
7436 ;; [vqrshruntq_m_n_s])
7438 (define_insn "mve_vqrshruntq_m_n_s<mode>"
7440 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7441 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7442 (match_operand:MVE_5 2 "s_register_operand" "w")
7443 (match_operand:SI 3 "mve_imm_8" "Rb")
7444 (match_operand:HI 4 "vpr_register_operand" "Up")]
7448 "vpst\;vqrshruntt.s%#<V_sz_elem>\t%q0, %q2, %3"
7449 [(set_attr "type" "mve_move")
7450 (set_attr "length""8")])
7453 ;; [vqshrunbq_m_n_s])
7455 (define_insn "mve_vqshrunbq_m_n_s<mode>"
7457 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7458 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7459 (match_operand:MVE_5 2 "s_register_operand" "w")
7460 (match_operand:SI 3 "mve_imm_8" "Rb")
7461 (match_operand:HI 4 "vpr_register_operand" "Up")]
7465 "vpst\;vqshrunbt.s%#<V_sz_elem>\t%q0, %q2, %3"
7466 [(set_attr "type" "mve_move")
7467 (set_attr "length""8")])
7470 ;; [vqshruntq_m_n_s])
7472 (define_insn "mve_vqshruntq_m_n_s<mode>"
7474 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7475 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7476 (match_operand:MVE_5 2 "s_register_operand" "w")
7477 (match_operand:SI 3 "mve_imm_8" "Rb")
7478 (match_operand:HI 4 "vpr_register_operand" "Up")]
7482 "vpst\;vqshruntt.s%#<V_sz_elem>\t%q0, %q2, %3"
7483 [(set_attr "type" "mve_move")
7484 (set_attr "length""8")])
7487 ;; [vrmlaldavhaq_p_u])
7489 (define_insn "mve_vrmlaldavhaq_p_uv4si"
7491 (set (match_operand:DI 0 "s_register_operand" "=r")
7492 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
7493 (match_operand:V4SI 2 "s_register_operand" "w")
7494 (match_operand:V4SI 3 "s_register_operand" "w")
7495 (match_operand:HI 4 "vpr_register_operand" "Up")]
7499 "vpst\;vrmlaldavhat.u32\t%Q0, %R0, %q2, %q3"
7500 [(set_attr "type" "mve_move")
7501 (set_attr "length""8")])
7504 ;; [vrmlaldavhaxq_p_s])
7506 (define_insn "mve_vrmlaldavhaxq_p_sv4si"
7508 (set (match_operand:DI 0 "s_register_operand" "=r")
7509 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
7510 (match_operand:V4SI 2 "s_register_operand" "w")
7511 (match_operand:V4SI 3 "s_register_operand" "w")
7512 (match_operand:HI 4 "vpr_register_operand" "Up")]
7516 "vpst\;vrmlaldavhaxt.s32\t%Q0, %R0, %q2, %q3"
7517 [(set_attr "type" "mve_move")
7518 (set_attr "length""8")])
7521 ;; [vrmlsldavhaq_p_s])
7523 (define_insn "mve_vrmlsldavhaq_p_sv4si"
7525 (set (match_operand:DI 0 "s_register_operand" "=r")
7526 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
7527 (match_operand:V4SI 2 "s_register_operand" "w")
7528 (match_operand:V4SI 3 "s_register_operand" "w")
7529 (match_operand:HI 4 "vpr_register_operand" "Up")]
7533 "vpst\;vrmlsldavhat.s32\t%Q0, %R0, %q2, %q3"
7534 [(set_attr "type" "mve_move")
7535 (set_attr "length""8")])
7538 ;; [vrmlsldavhaxq_p_s])
7540 (define_insn "mve_vrmlsldavhaxq_p_sv4si"
7542 (set (match_operand:DI 0 "s_register_operand" "=r")
7543 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
7544 (match_operand:V4SI 2 "s_register_operand" "w")
7545 (match_operand:V4SI 3 "s_register_operand" "w")
7546 (match_operand:HI 4 "vpr_register_operand" "Up")]
7550 "vpst\;vrmlsldavhaxt.s32\t%Q0, %R0, %q2, %q3"
7551 [(set_attr "type" "mve_move")
7552 (set_attr "length""8")])
7556 (define_insn "mve_vabdq_m_f<mode>"
7558 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7559 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7560 (match_operand:MVE_0 2 "s_register_operand" "w")
7561 (match_operand:MVE_0 3 "s_register_operand" "w")
7562 (match_operand:HI 4 "vpr_register_operand" "Up")]
7565 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7566 "vpst\;vabdt.f%#<V_sz_elem> %q0, %q2, %q3"
7567 [(set_attr "type" "mve_move")
7568 (set_attr "length""8")])
7573 (define_insn "mve_vaddq_m_f<mode>"
7575 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7576 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7577 (match_operand:MVE_0 2 "s_register_operand" "w")
7578 (match_operand:MVE_0 3 "s_register_operand" "w")
7579 (match_operand:HI 4 "vpr_register_operand" "Up")]
7582 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7583 "vpst\;vaddt.f%#<V_sz_elem> %q0, %q2, %q3"
7584 [(set_attr "type" "mve_move")
7585 (set_attr "length""8")])
7590 (define_insn "mve_vaddq_m_n_f<mode>"
7592 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7593 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7594 (match_operand:MVE_0 2 "s_register_operand" "w")
7595 (match_operand:<V_elem> 3 "s_register_operand" "r")
7596 (match_operand:HI 4 "vpr_register_operand" "Up")]
7599 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7600 "vpst\;vaddt.f%#<V_sz_elem> %q0, %q2, %3"
7601 [(set_attr "type" "mve_move")
7602 (set_attr "length""8")])
7607 (define_insn "mve_vandq_m_f<mode>"
7609 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7610 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7611 (match_operand:MVE_0 2 "s_register_operand" "w")
7612 (match_operand:MVE_0 3 "s_register_operand" "w")
7613 (match_operand:HI 4 "vpr_register_operand" "Up")]
7616 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7617 "vpst\;vandt %q0, %q2, %q3"
7618 [(set_attr "type" "mve_move")
7619 (set_attr "length""8")])
7624 (define_insn "mve_vbicq_m_f<mode>"
7626 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7627 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7628 (match_operand:MVE_0 2 "s_register_operand" "w")
7629 (match_operand:MVE_0 3 "s_register_operand" "w")
7630 (match_operand:HI 4 "vpr_register_operand" "Up")]
7633 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7634 "vpst\;vbict %q0, %q2, %q3"
7635 [(set_attr "type" "mve_move")
7636 (set_attr "length""8")])
7641 (define_insn "mve_vbrsrq_m_n_f<mode>"
7643 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7644 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7645 (match_operand:MVE_0 2 "s_register_operand" "w")
7646 (match_operand:SI 3 "s_register_operand" "r")
7647 (match_operand:HI 4 "vpr_register_operand" "Up")]
7650 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7651 "vpst\;vbrsrt.%#<V_sz_elem> %q0, %q2, %3"
7652 [(set_attr "type" "mve_move")
7653 (set_attr "length""8")])
7656 ;; [vcaddq_rot270_m_f])
7658 (define_insn "mve_vcaddq_rot270_m_f<mode>"
7660 (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
7661 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7662 (match_operand:MVE_0 2 "s_register_operand" "w")
7663 (match_operand:MVE_0 3 "s_register_operand" "w")
7664 (match_operand:HI 4 "vpr_register_operand" "Up")]
7667 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7668 "vpst\;vcaddt.f%#<V_sz_elem> %q0, %q2, %q3, #270"
7669 [(set_attr "type" "mve_move")
7670 (set_attr "length""8")])
7673 ;; [vcaddq_rot90_m_f])
7675 (define_insn "mve_vcaddq_rot90_m_f<mode>"
7677 (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
7678 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7679 (match_operand:MVE_0 2 "s_register_operand" "w")
7680 (match_operand:MVE_0 3 "s_register_operand" "w")
7681 (match_operand:HI 4 "vpr_register_operand" "Up")]
7684 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7685 "vpst\;vcaddt.f%#<V_sz_elem> %q0, %q2, %q3, #90"
7686 [(set_attr "type" "mve_move")
7687 (set_attr "length""8")])
7692 (define_insn "mve_vcmlaq_m_f<mode>"
7694 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7695 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7696 (match_operand:MVE_0 2 "s_register_operand" "w")
7697 (match_operand:MVE_0 3 "s_register_operand" "w")
7698 (match_operand:HI 4 "vpr_register_operand" "Up")]
7701 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7702 "vpst\;vcmlat.f%#<V_sz_elem> %q0, %q2, %q3, #0"
7703 [(set_attr "type" "mve_move")
7704 (set_attr "length""8")])
7707 ;; [vcmlaq_rot180_m_f])
7709 (define_insn "mve_vcmlaq_rot180_m_f<mode>"
7711 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7712 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7713 (match_operand:MVE_0 2 "s_register_operand" "w")
7714 (match_operand:MVE_0 3 "s_register_operand" "w")
7715 (match_operand:HI 4 "vpr_register_operand" "Up")]
7718 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7719 "vpst\;vcmlat.f%#<V_sz_elem> %q0, %q2, %q3, #180"
7720 [(set_attr "type" "mve_move")
7721 (set_attr "length""8")])
7724 ;; [vcmlaq_rot270_m_f])
7726 (define_insn "mve_vcmlaq_rot270_m_f<mode>"
7728 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7729 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7730 (match_operand:MVE_0 2 "s_register_operand" "w")
7731 (match_operand:MVE_0 3 "s_register_operand" "w")
7732 (match_operand:HI 4 "vpr_register_operand" "Up")]
7735 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7736 "vpst\;vcmlat.f%#<V_sz_elem> %q0, %q2, %q3, #270"
7737 [(set_attr "type" "mve_move")
7738 (set_attr "length""8")])
7741 ;; [vcmlaq_rot90_m_f])
7743 (define_insn "mve_vcmlaq_rot90_m_f<mode>"
7745 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7746 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7747 (match_operand:MVE_0 2 "s_register_operand" "w")
7748 (match_operand:MVE_0 3 "s_register_operand" "w")
7749 (match_operand:HI 4 "vpr_register_operand" "Up")]
7752 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7753 "vpst\;vcmlat.f%#<V_sz_elem> %q0, %q2, %q3, #90"
7754 [(set_attr "type" "mve_move")
7755 (set_attr "length""8")])
7760 (define_insn "mve_vcmulq_m_f<mode>"
7762 (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
7763 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7764 (match_operand:MVE_0 2 "s_register_operand" "w")
7765 (match_operand:MVE_0 3 "s_register_operand" "w")
7766 (match_operand:HI 4 "vpr_register_operand" "Up")]
7769 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7770 "vpst\;vcmult.f%#<V_sz_elem> %q0, %q2, %q3, #0"
7771 [(set_attr "type" "mve_move")
7772 (set_attr "length""8")])
7775 ;; [vcmulq_rot180_m_f])
7777 (define_insn "mve_vcmulq_rot180_m_f<mode>"
7779 (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
7780 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7781 (match_operand:MVE_0 2 "s_register_operand" "w")
7782 (match_operand:MVE_0 3 "s_register_operand" "w")
7783 (match_operand:HI 4 "vpr_register_operand" "Up")]
7786 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7787 "vpst\;vcmult.f%#<V_sz_elem> %q0, %q2, %q3, #180"
7788 [(set_attr "type" "mve_move")
7789 (set_attr "length""8")])
7792 ;; [vcmulq_rot270_m_f])
7794 (define_insn "mve_vcmulq_rot270_m_f<mode>"
7796 (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
7797 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7798 (match_operand:MVE_0 2 "s_register_operand" "w")
7799 (match_operand:MVE_0 3 "s_register_operand" "w")
7800 (match_operand:HI 4 "vpr_register_operand" "Up")]
7803 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7804 "vpst\;vcmult.f%#<V_sz_elem> %q0, %q2, %q3, #270"
7805 [(set_attr "type" "mve_move")
7806 (set_attr "length""8")])
7809 ;; [vcmulq_rot90_m_f])
7811 (define_insn "mve_vcmulq_rot90_m_f<mode>"
7813 (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
7814 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7815 (match_operand:MVE_0 2 "s_register_operand" "w")
7816 (match_operand:MVE_0 3 "s_register_operand" "w")
7817 (match_operand:HI 4 "vpr_register_operand" "Up")]
7820 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7821 "vpst\;vcmult.f%#<V_sz_elem> %q0, %q2, %q3, #90"
7822 [(set_attr "type" "mve_move")
7823 (set_attr "length""8")])
7828 (define_insn "mve_veorq_m_f<mode>"
7830 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7831 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7832 (match_operand:MVE_0 2 "s_register_operand" "w")
7833 (match_operand:MVE_0 3 "s_register_operand" "w")
7834 (match_operand:HI 4 "vpr_register_operand" "Up")]
7837 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7838 "vpst\;veort %q0, %q2, %q3"
7839 [(set_attr "type" "mve_move")
7840 (set_attr "length""8")])
7845 (define_insn "mve_vfmaq_m_f<mode>"
7847 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7848 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7849 (match_operand:MVE_0 2 "s_register_operand" "w")
7850 (match_operand:MVE_0 3 "s_register_operand" "w")
7851 (match_operand:HI 4 "vpr_register_operand" "Up")]
7854 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7855 "vpst\;vfmat.f%#<V_sz_elem> %q0, %q2, %q3"
7856 [(set_attr "type" "mve_move")
7857 (set_attr "length""8")])
7862 (define_insn "mve_vfmaq_m_n_f<mode>"
7864 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7865 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7866 (match_operand:MVE_0 2 "s_register_operand" "w")
7867 (match_operand:<V_elem> 3 "s_register_operand" "r")
7868 (match_operand:HI 4 "vpr_register_operand" "Up")]
7871 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7872 "vpst\;vfmat.f%#<V_sz_elem> %q0, %q2, %3"
7873 [(set_attr "type" "mve_move")
7874 (set_attr "length""8")])
7879 (define_insn "mve_vfmasq_m_n_f<mode>"
7881 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7882 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7883 (match_operand:MVE_0 2 "s_register_operand" "w")
7884 (match_operand:<V_elem> 3 "s_register_operand" "r")
7885 (match_operand:HI 4 "vpr_register_operand" "Up")]
7888 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7889 "vpst\;vfmast.f%#<V_sz_elem> %q0, %q2, %3"
7890 [(set_attr "type" "mve_move")
7891 (set_attr "length""8")])
7896 (define_insn "mve_vfmsq_m_f<mode>"
7898 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7899 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7900 (match_operand:MVE_0 2 "s_register_operand" "w")
7901 (match_operand:MVE_0 3 "s_register_operand" "w")
7902 (match_operand:HI 4 "vpr_register_operand" "Up")]
7905 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7906 "vpst\;vfmst.f%#<V_sz_elem> %q0, %q2, %q3"
7907 [(set_attr "type" "mve_move")
7908 (set_attr "length""8")])
7913 (define_insn "mve_vmaxnmq_m_f<mode>"
7915 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7916 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7917 (match_operand:MVE_0 2 "s_register_operand" "w")
7918 (match_operand:MVE_0 3 "s_register_operand" "w")
7919 (match_operand:HI 4 "vpr_register_operand" "Up")]
7922 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7923 "vpst\;vmaxnmt.f%#<V_sz_elem> %q0, %q2, %q3"
7924 [(set_attr "type" "mve_move")
7925 (set_attr "length""8")])
7930 (define_insn "mve_vminnmq_m_f<mode>"
7932 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7933 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7934 (match_operand:MVE_0 2 "s_register_operand" "w")
7935 (match_operand:MVE_0 3 "s_register_operand" "w")
7936 (match_operand:HI 4 "vpr_register_operand" "Up")]
7939 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7940 "vpst\;vminnmt.f%#<V_sz_elem> %q0, %q2, %q3"
7941 [(set_attr "type" "mve_move")
7942 (set_attr "length""8")])
7947 (define_insn "mve_vmulq_m_f<mode>"
7949 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7950 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7951 (match_operand:MVE_0 2 "s_register_operand" "w")
7952 (match_operand:MVE_0 3 "s_register_operand" "w")
7953 (match_operand:HI 4 "vpr_register_operand" "Up")]
7956 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7957 "vpst\;vmult.f%#<V_sz_elem> %q0, %q2, %q3"
7958 [(set_attr "type" "mve_move")
7959 (set_attr "length""8")])
7964 (define_insn "mve_vmulq_m_n_f<mode>"
7966 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7967 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7968 (match_operand:MVE_0 2 "s_register_operand" "w")
7969 (match_operand:<V_elem> 3 "s_register_operand" "r")
7970 (match_operand:HI 4 "vpr_register_operand" "Up")]
7973 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7974 "vpst\;vmult.f%#<V_sz_elem> %q0, %q2, %3"
7975 [(set_attr "type" "mve_move")
7976 (set_attr "length""8")])
7981 (define_insn "mve_vornq_m_f<mode>"
7983 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7984 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7985 (match_operand:MVE_0 2 "s_register_operand" "w")
7986 (match_operand:MVE_0 3 "s_register_operand" "w")
7987 (match_operand:HI 4 "vpr_register_operand" "Up")]
7990 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7991 "vpst\;vornt %q0, %q2, %q3"
7992 [(set_attr "type" "mve_move")
7993 (set_attr "length""8")])
7998 (define_insn "mve_vorrq_m_f<mode>"
8000 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
8001 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
8002 (match_operand:MVE_0 2 "s_register_operand" "w")
8003 (match_operand:MVE_0 3 "s_register_operand" "w")
8004 (match_operand:HI 4 "vpr_register_operand" "Up")]
8007 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8008 "vpst\;vorrt %q0, %q2, %q3"
8009 [(set_attr "type" "mve_move")
8010 (set_attr "length""8")])
8015 (define_insn "mve_vsubq_m_f<mode>"
8017 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
8018 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
8019 (match_operand:MVE_0 2 "s_register_operand" "w")
8020 (match_operand:MVE_0 3 "s_register_operand" "w")
8021 (match_operand:HI 4 "vpr_register_operand" "Up")]
8024 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8025 "vpst\;vsubt.f%#<V_sz_elem>\t%q0, %q2, %q3"
8026 [(set_attr "type" "mve_move")
8027 (set_attr "length""8")])
8032 (define_insn "mve_vsubq_m_n_f<mode>"
8034 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
8035 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
8036 (match_operand:MVE_0 2 "s_register_operand" "w")
8037 (match_operand:<V_elem> 3 "s_register_operand" "r")
8038 (match_operand:HI 4 "vpr_register_operand" "Up")]
8041 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8042 "vpst\;vsubt.f%#<V_sz_elem>\t%q0, %q2, %3"
8043 [(set_attr "type" "mve_move")
8044 (set_attr "length""8")])
8047 ;; [vstrbq_s vstrbq_u]
8049 (define_insn "mve_vstrbq_<supf><mode>"
8050 [(set (match_operand:<MVE_B_ELEM> 0 "memory_operand" "=Us")
8051 (unspec:<MVE_B_ELEM> [(match_operand:MVE_2 1 "s_register_operand" "w")]
8057 int regno = REGNO (operands[1]);
8058 ops[1] = gen_rtx_REG (TImode, regno);
8059 ops[0] = operands[0];
8060 output_asm_insn("vstrb.<V_sz_elem>\t%q1, %E0",ops);
8063 [(set_attr "length" "4")])
8066 ;; [vstrbq_scatter_offset_s vstrbq_scatter_offset_u]
8068 (define_insn "mve_vstrbq_scatter_offset_<supf><mode>"
8069 [(set (match_operand:<MVE_B_ELEM> 0 "memory_operand" "=Us")
8070 (unspec:<MVE_B_ELEM>
8071 [(match_operand:MVE_2 1 "s_register_operand" "w")
8072 (match_operand:MVE_2 2 "s_register_operand" "w")]
8078 ops[0] = operands[0];
8079 ops[1] = operands[1];
8080 ops[2] = operands[2];
8081 output_asm_insn("vstrb.<V_sz_elem>\t%q2, [%m0, %q1]",ops);
8084 [(set_attr "length" "4")])
8087 ;; [vstrwq_scatter_base_s vstrwq_scatter_base_u]
8089 (define_insn "mve_vstrwq_scatter_base_<supf>v4si"
8090 [(set (mem:BLK (scratch))
8092 [(match_operand:V4SI 0 "s_register_operand" "w")
8093 (match_operand:SI 1 "immediate_operand" "i")
8094 (match_operand:V4SI 2 "s_register_operand" "w")]
8100 ops[0] = operands[0];
8101 ops[1] = operands[1];
8102 ops[2] = operands[2];
8103 output_asm_insn("vstrw.u32\t%q2, [%q0, %1]",ops);
8106 [(set_attr "length" "4")])
8109 ;; [vldrbq_gather_offset_s vldrbq_gather_offset_u]
8111 (define_insn "mve_vldrbq_gather_offset_<supf><mode>"
8112 [(set (match_operand:MVE_2 0 "s_register_operand" "=&w")
8113 (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "memory_operand" "Us")
8114 (match_operand:MVE_2 2 "s_register_operand" "w")]
8120 ops[0] = operands[0];
8121 ops[1] = operands[1];
8122 ops[2] = operands[2];
8123 if (!strcmp ("<supf>","s") && <V_sz_elem> == 8)
8124 output_asm_insn ("vldrb.u8\t%q0, [%m1, %q2]",ops);
8126 output_asm_insn ("vldrb.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops);
8129 [(set_attr "length" "4")])
8132 ;; [vldrbq_s vldrbq_u]
8134 (define_insn "mve_vldrbq_<supf><mode>"
8135 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
8136 (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "memory_operand" "Us")]
8142 int regno = REGNO (operands[0]);
8143 ops[0] = gen_rtx_REG (TImode, regno);
8144 ops[1] = operands[1];
8145 output_asm_insn ("vldrb.<supf><V_sz_elem>\t%q0, %E1",ops);
8148 [(set_attr "length" "4")])
8151 ;; [vldrwq_gather_base_s vldrwq_gather_base_u]
8153 (define_insn "mve_vldrwq_gather_base_<supf>v4si"
8154 [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
8155 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
8156 (match_operand:SI 2 "immediate_operand" "i")]
8162 ops[0] = operands[0];
8163 ops[1] = operands[1];
8164 ops[2] = operands[2];
8165 output_asm_insn ("vldrw.u32\t%q0, [%q1, %2]",ops);
8168 [(set_attr "length" "4")])
8171 ;; [vstrbq_scatter_offset_p_s vstrbq_scatter_offset_p_u]
8173 (define_insn "mve_vstrbq_scatter_offset_p_<supf><mode>"
8174 [(set (match_operand:<MVE_B_ELEM> 0 "memory_operand" "=Us")
8175 (unspec:<MVE_B_ELEM>
8176 [(match_operand:MVE_2 1 "s_register_operand" "w")
8177 (match_operand:MVE_2 2 "s_register_operand" "w")
8178 (match_operand:HI 3 "vpr_register_operand" "Up")]
8184 ops[0] = operands[0];
8185 ops[1] = operands[1];
8186 ops[2] = operands[2];
8187 output_asm_insn ("vpst\n\tvstrbt.<V_sz_elem>\t%q2, [%m0, %q1]",ops);
8190 [(set_attr "length" "8")])
8193 ;; [vstrwq_scatter_base_p_s vstrwq_scatter_base_p_u]
8195 (define_insn "mve_vstrwq_scatter_base_p_<supf>v4si"
8196 [(set (mem:BLK (scratch))
8198 [(match_operand:V4SI 0 "s_register_operand" "w")
8199 (match_operand:SI 1 "immediate_operand" "i")
8200 (match_operand:V4SI 2 "s_register_operand" "w")
8201 (match_operand:HI 3 "vpr_register_operand" "Up")]
8207 ops[0] = operands[0];
8208 ops[1] = operands[1];
8209 ops[2] = operands[2];
8210 output_asm_insn ("vpst\n\tvstrwt.u32\t%q2, [%q0, %1]",ops);
8213 [(set_attr "length" "8")])
8216 ;; [vstrbq_p_s vstrbq_p_u]
8218 (define_insn "mve_vstrbq_p_<supf><mode>"
8219 [(set (match_operand:<MVE_B_ELEM> 0 "memory_operand" "=Us")
8220 (unspec:<MVE_B_ELEM> [(match_operand:MVE_2 1 "s_register_operand" "w")
8221 (match_operand:HI 2 "vpr_register_operand" "Up")]
8227 int regno = REGNO (operands[1]);
8228 ops[1] = gen_rtx_REG (TImode, regno);
8229 ops[0] = operands[0];
8230 output_asm_insn ("vpst\n\tvstrbt.<V_sz_elem>\t%q1, %E0",ops);
8233 [(set_attr "length" "8")])
8236 ;; [vldrbq_gather_offset_z_s vldrbq_gather_offset_z_u]
8238 (define_insn "mve_vldrbq_gather_offset_z_<supf><mode>"
8239 [(set (match_operand:MVE_2 0 "s_register_operand" "=&w")
8240 (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "memory_operand" "Us")
8241 (match_operand:MVE_2 2 "s_register_operand" "w")
8242 (match_operand:HI 3 "vpr_register_operand" "Up")]
8248 ops[0] = operands[0];
8249 ops[1] = operands[1];
8250 ops[2] = operands[2];
8251 ops[3] = operands[3];
8252 if (!strcmp ("<supf>","s") && <V_sz_elem> == 8)
8253 output_asm_insn ("vpst\n\tvldrbt.u8\t%q0, [%m1, %q2]",ops);
8255 output_asm_insn ("vpst\n\tvldrbt.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops);
8258 [(set_attr "length" "8")])
8261 ;; [vldrbq_z_s vldrbq_z_u]
8263 (define_insn "mve_vldrbq_z_<supf><mode>"
8264 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
8265 (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "memory_operand" "Us")
8266 (match_operand:HI 2 "vpr_register_operand" "Up")]
8272 int regno = REGNO (operands[0]);
8273 ops[0] = gen_rtx_REG (TImode, regno);
8274 ops[1] = operands[1];
8275 output_asm_insn ("vpst\n\tvldrbt.<supf><V_sz_elem>\t%q0, %E1",ops);
8278 [(set_attr "length" "8")])
8281 ;; [vldrwq_gather_base_z_s vldrwq_gather_base_z_u]
8283 (define_insn "mve_vldrwq_gather_base_z_<supf>v4si"
8284 [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
8285 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
8286 (match_operand:SI 2 "immediate_operand" "i")
8287 (match_operand:HI 3 "vpr_register_operand" "Up")]
8293 ops[0] = operands[0];
8294 ops[1] = operands[1];
8295 ops[2] = operands[2];
8296 output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%q1, %2]",ops);
8299 [(set_attr "length" "8")])
8304 (define_insn "mve_vldrhq_fv8hf"
8305 [(set (match_operand:V8HF 0 "s_register_operand" "=w")
8306 (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us")]
8309 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8312 int regno = REGNO (operands[0]);
8313 ops[0] = gen_rtx_REG (TImode, regno);
8314 ops[1] = operands[1];
8315 output_asm_insn ("vldrh.f16\t%q0, %E1",ops);
8318 [(set_attr "length" "4")])
8321 ;; [vldrhq_gather_offset_s vldrhq_gather_offset_u]
8323 (define_insn "mve_vldrhq_gather_offset_<supf><mode>"
8324 [(set (match_operand:MVE_6 0 "s_register_operand" "=&w")
8325 (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
8326 (match_operand:MVE_6 2 "s_register_operand" "w")]
8332 ops[0] = operands[0];
8333 ops[1] = operands[1];
8334 ops[2] = operands[2];
8335 if (!strcmp ("<supf>","s") && <V_sz_elem> == 16)
8336 output_asm_insn ("vldrh.u16\t%q0, [%m1, %q2]",ops);
8338 output_asm_insn ("vldrh.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops);
8341 [(set_attr "length" "4")])
8344 ;; [vldrhq_gather_offset_z_s vldrhq_gather_offset_z_u]
8346 (define_insn "mve_vldrhq_gather_offset_z_<supf><mode>"
8347 [(set (match_operand:MVE_6 0 "s_register_operand" "=&w")
8348 (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
8349 (match_operand:MVE_6 2 "s_register_operand" "w")
8350 (match_operand:HI 3 "vpr_register_operand" "Up")
8356 ops[0] = operands[0];
8357 ops[1] = operands[1];
8358 ops[2] = operands[2];
8359 ops[3] = operands[3];
8360 if (!strcmp ("<supf>","s") && <V_sz_elem> == 16)
8361 output_asm_insn ("vpst\n\tvldrht.u16\t%q0, [%m1, %q2]",ops);
8363 output_asm_insn ("vpst\n\tvldrht.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops);
8366 [(set_attr "length" "8")])
8369 ;; [vldrhq_gather_shifted_offset_s vldrhq_gather_shifted_offset_u]
8371 (define_insn "mve_vldrhq_gather_shifted_offset_<supf><mode>"
8372 [(set (match_operand:MVE_6 0 "s_register_operand" "=&w")
8373 (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
8374 (match_operand:MVE_6 2 "s_register_operand" "w")]
8380 ops[0] = operands[0];
8381 ops[1] = operands[1];
8382 ops[2] = operands[2];
8383 if (!strcmp ("<supf>","s") && <V_sz_elem> == 16)
8384 output_asm_insn ("vldrh.u16\t%q0, [%m1, %q2, uxtw #1]",ops);
8386 output_asm_insn ("vldrh.<supf><V_sz_elem>\t%q0, [%m1, %q2, uxtw #1]",ops);
8389 [(set_attr "length" "4")])
8392 ;; [vldrhq_gather_shifted_offset_z_s vldrhq_gather_shited_offset_z_u]
8394 (define_insn "mve_vldrhq_gather_shifted_offset_z_<supf><mode>"
8395 [(set (match_operand:MVE_6 0 "s_register_operand" "=&w")
8396 (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
8397 (match_operand:MVE_6 2 "s_register_operand" "w")
8398 (match_operand:HI 3 "vpr_register_operand" "Up")
8404 ops[0] = operands[0];
8405 ops[1] = operands[1];
8406 ops[2] = operands[2];
8407 ops[3] = operands[3];
8408 if (!strcmp ("<supf>","s") && <V_sz_elem> == 16)
8409 output_asm_insn ("vpst\n\tvldrht.u16\t%q0, [%m1, %q2, uxtw #1]",ops);
8411 output_asm_insn ("vpst\n\tvldrht.<supf><V_sz_elem>\t%q0, [%m1, %q2, uxtw #1]",ops);
8414 [(set_attr "length" "8")])
8418 ;; [vldrhq_s, vldrhq_u]
8420 (define_insn "mve_vldrhq_<supf><mode>"
8421 [(set (match_operand:MVE_6 0 "s_register_operand" "=w")
8422 (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")]
8428 int regno = REGNO (operands[0]);
8429 ops[0] = gen_rtx_REG (TImode, regno);
8430 ops[1] = operands[1];
8431 output_asm_insn ("vldrh.<supf><V_sz_elem>\t%q0, %E1",ops);
8434 [(set_attr "length" "4")])
8439 (define_insn "mve_vldrhq_z_fv8hf"
8440 [(set (match_operand:V8HF 0 "s_register_operand" "=w")
8441 (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us")
8442 (match_operand:HI 2 "vpr_register_operand" "Up")]
8445 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8448 int regno = REGNO (operands[0]);
8449 ops[0] = gen_rtx_REG (TImode, regno);
8450 ops[1] = operands[1];
8451 output_asm_insn ("vpst\n\tvldrht.f16\t%q0, %E1",ops);
8454 [(set_attr "length" "8")])
8457 ;; [vldrhq_z_s vldrhq_z_u]
8459 (define_insn "mve_vldrhq_z_<supf><mode>"
8460 [(set (match_operand:MVE_6 0 "s_register_operand" "=w")
8461 (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
8462 (match_operand:HI 2 "vpr_register_operand" "Up")]
8468 int regno = REGNO (operands[0]);
8469 ops[0] = gen_rtx_REG (TImode, regno);
8470 ops[1] = operands[1];
8471 output_asm_insn ("vpst\n\tvldrht.<supf><V_sz_elem>\t%q0, %E1",ops);
8474 [(set_attr "length" "8")])
8479 (define_insn "mve_vldrwq_fv4sf"
8480 [(set (match_operand:V4SF 0 "s_register_operand" "=w")
8481 (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us")]
8484 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8487 int regno = REGNO (operands[0]);
8488 ops[0] = gen_rtx_REG (TImode, regno);
8489 ops[1] = operands[1];
8490 output_asm_insn ("vldrw.f32\t%q0, %E1",ops);
8493 [(set_attr "length" "4")])
8496 ;; [vldrwq_s vldrwq_u]
8498 (define_insn "mve_vldrwq_<supf>v4si"
8499 [(set (match_operand:V4SI 0 "s_register_operand" "=w")
8500 (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us")]
8506 int regno = REGNO (operands[0]);
8507 ops[0] = gen_rtx_REG (TImode, regno);
8508 ops[1] = operands[1];
8509 output_asm_insn ("vldrw.<supf>32\t%q0, %E1",ops);
8512 [(set_attr "length" "4")])
8517 (define_insn "mve_vldrwq_z_fv4sf"
8518 [(set (match_operand:V4SF 0 "s_register_operand" "=w")
8519 (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us")
8520 (match_operand:HI 2 "vpr_register_operand" "Up")]
8523 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8526 int regno = REGNO (operands[0]);
8527 ops[0] = gen_rtx_REG (TImode, regno);
8528 ops[1] = operands[1];
8529 output_asm_insn ("vpst\n\tvldrwt.f32\t%q0, %E1",ops);
8532 [(set_attr "length" "8")])
8535 ;; [vldrwq_z_s vldrwq_z_u]
8537 (define_insn "mve_vldrwq_z_<supf>v4si"
8538 [(set (match_operand:V4SI 0 "s_register_operand" "=w")
8539 (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us")
8540 (match_operand:HI 2 "vpr_register_operand" "Up")]
8546 int regno = REGNO (operands[0]);
8547 ops[0] = gen_rtx_REG (TImode, regno);
8548 ops[1] = operands[1];
8549 output_asm_insn ("vpst\n\tvldrwt.<supf>32\t%q0, %E1",ops);
8552 [(set_attr "length" "8")])
8554 (define_expand "mve_vld1q_f<mode>"
8555 [(match_operand:MVE_0 0 "s_register_operand")
8556 (unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "memory_operand")] VLD1Q_F)
8558 "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT"
8560 emit_insn (gen_mve_vldr<V_sz_elem1>q_f<mode>(operands[0],operands[1]));
8564 (define_expand "mve_vld1q_<supf><mode>"
8565 [(match_operand:MVE_2 0 "s_register_operand")
8566 (unspec:MVE_2 [(match_operand:MVE_2 1 "memory_operand")] VLD1Q)
8570 emit_insn (gen_mve_vldr<V_sz_elem1>q_<supf><mode>(operands[0],operands[1]));
8575 ;; [vldrdq_gather_base_s vldrdq_gather_base_u]
8577 (define_insn "mve_vldrdq_gather_base_<supf>v2di"
8578 [(set (match_operand:V2DI 0 "s_register_operand" "=&w")
8579 (unspec:V2DI [(match_operand:V2DI 1 "s_register_operand" "w")
8580 (match_operand:SI 2 "immediate_operand" "i")]
8586 ops[0] = operands[0];
8587 ops[1] = operands[1];
8588 ops[2] = operands[2];
8589 output_asm_insn ("vldrd.64\t%q0, [%q1, %2]",ops);
8592 [(set_attr "length" "4")])
8595 ;; [vldrdq_gather_base_z_s vldrdq_gather_base_z_u]
8597 (define_insn "mve_vldrdq_gather_base_z_<supf>v2di"
8598 [(set (match_operand:V2DI 0 "s_register_operand" "=&w")
8599 (unspec:V2DI [(match_operand:V2DI 1 "s_register_operand" "w")
8600 (match_operand:SI 2 "immediate_operand" "i")
8601 (match_operand:HI 3 "vpr_register_operand" "Up")]
8607 ops[0] = operands[0];
8608 ops[1] = operands[1];
8609 ops[2] = operands[2];
8610 output_asm_insn ("vpst\n\tvldrdt.u64\t%q0, [%q1, %2]",ops);
8613 [(set_attr "length" "8")])
8616 ;; [vldrdq_gather_offset_s vldrdq_gather_offset_u]
8618 (define_insn "mve_vldrdq_gather_offset_<supf>v2di"
8619 [(set (match_operand:V2DI 0 "s_register_operand" "=&w")
8620 (unspec:V2DI [(match_operand:V2DI 1 "memory_operand" "Us")
8621 (match_operand:V2DI 2 "s_register_operand" "w")]
8627 ops[0] = operands[0];
8628 ops[1] = operands[1];
8629 ops[2] = operands[2];
8630 output_asm_insn ("vldrd.u64\t%q0, [%m1, %q2]",ops);
8633 [(set_attr "length" "4")])
8636 ;; [vldrdq_gather_offset_z_s vldrdq_gather_offset_z_u]
8638 (define_insn "mve_vldrdq_gather_offset_z_<supf>v2di"
8639 [(set (match_operand:V2DI 0 "s_register_operand" "=&w")
8640 (unspec:V2DI [(match_operand:V2DI 1 "memory_operand" "Us")
8641 (match_operand:V2DI 2 "s_register_operand" "w")
8642 (match_operand:HI 3 "vpr_register_operand" "Up")]
8648 ops[0] = operands[0];
8649 ops[1] = operands[1];
8650 ops[2] = operands[2];
8651 output_asm_insn ("vpst\n\tvldrdt.u64\t%q0, [%m1, %q2]",ops);
8654 [(set_attr "length" "8")])
8657 ;; [vldrdq_gather_shifted_offset_s vldrdq_gather_shifted_offset_u]
8659 (define_insn "mve_vldrdq_gather_shifted_offset_<supf>v2di"
8660 [(set (match_operand:V2DI 0 "s_register_operand" "=&w")
8661 (unspec:V2DI [(match_operand:V2DI 1 "memory_operand" "Us")
8662 (match_operand:V2DI 2 "s_register_operand" "w")]
8668 ops[0] = operands[0];
8669 ops[1] = operands[1];
8670 ops[2] = operands[2];
8671 output_asm_insn ("vldrd.u64\t%q0, [%m1, %q2, uxtw #3]",ops);
8674 [(set_attr "length" "4")])
8677 ;; [vldrdq_gather_shifted_offset_z_s vldrdq_gather_shifted_offset_z_u]
8679 (define_insn "mve_vldrdq_gather_shifted_offset_z_<supf>v2di"
8680 [(set (match_operand:V2DI 0 "s_register_operand" "=&w")
8681 (unspec:V2DI [(match_operand:V2DI 1 "memory_operand" "Us")
8682 (match_operand:V2DI 2 "s_register_operand" "w")
8683 (match_operand:HI 3 "vpr_register_operand" "Up")]
8689 ops[0] = operands[0];
8690 ops[1] = operands[1];
8691 ops[2] = operands[2];
8692 output_asm_insn ("vpst\n\tvldrdt.u64\t%q0, [%m1, %q2, uxtw #3]",ops);
8695 [(set_attr "length" "8")])
8698 ;; [vldrhq_gather_offset_f]
8700 (define_insn "mve_vldrhq_gather_offset_fv8hf"
8701 [(set (match_operand:V8HF 0 "s_register_operand" "=&w")
8702 (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us")
8703 (match_operand:V8HI 2 "s_register_operand" "w")]
8706 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8709 ops[0] = operands[0];
8710 ops[1] = operands[1];
8711 ops[2] = operands[2];
8712 output_asm_insn ("vldrh.f16\t%q0, [%m1, %q2]",ops);
8715 [(set_attr "length" "4")])
8718 ;; [vldrhq_gather_offset_z_f]
8720 (define_insn "mve_vldrhq_gather_offset_z_fv8hf"
8721 [(set (match_operand:V8HF 0 "s_register_operand" "=&w")
8722 (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us")
8723 (match_operand:V8HI 2 "s_register_operand" "w")
8724 (match_operand:HI 3 "vpr_register_operand" "Up")]
8727 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8730 ops[0] = operands[0];
8731 ops[1] = operands[1];
8732 ops[2] = operands[2];
8733 ops[3] = operands[3];
8734 output_asm_insn ("vpst\n\tvldrht.f16\t%q0, [%m1, %q2]",ops);
8737 [(set_attr "length" "8")])
8740 ;; [vldrhq_gather_shifted_offset_f]
8742 (define_insn "mve_vldrhq_gather_shifted_offset_fv8hf"
8743 [(set (match_operand:V8HF 0 "s_register_operand" "=&w")
8744 (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us")
8745 (match_operand:V8HI 2 "s_register_operand" "w")]
8748 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8751 ops[0] = operands[0];
8752 ops[1] = operands[1];
8753 ops[2] = operands[2];
8754 output_asm_insn ("vldrh.f16\t%q0, [%m1, %q2, uxtw #1]",ops);
8757 [(set_attr "length" "4")])
8760 ;; [vldrhq_gather_shifted_offset_z_f]
8762 (define_insn "mve_vldrhq_gather_shifted_offset_z_fv8hf"
8763 [(set (match_operand:V8HF 0 "s_register_operand" "=&w")
8764 (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us")
8765 (match_operand:V8HI 2 "s_register_operand" "w")
8766 (match_operand:HI 3 "vpr_register_operand" "Up")]
8769 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8772 ops[0] = operands[0];
8773 ops[1] = operands[1];
8774 ops[2] = operands[2];
8775 ops[3] = operands[3];
8776 output_asm_insn ("vpst\n\tvldrht.f16\t%q0, [%m1, %q2, uxtw #1]",ops);
8779 [(set_attr "length" "8")])
8782 ;; [vldrwq_gather_base_f]
8784 (define_insn "mve_vldrwq_gather_base_fv4sf"
8785 [(set (match_operand:V4SF 0 "s_register_operand" "=&w")
8786 (unspec:V4SF [(match_operand:V4SI 1 "s_register_operand" "w")
8787 (match_operand:SI 2 "immediate_operand" "i")]
8790 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8793 ops[0] = operands[0];
8794 ops[1] = operands[1];
8795 ops[2] = operands[2];
8796 output_asm_insn ("vldrw.u32\t%q0, [%q1, %2]",ops);
8799 [(set_attr "length" "4")])
8802 ;; [vldrwq_gather_base_z_f]
8804 (define_insn "mve_vldrwq_gather_base_z_fv4sf"
8805 [(set (match_operand:V4SF 0 "s_register_operand" "=&w")
8806 (unspec:V4SF [(match_operand:V4SI 1 "s_register_operand" "w")
8807 (match_operand:SI 2 "immediate_operand" "i")
8808 (match_operand:HI 3 "vpr_register_operand" "Up")]
8811 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8814 ops[0] = operands[0];
8815 ops[1] = operands[1];
8816 ops[2] = operands[2];
8817 output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%q1, %2]",ops);
8820 [(set_attr "length" "8")])
8823 ;; [vldrwq_gather_offset_f]
8825 (define_insn "mve_vldrwq_gather_offset_fv4sf"
8826 [(set (match_operand:V4SF 0 "s_register_operand" "=&w")
8827 (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us")
8828 (match_operand:V4SI 2 "s_register_operand" "w")]
8831 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8834 ops[0] = operands[0];
8835 ops[1] = operands[1];
8836 ops[2] = operands[2];
8837 output_asm_insn ("vldrw.u32\t%q0, [%m1, %q2]",ops);
8840 [(set_attr "length" "4")])
8843 ;; [vldrwq_gather_offset_s vldrwq_gather_offset_u]
8845 (define_insn "mve_vldrwq_gather_offset_<supf>v4si"
8846 [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
8847 (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us")
8848 (match_operand:V4SI 2 "s_register_operand" "w")]
8854 ops[0] = operands[0];
8855 ops[1] = operands[1];
8856 ops[2] = operands[2];
8857 output_asm_insn ("vldrw.u32\t%q0, [%m1, %q2]",ops);
8860 [(set_attr "length" "4")])
8863 ;; [vldrwq_gather_offset_z_f]
8865 (define_insn "mve_vldrwq_gather_offset_z_fv4sf"
8866 [(set (match_operand:V4SF 0 "s_register_operand" "=&w")
8867 (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us")
8868 (match_operand:V4SI 2 "s_register_operand" "w")
8869 (match_operand:HI 3 "vpr_register_operand" "Up")]
8872 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8875 ops[0] = operands[0];
8876 ops[1] = operands[1];
8877 ops[2] = operands[2];
8878 ops[3] = operands[3];
8879 output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%m1, %q2]",ops);
8882 [(set_attr "length" "8")])
8885 ;; [vldrwq_gather_offset_z_s vldrwq_gather_offset_z_u]
8887 (define_insn "mve_vldrwq_gather_offset_z_<supf>v4si"
8888 [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
8889 (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us")
8890 (match_operand:V4SI 2 "s_register_operand" "w")
8891 (match_operand:HI 3 "vpr_register_operand" "Up")]
8897 ops[0] = operands[0];
8898 ops[1] = operands[1];
8899 ops[2] = operands[2];
8900 ops[3] = operands[3];
8901 output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%m1, %q2]",ops);
8904 [(set_attr "length" "8")])
8907 ;; [vldrwq_gather_shifted_offset_f]
8909 (define_insn "mve_vldrwq_gather_shifted_offset_fv4sf"
8910 [(set (match_operand:V4SF 0 "s_register_operand" "=&w")
8911 (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us")
8912 (match_operand:V4SI 2 "s_register_operand" "w")]
8915 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8918 ops[0] = operands[0];
8919 ops[1] = operands[1];
8920 ops[2] = operands[2];
8921 output_asm_insn ("vldrw.u32\t%q0, [%m1, %q2, uxtw #2]",ops);
8924 [(set_attr "length" "4")])
8927 ;; [vldrwq_gather_shifted_offset_s vldrwq_gather_shifted_offset_u]
8929 (define_insn "mve_vldrwq_gather_shifted_offset_<supf>v4si"
8930 [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
8931 (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us")
8932 (match_operand:V4SI 2 "s_register_operand" "w")]
8938 ops[0] = operands[0];
8939 ops[1] = operands[1];
8940 ops[2] = operands[2];
8941 output_asm_insn ("vldrw.u32\t%q0, [%m1, %q2, uxtw #2]",ops);
8944 [(set_attr "length" "4")])
8947 ;; [vldrwq_gather_shifted_offset_z_f]
8949 (define_insn "mve_vldrwq_gather_shifted_offset_z_fv4sf"
8950 [(set (match_operand:V4SF 0 "s_register_operand" "=&w")
8951 (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us")
8952 (match_operand:V4SI 2 "s_register_operand" "w")
8953 (match_operand:HI 3 "vpr_register_operand" "Up")]
8956 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8959 ops[0] = operands[0];
8960 ops[1] = operands[1];
8961 ops[2] = operands[2];
8962 ops[3] = operands[3];
8963 output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%m1, %q2, uxtw #2]",ops);
8966 [(set_attr "length" "8")])
8969 ;; [vldrwq_gather_shifted_offset_z_s vldrwq_gather_shifted_offset_z_u]
8971 (define_insn "mve_vldrwq_gather_shifted_offset_z_<supf>v4si"
8972 [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
8973 (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us")
8974 (match_operand:V4SI 2 "s_register_operand" "w")
8975 (match_operand:HI 3 "vpr_register_operand" "Up")]
8981 ops[0] = operands[0];
8982 ops[1] = operands[1];
8983 ops[2] = operands[2];
8984 ops[3] = operands[3];
8985 output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%m1, %q2, uxtw #2]",ops);
8988 [(set_attr "length" "8")])
8993 (define_insn "mve_vstrhq_fv8hf"
8994 [(set (match_operand:V8HI 0 "memory_operand" "=Us")
8995 (unspec:V8HI [(match_operand:V8HF 1 "s_register_operand" "w")]
8998 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
9001 int regno = REGNO (operands[1]);
9002 ops[1] = gen_rtx_REG (TImode, regno);
9003 ops[0] = operands[0];
9004 output_asm_insn ("vstrh.16\t%q1, %E0",ops);
9007 [(set_attr "length" "4")])
9012 (define_insn "mve_vstrhq_p_fv8hf"
9013 [(set (match_operand:V8HI 0 "memory_operand" "=Us")
9014 (unspec:V8HI [(match_operand:V8HF 1 "s_register_operand" "w")
9015 (match_operand:HI 2 "vpr_register_operand" "Up")]
9018 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
9021 int regno = REGNO (operands[1]);
9022 ops[1] = gen_rtx_REG (TImode, regno);
9023 ops[0] = operands[0];
9024 output_asm_insn ("vpst\n\tvstrht.16\t%q1, %E0",ops);
9027 [(set_attr "length" "8")])
9030 ;; [vstrhq_p_s vstrhq_p_u]
9032 (define_insn "mve_vstrhq_p_<supf><mode>"
9033 [(set (match_operand:<MVE_H_ELEM> 0 "memory_operand" "=Us")
9034 (unspec:<MVE_H_ELEM> [(match_operand:MVE_6 1 "s_register_operand" "w")
9035 (match_operand:HI 2 "vpr_register_operand" "Up")]
9041 int regno = REGNO (operands[1]);
9042 ops[1] = gen_rtx_REG (TImode, regno);
9043 ops[0] = operands[0];
9044 output_asm_insn ("vpst\n\tvstrht.<V_sz_elem>\t%q1, %E0",ops);
9047 [(set_attr "length" "8")])
9050 ;; [vstrhq_scatter_offset_p_s vstrhq_scatter_offset_p_u]
9052 (define_insn "mve_vstrhq_scatter_offset_p_<supf><mode>"
9053 [(set (match_operand:<MVE_H_ELEM> 0 "memory_operand" "=Us")
9054 (unspec:<MVE_H_ELEM>
9055 [(match_operand:MVE_6 1 "s_register_operand" "w")
9056 (match_operand:MVE_6 2 "s_register_operand" "w")
9057 (match_operand:HI 3 "vpr_register_operand" "Up")]
9063 ops[0] = operands[0];
9064 ops[1] = operands[1];
9065 ops[2] = operands[2];
9066 output_asm_insn ("vpst\n\tvstrht.<V_sz_elem>\t%q2, [%m0, %q1]",ops);
9069 [(set_attr "length" "8")])
9072 ;; [vstrhq_scatter_offset_s vstrhq_scatter_offset_u]
9074 (define_insn "mve_vstrhq_scatter_offset_<supf><mode>"
9075 [(set (match_operand:<MVE_H_ELEM> 0 "memory_operand" "=Us")
9076 (unspec:<MVE_H_ELEM>
9077 [(match_operand:MVE_6 1 "s_register_operand" "w")
9078 (match_operand:MVE_6 2 "s_register_operand" "w")]
9084 ops[0] = operands[0];
9085 ops[1] = operands[1];
9086 ops[2] = operands[2];
9087 output_asm_insn ("vstrh.<V_sz_elem>\t%q2, [%m0, %q1]",ops);
9090 [(set_attr "length" "4")])
9093 ;; [vstrhq_scatter_shifted_offset_p_s vstrhq_scatter_shifted_offset_p_u]
9095 (define_insn "mve_vstrhq_scatter_shifted_offset_p_<supf><mode>"
9096 [(set (match_operand:<MVE_H_ELEM> 0 "memory_operand" "=Us")
9097 (unspec:<MVE_H_ELEM>
9098 [(match_operand:MVE_6 1 "s_register_operand" "w")
9099 (match_operand:MVE_6 2 "s_register_operand" "w")
9100 (match_operand:HI 3 "vpr_register_operand" "Up")]
9106 ops[0] = operands[0];
9107 ops[1] = operands[1];
9108 ops[2] = operands[2];
9109 output_asm_insn ("vpst\n\tvstrht.<V_sz_elem>\t%q2, [%m0, %q1, uxtw #1]",ops);
9112 [(set_attr "length" "8")])
9115 ;; [vstrhq_scatter_shifted_offset_s vstrhq_scatter_shifted_offset_u]
9117 (define_insn "mve_vstrhq_scatter_shifted_offset_<supf><mode>"
9118 [(set (match_operand:<MVE_H_ELEM> 0 "memory_operand" "=Us")
9119 (unspec:<MVE_H_ELEM>
9120 [(match_operand:MVE_6 1 "s_register_operand" "w")
9121 (match_operand:MVE_6 2 "s_register_operand" "w")]
9127 ops[0] = operands[0];
9128 ops[1] = operands[1];
9129 ops[2] = operands[2];
9130 output_asm_insn ("vstrh.<V_sz_elem>\t%q2, [%m0, %q1, uxtw #1]",ops);
9133 [(set_attr "length" "4")])
9136 ;; [vstrhq_s, vstrhq_u]
9138 (define_insn "mve_vstrhq_<supf><mode>"
9139 [(set (match_operand:<MVE_H_ELEM> 0 "memory_operand" "=Us")
9140 (unspec:<MVE_H_ELEM> [(match_operand:MVE_6 1 "s_register_operand" "w")]
9146 int regno = REGNO (operands[1]);
9147 ops[1] = gen_rtx_REG (TImode, regno);
9148 ops[0] = operands[0];
9149 output_asm_insn ("vstrh.<V_sz_elem>\t%q1, %E0",ops);
9152 [(set_attr "length" "4")])
9157 (define_insn "mve_vstrwq_fv4sf"
9158 [(set (match_operand:V4SI 0 "memory_operand" "=Us")
9159 (unspec:V4SI [(match_operand:V4SF 1 "s_register_operand" "w")]
9162 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
9165 int regno = REGNO (operands[1]);
9166 ops[1] = gen_rtx_REG (TImode, regno);
9167 ops[0] = operands[0];
9168 output_asm_insn ("vstrw.32\t%q1, %E0",ops);
9171 [(set_attr "length" "4")])
9176 (define_insn "mve_vstrwq_p_fv4sf"
9177 [(set (match_operand:V4SI 0 "memory_operand" "=Us")
9178 (unspec:V4SI [(match_operand:V4SF 1 "s_register_operand" "w")
9179 (match_operand:HI 2 "vpr_register_operand" "Up")]
9182 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
9185 int regno = REGNO (operands[1]);
9186 ops[1] = gen_rtx_REG (TImode, regno);
9187 ops[0] = operands[0];
9188 output_asm_insn ("vpst\n\tvstrwt.32\t%q1, %E0",ops);
9191 [(set_attr "length" "8")])
9194 ;; [vstrwq_p_s vstrwq_p_u]
9196 (define_insn "mve_vstrwq_p_<supf>v4si"
9197 [(set (match_operand:V4SI 0 "memory_operand" "=Us")
9198 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
9199 (match_operand:HI 2 "vpr_register_operand" "Up")]
9205 int regno = REGNO (operands[1]);
9206 ops[1] = gen_rtx_REG (TImode, regno);
9207 ops[0] = operands[0];
9208 output_asm_insn ("vpst\n\tvstrwt.32\t%q1, %E0",ops);
9211 [(set_attr "length" "8")])
9214 ;; [vstrwq_s vstrwq_u]
9216 (define_insn "mve_vstrwq_<supf>v4si"
9217 [(set (match_operand:V4SI 0 "memory_operand" "=Us")
9218 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")]
9224 int regno = REGNO (operands[1]);
9225 ops[1] = gen_rtx_REG (TImode, regno);
9226 ops[0] = operands[0];
9227 output_asm_insn ("vstrw.32\t%q1, %E0",ops);
9230 [(set_attr "length" "4")])
9232 (define_expand "mve_vst1q_f<mode>"
9233 [(match_operand:<MVE_CNVT> 0 "memory_operand")
9234 (unspec:<MVE_CNVT> [(match_operand:MVE_0 1 "s_register_operand")] VST1Q_F)
9236 "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT"
9238 emit_insn (gen_mve_vstr<V_sz_elem1>q_f<mode>(operands[0],operands[1]));
9242 (define_expand "mve_vst1q_<supf><mode>"
9243 [(match_operand:MVE_2 0 "memory_operand")
9244 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand")] VST1Q)
9248 emit_insn (gen_mve_vstr<V_sz_elem1>q_<supf><mode>(operands[0],operands[1]));
9253 ;; [vstrdq_scatter_base_p_s vstrdq_scatter_base_p_u]
9255 (define_insn "mve_vstrdq_scatter_base_p_<supf>v2di"
9256 [(set (mem:BLK (scratch))
9258 [(match_operand:V2DI 0 "s_register_operand" "w")
9259 (match_operand:SI 1 "mve_vldrd_immediate" "Ri")
9260 (match_operand:V2DI 2 "s_register_operand" "w")
9261 (match_operand:HI 3 "vpr_register_operand" "Up")]
9267 ops[0] = operands[0];
9268 ops[1] = operands[1];
9269 ops[2] = operands[2];
9270 output_asm_insn ("vpst\;\tvstrdt.u64\t%q2, [%q0, %1]",ops);
9273 [(set_attr "length" "8")])
9276 ;; [vstrdq_scatter_base_s vstrdq_scatter_base_u]
9278 (define_insn "mve_vstrdq_scatter_base_<supf>v2di"
9279 [(set (mem:BLK (scratch))
9281 [(match_operand:V2DI 0 "s_register_operand" "=w")
9282 (match_operand:SI 1 "mve_vldrd_immediate" "Ri")
9283 (match_operand:V2DI 2 "s_register_operand" "w")]
9289 ops[0] = operands[0];
9290 ops[1] = operands[1];
9291 ops[2] = operands[2];
9292 output_asm_insn ("vstrd.u64\t%q2, [%q0, %1]",ops);
9295 [(set_attr "length" "4")])
9298 ;; [vstrdq_scatter_offset_p_s vstrdq_scatter_offset_p_u]
9300 (define_insn "mve_vstrdq_scatter_offset_p_<supf>v2di"
9301 [(set (match_operand:V2DI 0 "memory_operand" "=Us")
9303 [(match_operand:V2DI 1 "s_register_operand" "w")
9304 (match_operand:V2DI 2 "s_register_operand" "w")
9305 (match_operand:HI 3 "vpr_register_operand" "Up")]
9311 ops[0] = operands[0];
9312 ops[1] = operands[1];
9313 ops[2] = operands[2];
9314 output_asm_insn ("vpst\;\tvstrdt.64\t%q2, [%m0, %q1]",ops);
9317 [(set_attr "length" "8")])
9320 ;; [vstrdq_scatter_offset_s vstrdq_scatter_offset_u]
9322 (define_insn "mve_vstrdq_scatter_offset_<supf>v2di"
9323 [(set (match_operand:V2DI 0 "memory_operand" "=Us")
9325 [(match_operand:V2DI 1 "s_register_operand" "w")
9326 (match_operand:V2DI 2 "s_register_operand" "w")]
9332 ops[0] = operands[0];
9333 ops[1] = operands[1];
9334 ops[2] = operands[2];
9335 output_asm_insn ("vstrd.64\t%q2, [%m0, %q1]",ops);
9338 [(set_attr "length" "4")])
9341 ;; [vstrdq_scatter_shifted_offset_p_s vstrdq_scatter_shifted_offset_p_u]
9343 (define_insn "mve_vstrdq_scatter_shifted_offset_p_<supf>v2di"
9344 [(set (match_operand:V2DI 0 "memory_operand" "=Us")
9346 [(match_operand:V2DI 1 "s_register_operand" "w")
9347 (match_operand:V2DI 2 "s_register_operand" "w")
9348 (match_operand:HI 3 "vpr_register_operand" "Up")]
9354 ops[0] = operands[0];
9355 ops[1] = operands[1];
9356 ops[2] = operands[2];
9357 output_asm_insn ("vpst\;\tvstrdt.64\t%q2, [%m0, %q1, UXTW #3]",ops);
9360 [(set_attr "length" "8")])
9363 ;; [vstrdq_scatter_shifted_offset_s vstrdq_scatter_shifted_offset_u]
9365 (define_insn "mve_vstrdq_scatter_shifted_offset_<supf>v2di"
9366 [(set (match_operand:V2DI 0 "memory_operand" "=Us")
9368 [(match_operand:V2DI 1 "s_register_operand" "w")
9369 (match_operand:V2DI 2 "s_register_operand" "w")]
9375 ops[0] = operands[0];
9376 ops[1] = operands[1];
9377 ops[2] = operands[2];
9378 output_asm_insn ("vstrd.64\t%q2, [%m0, %q1, UXTW #3]",ops);
9381 [(set_attr "length" "4")])
9384 ;; [vstrhq_scatter_offset_f]
9386 (define_insn "mve_vstrhq_scatter_offset_fv8hf"
9387 [(set (match_operand:V8HI 0 "memory_operand" "=Us")
9389 [(match_operand:V8HI 1 "s_register_operand" "w")
9390 (match_operand:V8HF 2 "s_register_operand" "w")]
9393 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
9396 ops[0] = operands[0];
9397 ops[1] = operands[1];
9398 ops[2] = operands[2];
9399 output_asm_insn ("vstrh.16\t%q2, [%m0, %q1]",ops);
9402 [(set_attr "length" "4")])
9405 ;; [vstrhq_scatter_offset_p_f]
9407 (define_insn "mve_vstrhq_scatter_offset_p_fv8hf"
9408 [(set (match_operand:V8HI 0 "memory_operand" "=Us")
9410 [(match_operand:V8HI 1 "s_register_operand" "w")
9411 (match_operand:V8HF 2 "s_register_operand" "w")
9412 (match_operand:HI 3 "vpr_register_operand" "Up")]
9415 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
9418 ops[0] = operands[0];
9419 ops[1] = operands[1];
9420 ops[2] = operands[2];
9421 output_asm_insn ("vpst\n\tvstrht.16\t%q2, [%m0, %q1]",ops);
9424 [(set_attr "length" "8")])
9427 ;; [vstrhq_scatter_shifted_offset_f]
9429 (define_insn "mve_vstrhq_scatter_shifted_offset_fv8hf"
9430 [(set (match_operand:V8HI 0 "memory_operand" "=Us")
9432 [(match_operand:V8HI 1 "s_register_operand" "w")
9433 (match_operand:V8HF 2 "s_register_operand" "w")]
9436 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
9439 ops[0] = operands[0];
9440 ops[1] = operands[1];
9441 ops[2] = operands[2];
9442 output_asm_insn ("vstrh.16\t%q2, [%m0, %q1, uxtw #1]",ops);
9445 [(set_attr "length" "4")])
9448 ;; [vstrhq_scatter_shifted_offset_p_f]
9450 (define_insn "mve_vstrhq_scatter_shifted_offset_p_fv8hf"
9451 [(set (match_operand:V8HI 0 "memory_operand" "=Us")
9453 [(match_operand:V8HI 1 "s_register_operand" "w")
9454 (match_operand:V8HF 2 "s_register_operand" "w")
9455 (match_operand:HI 3 "vpr_register_operand" "Up")]
9458 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
9461 ops[0] = operands[0];
9462 ops[1] = operands[1];
9463 ops[2] = operands[2];
9464 output_asm_insn ("vpst\n\tvstrht.16\t%q2, [%m0, %q1, uxtw #1]",ops);
9467 [(set_attr "length" "8")])
9470 ;; [vstrwq_scatter_base_f]
9472 (define_insn "mve_vstrwq_scatter_base_fv4sf"
9473 [(set (mem:BLK (scratch))
9475 [(match_operand:V4SI 0 "s_register_operand" "w")
9476 (match_operand:SI 1 "immediate_operand" "i")
9477 (match_operand:V4SF 2 "s_register_operand" "w")]
9480 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
9483 ops[0] = operands[0];
9484 ops[1] = operands[1];
9485 ops[2] = operands[2];
9486 output_asm_insn ("vstrw.u32\t%q2, [%q0, %1]",ops);
9489 [(set_attr "length" "4")])
9492 ;; [vstrwq_scatter_base_p_f]
9494 (define_insn "mve_vstrwq_scatter_base_p_fv4sf"
9495 [(set (mem:BLK (scratch))
9497 [(match_operand:V4SI 0 "s_register_operand" "w")
9498 (match_operand:SI 1 "immediate_operand" "i")
9499 (match_operand:V4SF 2 "s_register_operand" "w")
9500 (match_operand:HI 3 "vpr_register_operand" "Up")]
9503 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
9506 ops[0] = operands[0];
9507 ops[1] = operands[1];
9508 ops[2] = operands[2];
9509 output_asm_insn ("vpst\n\tvstrwt.u32\t%q2, [%q0, %1]",ops);
9512 [(set_attr "length" "8")])
9515 ;; [vstrwq_scatter_offset_f]
9517 (define_insn "mve_vstrwq_scatter_offset_fv4sf"
9518 [(set (match_operand:V4SI 0 "memory_operand" "=Us")
9520 [(match_operand:V4SI 1 "s_register_operand" "w")
9521 (match_operand:V4SF 2 "s_register_operand" "w")]
9524 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
9527 ops[0] = operands[0];
9528 ops[1] = operands[1];
9529 ops[2] = operands[2];
9530 output_asm_insn ("vstrw.32\t%q2, [%m0, %q1]",ops);
9533 [(set_attr "length" "4")])
9536 ;; [vstrwq_scatter_offset_p_f]
9538 (define_insn "mve_vstrwq_scatter_offset_p_fv4sf"
9539 [(set (match_operand:V4SI 0 "memory_operand" "=Us")
9541 [(match_operand:V4SI 1 "s_register_operand" "w")
9542 (match_operand:V4SF 2 "s_register_operand" "w")
9543 (match_operand:HI 3 "vpr_register_operand" "Up")]
9546 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
9549 ops[0] = operands[0];
9550 ops[1] = operands[1];
9551 ops[2] = operands[2];
9552 output_asm_insn ("vpst\n\tvstrwt.32\t%q2, [%m0, %q1]",ops);
9555 [(set_attr "length" "8")])
9558 ;; [vstrwq_scatter_offset_p_s vstrwq_scatter_offset_p_u]
9560 (define_insn "mve_vstrwq_scatter_offset_p_<supf>v4si"
9561 [(set (match_operand:V4SI 0 "memory_operand" "=Us")
9563 [(match_operand:V4SI 1 "s_register_operand" "w")
9564 (match_operand:V4SI 2 "s_register_operand" "w")
9565 (match_operand:HI 3 "vpr_register_operand" "Up")]
9571 ops[0] = operands[0];
9572 ops[1] = operands[1];
9573 ops[2] = operands[2];
9574 output_asm_insn ("vpst\n\tvstrwt.32\t%q2, [%m0, %q1]",ops);
9577 [(set_attr "length" "8")])
9580 ;; [vstrwq_scatter_offset_s vstrwq_scatter_offset_u]
9582 (define_insn "mve_vstrwq_scatter_offset_<supf>v4si"
9583 [(set (match_operand:V4SI 0 "memory_operand" "=Us")
9585 [(match_operand:V4SI 1 "s_register_operand" "w")
9586 (match_operand:V4SI 2 "s_register_operand" "w")]
9592 ops[0] = operands[0];
9593 ops[1] = operands[1];
9594 ops[2] = operands[2];
9595 output_asm_insn ("vstrw.32\t%q2, [%m0, %q1]",ops);
9598 [(set_attr "length" "4")])
9601 ;; [vstrwq_scatter_shifted_offset_f]
9603 (define_insn "mve_vstrwq_scatter_shifted_offset_fv4sf"
9604 [(set (match_operand:V4SI 0 "memory_operand" "=Us")
9606 [(match_operand:V4SI 1 "s_register_operand" "w")
9607 (match_operand:V4SF 2 "s_register_operand" "w")]
9610 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
9613 ops[0] = operands[0];
9614 ops[1] = operands[1];
9615 ops[2] = operands[2];
9616 output_asm_insn ("vstrw.32\t%q2, [%m0, %q1, uxtw #2]",ops);
9619 [(set_attr "length" "4")])
9622 ;; [vstrwq_scatter_shifted_offset_p_f]
9624 (define_insn "mve_vstrwq_scatter_shifted_offset_p_fv4sf"
9625 [(set (match_operand:V4SI 0 "memory_operand" "=Us")
9627 [(match_operand:V4SI 1 "s_register_operand" "w")
9628 (match_operand:V4SF 2 "s_register_operand" "w")
9629 (match_operand:HI 3 "vpr_register_operand" "Up")]
9632 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
9635 ops[0] = operands[0];
9636 ops[1] = operands[1];
9637 ops[2] = operands[2];
9638 output_asm_insn ("vpst\;\tvstrwt.32\t%q2, [%m0, %q1, uxtw #2]",ops);
9641 [(set_attr "length" "8")])
9644 ;; [vstrwq_scatter_shifted_offset_p_s vstrwq_scatter_shifted_offset_p_u]
9646 (define_insn "mve_vstrwq_scatter_shifted_offset_p_<supf>v4si"
9647 [(set (match_operand:V4SI 0 "memory_operand" "=Us")
9649 [(match_operand:V4SI 1 "s_register_operand" "w")
9650 (match_operand:V4SI 2 "s_register_operand" "w")
9651 (match_operand:HI 3 "vpr_register_operand" "Up")]
9657 ops[0] = operands[0];
9658 ops[1] = operands[1];
9659 ops[2] = operands[2];
9660 output_asm_insn ("vpst\;\tvstrwt.32\t%q2, [%m0, %q1, uxtw #2]",ops);
9663 [(set_attr "length" "8")])
9666 ;; [vstrwq_scatter_shifted_offset_s vstrwq_scatter_shifted_offset_u]
9668 (define_insn "mve_vstrwq_scatter_shifted_offset_<supf>v4si"
9669 [(set (match_operand:V4SI 0 "memory_operand" "=Us")
9671 [(match_operand:V4SI 1 "s_register_operand" "w")
9672 (match_operand:V4SI 2 "s_register_operand" "w")]
9678 ops[0] = operands[0];
9679 ops[1] = operands[1];
9680 ops[2] = operands[2];
9681 output_asm_insn ("vstrw.32\t%q2, [%m0, %q1, uxtw #2]",ops);
9684 [(set_attr "length" "4")])
9687 ;; [vaddq_s, vaddq_u])
9689 (define_insn "mve_vaddq<mode>"
9691 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
9692 (plus:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
9693 (match_operand:MVE_2 2 "s_register_operand" "w")))
9696 "vadd.i%#<V_sz_elem> %q0, %q1, %q2"
9697 [(set_attr "type" "mve_move")
9703 (define_insn "mve_vaddq_f<mode>"
9705 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
9706 (plus:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")
9707 (match_operand:MVE_0 2 "s_register_operand" "w")))
9709 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
9710 "vadd.f%#<V_sz_elem> %q0, %q1, %q2"
9711 [(set_attr "type" "mve_move")
9717 (define_expand "mve_vidupq_n_u<mode>"
9718 [(match_operand:MVE_2 0 "s_register_operand")
9719 (match_operand:SI 1 "s_register_operand")
9720 (match_operand:SI 2 "mve_imm_selective_upto_8")]
9723 rtx temp = gen_reg_rtx (SImode);
9724 emit_move_insn (temp, operands[1]);
9725 rtx inc = gen_int_mode (INTVAL(operands[2]) * <MVE_LANES>, SImode);
9726 emit_insn (gen_mve_vidupq_u<mode>_insn (operands[0], temp, operands[1],
9734 (define_insn "mve_vidupq_u<mode>_insn"
9735 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
9736 (unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1")
9737 (match_operand:SI 3 "mve_imm_selective_upto_8" "Rg")]
9739 (set (match_operand:SI 1 "s_register_operand" "=e")
9740 (plus:SI (match_dup 2)
9741 (match_operand:SI 4 "immediate_operand" "i")))]
9743 "vidup.u%#<V_sz_elem>\t%q0, %1, %3")
9748 (define_expand "mve_vidupq_m_n_u<mode>"
9749 [(match_operand:MVE_2 0 "s_register_operand")
9750 (match_operand:MVE_2 1 "s_register_operand")
9751 (match_operand:SI 2 "s_register_operand")
9752 (match_operand:SI 3 "mve_imm_selective_upto_8")
9753 (match_operand:HI 4 "vpr_register_operand")]
9756 rtx temp = gen_reg_rtx (SImode);
9757 emit_move_insn (temp, operands[2]);
9758 rtx inc = gen_int_mode (INTVAL(operands[3]) * <MVE_LANES>, SImode);
9759 emit_insn (gen_mve_vidupq_m_wb_u<mode>_insn(operands[0], operands[1], temp,
9760 operands[2], operands[3],
9766 ;; [vidupq_m_wb_u_insn])
9768 (define_insn "mve_vidupq_m_wb_u<mode>_insn"
9769 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
9770 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
9771 (match_operand:SI 3 "s_register_operand" "2")
9772 (match_operand:SI 4 "mve_imm_selective_upto_8" "Rg")
9773 (match_operand:HI 5 "vpr_register_operand" "Up")]
9775 (set (match_operand:SI 2 "s_register_operand" "=e")
9776 (plus:SI (match_dup 3)
9777 (match_operand:SI 6 "immediate_operand" "i")))]
9779 "vpst\;\tvidupt.u%#<V_sz_elem>\t%q0, %2, %4"
9780 [(set_attr "length""8")])
9785 (define_expand "mve_vddupq_n_u<mode>"
9786 [(match_operand:MVE_2 0 "s_register_operand")
9787 (match_operand:SI 1 "s_register_operand")
9788 (match_operand:SI 2 "mve_imm_selective_upto_8")]
9791 rtx temp = gen_reg_rtx (SImode);
9792 emit_move_insn (temp, operands[1]);
9793 rtx inc = gen_int_mode (INTVAL(operands[2]) * <MVE_LANES>, SImode);
9794 emit_insn (gen_mve_vddupq_u<mode>_insn (operands[0], temp, operands[1],
9802 (define_insn "mve_vddupq_u<mode>_insn"
9803 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
9804 (unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1")
9805 (match_operand:SI 3 "immediate_operand" "i")]
9807 (set (match_operand:SI 1 "s_register_operand" "=e")
9808 (minus:SI (match_dup 2)
9809 (match_operand:SI 4 "immediate_operand" "i")))]
9811 "vddup.u%#<V_sz_elem> %q0, %1, %3")
9816 (define_expand "mve_vddupq_m_n_u<mode>"
9817 [(match_operand:MVE_2 0 "s_register_operand")
9818 (match_operand:MVE_2 1 "s_register_operand")
9819 (match_operand:SI 2 "s_register_operand")
9820 (match_operand:SI 3 "mve_imm_selective_upto_8")
9821 (match_operand:HI 4 "vpr_register_operand")]
9824 rtx temp = gen_reg_rtx (SImode);
9825 emit_move_insn (temp, operands[2]);
9826 rtx inc = gen_int_mode (INTVAL(operands[3]) * <MVE_LANES>, SImode);
9827 emit_insn (gen_mve_vddupq_m_wb_u<mode>_insn(operands[0], operands[1], temp,
9828 operands[2], operands[3],
9834 ;; [vddupq_m_wb_u_insn])
9836 (define_insn "mve_vddupq_m_wb_u<mode>_insn"
9837 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
9838 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
9839 (match_operand:SI 3 "s_register_operand" "2")
9840 (match_operand:SI 4 "mve_imm_selective_upto_8" "Rg")
9841 (match_operand:HI 5 "vpr_register_operand" "Up")]
9843 (set (match_operand:SI 2 "s_register_operand" "=e")
9844 (minus:SI (match_dup 3)
9845 (match_operand:SI 6 "immediate_operand" "i")))]
9847 "vpst\;\tvddupt.u%#<V_sz_elem>\t%q0, %2, %4"
9848 [(set_attr "length""8")])
9853 (define_expand "mve_vdwdupq_n_u<mode>"
9854 [(match_operand:MVE_2 0 "s_register_operand")
9855 (match_operand:SI 1 "s_register_operand")
9856 (match_operand:SI 2 "s_register_operand")
9857 (match_operand:SI 3 "mve_imm_selective_upto_8")]
9860 rtx ignore_wb = gen_reg_rtx (SImode);
9861 emit_insn (gen_mve_vdwdupq_wb_u<mode>_insn (operands[0], ignore_wb,
9862 operands[1], operands[2],
9870 (define_expand "mve_vdwdupq_wb_u<mode>"
9871 [(match_operand:SI 0 "s_register_operand")
9872 (match_operand:SI 1 "s_register_operand")
9873 (match_operand:SI 2 "s_register_operand")
9874 (match_operand:SI 3 "mve_imm_selective_upto_8")
9875 (unspec:MVE_2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
9878 rtx ignore_vec = gen_reg_rtx (<MODE>mode);
9879 emit_insn (gen_mve_vdwdupq_wb_u<mode>_insn (ignore_vec, operands[0],
9880 operands[1], operands[2],
9886 ;; [vdwdupq_wb_u_insn])
9888 (define_insn "mve_vdwdupq_wb_u<mode>_insn"
9889 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
9890 (unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1")
9891 (match_operand:SI 3 "s_register_operand" "r")
9892 (match_operand:SI 4 "mve_imm_selective_upto_8" "Rg")]
9894 (set (match_operand:SI 1 "s_register_operand" "=e")
9895 (unspec:SI [(match_dup 2)
9900 "vdwdup.u%#<V_sz_elem>\t%q0, %2, %3, %4"
9906 (define_expand "mve_vdwdupq_m_n_u<mode>"
9907 [(match_operand:MVE_2 0 "s_register_operand")
9908 (match_operand:MVE_2 1 "s_register_operand")
9909 (match_operand:SI 2 "s_register_operand")
9910 (match_operand:SI 3 "s_register_operand")
9911 (match_operand:SI 4 "mve_imm_selective_upto_8")
9912 (match_operand:HI 5 "vpr_register_operand")]
9915 rtx ignore_wb = gen_reg_rtx (SImode);
9916 emit_insn (gen_mve_vdwdupq_m_wb_u<mode>_insn (operands[0], ignore_wb,
9917 operands[1], operands[2],
9918 operands[3], operands[4],
9924 ;; [vdwdupq_m_wb_u])
9926 (define_expand "mve_vdwdupq_m_wb_u<mode>"
9927 [(match_operand:SI 0 "s_register_operand")
9928 (match_operand:MVE_2 1 "s_register_operand")
9929 (match_operand:SI 2 "s_register_operand")
9930 (match_operand:SI 3 "s_register_operand")
9931 (match_operand:SI 4 "mve_imm_selective_upto_8")
9932 (match_operand:HI 5 "vpr_register_operand")]
9935 rtx ignore_vec = gen_reg_rtx (<MODE>mode);
9936 emit_insn (gen_mve_vdwdupq_m_wb_u<mode>_insn (ignore_vec, operands[0],
9937 operands[1], operands[2],
9938 operands[3], operands[4],
9944 ;; [vdwdupq_m_wb_u_insn])
9946 (define_insn "mve_vdwdupq_m_wb_u<mode>_insn"
9947 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
9948 (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "w")
9949 (match_operand:SI 3 "s_register_operand" "1")
9950 (match_operand:SI 4 "s_register_operand" "r")
9951 (match_operand:SI 5 "mve_imm_selective_upto_8" "Rg")
9952 (match_operand:HI 6 "vpr_register_operand" "Up")]
9954 (set (match_operand:SI 1 "s_register_operand" "=e")
9955 (unspec:SI [(match_dup 2)
9963 "vpst\;\tvdwdupt.u%#<V_sz_elem>\t%q2, %3, %4, %5"
9964 [(set_attr "type" "mve_move")
9965 (set_attr "length""8")])
9970 (define_expand "mve_viwdupq_n_u<mode>"
9971 [(match_operand:MVE_2 0 "s_register_operand")
9972 (match_operand:SI 1 "s_register_operand")
9973 (match_operand:SI 2 "s_register_operand")
9974 (match_operand:SI 3 "mve_imm_selective_upto_8")]
9977 rtx ignore_wb = gen_reg_rtx (SImode);
9978 emit_insn (gen_mve_viwdupq_wb_u<mode>_insn (operands[0], ignore_wb,
9979 operands[1], operands[2],
9987 (define_expand "mve_viwdupq_wb_u<mode>"
9988 [(match_operand:SI 0 "s_register_operand")
9989 (match_operand:SI 1 "s_register_operand")
9990 (match_operand:SI 2 "s_register_operand")
9991 (match_operand:SI 3 "mve_imm_selective_upto_8")
9992 (unspec:MVE_2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
9995 rtx ignore_vec = gen_reg_rtx (<MODE>mode);
9996 emit_insn (gen_mve_viwdupq_wb_u<mode>_insn (ignore_vec, operands[0],
9997 operands[1], operands[2],
10003 ;; [viwdupq_wb_u_insn])
10005 (define_insn "mve_viwdupq_wb_u<mode>_insn"
10006 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
10007 (unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1")
10008 (match_operand:SI 3 "s_register_operand" "r")
10009 (match_operand:SI 4 "mve_imm_selective_upto_8" "Rg")]
10011 (set (match_operand:SI 1 "s_register_operand" "=e")
10012 (unspec:SI [(match_dup 2)
10017 "viwdup.u%#<V_sz_elem>\t%q0, %2, %3, %4"
10021 ;; [viwdupq_m_n_u])
10023 (define_expand "mve_viwdupq_m_n_u<mode>"
10024 [(match_operand:MVE_2 0 "s_register_operand")
10025 (match_operand:MVE_2 1 "s_register_operand")
10026 (match_operand:SI 2 "s_register_operand")
10027 (match_operand:SI 3 "s_register_operand")
10028 (match_operand:SI 4 "mve_imm_selective_upto_8")
10029 (match_operand:HI 5 "vpr_register_operand")]
10032 rtx ignore_wb = gen_reg_rtx (SImode);
10033 emit_insn (gen_mve_viwdupq_m_wb_u<mode>_insn (operands[0], ignore_wb,
10034 operands[1], operands[2],
10035 operands[3], operands[4],
10041 ;; [viwdupq_m_wb_u])
10043 (define_expand "mve_viwdupq_m_wb_u<mode>"
10044 [(match_operand:SI 0 "s_register_operand")
10045 (match_operand:MVE_2 1 "s_register_operand")
10046 (match_operand:SI 2 "s_register_operand")
10047 (match_operand:SI 3 "s_register_operand")
10048 (match_operand:SI 4 "mve_imm_selective_upto_8")
10049 (match_operand:HI 5 "vpr_register_operand")]
10052 rtx ignore_vec = gen_reg_rtx (<MODE>mode);
10053 emit_insn (gen_mve_viwdupq_m_wb_u<mode>_insn (ignore_vec, operands[0],
10054 operands[1], operands[2],
10055 operands[3], operands[4],
10061 ;; [viwdupq_m_wb_u_insn])
10063 (define_insn "mve_viwdupq_m_wb_u<mode>_insn"
10064 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
10065 (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "w")
10066 (match_operand:SI 3 "s_register_operand" "1")
10067 (match_operand:SI 4 "s_register_operand" "r")
10068 (match_operand:SI 5 "mve_imm_selective_upto_8" "Rg")
10069 (match_operand:HI 6 "vpr_register_operand" "Up")]
10071 (set (match_operand:SI 1 "s_register_operand" "=e")
10072 (unspec:SI [(match_dup 2)
10080 "vpst\;\tviwdupt.u%#<V_sz_elem>\t%q2, %3, %4, %5"
10081 [(set_attr "type" "mve_move")
10082 (set_attr "length""8")])
10083 (define_expand "mve_vstrwq_scatter_base_wb_<supf>v4si"
10084 [(match_operand:V4SI 0 "s_register_operand" "=w")
10085 (match_operand:SI 1 "mve_vldrd_immediate" "Ri")
10086 (match_operand:V4SI 2 "s_register_operand" "w")
10087 (unspec:V4SI [(const_int 0)] VSTRWSBWBQ)]
10090 rtx ignore_wb = gen_reg_rtx (V4SImode);
10092 gen_mve_vstrwq_scatter_base_wb_<supf>v4si_insn (ignore_wb, operands[0],
10093 operands[1], operands[2]));
10097 (define_expand "mve_vstrwq_scatter_base_wb_add_<supf>v4si"
10098 [(match_operand:V4SI 0 "s_register_operand" "=w")
10099 (match_operand:SI 1 "mve_vldrd_immediate" "Ri")
10100 (match_operand:V4SI 2 "s_register_operand" "0")
10101 (unspec:V4SI [(const_int 0)] VSTRWSBWBQ)]
10104 rtx ignore_vec = gen_reg_rtx (V4SImode);
10106 gen_mve_vstrwq_scatter_base_wb_<supf>v4si_insn (operands[0], operands[2],
10107 operands[1], ignore_vec));
10112 ;; [vstrwq_scatter_base_wb_s vstrdq_scatter_base_wb_u]
10114 (define_insn "mve_vstrwq_scatter_base_wb_<supf>v4si_insn"
10115 [(set (mem:BLK (scratch))
10117 [(match_operand:V4SI 1 "s_register_operand" "0")
10118 (match_operand:SI 2 "mve_vldrd_immediate" "Ri")
10119 (match_operand:V4SI 3 "s_register_operand" "w")]
10121 (set (match_operand:V4SI 0 "s_register_operand" "=w")
10122 (unspec:V4SI [(match_dup 1) (match_dup 2)]
10128 ops[0] = operands[1];
10129 ops[1] = operands[2];
10130 ops[2] = operands[3];
10131 output_asm_insn ("vstrw.u32\t%q2, [%q0, %1]!",ops);
10134 [(set_attr "length" "4")])
10136 (define_expand "mve_vstrwq_scatter_base_wb_p_<supf>v4si"
10137 [(match_operand:V4SI 0 "s_register_operand" "=w")
10138 (match_operand:SI 1 "mve_vldrd_immediate" "Ri")
10139 (match_operand:V4SI 2 "s_register_operand" "w")
10140 (match_operand:HI 3 "vpr_register_operand")
10141 (unspec:V4SI [(const_int 0)] VSTRWSBWBQ)]
10144 rtx ignore_wb = gen_reg_rtx (V4SImode);
10146 gen_mve_vstrwq_scatter_base_wb_p_<supf>v4si_insn (ignore_wb, operands[0],
10147 operands[1], operands[2],
10152 (define_expand "mve_vstrwq_scatter_base_wb_p_add_<supf>v4si"
10153 [(match_operand:V4SI 0 "s_register_operand" "=w")
10154 (match_operand:SI 1 "mve_vldrd_immediate" "Ri")
10155 (match_operand:V4SI 2 "s_register_operand" "0")
10156 (match_operand:HI 3 "vpr_register_operand")
10157 (unspec:V4SI [(const_int 0)] VSTRWSBWBQ)]
10160 rtx ignore_vec = gen_reg_rtx (V4SImode);
10162 gen_mve_vstrwq_scatter_base_wb_p_<supf>v4si_insn (operands[0], operands[2],
10163 operands[1], ignore_vec,
10169 ;; [vstrwq_scatter_base_wb_p_s vstrwq_scatter_base_wb_p_u]
10171 (define_insn "mve_vstrwq_scatter_base_wb_p_<supf>v4si_insn"
10172 [(set (mem:BLK (scratch))
10174 [(match_operand:V4SI 1 "s_register_operand" "0")
10175 (match_operand:SI 2 "mve_vldrd_immediate" "Ri")
10176 (match_operand:V4SI 3 "s_register_operand" "w")
10177 (match_operand:HI 4 "vpr_register_operand")]
10179 (set (match_operand:V4SI 0 "s_register_operand" "=w")
10180 (unspec:V4SI [(match_dup 1) (match_dup 2)]
10186 ops[0] = operands[1];
10187 ops[1] = operands[2];
10188 ops[2] = operands[3];
10189 output_asm_insn ("vpst\;\tvstrwt.u32\t%q2, [%q0, %1]!",ops);
10192 [(set_attr "length" "8")])
10194 (define_expand "mve_vstrwq_scatter_base_wb_fv4sf"
10195 [(match_operand:V4SI 0 "s_register_operand" "=w")
10196 (match_operand:SI 1 "mve_vldrd_immediate" "Ri")
10197 (match_operand:V4SF 2 "s_register_operand" "w")
10198 (unspec:V4SI [(const_int 0)] VSTRWQSBWB_F)]
10199 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
10201 rtx ignore_wb = gen_reg_rtx (V4SImode);
10203 gen_mve_vstrwq_scatter_base_wb_fv4sf_insn (ignore_wb,operands[0],
10204 operands[1], operands[2]));
10208 (define_expand "mve_vstrwq_scatter_base_wb_add_fv4sf"
10209 [(match_operand:V4SI 0 "s_register_operand" "=w")
10210 (match_operand:SI 1 "mve_vldrd_immediate" "Ri")
10211 (match_operand:V4SI 2 "s_register_operand" "0")
10212 (unspec:V4SI [(const_int 0)] VSTRWQSBWB_F)]
10213 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
10215 rtx ignore_vec = gen_reg_rtx (V4SFmode);
10217 gen_mve_vstrwq_scatter_base_wb_fv4sf_insn (operands[0], operands[2],
10218 operands[1], ignore_vec));
10223 ;; [vstrwq_scatter_base_wb_f]
10225 (define_insn "mve_vstrwq_scatter_base_wb_fv4sf_insn"
10226 [(set (mem:BLK (scratch))
10228 [(match_operand:V4SI 1 "s_register_operand" "0")
10229 (match_operand:SI 2 "mve_vldrd_immediate" "Ri")
10230 (match_operand:V4SF 3 "s_register_operand" "w")]
10232 (set (match_operand:V4SI 0 "s_register_operand" "=w")
10233 (unspec:V4SI [(match_dup 1) (match_dup 2)]
10236 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
10239 ops[0] = operands[1];
10240 ops[1] = operands[2];
10241 ops[2] = operands[3];
10242 output_asm_insn ("vstrw.u32\t%q2, [%q0, %1]!",ops);
10245 [(set_attr "length" "4")])
10247 (define_expand "mve_vstrwq_scatter_base_wb_p_fv4sf"
10248 [(match_operand:V4SI 0 "s_register_operand" "=w")
10249 (match_operand:SI 1 "mve_vldrd_immediate" "Ri")
10250 (match_operand:V4SF 2 "s_register_operand" "w")
10251 (match_operand:HI 3 "vpr_register_operand")
10252 (unspec:V4SI [(const_int 0)] VSTRWQSBWB_F)]
10253 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
10255 rtx ignore_wb = gen_reg_rtx (V4SImode);
10257 gen_mve_vstrwq_scatter_base_wb_p_fv4sf_insn (ignore_wb, operands[0],
10258 operands[1], operands[2],
10263 (define_expand "mve_vstrwq_scatter_base_wb_p_add_fv4sf"
10264 [(match_operand:V4SI 0 "s_register_operand" "=w")
10265 (match_operand:SI 1 "mve_vldrd_immediate" "Ri")
10266 (match_operand:V4SI 2 "s_register_operand" "0")
10267 (match_operand:HI 3 "vpr_register_operand")
10268 (unspec:V4SI [(const_int 0)] VSTRWQSBWB_F)]
10269 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
10271 rtx ignore_vec = gen_reg_rtx (V4SFmode);
10273 gen_mve_vstrwq_scatter_base_wb_p_fv4sf_insn (operands[0], operands[2],
10274 operands[1], ignore_vec,
10280 ;; [vstrwq_scatter_base_wb_p_f]
10282 (define_insn "mve_vstrwq_scatter_base_wb_p_fv4sf_insn"
10283 [(set (mem:BLK (scratch))
10285 [(match_operand:V4SI 1 "s_register_operand" "0")
10286 (match_operand:SI 2 "mve_vldrd_immediate" "Ri")
10287 (match_operand:V4SF 3 "s_register_operand" "w")
10288 (match_operand:HI 4 "vpr_register_operand")]
10290 (set (match_operand:V4SI 0 "s_register_operand" "=w")
10291 (unspec:V4SI [(match_dup 1) (match_dup 2)]
10294 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
10297 ops[0] = operands[1];
10298 ops[1] = operands[2];
10299 ops[2] = operands[3];
10300 output_asm_insn ("vpst\;\tvstrwt.u32\t%q2, [%q0, %1]!",ops);
10303 [(set_attr "length" "8")])
10305 (define_expand "mve_vstrdq_scatter_base_wb_<supf>v2di"
10306 [(match_operand:V2DI 0 "s_register_operand" "=w")
10307 (match_operand:SI 1 "mve_vldrd_immediate" "Ri")
10308 (match_operand:V2DI 2 "s_register_operand" "w")
10309 (unspec:V2DI [(const_int 0)] VSTRDSBWBQ)]
10312 rtx ignore_wb = gen_reg_rtx (V2DImode);
10314 gen_mve_vstrdq_scatter_base_wb_<supf>v2di_insn (ignore_wb, operands[0],
10315 operands[1], operands[2]));
10319 (define_expand "mve_vstrdq_scatter_base_wb_add_<supf>v2di"
10320 [(match_operand:V2DI 0 "s_register_operand" "=w")
10321 (match_operand:SI 1 "mve_vldrd_immediate" "Ri")
10322 (match_operand:V2DI 2 "s_register_operand" "0")
10323 (unspec:V2DI [(const_int 0)] VSTRDSBWBQ)]
10326 rtx ignore_vec = gen_reg_rtx (V2DImode);
10328 gen_mve_vstrdq_scatter_base_wb_<supf>v2di_insn (operands[0], operands[2],
10329 operands[1], ignore_vec));
10334 ;; [vstrdq_scatter_base_wb_s vstrdq_scatter_base_wb_u]
10336 (define_insn "mve_vstrdq_scatter_base_wb_<supf>v2di_insn"
10337 [(set (mem:BLK (scratch))
10339 [(match_operand:V2DI 1 "s_register_operand" "0")
10340 (match_operand:SI 2 "mve_vldrd_immediate" "Ri")
10341 (match_operand:V2DI 3 "s_register_operand" "w")]
10343 (set (match_operand:V2DI 0 "s_register_operand" "=&w")
10344 (unspec:V2DI [(match_dup 1) (match_dup 2)]
10350 ops[0] = operands[1];
10351 ops[1] = operands[2];
10352 ops[2] = operands[3];
10353 output_asm_insn ("vstrd.u64\t%q2, [%q0, %1]!",ops);
10356 [(set_attr "length" "4")])
10358 (define_expand "mve_vstrdq_scatter_base_wb_p_<supf>v2di"
10359 [(match_operand:V2DI 0 "s_register_operand" "=w")
10360 (match_operand:SI 1 "mve_vldrd_immediate" "Ri")
10361 (match_operand:V2DI 2 "s_register_operand" "w")
10362 (match_operand:HI 3 "vpr_register_operand")
10363 (unspec:V2DI [(const_int 0)] VSTRDSBWBQ)]
10366 rtx ignore_wb = gen_reg_rtx (V2DImode);
10368 gen_mve_vstrdq_scatter_base_wb_p_<supf>v2di_insn (ignore_wb, operands[0],
10369 operands[1], operands[2],
10374 (define_expand "mve_vstrdq_scatter_base_wb_p_add_<supf>v2di"
10375 [(match_operand:V2DI 0 "s_register_operand" "=w")
10376 (match_operand:SI 1 "mve_vldrd_immediate" "Ri")
10377 (match_operand:V2DI 2 "s_register_operand" "0")
10378 (match_operand:HI 3 "vpr_register_operand")
10379 (unspec:V2DI [(const_int 0)] VSTRDSBWBQ)]
10382 rtx ignore_vec = gen_reg_rtx (V2DImode);
10384 gen_mve_vstrdq_scatter_base_wb_p_<supf>v2di_insn (operands[0], operands[2],
10385 operands[1], ignore_vec,
10391 ;; [vstrdq_scatter_base_wb_p_s vstrdq_scatter_base_wb_p_u]
10393 (define_insn "mve_vstrdq_scatter_base_wb_p_<supf>v2di_insn"
10394 [(set (mem:BLK (scratch))
10396 [(match_operand:V2DI 1 "s_register_operand" "0")
10397 (match_operand:SI 2 "mve_vldrd_immediate" "Ri")
10398 (match_operand:V2DI 3 "s_register_operand" "w")
10399 (match_operand:HI 4 "vpr_register_operand")]
10401 (set (match_operand:V2DI 0 "s_register_operand" "=w")
10402 (unspec:V2DI [(match_dup 1) (match_dup 2)]
10408 ops[0] = operands[1];
10409 ops[1] = operands[2];
10410 ops[2] = operands[3];
10411 output_asm_insn ("vpst\;\tvstrdt.u64\t%q2, [%q0, %1]!",ops);
10414 [(set_attr "length" "8")])
10416 (define_expand "mve_vldrwq_gather_base_wb_<supf>v4si"
10417 [(match_operand:V4SI 0 "s_register_operand")
10418 (match_operand:V4SI 1 "s_register_operand")
10419 (match_operand:SI 2 "mve_vldrd_immediate")
10420 (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)]
10423 rtx ignore_result = gen_reg_rtx (V4SImode);
10425 gen_mve_vldrwq_gather_base_wb_<supf>v4si_insn (ignore_result, operands[0],
10426 operands[1], operands[2]));
10430 (define_expand "mve_vldrwq_gather_base_nowb_<supf>v4si"
10431 [(match_operand:V4SI 0 "s_register_operand")
10432 (match_operand:V4SI 1 "s_register_operand")
10433 (match_operand:SI 2 "mve_vldrd_immediate")
10434 (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)]
10437 rtx ignore_wb = gen_reg_rtx (V4SImode);
10439 gen_mve_vldrwq_gather_base_wb_<supf>v4si_insn (operands[0], ignore_wb,
10440 operands[1], operands[2]));
10445 ;; [vldrwq_gather_base_wb_s vldrwq_gather_base_wb_u]
10447 (define_insn "mve_vldrwq_gather_base_wb_<supf>v4si_insn"
10448 [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
10449 (unspec:V4SI [(match_operand:V4SI 2 "s_register_operand" "1")
10450 (match_operand:SI 3 "mve_vldrd_immediate" "Ri")
10451 (mem:BLK (scratch))]
10453 (set (match_operand:V4SI 1 "s_register_operand" "=&w")
10454 (unspec:V4SI [(match_dup 2) (match_dup 3)]
10460 ops[0] = operands[0];
10461 ops[1] = operands[2];
10462 ops[2] = operands[3];
10463 output_asm_insn ("vldrw.u32\t%q0, [%q1, %2]!",ops);
10466 [(set_attr "length" "4")])
10468 (define_expand "mve_vldrwq_gather_base_wb_z_<supf>v4si"
10469 [(match_operand:V4SI 0 "s_register_operand")
10470 (match_operand:V4SI 1 "s_register_operand")
10471 (match_operand:SI 2 "mve_vldrd_immediate")
10472 (match_operand:HI 3 "vpr_register_operand")
10473 (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)]
10476 rtx ignore_result = gen_reg_rtx (V4SImode);
10478 gen_mve_vldrwq_gather_base_wb_z_<supf>v4si_insn (ignore_result, operands[0],
10479 operands[1], operands[2],
10483 (define_expand "mve_vldrwq_gather_base_nowb_z_<supf>v4si"
10484 [(match_operand:V4SI 0 "s_register_operand")
10485 (match_operand:V4SI 1 "s_register_operand")
10486 (match_operand:SI 2 "mve_vldrd_immediate")
10487 (match_operand:HI 3 "vpr_register_operand")
10488 (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)]
10491 rtx ignore_wb = gen_reg_rtx (V4SImode);
10493 gen_mve_vldrwq_gather_base_wb_z_<supf>v4si_insn (operands[0], ignore_wb,
10494 operands[1], operands[2],
10500 ;; [vldrwq_gather_base_wb_z_s vldrwq_gather_base_wb_z_u]
10502 (define_insn "mve_vldrwq_gather_base_wb_z_<supf>v4si_insn"
10503 [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
10504 (unspec:V4SI [(match_operand:V4SI 2 "s_register_operand" "1")
10505 (match_operand:SI 3 "mve_vldrd_immediate" "Ri")
10506 (match_operand:HI 4 "vpr_register_operand" "Up")
10507 (mem:BLK (scratch))]
10509 (set (match_operand:V4SI 1 "s_register_operand" "=&w")
10510 (unspec:V4SI [(match_dup 2) (match_dup 3)]
10516 ops[0] = operands[0];
10517 ops[1] = operands[2];
10518 ops[2] = operands[3];
10519 output_asm_insn ("vpst\;vldrwt.u32\t%q0, [%q1, %2]!",ops);
10522 [(set_attr "length" "8")])
10524 (define_expand "mve_vldrwq_gather_base_wb_fv4sf"
10525 [(match_operand:V4SI 0 "s_register_operand")
10526 (match_operand:V4SI 1 "s_register_operand")
10527 (match_operand:SI 2 "mve_vldrd_immediate")
10528 (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)]
10529 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
10531 rtx ignore_result = gen_reg_rtx (V4SFmode);
10533 gen_mve_vldrwq_gather_base_wb_fv4sf_insn (ignore_result, operands[0],
10534 operands[1], operands[2]));
10538 (define_expand "mve_vldrwq_gather_base_nowb_fv4sf"
10539 [(match_operand:V4SF 0 "s_register_operand")
10540 (match_operand:V4SI 1 "s_register_operand")
10541 (match_operand:SI 2 "mve_vldrd_immediate")
10542 (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)]
10543 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
10545 rtx ignore_wb = gen_reg_rtx (V4SImode);
10547 gen_mve_vldrwq_gather_base_wb_fv4sf_insn (operands[0], ignore_wb,
10548 operands[1], operands[2]));
10553 ;; [vldrwq_gather_base_wb_f]
10555 (define_insn "mve_vldrwq_gather_base_wb_fv4sf_insn"
10556 [(set (match_operand:V4SF 0 "s_register_operand" "=&w")
10557 (unspec:V4SF [(match_operand:V4SI 2 "s_register_operand" "1")
10558 (match_operand:SI 3 "mve_vldrd_immediate" "Ri")
10559 (mem:BLK (scratch))]
10561 (set (match_operand:V4SI 1 "s_register_operand" "=&w")
10562 (unspec:V4SI [(match_dup 2) (match_dup 3)]
10565 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
10568 ops[0] = operands[0];
10569 ops[1] = operands[2];
10570 ops[2] = operands[3];
10571 output_asm_insn ("vldrw.u32\t%q0, [%q1, %2]!",ops);
10574 [(set_attr "length" "4")])
10576 (define_expand "mve_vldrwq_gather_base_wb_z_fv4sf"
10577 [(match_operand:V4SI 0 "s_register_operand")
10578 (match_operand:V4SI 1 "s_register_operand")
10579 (match_operand:SI 2 "mve_vldrd_immediate")
10580 (match_operand:HI 3 "vpr_register_operand")
10581 (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)]
10582 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
10584 rtx ignore_result = gen_reg_rtx (V4SFmode);
10586 gen_mve_vldrwq_gather_base_wb_z_fv4sf_insn (ignore_result, operands[0],
10587 operands[1], operands[2],
10592 (define_expand "mve_vldrwq_gather_base_nowb_z_fv4sf"
10593 [(match_operand:V4SF 0 "s_register_operand")
10594 (match_operand:V4SI 1 "s_register_operand")
10595 (match_operand:SI 2 "mve_vldrd_immediate")
10596 (match_operand:HI 3 "vpr_register_operand")
10597 (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)]
10598 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
10600 rtx ignore_wb = gen_reg_rtx (V4SImode);
10602 gen_mve_vldrwq_gather_base_wb_z_fv4sf_insn (operands[0], ignore_wb,
10603 operands[1], operands[2],
10609 ;; [vldrwq_gather_base_wb_z_f]
10611 (define_insn "mve_vldrwq_gather_base_wb_z_fv4sf_insn"
10612 [(set (match_operand:V4SF 0 "s_register_operand" "=&w")
10613 (unspec:V4SF [(match_operand:V4SI 2 "s_register_operand" "1")
10614 (match_operand:SI 3 "mve_vldrd_immediate" "Ri")
10615 (match_operand:HI 4 "vpr_register_operand" "Up")
10616 (mem:BLK (scratch))]
10618 (set (match_operand:V4SI 1 "s_register_operand" "=&w")
10619 (unspec:V4SI [(match_dup 2) (match_dup 3)]
10622 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
10625 ops[0] = operands[0];
10626 ops[1] = operands[2];
10627 ops[2] = operands[3];
10628 output_asm_insn ("vpst\;vldrwt.u32\t%q0, [%q1, %2]!",ops);
10631 [(set_attr "length" "8")])
10633 (define_expand "mve_vldrdq_gather_base_wb_<supf>v2di"
10634 [(match_operand:V2DI 0 "s_register_operand")
10635 (match_operand:V2DI 1 "s_register_operand")
10636 (match_operand:SI 2 "mve_vldrd_immediate")
10637 (unspec:V2DI [(const_int 0)] VLDRDGBWBQ)]
10640 rtx ignore_result = gen_reg_rtx (V2DImode);
10642 gen_mve_vldrdq_gather_base_wb_<supf>v2di_insn (ignore_result, operands[0],
10643 operands[1], operands[2]));
10647 (define_expand "mve_vldrdq_gather_base_nowb_<supf>v2di"
10648 [(match_operand:V2DI 0 "s_register_operand")
10649 (match_operand:V2DI 1 "s_register_operand")
10650 (match_operand:SI 2 "mve_vldrd_immediate")
10651 (unspec:V2DI [(const_int 0)] VLDRDGBWBQ)]
10654 rtx ignore_wb = gen_reg_rtx (V2DImode);
10656 gen_mve_vldrdq_gather_base_wb_<supf>v2di_insn (operands[0], ignore_wb,
10657 operands[1], operands[2]));
10663 ;; [vldrdq_gather_base_wb_s vldrdq_gather_base_wb_u]
10665 (define_insn "mve_vldrdq_gather_base_wb_<supf>v2di_insn"
10666 [(set (match_operand:V2DI 0 "s_register_operand" "=&w")
10667 (unspec:V2DI [(match_operand:V2DI 2 "s_register_operand" "1")
10668 (match_operand:SI 3 "mve_vldrd_immediate" "Ri")
10669 (mem:BLK (scratch))]
10671 (set (match_operand:V2DI 1 "s_register_operand" "=&w")
10672 (unspec:V2DI [(match_dup 2) (match_dup 3)]
10678 ops[0] = operands[0];
10679 ops[1] = operands[2];
10680 ops[2] = operands[3];
10681 output_asm_insn ("vldrd.64\t%q0, [%q1, %2]!",ops);
10684 [(set_attr "length" "4")])
10686 (define_expand "mve_vldrdq_gather_base_wb_z_<supf>v2di"
10687 [(match_operand:V2DI 0 "s_register_operand")
10688 (match_operand:V2DI 1 "s_register_operand")
10689 (match_operand:SI 2 "mve_vldrd_immediate")
10690 (match_operand:HI 3 "vpr_register_operand")
10691 (unspec:V2DI [(const_int 0)] VLDRDGBWBQ)]
10694 rtx ignore_result = gen_reg_rtx (V2DImode);
10696 gen_mve_vldrdq_gather_base_wb_z_<supf>v2di_insn (ignore_result, operands[0],
10697 operands[1], operands[2],
10702 (define_expand "mve_vldrdq_gather_base_nowb_z_<supf>v2di"
10703 [(match_operand:V2DI 0 "s_register_operand")
10704 (match_operand:V2DI 1 "s_register_operand")
10705 (match_operand:SI 2 "mve_vldrd_immediate")
10706 (match_operand:HI 3 "vpr_register_operand")
10707 (unspec:V2DI [(const_int 0)] VLDRDGBWBQ)]
10710 rtx ignore_wb = gen_reg_rtx (V2DImode);
10712 gen_mve_vldrdq_gather_base_wb_z_<supf>v2di_insn (operands[0], ignore_wb,
10713 operands[1], operands[2],
10718 (define_insn "get_fpscr_nzcvqc"
10719 [(set (match_operand:SI 0 "register_operand" "=r")
10720 (unspec:SI [(reg:SI VFPCC_REGNUM)] UNSPEC_GET_FPSCR_NZCVQC))]
10722 "vmrs\\t%0, FPSCR_nzcvqc"
10723 [(set_attr "type" "mve_move")])
10725 (define_insn "set_fpscr_nzcvqc"
10726 [(set (reg:SI VFPCC_REGNUM)
10727 (unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
10728 VUNSPEC_SET_FPSCR_NZCVQC))]
10730 "vmsr\\tFPSCR_nzcvqc, %0"
10731 [(set_attr "type" "mve_move")])
10734 ;; [vldrdq_gather_base_wb_z_s vldrdq_gather_base_wb_z_u]
10736 (define_insn "mve_vldrdq_gather_base_wb_z_<supf>v2di_insn"
10737 [(set (match_operand:V2DI 0 "s_register_operand" "=&w")
10738 (unspec:V2DI [(match_operand:V2DI 2 "s_register_operand" "1")
10739 (match_operand:SI 3 "mve_vldrd_immediate" "Ri")
10740 (match_operand:HI 4 "vpr_register_operand" "Up")
10741 (mem:BLK (scratch))]
10743 (set (match_operand:V2DI 1 "s_register_operand" "=&w")
10744 (unspec:V2DI [(match_dup 2) (match_dup 3)]
10750 ops[0] = operands[0];
10751 ops[1] = operands[2];
10752 ops[2] = operands[3];
10753 output_asm_insn ("vpst\;vldrdt.u64\t%q0, [%q1, %2]!",ops);
10756 [(set_attr "length" "8")])
10758 ;; [vadciq_m_s, vadciq_m_u])
10760 (define_insn "mve_vadciq_m_<supf>v4si"
10761 [(set (match_operand:V4SI 0 "s_register_operand" "=w")
10762 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "0")
10763 (match_operand:V4SI 2 "s_register_operand" "w")
10764 (match_operand:V4SI 3 "s_register_operand" "w")
10765 (match_operand:HI 4 "vpr_register_operand" "Up")]
10767 (set (reg:SI VFPCC_REGNUM)
10768 (unspec:SI [(const_int 0)]
10772 "vpst\;vadcit.i32\t%q0, %q2, %q3"
10773 [(set_attr "type" "mve_move")
10774 (set_attr "length" "8")])
10777 ;; [vadciq_u, vadciq_s])
10779 (define_insn "mve_vadciq_<supf>v4si"
10780 [(set (match_operand:V4SI 0 "s_register_operand" "=w")
10781 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
10782 (match_operand:V4SI 2 "s_register_operand" "w")]
10784 (set (reg:SI VFPCC_REGNUM)
10785 (unspec:SI [(const_int 0)]
10789 "vadci.i32\t%q0, %q1, %q2"
10790 [(set_attr "type" "mve_move")
10791 (set_attr "length" "4")])
10794 ;; [vadcq_m_s, vadcq_m_u])
10796 (define_insn "mve_vadcq_m_<supf>v4si"
10797 [(set (match_operand:V4SI 0 "s_register_operand" "=w")
10798 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "0")
10799 (match_operand:V4SI 2 "s_register_operand" "w")
10800 (match_operand:V4SI 3 "s_register_operand" "w")
10801 (match_operand:HI 4 "vpr_register_operand" "Up")]
10803 (set (reg:SI VFPCC_REGNUM)
10804 (unspec:SI [(reg:SI VFPCC_REGNUM)]
10808 "vpst\;vadct.i32\t%q0, %q2, %q3"
10809 [(set_attr "type" "mve_move")
10810 (set_attr "length" "8")])
10813 ;; [vadcq_u, vadcq_s])
10815 (define_insn "mve_vadcq_<supf>v4si"
10816 [(set (match_operand:V4SI 0 "s_register_operand" "=w")
10817 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
10818 (match_operand:V4SI 2 "s_register_operand" "w")]
10820 (set (reg:SI VFPCC_REGNUM)
10821 (unspec:SI [(reg:SI VFPCC_REGNUM)]
10825 "vadc.i32\t%q0, %q1, %q2"
10826 [(set_attr "type" "mve_move")
10827 (set_attr "length" "4")
10828 (set_attr "conds" "set")])
10831 ;; [vsbciq_m_u, vsbciq_m_s])
10833 (define_insn "mve_vsbciq_m_<supf>v4si"
10834 [(set (match_operand:V4SI 0 "s_register_operand" "=w")
10835 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
10836 (match_operand:V4SI 2 "s_register_operand" "w")
10837 (match_operand:V4SI 3 "s_register_operand" "w")
10838 (match_operand:HI 4 "vpr_register_operand" "Up")]
10840 (set (reg:SI VFPCC_REGNUM)
10841 (unspec:SI [(const_int 0)]
10845 "vpst\;vsbcit.i32\t%q0, %q2, %q3"
10846 [(set_attr "type" "mve_move")
10847 (set_attr "length" "8")])
10850 ;; [vsbciq_s, vsbciq_u])
10852 (define_insn "mve_vsbciq_<supf>v4si"
10853 [(set (match_operand:V4SI 0 "s_register_operand" "=w")
10854 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
10855 (match_operand:V4SI 2 "s_register_operand" "w")]
10857 (set (reg:SI VFPCC_REGNUM)
10858 (unspec:SI [(const_int 0)]
10862 "vsbci.i32\t%q0, %q1, %q2"
10863 [(set_attr "type" "mve_move")
10864 (set_attr "length" "4")])
10867 ;; [vsbcq_m_u, vsbcq_m_s])
10869 (define_insn "mve_vsbcq_m_<supf>v4si"
10870 [(set (match_operand:V4SI 0 "s_register_operand" "=w")
10871 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
10872 (match_operand:V4SI 2 "s_register_operand" "w")
10873 (match_operand:V4SI 3 "s_register_operand" "w")
10874 (match_operand:HI 4 "vpr_register_operand" "Up")]
10876 (set (reg:SI VFPCC_REGNUM)
10877 (unspec:SI [(reg:SI VFPCC_REGNUM)]
10881 "vpst\;vsbct.i32\t%q0, %q2, %q3"
10882 [(set_attr "type" "mve_move")
10883 (set_attr "length" "8")])
10886 ;; [vsbcq_s, vsbcq_u])
10888 (define_insn "mve_vsbcq_<supf>v4si"
10889 [(set (match_operand:V4SI 0 "s_register_operand" "=w")
10890 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
10891 (match_operand:V4SI 2 "s_register_operand" "w")]
10893 (set (reg:SI VFPCC_REGNUM)
10894 (unspec:SI [(reg:SI VFPCC_REGNUM)]
10898 "vsbc.i32\t%q0, %q1, %q2"
10899 [(set_attr "type" "mve_move")
10900 (set_attr "length" "4")])
10905 (define_insn "mve_vst2q<mode>"
10906 [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
10907 (unspec:OI [(match_operand:OI 1 "s_register_operand" "w")
10908 (unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
10911 "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode))
10912 || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))"
10915 int regno = REGNO (operands[1]);
10916 ops[0] = gen_rtx_REG (TImode, regno);
10917 ops[1] = gen_rtx_REG (TImode, regno + 4);
10918 rtx reg = operands[0];
10919 while (reg && !REG_P (reg))
10920 reg = XEXP (reg, 0);
10921 gcc_assert (REG_P (reg));
10923 ops[3] = operands[0];
10924 output_asm_insn ("vst20.<V_sz_elem>\t{%q0, %q1}, [%2]\n\t"
10925 "vst21.<V_sz_elem>\t{%q0, %q1}, %3", ops);
10928 [(set_attr "length" "8")])
10933 (define_insn "mve_vld2q<mode>"
10934 [(set (match_operand:OI 0 "s_register_operand" "=w")
10935 (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um")
10936 (unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
10939 "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode))
10940 || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))"
10943 int regno = REGNO (operands[0]);
10944 ops[0] = gen_rtx_REG (TImode, regno);
10945 ops[1] = gen_rtx_REG (TImode, regno + 4);
10946 rtx reg = operands[1];
10947 while (reg && !REG_P (reg))
10948 reg = XEXP (reg, 0);
10949 gcc_assert (REG_P (reg));
10951 ops[3] = operands[1];
10952 output_asm_insn ("vld20.<V_sz_elem>\t{%q0, %q1}, [%2]\n\t"
10953 "vld21.<V_sz_elem>\t{%q0, %q1}, %3", ops);
10956 [(set_attr "length" "8")])
10961 (define_insn "mve_vld4q<mode>"
10962 [(set (match_operand:XI 0 "s_register_operand" "=w")
10963 (unspec:XI [(match_operand:XI 1 "neon_struct_operand" "Um")
10964 (unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
10967 "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode))
10968 || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))"
10971 int regno = REGNO (operands[0]);
10972 ops[0] = gen_rtx_REG (TImode, regno);
10973 ops[1] = gen_rtx_REG (TImode, regno+4);
10974 ops[2] = gen_rtx_REG (TImode, regno+8);
10975 ops[3] = gen_rtx_REG (TImode, regno + 12);
10976 rtx reg = operands[1];
10977 while (reg && !REG_P (reg))
10978 reg = XEXP (reg, 0);
10979 gcc_assert (REG_P (reg));
10981 ops[5] = operands[1];
10982 output_asm_insn ("vld40.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t"
10983 "vld41.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t"
10984 "vld42.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t"
10985 "vld43.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, %5", ops);
10988 [(set_attr "length" "16")])
10990 ;; [vgetq_lane_u, vgetq_lane_s, vgetq_lane_f])
10992 (define_insn "mve_vec_extract<mode><V_elem_l>"
10993 [(set (match_operand:<V_elem> 0 "s_register_operand" "=r")
10994 (vec_select:<V_elem>
10995 (match_operand:MVE_VLD_ST 1 "s_register_operand" "w")
10996 (parallel [(match_operand:SI 2 "immediate_operand" "i")])))]
10997 "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode))
10998 || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))"
11000 if (BYTES_BIG_ENDIAN)
11002 int elt = INTVAL (operands[2]);
11003 elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt;
11004 operands[2] = GEN_INT (elt);
11006 return "vmov.<V_extr_elem>\t%0, %q1[%c2]";
11008 [(set_attr "type" "mve_move")])
11010 (define_insn "mve_vec_extractv2didi"
11011 [(set (match_operand:DI 0 "s_register_operand" "=r")
11013 (match_operand:V2DI 1 "s_register_operand" "w")
11014 (parallel [(match_operand:SI 2 "immediate_operand" "i")])))]
11017 int elt = INTVAL (operands[2]);
11018 if (BYTES_BIG_ENDIAN)
11022 return "vmov\t%Q0, %R0, %e1";
11024 return "vmov\t%J0, %K0, %f1";
11026 [(set_attr "type" "mve_move")])
11028 (define_insn "*mve_vec_extract_sext_internal<mode>"
11029 [(set (match_operand:SI 0 "s_register_operand" "=r")
11031 (vec_select:<V_elem>
11032 (match_operand:MVE_2 1 "s_register_operand" "w")
11033 (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))]
11034 "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode))
11035 || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))"
11037 if (BYTES_BIG_ENDIAN)
11039 int elt = INTVAL (operands[2]);
11040 elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt;
11041 operands[2] = GEN_INT (elt);
11043 return "vmov.s<V_sz_elem>\t%0, %q1[%c2]";
11045 [(set_attr "type" "mve_move")])
11047 (define_insn "*mve_vec_extract_zext_internal<mode>"
11048 [(set (match_operand:SI 0 "s_register_operand" "=r")
11050 (vec_select:<V_elem>
11051 (match_operand:MVE_2 1 "s_register_operand" "w")
11052 (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))]
11053 "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode))
11054 || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))"
11056 if (BYTES_BIG_ENDIAN)
11058 int elt = INTVAL (operands[2]);
11059 elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt;
11060 operands[2] = GEN_INT (elt);
11062 return "vmov.u<V_sz_elem>\t%0, %q1[%c2]";
11064 [(set_attr "type" "mve_move")])
11067 ;; [vsetq_lane_u, vsetq_lane_s, vsetq_lane_f])
11069 (define_insn "mve_vec_set<mode>_internal"
11070 [(set (match_operand:VQ2 0 "s_register_operand" "=w")
11073 (match_operand:<V_elem> 1 "nonimmediate_operand" "r"))
11074 (match_operand:VQ2 3 "s_register_operand" "0")
11075 (match_operand:SI 2 "immediate_operand" "i")))]
11076 "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode))
11077 || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))"
11079 int elt = ffs ((int) INTVAL (operands[2])) - 1;
11080 if (BYTES_BIG_ENDIAN)
11081 elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt;
11082 operands[2] = GEN_INT (elt);
11084 return "vmov.<V_sz_elem>\t%q0[%c2], %1";
11086 [(set_attr "type" "mve_move")])
11088 (define_insn "mve_vec_setv2di_internal"
11089 [(set (match_operand:V2DI 0 "s_register_operand" "=w")
11091 (vec_duplicate:V2DI
11092 (match_operand:DI 1 "nonimmediate_operand" "r"))
11093 (match_operand:V2DI 3 "s_register_operand" "0")
11094 (match_operand:SI 2 "immediate_operand" "i")))]
11097 int elt = ffs ((int) INTVAL (operands[2])) - 1;
11098 if (BYTES_BIG_ENDIAN)
11102 return "vmov\t%e0, %Q1, %R1";
11104 return "vmov\t%f0, %J1, %K1";
11106 [(set_attr "type" "mve_move")])
11111 (define_insn "mve_uqrshll_sat<supf>_di"
11112 [(set (match_operand:DI 0 "arm_general_register_operand" "+r")
11113 (unspec:DI [(match_operand:DI 1 "arm_general_register_operand" "r")
11114 (match_operand:SI 2 "s_register_operand" "r")]
11117 "uqrshll%?\\t%Q1, %R1, #<supf>, %2"
11118 [(set_attr "predicable" "yes")])
11123 (define_insn "mve_sqrshrl_sat<supf>_di"
11124 [(set (match_operand:DI 0 "arm_general_register_operand" "+r")
11125 (unspec:DI [(match_operand:DI 1 "arm_general_register_operand" "r")
11126 (match_operand:SI 2 "s_register_operand" "r")]
11129 "sqrshrl%?\\t%Q1, %R1, #<supf>, %2"
11130 [(set_attr "predicable" "yes")])
11135 (define_insn "mve_uqrshl_si"
11136 [(set (match_operand:SI 0 "arm_general_register_operand" "+r")
11137 (unspec:SI [(match_operand:SI 1 "arm_general_register_operand" "r")
11138 (match_operand:SI 2 "s_register_operand" "r")]
11141 "uqrshl%?\\t%1, %2"
11142 [(set_attr "predicable" "yes")])
11147 (define_insn "mve_sqrshr_si"
11148 [(set (match_operand:SI 0 "arm_general_register_operand" "+r")
11149 (unspec:SI [(match_operand:SI 1 "arm_general_register_operand" "r")
11150 (match_operand:SI 2 "s_register_operand" "r")]
11153 "sqrshr%?\\t%1, %2"
11154 [(set_attr "predicable" "yes")])
11159 (define_insn "mve_uqshll_di"
11160 [(set (match_operand:DI 0 "arm_general_register_operand" "+r")
11161 (us_ashift:DI (match_operand:DI 1 "arm_general_register_operand" "r")
11162 (match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")))]
11164 "uqshll%?\\t%Q1, %R1, %2"
11165 [(set_attr "predicable" "yes")])
11170 (define_insn "mve_urshrl_di"
11171 [(set (match_operand:DI 0 "arm_general_register_operand" "+r")
11172 (unspec:DI [(match_operand:DI 1 "arm_general_register_operand" "r")
11173 (match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")]
11176 "urshrl%?\\t%Q1, %R1, %2"
11177 [(set_attr "predicable" "yes")])
11182 (define_insn "mve_uqshl_si"
11183 [(set (match_operand:SI 0 "arm_general_register_operand" "+r")
11184 (us_ashift:SI (match_operand:SI 1 "arm_general_register_operand" "r")
11185 (match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")))]
11188 [(set_attr "predicable" "yes")])
11193 (define_insn "mve_urshr_si"
11194 [(set (match_operand:SI 0 "arm_general_register_operand" "+r")
11195 (unspec:SI [(match_operand:SI 1 "arm_general_register_operand" "r")
11196 (match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")]
11200 [(set_attr "predicable" "yes")])
11205 (define_insn "mve_sqshl_si"
11206 [(set (match_operand:SI 0 "arm_general_register_operand" "+r")
11207 (ss_ashift:SI (match_operand:DI 1 "arm_general_register_operand" "r")
11208 (match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")))]
11211 [(set_attr "predicable" "yes")])
11216 (define_insn "mve_srshr_si"
11217 [(set (match_operand:SI 0 "arm_general_register_operand" "+r")
11218 (unspec:SI [(match_operand:DI 1 "arm_general_register_operand" "r")
11219 (match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")]
11223 [(set_attr "predicable" "yes")])
11228 (define_insn "mve_srshrl_di"
11229 [(set (match_operand:DI 0 "arm_general_register_operand" "+r")
11230 (unspec:DI [(match_operand:DI 1 "arm_general_register_operand" "r")
11231 (match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")]
11234 "srshrl%?\\t%Q1, %R1, %2"
11235 [(set_attr "predicable" "yes")])
11240 (define_insn "mve_sqshll_di"
11241 [(set (match_operand:DI 0 "arm_general_register_operand" "+r")
11242 (ss_ashift:DI (match_operand:DI 1 "arm_general_register_operand" "r")
11243 (match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")))]
11245 "sqshll%?\\t%Q1, %R1, %2"
11246 [(set_attr "predicable" "yes")])
11249 ;; [vshlcq_m_u vshlcq_m_s]
11251 (define_expand "mve_vshlcq_m_vec_<supf><mode>"
11252 [(match_operand:MVE_2 0 "s_register_operand")
11253 (match_operand:MVE_2 1 "s_register_operand")
11254 (match_operand:SI 2 "s_register_operand")
11255 (match_operand:SI 3 "mve_imm_32")
11256 (match_operand:HI 4 "vpr_register_operand")
11257 (unspec:MVE_2 [(const_int 0)] VSHLCQ_M)]
11260 rtx ignore_wb = gen_reg_rtx (SImode);
11261 emit_insn (gen_mve_vshlcq_m_<supf><mode> (operands[0], ignore_wb, operands[1],
11262 operands[2], operands[3],
11267 (define_expand "mve_vshlcq_m_carry_<supf><mode>"
11268 [(match_operand:SI 0 "s_register_operand")
11269 (match_operand:MVE_2 1 "s_register_operand")
11270 (match_operand:SI 2 "s_register_operand")
11271 (match_operand:SI 3 "mve_imm_32")
11272 (match_operand:HI 4 "vpr_register_operand")
11273 (unspec:MVE_2 [(const_int 0)] VSHLCQ_M)]
11276 rtx ignore_vec = gen_reg_rtx (<MODE>mode);
11277 emit_insn (gen_mve_vshlcq_m_<supf><mode> (ignore_vec, operands[0],
11278 operands[1], operands[2],
11279 operands[3], operands[4]));
11283 (define_insn "mve_vshlcq_m_<supf><mode>"
11284 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
11285 (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0")
11286 (match_operand:SI 3 "s_register_operand" "1")
11287 (match_operand:SI 4 "mve_imm_32" "Rf")
11288 (match_operand:HI 5 "vpr_register_operand" "Up")]
11290 (set (match_operand:SI 1 "s_register_operand" "=r")
11291 (unspec:SI [(match_dup 2)
11298 "vpst\;vshlct\t%q0, %1, %4"
11299 [(set_attr "type" "mve_move")
11300 (set_attr "length" "8")])